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* config/tc-xtensa.c (find_vinsn_conflicts): Change error messages to
[deliverable/binutils-gdb.git] / opcodes / m32c-opc.c
CommitLineData
49f58d10
JB		 1/* Instruction opcode table for m32c.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996-2005 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2151 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
25#include "sysdep.h"
26#include "ansidecl.h"
27#include "bfd.h"
28#include "symcat.h"
29#include "m32c-desc.h"
30#include "m32c-opc.h"
31#include "libiberty.h"
32
33/* -- opc.c */
34static unsigned int
35m32c_asm_hash (const char *mnem)
36{
37 unsigned int h;
38
39 /* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */
40 if (mnem[0] == 'j' && mnem[1] != 's')
41 return 'j';
42
43 /* Don't hash scCND */
44 if (mnem[0] == 's' && mnem[1] == 'c')
45 return 's';
46
47 for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
48 h += *mnem;
49 return h % CGEN_ASM_HASH_SIZE;
50}
51\f
52/* -- asm.c */
53/* The hash functions are recorded here to help keep assembler code out of
54 the disassembler and vice versa. */
55
e729279b
NC		 56static int asm_hash_insn_p (const CGEN_INSN *);
57static unsigned int asm_hash_insn (const char *);
58static int dis_hash_insn_p (const CGEN_INSN *);
59static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
49f58d10
JB		 60
61/* Instruction formats. */
62
63#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
64#define F(f) & m32c_cgen_ifld_table[M32C_##f]
65#else
66#define F(f) & m32c_cgen_ifld_table[M32C_/**/f]
67#endif
68static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
69 0, 0, 0x0, { { 0 } }
70};
71
72static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
73 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
74};
75
76static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
77 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
78};
79
80static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
81 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
82};
83
84static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
85 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
86};
87
88static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
89 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
90};
91
92static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
93 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
94};
95
96static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
97 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
98};
99
100static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
101 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
102};
103
104static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
105 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
106};
107
108static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
109 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
110};
111
112static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
113 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
114};
115
116static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
117 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
118};
119
120static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
121 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
122};
123
124static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
125 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
126};
127
128static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
129 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
130};
131
132static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
133 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
134};
135
136static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
137 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
138};
139
140static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
141 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
142};
143
144static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
145 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
146};
147
148static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
149 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
150};
151
152static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
153 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
154};
155
156static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
157 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
158};
159
160static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
161 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
162};
163
164static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
165 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
166};
167
168static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
169 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
170};
171
172static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
173 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
174};
175
176static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
177 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
178};
179
180static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
181 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
182};
183
184static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
185 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
186};
187
188static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
189 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
190};
191
192static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
193 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
194};
195
196static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
197 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
198};
199
200static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
201 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
202};
203
204static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
205 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
206};
207
208static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
209 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
210};
211
212static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
213 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
214};
215
216static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
217 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
218};
219
220static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
221 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
222};
223
224static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
225 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
226};
227
228static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
229 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
230};
231
232static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
233 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
234};
235
236static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
237 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
238};
239
240static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
241 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
242};
243
244static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
245 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
246};
247
248static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
249 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
250};
251
252static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
253 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
254};
255
256static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
257 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
258};
259
260static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
261 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
262};
263
264static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
265 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
266};
267
268static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
269 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
270};
271
272static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
273 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
274};
275
276static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
277 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
278};
279
280static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
281 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
282};
283
284static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
285 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
286};
287
288static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
289 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
290};
291
292static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
293 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
294};
295
296static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
297 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
298};
299
300static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
301 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
302};
303
304static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
305 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
306};
307
308static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
309 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
310};
311
312static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
313 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
314};
315
316static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
317 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
318};
319
320static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
321 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
322};
323
324static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
325 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
326};
327
328static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
329 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
330};
331
332static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
333 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
334};
335
336static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
337 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
338};
339
340static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
341 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
342};
343
344static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
345 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
346};
347
348static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
349 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
350};
351
352static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
353 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
354};
355
356static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
357 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
358};
359
360static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
361 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
362};
363
364static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
365 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
366};
367
368static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
369 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
370};
371
372static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
373 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
374};
375
376static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
377 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
378};
379
380static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
381 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
382};
383
384static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
385 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
386};
387
388static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
389 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
390};
391
392static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
393 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
394};
395
396static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
397 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
398};
399
400static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
401 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
402};
403
404static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
405 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
406};
407
408static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
409 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
410};
411
412static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
413 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
414};
415
416static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
417 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
418};
419
420static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
421 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
422};
423
424static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
425 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
426};
427
428static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
429 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
430};
431
432static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
433 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
434};
435
436static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
437 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
438};
439
440static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
441 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
442};
443
444static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
445 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
446};
447
448static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
449 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
450};
451
452static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
453 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
454};
455
456static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
457 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
458};
459
460static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
461 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
462};
463
464static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
465 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
466};
467
468static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
469 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
470};
471
472static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
473 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
474};
475
476static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
477 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
478};
479
480static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
481 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
482};
483
484static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
485 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
486};
487
488static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
489 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
490};
491
492static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
493 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
494};
495
496static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
497 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
498};
499
500static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
501 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
502};
503
504static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
505 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
506};
507
508static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
509 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
510};
511
512static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
513 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
514};
515
516static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
517 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
518};
519
520static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
521 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
522};
523
524static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
525 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
526};
527
528static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
529 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
530};
531
532static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
533 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
534};
535
536static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
537 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
538};
539
540static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
541 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
542};
543
544static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
545 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
546};
547
548static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
549 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
550};
551
552static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
553 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
554};
555
556static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
557 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
558};
559
560static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
561 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
562};
563
564static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
565 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
566};
567
568static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
569 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
570};
571
572static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
573 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
574};
575
576static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
577 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
578};
579
580static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
581 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
582};
583
584static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
585 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
586};
587
588static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
589 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
590};
591
592static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
593 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
594};
595
596static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
597 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
598};
599
600static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
601 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
602};
603
604static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
605 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
606};
607
608static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
609 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
610};
611
612static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
613 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
614};
615
616static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
617 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
618};
619
620static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
621 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
622};
623
624static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
625 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
626};
627
628static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
629 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
630};
631
632static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
633 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
634};
635
636static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
637 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
638};
639
640static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
641 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
642};
643
644static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
645 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
646};
647
648static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
649 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
650};
651
652static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
653 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
654};
655
656static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
657 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
658};
659
660static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
661 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
662};
663
664static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
665 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
666};
667
668static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
669 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
670};
671
672static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
673 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
674};
675
676static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
677 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
678};
679
680static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
681 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
682};
683
684static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
685 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
686};
687
688static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
689 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
690};
691
692static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
693 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
694};
695
696static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI ATTRIBUTE_UNUSED = {
697 16, 16, 0xfffd, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN_EXT) }, { F (F_15_1) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
698};
699
700static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI ATTRIBUTE_UNUSED = {
701 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
702};
703
704static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI ATTRIBUTE_UNUSED = {
705 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
706};
707
708static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI ATTRIBUTE_UNUSED = {
709 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
710};
711
712static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI ATTRIBUTE_UNUSED = {
713 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
714};
715
716static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI ATTRIBUTE_UNUSED = {
717 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
718};
719
720static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI ATTRIBUTE_UNUSED = {
721 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
722};
723
724static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI ATTRIBUTE_UNUSED = {
725 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
726};
727
728static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
729 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
730};
731
732static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
733 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
734};
735
736static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
737 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
738};
739
740static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
741 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
742};
743
744static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
745 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
746};
747
748static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
749 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
750};
751
752static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
753 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
754};
755
756static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
757 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
758};
759
760static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
761 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
762};
763
764static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
765 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
766};
767
768static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
769 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
770};
771
772static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
773 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
774};
775
776static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
777 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
778};
779
780static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
781 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
782};
783
784static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
785 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
786};
787
788static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
789 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
790};
791
792static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
793 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
794};
795
796static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
797 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
798};
799
800static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
801 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
802};
803
804static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
805 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
806};
807
808static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
809 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
810};
811
812static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
813 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
814};
815
816static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
817 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
818};
819
820static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
821 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
822};
823
824static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
825 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
826};
827
828static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
829 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
830};
831
832static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
833 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
834};
835
836static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
837 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
838};
839
840static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
841 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
842};
843
844static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
845 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
846};
847
848static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
849 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
850};
851
852static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
853 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
854};
855
856static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
857 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
858};
859
860static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
861 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
862};
863
864static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
865 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
866};
867
868static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
869 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
870};
871
872static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
873 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
874};
875
876static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
877 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
878};
879
880static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
881 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
882};
883
884static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
885 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
886};
887
888static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
889 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
890};
891
892static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
893 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
894};
895
896static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
897 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
898};
899
900static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
901 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
902};
903
904static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
905 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
906};
907
908static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
909 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
910};
911
912static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
913 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
914};
915
916static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
917 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
918};
919
920static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
921 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
922};
923
924static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
925 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
926};
927
928static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
929 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
930};
931
932static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
933 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
934};
935
936static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
937 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
938};
939
940static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
941 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
942};
943
944static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
945 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
946};
947
948static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
949 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
950};
951
952static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
953 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
954};
955
956static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
957 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
958};
959
960static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
961 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
962};
963
964static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
965 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
966};
967
968static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
969 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
970};
971
972static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
973 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
974};
975
976static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
977 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
978};
979
980static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
981 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
982};
983
984static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
985 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
986};
987
988static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
989 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
990};
991
992static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
993 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
994};
995
996static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
997 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
998};
999
1000static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1001 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1002};
1003
1004static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1005 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1006};
1007
1008static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1009 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1010};
1011
1012static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1013 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1014};
1015
1016static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1017 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1018};
1019
1020static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1021 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1022};
1023
1024static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1025 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1026};
1027
1028static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1029 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1030};
1031
1032static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1033 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1034};
1035
1036static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1037 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1038};
1039
1040static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1041 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1042};
1043
1044static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1045 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1046};
1047
1048static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1049 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1050};
1051
1052static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1053 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1054};
1055
1056static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1057 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1058};
1059
1060static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1061 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1062};
1063
1064static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1065 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1066};
1067
1068static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1069 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1070};
1071
1072static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1073 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1074};
1075
1076static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1077 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1078};
1079
1080static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1081 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1082};
1083
1084static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1085 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1086};
1087
1088static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1089 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1090};
1091
1092static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1093 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1094};
1095
1096static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1097 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1098};
1099
1100static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1101 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1102};
1103
1104static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1105 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1106};
1107
1108static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1109 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1110};
1111
1112static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1113 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1114};
1115
1116static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1117 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1118};
1119
1120static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1121 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1122};
1123
1124static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1125 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1126};
1127
1128static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1129 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1130};
1131
1132static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1133 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1134};
1135
1136static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1137 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1138};
1139
1140static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1141 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1142};
1143
1144static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1145 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1146};
1147
1148static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1149 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1150};
1151
1152static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1153 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1154};
1155
1156static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1157 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1158};
1159
1160static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1161 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1162};
1163
1164static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1165 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1166};
1167
1168static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1169 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1170};
1171
1172static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1173 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1174};
1175
1176static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1177 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1178};
1179
1180static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1181 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1182};
1183
1184static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1185 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1186};
1187
1188static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1189 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1190};
1191
1192static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1193 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1194};
1195
1196static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1197 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1198};
1199
1200static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1201 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1202};
1203
1204static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1205 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1206};
1207
1208static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1209 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1210};
1211
1212static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1213 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1214};
1215
1216static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1217 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1218};
1219
1220static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1221 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1222};
1223
1224static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1225 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1226};
1227
1228static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1229 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1230};
1231
1232static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1233 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1234};
1235
1236static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1237 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1238};
1239
1240static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1241 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1242};
1243
1244static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1245 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1246};
1247
1248static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1249 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1250};
1251
1252static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1253 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1254};
1255
1256static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1257 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1258};
1259
1260static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1261 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1262};
1263
1264static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1265 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1266};
1267
1268static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1269 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1270};
1271
1272static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1273 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1274};
1275
1276static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1277 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1278};
1279
1280static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1281 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1282};
1283
1284static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1285 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1286};
1287
1288static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1289 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1290};
1291
1292static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1293 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1294};
1295
1296static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1297 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1298};
1299
1300static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1301 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1302};
1303
1304static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1305 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1306};
1307
1308static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1309 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1310};
1311
1312static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1313 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1314};
1315
1316static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1317 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1318};
1319
1320static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1321 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1322};
1323
1324static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1325 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1326};
1327
1328static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1329 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1330};
1331
1332static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1333 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1334};
1335
1336static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1337 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1338};
1339
1340static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1341 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1342};
1343
1344static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1345 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1346};
1347
1348static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1349 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1350};
1351
1352static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1353 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1354};
1355
1356static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1357 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1358};
1359
1360static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1361 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1362};
1363
1364static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1365 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1366};
1367
1368static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1369 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1370};
1371
1372static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1373 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1374};
1375
1376static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1377 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1378};
1379
1380static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1381 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1382};
1383
1384static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1385 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1386};
1387
1388static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1389 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1390};
1391
1392static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1393 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1394};
1395
1396static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1397 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1398};
1399
1400static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1401 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1402};
1403
1404static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1405 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1406};
1407
1408static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1409 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1410};
1411
1412static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1413 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1414};
1415
1416static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1417 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1418};
1419
1420static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1421 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1422};
1423
1424static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1425 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1426};
1427
1428static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1429 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1430};
1431
1432static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1433 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1434};
1435
1436static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1437 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1438};
1439
1440static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1441 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1442};
1443
1444static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1445 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1446};
1447
1448static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1449 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1450};
1451
1452static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1453 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1454};
1455
1456static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1457 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1458};
1459
1460static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1461 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1462};
1463
1464static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1465 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1466};
1467
1468static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1469 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1470};
1471
1472static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1473 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1474};
1475
1476static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1477 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1478};
1479
1480static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1481 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1482};
1483
1484static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1485 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1486};
1487
1488static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1489 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1490};
1491
1492static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1493 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1494};
1495
1496static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1497 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1498};
1499
1500static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1501 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1502};
1503
1504static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1505 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1506};
1507
1508static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1509 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1510};
1511
1512static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1513 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1514};
1515
1516static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1517 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1518};
1519
1520static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1521 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1522};
1523
1524static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1525 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1526};
1527
1528static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1529 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1530};
1531
1532static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1533 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1534};
1535
1536static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1537 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1538};
1539
1540static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1541 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1542};
1543
1544static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1545 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1546};
1547
1548static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1549 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1550};
1551
1552static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1553 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1554};
1555
1556static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1557 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1558};
1559
1560static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1561 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1562};
1563
1564static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1565 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1566};
1567
1568static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1569 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1570};
1571
1572static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1573 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1574};
1575
1576static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1577 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1578};
1579
1580static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1581 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1582};
1583
1584static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1585 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1586};
1587
1588static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1589 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1590};
1591
1592static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1593 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1594};
1595
1596static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1597 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1598};
1599
1600static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1601 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1602};
1603
1604static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1605 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1606};
1607
1608static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1609 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1610};
1611
1612static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1613 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1614};
1615
1616static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1617 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1618};
1619
1620static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1621 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1622};
1623
1624static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1625 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1626};
1627
1628static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1629 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1630};
1631
1632static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1633 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1634};
1635
1636static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1637 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1638};
1639
1640static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1641 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1642};
1643
1644static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1645 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1646};
1647
1648static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1649 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1650};
1651
1652static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1653 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1654};
1655
1656static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1657 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1658};
1659
1660static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1661 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1662};
1663
1664static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1665 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1666};
1667
1668static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1669 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1670};
1671
1672static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1673 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1674};
1675
1676static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1677 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1678};
1679
1680static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1681 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1682};
1683
1684static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1685 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1686};
1687
1688static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1689 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1690};
1691
1692static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1693 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1694};
1695
1696static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1697 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1698};
1699
1700static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1701 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1702};
1703
1704static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1705 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1706};
1707
1708static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1709 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1710};
1711
1712static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1713 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1714};
1715
1716static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1717 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1718};
1719
1720static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1721 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1722};
1723
1724static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1725 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1726};
1727
1728static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1729 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1730};
1731
1732static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1733 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1734};
1735
1736static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1737 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1738};
1739
1740static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1741 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1742};
1743
1744static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1745 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1746};
1747
1748static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1749 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1750};
1751
1752static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1753 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1754};
1755
1756static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1757 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1758};
1759
1760static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1761 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1762};
1763
1764static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1765 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1766};
1767
1768static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1769 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1770};
1771
1772static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1773 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1774};
1775
1776static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1777 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1778};
1779
1780static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1781 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1782};
1783
1784static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1785 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1786};
1787
1788static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1789 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1790};
1791
1792static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1793 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1794};
1795
1796static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1797 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1798};
1799
1800static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1801 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1802};
1803
1804static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1805 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1806};
1807
1808static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1809 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1810};
1811
1812static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1813 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1814};
1815
1816static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1817 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1818};
1819
1820static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1821 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1822};
1823
1824static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1825 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1826};
1827
1828static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1829 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1830};
1831
1832static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1833 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1834};
1835
1836static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1837 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1838};
1839
1840static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1841 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1842};
1843
1844static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1845 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1846};
1847
1848static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1849 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1850};
1851
1852static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1853 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1854};
1855
1856static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1857 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1858};
1859
1860static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1861 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1862};
1863
1864static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1865 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1866};
1867
1868static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1869 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1870};
1871
1872static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1873 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1874};
1875
1876static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1877 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1878};
1879
1880static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1881 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1882};
1883
1884static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1885 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1886};
1887
1888static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1889 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1890};
1891
1892static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1893 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1894};
1895
1896static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1897 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1898};
1899
1900static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1901 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1902};
1903
1904static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1905 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1906};
1907
1908static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1909 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1910};
1911
1912static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1913 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1914};
1915
1916static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1917 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1918};
1919
1920static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1921 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1922};
1923
1924static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1925 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1926};
1927
1928static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1929 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1930};
1931
1932static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1933 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1934};
1935
1936static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1937 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1938};
1939
1940static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1941 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1942};
1943
1944static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1945 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1946};
1947
1948static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1949 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1950};
1951
1952static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1953 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1954};
1955
1956static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1957 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1958};
1959
1960static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1961 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1962};
1963
1964static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1965 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1966};
1967
1968static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1969 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1970};
1971
1972static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1973 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1974};
1975
1976static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1977 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1978};
1979
1980static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1981 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1982};
1983
1984static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1985 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1986};
1987
1988static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1989 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1990};
1991
1992static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1993 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1994};
1995
1996static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1997 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1998};
1999
2000static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2001 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2002};
2003
2004static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2005 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2006};
2007
2008static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2009 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2010};
2011
2012static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2013 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2014};
2015
2016static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2017 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2018};
2019
2020static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2021 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2022};
2023
2024static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2025 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2026};
2027
2028static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2029 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2030};
2031
2032static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2033 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2034};
2035
2036static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2037 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2038};
2039
2040static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2041 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2042};
2043
2044static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2045 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2046};
2047
2048static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2049 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2050};
2051
2052static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2053 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2054};
2055
2056static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2057 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2058};
2059
2060static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2061 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2062};
2063
2064static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2065 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2066};
2067
2068static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2069 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2070};
2071
2072static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2073 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2074};
2075
2076static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2077 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2078};
2079
2080static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2081 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2082};
2083
2084static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2085 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2086};
2087
2088static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2089 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2090};
2091
2092static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2093 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2094};
2095
2096static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2097 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2098};
2099
2100static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2101 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2102};
2103
2104static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2105 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2106};
2107
2108static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2109 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2110};
2111
2112static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2113 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2114};
2115
2116static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2117 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2118};
2119
2120static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2121 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2122};
2123
2124static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2125 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2126};
2127
2128static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2129 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2130};
2131
2132static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2133 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2134};
2135
2136static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2137 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2138};
2139
2140static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2141 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2142};
2143
2144static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2145 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2146};
2147
2148static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2149 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2150};
2151
2152static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2153 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2154};
2155
2156static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2157 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2158};
2159
2160static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2161 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2162};
2163
2164static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2165 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2166};
2167
2168static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2169 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2170};
2171
2172static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2173 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2174};
2175
2176static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2177 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2178};
2179
2180static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2181 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2182};
2183
2184static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2185 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2186};
2187
2188static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2189 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2190};
2191
2192static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2193 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2194};
2195
2196static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2197 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2198};
2199
2200static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2201 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2202};
2203
2204static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2205 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2206};
2207
2208static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2209 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2210};
2211
2212static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2213 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2214};
2215
2216static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2217 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2218};
2219
2220static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2221 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2222};
2223
2224static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2225 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2226};
2227
2228static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2229 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2230};
2231
2232static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2233 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2234};
2235
2236static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2237 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2238};
2239
2240static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2241 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2242};
2243
2244static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2245 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2246};
2247
2248static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2249 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2250};
2251
2252static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2253 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2254};
2255
2256static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2257 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2258};
2259
2260static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2261 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2262};
2263
2264static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2265 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2266};
2267
2268static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2269 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2270};
2271
2272static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2273 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2274};
2275
2276static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2277 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2278};
2279
2280static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2281 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2282};
2283
2284static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2285 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2286};
2287
2288static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2289 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2290};
2291
2292static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2293 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2294};
2295
2296static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2297 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2298};
2299
2300static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2301 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2302};
2303
2304static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2305 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2306};
2307
2308static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2309 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2310};
2311
2312static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2313 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2314};
2315
2316static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2317 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2318};
2319
2320static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2321 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2322};
2323
2324static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2325 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2326};
2327
2328static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2329 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2330};
2331
2332static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2333 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2334};
2335
2336static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2337 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2338};
2339
2340static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2341 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2342};
2343
2344static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2345 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2346};
2347
2348static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2349 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2350};
2351
2352static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2353 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2354};
2355
2356static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2357 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2358};
2359
2360static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2361 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2362};
2363
2364static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2365 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2366};
2367
2368static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2369 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2370};
2371
2372static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2373 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2374};
2375
2376static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2377 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2378};
2379
2380static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2381 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2382};
2383
2384static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2385 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2386};
2387
2388static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2389 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2390};
2391
2392static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2393 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2394};
2395
2396static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2397 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2398};
2399
2400static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2401 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2402};
2403
2404static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2405 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2406};
2407
2408static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2409 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2410};
2411
2412static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2413 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2414};
2415
2416static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2417 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2418};
2419
2420static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2421 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2422};
2423
2424static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2425 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2426};
2427
2428static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2429 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2430};
2431
2432static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2433 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2434};
2435
2436static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2437 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2438};
2439
2440static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2441 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2442};
2443
2444static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2445 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2446};
2447
2448static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2449 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2450};
2451
2452static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2453 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2454};
2455
2456static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2457 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2458};
2459
2460static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2461 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2462};
2463
2464static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2465 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2466};
2467
2468static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2469 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2470};
2471
2472static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2473 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2474};
2475
2476static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2477 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2478};
2479
2480static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2481 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2482};
2483
2484static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2485 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2486};
2487
2488static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2489 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2490};
2491
2492static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2493 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2494};
2495
2496static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2497 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2498};
2499
2500static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2501 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2502};
2503
2504static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2505 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2506};
2507
2508static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2509 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2510};
2511
2512static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2513 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2514};
2515
2516static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2517 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2518};
2519
2520static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2521 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2522};
2523
2524static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2525 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2526};
2527
2528static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2529 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2530};
2531
2532static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2533 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2534};
2535
2536static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
2537 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2538};
2539
2540static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2541 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2542};
2543
2544static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2545 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2546};
2547
2548static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2549 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2550};
2551
2552static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2553 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2554};
2555
2556static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2557 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2558};
2559
2560static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2561 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2562};
2563
2564static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2565 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2566};
2567
2568static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2569 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2570};
2571
2572static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2573 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2574};
2575
2576static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2577 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2578};
2579
2580static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2581 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2582};
2583
2584static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
2585 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2586};
2587
2588static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2589 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2590};
2591
2592static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2593 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2594};
2595
2596static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2597 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2598};
2599
2600static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2601 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2602};
2603
2604static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2605 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2606};
2607
2608static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2609 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2610};
2611
2612static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2613 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2614};
2615
2616static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2617 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2618};
2619
2620static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2621 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2622};
2623
2624static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2625 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2626};
2627
2628static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2629 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2630};
2631
2632static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2633 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2634};
2635
2636static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2637 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2638};
2639
2640static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2641 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2642};
2643
2644static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2645 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2646};
2647
2648static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2649 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2650};
2651
2652static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2653 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2654};
2655
2656static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2657 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2658};
2659
2660static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2661 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2662};
2663
2664static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2665 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2666};
2667
2668static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2669 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2670};
2671
2672static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2673 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2674};
2675
2676static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2677 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2678};
2679
2680static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2681 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2682};
2683
2684static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2685 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2686};
2687
2688static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2689 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2690};
2691
2692static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2693 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2694};
2695
2696static const CGEN_IFMT ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2697 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2698};
2699
2700static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2701 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2702};
2703
2704static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
2705 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2706};
2707
2708static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2709 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2710};
2711
2712static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2713 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2714};
2715
2716static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2717 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2718};
2719
2720static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2721 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2722};
2723
2724static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2725 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2726};
2727
2728static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2729 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2730};
2731
2732static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2733 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2734};
2735
2736static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2737 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2738};
2739
2740static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2741 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2742};
2743
2744static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2745 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2746};
2747
2748static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2749 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2750};
2751
2752static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
2753 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2754};
2755
2756static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2757 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2758};
2759
2760static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2761 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2762};
2763
2764static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2765 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2766};
2767
2768static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2769 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2770};
2771
2772static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2773 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2774};
2775
2776static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2777 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2778};
2779
2780static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2781 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2782};
2783
2784static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2785 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2786};
2787
2788static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2789 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2790};
2791
2792static const CGEN_IFMT ifmt_xchg16w_r3_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2793 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2794};
2795
2796static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2797 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2798};
2799
2800static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2801 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2802};
2803
2804static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2805 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2806};
2807
2808static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2809 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2810};
2811
2812static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2813 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2814};
2815
2816static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2817 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2818};
2819
2820static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2821 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2822};
2823
2824static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2825 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2826};
2827
a1a280bb 2828static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2829 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2830};
2831
a1a280bb 2832static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2833 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2834};
2835
a1a280bb 2836static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2837 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2838};
2839
a1a280bb 2840static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2841 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2842};
2843
a1a280bb 2844static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2845 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2846};
2847
a1a280bb 2848static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2849 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2850};
2851
a1a280bb 2852static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2853 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2854};
2855
a1a280bb 2856static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2857 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2858};
2859
a1a280bb 2860static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2861 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2862};
2863
2864static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2865 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } }
2866};
2867
2868static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2869 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } }
2870};
2871
2872static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
2873 32, 40, 0xff000000, { { F (F_0_2) }, { F (F_DSP_24_S16) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2874};
2875
2876static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
2877 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S16) }, { 0 } }
2878};
2879
2880static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2881 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } }
2882};
2883
2884static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2885 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } }
2886};
2887
2888static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
2889 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_24_S8) }, { 0 } }
2890};
2891
2892static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
2893 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S8) }, { 0 } }
2894};
2895
2896static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2897 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2898};
2899
2900static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2901 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2902};
2903
2904static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2905 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2906};
2907
2908static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2909 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2910};
2911
2912static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2913 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2914};
2915
2916static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2917 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2918};
2919
2920static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2921 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2922};
2923
2924static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2925 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2926};
2927
2928static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2929 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2930};
2931
2932static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2933 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2934};
2935
2936static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2937 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2938};
2939
2940static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2941 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2942};
2943
2944static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2945 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2946};
2947
2948static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2949 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2950};
2951
2952static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2953 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2954};
2955
2956static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2957 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2958};
2959
2960static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2961 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2962};
2963
2964static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2965 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2966};
2967
2968static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2969 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2970};
2971
2972static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2973 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2974};
2975
2976static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2977 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2978};
2979
2980static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2981 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2982};
2983
2984static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2985 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2986};
2987
2988static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2989 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2990};
2991
2992static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2993 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2994};
2995
2996static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2997 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2998};
2999
3000static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3001 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3002};
3003
3004static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3005 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3006};
3007
3008static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3009 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3010};
3011
3012static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3013 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3014};
3015
3016static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3017 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3018};
3019
3020static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3021 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3022};
3023
3024static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3025 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3026};
3027
3028static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3029 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3030};
3031
3032static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3033 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3034};
3035
3036static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3037 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3038};
3039
3040static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3041 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3042};
3043
3044static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3045 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3046};
3047
3048static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3049 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3050};
3051
3052static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3053 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3054};
3055
3056static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3057 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3058};
3059
3060static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3061 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3062};
3063
3064static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3065 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3066};
3067
3068static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3069 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3070};
3071
3072static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3073 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3074};
3075
3076static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3077 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3078};
3079
3080static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3081 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3082};
3083
3084static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3085 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3086};
3087
3088static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3089 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3090};
3091
3092static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3093 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3094};
3095
3096static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3097 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3098};
3099
3100static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3101 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3102};
3103
3104static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3105 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3106};
3107
3108static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3109 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3110};
3111
3112static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3113 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3114};
3115
3116static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3117 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3118};
3119
3120static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3121 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3122};
3123
3124static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3125 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3126};
3127
3128static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3129 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3130};
3131
3132static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3133 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3134};
3135
3136static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3137 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3138};
3139
3140static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3141 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3142};
3143
3144static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3145 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3146};
3147
3148static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3149 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3150};
3151
3152static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3153 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3154};
3155
3156static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3157 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3158};
3159
3160static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3161 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3162};
3163
3164static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3165 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3166};
3167
3168static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3169 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3170};
3171
3172static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3173 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3174};
3175
3176static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3177 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3178};
3179
3180static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3181 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3182};
3183
3184static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3185 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3186};
3187
3188static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3189 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3190};
3191
3192static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3193 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3194};
3195
3196static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3197 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3198};
3199
3200static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3201 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3202};
3203
3204static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3205 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3206};
3207
3208static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3209 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3210};
3211
3212static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3213 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3214};
3215
3216static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3217 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3218};
3219
3220static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3221 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3222};
3223
3224static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3225 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3226};
3227
3228static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3229 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3230};
3231
3232static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3233 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3234};
3235
3236static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3237 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3238};
3239
3240static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3241 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3242};
3243
3244static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3245 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3246};
3247
3248static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3249 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3250};
3251
3252static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3253 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3254};
3255
3256static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3257 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3258};
3259
3260static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3261 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3262};
3263
3264static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3265 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3266};
3267
3268static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3269 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3270};
3271
3272static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3273 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3274};
3275
3276static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3277 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3278};
3279
3280static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3281 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3282};
3283
3284static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3285 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3286};
3287
3288static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3289 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3290};
3291
3292static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3293 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3294};
3295
3296static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3297 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3298};
3299
3300static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3301 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3302};
3303
3304static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3305 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3306};
3307
3308static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3309 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3310};
3311
3312static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3313 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3314};
3315
3316static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3317 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3318};
3319
3320static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3321 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3322};
3323
3324static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3325 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3326};
3327
3328static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3329 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3330};
3331
3332static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3333 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3334};
3335
3336static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3337 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3338};
3339
3340static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3341 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3342};
3343
3344static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3345 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3346};
3347
3348static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3349 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3350};
3351
3352static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3353 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3354};
3355
3356static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3357 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3358};
3359
3360static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3361 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3362};
3363
3364static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3365 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3366};
3367
3368static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3369 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3370};
3371
3372static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3373 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3374};
3375
3376static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3377 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3378};
3379
3380static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3381 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3382};
3383
3384static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3385 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3386};
3387
3388static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3389 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3390};
3391
3392static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3393 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3394};
3395
3396static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3397 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3398};
3399
3400static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3401 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3402};
3403
3404static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3405 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3406};
3407
3408static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3409 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3410};
3411
3412static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3413 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3414};
3415
3416static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3417 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3418};
3419
3420static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3421 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3422};
3423
3424static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3425 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3426};
3427
3428static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3429 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3430};
3431
3432static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3433 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3434};
3435
3436static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3437 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3438};
3439
3440static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3441 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3442};
3443
3444static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3445 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3446};
3447
3448static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3449 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3450};
3451
3452static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3453 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3454};
3455
3456static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3457 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3458};
3459
3460static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3461 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3462};
3463
3464static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3465 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3466};
3467
3468static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3469 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3470};
3471
3472static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3473 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3474};
3475
3476static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3477 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3478};
3479
3480static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3481 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3482};
3483
3484static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3485 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3486};
3487
3488static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3489 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3490};
3491
3492static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3493 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3494};
3495
3496static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3497 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3498};
3499
3500static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3501 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3502};
3503
3504static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3505 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3506};
3507
3508static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3509 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3510};
3511
3512static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3513 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3514};
3515
3516static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3517 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3518};
3519
3520static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3521 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3522};
3523
3524static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3525 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3526};
3527
3528static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3529 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3530};
3531
3532static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3533 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3534};
3535
3536static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3537 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3538};
3539
3540static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3541 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3542};
3543
3544static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3545 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3546};
3547
3548static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3549 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3550};
3551
3552static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3553 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3554};
3555
3556static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3557 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3558};
3559
3560static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3561 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3562};
3563
3564static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3565 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3566};
3567
3568static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3569 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3570};
3571
3572static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3573 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3574};
3575
3576static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3577 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3578};
3579
3580static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3581 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3582};
3583
3584static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3585 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3586};
3587
3588static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3589 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3590};
3591
3592static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3593 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3594};
3595
3596static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3597 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3598};
3599
3600static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3601 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3602};
3603
3604static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3605 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3606};
3607
3608static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3609 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3610};
3611
3612static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3613 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3614};
3615
3616static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3617 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3618};
3619
3620static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3621 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3622};
3623
3624static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3625 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3626};
3627
3628static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3629 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3630};
3631
3632static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3633 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3634};
3635
3636static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3637 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3638};
3639
3640static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3641 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3642};
3643
3644static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3645 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3646};
3647
3648static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3649 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3650};
3651
3652static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3653 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3654};
3655
3656static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3657 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3658};
3659
3660static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3661 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3662};
3663
3664static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3665 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3666};
3667
3668static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3669 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3670};
3671
3672static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3673 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3674};
3675
3676static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3677 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3678};
3679
3680static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3681 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3682};
3683
3684static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3685 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3686};
3687
3688static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3689 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3690};
3691
3692static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3693 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3694};
3695
3696static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3697 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3698};
3699
3700static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3701 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3702};
3703
3704static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3705 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3706};
3707
3708static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3709 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3710};
3711
3712static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3713 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3714};
3715
3716static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3717 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3718};
3719
3720static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3721 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3722};
3723
3724static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3725 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3726};
3727
3728static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3729 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3730};
3731
3732static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3733 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3734};
3735
3736static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3737 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3738};
3739
3740static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3741 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3742};
3743
3744static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3745 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3746};
3747
3748static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3749 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3750};
3751
3752static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3753 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3754};
3755
3756static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3757 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3758};
3759
3760static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3761 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3762};
3763
3764static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3765 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3766};
3767
3768static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3769 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3770};
3771
3772static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3773 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3774};
3775
3776static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3777 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3778};
3779
3780static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3781 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3782};
3783
3784static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3785 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3786};
3787
3788static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3789 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3790};
3791
3792static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3793 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3794};
3795
3796static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3797 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3798};
3799
3800static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3801 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3802};
3803
3804static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3805 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3806};
3807
3808static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3809 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3810};
3811
3812static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3813 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3814};
3815
3816static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3817 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3818};
3819
3820static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3821 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3822};
3823
3824static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3825 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3826};
3827
3828static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3829 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3830};
3831
3832static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3833 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3834};
3835
3836static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3837 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3838};
3839
3840static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3841 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3842};
3843
3844static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3845 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3846};
3847
3848static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3849 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3850};
3851
3852static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3853 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3854};
3855
3856static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3857 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3858};
3859
3860static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3861 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3862};
3863
3864static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3865 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3866};
3867
3868static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3869 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3870};
3871
3872static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3873 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3874};
3875
3876static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3877 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3878};
3879
3880static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3881 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3882};
3883
3884static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3885 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3886};
3887
3888static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3889 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3890};
3891
3892static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3893 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3894};
3895
3896static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3897 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3898};
3899
3900static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3901 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3902};
3903
3904static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3905 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3906};
3907
3908static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3909 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3910};
3911
3912static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3913 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3914};
3915
3916static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3917 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3918};
3919
3920static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3921 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3922};
3923
3924static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3925 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3926};
3927
3928static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3929 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3930};
3931
3932static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3933 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3934};
3935
3936static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3937 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3938};
3939
3940static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3941 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3942};
3943
3944static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3945 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3946};
3947
3948static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3949 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3950};
3951
3952static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3953 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3954};
3955
3956static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3957 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3958};
3959
3960static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3961 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3962};
3963
3964static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3965 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3966};
3967
3968static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3969 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3970};
3971
3972static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3973 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3974};
3975
3976static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3977 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3978};
3979
3980static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3981 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3982};
3983
3984static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3985 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3986};
3987
3988static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3989 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3990};
3991
3992static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3993 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3994};
3995
3996static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3997 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3998};
3999
4000static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4001 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4002};
4003
4004static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4005 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4006};
4007
4008static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4009 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4010};
4011
4012static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4013 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4014};
4015
4016static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4017 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4018};
4019
4020static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4021 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4022};
4023
4024static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4025 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4026};
4027
4028static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4029 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4030};
4031
4032static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4033 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4034};
4035
4036static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4037 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4038};
4039
4040static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4041 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4042};
4043
4044static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4045 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4046};
4047
4048static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4049 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4050};
4051
4052static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4053 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4054};
4055
4056static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4057 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4058};
4059
4060static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4061 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4062};
4063
4064static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4065 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4066};
4067
4068static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4069 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4070};
4071
4072static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4073 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4074};
4075
4076static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4077 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4078};
4079
4080static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4081 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4082};
4083
4084static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4085 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4086};
4087
4088static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4089 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4090};
4091
4092static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4093 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4094};
4095
4096static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4097 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4098};
4099
4100static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4101 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4102};
4103
4104static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4105 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4106};
4107
4108static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4109 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4110};
4111
4112static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4113 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4114};
4115
4116static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4117 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4118};
4119
4120static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4121 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4122};
4123
4124static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4125 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4126};
4127
4128static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4129 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4130};
4131
4132static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4133 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4134};
4135
4136static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4137 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4138};
4139
4140static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4141 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4142};
4143
4144static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4145 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4146};
4147
4148static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4149 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4150};
4151
4152static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4153 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4154};
4155
4156static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4157 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4158};
4159
4160static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4161 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4162};
4163
4164static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4165 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4166};
4167
4168static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4169 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4170};
4171
4172static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4173 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4174};
4175
4176static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4177 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4178};
4179
4180static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4181 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4182};
4183
4184static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4185 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4186};
4187
4188static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4189 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4190};
4191
4192static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4193 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4194};
4195
4196static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4197 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4198};
4199
4200static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4201 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4202};
4203
4204static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4205 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4206};
4207
4208static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4209 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4210};
4211
4212static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4213 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4214};
4215
4216static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4217 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4218};
4219
4220static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4221 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4222};
4223
4224static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4225 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4226};
4227
4228static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4229 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4230};
4231
4232static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4233 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4234};
4235
4236static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4237 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4238};
4239
4240static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4241 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4242};
4243
4244static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4245 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4246};
4247
4248static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4249 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4250};
4251
4252static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4253 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4254};
4255
4256static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4257 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4258};
4259
4260static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4261 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4262};
4263
4264static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4265 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4266};
4267
4268static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4269 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4270};
4271
4272static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4273 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4274};
4275
4276static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4277 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4278};
4279
4280static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4281 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4282};
4283
4284static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4285 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4286};
4287
4288static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4289 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4290};
4291
4292static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4293 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4294};
4295
4296static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4297 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4298};
4299
4300static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4301 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4302};
4303
4304static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4305 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4306};
4307
4308static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4309 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4310};
4311
4312static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4313 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4314};
4315
4316static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4317 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4318};
4319
4320static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4321 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4322};
4323
4324static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4325 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4326};
4327
4328static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4329 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4330};
4331
4332static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4333 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4334};
4335
4336static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4337 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4338};
4339
4340static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4341 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4342};
4343
4344static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4345 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4346};
4347
4348static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4349 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4350};
4351
4352static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4353 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4354};
4355
4356static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4357 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4358};
4359
4360static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4361 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4362};
4363
4364static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4365 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4366};
4367
4368static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4369 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4370};
4371
4372static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4373 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4374};
4375
4376static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4377 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4378};
4379
4380static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4381 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4382};
4383
4384static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4385 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4386};
4387
4388static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4389 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4390};
4391
4392static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4393 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4394};
4395
4396static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4397 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4398};
4399
4400static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4401 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4402};
4403
4404static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4405 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4406};
4407
4408static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4409 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4410};
4411
4412static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4413 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4414};
4415
4416static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4417 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4418};
4419
4420static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4421 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4422};
4423
4424static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4425 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4426};
4427
4428static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4429 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4430};
4431
4432static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4433 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4434};
4435
4436static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4437 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4438};
4439
4440static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4441 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4442};
4443
4444static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4445 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4446};
4447
4448static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4449 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4450};
4451
4452static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4453 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4454};
4455
4456static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4457 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4458};
4459
4460static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4461 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4462};
4463
4464static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4465 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4466};
4467
4468static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4469 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4470};
4471
4472static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4473 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4474};
4475
4476static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4477 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4478};
4479
4480static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4481 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4482};
4483
4484static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4485 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4486};
4487
4488static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4489 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4490};
4491
4492static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4493 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4494};
4495
4496static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4497 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4498};
4499
4500static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4501 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4502};
4503
4504static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4505 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4506};
4507
4508static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4509 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4510};
4511
4512static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4513 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4514};
4515
4516static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4517 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4518};
4519
4520static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4521 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4522};
4523
4524static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4525 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4526};
4527
4528static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4529 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4530};
4531
4532static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4533 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4534};
4535
4536static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4537 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4538};
4539
4540static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4541 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4542};
4543
4544static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4545 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4546};
4547
4548static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4549 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4550};
4551
4552static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4553 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4554};
4555
4556static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4557 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4558};
4559
4560static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4561 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4562};
4563
4564static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4565 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4566};
4567
4568static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4569 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4570};
4571
4572static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4573 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4574};
4575
4576static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4577 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4578};
4579
4580static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4581 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4582};
4583
4584static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4585 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4586};
4587
4588static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4589 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4590};
4591
4592static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4593 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4594};
4595
4596static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4597 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4598};
4599
4600static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4601 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4602};
4603
4604static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4605 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4606};
4607
4608static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4609 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4610};
4611
4612static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4613 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4614};
4615
4616static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4617 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4618};
4619
4620static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4621 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4622};
4623
4624static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4625 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4626};
4627
4628static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4629 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4630};
4631
4632static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4633 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4634};
4635
4636static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4637 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4638};
4639
4640static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4641 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4642};
4643
4644static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4645 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4646};
4647
4648static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4649 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4650};
4651
4652static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4653 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4654};
4655
4656static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4657 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4658};
4659
4660static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4661 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4662};
4663
4664static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4665 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4666};
4667
4668static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4669 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4670};
4671
4672static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4673 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4674};
4675
4676static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4677 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4678};
4679
4680static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
4681 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4682};
4683
4684static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4685 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4686};
4687
4688static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4689 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4690};
4691
4692static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4693 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4694};
4695
4696static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4697 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4698};
4699
4700static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4701 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4702};
4703
4704static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4705 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4706};
4707
4708static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4709 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4710};
4711
4712static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4713 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4714};
4715
4716static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4717 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4718};
4719
4720static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4721 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4722};
4723
4724static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4725 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4726};
4727
4728static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
4729 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4730};
4731
4732static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4733 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4734};
4735
4736static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4737 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4738};
4739
4740static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4741 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4742};
4743
4744static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4745 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4746};
4747
4748static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4749 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4750};
4751
4752static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4753 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4754};
4755
4756static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4757 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4758};
4759
4760static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4761 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } }
4762};
4763
4764static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4765 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } }
4766};
4767
4768static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
4769 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4770};
4771
4772static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
4773 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4774};
4775
4776static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
4777 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4778};
4779
4780static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
4781 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_S8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4782};
4783
4784static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI ATTRIBUTE_UNUSED = {
4785 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U16) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4786};
4787
4788static const CGEN_IFMT ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4789 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4790};
4791
4792static const CGEN_IFMT ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4793 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4794};
4795
4796static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4797 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4798};
4799
4800static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4801 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4802};
4803
4804static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4805 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4806};
4807
4808static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4809 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4810};
4811
4812static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4813 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4814};
4815
4816static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4817 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4818};
4819
4820static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4821 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4822};
4823
4824static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4825 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4826};
4827
4828static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4829 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4830};
4831
4832static const CGEN_IFMT ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4833 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4834};
4835
4836static const CGEN_IFMT ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
4837 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4838};
4839
4840static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4841 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4842};
4843
4844static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4845 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4846};
4847
4848static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4849 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4850};
4851
4852static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4853 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4854};
4855
4856static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4857 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4858};
4859
4860static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4861 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4862};
4863
4864static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4865 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4866};
4867
4868static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4869 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4870};
4871
4872static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4873 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4874};
4875
4876static const CGEN_IFMT ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4877 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4878};
4879
4880static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4881 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4882};
4883
4884static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
4885 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4886};
4887
4888static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4889 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4890};
4891
4892static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4893 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4894};
4895
4896static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4897 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4898};
4899
4900static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4901 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4902};
4903
4904static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4905 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4906};
4907
4908static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4909 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4910};
4911
4912static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4913 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4914};
4915
4916static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4917 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4918};
4919
4920static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4921 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4922};
4923
4924static const CGEN_IFMT ifmt_shl16_w_dst_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
4925 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4926};
4927
4928static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
4929 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4930};
4931
4932static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
4933 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4934};
4935
4936static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
4937 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4938};
4939
4940static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
4941 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4942};
4943
4944static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
4945 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4946};
4947
4948static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
4949 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4950};
4951
4952static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
4953 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4954};
4955
4956static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
4957 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4958};
4959
4960static const CGEN_IFMT ifmt_shl16_b_dst_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
4961 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4962};
4963
4964static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
4965 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4966};
4967
4968static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
4969 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4970};
4971
4972static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
4973 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4974};
4975
4976static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
4977 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4978};
4979
4980static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
4981 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4982};
4983
4984static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
4985 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4986};
4987
4988static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
4989 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4990};
4991
4992static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
4993 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4994};
4995
4996static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4997 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
4998};
4999
5000static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5001 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5002};
5003
5004static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5005 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5006};
5007
5008static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5009 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5010};
5011
5012static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5013 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5014};
5015
5016static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5017 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5018};
5019
5020static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5021 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5022};
5023
5024static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5025 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5026};
5027
5028static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5029 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5030};
5031
5032static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5033 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5034};
5035
5036static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5037 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5038};
5039
5040static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5041 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5042};
5043
5044static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5045 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5046};
5047
5048static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5049 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5050};
5051
5052static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
5053 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5054};
5055
5056static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5057 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5058};
5059
5060static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5061 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5062};
5063
5064static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5065 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5066};
5067
5068static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5069 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5070};
5071
5072static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5073 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5074};
5075
5076static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5077 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5078};
5079
5080static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5081 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5082};
5083
5084static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5085 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5086};
5087
5088static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5089 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5090};
5091
5092static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5093 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5094};
5095
5096static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5097 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5098};
5099
5100static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5101 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5102};
5103
5104static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5105 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5106};
5107
5108static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5109 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5110};
5111
5112static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5113 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5114};
5115
5116static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5117 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5118};
5119
5120static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5121 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5122};
5123
5124static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5125 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5126};
5127
5128static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5129 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5130};
5131
5132static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5133 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5134};
5135
5136static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5137 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5138};
5139
5140static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5141 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5142};
5143
5144static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5145 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5146};
5147
5148static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5149 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5150};
5151
5152static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5153 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5154};
5155
5156static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5157 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5158};
5159
5160static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5161 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5162};
5163
5164static const CGEN_IFMT ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5165 16, 16, 0xff30, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5166};
5167
5168static const CGEN_IFMT ifmt_sccnd_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5169 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5170};
5171
5172static const CGEN_IFMT ifmt_sccnd_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5173 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5174};
5175
5176static const CGEN_IFMT ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5177 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5178};
5179
5180static const CGEN_IFMT ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5181 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5182};
5183
5184static const CGEN_IFMT ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5185 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5186};
5187
5188static const CGEN_IFMT ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5189 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5190};
5191
5192static const CGEN_IFMT ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5193 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5194};
5195
5196static const CGEN_IFMT ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5197 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5198};
5199
5200static const CGEN_IFMT ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5201 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5202};
5203
5204static const CGEN_IFMT ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5205 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5206};
5207
5208static const CGEN_IFMT ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5209 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5210};
5211
5212static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5213 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5214};
5215
5216static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5217 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5218};
5219
5220static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5221 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5222};
5223
5224static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5225 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5226};
5227
5228static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5229 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5230};
5231
5232static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5233 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5234};
5235
5236static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5237 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5238};
5239
5240static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5241 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5242};
5243
5244static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5245 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5246};
5247
5248static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5249 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5250};
5251
5252static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5253 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5254};
5255
5256static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5257 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5258};
5259
5260static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5261 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5262};
5263
5264static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5265 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5266};
5267
5268static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5269 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5270};
5271
5272static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5273 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5274};
5275
5276static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5277 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5278};
5279
5280static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5281 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5282};
5283
5284static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5285 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5286};
5287
5288static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5289 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5290};
5291
5292static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5293 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5294};
5295
5296static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5297 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5298};
5299
5300static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5301 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5302};
5303
5304static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
5305 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5306};
5307
5308static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5309 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5310};
5311
5312static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5313 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5314};
5315
5316static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5317 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5318};
5319
5320static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5321 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5322};
5323
5324static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5325 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5326};
5327
5328static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5329 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5330};
5331
5332static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5333 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5334};
5335
5336static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5337 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5338};
5339
5340static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5341 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5342};
5343
5344static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5345 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5346};
5347
5348static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5349 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5350};
5351
5352static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5353 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5354};
5355
5356static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5357 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5358};
5359
5360static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5361 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5362};
5363
5364static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5365 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5366};
5367
5368static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5369 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5370};
5371
5372static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5373 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5374};
5375
5376static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5377 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5378};
5379
5380static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
5381 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5382};
5383
5384static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
5385 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5386};
5387
5388static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
5389 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5390};
5391
5392static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5393 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5394};
5395
5396static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5397 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5398};
5399
5400static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5401 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5402};
5403
5404static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5405 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5406};
5407
5408static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5409 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5410};
5411
5412static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5413 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5414};
5415
5416static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
5417 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5418};
5419
5420static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5421 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5422};
5423
5424static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
5425 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5426};
5427
5428static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5429 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5430};
5431
5432static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5433 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5434};
5435
5436static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
5437 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5438};
5439
5440static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5441 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5442};
5443
5444static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5445 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5446};
5447
5448static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5449 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5450};
5451
5452static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5453 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5454};
5455
5456static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5457 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5458};
5459
5460static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5461 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5462};
5463
5464static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5465 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5466};
5467
5468static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5469 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5470};
5471
5472static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5473 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5474};
5475
5476static const CGEN_IFMT ifmt_rorc16_w_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5477 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5478};
5479
5480static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5481 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5482};
5483
5484static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5485 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5486};
5487
5488static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5489 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5490};
5491
5492static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5493 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5494};
5495
5496static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5497 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5498};
5499
5500static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5501 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5502};
5503
5504static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5505 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5506};
5507
5508static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5509 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5510};
5511
5512static const CGEN_IFMT ifmt_rorc16_b_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5513 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5514};
5515
5516static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5517 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5518};
5519
5520static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5521 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5522};
5523
5524static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5525 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5526};
5527
5528static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5529 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5530};
5531
5532static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5533 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5534};
5535
5536static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5537 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5538};
5539
5540static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5541 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5542};
5543
5544static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5545 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5546};
5547
5548static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5549 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5550};
5551
5552static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5553 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5554};
5555
5556static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5557 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5558};
5559
5560static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5561 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5562};
5563
5564static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5565 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5566};
5567
5568static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5569 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5570};
5571
5572static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5573 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5574};
5575
5576static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5577 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5578};
5579
5580static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5581 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5582};
5583
5584static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5585 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5586};
5587
5588static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI ATTRIBUTE_UNUSED = {
5589 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5590};
5591
5592static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI ATTRIBUTE_UNUSED = {
5593 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5594};
5595
5596static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI ATTRIBUTE_UNUSED = {
5597 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5598};
5599
5600static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5601 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5602};
5603
5604static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5605 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5606};
5607
5608static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5609 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5610};
5611
5612static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI ATTRIBUTE_UNUSED = {
5613 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5614};
5615
5616static const CGEN_IFMT ifmt_push16_b_s_an_An16_push_S_derived ATTRIBUTE_UNUSED = {
5617 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } }
5618};
5619
5620static const CGEN_IFMT ifmt_push16_b_s_rn_Rn16_push_S_derived ATTRIBUTE_UNUSED = {
5621 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } }
5622};
5623
5624static const CGEN_IFMT ifmt_mulex_dst32_R3_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5625 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5626};
5627
5628static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5629 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5630};
5631
5632static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5633 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5634};
5635
5636static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
5637 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5638};
5639
5640static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5641 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5642};
5643
5644static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5645 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5646};
5647
5648static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5649 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5650};
5651
5652static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5653 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5654};
5655
5656static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5657 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5658};
5659
5660static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5661 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5662};
5663
5664static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5665 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5666};
5667
5668static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5669 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5670};
5671
5672static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5673 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5674};
5675
5676static const CGEN_IFMT ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5677 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5678};
5679
5680static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5681 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5682};
5683
5684static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5685 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5686};
5687
5688static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5689 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5690};
5691
5692static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5693 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5694};
5695
5696static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5697 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5698};
5699
5700static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5701 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5702};
5703
5704static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5705 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5706};
5707
5708static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5709 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5710};
5711
5712static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5713 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5714};
5715
5716static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5717 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5718};
5719
5720static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5721 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5722};
5723
5724static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5725 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5726};
5727
5728static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5729 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5730};
5731
5732static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5733 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5734};
5735
5736static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5737 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5738};
5739
5740static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5741 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5742};
5743
5744static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5745 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5746};
5747
5748static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5749 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5750};
5751
5752static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5753 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5754};
5755
5756static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5757 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5758};
5759
5760static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5761 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5762};
5763
5764static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5765 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5766};
5767
5768static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5769 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5770};
5771
5772static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5773 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5774};
5775
5776static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5777 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5778};
5779
5780static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5781 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5782};
5783
5784static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5785 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5786};
5787
5788static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5789 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5790};
5791
5792static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5793 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5794};
5795
5796static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5797 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5798};
5799
5800static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5801 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5802};
5803
5804static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5805 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5806};
5807
5808static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5809 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5810};
5811
5812static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5813 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5814};
5815
5816static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5817 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5818};
5819
5820static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5821 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5822};
5823
5824static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5825 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5826};
5827
5828static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5829 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5830};
5831
5832static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5833 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5834};
5835
5836static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5837 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5838};
5839
5840static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5841 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5842};
5843
5844static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5845 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5846};
5847
5848static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5849 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5850};
5851
5852static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5853 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5854};
5855
5856static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5857 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5858};
5859
5860static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5861 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5862};
5863
5864static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5865 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5866};
5867
5868static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5869 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5870};
5871
5872static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5873 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5874};
5875
5876static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5877 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5878};
5879
5880static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5881 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5882};
5883
5884static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI ATTRIBUTE_UNUSED = {
5885 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5886};
5887
5888static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI ATTRIBUTE_UNUSED = {
5889 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5890};
5891
5892static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI ATTRIBUTE_UNUSED = {
5893 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5894};
5895
5896static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5897 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5898};
5899
5900static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5901 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5902};
5903
5904static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5905 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5906};
5907
5908static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5909 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5910};
5911
5912static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
5913 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5914};
5915
5916static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
5917 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5918};
5919
f75eb1c0 5920static const CGEN_IFMT ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 5921 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5922};
5923
5924static const CGEN_IFMT ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
5925 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5926};
5927
5928static const CGEN_IFMT ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived ATTRIBUTE_UNUSED = {
5929 8, 8, 0xfb, { { F (F_0_4) }, { F (F_6_2) }, { F (F_5_1) }, { F (F_4_1) }, { 0 } }
5930};
5931
5932static const CGEN_IFMT ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5933 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5934};
5935
5936static const CGEN_IFMT ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5937 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5938};
5939
5940static const CGEN_IFMT ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
5941 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5942};
5943
5944static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
5945 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5946};
5947
5948static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
5949 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5950};
5951
5952static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
5953 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5954};
5955
5956static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
5957 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5958};
5959
5960static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
5961 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5962};
5963
5964static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
5965 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5966};
5967
5968static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
5969 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5970};
5971
5972static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
5973 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5974};
5975
5976static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
5977 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5978};
5979
5980static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
5981 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5982};
5983
5984static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
5985 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5986};
5987
5988static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
5989 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5990};
5991
5992static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
5993 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5994};
5995
5996static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
5997 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
5998};
5999
6000static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6001 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6002};
6003
6004static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6005 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6006};
6007
6008static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6009 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6010};
6011
6012static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6013 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6014};
6015
6016static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6017 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6018};
6019
6020static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6021 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6022};
6023
6024static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6025 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6026};
6027
6028static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6029 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6030};
6031
6032static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6033 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6034};
6035
6036static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6037 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6038};
6039
6040static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6041 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6042};
6043
6044static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6045 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6046};
6047
6048static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6049 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6050};
6051
6052static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6053 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6054};
6055
6056static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6057 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6058};
6059
6060static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6061 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6062};
6063
6064static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6065 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6066};
6067
6068static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6069 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6070};
6071
6072static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6073 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6074};
6075
6076static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6077 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6078};
6079
6080static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6081 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6082};
6083
6084static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6085 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6086};
6087
6088static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6089 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6090};
6091
6092static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6093 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6094};
6095
6096static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6097 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6098};
6099
6100static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6101 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6102};
6103
6104static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6105 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6106};
6107
6108static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6109 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6110};
6111
6112static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6113 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6114};
6115
6116static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6117 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6118};
6119
6120static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6121 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6122};
6123
6124static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6125 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6126};
6127
6128static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6129 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6130};
6131
6132static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6133 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6134};
6135
6136static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6137 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6138};
6139
6140static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6141 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6142};
6143
6144static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6145 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6146};
6147
6148static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6149 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6150};
6151
6152static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6153 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6154};
6155
6156static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6157 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6158};
6159
6160static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6161 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6162};
6163
6164static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6165 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6166};
6167
6168static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6169 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6170};
6171
6172static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6173 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6174};
6175
6176static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6177 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6178};
6179
6180static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6181 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6182};
6183
6184static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6185 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6186};
6187
6188static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6189 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6190};
6191
6192static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6193 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6194};
6195
6196static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6197 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6198};
6199
6200static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6201 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6202};
6203
6204static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6205 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6206};
6207
6208static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6209 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6210};
6211
6212static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6213 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6214};
6215
6216static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6217 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6218};
6219
6220static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6221 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6222};
6223
6224static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6225 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6226};
6227
6228static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6229 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6230};
6231
6232static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6233 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6234};
6235
6236static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6237 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6238};
6239
6240static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6241 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6242};
6243
6244static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6245 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6246};
6247
6248static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6249 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6250};
6251
6252static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6253 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6254};
6255
6256static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6257 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6258};
6259
6260static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6261 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6262};
6263
6264static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6265 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6266};
6267
6268static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6269 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6270};
6271
6272static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6273 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6274};
6275
6276static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6277 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6278};
6279
6280static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6281 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6282};
6283
6284static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6285 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6286};
6287
6288static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6289 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6290};
6291
6292static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6293 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6294};
6295
6296static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6297 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6298};
6299
6300static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6301 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6302};
6303
6304static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6305 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6306};
6307
6308static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6309 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6310};
6311
6312static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6313 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6314};
6315
6316static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6317 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6318};
6319
6320static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6321 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6322};
6323
6324static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6325 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6326};
6327
6328static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6329 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6330};
6331
6332static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6333 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6334};
6335
6336static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6337 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6338};
6339
6340static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6341 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6342};
6343
6344static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6345 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6346};
6347
6348static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6349 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6350};
6351
6352static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6353 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6354};
6355
6356static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6357 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6358};
6359
6360static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6361 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6362};
6363
6364static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6365 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6366};
6367
6368static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6369 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6370};
6371
6372static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6373 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6374};
6375
6376static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6377 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6378};
6379
6380static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6381 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6382};
6383
6384static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6385 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6386};
6387
6388static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6389 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6390};
6391
6392static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6393 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6394};
6395
6396static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6397 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6398};
6399
6400static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6401 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6402};
6403
6404static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6405 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6406};
6407
6408static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6409 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6410};
6411
6412static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6413 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6414};
6415
6416static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6417 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6418};
6419
6420static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6421 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6422};
6423
6424static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6425 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6426};
6427
6428static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6429 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6430};
6431
6432static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6433 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6434};
6435
6436static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6437 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6438};
6439
6440static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6441 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6442};
6443
6444static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6445 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6446};
6447
6448static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6449 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6450};
6451
6452static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6453 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6454};
6455
6456static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6457 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6458};
6459
6460static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6461 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6462};
6463
6464static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6465 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6466};
6467
6468static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6469 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6470};
6471
6472static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6473 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6474};
6475
6476static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6477 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6478};
6479
6480static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6481 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6482};
6483
6484static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6485 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6486};
6487
6488static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6489 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6490};
6491
6492static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6493 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6494};
6495
6496static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6497 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6498};
6499
6500static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6501 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6502};
6503
6504static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6505 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6506};
6507
6508static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6509 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6510};
6511
6512static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6513 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6514};
6515
6516static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6517 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6518};
6519
6520static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6521 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6522};
6523
6524static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6525 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6526};
6527
6528static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
6529 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6530};
6531
6532static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
6533 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
6534};
6535
6536static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
6537 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
6538};
6539
6540static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6541 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { 0 } }
6542};
6543
6544static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6545 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { 0 } }
6546};
6547
6548static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI ATTRIBUTE_UNUSED = {
6549 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { 0 } }
6550};
6551
6552static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
6553 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6554};
6555
6556static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
6557 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6558};
6559
6560static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
6561 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6562};
6563
6564static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6565 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6566};
6567
6568static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6569 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6570};
6571
6572static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6573 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6574};
6575
6576static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6577 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6578};
6579
6580static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6581 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6582};
6583
6584static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6585 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6586};
6587
6588static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6589 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6590};
6591
6592static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
6593 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6594};
6595
6596static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
6597 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6598};
6599
6600static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
6601 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6602};
6603
6604static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
6605 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6606};
6607
6608static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
6609 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6610};
6611
6612static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6613 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6614};
6615
6616static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6617 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6618};
6619
6620static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6621 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6622};
6623
6624static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6625 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6626};
6627
6628static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6629 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6630};
6631
6632static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6633 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6634};
6635
6636static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6637 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6638};
6639
6640static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
6641 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6642};
6643
6644static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
6645 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6646};
6647
6648static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
6649 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6650};
6651
6652static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
6653 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6654};
6655
6656static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
6657 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6658};
6659
6660static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
6661 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6662};
6663
6664static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
6665 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6666};
6667
6668static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6669 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6670};
6671
6672static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
6673 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6674};
6675
6676static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6677 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6678};
6679
6680static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
6681 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6682};
6683
6684static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6685 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6686};
6687
6688static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6689 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6690};
6691
6692static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6693 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6694};
6695
6696static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6697 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6698};
6699
6700static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6701 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6702};
6703
6704static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6705 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6706};
6707
6708static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6709 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6710};
6711
6712static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6713 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6714};
6715
6716static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6717 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6718};
6719
6720static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6721 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6722};
6723
6724static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6725 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6726};
6727
6728static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6729 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6730};
6731
a1a280bb
DD		 6732static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
6733 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6734};
6735
a1a280bb
DD		 6736static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
6737 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6738};
6739
a1a280bb
DD		 6740static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
6741 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6742};
6743
a1a280bb
DD		 6744static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
6745 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6746};
6747
a1a280bb
DD		 6748static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
6749 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6750};
6751
a1a280bb
DD		 6752static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
6753 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6754};
6755
a1a280bb 6756static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6757 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6758};
6759
a1a280bb 6760static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6761 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6762};
6763
a1a280bb 6764static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6765 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6766};
6767
a1a280bb
DD		 6768static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
6769 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6770};
6771
a1a280bb
DD		 6772static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
6773 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6774};
6775
a1a280bb
DD		 6776static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
6777 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6778};
6779
a1a280bb
DD		 6780static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
6781 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6782};
6783
a1a280bb
DD		 6784static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6785 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6786};
6787
a1a280bb
DD		 6788static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6789 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6790};
6791
a1a280bb 6792static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6793 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6794};
6795
a1a280bb 6796static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6797 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6798};
6799
a1a280bb 6800static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6801 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6802};
6803
6804static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
6805 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6806};
6807
6808static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
6809 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6810};
6811
6812static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = {
6813 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6814};
6815
6816static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6817 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6818};
6819
6820static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6821 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6822};
6823
6824static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6825 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6826};
6827
6828static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6829 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6830};
6831
6832static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6833 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6834};
6835
6836static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6837 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6838};
6839
6840static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6841 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6842};
6843
6844static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
6845 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6846};
6847
6848static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
6849 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6850};
6851
6852static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6853 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6854};
6855
6856static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6857 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6858};
6859
6860static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6861 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6862};
6863
6864static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6865 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6866};
6867
6868static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6869 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6870};
6871
6872static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6873 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6874};
6875
6876static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6877 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6878};
6879
6880static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6881 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6882};
6883
6884static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6885 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6886};
6887
6888static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6889 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6890};
6891
6892static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6893 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6894};
6895
6896static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6897 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6898};
6899
6900static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
6901 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6902};
6903
6904static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
6905 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6906};
6907
6908static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
6909 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6910};
6911
6912static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6913 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6914};
6915
6916static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6917 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6918};
6919
6920static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6921 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6922};
6923
6924static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6925 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6926};
6927
6928static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6929 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6930};
6931
6932static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6933 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6934};
6935
6936static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6937 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6938};
6939
6940static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
6941 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6942};
6943
6944static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
6945 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6946};
6947
6948static const CGEN_IFMT ifmt_stc16_src_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
6949 16, 16, 0xff8c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6950};
6951
6952static const CGEN_IFMT ifmt_stc16_src_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
6953 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6954};
6955
6956static const CGEN_IFMT ifmt_stc16_src_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
6957 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6958};
6959
6960static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
6961 24, 24, 0xff8e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6962};
6963
6964static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
6965 32, 32, 0xff8e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6966};
6967
6968static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
6969 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6970};
6971
6972static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
6973 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6974};
6975
6976static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
6977 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6978};
6979
6980static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
6981 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
6982};
6983
6984static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = {
6985 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
6986};
6987
6988static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI ATTRIBUTE_UNUSED = {
6989 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
6990};
6991
6992static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI ATTRIBUTE_UNUSED = {
6993 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
6994};
6995
6996static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI ATTRIBUTE_UNUSED = {
6997 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
6998};
6999
7000static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI ATTRIBUTE_UNUSED = {
7001 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7002};
7003
7004static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI ATTRIBUTE_UNUSED = {
7005 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7006};
7007
7008static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI ATTRIBUTE_UNUSED = {
7009 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7010};
7011
7012static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI ATTRIBUTE_UNUSED = {
7013 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7014};
7015
7016static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUTE_UNUSED = {
7017 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7018};
7019
7020static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
7021 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7022};
7023
7024static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
7025 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7026};
7027
7028static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = {
7029 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7030};
7031
7032static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
7033 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7034};
7035
7036static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
7037 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7038};
7039
7040static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
7041 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7042};
7043
7044static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
7045 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7046};
7047
7048static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
7049 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7050};
7051
7052static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
7053 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7054};
7055
7056static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
7057 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7058};
7059
7060static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
7061 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7062};
7063
7064static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
7065 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7066};
7067
7068static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
7069 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7070};
7071
7072static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
7073 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7074};
7075
7076static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
7077 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7078};
7079
7080static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
7081 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7082};
7083
7084static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
7085 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7086};
7087
7088static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
7089 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7090};
7091
7092static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
7093 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7094};
7095
7096static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
7097 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7098};
7099
7100static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
7101 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7102};
7103
7104static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
7105 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7106};
7107
7108static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
7109 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7110};
7111
7112static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
7113 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7114};
7115
7116static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
7117 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7118};
7119
7120static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
7121 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7122};
7123
7124static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
7125 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7126};
7127
7128static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
7129 32, 56, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7130};
7131
7132static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
7133 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7134};
7135
7136static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
7137 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7138};
7139
7140static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7141 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7142};
7143
7144static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7145 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7146};
7147
7148static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7149 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7150};
7151
7152static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7153 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7154};
7155
7156static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7157 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7158};
7159
7160static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7161 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7162};
7163
7164static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7165 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7166};
7167
7168static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7169 32, 80, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7170};
7171
7172static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7173 32, 80, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7174};
7175
7176static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
7177 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7178};
7179
7180static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
7181 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7182};
7183
7184static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
7185 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7186};
7187
7188static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7189 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7190};
7191
7192static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7193 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7194};
7195
7196static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7197 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7198};
7199
7200static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7201 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7202};
7203
7204static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7205 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7206};
7207
7208static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7209 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7210};
7211
7212static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
7213 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7214};
7215
7216static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7217 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } }
7218};
7219
7220static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
7221 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } }
7222};
7223
7224static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed ATTRIBUTE_UNUSED = {
7225 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7226};
7227
7228static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed ATTRIBUTE_UNUSED = {
7229 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7230};
7231
7232static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed ATTRIBUTE_UNUSED = {
7233 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7234};
7235
7236static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7237 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7238};
7239
7240static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7241 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7242};
7243
7244static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7245 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7246};
7247
7248static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed ATTRIBUTE_UNUSED = {
7249 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7250};
7251
7252static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed ATTRIBUTE_UNUSED = {
7253 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7254};
7255
7256static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed ATTRIBUTE_UNUSED = {
7257 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7258};
7259
7260static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed ATTRIBUTE_UNUSED = {
7261 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7262};
7263
7264static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed ATTRIBUTE_UNUSED = {
7265 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7266};
7267
7268static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed ATTRIBUTE_UNUSED = {
7269 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7270};
7271
7272static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_Rn_direct ATTRIBUTE_UNUSED = {
7273 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7274};
7275
7276static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_direct ATTRIBUTE_UNUSED = {
7277 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7278};
7279
7280static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_indirect ATTRIBUTE_UNUSED = {
7281 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7282};
7283
7284static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative ATTRIBUTE_UNUSED = {
7285 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7286};
7287
7288static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative ATTRIBUTE_UNUSED = {
7289 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7290};
7291
7292static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = {
7293 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7294};
7295
7296static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = {
7297 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7298};
7299
7300static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = {
7301 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7302};
7303
7304static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_absolute ATTRIBUTE_UNUSED = {
7305 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7306};
7307
7308static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = {
7309 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7310};
7311
7312static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = {
7313 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7314};
7315
7316static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = {
7317 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7318};
7319
7320static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7321 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7322};
7323
7324static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7325 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7326};
7327
7328static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7329 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7330};
7331
7332static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7333 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7334};
7335
7336static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7337 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7338};
7339
7340static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7341 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7342};
7343
7344static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7345 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7346};
7347
7348static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7349 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7350};
7351
7352static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7353 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7354};
7355
7356static const CGEN_IFMT ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S ATTRIBUTE_UNUSED = {
7357 16, 16, 0xf800, { { F (F_0_2) }, { F (F_BITBASE16_U11_S) }, { F (F_2_2) }, { F (F_4_1) }, { 0 } }
7358};
7359
7360static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = {
7361 24, 24, 0xff3800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7362};
7363
7364static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = {
7365 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7366};
7367
7368static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = {
7369 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7370};
7371
7372static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7373 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7374};
7375
7376static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7377 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7378};
7379
7380static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7381 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7382};
7383
7384static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7385 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7386};
7387
7388static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7389 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7390};
7391
7392static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7393 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7394};
7395
7396static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7397 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7398};
7399
7400static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7401 32, 48, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } }
7402};
7403
7404static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7405 32, 48, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } }
7406};
7407
7408static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct ATTRIBUTE_UNUSED = {
7409 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7410};
7411
7412static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct ATTRIBUTE_UNUSED = {
7413 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7414};
7415
7416static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative ATTRIBUTE_UNUSED = {
7417 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7418};
7419
7420static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = {
7421 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7422};
7423
7424static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = {
7425 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7426};
7427
7428static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative ATTRIBUTE_UNUSED = {
7429 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7430};
7431
7432static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = {
7433 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7434};
7435
7436static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute ATTRIBUTE_UNUSED = {
7437 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7438};
7439
7440static const CGEN_IFMT ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect ATTRIBUTE_UNUSED = {
7441 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
7442};
7443
7444static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI ATTRIBUTE_UNUSED = {
7445 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } }
7446};
7447
7448static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI ATTRIBUTE_UNUSED = {
7449 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } }
7450};
7451
7452static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
7453 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7454};
7455
7456static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
7457 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7458};
7459
7460static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
7461 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7462};
7463
7464static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7465 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7466};
7467
7468static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7469 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7470};
7471
7472static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7473 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7474};
7475
7476static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7477 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7478};
7479
7480static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7481 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7482};
7483
7484static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7485 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7486};
7487
7488static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7489 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7490};
7491
7492static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
7493 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7494};
7495
7496static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
7497 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7498};
7499
92e0a941 7500static const CGEN_IFMT ifmt_add16_wQ_sp ATTRIBUTE_UNUSED = {
49f58d10
JB		 7501 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
7502};
7503
7504static const CGEN_IFMT ifmt_add16_b_G_sp ATTRIBUTE_UNUSED = {
7505 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7506};
7507
7508static const CGEN_IFMT ifmt_add16_w_G_sp ATTRIBUTE_UNUSED = {
7509 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7510};
7511
7512static const CGEN_IFMT ifmt_add32_l_imm3_Q ATTRIBUTE_UNUSED = {
7513 8, 8, 0xce, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { 0 } }
7514};
7515
7516static const CGEN_IFMT ifmt_add32_l_imm8_S ATTRIBUTE_UNUSED = {
7517 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7518};
7519
7520static const CGEN_IFMT ifmt_add32_l_imm16_G ATTRIBUTE_UNUSED = {
7521 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7522};
7523
7524static const CGEN_IFMT ifmt_dadc16_b_r0h_r0l ATTRIBUTE_UNUSED = {
7525 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } }
7526};
7527
7528static const CGEN_IFMT ifmt_bm16_c ATTRIBUTE_UNUSED = {
7529 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { 0 } }
7530};
7531
7532static const CGEN_IFMT ifmt_bm32_c ATTRIBUTE_UNUSED = {
7533 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_COND32) }, { F (F_10_3) }, { 0 } }
7534};
7535
7536static const CGEN_IFMT ifmt_brk16 ATTRIBUTE_UNUSED = {
7537 8, 8, 0xff, { { F (F_0_4) }, { F (F_4_4) }, { 0 } }
7538};
7539
7540static const CGEN_IFMT ifmt_dec16_w ATTRIBUTE_UNUSED = {
7541 8, 8, 0xf7, { { F (F_0_4) }, { F (F_DST16_AN_S) }, { F (F_5_3) }, { 0 } }
7542};
7543
7544static const CGEN_IFMT ifmt_div32_b_Imm_16_QI ATTRIBUTE_UNUSED = {
7545 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7546};
7547
7548static const CGEN_IFMT ifmt_div32_w_Imm_16_HI ATTRIBUTE_UNUSED = {
7549 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7550};
7551
7552static const CGEN_IFMT ifmt_enter16 ATTRIBUTE_UNUSED = {
7553 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
7554};
7555
7556static const CGEN_IFMT ifmt_enter32 ATTRIBUTE_UNUSED = {
7557 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U8) }, { 0 } }
7558};
7559
7560static const CGEN_IFMT ifmt_fclr16 ATTRIBUTE_UNUSED = {
7561 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } }
7562};
7563
7564static const CGEN_IFMT ifmt_fclr ATTRIBUTE_UNUSED = {
7565 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7566};
7567
7568static const CGEN_IFMT ifmt_int16 ATTRIBUTE_UNUSED = {
7569 16, 16, 0xffc0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_2) }, { F (F_DSP_10_U6) }, { 0 } }
7570};
7571
7572static const CGEN_IFMT ifmt_int32 ATTRIBUTE_UNUSED = {
7573 16, 16, 0xff03, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U6) }, { F (F_14_2) }, { 0 } }
7574};
7575
7576static const CGEN_IFMT ifmt_jcnd16_5 ATTRIBUTE_UNUSED = {
7577 16, 16, 0xf800, { { F (F_0_4) }, { F (F_4_1) }, { F (F_COND16J_5) }, { F (F_LAB_8_8) }, { 0 } }
7578};
7579
7580static const CGEN_IFMT ifmt_jcnd16 ATTRIBUTE_UNUSED = {
7581 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { F (F_LAB_16_8) }, { 0 } }
7582};
7583
7584static const CGEN_IFMT ifmt_jcnd32 ATTRIBUTE_UNUSED = {
7585 16, 16, 0x8e00, { { F (F_0_1) }, { F (F_COND32J) }, { F (F_4_3) }, { F (F_LAB_8_8) }, { 0 } }
7586};
7587
7588static const CGEN_IFMT ifmt_jmp16_s ATTRIBUTE_UNUSED = {
7589 8, 8, 0xf8, { { F (F_0_4) }, { F (F_4_1) }, { F (F_LAB_5_3) }, { 0 } }
7590};
7591
7592static const CGEN_IFMT ifmt_jmp16_b ATTRIBUTE_UNUSED = {
7593 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_8) }, { 0 } }
7594};
7595
7596static const CGEN_IFMT ifmt_jmp16_w ATTRIBUTE_UNUSED = {
7597 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_16) }, { 0 } }
7598};
7599
7600static const CGEN_IFMT ifmt_jmp16_a ATTRIBUTE_UNUSED = {
7601 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_24) }, { 0 } }
7602};
7603
7604static const CGEN_IFMT ifmt_jmps16 ATTRIBUTE_UNUSED = {
7605 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { 0 } }
7606};
7607
7608static const CGEN_IFMT ifmt_jmp32_s ATTRIBUTE_UNUSED = {
7609 8, 8, 0xce, { { F (F_0_2) }, { F (F_LAB32_JMP_S) }, { F (F_4_3) }, { 0 } }
7610};
7611
7612static const CGEN_IFMT ifmt_ldc16_imm16 ATTRIBUTE_UNUSED = {
7613 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7614};
7615
7616static const CGEN_IFMT ifmt_ldc32_imm16_cr1 ATTRIBUTE_UNUSED = {
7617 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { F (F_DSP_16_S16) }, { 0 } }
7618};
7619
7620static const CGEN_IFMT ifmt_ldc32_imm16_cr2 ATTRIBUTE_UNUSED = {
7621 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7622};
7623
7624static const CGEN_IFMT ifmt_ldc32_imm16_cr3 ATTRIBUTE_UNUSED = {
7625 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7626};
7627
7628static const CGEN_IFMT ifmt_ldctx16 ATTRIBUTE_UNUSED = {
7629 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { 0 } }
7630};
7631
7632static const CGEN_IFMT ifmt_ldipl16_imm ATTRIBUTE_UNUSED = {
7633 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_IMM_13_U3) }, { 0 } }
7634};
7635
7636static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = {
7637 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S16) }, { 0 } }
7638};
7639
7640static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = {
f75eb1c0 7641 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S24) }, { 0 } }
49f58d10
JB		 7642};
7643
7644static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = {
7645 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } }
7646};
7647
7648static const CGEN_IFMT ifmt_popc32_imm16_cr1 ATTRIBUTE_UNUSED = {
7649 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7650};
7651
7652static const CGEN_IFMT ifmt_popc32_imm16_cr2 ATTRIBUTE_UNUSED = {
7653 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7654};
7655
7656static const CGEN_IFMT ifmt_popm16 ATTRIBUTE_UNUSED = {
7657 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } }
7658};
7659
7660static const CGEN_IFMT ifmt_pushm16 ATTRIBUTE_UNUSED = {
7661 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } }
7662};
7663
7664static const CGEN_IFMT ifmt_push32_l_imm ATTRIBUTE_UNUSED = {
7665 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } }
7666};
7667
7668static const CGEN_IFMT ifmt_sha16_L_imm_r2r0 ATTRIBUTE_UNUSED = {
7669 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
7670};
7671
7672static const CGEN_IFMT ifmt_stzx16_imm8_imm8_r0h ATTRIBUTE_UNUSED = {
7673 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { 0 } }
7674};
7675
7676static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8sb ATTRIBUTE_UNUSED = {
7677 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U8) }, { F (F_DSP_24_S8) }, { 0 } }
7678};
7679
7680static const CGEN_IFMT ifmt_stzx16_imm8_imm8_abs16 ATTRIBUTE_UNUSED = {
7681 32, 40, 0xff000000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U16) }, { 0 } }
7682};
7683
7684#undef F
7685
7686#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
7687#define A(a) (1 << CGEN_INSN_##a)
7688#else
7689#define A(a) (1 << CGEN_INSN_/**/a)
7690#endif
7691#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
7692#define OPERAND(op) M32C_OPERAND_##op
7693#else
7694#define OPERAND(op) M32C_OPERAND_/**/op
7695#endif
7696#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
7697#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
7698
7699/* The instruction table. */
7700
7701static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
7702{
7703 /* Special null first entry.
7704 A `num' value of zero is thus invalid.
7705 Also, the special `invalid' insn resides here. */
7706 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
7707/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7708 {
7709 { 0, 0, 0, 0 },
7710 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7711 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980b00 }
7712 },
7713/* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
7714 {
7715 { 0, 0, 0, 0 },
7716 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7717 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982b00 }
7718 },
7719/* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
7720 {
7721 { 0, 0, 0, 0 },
7722 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7723 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983b00 }
7724 },
7725/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7726 {
7727 { 0, 0, 0, 0 },
7728 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7729 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908b00 }
7730 },
7731/* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
7732 {
7733 { 0, 0, 0, 0 },
7734 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7735 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190ab00 }
7736 },
7737/* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
7738 {
7739 { 0, 0, 0, 0 },
7740 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7741 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190bb00 }
7742 },
7743/* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7744 {
7745 { 0, 0, 0, 0 },
7746 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7747 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900b00 }
7748 },
7749/* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
7750 {
7751 { 0, 0, 0, 0 },
7752 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7753 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902b00 }
7754 },
7755/* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
7756 {
7757 { 0, 0, 0, 0 },
7758 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7759 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903b00 }
7760 },
7761/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
7762 {
7763 { 0, 0, 0, 0 },
7764 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7765 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920b00 }
7766 },
7767/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7768 {
7769 { 0, 0, 0, 0 },
7770 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7771 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922b00 }
7772 },
7773/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7774 {
7775 { 0, 0, 0, 0 },
7776 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7777 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923b00 }
7778 },
7779/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
7780 {
7781 { 0, 0, 0, 0 },
7782 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7783 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940b00 }
7784 },
7785/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7786 {
7787 { 0, 0, 0, 0 },
7788 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7789 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942b00 }
7790 },
7791/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7792 {
7793 { 0, 0, 0, 0 },
7794 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7795 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943b00 }
7796 },
7797/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
7798 {
7799 { 0, 0, 0, 0 },
7800 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7801 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960b00 }
7802 },
7803/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7804 {
7805 { 0, 0, 0, 0 },
7806 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7807 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962b00 }
7808 },
7809/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7810 {
7811 { 0, 0, 0, 0 },
7812 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7813 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963b00 }
7814 },
7815/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
7816 {
7817 { 0, 0, 0, 0 },
7818 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
7819 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928b00 }
7820 },
7821/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
7822 {
7823 { 0, 0, 0, 0 },
7824 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
7825 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192ab00 }
7826 },
7827/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
7828 {
7829 { 0, 0, 0, 0 },
7830 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
7831 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192bb00 }
7832 },
7833/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
7834 {
7835 { 0, 0, 0, 0 },
7836 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
7837 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948b00 }
7838 },
7839/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
7840 {
7841 { 0, 0, 0, 0 },
7842 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
7843 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194ab00 }
7844 },
7845/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
7846 {
7847 { 0, 0, 0, 0 },
7848 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
7849 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194bb00 }
7850 },
7851/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
7852 {
7853 { 0, 0, 0, 0 },
7854 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
7855 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192cb00 }
7856 },
7857/* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
7858 {
7859 { 0, 0, 0, 0 },
7860 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
7861 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192eb00 }
7862 },
7863/* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
7864 {
7865 { 0, 0, 0, 0 },
7866 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
7867 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192fb00 }
7868 },
7869/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
7870 {
7871 { 0, 0, 0, 0 },
7872 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
7873 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194cb00 }
7874 },
7875/* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
7876 {
7877 { 0, 0, 0, 0 },
7878 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
7879 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194eb00 }
7880 },
7881/* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
7882 {
7883 { 0, 0, 0, 0 },
7884 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
7885 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194fb00 }
7886 },
7887/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
7888 {
7889 { 0, 0, 0, 0 },
7890 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
7891 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196cb00 }
7892 },
7893/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
7894 {
7895 { 0, 0, 0, 0 },
7896 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
7897 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196eb00 }
7898 },
7899/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
7900 {
7901 { 0, 0, 0, 0 },
7902 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
7903 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196fb00 }
7904 },
7905/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
7906 {
7907 { 0, 0, 0, 0 },
7908 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
7909 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968b00 }
7910 },
7911/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
7912 {
7913 { 0, 0, 0, 0 },
7914 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
7915 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196ab00 }
7916 },
7917/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
7918 {
7919 { 0, 0, 0, 0 },
7920 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
7921 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196bb00 }
7922 },
7923/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7924 {
7925 { 0, 0, 0, 0 },
7926 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7927 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80b00 }
7928 },
7929/* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
7930 {
7931 { 0, 0, 0, 0 },
7932 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7933 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82b00 }
7934 },
7935/* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
7936 {
7937 { 0, 0, 0, 0 },
7938 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7939 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83b00 }
7940 },
7941/* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
7942 {
7943 { 0, 0, 0, 0 },
7944 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
7945 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83b00 }
7946 },
7947/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7948 {
7949 { 0, 0, 0, 0 },
7950 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7951 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08b00 }
7952 },
7953/* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
7954 {
7955 { 0, 0, 0, 0 },
7956 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7957 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0ab00 }
7958 },
7959/* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
7960 {
7961 { 0, 0, 0, 0 },
7962 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7963 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0bb00 }
7964 },
7965/* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
7966 {
7967 { 0, 0, 0, 0 },
7968 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
7969 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0bb00 }
7970 },
7971/* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7972 {
7973 { 0, 0, 0, 0 },
7974 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7975 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00b00 }
7976 },
7977/* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
7978 {
7979 { 0, 0, 0, 0 },
7980 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7981 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02b00 }
7982 },
7983/* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
7984 {
7985 { 0, 0, 0, 0 },
7986 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7987 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03b00 }
7988 },
7989/* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
7990 {
7991 { 0, 0, 0, 0 },
7992 { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7993 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03b00 }
7994 },
7995/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
7996 {
7997 { 0, 0, 0, 0 },
7998 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7999 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20b00 }
8000 },
8001/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8002 {
8003 { 0, 0, 0, 0 },
8004 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8005 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22b00 }
8006 },
8007/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8008 {
8009 { 0, 0, 0, 0 },
8010 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8011 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23b00 }
8012 },
8013/* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8014 {
8015 { 0, 0, 0, 0 },
8016 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8017 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23b00 }
8018 },
8019/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8020 {
8021 { 0, 0, 0, 0 },
8022 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8023 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40b00 }
8024 },
8025/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8026 {
8027 { 0, 0, 0, 0 },
8028 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8029 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42b00 }
8030 },
8031/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8032 {
8033 { 0, 0, 0, 0 },
8034 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8035 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43b00 }
8036 },
8037/* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8038 {
8039 { 0, 0, 0, 0 },
8040 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8041 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43b00 }
8042 },
8043/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8044 {
8045 { 0, 0, 0, 0 },
8046 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8047 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60b00 }
8048 },
8049/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8050 {
8051 { 0, 0, 0, 0 },
8052 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8053 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62b00 }
8054 },
8055/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8056 {
8057 { 0, 0, 0, 0 },
8058 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8059 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63b00 }
8060 },
8061/* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8062 {
8063 { 0, 0, 0, 0 },
8064 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8065 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63b00 }
8066 },
8067/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8068 {
8069 { 0, 0, 0, 0 },
8070 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8071 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28b00 }
8072 },
8073/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8074 {
8075 { 0, 0, 0, 0 },
8076 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8077 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2ab00 }
8078 },
8079/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8080 {
8081 { 0, 0, 0, 0 },
8082 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8083 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2bb00 }
8084 },
8085/* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8086 {
8087 { 0, 0, 0, 0 },
8088 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8089 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2bb00 }
8090 },
8091/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8092 {
8093 { 0, 0, 0, 0 },
8094 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8095 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48b00 }
8096 },
8097/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8098 {
8099 { 0, 0, 0, 0 },
8100 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8101 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4ab00 }
8102 },
8103/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8104 {
8105 { 0, 0, 0, 0 },
8106 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8107 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4bb00 }
8108 },
8109/* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8110 {
8111 { 0, 0, 0, 0 },
8112 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8113 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4bb00 }
8114 },
8115/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8116 {
8117 { 0, 0, 0, 0 },
8118 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8119 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2cb00 }
8120 },
8121/* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8122 {
8123 { 0, 0, 0, 0 },
8124 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8125 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2eb00 }
8126 },
8127/* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8128 {
8129 { 0, 0, 0, 0 },
8130 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8131 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2fb00 }
8132 },
8133/* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8134 {
8135 { 0, 0, 0, 0 },
8136 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8137 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2fb00 }
8138 },
8139/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8140 {
8141 { 0, 0, 0, 0 },
8142 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8143 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4cb00 }
8144 },
8145/* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8146 {
8147 { 0, 0, 0, 0 },
8148 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8149 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4eb00 }
8150 },
8151/* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8152 {
8153 { 0, 0, 0, 0 },
8154 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8155 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4fb00 }
8156 },
8157/* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8158 {
8159 { 0, 0, 0, 0 },
8160 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8161 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4fb00 }
8162 },
8163/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8164 {
8165 { 0, 0, 0, 0 },
8166 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
8167 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6cb00 }
8168 },
8169/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8170 {
8171 { 0, 0, 0, 0 },
8172 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8173 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6eb00 }
8174 },
8175/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8176 {
8177 { 0, 0, 0, 0 },
8178 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8179 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6fb00 }
8180 },
8181/* extz ${Dsp-24-u16},${Dsp-40-u16} */
8182 {
8183 { 0, 0, 0, 0 },
8184 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
8185 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6fb00 }
8186 },
8187/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8188 {
8189 { 0, 0, 0, 0 },
8190 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
8191 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68b00 }
8192 },
8193/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8194 {
8195 { 0, 0, 0, 0 },
8196 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8197 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6ab00 }
8198 },
8199/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8200 {
8201 { 0, 0, 0, 0 },
8202 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8203 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6bb00 }
8204 },
8205/* extz ${Dsp-24-u16},${Dsp-40-u24} */
8206 {
8207 { 0, 0, 0, 0 },
8208 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
8209 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6bb00 }
8210 },
8211/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8212 {
8213 { 0, 0, 0, 0 },
8214 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8215 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80b00 }
8216 },
8217/* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
8218 {
8219 { 0, 0, 0, 0 },
8220 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
8221 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82b00 }
8222 },
8223/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8224 {
8225 { 0, 0, 0, 0 },
8226 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8227 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08b00 }
8228 },
8229/* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
8230 {
8231 { 0, 0, 0, 0 },
8232 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
8233 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0ab00 }
8234 },
8235/* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8236 {
8237 { 0, 0, 0, 0 },
8238 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8239 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00b00 }
8240 },
8241/* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
8242 {
8243 { 0, 0, 0, 0 },
8244 { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8245 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02b00 }
8246 },
8247/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8248 {
8249 { 0, 0, 0, 0 },
8250 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8251 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20b00 }
8252 },
8253/* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8254 {
8255 { 0, 0, 0, 0 },
8256 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8257 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22b00 }
8258 },
8259/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8260 {
8261 { 0, 0, 0, 0 },
8262 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8263 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40b00 }
8264 },
8265/* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8266 {
8267 { 0, 0, 0, 0 },
8268 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8269 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42b00 }
8270 },
8271/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8272 {
8273 { 0, 0, 0, 0 },
8274 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8275 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60b00 }
8276 },
8277/* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8278 {
8279 { 0, 0, 0, 0 },
8280 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8281 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62b00 }
8282 },
8283/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8284 {
8285 { 0, 0, 0, 0 },
8286 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
8287 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28b00 }
8288 },
8289/* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8290 {
8291 { 0, 0, 0, 0 },
8292 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
8293 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2ab00 }
8294 },
8295/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8296 {
8297 { 0, 0, 0, 0 },
8298 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
8299 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48b00 }
8300 },
8301/* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8302 {
8303 { 0, 0, 0, 0 },
8304 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
8305 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4ab00 }
8306 },
8307/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8308 {
8309 { 0, 0, 0, 0 },
8310 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
8311 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2cb00 }
8312 },
8313/* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8314 {
8315 { 0, 0, 0, 0 },
8316 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
8317 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2eb00 }
8318 },
8319/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8320 {
8321 { 0, 0, 0, 0 },
8322 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
8323 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4cb00 }
8324 },
8325/* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8326 {
8327 { 0, 0, 0, 0 },
8328 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
8329 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4eb00 }
8330 },
8331/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8332 {
8333 { 0, 0, 0, 0 },
8334 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
8335 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6cb00 }
8336 },
8337/* extz ${Dsp-24-u24},${Dsp-48-u16} */
8338 {
8339 { 0, 0, 0, 0 },
8340 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
8341 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6eb00 }
8342 },
8343/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8344 {
8345 { 0, 0, 0, 0 },
8346 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
8347 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68b00 }
8348 },
8349/* extz ${Dsp-24-u24},${Dsp-48-u24} */
8350 {
8351 { 0, 0, 0, 0 },
8352 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
8353 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6ab00 }
8354 },
8355/* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
8356 {
8357 { 0, 0, 0, 0 },
8358 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } },
8359 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c80b }
8360 },
8361/* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
8362 {
8363 { 0, 0, 0, 0 },
8364 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8365 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1880b }
8366 },
8367/* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
8368 {
8369 { 0, 0, 0, 0 },
8370 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } },
8371 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c08b }
8372 },
8373/* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
8374 {
8375 { 0, 0, 0, 0 },
8376 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8377 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1808b }
8378 },
8379/* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
8380 {
8381 { 0, 0, 0, 0 },
8382 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8383 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c00b }
8384 },
8385/* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
8386 {
8387 { 0, 0, 0, 0 },
8388 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8389 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1800b }
8390 },
8391/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8392 {
8393 { 0, 0, 0, 0 },
8394 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8395 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20b00 }
8396 },
8397/* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
8398 {
8399 { 0, 0, 0, 0 },
8400 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8401 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820b00 }
8402 },
8403/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8404 {
8405 { 0, 0, 0, 0 },
8406 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8407 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40b00 }
8408 },
8409/* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
8410 {
8411 { 0, 0, 0, 0 },
8412 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8413 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840b00 }
8414 },
8415/* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8416 {
8417 { 0, 0, 0, 0 },
8418 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8419 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60b00 }
8420 },
8421/* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
8422 {
8423 { 0, 0, 0, 0 },
8424 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8425 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860b00 }
8426 },
8427/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
8428 {
8429 { 0, 0, 0, 0 },
8430 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
8431 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28b00 }
8432 },
8433/* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
8434 {
8435 { 0, 0, 0, 0 },
8436 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
8437 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828b00 }
8438 },
8439/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
8440 {
8441 { 0, 0, 0, 0 },
8442 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
8443 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48b00 }
8444 },
8445/* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
8446 {
8447 { 0, 0, 0, 0 },
8448 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
8449 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848b00 }
8450 },
8451/* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
8452 {
8453 { 0, 0, 0, 0 },
8454 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
8455 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2cb00 }
8456 },
8457/* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
8458 {
8459 { 0, 0, 0, 0 },
8460 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
8461 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182cb00 }
8462 },
8463/* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
8464 {
8465 { 0, 0, 0, 0 },
8466 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
8467 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4cb00 }
8468 },
8469/* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
8470 {
8471 { 0, 0, 0, 0 },
8472 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
8473 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184cb00 }
8474 },
8475/* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
8476 {
8477 { 0, 0, 0, 0 },
8478 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
8479 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6cb00 }
8480 },
8481/* extz [$Src32AnPrefixed],${Dsp-24-u16} */
8482 {
8483 { 0, 0, 0, 0 },
8484 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
8485 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186cb00 }
8486 },
8487/* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
8488 {
8489 { 0, 0, 0, 0 },
8490 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
8491 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68b00 }
8492 },
8493/* extz [$Src32AnPrefixed],${Dsp-24-u24} */
8494 {
8495 { 0, 0, 0, 0 },
8496 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
8497 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868b00 }
8498 },
8499/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8500 {
8501 { 0, 0, 0, 0 },
8502 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8503 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980700 }
8504 },
8505/* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
8506 {
8507 { 0, 0, 0, 0 },
8508 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8509 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982700 }
8510 },
8511/* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
8512 {
8513 { 0, 0, 0, 0 },
8514 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8515 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983700 }
8516 },
8517/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8518 {
8519 { 0, 0, 0, 0 },
8520 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8521 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908700 }
8522 },
8523/* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
8524 {
8525 { 0, 0, 0, 0 },
8526 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8527 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190a700 }
8528 },
8529/* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
8530 {
8531 { 0, 0, 0, 0 },
8532 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8533 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190b700 }
8534 },
8535/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8536 {
8537 { 0, 0, 0, 0 },
8538 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8539 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900700 }
8540 },
8541/* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
8542 {
8543 { 0, 0, 0, 0 },
8544 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8545 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902700 }
8546 },
8547/* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
8548 {
8549 { 0, 0, 0, 0 },
8550 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8551 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903700 }
8552 },
8553/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
8554 {
8555 { 0, 0, 0, 0 },
8556 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8557 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920700 }
8558 },
8559/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8560 {
8561 { 0, 0, 0, 0 },
8562 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8563 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922700 }
8564 },
8565/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8566 {
8567 { 0, 0, 0, 0 },
8568 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8569 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923700 }
8570 },
8571/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
8572 {
8573 { 0, 0, 0, 0 },
8574 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8575 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940700 }
8576 },
8577/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8578 {
8579 { 0, 0, 0, 0 },
8580 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8581 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942700 }
8582 },
8583/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8584 {
8585 { 0, 0, 0, 0 },
8586 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8587 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943700 }
8588 },
8589/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
8590 {
8591 { 0, 0, 0, 0 },
8592 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8593 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960700 }
8594 },
8595/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8596 {
8597 { 0, 0, 0, 0 },
8598 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8599 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962700 }
8600 },
8601/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8602 {
8603 { 0, 0, 0, 0 },
8604 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8605 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963700 }
8606 },
8607/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8608 {
8609 { 0, 0, 0, 0 },
8610 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8611 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928700 }
8612 },
8613/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8614 {
8615 { 0, 0, 0, 0 },
8616 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8617 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192a700 }
8618 },
8619/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8620 {
8621 { 0, 0, 0, 0 },
8622 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8623 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192b700 }
8624 },
8625/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8626 {
8627 { 0, 0, 0, 0 },
8628 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8629 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948700 }
8630 },
8631/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8632 {
8633 { 0, 0, 0, 0 },
8634 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8635 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194a700 }
8636 },
8637/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8638 {
8639 { 0, 0, 0, 0 },
8640 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8641 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194b700 }
8642 },
8643/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8644 {
8645 { 0, 0, 0, 0 },
8646 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8647 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192c700 }
8648 },
8649/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8650 {
8651 { 0, 0, 0, 0 },
8652 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8653 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192e700 }
8654 },
8655/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8656 {
8657 { 0, 0, 0, 0 },
8658 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8659 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192f700 }
8660 },
8661/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8662 {
8663 { 0, 0, 0, 0 },
8664 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8665 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194c700 }
8666 },
8667/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8668 {
8669 { 0, 0, 0, 0 },
8670 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8671 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194e700 }
8672 },
8673/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8674 {
8675 { 0, 0, 0, 0 },
8676 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8677 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194f700 }
8678 },
8679/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8680 {
8681 { 0, 0, 0, 0 },
8682 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
8683 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196c700 }
8684 },
8685/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8686 {
8687 { 0, 0, 0, 0 },
8688 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8689 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196e700 }
8690 },
8691/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8692 {
8693 { 0, 0, 0, 0 },
8694 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8695 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196f700 }
8696 },
8697/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8698 {
8699 { 0, 0, 0, 0 },
8700 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
8701 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968700 }
8702 },
8703/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8704 {
8705 { 0, 0, 0, 0 },
8706 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8707 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196a700 }
8708 },
8709/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8710 {
8711 { 0, 0, 0, 0 },
8712 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8713 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196b700 }
8714 },
8715/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8716 {
8717 { 0, 0, 0, 0 },
8718 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8719 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80700 }
8720 },
8721/* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
8722 {
8723 { 0, 0, 0, 0 },
8724 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8725 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82700 }
8726 },
8727/* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
8728 {
8729 { 0, 0, 0, 0 },
8730 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8731 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83700 }
8732 },
8733/* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
8734 {
8735 { 0, 0, 0, 0 },
8736 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
8737 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83700 }
8738 },
8739/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8740 {
8741 { 0, 0, 0, 0 },
8742 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8743 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08700 }
8744 },
8745/* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
8746 {
8747 { 0, 0, 0, 0 },
8748 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8749 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0a700 }
8750 },
8751/* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
8752 {
8753 { 0, 0, 0, 0 },
8754 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8755 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0b700 }
8756 },
8757/* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
8758 {
8759 { 0, 0, 0, 0 },
8760 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
8761 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0b700 }
8762 },
8763/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8764 {
8765 { 0, 0, 0, 0 },
8766 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8767 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00700 }
8768 },
8769/* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8770 {
8771 { 0, 0, 0, 0 },
8772 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8773 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02700 }
8774 },
8775/* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8776 {
8777 { 0, 0, 0, 0 },
8778 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8779 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03700 }
8780 },
8781/* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
8782 {
8783 { 0, 0, 0, 0 },
8784 { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8785 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03700 }
8786 },
8787/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8788 {
8789 { 0, 0, 0, 0 },
8790 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8791 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20700 }
8792 },
8793/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8794 {
8795 { 0, 0, 0, 0 },
8796 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8797 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22700 }
8798 },
8799/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8800 {
8801 { 0, 0, 0, 0 },
8802 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8803 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23700 }
8804 },
8805/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8806 {
8807 { 0, 0, 0, 0 },
8808 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8809 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23700 }
8810 },
8811/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8812 {
8813 { 0, 0, 0, 0 },
8814 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8815 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40700 }
8816 },
8817/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8818 {
8819 { 0, 0, 0, 0 },
8820 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8821 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42700 }
8822 },
8823/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8824 {
8825 { 0, 0, 0, 0 },
8826 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8827 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43700 }
8828 },
8829/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8830 {
8831 { 0, 0, 0, 0 },
8832 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8833 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43700 }
8834 },
8835/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8836 {
8837 { 0, 0, 0, 0 },
8838 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8839 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60700 }
8840 },
8841/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8842 {
8843 { 0, 0, 0, 0 },
8844 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8845 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62700 }
8846 },
8847/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8848 {
8849 { 0, 0, 0, 0 },
8850 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8851 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63700 }
8852 },
8853/* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8854 {
8855 { 0, 0, 0, 0 },
8856 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8857 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63700 }
8858 },
8859/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8860 {
8861 { 0, 0, 0, 0 },
8862 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8863 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28700 }
8864 },
8865/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8866 {
8867 { 0, 0, 0, 0 },
8868 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8869 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2a700 }
8870 },
8871/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8872 {
8873 { 0, 0, 0, 0 },
8874 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8875 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2b700 }
8876 },
8877/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8878 {
8879 { 0, 0, 0, 0 },
8880 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8881 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2b700 }
8882 },
8883/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8884 {
8885 { 0, 0, 0, 0 },
8886 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8887 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48700 }
8888 },
8889/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8890 {
8891 { 0, 0, 0, 0 },
8892 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8893 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4a700 }
8894 },
8895/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8896 {
8897 { 0, 0, 0, 0 },
8898 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8899 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4b700 }
8900 },
8901/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8902 {
8903 { 0, 0, 0, 0 },
8904 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8905 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4b700 }
8906 },
8907/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8908 {
8909 { 0, 0, 0, 0 },
8910 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8911 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2c700 }
8912 },
8913/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8914 {
8915 { 0, 0, 0, 0 },
8916 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8917 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2e700 }
8918 },
8919/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8920 {
8921 { 0, 0, 0, 0 },
8922 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8923 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2f700 }
8924 },
8925/* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8926 {
8927 { 0, 0, 0, 0 },
8928 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8929 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2f700 }
8930 },
8931/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8932 {
8933 { 0, 0, 0, 0 },
8934 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8935 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4c700 }
8936 },
8937/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8938 {
8939 { 0, 0, 0, 0 },
8940 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8941 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4e700 }
8942 },
8943/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8944 {
8945 { 0, 0, 0, 0 },
8946 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8947 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4f700 }
8948 },
8949/* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8950 {
8951 { 0, 0, 0, 0 },
8952 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8953 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4f700 }
8954 },
8955/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8956 {
8957 { 0, 0, 0, 0 },
8958 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
8959 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6c700 }
8960 },
8961/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8962 {
8963 { 0, 0, 0, 0 },
8964 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8965 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6e700 }
8966 },
8967/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8968 {
8969 { 0, 0, 0, 0 },
8970 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8971 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6f700 }
8972 },
8973/* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
8974 {
8975 { 0, 0, 0, 0 },
8976 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
8977 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6f700 }
8978 },
8979/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8980 {
8981 { 0, 0, 0, 0 },
8982 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
8983 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68700 }
8984 },
8985/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8986 {
8987 { 0, 0, 0, 0 },
8988 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8989 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6a700 }
8990 },
8991/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8992 {
8993 { 0, 0, 0, 0 },
8994 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8995 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6b700 }
8996 },
8997/* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
8998 {
8999 { 0, 0, 0, 0 },
9000 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
9001 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6b700 }
9002 },
9003/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
9004 {
9005 { 0, 0, 0, 0 },
9006 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
9007 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80700 }
9008 },
9009/* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
9010 {
9011 { 0, 0, 0, 0 },
9012 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
9013 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82700 }
9014 },
9015/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
9016 {
9017 { 0, 0, 0, 0 },
9018 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
9019 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08700 }
9020 },
9021/* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
9022 {
9023 { 0, 0, 0, 0 },
9024 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
9025 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0a700 }
9026 },
9027/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
9028 {
9029 { 0, 0, 0, 0 },
9030 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9031 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00700 }
9032 },
9033/* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
9034 {
9035 { 0, 0, 0, 0 },
9036 { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9037 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02700 }
9038 },
9039/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
9040 {
9041 { 0, 0, 0, 0 },
9042 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9043 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20700 }
9044 },
9045/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
9046 {
9047 { 0, 0, 0, 0 },
9048 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9049 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22700 }
9050 },
9051/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
9052 {
9053 { 0, 0, 0, 0 },
9054 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9055 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40700 }
9056 },
9057/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
9058 {
9059 { 0, 0, 0, 0 },
9060 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9061 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42700 }
9062 },
9063/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
9064 {
9065 { 0, 0, 0, 0 },
9066 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9067 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60700 }
9068 },
9069/* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
9070 {
9071 { 0, 0, 0, 0 },
9072 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9073 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62700 }
9074 },
9075/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
9076 {
9077 { 0, 0, 0, 0 },
9078 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
9079 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28700 }
9080 },
9081/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
9082 {
9083 { 0, 0, 0, 0 },
9084 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
9085 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2a700 }
9086 },
9087/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
9088 {
9089 { 0, 0, 0, 0 },
9090 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
9091 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48700 }
9092 },
9093/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
9094 {
9095 { 0, 0, 0, 0 },
9096 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
9097 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4a700 }
9098 },
9099/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
9100 {
9101 { 0, 0, 0, 0 },
9102 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
9103 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2c700 }
9104 },
9105/* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
9106 {
9107 { 0, 0, 0, 0 },
9108 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
9109 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2e700 }
9110 },
9111/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
9112 {
9113 { 0, 0, 0, 0 },
9114 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
9115 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4c700 }
9116 },
9117/* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
9118 {
9119 { 0, 0, 0, 0 },
9120 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
9121 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4e700 }
9122 },
9123/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
9124 {
9125 { 0, 0, 0, 0 },
9126 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
9127 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6c700 }
9128 },
9129/* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
9130 {
9131 { 0, 0, 0, 0 },
9132 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
9133 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6e700 }
9134 },
9135/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
9136 {
9137 { 0, 0, 0, 0 },
9138 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
9139 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68700 }
9140 },
9141/* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
9142 {
9143 { 0, 0, 0, 0 },
9144 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
9145 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6a700 }
9146 },
9147/* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
9148 {
9149 { 0, 0, 0, 0 },
9150 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } },
9151 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c807 }
9152 },
9153/* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
9154 {
9155 { 0, 0, 0, 0 },
9156 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
9157 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x18807 }
9158 },
9159/* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
9160 {
9161 { 0, 0, 0, 0 },
9162 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } },
9163 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c087 }
9164 },
9165/* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
9166 {
9167 { 0, 0, 0, 0 },
9168 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
9169 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x18087 }
9170 },
9171/* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
9172 {
9173 { 0, 0, 0, 0 },
9174 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9175 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c007 }
9176 },
9177/* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
9178 {
9179 { 0, 0, 0, 0 },
9180 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9181 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x18007 }
9182 },
9183/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9184 {
9185 { 0, 0, 0, 0 },
9186 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9187 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20700 }
9188 },
9189/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
9190 {
9191 { 0, 0, 0, 0 },
9192 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9193 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820700 }
9194 },
9195/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9196 {
9197 { 0, 0, 0, 0 },
9198 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9199 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40700 }
9200 },
9201/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
9202 {
9203 { 0, 0, 0, 0 },
9204 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9205 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840700 }
9206 },
9207/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9208 {
9209 { 0, 0, 0, 0 },
9210 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9211 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60700 }
9212 },
9213/* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
9214 {
9215 { 0, 0, 0, 0 },
9216 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9217 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860700 }
9218 },
9219/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
9220 {
9221 { 0, 0, 0, 0 },
9222 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9223 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28700 }
9224 },
9225/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
9226 {
9227 { 0, 0, 0, 0 },
9228 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9229 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828700 }
9230 },
9231/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
9232 {
9233 { 0, 0, 0, 0 },
9234 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9235 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48700 }
9236 },
9237/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
9238 {
9239 { 0, 0, 0, 0 },
9240 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9241 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848700 }
9242 },
9243/* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
9244 {
9245 { 0, 0, 0, 0 },
9246 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9247 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2c700 }
9248 },
9249/* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
9250 {
9251 { 0, 0, 0, 0 },
9252 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9253 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182c700 }
9254 },
9255/* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
9256 {
9257 { 0, 0, 0, 0 },
9258 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9259 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4c700 }
9260 },
9261/* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
9262 {
9263 { 0, 0, 0, 0 },
9264 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9265 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184c700 }
9266 },
9267/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
9268 {
9269 { 0, 0, 0, 0 },
9270 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
9271 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6c700 }
9272 },
9273/* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
9274 {
9275 { 0, 0, 0, 0 },
9276 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
9277 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186c700 }
9278 },
9279/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
9280 {
9281 { 0, 0, 0, 0 },
9282 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
9283 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68700 }
9284 },
9285/* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
9286 {
9287 { 0, 0, 0, 0 },
9288 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
9289 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868700 }
9290 },
9291/* exts.w $Dst32RnExtUnprefixedHI */
9292 {
9293 { 0, 0, 0, 0 },
9294 { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDHI), 0 } },
9295 & ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI, { 0xc99e }
9296 },
9297/* exts.w $Dst32AnUnprefixedSI */
9298 {
9299 { 0, 0, 0, 0 },
9300 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
9301 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc19e }
9302 },
9303/* exts.w [$Dst32AnExtUnprefixed] */
9304 {
9305 { 0, 0, 0, 0 },
9306 { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9307 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI, { 0xc11e }
9308 },
9309/* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
9310 {
9311 { 0, 0, 0, 0 },
9312 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9313 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI, { 0xc31e00 }
9314 },
9315/* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
9316 {
9317 { 0, 0, 0, 0 },
9318 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9319 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI, { 0xc51e0000 }
9320 },
9321/* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
9322 {
9323 { 0, 0, 0, 0 },
9324 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9325 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI, { 0xc71e0000 }
9326 },
9327/* exts.w ${Dsp-16-u8}[sb] */
9328 {
9329 { 0, 0, 0, 0 },
9330 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9331 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI, { 0xc39e00 }
9332 },
9333/* exts.w ${Dsp-16-u16}[sb] */
9334 {
9335 { 0, 0, 0, 0 },
9336 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9337 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI, { 0xc59e0000 }
9338 },
9339/* exts.w ${Dsp-16-s8}[fb] */
9340 {
9341 { 0, 0, 0, 0 },
9342 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9343 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI, { 0xc3de00 }
9344 },
9345/* exts.w ${Dsp-16-s16}[fb] */
9346 {
9347 { 0, 0, 0, 0 },
9348 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
9349 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI, { 0xc5de0000 }
9350 },
9351/* exts.w ${Dsp-16-u16} */
9352 {
9353 { 0, 0, 0, 0 },
9354 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9355 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI, { 0xc7de0000 }
9356 },
9357/* exts.w ${Dsp-16-u24} */
9358 {
9359 { 0, 0, 0, 0 },
9360 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
9361 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI, { 0xc79e0000 }
9362 },
9363/* exts.b $Dst32RnExtUnprefixedQI */
9364 {
9365 { 0, 0, 0, 0 },
9366 { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDQI), 0 } },
9367 & ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI, { 0xc89e }
9368 },
9369/* exts.b $Dst32AnUnprefixedHI */
9370 {
9371 { 0, 0, 0, 0 },
9372 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
9373 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc09e }
9374 },
9375/* exts.b [$Dst32AnExtUnprefixed] */
9376 {
9377 { 0, 0, 0, 0 },
9378 { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9379 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI, { 0xc01e }
9380 },
9381/* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
9382 {
9383 { 0, 0, 0, 0 },
9384 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9385 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI, { 0xc21e00 }
9386 },
9387/* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
9388 {
9389 { 0, 0, 0, 0 },
9390 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9391 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI, { 0xc41e0000 }
9392 },
9393/* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
9394 {
9395 { 0, 0, 0, 0 },
9396 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9397 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI, { 0xc61e0000 }
9398 },
9399/* exts.b ${Dsp-16-u8}[sb] */
9400 {
9401 { 0, 0, 0, 0 },
9402 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9403 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI, { 0xc29e00 }
9404 },
9405/* exts.b ${Dsp-16-u16}[sb] */
9406 {
9407 { 0, 0, 0, 0 },
9408 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9409 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI, { 0xc49e0000 }
9410 },
9411/* exts.b ${Dsp-16-s8}[fb] */
9412 {
9413 { 0, 0, 0, 0 },
9414 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9415 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI, { 0xc2de00 }
9416 },
9417/* exts.b ${Dsp-16-s16}[fb] */
9418 {
9419 { 0, 0, 0, 0 },
9420 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
9421 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI, { 0xc4de0000 }
9422 },
9423/* exts.b ${Dsp-16-u16} */
9424 {
9425 { 0, 0, 0, 0 },
9426 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9427 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI, { 0xc6de0000 }
9428 },
9429/* exts.b ${Dsp-16-u24} */
9430 {
9431 { 0, 0, 0, 0 },
9432 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
9433 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI, { 0xc69e0000 }
9434 },
9435/* exts.b $Dst16RnExtQI */
9436 {
9437 { 0, 0, 0, 0 },
9438 { { MNEM, ' ', OP (DST16RNEXTQI), 0 } },
9439 & ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI, { 0x7c60 }
9440 },
9441/* exts.b [$Dst16An] */
9442 {
9443 { 0, 0, 0, 0 },
9444 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
9445 & ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI, { 0x7c66 }
9446 },
9447/* exts.b ${Dsp-16-u8}[$Dst16An] */
9448 {
9449 { 0, 0, 0, 0 },
9450 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
9451 & ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI, { 0x7c6800 }
9452 },
9453/* exts.b ${Dsp-16-u16}[$Dst16An] */
9454 {
9455 { 0, 0, 0, 0 },
9456 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
9457 & ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI, { 0x7c6c0000 }
9458 },
9459/* exts.b ${Dsp-16-u8}[sb] */
9460 {
9461 { 0, 0, 0, 0 },
9462 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9463 & ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI, { 0x7c6a00 }
9464 },
9465/* exts.b ${Dsp-16-u16}[sb] */
9466 {
9467 { 0, 0, 0, 0 },
9468 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9469 & ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI, { 0x7c6e0000 }
9470 },
9471/* exts.b ${Dsp-16-s8}[fb] */
9472 {
9473 { 0, 0, 0, 0 },
9474 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9475 & ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI, { 0x7c6b00 }
9476 },
9477/* exts.b ${Dsp-16-u16} */
9478 {
9479 { 0, 0, 0, 0 },
9480 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9481 & ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI, { 0x7c6f0000 }
9482 },
9483/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
9484 {
9485 { 0, 0, 0, 0 },
9486 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9487 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990900 }
9488 },
9489/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
9490 {
9491 { 0, 0, 0, 0 },
9492 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9493 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992900 }
9494 },
9495/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
9496 {
9497 { 0, 0, 0, 0 },
9498 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9499 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993900 }
9500 },
9501/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
9502 {
9503 { 0, 0, 0, 0 },
9504 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9505 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918900 }
9506 },
9507/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
9508 {
9509 { 0, 0, 0, 0 },
9510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9511 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a900 }
9512 },
9513/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
9514 {
9515 { 0, 0, 0, 0 },
9516 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9517 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b900 }
9518 },
9519/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
9520 {
9521 { 0, 0, 0, 0 },
9522 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9523 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910900 }
9524 },
9525/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
9526 {
9527 { 0, 0, 0, 0 },
9528 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9529 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912900 }
9530 },
9531/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
9532 {
9533 { 0, 0, 0, 0 },
9534 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9535 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913900 }
9536 },
9537/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9538 {
9539 { 0, 0, 0, 0 },
9540 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9541 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93090000 }
9542 },
9543/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9544 {
9545 { 0, 0, 0, 0 },
9546 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9547 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93290000 }
9548 },
9549/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9550 {
9551 { 0, 0, 0, 0 },
9552 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9553 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93390000 }
9554 },
9555/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9556 {
9557 { 0, 0, 0, 0 },
9558 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9559 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95090000 }
9560 },
9561/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9562 {
9563 { 0, 0, 0, 0 },
9564 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9565 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95290000 }
9566 },
9567/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9568 {
9569 { 0, 0, 0, 0 },
9570 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9571 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95390000 }
9572 },
9573/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9574 {
9575 { 0, 0, 0, 0 },
9576 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9577 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97090000 }
9578 },
9579/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9580 {
9581 { 0, 0, 0, 0 },
9582 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9583 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97290000 }
9584 },
9585/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9586 {
9587 { 0, 0, 0, 0 },
9588 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9589 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97390000 }
9590 },
9591/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
9592 {
9593 { 0, 0, 0, 0 },
9594 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9595 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93890000 }
9596 },
9597/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9598 {
9599 { 0, 0, 0, 0 },
9600 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9601 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a90000 }
9602 },
9603/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9604 {
9605 { 0, 0, 0, 0 },
9606 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9607 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b90000 }
9608 },
9609/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
9610 {
9611 { 0, 0, 0, 0 },
9612 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9613 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95890000 }
9614 },
9615/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9616 {
9617 { 0, 0, 0, 0 },
9618 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9619 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a90000 }
9620 },
9621/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9622 {
9623 { 0, 0, 0, 0 },
9624 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9625 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b90000 }
9626 },
9627/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
9628 {
9629 { 0, 0, 0, 0 },
9630 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9631 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c90000 }
9632 },
9633/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9634 {
9635 { 0, 0, 0, 0 },
9636 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9637 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e90000 }
9638 },
9639/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9640 {
9641 { 0, 0, 0, 0 },
9642 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9643 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f90000 }
9644 },
9645/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
9646 {
9647 { 0, 0, 0, 0 },
9648 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9649 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c90000 }
9650 },
9651/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
9652 {
9653 { 0, 0, 0, 0 },
9654 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9655 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e90000 }
9656 },
9657/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
9658 {
9659 { 0, 0, 0, 0 },
9660 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9661 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f90000 }
9662 },
9663/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
9664 {
9665 { 0, 0, 0, 0 },
9666 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
9667 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c90000 }
9668 },
9669/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9670 {
9671 { 0, 0, 0, 0 },
9672 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
9673 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e90000 }
9674 },
9675/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9676 {
9677 { 0, 0, 0, 0 },
9678 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
9679 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f90000 }
9680 },
9681/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
9682 {
9683 { 0, 0, 0, 0 },
9684 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
9685 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97890000 }
9686 },
9687/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
9688 {
9689 { 0, 0, 0, 0 },
9690 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
9691 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a90000 }
9692 },
9693/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
9694 {
9695 { 0, 0, 0, 0 },
9696 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
9697 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b90000 }
9698 },
9699/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
9700 {
9701 { 0, 0, 0, 0 },
9702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9703 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9090000 }
9704 },
9705/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
9706 {
9707 { 0, 0, 0, 0 },
9708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9709 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9290000 }
9710 },
9711/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
9712 {
9713 { 0, 0, 0, 0 },
9714 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9715 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9390000 }
9716 },
9717/* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
9718 {
9719 { 0, 0, 0, 0 },
9720 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9721 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9390000 }
9722 },
9723/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
9724 {
9725 { 0, 0, 0, 0 },
9726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9727 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1890000 }
9728 },
9729/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
9730 {
9731 { 0, 0, 0, 0 },
9732 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9733 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a90000 }
9734 },
9735/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
9736 {
9737 { 0, 0, 0, 0 },
9738 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9739 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b90000 }
9740 },
9741/* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
9742 {
9743 { 0, 0, 0, 0 },
9744 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9745 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b90000 }
9746 },
9747/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
9748 {
9749 { 0, 0, 0, 0 },
9750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9751 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1090000 }
9752 },
9753/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
9754 {
9755 { 0, 0, 0, 0 },
9756 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9757 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1290000 }
9758 },
9759/* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
9760 {
9761 { 0, 0, 0, 0 },
9762 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9763 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1390000 }
9764 },
9765/* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
9766 {
9767 { 0, 0, 0, 0 },
9768 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9769 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1390000 }
9770 },
9771/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9772 {
9773 { 0, 0, 0, 0 },
9774 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9775 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3090000 }
9776 },
9777/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9778 {
9779 { 0, 0, 0, 0 },
9780 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9781 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3290000 }
9782 },
9783/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9784 {
9785 { 0, 0, 0, 0 },
9786 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9787 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3390000 }
9788 },
9789/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
9790 {
9791 { 0, 0, 0, 0 },
9792 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9793 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3390000 }
9794 },
9795/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9796 {
9797 { 0, 0, 0, 0 },
9798 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9799 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5090000 }
9800 },
9801/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9802 {
9803 { 0, 0, 0, 0 },
9804 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9805 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5290000 }
9806 },
9807/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9808 {
9809 { 0, 0, 0, 0 },
9810 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9811 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5390000 }
9812 },
9813/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
9814 {
9815 { 0, 0, 0, 0 },
9816 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9817 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5390000 }
9818 },
9819/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
9820 {
9821 { 0, 0, 0, 0 },
9822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9823 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7090000 }
9824 },
9825/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
9826 {
9827 { 0, 0, 0, 0 },
9828 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9829 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7290000 }
9830 },
9831/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
9832 {
9833 { 0, 0, 0, 0 },
9834 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9835 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7390000 }
9836 },
9837/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
9838 {
9839 { 0, 0, 0, 0 },
9840 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9841 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7390000 }
9842 },
9843/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
9844 {
9845 { 0, 0, 0, 0 },
9846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
9847 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3890000 }
9848 },
9849/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9850 {
9851 { 0, 0, 0, 0 },
9852 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
9853 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a90000 }
9854 },
9855/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
9856 {
9857 { 0, 0, 0, 0 },
9858 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
9859 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b90000 }
9860 },
9861/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9862 {
9863 { 0, 0, 0, 0 },
9864 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
9865 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b90000 }
9866 },
9867/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
9868 {
9869 { 0, 0, 0, 0 },
9870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
9871 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5890000 }
9872 },
9873/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9874 {
9875 { 0, 0, 0, 0 },
9876 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
9877 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a90000 }
9878 },
9879/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
9880 {
9881 { 0, 0, 0, 0 },
9882 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
9883 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b90000 }
9884 },
9885/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9886 {
9887 { 0, 0, 0, 0 },
9888 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
9889 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b90000 }
9890 },
9891/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
9892 {
9893 { 0, 0, 0, 0 },
9894 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
9895 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c90000 }
9896 },
9897/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9898 {
9899 { 0, 0, 0, 0 },
9900 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
9901 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e90000 }
9902 },
9903/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
9904 {
9905 { 0, 0, 0, 0 },
9906 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
9907 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f90000 }
9908 },
9909/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9910 {
9911 { 0, 0, 0, 0 },
9912 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
9913 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f90000 }
9914 },
9915/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
9916 {
9917 { 0, 0, 0, 0 },
9918 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
9919 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c90000 }
9920 },
9921/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
9922 {
9923 { 0, 0, 0, 0 },
9924 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
9925 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e90000 }
9926 },
9927/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
9928 {
9929 { 0, 0, 0, 0 },
9930 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
9931 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f90000 }
9932 },
9933/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
9934 {
9935 { 0, 0, 0, 0 },
9936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
9937 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f90000 }
9938 },
9939/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
9940 {
9941 { 0, 0, 0, 0 },
9942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
9943 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c90000 }
9944 },
9945/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9946 {
9947 { 0, 0, 0, 0 },
9948 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
9949 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e90000 }
9950 },
9951/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
9952 {
9953 { 0, 0, 0, 0 },
9954 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
9955 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f90000 }
9956 },
9957/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
9958 {
9959 { 0, 0, 0, 0 },
9960 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
9961 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f90000 }
9962 },
9963/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
9964 {
9965 { 0, 0, 0, 0 },
9966 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
9967 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7890000 }
9968 },
9969/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
9970 {
9971 { 0, 0, 0, 0 },
9972 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
9973 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a90000 }
9974 },
9975/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
9976 {
9977 { 0, 0, 0, 0 },
9978 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
9979 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b90000 }
9980 },
9981/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
9982 {
9983 { 0, 0, 0, 0 },
9984 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
9985 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b90000 }
9986 },
9987/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
9988 {
9989 { 0, 0, 0, 0 },
9990 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9991 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9090000 }
9992 },
9993/* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
9994 {
9995 { 0, 0, 0, 0 },
9996 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9997 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9290000 }
9998 },
9999/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
10000 {
10001 { 0, 0, 0, 0 },
10002 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10003 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1890000 }
10004 },
10005/* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
10006 {
10007 { 0, 0, 0, 0 },
10008 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10009 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a90000 }
10010 },
10011/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10012 {
10013 { 0, 0, 0, 0 },
10014 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10015 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1090000 }
10016 },
10017/* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10018 {
10019 { 0, 0, 0, 0 },
10020 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10021 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1290000 }
10022 },
10023/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10024 {
10025 { 0, 0, 0, 0 },
10026 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10027 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3090000 }
10028 },
10029/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10030 {
10031 { 0, 0, 0, 0 },
10032 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10033 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3290000 }
10034 },
10035/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10036 {
10037 { 0, 0, 0, 0 },
10038 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10039 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5090000 }
10040 },
10041/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10042 {
10043 { 0, 0, 0, 0 },
10044 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10045 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5290000 }
10046 },
10047/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10048 {
10049 { 0, 0, 0, 0 },
10050 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10051 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7090000 }
10052 },
10053/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10054 {
10055 { 0, 0, 0, 0 },
10056 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10057 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7290000 }
10058 },
10059/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10060 {
10061 { 0, 0, 0, 0 },
10062 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10063 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3890000 }
10064 },
10065/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10066 {
10067 { 0, 0, 0, 0 },
10068 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10069 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a90000 }
10070 },
10071/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10072 {
10073 { 0, 0, 0, 0 },
10074 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10075 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5890000 }
10076 },
10077/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10078 {
10079 { 0, 0, 0, 0 },
10080 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10081 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a90000 }
10082 },
10083/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10084 {
10085 { 0, 0, 0, 0 },
10086 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10087 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c90000 }
10088 },
10089/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10090 {
10091 { 0, 0, 0, 0 },
10092 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10093 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e90000 }
10094 },
10095/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10096 {
10097 { 0, 0, 0, 0 },
10098 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10099 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c90000 }
10100 },
10101/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10102 {
10103 { 0, 0, 0, 0 },
10104 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10105 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e90000 }
10106 },
10107/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10108 {
10109 { 0, 0, 0, 0 },
10110 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
10111 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c90000 }
10112 },
10113/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
10114 {
10115 { 0, 0, 0, 0 },
10116 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
10117 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e90000 }
10118 },
10119/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10120 {
10121 { 0, 0, 0, 0 },
10122 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
10123 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7890000 }
10124 },
10125/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
10126 {
10127 { 0, 0, 0, 0 },
10128 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
10129 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a90000 }
10130 },
10131/* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
10132 {
10133 { 0, 0, 0, 0 },
10134 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10135 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc909 }
10136 },
10137/* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
10138 {
10139 { 0, 0, 0, 0 },
10140 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10141 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8929 }
10142 },
10143/* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
10144 {
10145 { 0, 0, 0, 0 },
10146 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10147 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8909 }
10148 },
10149/* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
10150 {
10151 { 0, 0, 0, 0 },
10152 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10153 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc189 }
10154 },
10155/* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
10156 {
10157 { 0, 0, 0, 0 },
10158 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10159 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a9 }
10160 },
10161/* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
10162 {
10163 { 0, 0, 0, 0 },
10164 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10165 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8189 }
10166 },
10167/* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
10168 {
10169 { 0, 0, 0, 0 },
10170 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10171 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc109 }
10172 },
10173/* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
10174 {
10175 { 0, 0, 0, 0 },
10176 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10177 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8129 }
10178 },
10179/* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10180 {
10181 { 0, 0, 0, 0 },
10182 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10183 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8109 }
10184 },
10185/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10186 {
10187 { 0, 0, 0, 0 },
10188 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10189 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30900 }
10190 },
10191/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10192 {
10193 { 0, 0, 0, 0 },
10194 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10195 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832900 }
10196 },
10197/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10198 {
10199 { 0, 0, 0, 0 },
10200 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10201 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830900 }
10202 },
10203/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10204 {
10205 { 0, 0, 0, 0 },
10206 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10207 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5090000 }
10208 },
10209/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10210 {
10211 { 0, 0, 0, 0 },
10212 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10213 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85290000 }
10214 },
10215/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10216 {
10217 { 0, 0, 0, 0 },
10218 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10219 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85090000 }
10220 },
10221/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10222 {
10223 { 0, 0, 0, 0 },
10224 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10225 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7090000 }
10226 },
10227/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10228 {
10229 { 0, 0, 0, 0 },
10230 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10231 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87290000 }
10232 },
10233/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10234 {
10235 { 0, 0, 0, 0 },
10236 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10237 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87090000 }
10238 },
10239/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
10240 {
10241 { 0, 0, 0, 0 },
10242 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10243 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38900 }
10244 },
10245/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
10246 {
10247 { 0, 0, 0, 0 },
10248 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10249 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a900 }
10250 },
10251/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10252 {
10253 { 0, 0, 0, 0 },
10254 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10255 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838900 }
10256 },
10257/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
10258 {
10259 { 0, 0, 0, 0 },
10260 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10261 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5890000 }
10262 },
10263/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
10264 {
10265 { 0, 0, 0, 0 },
10266 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10267 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a90000 }
10268 },
10269/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10270 {
10271 { 0, 0, 0, 0 },
10272 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10273 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85890000 }
10274 },
10275/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
10276 {
10277 { 0, 0, 0, 0 },
10278 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10279 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c900 }
10280 },
10281/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
10282 {
10283 { 0, 0, 0, 0 },
10284 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10285 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e900 }
10286 },
10287/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10288 {
10289 { 0, 0, 0, 0 },
10290 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10291 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c900 }
10292 },
10293/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
10294 {
10295 { 0, 0, 0, 0 },
10296 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10297 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c90000 }
10298 },
10299/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
10300 {
10301 { 0, 0, 0, 0 },
10302 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10303 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e90000 }
10304 },
10305/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10306 {
10307 { 0, 0, 0, 0 },
10308 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10309 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c90000 }
10310 },
10311/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
10312 {
10313 { 0, 0, 0, 0 },
10314 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
10315 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c90000 }
10316 },
10317/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
10318 {
10319 { 0, 0, 0, 0 },
10320 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
10321 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e90000 }
10322 },
10323/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10324 {
10325 { 0, 0, 0, 0 },
10326 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
10327 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c90000 }
10328 },
10329/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
10330 {
10331 { 0, 0, 0, 0 },
10332 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
10333 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7890000 }
10334 },
10335/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
10336 {
10337 { 0, 0, 0, 0 },
10338 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
10339 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a90000 }
10340 },
10341/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10342 {
10343 { 0, 0, 0, 0 },
10344 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
10345 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87890000 }
10346 },
10347/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
10348 {
10349 { 0, 0, 0, 0 },
10350 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10351 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980900 }
10352 },
10353/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
10354 {
10355 { 0, 0, 0, 0 },
10356 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10357 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982900 }
10358 },
10359/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
10360 {
10361 { 0, 0, 0, 0 },
10362 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10363 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983900 }
10364 },
10365/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
10366 {
10367 { 0, 0, 0, 0 },
10368 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10369 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908900 }
10370 },
10371/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
10372 {
10373 { 0, 0, 0, 0 },
10374 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10375 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a900 }
10376 },
10377/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
10378 {
10379 { 0, 0, 0, 0 },
10380 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10381 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b900 }
10382 },
10383/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10384 {
10385 { 0, 0, 0, 0 },
10386 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10387 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900900 }
10388 },
10389/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10390 {
10391 { 0, 0, 0, 0 },
10392 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10393 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902900 }
10394 },
10395/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10396 {
10397 { 0, 0, 0, 0 },
10398 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10399 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903900 }
10400 },
10401/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10402 {
10403 { 0, 0, 0, 0 },
10404 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10405 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92090000 }
10406 },
10407/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10408 {
10409 { 0, 0, 0, 0 },
10410 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10411 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92290000 }
10412 },
10413/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10414 {
10415 { 0, 0, 0, 0 },
10416 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10417 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92390000 }
10418 },
10419/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10420 {
10421 { 0, 0, 0, 0 },
10422 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10423 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94090000 }
10424 },
10425/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10426 {
10427 { 0, 0, 0, 0 },
10428 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10429 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94290000 }
10430 },
10431/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10432 {
10433 { 0, 0, 0, 0 },
10434 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10435 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94390000 }
10436 },
10437/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10438 {
10439 { 0, 0, 0, 0 },
10440 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10441 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96090000 }
10442 },
10443/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10444 {
10445 { 0, 0, 0, 0 },
10446 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10447 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96290000 }
10448 },
10449/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10450 {
10451 { 0, 0, 0, 0 },
10452 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10453 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96390000 }
10454 },
10455/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10456 {
10457 { 0, 0, 0, 0 },
10458 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10459 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92890000 }
10460 },
10461/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10462 {
10463 { 0, 0, 0, 0 },
10464 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10465 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a90000 }
10466 },
10467/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10468 {
10469 { 0, 0, 0, 0 },
10470 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10471 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b90000 }
10472 },
10473/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10474 {
10475 { 0, 0, 0, 0 },
10476 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10477 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94890000 }
10478 },
10479/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10480 {
10481 { 0, 0, 0, 0 },
10482 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10483 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a90000 }
10484 },
10485/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10486 {
10487 { 0, 0, 0, 0 },
10488 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10489 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b90000 }
10490 },
10491/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10492 {
10493 { 0, 0, 0, 0 },
10494 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10495 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c90000 }
10496 },
10497/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10498 {
10499 { 0, 0, 0, 0 },
10500 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10501 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e90000 }
10502 },
10503/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10504 {
10505 { 0, 0, 0, 0 },
10506 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10507 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f90000 }
10508 },
10509/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10510 {
10511 { 0, 0, 0, 0 },
10512 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10513 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c90000 }
10514 },
10515/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10516 {
10517 { 0, 0, 0, 0 },
10518 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10519 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e90000 }
10520 },
10521/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10522 {
10523 { 0, 0, 0, 0 },
10524 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10525 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f90000 }
10526 },
10527/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10528 {
10529 { 0, 0, 0, 0 },
10530 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
10531 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c90000 }
10532 },
10533/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10534 {
10535 { 0, 0, 0, 0 },
10536 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
10537 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e90000 }
10538 },
10539/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10540 {
10541 { 0, 0, 0, 0 },
10542 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
10543 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f90000 }
10544 },
10545/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10546 {
10547 { 0, 0, 0, 0 },
10548 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
10549 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96890000 }
10550 },
10551/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10552 {
10553 { 0, 0, 0, 0 },
10554 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
10555 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a90000 }
10556 },
10557/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10558 {
10559 { 0, 0, 0, 0 },
10560 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
10561 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b90000 }
10562 },
10563/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
10564 {
10565 { 0, 0, 0, 0 },
10566 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10567 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8090000 }
10568 },
10569/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
10570 {
10571 { 0, 0, 0, 0 },
10572 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10573 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8290000 }
10574 },
10575/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
10576 {
10577 { 0, 0, 0, 0 },
10578 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10579 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8390000 }
10580 },
10581/* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
10582 {
10583 { 0, 0, 0, 0 },
10584 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10585 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8390000 }
10586 },
10587/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
10588 {
10589 { 0, 0, 0, 0 },
10590 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10591 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0890000 }
10592 },
10593/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
10594 {
10595 { 0, 0, 0, 0 },
10596 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10597 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a90000 }
10598 },
10599/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
10600 {
10601 { 0, 0, 0, 0 },
10602 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10603 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b90000 }
10604 },
10605/* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
10606 {
10607 { 0, 0, 0, 0 },
10608 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10609 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b90000 }
10610 },
10611/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10612 {
10613 { 0, 0, 0, 0 },
10614 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10615 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0090000 }
10616 },
10617/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10618 {
10619 { 0, 0, 0, 0 },
10620 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10621 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0290000 }
10622 },
10623/* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10624 {
10625 { 0, 0, 0, 0 },
10626 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10627 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0390000 }
10628 },
10629/* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10630 {
10631 { 0, 0, 0, 0 },
10632 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10633 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0390000 }
10634 },
10635/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10636 {
10637 { 0, 0, 0, 0 },
10638 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10639 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2090000 }
10640 },
10641/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10642 {
10643 { 0, 0, 0, 0 },
10644 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10645 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2290000 }
10646 },
10647/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10648 {
10649 { 0, 0, 0, 0 },
10650 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10651 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2390000 }
10652 },
10653/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10654 {
10655 { 0, 0, 0, 0 },
10656 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10657 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2390000 }
10658 },
10659/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10660 {
10661 { 0, 0, 0, 0 },
10662 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10663 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4090000 }
10664 },
10665/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10666 {
10667 { 0, 0, 0, 0 },
10668 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10669 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4290000 }
10670 },
10671/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10672 {
10673 { 0, 0, 0, 0 },
10674 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10675 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4390000 }
10676 },
10677/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10678 {
10679 { 0, 0, 0, 0 },
10680 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10681 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4390000 }
10682 },
10683/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10684 {
10685 { 0, 0, 0, 0 },
10686 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10687 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6090000 }
10688 },
10689/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10690 {
10691 { 0, 0, 0, 0 },
10692 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10693 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6290000 }
10694 },
10695/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10696 {
10697 { 0, 0, 0, 0 },
10698 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10699 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6390000 }
10700 },
10701/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10702 {
10703 { 0, 0, 0, 0 },
10704 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10705 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6390000 }
10706 },
10707/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10708 {
10709 { 0, 0, 0, 0 },
10710 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10711 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2890000 }
10712 },
10713/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10714 {
10715 { 0, 0, 0, 0 },
10716 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10717 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a90000 }
10718 },
10719/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10720 {
10721 { 0, 0, 0, 0 },
10722 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10723 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b90000 }
10724 },
10725/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10726 {
10727 { 0, 0, 0, 0 },
10728 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10729 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b90000 }
10730 },
10731/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10732 {
10733 { 0, 0, 0, 0 },
10734 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10735 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4890000 }
10736 },
10737/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10738 {
10739 { 0, 0, 0, 0 },
10740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10741 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a90000 }
10742 },
10743/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10744 {
10745 { 0, 0, 0, 0 },
10746 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10747 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b90000 }
10748 },
10749/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10750 {
10751 { 0, 0, 0, 0 },
10752 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10753 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b90000 }
10754 },
10755/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10756 {
10757 { 0, 0, 0, 0 },
10758 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10759 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c90000 }
10760 },
10761/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10762 {
10763 { 0, 0, 0, 0 },
10764 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10765 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e90000 }
10766 },
10767/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10768 {
10769 { 0, 0, 0, 0 },
10770 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10771 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f90000 }
10772 },
10773/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10774 {
10775 { 0, 0, 0, 0 },
10776 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10777 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f90000 }
10778 },
10779/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10780 {
10781 { 0, 0, 0, 0 },
10782 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10783 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c90000 }
10784 },
10785/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10786 {
10787 { 0, 0, 0, 0 },
10788 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10789 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e90000 }
10790 },
10791/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10792 {
10793 { 0, 0, 0, 0 },
10794 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10795 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f90000 }
10796 },
10797/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10798 {
10799 { 0, 0, 0, 0 },
10800 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10801 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f90000 }
10802 },
10803/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10804 {
10805 { 0, 0, 0, 0 },
10806 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
10807 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c90000 }
10808 },
10809/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10810 {
10811 { 0, 0, 0, 0 },
10812 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10813 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e90000 }
10814 },
10815/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10816 {
10817 { 0, 0, 0, 0 },
10818 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10819 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f90000 }
10820 },
10821/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
10822 {
10823 { 0, 0, 0, 0 },
10824 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
10825 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f90000 }
10826 },
10827/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10828 {
10829 { 0, 0, 0, 0 },
10830 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
10831 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6890000 }
10832 },
10833/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10834 {
10835 { 0, 0, 0, 0 },
10836 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
10837 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a90000 }
10838 },
10839/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10840 {
10841 { 0, 0, 0, 0 },
10842 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
10843 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b90000 }
10844 },
10845/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
10846 {
10847 { 0, 0, 0, 0 },
10848 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
10849 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b90000 }
10850 },
10851/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
10852 {
10853 { 0, 0, 0, 0 },
10854 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10855 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8090000 }
10856 },
10857/* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
10858 {
10859 { 0, 0, 0, 0 },
10860 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10861 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8290000 }
10862 },
10863/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
10864 {
10865 { 0, 0, 0, 0 },
10866 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10867 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0890000 }
10868 },
10869/* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
10870 {
10871 { 0, 0, 0, 0 },
10872 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10873 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a90000 }
10874 },
10875/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10876 {
10877 { 0, 0, 0, 0 },
10878 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10879 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0090000 }
10880 },
10881/* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10882 {
10883 { 0, 0, 0, 0 },
10884 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10885 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0290000 }
10886 },
10887/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10888 {
10889 { 0, 0, 0, 0 },
10890 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10891 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2090000 }
10892 },
10893/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10894 {
10895 { 0, 0, 0, 0 },
10896 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10897 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2290000 }
10898 },
10899/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10900 {
10901 { 0, 0, 0, 0 },
10902 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10903 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4090000 }
10904 },
10905/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10906 {
10907 { 0, 0, 0, 0 },
10908 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10909 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4290000 }
10910 },
10911/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10912 {
10913 { 0, 0, 0, 0 },
10914 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10915 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6090000 }
10916 },
10917/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10918 {
10919 { 0, 0, 0, 0 },
10920 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10921 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6290000 }
10922 },
10923/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10924 {
10925 { 0, 0, 0, 0 },
10926 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10927 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2890000 }
10928 },
10929/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10930 {
10931 { 0, 0, 0, 0 },
10932 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10933 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a90000 }
10934 },
10935/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10936 {
10937 { 0, 0, 0, 0 },
10938 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10939 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4890000 }
10940 },
10941/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10942 {
10943 { 0, 0, 0, 0 },
10944 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10945 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a90000 }
10946 },
10947/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10948 {
10949 { 0, 0, 0, 0 },
10950 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10951 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c90000 }
10952 },
10953/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10954 {
10955 { 0, 0, 0, 0 },
10956 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10957 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e90000 }
10958 },
10959/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10960 {
10961 { 0, 0, 0, 0 },
10962 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10963 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c90000 }
10964 },
10965/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10966 {
10967 { 0, 0, 0, 0 },
10968 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10969 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e90000 }
10970 },
10971/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10972 {
10973 { 0, 0, 0, 0 },
10974 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
10975 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c90000 }
10976 },
10977/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
10978 {
10979 { 0, 0, 0, 0 },
10980 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
10981 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e90000 }
10982 },
10983/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10984 {
10985 { 0, 0, 0, 0 },
10986 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
10987 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6890000 }
10988 },
10989/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
10990 {
10991 { 0, 0, 0, 0 },
10992 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
10993 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a90000 }
10994 },
10995/* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
10996 {
10997 { 0, 0, 0, 0 },
10998 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10999 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc809 }
11000 },
11001/* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
11002 {
11003 { 0, 0, 0, 0 },
11004 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11005 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8829 }
11006 },
11007/* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
11008 {
11009 { 0, 0, 0, 0 },
11010 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11011 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8809 }
11012 },
11013/* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
11014 {
11015 { 0, 0, 0, 0 },
11016 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11017 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc089 }
11018 },
11019/* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
11020 {
11021 { 0, 0, 0, 0 },
11022 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11023 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a9 }
11024 },
11025/* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
11026 {
11027 { 0, 0, 0, 0 },
11028 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11029 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8089 }
11030 },
11031/* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
11032 {
11033 { 0, 0, 0, 0 },
11034 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11035 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc009 }
11036 },
11037/* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
11038 {
11039 { 0, 0, 0, 0 },
11040 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11041 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8029 }
11042 },
11043/* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
11044 {
11045 { 0, 0, 0, 0 },
11046 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11047 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8009 }
11048 },
11049/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11050 {
11051 { 0, 0, 0, 0 },
11052 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11053 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20900 }
11054 },
11055/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11056 {
11057 { 0, 0, 0, 0 },
11058 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11059 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822900 }
11060 },
11061/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
11062 {
11063 { 0, 0, 0, 0 },
11064 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11065 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820900 }
11066 },
11067/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11068 {
11069 { 0, 0, 0, 0 },
11070 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11071 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4090000 }
11072 },
11073/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11074 {
11075 { 0, 0, 0, 0 },
11076 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11077 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84290000 }
11078 },
11079/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
11080 {
11081 { 0, 0, 0, 0 },
11082 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11083 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84090000 }
11084 },
11085/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11086 {
11087 { 0, 0, 0, 0 },
11088 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11089 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6090000 }
11090 },
11091/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11092 {
11093 { 0, 0, 0, 0 },
11094 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11095 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86290000 }
11096 },
11097/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
11098 {
11099 { 0, 0, 0, 0 },
11100 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11101 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86090000 }
11102 },
11103/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
11104 {
11105 { 0, 0, 0, 0 },
11106 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11107 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28900 }
11108 },
11109/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
11110 {
11111 { 0, 0, 0, 0 },
11112 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11113 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a900 }
11114 },
11115/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
11116 {
11117 { 0, 0, 0, 0 },
11118 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11119 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828900 }
11120 },
11121/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
11122 {
11123 { 0, 0, 0, 0 },
11124 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11125 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4890000 }
11126 },
11127/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
11128 {
11129 { 0, 0, 0, 0 },
11130 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11131 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a90000 }
11132 },
11133/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
11134 {
11135 { 0, 0, 0, 0 },
11136 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11137 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84890000 }
11138 },
11139/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
11140 {
11141 { 0, 0, 0, 0 },
11142 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11143 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c900 }
11144 },
11145/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
11146 {
11147 { 0, 0, 0, 0 },
11148 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11149 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e900 }
11150 },
11151/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
11152 {
11153 { 0, 0, 0, 0 },
11154 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11155 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c900 }
11156 },
11157/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
11158 {
11159 { 0, 0, 0, 0 },
11160 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11161 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c90000 }
11162 },
11163/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
11164 {
11165 { 0, 0, 0, 0 },
11166 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11167 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e90000 }
11168 },
11169/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
11170 {
11171 { 0, 0, 0, 0 },
11172 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11173 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c90000 }
11174 },
11175/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
11176 {
11177 { 0, 0, 0, 0 },
11178 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
11179 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c90000 }
11180 },
11181/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
11182 {
11183 { 0, 0, 0, 0 },
11184 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
11185 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e90000 }
11186 },
11187/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
11188 {
11189 { 0, 0, 0, 0 },
11190 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
11191 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c90000 }
11192 },
11193/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
11194 {
11195 { 0, 0, 0, 0 },
11196 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
11197 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6890000 }
11198 },
11199/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
11200 {
11201 { 0, 0, 0, 0 },
11202 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
11203 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a90000 }
11204 },
11205/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
11206 {
11207 { 0, 0, 0, 0 },
11208 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
11209 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86890000 }
11210 },
11211/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
11212 {
11213 { 0, 0, 0, 0 },
11214 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11215 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x898000 }
11216 },
11217/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
11218 {
11219 { 0, 0, 0, 0 },
11220 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
11221 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x89a000 }
11222 },
11223/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
11224 {
11225 { 0, 0, 0, 0 },
11226 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
11227 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x89b000 }
11228 },
11229/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
11230 {
11231 { 0, 0, 0, 0 },
11232 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11233 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x898400 }
11234 },
11235/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
11236 {
11237 { 0, 0, 0, 0 },
11238 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
11239 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x89a400 }
11240 },
11241/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
11242 {
11243 { 0, 0, 0, 0 },
11244 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
11245 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x89b400 }
11246 },
11247/* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
11248 {
11249 { 0, 0, 0, 0 },
11250 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11251 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x898600 }
11252 },
11253/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
11254 {
11255 { 0, 0, 0, 0 },
11256 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11257 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x89a600 }
11258 },
11259/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
11260 {
11261 { 0, 0, 0, 0 },
11262 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11263 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x89b600 }
11264 },
11265/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
11266 {
11267 { 0, 0, 0, 0 },
11268 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11269 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x89880000 }
11270 },
11271/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
11272 {
11273 { 0, 0, 0, 0 },
11274 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11275 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x89a80000 }
11276 },
11277/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
11278 {
11279 { 0, 0, 0, 0 },
11280 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11281 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x89b80000 }
11282 },
11283/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
11284 {
11285 { 0, 0, 0, 0 },
11286 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11287 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x898c0000 }
11288 },
11289/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
11290 {
11291 { 0, 0, 0, 0 },
11292 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11293 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x89ac0000 }
11294 },
11295/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
11296 {
11297 { 0, 0, 0, 0 },
11298 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11299 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x89bc0000 }
11300 },
11301/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
11302 {
11303 { 0, 0, 0, 0 },
11304 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11305 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x898a0000 }
11306 },
11307/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
11308 {
11309 { 0, 0, 0, 0 },
11310 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11311 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89aa0000 }
11312 },
11313/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
11314 {
11315 { 0, 0, 0, 0 },
11316 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11317 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89ba0000 }
11318 },
11319/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
11320 {
11321 { 0, 0, 0, 0 },
11322 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11323 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x898e0000 }
11324 },
11325/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
11326 {
11327 { 0, 0, 0, 0 },
11328 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11329 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89ae0000 }
11330 },
11331/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
11332 {
11333 { 0, 0, 0, 0 },
11334 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11335 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89be0000 }
11336 },
11337/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
11338 {
11339 { 0, 0, 0, 0 },
11340 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11341 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x898b0000 }
11342 },
11343/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
11344 {
11345 { 0, 0, 0, 0 },
11346 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11347 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89ab0000 }
11348 },
11349/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
11350 {
11351 { 0, 0, 0, 0 },
11352 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11353 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89bb0000 }
11354 },
11355/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
11356 {
11357 { 0, 0, 0, 0 },
11358 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
11359 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x898f0000 }
11360 },
11361/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
11362 {
11363 { 0, 0, 0, 0 },
11364 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11365 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x89af0000 }
11366 },
11367/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
11368 {
11369 { 0, 0, 0, 0 },
11370 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11371 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x89bf0000 }
11372 },
11373/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
11374 {
11375 { 0, 0, 0, 0 },
11376 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11377 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x89c00000 }
11378 },
11379/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
11380 {
11381 { 0, 0, 0, 0 },
11382 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
11383 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x89e00000 }
11384 },
11385/* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
11386 {
11387 { 0, 0, 0, 0 },
11388 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
11389 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x89f00000 }
11390 },
11391/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
11392 {
11393 { 0, 0, 0, 0 },
11394 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11395 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x89c40000 }
11396 },
11397/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
11398 {
11399 { 0, 0, 0, 0 },
11400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
11401 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x89e40000 }
11402 },
11403/* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
11404 {
11405 { 0, 0, 0, 0 },
11406 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
11407 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x89f40000 }
11408 },
11409/* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
11410 {
11411 { 0, 0, 0, 0 },
11412 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11413 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x89c60000 }
11414 },
11415/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
11416 {
11417 { 0, 0, 0, 0 },
11418 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11419 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x89e60000 }
11420 },
11421/* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
11422 {
11423 { 0, 0, 0, 0 },
11424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
11425 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x89f60000 }
11426 },
11427/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
11428 {
11429 { 0, 0, 0, 0 },
11430 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11431 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x89c80000 }
11432 },
11433/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
11434 {
11435 { 0, 0, 0, 0 },
11436 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11437 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x89e80000 }
11438 },
11439/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
11440 {
11441 { 0, 0, 0, 0 },
11442 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11443 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x89f80000 }
11444 },
11445/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
11446 {
11447 { 0, 0, 0, 0 },
11448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11449 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x89cc0000 }
11450 },
11451/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
11452 {
11453 { 0, 0, 0, 0 },
11454 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11455 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x89ec0000 }
11456 },
11457/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
11458 {
11459 { 0, 0, 0, 0 },
11460 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11461 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x89fc0000 }
11462 },
11463/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
11464 {
11465 { 0, 0, 0, 0 },
11466 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11467 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ca0000 }
11468 },
11469/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
11470 {
11471 { 0, 0, 0, 0 },
11472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11473 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ea0000 }
11474 },
11475/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
11476 {
11477 { 0, 0, 0, 0 },
11478 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11479 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x89fa0000 }
11480 },
11481/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
11482 {
11483 { 0, 0, 0, 0 },
11484 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11485 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ce0000 }
11486 },
11487/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
11488 {
11489 { 0, 0, 0, 0 },
11490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11491 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ee0000 }
11492 },
11493/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
11494 {
11495 { 0, 0, 0, 0 },
11496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11497 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x89fe0000 }
11498 },
11499/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
11500 {
11501 { 0, 0, 0, 0 },
11502 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11503 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x89cb0000 }
11504 },
11505/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
11506 {
11507 { 0, 0, 0, 0 },
11508 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11509 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x89eb0000 }
11510 },
11511/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
11512 {
11513 { 0, 0, 0, 0 },
11514 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11515 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x89fb0000 }
11516 },
11517/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
11518 {
11519 { 0, 0, 0, 0 },
11520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
11521 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x89cf0000 }
11522 },
11523/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
11524 {
11525 { 0, 0, 0, 0 },
11526 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
11527 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x89ef0000 }
11528 },
11529/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
11530 {
11531 { 0, 0, 0, 0 },
11532 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
11533 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x89ff0000 }
11534 },
11535/* xor.w${G} $Src16RnHI,$Dst16RnHI */
11536 {
11537 { 0, 0, 0, 0 },
11538 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
11539 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8900 }
11540 },
11541/* xor.w${G} $Src16AnHI,$Dst16RnHI */
11542 {
11543 { 0, 0, 0, 0 },
11544 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
11545 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8940 }
11546 },
11547/* xor.w${G} [$Src16An],$Dst16RnHI */
11548 {
11549 { 0, 0, 0, 0 },
11550 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11551 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8960 }
11552 },
11553/* xor.w${G} $Src16RnHI,$Dst16AnHI */
11554 {
11555 { 0, 0, 0, 0 },
11556 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
11557 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8904 }
11558 },
11559/* xor.w${G} $Src16AnHI,$Dst16AnHI */
11560 {
11561 { 0, 0, 0, 0 },
11562 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
11563 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8944 }
11564 },
11565/* xor.w${G} [$Src16An],$Dst16AnHI */
11566 {
11567 { 0, 0, 0, 0 },
11568 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11569 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8964 }
11570 },
11571/* xor.w${G} $Src16RnHI,[$Dst16An] */
11572 {
11573 { 0, 0, 0, 0 },
11574 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
11575 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8906 }
11576 },
11577/* xor.w${G} $Src16AnHI,[$Dst16An] */
11578 {
11579 { 0, 0, 0, 0 },
11580 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
11581 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8946 }
11582 },
11583/* xor.w${G} [$Src16An],[$Dst16An] */
11584 {
11585 { 0, 0, 0, 0 },
11586 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11587 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8966 }
11588 },
11589/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
11590 {
11591 { 0, 0, 0, 0 },
11592 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11593 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x890800 }
11594 },
11595/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
11596 {
11597 { 0, 0, 0, 0 },
11598 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11599 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x894800 }
11600 },
11601/* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
11602 {
11603 { 0, 0, 0, 0 },
11604 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11605 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x896800 }
11606 },
11607/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
11608 {
11609 { 0, 0, 0, 0 },
11610 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11611 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x890c0000 }
11612 },
11613/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
11614 {
11615 { 0, 0, 0, 0 },
11616 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11617 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x894c0000 }
11618 },
11619/* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
11620 {
11621 { 0, 0, 0, 0 },
11622 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11623 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x896c0000 }
11624 },
11625/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
11626 {
11627 { 0, 0, 0, 0 },
11628 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11629 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x890a00 }
11630 },
11631/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
11632 {
11633 { 0, 0, 0, 0 },
11634 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11635 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x894a00 }
11636 },
11637/* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
11638 {
11639 { 0, 0, 0, 0 },
11640 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11641 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x896a00 }
11642 },
11643/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
11644 {
11645 { 0, 0, 0, 0 },
11646 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11647 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x890e0000 }
11648 },
11649/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
11650 {
11651 { 0, 0, 0, 0 },
11652 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11653 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x894e0000 }
11654 },
11655/* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
11656 {
11657 { 0, 0, 0, 0 },
11658 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11659 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x896e0000 }
11660 },
11661/* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
11662 {
11663 { 0, 0, 0, 0 },
11664 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11665 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x890b00 }
11666 },
11667/* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
11668 {
11669 { 0, 0, 0, 0 },
11670 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11671 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x894b00 }
11672 },
11673/* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
11674 {
11675 { 0, 0, 0, 0 },
11676 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11677 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x896b00 }
11678 },
11679/* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
11680 {
11681 { 0, 0, 0, 0 },
11682 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
11683 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x890f0000 }
11684 },
11685/* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
11686 {
11687 { 0, 0, 0, 0 },
11688 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
11689 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x894f0000 }
11690 },
11691/* xor.w${G} [$Src16An],${Dsp-16-u16} */
11692 {
11693 { 0, 0, 0, 0 },
11694 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
11695 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x896f0000 }
11696 },
11697/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
11698 {
11699 { 0, 0, 0, 0 },
11700 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
11701 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x888000 }
11702 },
11703/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
11704 {
11705 { 0, 0, 0, 0 },
11706 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
11707 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x88a000 }
11708 },
11709/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
11710 {
11711 { 0, 0, 0, 0 },
11712 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
11713 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x88b000 }
11714 },
11715/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
11716 {
11717 { 0, 0, 0, 0 },
11718 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
11719 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x888400 }
11720 },
11721/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
11722 {
11723 { 0, 0, 0, 0 },
11724 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
11725 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x88a400 }
11726 },
11727/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
11728 {
11729 { 0, 0, 0, 0 },
11730 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
11731 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x88b400 }
11732 },
11733/* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
11734 {
11735 { 0, 0, 0, 0 },
11736 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11737 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x888600 }
11738 },
11739/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
11740 {
11741 { 0, 0, 0, 0 },
11742 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11743 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x88a600 }
11744 },
11745/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
11746 {
11747 { 0, 0, 0, 0 },
11748 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11749 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x88b600 }
11750 },
11751/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
11752 {
11753 { 0, 0, 0, 0 },
11754 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11755 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x88880000 }
11756 },
11757/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
11758 {
11759 { 0, 0, 0, 0 },
11760 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11761 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x88a80000 }
11762 },
11763/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
11764 {
11765 { 0, 0, 0, 0 },
11766 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11767 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x88b80000 }
11768 },
11769/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
11770 {
11771 { 0, 0, 0, 0 },
11772 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11773 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x888c0000 }
11774 },
11775/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
11776 {
11777 { 0, 0, 0, 0 },
11778 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11779 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x88ac0000 }
11780 },
11781/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
11782 {
11783 { 0, 0, 0, 0 },
11784 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11785 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x88bc0000 }
11786 },
11787/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
11788 {
11789 { 0, 0, 0, 0 },
11790 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11791 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x888a0000 }
11792 },
11793/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
11794 {
11795 { 0, 0, 0, 0 },
11796 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11797 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88aa0000 }
11798 },
11799/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
11800 {
11801 { 0, 0, 0, 0 },
11802 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11803 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88ba0000 }
11804 },
11805/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
11806 {
11807 { 0, 0, 0, 0 },
11808 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11809 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x888e0000 }
11810 },
11811/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
11812 {
11813 { 0, 0, 0, 0 },
11814 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11815 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88ae0000 }
11816 },
11817/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
11818 {
11819 { 0, 0, 0, 0 },
11820 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11821 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88be0000 }
11822 },
11823/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
11824 {
11825 { 0, 0, 0, 0 },
11826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11827 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x888b0000 }
11828 },
11829/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
11830 {
11831 { 0, 0, 0, 0 },
11832 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11833 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88ab0000 }
11834 },
11835/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
11836 {
11837 { 0, 0, 0, 0 },
11838 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11839 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88bb0000 }
11840 },
11841/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
11842 {
11843 { 0, 0, 0, 0 },
11844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
11845 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x888f0000 }
11846 },
11847/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
11848 {
11849 { 0, 0, 0, 0 },
11850 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11851 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x88af0000 }
11852 },
11853/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
11854 {
11855 { 0, 0, 0, 0 },
11856 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11857 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x88bf0000 }
11858 },
11859/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
11860 {
11861 { 0, 0, 0, 0 },
11862 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
11863 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x88c00000 }
11864 },
11865/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
11866 {
11867 { 0, 0, 0, 0 },
11868 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
11869 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x88e00000 }
11870 },
11871/* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
11872 {
11873 { 0, 0, 0, 0 },
11874 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
11875 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x88f00000 }
11876 },
11877/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
11878 {
11879 { 0, 0, 0, 0 },
11880 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
11881 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x88c40000 }
11882 },
11883/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
11884 {
11885 { 0, 0, 0, 0 },
11886 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
11887 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x88e40000 }
11888 },
11889/* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
11890 {
11891 { 0, 0, 0, 0 },
11892 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
11893 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x88f40000 }
11894 },
11895/* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
11896 {
11897 { 0, 0, 0, 0 },
11898 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11899 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x88c60000 }
11900 },
11901/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
11902 {
11903 { 0, 0, 0, 0 },
11904 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11905 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x88e60000 }
11906 },
11907/* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
11908 {
11909 { 0, 0, 0, 0 },
11910 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
11911 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x88f60000 }
11912 },
11913/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
11914 {
11915 { 0, 0, 0, 0 },
11916 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11917 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x88c80000 }
11918 },
11919/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
11920 {
11921 { 0, 0, 0, 0 },
11922 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11923 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x88e80000 }
11924 },
11925/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
11926 {
11927 { 0, 0, 0, 0 },
11928 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11929 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x88f80000 }
11930 },
11931/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
11932 {
11933 { 0, 0, 0, 0 },
11934 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11935 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x88cc0000 }
11936 },
11937/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
11938 {
11939 { 0, 0, 0, 0 },
11940 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11941 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x88ec0000 }
11942 },
11943/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
11944 {
11945 { 0, 0, 0, 0 },
11946 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11947 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x88fc0000 }
11948 },
11949/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
11950 {
11951 { 0, 0, 0, 0 },
11952 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11953 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ca0000 }
11954 },
11955/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
11956 {
11957 { 0, 0, 0, 0 },
11958 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11959 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ea0000 }
11960 },
11961/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
11962 {
11963 { 0, 0, 0, 0 },
11964 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11965 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x88fa0000 }
11966 },
11967/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
11968 {
11969 { 0, 0, 0, 0 },
11970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11971 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ce0000 }
11972 },
11973/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
11974 {
11975 { 0, 0, 0, 0 },
11976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11977 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ee0000 }
11978 },
11979/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
11980 {
11981 { 0, 0, 0, 0 },
11982 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11983 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x88fe0000 }
11984 },
11985/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
11986 {
11987 { 0, 0, 0, 0 },
11988 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11989 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x88cb0000 }
11990 },
11991/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
11992 {
11993 { 0, 0, 0, 0 },
11994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11995 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x88eb0000 }
11996 },
11997/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
11998 {
11999 { 0, 0, 0, 0 },
12000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
12001 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x88fb0000 }
12002 },
12003/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
12004 {
12005 { 0, 0, 0, 0 },
12006 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
12007 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x88cf0000 }
12008 },
12009/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
12010 {
12011 { 0, 0, 0, 0 },
12012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
12013 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x88ef0000 }
12014 },
12015/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
12016 {
12017 { 0, 0, 0, 0 },
12018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
12019 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x88ff0000 }
12020 },
12021/* xor.b${G} $Src16RnQI,$Dst16RnQI */
12022 {
12023 { 0, 0, 0, 0 },
12024 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
12025 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8800 }
12026 },
12027/* xor.b${G} $Src16AnQI,$Dst16RnQI */
12028 {
12029 { 0, 0, 0, 0 },
12030 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
12031 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8840 }
12032 },
12033/* xor.b${G} [$Src16An],$Dst16RnQI */
12034 {
12035 { 0, 0, 0, 0 },
12036 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
12037 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8860 }
12038 },
12039/* xor.b${G} $Src16RnQI,$Dst16AnQI */
12040 {
12041 { 0, 0, 0, 0 },
12042 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
12043 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8804 }
12044 },
12045/* xor.b${G} $Src16AnQI,$Dst16AnQI */
12046 {
12047 { 0, 0, 0, 0 },
12048 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
12049 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8844 }
12050 },
12051/* xor.b${G} [$Src16An],$Dst16AnQI */
12052 {
12053 { 0, 0, 0, 0 },
12054 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
12055 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8864 }
12056 },
12057/* xor.b${G} $Src16RnQI,[$Dst16An] */
12058 {
12059 { 0, 0, 0, 0 },
12060 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
12061 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8806 }
12062 },
12063/* xor.b${G} $Src16AnQI,[$Dst16An] */
12064 {
12065 { 0, 0, 0, 0 },
12066 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
12067 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8846 }
12068 },
12069/* xor.b${G} [$Src16An],[$Dst16An] */
12070 {
12071 { 0, 0, 0, 0 },
12072 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
12073 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8866 }
12074 },
12075/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
12076 {
12077 { 0, 0, 0, 0 },
12078 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12079 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x880800 }
12080 },
12081/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
12082 {
12083 { 0, 0, 0, 0 },
12084 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12085 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x884800 }
12086 },
12087/* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
12088 {
12089 { 0, 0, 0, 0 },
12090 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12091 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x886800 }
12092 },
12093/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
12094 {
12095 { 0, 0, 0, 0 },
12096 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12097 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x880c0000 }
12098 },
12099/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
12100 {
12101 { 0, 0, 0, 0 },
12102 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12103 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x884c0000 }
12104 },
12105/* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
12106 {
12107 { 0, 0, 0, 0 },
12108 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12109 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x886c0000 }
12110 },
12111/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
12112 {
12113 { 0, 0, 0, 0 },
12114 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12115 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x880a00 }
12116 },
12117/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
12118 {
12119 { 0, 0, 0, 0 },
12120 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12121 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x884a00 }
12122 },
12123/* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
12124 {
12125 { 0, 0, 0, 0 },
12126 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12127 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x886a00 }
12128 },
12129/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
12130 {
12131 { 0, 0, 0, 0 },
12132 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12133 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x880e0000 }
12134 },
12135/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
12136 {
12137 { 0, 0, 0, 0 },
12138 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12139 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x884e0000 }
12140 },
12141/* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
12142 {
12143 { 0, 0, 0, 0 },
12144 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12145 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x886e0000 }
12146 },
12147/* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
12148 {
12149 { 0, 0, 0, 0 },
12150 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12151 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x880b00 }
12152 },
12153/* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
12154 {
12155 { 0, 0, 0, 0 },
12156 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12157 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x884b00 }
12158 },
12159/* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
12160 {
12161 { 0, 0, 0, 0 },
12162 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12163 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x886b00 }
12164 },
12165/* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
12166 {
12167 { 0, 0, 0, 0 },
12168 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
12169 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x880f0000 }
12170 },
12171/* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
12172 {
12173 { 0, 0, 0, 0 },
12174 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
12175 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x884f0000 }
12176 },
12177/* xor.b${G} [$Src16An],${Dsp-16-u16} */
12178 {
12179 { 0, 0, 0, 0 },
12180 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
12181 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x886f0000 }
12182 },
12183/* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
12184 {
12185 { 0, 0, 0, 0 },
12186 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12187 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990e0000 }
12188 },
12189/* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
12190 {
12191 { 0, 0, 0, 0 },
12192 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12193 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918e0000 }
12194 },
12195/* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
12196 {
12197 { 0, 0, 0, 0 },
12198 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12199 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910e0000 }
12200 },
12201/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12202 {
12203 { 0, 0, 0, 0 },
12204 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12205 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930e0000 }
12206 },
12207/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
12208 {
12209 { 0, 0, 0, 0 },
12210 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12211 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938e0000 }
12212 },
12213/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
12214 {
12215 { 0, 0, 0, 0 },
12216 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12217 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ce0000 }
12218 },
12219/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12220 {
12221 { 0, 0, 0, 0 },
12222 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12223 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950e0000 }
12224 },
12225/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
12226 {
12227 { 0, 0, 0, 0 },
12228 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12229 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958e0000 }
12230 },
12231/* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
12232 {
12233 { 0, 0, 0, 0 },
12234 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12235 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ce0000 }
12236 },
12237/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
12238 {
12239 { 0, 0, 0, 0 },
12240 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
12241 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ce0000 }
12242 },
12243/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12244 {
12245 { 0, 0, 0, 0 },
12246 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12247 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970e0000 }
12248 },
12249/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
12250 {
12251 { 0, 0, 0, 0 },
12252 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
12253 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978e0000 }
12254 },
12255/* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
12256 {
12257 { 0, 0, 0, 0 },
12258 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
12259 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980e00 }
12260 },
12261/* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
12262 {
12263 { 0, 0, 0, 0 },
12264 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
12265 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908e00 }
12266 },
12267/* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12268 {
12269 { 0, 0, 0, 0 },
12270 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12271 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900e00 }
12272 },
12273/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12274 {
12275 { 0, 0, 0, 0 },
12276 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12277 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920e0000 }
12278 },
12279/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12280 {
12281 { 0, 0, 0, 0 },
12282 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12283 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928e0000 }
12284 },
12285/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12286 {
12287 { 0, 0, 0, 0 },
12288 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12289 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ce0000 }
12290 },
12291/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12292 {
12293 { 0, 0, 0, 0 },
12294 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12295 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940e0000 }
12296 },
12297/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12298 {
12299 { 0, 0, 0, 0 },
12300 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12301 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948e0000 }
12302 },
12303/* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12304 {
12305 { 0, 0, 0, 0 },
12306 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12307 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ce0000 }
12308 },
12309/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
12310 {
12311 { 0, 0, 0, 0 },
12312 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
12313 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ce0000 }
12314 },
12315/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12316 {
12317 { 0, 0, 0, 0 },
12318 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12319 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960e0000 }
12320 },
12321/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
12322 {
12323 { 0, 0, 0, 0 },
12324 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
12325 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968e0000 }
12326 },
12327/* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
12328 {
12329 { 0, 0, 0, 0 },
12330 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
12331 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77100000 }
12332 },
12333/* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
12334 {
12335 { 0, 0, 0, 0 },
12336 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
12337 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77140000 }
12338 },
12339/* xor.w${G} #${Imm-16-HI},[$Dst16An] */
12340 {
12341 { 0, 0, 0, 0 },
12342 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
12343 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77160000 }
12344 },
12345/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
12346 {
12347 { 0, 0, 0, 0 },
12348 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12349 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77180000 }
12350 },
12351/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
12352 {
12353 { 0, 0, 0, 0 },
12354 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12355 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x771a0000 }
12356 },
12357/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
12358 {
12359 { 0, 0, 0, 0 },
12360 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12361 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x771b0000 }
12362 },
12363/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
12364 {
12365 { 0, 0, 0, 0 },
12366 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12367 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x771c0000 }
12368 },
12369/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
12370 {
12371 { 0, 0, 0, 0 },
12372 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12373 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x771e0000 }
12374 },
12375/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
12376 {
12377 { 0, 0, 0, 0 },
12378 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
12379 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x771f0000 }
12380 },
12381/* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
12382 {
12383 { 0, 0, 0, 0 },
12384 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
12385 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x761000 }
12386 },
12387/* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
12388 {
12389 { 0, 0, 0, 0 },
12390 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
12391 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x761400 }
12392 },
12393/* xor.b${G} #${Imm-16-QI},[$Dst16An] */
12394 {
12395 { 0, 0, 0, 0 },
12396 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
12397 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x761600 }
12398 },
12399/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
12400 {
12401 { 0, 0, 0, 0 },
12402 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12403 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76180000 }
12404 },
12405/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12406 {
12407 { 0, 0, 0, 0 },
12408 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12409 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x761a0000 }
12410 },
12411/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12412 {
12413 { 0, 0, 0, 0 },
12414 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12415 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x761b0000 }
12416 },
12417/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
12418 {
12419 { 0, 0, 0, 0 },
12420 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12421 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x761c0000 }
12422 },
12423/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12424 {
12425 { 0, 0, 0, 0 },
12426 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12427 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x761e0000 }
12428 },
12429/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
12430 {
12431 { 0, 0, 0, 0 },
12432 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
12433 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x761f0000 }
12434 },
12435/* xchg.w r3,$Dst32RnUnprefixedHI */
12436 {
12437 { 0, 0, 0, 0 },
12438 { { MNEM, ' ', 'r', '3', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12439 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90d }
12440 },
12441/* xchg.w r3,$Dst32AnUnprefixedHI */
12442 {
12443 { 0, 0, 0, 0 },
12444 { { MNEM, ' ', 'r', '3', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12445 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18d }
12446 },
12447/* xchg.w r3,[$Dst32AnUnprefixed] */
12448 {
12449 { 0, 0, 0, 0 },
12450 { { MNEM, ' ', 'r', '3', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12451 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10d }
12452 },
12453/* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12454 {
12455 { 0, 0, 0, 0 },
12456 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12457 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30d00 }
12458 },
12459/* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12460 {
12461 { 0, 0, 0, 0 },
12462 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12463 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50d0000 }
12464 },
12465/* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12466 {
12467 { 0, 0, 0, 0 },
12468 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12469 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70d0000 }
12470 },
12471/* xchg.w r3,${Dsp-16-u8}[sb] */
12472 {
12473 { 0, 0, 0, 0 },
12474 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12475 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38d00 }
12476 },
12477/* xchg.w r3,${Dsp-16-u16}[sb] */
12478 {
12479 { 0, 0, 0, 0 },
12480 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12481 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58d0000 }
12482 },
12483/* xchg.w r3,${Dsp-16-s8}[fb] */
12484 {
12485 { 0, 0, 0, 0 },
12486 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12487 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cd00 }
12488 },
12489/* xchg.w r3,${Dsp-16-s16}[fb] */
12490 {
12491 { 0, 0, 0, 0 },
12492 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12493 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cd0000 }
12494 },
12495/* xchg.w r3,${Dsp-16-u16} */
12496 {
12497 { 0, 0, 0, 0 },
12498 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } },
12499 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cd0000 }
12500 },
12501/* xchg.w r3,${Dsp-16-u24} */
12502 {
12503 { 0, 0, 0, 0 },
12504 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), 0 } },
12505 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78d0000 }
12506 },
12507/* xchg.w r2,$Dst32RnUnprefixedHI */
12508 {
12509 { 0, 0, 0, 0 },
12510 { { MNEM, ' ', 'r', '2', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12511 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90c }
12512 },
12513/* xchg.w r2,$Dst32AnUnprefixedHI */
12514 {
12515 { 0, 0, 0, 0 },
12516 { { MNEM, ' ', 'r', '2', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12517 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18c }
12518 },
12519/* xchg.w r2,[$Dst32AnUnprefixed] */
12520 {
12521 { 0, 0, 0, 0 },
12522 { { MNEM, ' ', 'r', '2', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12523 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10c }
12524 },
12525/* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12526 {
12527 { 0, 0, 0, 0 },
12528 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12529 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30c00 }
12530 },
12531/* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12532 {
12533 { 0, 0, 0, 0 },
12534 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12535 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50c0000 }
12536 },
12537/* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12538 {
12539 { 0, 0, 0, 0 },
12540 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12541 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70c0000 }
12542 },
12543/* xchg.w r2,${Dsp-16-u8}[sb] */
12544 {
12545 { 0, 0, 0, 0 },
12546 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12547 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38c00 }
12548 },
12549/* xchg.w r2,${Dsp-16-u16}[sb] */
12550 {
12551 { 0, 0, 0, 0 },
12552 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12553 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58c0000 }
12554 },
12555/* xchg.w r2,${Dsp-16-s8}[fb] */
12556 {
12557 { 0, 0, 0, 0 },
12558 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12559 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cc00 }
12560 },
12561/* xchg.w r2,${Dsp-16-s16}[fb] */
12562 {
12563 { 0, 0, 0, 0 },
12564 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12565 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cc0000 }
12566 },
12567/* xchg.w r2,${Dsp-16-u16} */
12568 {
12569 { 0, 0, 0, 0 },
12570 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } },
12571 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cc0000 }
12572 },
12573/* xchg.w r2,${Dsp-16-u24} */
12574 {
12575 { 0, 0, 0, 0 },
12576 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), 0 } },
12577 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78c0000 }
12578 },
12579/* xchg.w a1,$Dst32RnUnprefixedHI */
12580 {
12581 { 0, 0, 0, 0 },
12582 { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12583 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90b }
12584 },
12585/* xchg.w a1,$Dst32AnUnprefixedHI */
12586 {
12587 { 0, 0, 0, 0 },
12588 { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12589 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18b }
12590 },
12591/* xchg.w a1,[$Dst32AnUnprefixed] */
12592 {
12593 { 0, 0, 0, 0 },
12594 { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12595 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10b }
12596 },
12597/* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12598 {
12599 { 0, 0, 0, 0 },
12600 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12601 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30b00 }
12602 },
12603/* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12604 {
12605 { 0, 0, 0, 0 },
12606 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12607 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50b0000 }
12608 },
12609/* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12610 {
12611 { 0, 0, 0, 0 },
12612 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12613 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70b0000 }
12614 },
12615/* xchg.w a1,${Dsp-16-u8}[sb] */
12616 {
12617 { 0, 0, 0, 0 },
12618 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12619 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38b00 }
12620 },
12621/* xchg.w a1,${Dsp-16-u16}[sb] */
12622 {
12623 { 0, 0, 0, 0 },
12624 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12625 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58b0000 }
12626 },
12627/* xchg.w a1,${Dsp-16-s8}[fb] */
12628 {
12629 { 0, 0, 0, 0 },
12630 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12631 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cb00 }
12632 },
12633/* xchg.w a1,${Dsp-16-s16}[fb] */
12634 {
12635 { 0, 0, 0, 0 },
12636 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12637 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cb0000 }
12638 },
12639/* xchg.w a1,${Dsp-16-u16} */
12640 {
12641 { 0, 0, 0, 0 },
12642 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } },
12643 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cb0000 }
12644 },
12645/* xchg.w a1,${Dsp-16-u24} */
12646 {
12647 { 0, 0, 0, 0 },
12648 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } },
12649 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78b0000 }
12650 },
12651/* xchg.w a0,$Dst32RnUnprefixedHI */
12652 {
12653 { 0, 0, 0, 0 },
12654 { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12655 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90a }
12656 },
12657/* xchg.w a0,$Dst32AnUnprefixedHI */
12658 {
12659 { 0, 0, 0, 0 },
12660 { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12661 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18a }
12662 },
12663/* xchg.w a0,[$Dst32AnUnprefixed] */
12664 {
12665 { 0, 0, 0, 0 },
12666 { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12667 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10a }
12668 },
12669/* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12670 {
12671 { 0, 0, 0, 0 },
12672 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12673 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30a00 }
12674 },
12675/* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12676 {
12677 { 0, 0, 0, 0 },
12678 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12679 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50a0000 }
12680 },
12681/* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12682 {
12683 { 0, 0, 0, 0 },
12684 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12685 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70a0000 }
12686 },
12687/* xchg.w a0,${Dsp-16-u8}[sb] */
12688 {
12689 { 0, 0, 0, 0 },
12690 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12691 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38a00 }
12692 },
12693/* xchg.w a0,${Dsp-16-u16}[sb] */
12694 {
12695 { 0, 0, 0, 0 },
12696 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12697 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58a0000 }
12698 },
12699/* xchg.w a0,${Dsp-16-s8}[fb] */
12700 {
12701 { 0, 0, 0, 0 },
12702 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12703 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3ca00 }
12704 },
12705/* xchg.w a0,${Dsp-16-s16}[fb] */
12706 {
12707 { 0, 0, 0, 0 },
12708 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12709 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5ca0000 }
12710 },
12711/* xchg.w a0,${Dsp-16-u16} */
12712 {
12713 { 0, 0, 0, 0 },
12714 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } },
12715 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7ca0000 }
12716 },
12717/* xchg.w a0,${Dsp-16-u24} */
12718 {
12719 { 0, 0, 0, 0 },
12720 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } },
12721 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78a0000 }
12722 },
12723/* xchg.w r1,$Dst32RnUnprefixedHI */
12724 {
12725 { 0, 0, 0, 0 },
12726 { { MNEM, ' ', 'r', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12727 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd909 }
12728 },
12729/* xchg.w r1,$Dst32AnUnprefixedHI */
12730 {
12731 { 0, 0, 0, 0 },
12732 { { MNEM, ' ', 'r', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12733 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd189 }
12734 },
12735/* xchg.w r1,[$Dst32AnUnprefixed] */
12736 {
12737 { 0, 0, 0, 0 },
12738 { { MNEM, ' ', 'r', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12739 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd109 }
12740 },
12741/* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12742 {
12743 { 0, 0, 0, 0 },
12744 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12745 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30900 }
12746 },
12747/* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12748 {
12749 { 0, 0, 0, 0 },
12750 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12751 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5090000 }
12752 },
12753/* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12754 {
12755 { 0, 0, 0, 0 },
12756 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12757 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7090000 }
12758 },
12759/* xchg.w r1,${Dsp-16-u8}[sb] */
12760 {
12761 { 0, 0, 0, 0 },
12762 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12763 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38900 }
12764 },
12765/* xchg.w r1,${Dsp-16-u16}[sb] */
12766 {
12767 { 0, 0, 0, 0 },
12768 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12769 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5890000 }
12770 },
12771/* xchg.w r1,${Dsp-16-s8}[fb] */
12772 {
12773 { 0, 0, 0, 0 },
12774 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12775 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c900 }
12776 },
12777/* xchg.w r1,${Dsp-16-s16}[fb] */
12778 {
12779 { 0, 0, 0, 0 },
12780 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12781 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c90000 }
12782 },
12783/* xchg.w r1,${Dsp-16-u16} */
12784 {
12785 { 0, 0, 0, 0 },
12786 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } },
12787 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c90000 }
12788 },
12789/* xchg.w r1,${Dsp-16-u24} */
12790 {
12791 { 0, 0, 0, 0 },
12792 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), 0 } },
12793 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7890000 }
12794 },
12795/* xchg.w r0,$Dst32RnUnprefixedHI */
12796 {
12797 { 0, 0, 0, 0 },
12798 { { MNEM, ' ', 'r', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12799 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd908 }
12800 },
12801/* xchg.w r0,$Dst32AnUnprefixedHI */
12802 {
12803 { 0, 0, 0, 0 },
12804 { { MNEM, ' ', 'r', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12805 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd188 }
12806 },
12807/* xchg.w r0,[$Dst32AnUnprefixed] */
12808 {
12809 { 0, 0, 0, 0 },
12810 { { MNEM, ' ', 'r', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12811 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd108 }
12812 },
12813/* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12814 {
12815 { 0, 0, 0, 0 },
12816 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12817 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30800 }
12818 },
12819/* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12820 {
12821 { 0, 0, 0, 0 },
12822 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12823 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5080000 }
12824 },
12825/* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12826 {
12827 { 0, 0, 0, 0 },
12828 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12829 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7080000 }
12830 },
12831/* xchg.w r0,${Dsp-16-u8}[sb] */
12832 {
12833 { 0, 0, 0, 0 },
12834 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12835 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38800 }
12836 },
12837/* xchg.w r0,${Dsp-16-u16}[sb] */
12838 {
12839 { 0, 0, 0, 0 },
12840 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12841 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5880000 }
12842 },
12843/* xchg.w r0,${Dsp-16-s8}[fb] */
12844 {
12845 { 0, 0, 0, 0 },
12846 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12847 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c800 }
12848 },
12849/* xchg.w r0,${Dsp-16-s16}[fb] */
12850 {
12851 { 0, 0, 0, 0 },
12852 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12853 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c80000 }
12854 },
12855/* xchg.w r0,${Dsp-16-u16} */
12856 {
12857 { 0, 0, 0, 0 },
12858 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } },
12859 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c80000 }
12860 },
12861/* xchg.w r0,${Dsp-16-u24} */
12862 {
12863 { 0, 0, 0, 0 },
12864 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), 0 } },
12865 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7880000 }
12866 },
12867/* xchg.b r1h,$Dst32RnUnprefixedQI */
12868 {
12869 { 0, 0, 0, 0 },
12870 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
12871 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80d }
12872 },
12873/* xchg.b r1h,$Dst32AnUnprefixedQI */
12874 {
12875 { 0, 0, 0, 0 },
12876 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
12877 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08d }
12878 },
12879/* xchg.b r1h,[$Dst32AnUnprefixed] */
12880 {
12881 { 0, 0, 0, 0 },
12882 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12883 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00d }
12884 },
12885/* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12886 {
12887 { 0, 0, 0, 0 },
12888 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12889 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20d00 }
12890 },
12891/* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12892 {
12893 { 0, 0, 0, 0 },
12894 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12895 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40d0000 }
12896 },
12897/* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12898 {
12899 { 0, 0, 0, 0 },
12900 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12901 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60d0000 }
12902 },
12903/* xchg.b r1h,${Dsp-16-u8}[sb] */
12904 {
12905 { 0, 0, 0, 0 },
12906 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12907 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28d00 }
12908 },
12909/* xchg.b r1h,${Dsp-16-u16}[sb] */
12910 {
12911 { 0, 0, 0, 0 },
12912 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12913 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48d0000 }
12914 },
12915/* xchg.b r1h,${Dsp-16-s8}[fb] */
12916 {
12917 { 0, 0, 0, 0 },
12918 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12919 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cd00 }
12920 },
12921/* xchg.b r1h,${Dsp-16-s16}[fb] */
12922 {
12923 { 0, 0, 0, 0 },
12924 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12925 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cd0000 }
12926 },
12927/* xchg.b r1h,${Dsp-16-u16} */
12928 {
12929 { 0, 0, 0, 0 },
12930 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
12931 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cd0000 }
12932 },
12933/* xchg.b r1h,${Dsp-16-u24} */
12934 {
12935 { 0, 0, 0, 0 },
12936 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
12937 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68d0000 }
12938 },
12939/* xchg.b r0h,$Dst32RnUnprefixedQI */
12940 {
12941 { 0, 0, 0, 0 },
12942 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
12943 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80c }
12944 },
12945/* xchg.b r0h,$Dst32AnUnprefixedQI */
12946 {
12947 { 0, 0, 0, 0 },
12948 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
12949 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08c }
12950 },
12951/* xchg.b r0h,[$Dst32AnUnprefixed] */
12952 {
12953 { 0, 0, 0, 0 },
12954 { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12955 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00c }
12956 },
12957/* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12958 {
12959 { 0, 0, 0, 0 },
12960 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12961 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20c00 }
12962 },
12963/* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12964 {
12965 { 0, 0, 0, 0 },
12966 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12967 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40c0000 }
12968 },
12969/* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12970 {
12971 { 0, 0, 0, 0 },
12972 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12973 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60c0000 }
12974 },
12975/* xchg.b r0h,${Dsp-16-u8}[sb] */
12976 {
12977 { 0, 0, 0, 0 },
12978 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12979 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28c00 }
12980 },
12981/* xchg.b r0h,${Dsp-16-u16}[sb] */
12982 {
12983 { 0, 0, 0, 0 },
12984 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12985 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48c0000 }
12986 },
12987/* xchg.b r0h,${Dsp-16-s8}[fb] */
12988 {
12989 { 0, 0, 0, 0 },
12990 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12991 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cc00 }
12992 },
12993/* xchg.b r0h,${Dsp-16-s16}[fb] */
12994 {
12995 { 0, 0, 0, 0 },
12996 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12997 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cc0000 }
12998 },
12999/* xchg.b r0h,${Dsp-16-u16} */
13000 {
13001 { 0, 0, 0, 0 },
13002 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } },
13003 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cc0000 }
13004 },
13005/* xchg.b r0h,${Dsp-16-u24} */
13006 {
13007 { 0, 0, 0, 0 },
13008 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), 0 } },
13009 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68c0000 }
13010 },
13011/* xchg.b a1,$Dst32RnUnprefixedQI */
13012 {
13013 { 0, 0, 0, 0 },
13014 { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13015 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80b }
13016 },
13017/* xchg.b a1,$Dst32AnUnprefixedQI */
13018 {
13019 { 0, 0, 0, 0 },
13020 { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13021 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08b }
13022 },
13023/* xchg.b a1,[$Dst32AnUnprefixed] */
13024 {
13025 { 0, 0, 0, 0 },
13026 { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13027 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00b }
13028 },
13029/* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13030 {
13031 { 0, 0, 0, 0 },
13032 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13033 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20b00 }
13034 },
13035/* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13036 {
13037 { 0, 0, 0, 0 },
13038 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13039 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40b0000 }
13040 },
13041/* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13042 {
13043 { 0, 0, 0, 0 },
13044 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13045 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60b0000 }
13046 },
13047/* xchg.b a1,${Dsp-16-u8}[sb] */
13048 {
13049 { 0, 0, 0, 0 },
13050 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13051 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28b00 }
13052 },
13053/* xchg.b a1,${Dsp-16-u16}[sb] */
13054 {
13055 { 0, 0, 0, 0 },
13056 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13057 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48b0000 }
13058 },
13059/* xchg.b a1,${Dsp-16-s8}[fb] */
13060 {
13061 { 0, 0, 0, 0 },
13062 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13063 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cb00 }
13064 },
13065/* xchg.b a1,${Dsp-16-s16}[fb] */
13066 {
13067 { 0, 0, 0, 0 },
13068 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13069 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cb0000 }
13070 },
13071/* xchg.b a1,${Dsp-16-u16} */
13072 {
13073 { 0, 0, 0, 0 },
13074 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } },
13075 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cb0000 }
13076 },
13077/* xchg.b a1,${Dsp-16-u24} */
13078 {
13079 { 0, 0, 0, 0 },
13080 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } },
13081 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68b0000 }
13082 },
13083/* xchg.b a0,$Dst32RnUnprefixedQI */
13084 {
13085 { 0, 0, 0, 0 },
13086 { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13087 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80a }
13088 },
13089/* xchg.b a0,$Dst32AnUnprefixedQI */
13090 {
13091 { 0, 0, 0, 0 },
13092 { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13093 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08a }
13094 },
13095/* xchg.b a0,[$Dst32AnUnprefixed] */
13096 {
13097 { 0, 0, 0, 0 },
13098 { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13099 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00a }
13100 },
13101/* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13102 {
13103 { 0, 0, 0, 0 },
13104 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13105 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20a00 }
13106 },
13107/* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13108 {
13109 { 0, 0, 0, 0 },
13110 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13111 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40a0000 }
13112 },
13113/* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13114 {
13115 { 0, 0, 0, 0 },
13116 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13117 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60a0000 }
13118 },
13119/* xchg.b a0,${Dsp-16-u8}[sb] */
13120 {
13121 { 0, 0, 0, 0 },
13122 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13123 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28a00 }
13124 },
13125/* xchg.b a0,${Dsp-16-u16}[sb] */
13126 {
13127 { 0, 0, 0, 0 },
13128 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13129 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48a0000 }
13130 },
13131/* xchg.b a0,${Dsp-16-s8}[fb] */
13132 {
13133 { 0, 0, 0, 0 },
13134 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13135 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2ca00 }
13136 },
13137/* xchg.b a0,${Dsp-16-s16}[fb] */
13138 {
13139 { 0, 0, 0, 0 },
13140 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13141 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4ca0000 }
13142 },
13143/* xchg.b a0,${Dsp-16-u16} */
13144 {
13145 { 0, 0, 0, 0 },
13146 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } },
13147 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6ca0000 }
13148 },
13149/* xchg.b a0,${Dsp-16-u24} */
13150 {
13151 { 0, 0, 0, 0 },
13152 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } },
13153 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68a0000 }
13154 },
13155/* xchg.b r1l,$Dst32RnUnprefixedQI */
13156 {
13157 { 0, 0, 0, 0 },
13158 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13159 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd809 }
13160 },
13161/* xchg.b r1l,$Dst32AnUnprefixedQI */
13162 {
13163 { 0, 0, 0, 0 },
13164 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13165 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd089 }
13166 },
13167/* xchg.b r1l,[$Dst32AnUnprefixed] */
13168 {
13169 { 0, 0, 0, 0 },
13170 { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13171 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd009 }
13172 },
13173/* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13174 {
13175 { 0, 0, 0, 0 },
13176 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13177 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20900 }
13178 },
13179/* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13180 {
13181 { 0, 0, 0, 0 },
13182 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13183 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4090000 }
13184 },
13185/* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13186 {
13187 { 0, 0, 0, 0 },
13188 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13189 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6090000 }
13190 },
13191/* xchg.b r1l,${Dsp-16-u8}[sb] */
13192 {
13193 { 0, 0, 0, 0 },
13194 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13195 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28900 }
13196 },
13197/* xchg.b r1l,${Dsp-16-u16}[sb] */
13198 {
13199 { 0, 0, 0, 0 },
13200 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13201 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4890000 }
13202 },
13203/* xchg.b r1l,${Dsp-16-s8}[fb] */
13204 {
13205 { 0, 0, 0, 0 },
13206 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13207 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c900 }
13208 },
13209/* xchg.b r1l,${Dsp-16-s16}[fb] */
13210 {
13211 { 0, 0, 0, 0 },
13212 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13213 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c90000 }
13214 },
13215/* xchg.b r1l,${Dsp-16-u16} */
13216 {
13217 { 0, 0, 0, 0 },
13218 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } },
13219 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c90000 }
13220 },
13221/* xchg.b r1l,${Dsp-16-u24} */
13222 {
13223 { 0, 0, 0, 0 },
13224 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), 0 } },
13225 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6890000 }
13226 },
13227/* xchg.b r0l,$Dst32RnUnprefixedQI */
13228 {
13229 { 0, 0, 0, 0 },
13230 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13231 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd808 }
13232 },
13233/* xchg.b r0l,$Dst32AnUnprefixedQI */
13234 {
13235 { 0, 0, 0, 0 },
13236 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13237 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd088 }
13238 },
13239/* xchg.b r0l,[$Dst32AnUnprefixed] */
13240 {
13241 { 0, 0, 0, 0 },
13242 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13243 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd008 }
13244 },
13245/* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13246 {
13247 { 0, 0, 0, 0 },
13248 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13249 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20800 }
13250 },
13251/* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13252 {
13253 { 0, 0, 0, 0 },
13254 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13255 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4080000 }
13256 },
13257/* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13258 {
13259 { 0, 0, 0, 0 },
13260 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13261 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6080000 }
13262 },
13263/* xchg.b r0l,${Dsp-16-u8}[sb] */
13264 {
13265 { 0, 0, 0, 0 },
13266 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13267 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28800 }
13268 },
13269/* xchg.b r0l,${Dsp-16-u16}[sb] */
13270 {
13271 { 0, 0, 0, 0 },
13272 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13273 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4880000 }
13274 },
13275/* xchg.b r0l,${Dsp-16-s8}[fb] */
13276 {
13277 { 0, 0, 0, 0 },
13278 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13279 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c800 }
13280 },
13281/* xchg.b r0l,${Dsp-16-s16}[fb] */
13282 {
13283 { 0, 0, 0, 0 },
13284 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13285 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c80000 }
13286 },
13287/* xchg.b r0l,${Dsp-16-u16} */
13288 {
13289 { 0, 0, 0, 0 },
13290 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
13291 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c80000 }
13292 },
13293/* xchg.b r0l,${Dsp-16-u24} */
13294 {
13295 { 0, 0, 0, 0 },
13296 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), 0 } },
13297 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6880000 }
13298 },
13299/* xchg.w r3,$Dst16RnHI */
13300 {
13301 { 0, 0, 0, 0 },
13302 { { MNEM, ' ', 'r', '3', ',', OP (DST16RNHI), 0 } },
13303 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b30 }
13304 },
13305/* xchg.w r3,$Dst16AnHI */
13306 {
13307 { 0, 0, 0, 0 },
13308 { { MNEM, ' ', 'r', '3', ',', OP (DST16ANHI), 0 } },
13309 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b34 }
13310 },
13311/* xchg.w r3,[$Dst16An] */
13312 {
13313 { 0, 0, 0, 0 },
13314 { { MNEM, ' ', 'r', '3', ',', '[', OP (DST16AN), ']', 0 } },
13315 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b36 }
13316 },
13317/* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
13318 {
13319 { 0, 0, 0, 0 },
13320 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13321 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b3800 }
13322 },
13323/* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
13324 {
13325 { 0, 0, 0, 0 },
13326 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13327 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b3c0000 }
13328 },
13329/* xchg.w r3,${Dsp-16-u8}[sb] */
13330 {
13331 { 0, 0, 0, 0 },
13332 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13333 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b3a00 }
13334 },
13335/* xchg.w r3,${Dsp-16-u16}[sb] */
13336 {
13337 { 0, 0, 0, 0 },
13338 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13339 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b3e0000 }
13340 },
13341/* xchg.w r3,${Dsp-16-s8}[fb] */
13342 {
13343 { 0, 0, 0, 0 },
13344 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13345 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b3b00 }
13346 },
13347/* xchg.w r3,${Dsp-16-u16} */
13348 {
13349 { 0, 0, 0, 0 },
13350 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } },
13351 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b3f0000 }
13352 },
13353/* xchg.w r2,$Dst16RnHI */
13354 {
13355 { 0, 0, 0, 0 },
13356 { { MNEM, ' ', 'r', '2', ',', OP (DST16RNHI), 0 } },
13357 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b20 }
13358 },
13359/* xchg.w r2,$Dst16AnHI */
13360 {
13361 { 0, 0, 0, 0 },
13362 { { MNEM, ' ', 'r', '2', ',', OP (DST16ANHI), 0 } },
13363 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b24 }
13364 },
13365/* xchg.w r2,[$Dst16An] */
13366 {
13367 { 0, 0, 0, 0 },
13368 { { MNEM, ' ', 'r', '2', ',', '[', OP (DST16AN), ']', 0 } },
13369 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b26 }
13370 },
13371/* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
13372 {
13373 { 0, 0, 0, 0 },
13374 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13375 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b2800 }
13376 },
13377/* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
13378 {
13379 { 0, 0, 0, 0 },
13380 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13381 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b2c0000 }
13382 },
13383/* xchg.w r2,${Dsp-16-u8}[sb] */
13384 {
13385 { 0, 0, 0, 0 },
13386 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13387 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b2a00 }
13388 },
13389/* xchg.w r2,${Dsp-16-u16}[sb] */
13390 {
13391 { 0, 0, 0, 0 },
13392 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13393 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b2e0000 }
13394 },
13395/* xchg.w r2,${Dsp-16-s8}[fb] */
13396 {
13397 { 0, 0, 0, 0 },
13398 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13399 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b2b00 }
13400 },
13401/* xchg.w r2,${Dsp-16-u16} */
13402 {
13403 { 0, 0, 0, 0 },
13404 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } },
13405 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b2f0000 }
13406 },
13407/* xchg.w r1,$Dst16RnHI */
13408 {
13409 { 0, 0, 0, 0 },
13410 { { MNEM, ' ', 'r', '1', ',', OP (DST16RNHI), 0 } },
13411 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b10 }
13412 },
13413/* xchg.w r1,$Dst16AnHI */
13414 {
13415 { 0, 0, 0, 0 },
13416 { { MNEM, ' ', 'r', '1', ',', OP (DST16ANHI), 0 } },
13417 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b14 }
13418 },
13419/* xchg.w r1,[$Dst16An] */
13420 {
13421 { 0, 0, 0, 0 },
13422 { { MNEM, ' ', 'r', '1', ',', '[', OP (DST16AN), ']', 0 } },
13423 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b16 }
13424 },
13425/* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
13426 {
13427 { 0, 0, 0, 0 },
13428 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13429 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b1800 }
13430 },
13431/* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
13432 {
13433 { 0, 0, 0, 0 },
13434 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13435 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b1c0000 }
13436 },
13437/* xchg.w r1,${Dsp-16-u8}[sb] */
13438 {
13439 { 0, 0, 0, 0 },
13440 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13441 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b1a00 }
13442 },
13443/* xchg.w r1,${Dsp-16-u16}[sb] */
13444 {
13445 { 0, 0, 0, 0 },
13446 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13447 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b1e0000 }
13448 },
13449/* xchg.w r1,${Dsp-16-s8}[fb] */
13450 {
13451 { 0, 0, 0, 0 },
13452 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13453 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b1b00 }
13454 },
13455/* xchg.w r1,${Dsp-16-u16} */
13456 {
13457 { 0, 0, 0, 0 },
13458 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } },
13459 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b1f0000 }
13460 },
a1a280bb 13461/* xchg.w r0,$Dst16RnHI */
49f58d10
JB		 13462 {
13463 { 0, 0, 0, 0 },
a1a280bb
DD		 13464 { { MNEM, ' ', 'r', '0', ',', OP (DST16RNHI), 0 } },
13465 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b00 }
49f58d10 13466 },
a1a280bb 13467/* xchg.w r0,$Dst16AnHI */
49f58d10
JB		 13468 {
13469 { 0, 0, 0, 0 },
a1a280bb
DD		 13470 { { MNEM, ' ', 'r', '0', ',', OP (DST16ANHI), 0 } },
13471 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b04 }
49f58d10
JB		 13472 },
13473/* xchg.w r0,[$Dst16An] */
13474 {
13475 { 0, 0, 0, 0 },
13476 { { MNEM, ' ', 'r', '0', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13477 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b06 }
49f58d10
JB		 13478 },
13479/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
13480 {
13481 { 0, 0, 0, 0 },
13482 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13483 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b0800 }
49f58d10
JB		 13484 },
13485/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
13486 {
13487 { 0, 0, 0, 0 },
13488 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13489 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b0c0000 }
49f58d10
JB		 13490 },
13491/* xchg.w r0,${Dsp-16-u8}[sb] */
13492 {
13493 { 0, 0, 0, 0 },
13494 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13495 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b0a00 }
49f58d10
JB		 13496 },
13497/* xchg.w r0,${Dsp-16-u16}[sb] */
13498 {
13499 { 0, 0, 0, 0 },
13500 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13501 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b0e0000 }
49f58d10
JB		 13502 },
13503/* xchg.w r0,${Dsp-16-s8}[fb] */
13504 {
13505 { 0, 0, 0, 0 },
13506 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13507 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b0b00 }
49f58d10
JB		 13508 },
13509/* xchg.w r0,${Dsp-16-u16} */
13510 {
13511 { 0, 0, 0, 0 },
13512 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13513 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b0f0000 }
49f58d10
JB		 13514 },
13515/* xchg.b r1h,$Dst16RnQI */
13516 {
13517 { 0, 0, 0, 0 },
13518 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
a1a280bb 13519 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a30 }
49f58d10
JB		 13520 },
13521/* xchg.b r1h,$Dst16AnQI */
13522 {
13523 { 0, 0, 0, 0 },
13524 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
a1a280bb 13525 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a34 }
49f58d10
JB		 13526 },
13527/* xchg.b r1h,[$Dst16An] */
13528 {
13529 { 0, 0, 0, 0 },
13530 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13531 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a36 }
49f58d10
JB		 13532 },
13533/* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
13534 {
13535 { 0, 0, 0, 0 },
13536 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13537 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a3800 }
49f58d10
JB		 13538 },
13539/* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
13540 {
13541 { 0, 0, 0, 0 },
13542 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13543 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a3c0000 }
49f58d10
JB		 13544 },
13545/* xchg.b r1h,${Dsp-16-u8}[sb] */
13546 {
13547 { 0, 0, 0, 0 },
13548 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13549 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a3a00 }
49f58d10
JB		 13550 },
13551/* xchg.b r1h,${Dsp-16-u16}[sb] */
13552 {
13553 { 0, 0, 0, 0 },
13554 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13555 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a3e0000 }
49f58d10
JB		 13556 },
13557/* xchg.b r1h,${Dsp-16-s8}[fb] */
13558 {
13559 { 0, 0, 0, 0 },
13560 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13561 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a3b00 }
49f58d10
JB		 13562 },
13563/* xchg.b r1h,${Dsp-16-u16} */
13564 {
13565 { 0, 0, 0, 0 },
13566 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13567 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a3f0000 }
49f58d10
JB		 13568 },
13569/* xchg.b r1l,$Dst16RnQI */
13570 {
13571 { 0, 0, 0, 0 },
13572 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16RNQI), 0 } },
a1a280bb 13573 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a20 }
49f58d10
JB		 13574 },
13575/* xchg.b r1l,$Dst16AnQI */
13576 {
13577 { 0, 0, 0, 0 },
13578 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16ANQI), 0 } },
a1a280bb 13579 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a24 }
49f58d10
JB		 13580 },
13581/* xchg.b r1l,[$Dst16An] */
13582 {
13583 { 0, 0, 0, 0 },
13584 { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13585 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a26 }
49f58d10
JB		 13586 },
13587/* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
13588 {
13589 { 0, 0, 0, 0 },
13590 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13591 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a2800 }
49f58d10
JB		 13592 },
13593/* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
13594 {
13595 { 0, 0, 0, 0 },
13596 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13597 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a2c0000 }
49f58d10
JB		 13598 },
13599/* xchg.b r1l,${Dsp-16-u8}[sb] */
13600 {
13601 { 0, 0, 0, 0 },
13602 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13603 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a2a00 }
49f58d10
JB		 13604 },
13605/* xchg.b r1l,${Dsp-16-u16}[sb] */
13606 {
13607 { 0, 0, 0, 0 },
13608 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13609 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a2e0000 }
49f58d10
JB		 13610 },
13611/* xchg.b r1l,${Dsp-16-s8}[fb] */
13612 {
13613 { 0, 0, 0, 0 },
13614 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13615 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a2b00 }
49f58d10
JB		 13616 },
13617/* xchg.b r1l,${Dsp-16-u16} */
13618 {
13619 { 0, 0, 0, 0 },
13620 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13621 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a2f0000 }
49f58d10
JB		 13622 },
13623/* xchg.b r0h,$Dst16RnQI */
13624 {
13625 { 0, 0, 0, 0 },
13626 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16RNQI), 0 } },
a1a280bb 13627 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a10 }
49f58d10
JB		 13628 },
13629/* xchg.b r0h,$Dst16AnQI */
13630 {
13631 { 0, 0, 0, 0 },
13632 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16ANQI), 0 } },
a1a280bb 13633 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a14 }
49f58d10
JB		 13634 },
13635/* xchg.b r0h,[$Dst16An] */
13636 {
13637 { 0, 0, 0, 0 },
13638 { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13639 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a16 }
49f58d10
JB		 13640 },
13641/* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
13642 {
13643 { 0, 0, 0, 0 },
13644 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13645 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a1800 }
49f58d10
JB		 13646 },
13647/* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
13648 {
13649 { 0, 0, 0, 0 },
13650 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13651 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a1c0000 }
49f58d10
JB		 13652 },
13653/* xchg.b r0h,${Dsp-16-u8}[sb] */
13654 {
13655 { 0, 0, 0, 0 },
13656 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13657 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a1a00 }
49f58d10
JB		 13658 },
13659/* xchg.b r0h,${Dsp-16-u16}[sb] */
13660 {
13661 { 0, 0, 0, 0 },
13662 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13663 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a1e0000 }
49f58d10
JB		 13664 },
13665/* xchg.b r0h,${Dsp-16-s8}[fb] */
13666 {
13667 { 0, 0, 0, 0 },
13668 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13669 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a1b00 }
49f58d10
JB		 13670 },
13671/* xchg.b r0h,${Dsp-16-u16} */
13672 {
13673 { 0, 0, 0, 0 },
13674 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13675 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a1f0000 }
49f58d10
JB		 13676 },
13677/* xchg.b r0l,$Dst16RnQI */
13678 {
13679 { 0, 0, 0, 0 },
13680 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
a1a280bb 13681 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a00 }
49f58d10
JB		 13682 },
13683/* xchg.b r0l,$Dst16AnQI */
13684 {
13685 { 0, 0, 0, 0 },
13686 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
a1a280bb 13687 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a04 }
49f58d10
JB		 13688 },
13689/* xchg.b r0l,[$Dst16An] */
13690 {
13691 { 0, 0, 0, 0 },
13692 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13693 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a06 }
49f58d10
JB		 13694 },
13695/* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
13696 {
13697 { 0, 0, 0, 0 },
13698 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13699 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a0800 }
49f58d10
JB		 13700 },
13701/* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
13702 {
13703 { 0, 0, 0, 0 },
13704 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13705 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a0c0000 }
49f58d10
JB		 13706 },
13707/* xchg.b r0l,${Dsp-16-u8}[sb] */
13708 {
13709 { 0, 0, 0, 0 },
13710 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13711 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a0a00 }
49f58d10
JB		 13712 },
13713/* xchg.b r0l,${Dsp-16-u16}[sb] */
13714 {
13715 { 0, 0, 0, 0 },
13716 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13717 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a0e0000 }
49f58d10
JB		 13718 },
13719/* xchg.b r0l,${Dsp-16-s8}[fb] */
13720 {
13721 { 0, 0, 0, 0 },
13722 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13723 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a0b00 }
49f58d10
JB		 13724 },
13725/* xchg.b r0l,${Dsp-16-u16} */
13726 {
13727 { 0, 0, 0, 0 },
13728 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13729 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a0f0000 }
49f58d10
JB		 13730 },
13731/* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
13732 {
13733 { 0, 0, 0, 0 },
13734 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
13735 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2d000000 }
13736 },
13737/* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
13738 {
13739 { 0, 0, 0, 0 },
13740 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
13741 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3d000000 }
13742 },
13743/* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
13744 {
13745 { 0, 0, 0, 0 },
13746 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
13747 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1d000000 }
13748 },
13749/* tst.w${S} #${Imm-8-HI},r0 */
13750 {
13751 { 0, 0, 0, 0 },
13752 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
13753 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xd0000 }
13754 },
13755/* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
13756 {
13757 { 0, 0, 0, 0 },
13758 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
13759 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2c0000 }
13760 },
13761/* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
13762 {
13763 { 0, 0, 0, 0 },
13764 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
13765 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3c0000 }
13766 },
13767/* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
13768 {
13769 { 0, 0, 0, 0 },
13770 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
13771 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1c000000 }
13772 },
13773/* tst.b${S} #${Imm-8-QI},r0l */
13774 {
13775 { 0, 0, 0, 0 },
13776 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
13777 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xc00 }
13778 },
f75eb1c0 13779/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 13780 {
13781 { 0, 0, 0, 0 },
f75eb1c0 13782 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 13783 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990900 }
13784 },
f75eb1c0 13785/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
49f58d10
JB		 13786 {
13787 { 0, 0, 0, 0 },
f75eb1c0 13788 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 13789 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992900 }
13790 },
f75eb1c0 13791/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
49f58d10
JB		 13792 {
13793 { 0, 0, 0, 0 },
f75eb1c0 13794 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 13795 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993900 }
13796 },
f75eb1c0 13797/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 13798 {
13799 { 0, 0, 0, 0 },
f75eb1c0 13800 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 13801 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918900 }
13802 },
f75eb1c0 13803/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
49f58d10
JB		 13804 {
13805 { 0, 0, 0, 0 },
f75eb1c0 13806 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 13807 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a900 }
13808 },
f75eb1c0 13809/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
49f58d10
JB		 13810 {
13811 { 0, 0, 0, 0 },
f75eb1c0 13812 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 13813 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b900 }
13814 },
f75eb1c0 13815/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 13816 {
13817 { 0, 0, 0, 0 },
f75eb1c0 13818 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13819 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910900 }
13820 },
f75eb1c0 13821/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 13822 {
13823 { 0, 0, 0, 0 },
f75eb1c0 13824 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13825 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912900 }
13826 },
f75eb1c0 13827/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 13828 {
13829 { 0, 0, 0, 0 },
f75eb1c0 13830 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13831 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913900 }
13832 },
f75eb1c0 13833/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 13834 {
13835 { 0, 0, 0, 0 },
f75eb1c0 13836 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13837 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930900 }
13838 },
f75eb1c0 13839/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 13840 {
13841 { 0, 0, 0, 0 },
f75eb1c0 13842 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13843 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932900 }
13844 },
f75eb1c0 13845/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 13846 {
13847 { 0, 0, 0, 0 },
f75eb1c0 13848 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13849 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933900 }
13850 },
f75eb1c0 13851/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 13852 {
13853 { 0, 0, 0, 0 },
f75eb1c0 13854 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13855 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950900 }
13856 },
f75eb1c0 13857/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 13858 {
13859 { 0, 0, 0, 0 },
f75eb1c0 13860 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13861 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952900 }
13862 },
f75eb1c0 13863/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 13864 {
13865 { 0, 0, 0, 0 },
f75eb1c0 13866 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13867 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953900 }
13868 },
f75eb1c0 13869/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 13870 {
13871 { 0, 0, 0, 0 },
f75eb1c0 13872 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13873 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970900 }
13874 },
f75eb1c0 13875/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 13876 {
13877 { 0, 0, 0, 0 },
f75eb1c0 13878 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13879 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972900 }
13880 },
f75eb1c0 13881/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 13882 {
13883 { 0, 0, 0, 0 },
f75eb1c0 13884 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 13885 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973900 }
13886 },
f75eb1c0 13887/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
49f58d10
JB		 13888 {
13889 { 0, 0, 0, 0 },
f75eb1c0 13890 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 13891 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938900 }
13892 },
f75eb1c0 13893/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
49f58d10
JB		 13894 {
13895 { 0, 0, 0, 0 },
f75eb1c0 13896 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 13897 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a900 }
13898 },
f75eb1c0 13899/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
49f58d10
JB		 13900 {
13901 { 0, 0, 0, 0 },
f75eb1c0 13902 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 13903 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b900 }
13904 },
f75eb1c0 13905/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
49f58d10
JB		 13906 {
13907 { 0, 0, 0, 0 },
f75eb1c0 13908 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 13909 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958900 }
13910 },
f75eb1c0 13911/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
49f58d10
JB		 13912 {
13913 { 0, 0, 0, 0 },
f75eb1c0 13914 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 13915 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a900 }
13916 },
f75eb1c0 13917/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
49f58d10
JB		 13918 {
13919 { 0, 0, 0, 0 },
f75eb1c0 13920 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 13921 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b900 }
13922 },
f75eb1c0 13923/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
49f58d10
JB		 13924 {
13925 { 0, 0, 0, 0 },
f75eb1c0 13926 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 13927 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c900 }
13928 },
f75eb1c0 13929/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
49f58d10
JB		 13930 {
13931 { 0, 0, 0, 0 },
f75eb1c0 13932 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 13933 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e900 }
13934 },
f75eb1c0 13935/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
49f58d10
JB		 13936 {
13937 { 0, 0, 0, 0 },
f75eb1c0 13938 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 13939 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f900 }
13940 },
f75eb1c0 13941/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
49f58d10
JB		 13942 {
13943 { 0, 0, 0, 0 },
f75eb1c0 13944 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 13945 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c900 }
13946 },
f75eb1c0 13947/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
49f58d10
JB		 13948 {
13949 { 0, 0, 0, 0 },
f75eb1c0 13950 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 13951 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e900 }
13952 },
f75eb1c0 13953/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
49f58d10
JB		 13954 {
13955 { 0, 0, 0, 0 },
f75eb1c0 13956 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 13957 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f900 }
13958 },
f75eb1c0 13959/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
49f58d10
JB		 13960 {
13961 { 0, 0, 0, 0 },
f75eb1c0 13962 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 13963 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c900 }
13964 },
f75eb1c0 13965/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
49f58d10
JB		 13966 {
13967 { 0, 0, 0, 0 },
f75eb1c0 13968 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 13969 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e900 }
13970 },
f75eb1c0 13971/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
49f58d10
JB		 13972 {
13973 { 0, 0, 0, 0 },
f75eb1c0 13974 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 13975 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f900 }
13976 },
f75eb1c0 13977/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
49f58d10
JB		 13978 {
13979 { 0, 0, 0, 0 },
f75eb1c0 13980 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 13981 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978900 }
13982 },
f75eb1c0 13983/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
49f58d10
JB		 13984 {
13985 { 0, 0, 0, 0 },
f75eb1c0 13986 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 13987 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a900 }
13988 },
f75eb1c0 13989/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
49f58d10
JB		 13990 {
13991 { 0, 0, 0, 0 },
f75eb1c0 13992 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 13993 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b900 }
13994 },
f75eb1c0 13995/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 13996 {
13997 { 0, 0, 0, 0 },
f75eb1c0 13998 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 13999 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90900 }
14000 },
f75eb1c0 14001/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
49f58d10
JB		 14002 {
14003 { 0, 0, 0, 0 },
f75eb1c0 14004 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14005 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92900 }
14006 },
f75eb1c0 14007/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
49f58d10
JB		 14008 {
14009 { 0, 0, 0, 0 },
f75eb1c0 14010 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14011 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93900 }
14012 },
f75eb1c0 14013/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
49f58d10
JB		 14014 {
14015 { 0, 0, 0, 0 },
f75eb1c0 14016 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14017 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93900 }
14018 },
f75eb1c0 14019/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 14020 {
14021 { 0, 0, 0, 0 },
f75eb1c0 14022 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14023 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18900 }
14024 },
f75eb1c0 14025/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
49f58d10
JB		 14026 {
14027 { 0, 0, 0, 0 },
f75eb1c0 14028 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14029 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a900 }
14030 },
f75eb1c0 14031/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
49f58d10
JB		 14032 {
14033 { 0, 0, 0, 0 },
f75eb1c0 14034 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14035 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b900 }
14036 },
f75eb1c0 14037/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
49f58d10
JB		 14038 {
14039 { 0, 0, 0, 0 },
f75eb1c0 14040 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14041 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b900 }
14042 },
f75eb1c0 14043/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14044 {
14045 { 0, 0, 0, 0 },
f75eb1c0 14046 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14047 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10900 }
14048 },
f75eb1c0 14049/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 14050 {
14051 { 0, 0, 0, 0 },
f75eb1c0 14052 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14053 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12900 }
14054 },
f75eb1c0 14055/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 14056 {
14057 { 0, 0, 0, 0 },
f75eb1c0 14058 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14059 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13900 }
14060 },
f75eb1c0 14061/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
49f58d10
JB		 14062 {
14063 { 0, 0, 0, 0 },
f75eb1c0 14064 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14065 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13900 }
14066 },
f75eb1c0 14067/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14068 {
14069 { 0, 0, 0, 0 },
f75eb1c0 14070 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14071 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30900 }
14072 },
f75eb1c0 14073/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14074 {
14075 { 0, 0, 0, 0 },
f75eb1c0 14076 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14077 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32900 }
14078 },
f75eb1c0 14079/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14080 {
14081 { 0, 0, 0, 0 },
f75eb1c0 14082 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14083 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33900 }
14084 },
f75eb1c0 14085/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14086 {
14087 { 0, 0, 0, 0 },
f75eb1c0 14088 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14089 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33900 }
14090 },
f75eb1c0 14091/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14092 {
14093 { 0, 0, 0, 0 },
f75eb1c0 14094 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14095 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50900 }
14096 },
f75eb1c0 14097/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14098 {
14099 { 0, 0, 0, 0 },
f75eb1c0 14100 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14101 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52900 }
14102 },
f75eb1c0 14103/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14104 {
14105 { 0, 0, 0, 0 },
f75eb1c0 14106 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14107 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53900 }
14108 },
f75eb1c0 14109/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14110 {
14111 { 0, 0, 0, 0 },
f75eb1c0 14112 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14113 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53900 }
14114 },
f75eb1c0 14115/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14116 {
14117 { 0, 0, 0, 0 },
f75eb1c0 14118 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14119 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70900 }
14120 },
f75eb1c0 14121/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14122 {
14123 { 0, 0, 0, 0 },
f75eb1c0 14124 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14125 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72900 }
14126 },
f75eb1c0 14127/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14128 {
14129 { 0, 0, 0, 0 },
f75eb1c0 14130 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14131 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73900 }
14132 },
f75eb1c0 14133/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14134 {
14135 { 0, 0, 0, 0 },
f75eb1c0 14136 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14137 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73900 }
14138 },
f75eb1c0 14139/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
49f58d10
JB		 14140 {
14141 { 0, 0, 0, 0 },
f75eb1c0 14142 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14143 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38900 }
14144 },
f75eb1c0 14145/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
49f58d10
JB		 14146 {
14147 { 0, 0, 0, 0 },
f75eb1c0 14148 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14149 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a900 }
14150 },
f75eb1c0 14151/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
49f58d10
JB		 14152 {
14153 { 0, 0, 0, 0 },
f75eb1c0 14154 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14155 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b900 }
14156 },
f75eb1c0 14157/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
49f58d10
JB		 14158 {
14159 { 0, 0, 0, 0 },
f75eb1c0 14160 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14161 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b900 }
14162 },
f75eb1c0 14163/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
49f58d10
JB		 14164 {
14165 { 0, 0, 0, 0 },
f75eb1c0 14166 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14167 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58900 }
14168 },
f75eb1c0 14169/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
49f58d10
JB		 14170 {
14171 { 0, 0, 0, 0 },
f75eb1c0 14172 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14173 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a900 }
14174 },
f75eb1c0 14175/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
49f58d10
JB		 14176 {
14177 { 0, 0, 0, 0 },
f75eb1c0 14178 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14179 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b900 }
14180 },
f75eb1c0 14181/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
49f58d10
JB		 14182 {
14183 { 0, 0, 0, 0 },
f75eb1c0 14184 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14185 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b900 }
14186 },
f75eb1c0 14187/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
49f58d10
JB		 14188 {
14189 { 0, 0, 0, 0 },
f75eb1c0 14190 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14191 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c900 }
14192 },
f75eb1c0 14193/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
49f58d10
JB		 14194 {
14195 { 0, 0, 0, 0 },
f75eb1c0 14196 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14197 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e900 }
14198 },
f75eb1c0 14199/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
49f58d10
JB		 14200 {
14201 { 0, 0, 0, 0 },
f75eb1c0 14202 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14203 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f900 }
14204 },
f75eb1c0 14205/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
49f58d10
JB		 14206 {
14207 { 0, 0, 0, 0 },
f75eb1c0 14208 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14209 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f900 }
14210 },
f75eb1c0 14211/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
49f58d10
JB		 14212 {
14213 { 0, 0, 0, 0 },
f75eb1c0 14214 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14215 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c900 }
14216 },
f75eb1c0 14217/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
49f58d10
JB		 14218 {
14219 { 0, 0, 0, 0 },
f75eb1c0 14220 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14221 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e900 }
14222 },
f75eb1c0 14223/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
49f58d10
JB		 14224 {
14225 { 0, 0, 0, 0 },
f75eb1c0 14226 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14227 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f900 }
14228 },
f75eb1c0 14229/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
49f58d10
JB		 14230 {
14231 { 0, 0, 0, 0 },
f75eb1c0 14232 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14233 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f900 }
14234 },
f75eb1c0 14235/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
49f58d10
JB		 14236 {
14237 { 0, 0, 0, 0 },
f75eb1c0 14238 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14239 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c900 }
14240 },
f75eb1c0 14241/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
49f58d10
JB		 14242 {
14243 { 0, 0, 0, 0 },
f75eb1c0 14244 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14245 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e900 }
14246 },
f75eb1c0 14247/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
49f58d10
JB		 14248 {
14249 { 0, 0, 0, 0 },
f75eb1c0 14250 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14251 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f900 }
14252 },
f75eb1c0 14253/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
49f58d10
JB		 14254 {
14255 { 0, 0, 0, 0 },
f75eb1c0 14256 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14257 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f900 }
14258 },
f75eb1c0 14259/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
49f58d10
JB		 14260 {
14261 { 0, 0, 0, 0 },
f75eb1c0 14262 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14263 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78900 }
14264 },
f75eb1c0 14265/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
49f58d10
JB		 14266 {
14267 { 0, 0, 0, 0 },
f75eb1c0 14268 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14269 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a900 }
14270 },
f75eb1c0 14271/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
49f58d10
JB		 14272 {
14273 { 0, 0, 0, 0 },
f75eb1c0 14274 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14275 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b900 }
14276 },
f75eb1c0 14277/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
49f58d10
JB		 14278 {
14279 { 0, 0, 0, 0 },
f75eb1c0 14280 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14281 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b900 }
14282 },
f75eb1c0 14283/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 14284 {
14285 { 0, 0, 0, 0 },
f75eb1c0 14286 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14287 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90900 }
14288 },
f75eb1c0 14289/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
49f58d10
JB		 14290 {
14291 { 0, 0, 0, 0 },
f75eb1c0 14292 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14293 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92900 }
14294 },
f75eb1c0 14295/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 14296 {
14297 { 0, 0, 0, 0 },
f75eb1c0 14298 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14299 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18900 }
14300 },
f75eb1c0 14301/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
49f58d10
JB		 14302 {
14303 { 0, 0, 0, 0 },
f75eb1c0 14304 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14305 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a900 }
14306 },
f75eb1c0 14307/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14308 {
14309 { 0, 0, 0, 0 },
f75eb1c0 14310 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14311 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10900 }
14312 },
f75eb1c0 14313/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
49f58d10
JB		 14314 {
14315 { 0, 0, 0, 0 },
f75eb1c0 14316 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14317 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12900 }
14318 },
f75eb1c0 14319/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14320 {
14321 { 0, 0, 0, 0 },
f75eb1c0 14322 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14323 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30900 }
14324 },
f75eb1c0 14325/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14326 {
14327 { 0, 0, 0, 0 },
f75eb1c0 14328 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14329 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32900 }
14330 },
f75eb1c0 14331/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14332 {
14333 { 0, 0, 0, 0 },
f75eb1c0 14334 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14335 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50900 }
14336 },
f75eb1c0 14337/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14338 {
14339 { 0, 0, 0, 0 },
f75eb1c0 14340 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14341 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52900 }
14342 },
f75eb1c0 14343/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14344 {
14345 { 0, 0, 0, 0 },
f75eb1c0 14346 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14347 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70900 }
14348 },
f75eb1c0 14349/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14350 {
14351 { 0, 0, 0, 0 },
f75eb1c0 14352 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14353 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72900 }
14354 },
f75eb1c0 14355/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
49f58d10
JB		 14356 {
14357 { 0, 0, 0, 0 },
f75eb1c0 14358 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14359 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38900 }
14360 },
f75eb1c0 14361/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
49f58d10
JB		 14362 {
14363 { 0, 0, 0, 0 },
f75eb1c0 14364 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14365 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a900 }
14366 },
f75eb1c0 14367/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
49f58d10
JB		 14368 {
14369 { 0, 0, 0, 0 },
f75eb1c0 14370 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14371 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58900 }
14372 },
f75eb1c0 14373/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
49f58d10
JB		 14374 {
14375 { 0, 0, 0, 0 },
f75eb1c0 14376 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14377 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a900 }
14378 },
f75eb1c0 14379/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
49f58d10
JB		 14380 {
14381 { 0, 0, 0, 0 },
f75eb1c0 14382 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14383 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c900 }
14384 },
f75eb1c0 14385/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
49f58d10
JB		 14386 {
14387 { 0, 0, 0, 0 },
f75eb1c0 14388 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14389 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e900 }
14390 },
f75eb1c0 14391/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
49f58d10
JB		 14392 {
14393 { 0, 0, 0, 0 },
f75eb1c0 14394 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14395 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c900 }
14396 },
f75eb1c0 14397/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
49f58d10
JB		 14398 {
14399 { 0, 0, 0, 0 },
f75eb1c0 14400 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14401 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e900 }
14402 },
f75eb1c0 14403/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
49f58d10
JB		 14404 {
14405 { 0, 0, 0, 0 },
f75eb1c0 14406 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 14407 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c900 }
14408 },
f75eb1c0 14409/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
49f58d10
JB		 14410 {
14411 { 0, 0, 0, 0 },
f75eb1c0 14412 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 14413 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e900 }
14414 },
f75eb1c0 14415/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
49f58d10
JB		 14416 {
14417 { 0, 0, 0, 0 },
f75eb1c0 14418 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 14419 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78900 }
14420 },
f75eb1c0 14421/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
49f58d10
JB		 14422 {
14423 { 0, 0, 0, 0 },
f75eb1c0 14424 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 14425 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a900 }
14426 },
f75eb1c0 14427/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
49f58d10
JB		 14428 {
14429 { 0, 0, 0, 0 },
f75eb1c0 14430 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14431 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c909 }
14432 },
f75eb1c0 14433/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
49f58d10
JB		 14434 {
14435 { 0, 0, 0, 0 },
f75eb1c0 14436 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14437 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18929 }
14438 },
f75eb1c0 14439/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 14440 {
14441 { 0, 0, 0, 0 },
f75eb1c0 14442 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14443 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18909 }
14444 },
f75eb1c0 14445/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
49f58d10
JB		 14446 {
14447 { 0, 0, 0, 0 },
f75eb1c0 14448 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14449 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c189 }
14450 },
f75eb1c0 14451/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
49f58d10
JB		 14452 {
14453 { 0, 0, 0, 0 },
f75eb1c0 14454 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14455 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a9 }
14456 },
f75eb1c0 14457/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 14458 {
14459 { 0, 0, 0, 0 },
f75eb1c0 14460 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14461 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18189 }
14462 },
f75eb1c0 14463/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
49f58d10
JB		 14464 {
14465 { 0, 0, 0, 0 },
f75eb1c0 14466 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14467 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c109 }
14468 },
f75eb1c0 14469/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
49f58d10
JB		 14470 {
14471 { 0, 0, 0, 0 },
f75eb1c0 14472 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14473 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18129 }
14474 },
f75eb1c0 14475/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14476 {
14477 { 0, 0, 0, 0 },
f75eb1c0 14478 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14479 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18109 }
14480 },
f75eb1c0 14481/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14482 {
14483 { 0, 0, 0, 0 },
f75eb1c0 14484 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14485 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30900 }
14486 },
f75eb1c0 14487/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14488 {
14489 { 0, 0, 0, 0 },
f75eb1c0 14490 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14491 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832900 }
14492 },
f75eb1c0 14493/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14494 {
14495 { 0, 0, 0, 0 },
f75eb1c0 14496 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14497 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830900 }
14498 },
f75eb1c0 14499/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14500 {
14501 { 0, 0, 0, 0 },
f75eb1c0 14502 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14503 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50900 }
14504 },
f75eb1c0 14505/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14506 {
14507 { 0, 0, 0, 0 },
f75eb1c0 14508 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14509 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852900 }
14510 },
f75eb1c0 14511/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14512 {
14513 { 0, 0, 0, 0 },
f75eb1c0 14514 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14515 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850900 }
14516 },
f75eb1c0 14517/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14518 {
14519 { 0, 0, 0, 0 },
f75eb1c0 14520 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14521 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70900 }
14522 },
f75eb1c0 14523/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14524 {
14525 { 0, 0, 0, 0 },
f75eb1c0 14526 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14527 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872900 }
14528 },
f75eb1c0 14529/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14530 {
14531 { 0, 0, 0, 0 },
f75eb1c0 14532 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14533 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870900 }
14534 },
f75eb1c0 14535/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
49f58d10
JB		 14536 {
14537 { 0, 0, 0, 0 },
f75eb1c0 14538 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14539 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38900 }
14540 },
f75eb1c0 14541/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
49f58d10
JB		 14542 {
14543 { 0, 0, 0, 0 },
f75eb1c0 14544 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14545 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a900 }
14546 },
f75eb1c0 14547/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
49f58d10
JB		 14548 {
14549 { 0, 0, 0, 0 },
f75eb1c0 14550 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14551 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838900 }
14552 },
f75eb1c0 14553/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
49f58d10
JB		 14554 {
14555 { 0, 0, 0, 0 },
f75eb1c0 14556 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14557 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58900 }
14558 },
f75eb1c0 14559/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
49f58d10
JB		 14560 {
14561 { 0, 0, 0, 0 },
f75eb1c0 14562 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14563 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a900 }
14564 },
f75eb1c0 14565/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
49f58d10
JB		 14566 {
14567 { 0, 0, 0, 0 },
f75eb1c0 14568 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14569 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858900 }
14570 },
f75eb1c0 14571/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
49f58d10
JB		 14572 {
14573 { 0, 0, 0, 0 },
f75eb1c0 14574 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14575 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c900 }
14576 },
f75eb1c0 14577/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
49f58d10
JB		 14578 {
14579 { 0, 0, 0, 0 },
f75eb1c0 14580 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14581 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e900 }
14582 },
f75eb1c0 14583/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
49f58d10
JB		 14584 {
14585 { 0, 0, 0, 0 },
f75eb1c0 14586 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14587 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c900 }
14588 },
f75eb1c0 14589/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
49f58d10
JB		 14590 {
14591 { 0, 0, 0, 0 },
f75eb1c0 14592 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14593 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c900 }
14594 },
f75eb1c0 14595/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
49f58d10
JB		 14596 {
14597 { 0, 0, 0, 0 },
f75eb1c0 14598 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14599 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e900 }
14600 },
f75eb1c0 14601/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
49f58d10
JB		 14602 {
14603 { 0, 0, 0, 0 },
f75eb1c0 14604 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14605 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c900 }
14606 },
f75eb1c0 14607/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
49f58d10
JB		 14608 {
14609 { 0, 0, 0, 0 },
f75eb1c0 14610 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 14611 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c900 }
14612 },
f75eb1c0 14613/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
49f58d10
JB		 14614 {
14615 { 0, 0, 0, 0 },
f75eb1c0 14616 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 14617 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e900 }
14618 },
f75eb1c0 14619/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
49f58d10
JB		 14620 {
14621 { 0, 0, 0, 0 },
f75eb1c0 14622 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 14623 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c900 }
14624 },
f75eb1c0 14625/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
49f58d10
JB		 14626 {
14627 { 0, 0, 0, 0 },
f75eb1c0 14628 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 14629 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78900 }
14630 },
f75eb1c0 14631/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
49f58d10
JB		 14632 {
14633 { 0, 0, 0, 0 },
f75eb1c0 14634 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 14635 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a900 }
14636 },
f75eb1c0 14637/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
49f58d10
JB		 14638 {
14639 { 0, 0, 0, 0 },
f75eb1c0 14640 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 14641 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878900 }
14642 },
f75eb1c0 14643/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 14644 {
14645 { 0, 0, 0, 0 },
f75eb1c0 14646 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14647 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980900 }
14648 },
f75eb1c0 14649/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
49f58d10
JB		 14650 {
14651 { 0, 0, 0, 0 },
f75eb1c0 14652 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14653 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982900 }
14654 },
f75eb1c0 14655/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
49f58d10
JB		 14656 {
14657 { 0, 0, 0, 0 },
f75eb1c0 14658 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14659 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983900 }
14660 },
f75eb1c0 14661/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 14662 {
14663 { 0, 0, 0, 0 },
f75eb1c0 14664 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14665 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908900 }
14666 },
f75eb1c0 14667/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
49f58d10
JB		 14668 {
14669 { 0, 0, 0, 0 },
f75eb1c0 14670 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14671 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a900 }
14672 },
f75eb1c0 14673/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
49f58d10
JB		 14674 {
14675 { 0, 0, 0, 0 },
f75eb1c0 14676 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14677 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b900 }
14678 },
f75eb1c0 14679/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14680 {
14681 { 0, 0, 0, 0 },
f75eb1c0 14682 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14683 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900900 }
14684 },
f75eb1c0 14685/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 14686 {
14687 { 0, 0, 0, 0 },
f75eb1c0 14688 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14689 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902900 }
14690 },
f75eb1c0 14691/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 14692 {
14693 { 0, 0, 0, 0 },
f75eb1c0 14694 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14695 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903900 }
14696 },
f75eb1c0 14697/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14698 {
14699 { 0, 0, 0, 0 },
f75eb1c0 14700 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14701 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920900 }
14702 },
f75eb1c0 14703/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14704 {
14705 { 0, 0, 0, 0 },
f75eb1c0 14706 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14707 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922900 }
14708 },
f75eb1c0 14709/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14710 {
14711 { 0, 0, 0, 0 },
f75eb1c0 14712 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14713 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923900 }
14714 },
f75eb1c0 14715/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14716 {
14717 { 0, 0, 0, 0 },
f75eb1c0 14718 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14719 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940900 }
14720 },
f75eb1c0 14721/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14722 {
14723 { 0, 0, 0, 0 },
f75eb1c0 14724 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14725 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942900 }
14726 },
f75eb1c0 14727/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14728 {
14729 { 0, 0, 0, 0 },
f75eb1c0 14730 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14731 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943900 }
14732 },
f75eb1c0 14733/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14734 {
14735 { 0, 0, 0, 0 },
f75eb1c0 14736 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14737 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960900 }
14738 },
f75eb1c0 14739/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14740 {
14741 { 0, 0, 0, 0 },
f75eb1c0 14742 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14743 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962900 }
14744 },
f75eb1c0 14745/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14746 {
14747 { 0, 0, 0, 0 },
f75eb1c0 14748 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14749 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963900 }
14750 },
f75eb1c0 14751/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
49f58d10
JB		 14752 {
14753 { 0, 0, 0, 0 },
f75eb1c0 14754 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14755 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928900 }
14756 },
f75eb1c0 14757/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
49f58d10
JB		 14758 {
14759 { 0, 0, 0, 0 },
f75eb1c0 14760 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14761 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a900 }
14762 },
f75eb1c0 14763/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
49f58d10
JB		 14764 {
14765 { 0, 0, 0, 0 },
f75eb1c0 14766 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14767 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b900 }
14768 },
f75eb1c0 14769/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
49f58d10
JB		 14770 {
14771 { 0, 0, 0, 0 },
f75eb1c0 14772 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14773 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948900 }
14774 },
f75eb1c0 14775/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
49f58d10
JB		 14776 {
14777 { 0, 0, 0, 0 },
f75eb1c0 14778 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14779 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a900 }
14780 },
f75eb1c0 14781/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
49f58d10
JB		 14782 {
14783 { 0, 0, 0, 0 },
f75eb1c0 14784 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14785 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b900 }
14786 },
f75eb1c0 14787/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
49f58d10
JB		 14788 {
14789 { 0, 0, 0, 0 },
f75eb1c0 14790 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14791 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c900 }
14792 },
f75eb1c0 14793/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
49f58d10
JB		 14794 {
14795 { 0, 0, 0, 0 },
f75eb1c0 14796 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14797 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e900 }
14798 },
f75eb1c0 14799/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
49f58d10
JB		 14800 {
14801 { 0, 0, 0, 0 },
f75eb1c0 14802 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14803 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f900 }
14804 },
f75eb1c0 14805/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
49f58d10
JB		 14806 {
14807 { 0, 0, 0, 0 },
f75eb1c0 14808 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14809 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c900 }
14810 },
f75eb1c0 14811/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
49f58d10
JB		 14812 {
14813 { 0, 0, 0, 0 },
f75eb1c0 14814 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14815 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e900 }
14816 },
f75eb1c0 14817/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
49f58d10
JB		 14818 {
14819 { 0, 0, 0, 0 },
f75eb1c0 14820 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14821 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f900 }
14822 },
f75eb1c0 14823/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
49f58d10
JB		 14824 {
14825 { 0, 0, 0, 0 },
f75eb1c0 14826 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 14827 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c900 }
14828 },
f75eb1c0 14829/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
49f58d10
JB		 14830 {
14831 { 0, 0, 0, 0 },
f75eb1c0 14832 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 14833 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e900 }
14834 },
f75eb1c0 14835/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
49f58d10
JB		 14836 {
14837 { 0, 0, 0, 0 },
f75eb1c0 14838 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 14839 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f900 }
14840 },
f75eb1c0 14841/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
49f58d10
JB		 14842 {
14843 { 0, 0, 0, 0 },
f75eb1c0 14844 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 14845 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968900 }
14846 },
f75eb1c0 14847/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
49f58d10
JB		 14848 {
14849 { 0, 0, 0, 0 },
f75eb1c0 14850 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 14851 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a900 }
14852 },
f75eb1c0 14853/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
49f58d10
JB		 14854 {
14855 { 0, 0, 0, 0 },
f75eb1c0 14856 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 14857 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b900 }
14858 },
f75eb1c0 14859/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 14860 {
14861 { 0, 0, 0, 0 },
f75eb1c0 14862 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14863 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80900 }
14864 },
f75eb1c0 14865/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
49f58d10
JB		 14866 {
14867 { 0, 0, 0, 0 },
f75eb1c0 14868 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14869 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82900 }
14870 },
f75eb1c0 14871/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
49f58d10
JB		 14872 {
14873 { 0, 0, 0, 0 },
f75eb1c0 14874 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14875 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83900 }
14876 },
f75eb1c0 14877/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
49f58d10
JB		 14878 {
14879 { 0, 0, 0, 0 },
f75eb1c0 14880 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14881 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83900 }
14882 },
f75eb1c0 14883/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 14884 {
14885 { 0, 0, 0, 0 },
f75eb1c0 14886 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14887 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08900 }
14888 },
f75eb1c0 14889/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
49f58d10
JB		 14890 {
14891 { 0, 0, 0, 0 },
f75eb1c0 14892 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14893 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a900 }
14894 },
f75eb1c0 14895/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
49f58d10
JB		 14896 {
14897 { 0, 0, 0, 0 },
f75eb1c0 14898 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14899 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b900 }
14900 },
f75eb1c0 14901/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
49f58d10
JB		 14902 {
14903 { 0, 0, 0, 0 },
f75eb1c0 14904 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14905 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b900 }
14906 },
f75eb1c0 14907/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14908 {
14909 { 0, 0, 0, 0 },
f75eb1c0 14910 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14911 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00900 }
14912 },
f75eb1c0 14913/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 14914 {
14915 { 0, 0, 0, 0 },
f75eb1c0 14916 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14917 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02900 }
14918 },
f75eb1c0 14919/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 14920 {
14921 { 0, 0, 0, 0 },
f75eb1c0 14922 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14923 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03900 }
14924 },
f75eb1c0 14925/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
49f58d10
JB		 14926 {
14927 { 0, 0, 0, 0 },
f75eb1c0 14928 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14929 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03900 }
14930 },
f75eb1c0 14931/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14932 {
14933 { 0, 0, 0, 0 },
f75eb1c0 14934 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14935 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20900 }
14936 },
f75eb1c0 14937/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14938 {
14939 { 0, 0, 0, 0 },
f75eb1c0 14940 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14941 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22900 }
14942 },
f75eb1c0 14943/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14944 {
14945 { 0, 0, 0, 0 },
f75eb1c0 14946 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14947 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23900 }
14948 },
f75eb1c0 14949/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14950 {
14951 { 0, 0, 0, 0 },
f75eb1c0 14952 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14953 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23900 }
14954 },
f75eb1c0 14955/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14956 {
14957 { 0, 0, 0, 0 },
f75eb1c0 14958 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14959 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40900 }
14960 },
f75eb1c0 14961/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14962 {
14963 { 0, 0, 0, 0 },
f75eb1c0 14964 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14965 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42900 }
14966 },
f75eb1c0 14967/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14968 {
14969 { 0, 0, 0, 0 },
f75eb1c0 14970 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14971 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43900 }
14972 },
f75eb1c0 14973/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14974 {
14975 { 0, 0, 0, 0 },
f75eb1c0 14976 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14977 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43900 }
14978 },
f75eb1c0 14979/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14980 {
14981 { 0, 0, 0, 0 },
f75eb1c0 14982 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14983 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60900 }
14984 },
f75eb1c0 14985/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14986 {
14987 { 0, 0, 0, 0 },
f75eb1c0 14988 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14989 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62900 }
14990 },
f75eb1c0 14991/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14992 {
14993 { 0, 0, 0, 0 },
f75eb1c0 14994 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14995 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63900 }
14996 },
f75eb1c0 14997/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14998 {
14999 { 0, 0, 0, 0 },
f75eb1c0 15000 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15001 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63900 }
15002 },
f75eb1c0 15003/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
49f58d10
JB		 15004 {
15005 { 0, 0, 0, 0 },
f75eb1c0 15006 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15007 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28900 }
15008 },
f75eb1c0 15009/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
49f58d10
JB		 15010 {
15011 { 0, 0, 0, 0 },
f75eb1c0 15012 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15013 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a900 }
15014 },
f75eb1c0 15015/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
49f58d10
JB		 15016 {
15017 { 0, 0, 0, 0 },
f75eb1c0 15018 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15019 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b900 }
15020 },
f75eb1c0 15021/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
49f58d10
JB		 15022 {
15023 { 0, 0, 0, 0 },
f75eb1c0 15024 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15025 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b900 }
15026 },
f75eb1c0 15027/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
49f58d10
JB		 15028 {
15029 { 0, 0, 0, 0 },
f75eb1c0 15030 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15031 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48900 }
15032 },
f75eb1c0 15033/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
49f58d10
JB		 15034 {
15035 { 0, 0, 0, 0 },
f75eb1c0 15036 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15037 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a900 }
15038 },
f75eb1c0 15039/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
49f58d10
JB		 15040 {
15041 { 0, 0, 0, 0 },
f75eb1c0 15042 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15043 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b900 }
15044 },
f75eb1c0 15045/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
49f58d10
JB		 15046 {
15047 { 0, 0, 0, 0 },
f75eb1c0 15048 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15049 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b900 }
15050 },
f75eb1c0 15051/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
49f58d10
JB		 15052 {
15053 { 0, 0, 0, 0 },
f75eb1c0 15054 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15055 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c900 }
15056 },
f75eb1c0 15057/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
49f58d10
JB		 15058 {
15059 { 0, 0, 0, 0 },
f75eb1c0 15060 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15061 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e900 }
15062 },
f75eb1c0 15063/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
49f58d10
JB		 15064 {
15065 { 0, 0, 0, 0 },
f75eb1c0 15066 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15067 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f900 }
15068 },
f75eb1c0 15069/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
49f58d10
JB		 15070 {
15071 { 0, 0, 0, 0 },
f75eb1c0 15072 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15073 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f900 }
15074 },
f75eb1c0 15075/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
49f58d10
JB		 15076 {
15077 { 0, 0, 0, 0 },
f75eb1c0 15078 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15079 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c900 }
15080 },
f75eb1c0 15081/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
49f58d10
JB		 15082 {
15083 { 0, 0, 0, 0 },
f75eb1c0 15084 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15085 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e900 }
15086 },
f75eb1c0 15087/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
49f58d10
JB		 15088 {
15089 { 0, 0, 0, 0 },
f75eb1c0 15090 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15091 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f900 }
15092 },
f75eb1c0 15093/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
49f58d10
JB		 15094 {
15095 { 0, 0, 0, 0 },
f75eb1c0 15096 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15097 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f900 }
15098 },
f75eb1c0 15099/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
49f58d10
JB		 15100 {
15101 { 0, 0, 0, 0 },
f75eb1c0 15102 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15103 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c900 }
15104 },
f75eb1c0 15105/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
49f58d10
JB		 15106 {
15107 { 0, 0, 0, 0 },
f75eb1c0 15108 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15109 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e900 }
15110 },
f75eb1c0 15111/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
49f58d10
JB		 15112 {
15113 { 0, 0, 0, 0 },
f75eb1c0 15114 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15115 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f900 }
15116 },
f75eb1c0 15117/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
49f58d10
JB		 15118 {
15119 { 0, 0, 0, 0 },
f75eb1c0 15120 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15121 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f900 }
15122 },
f75eb1c0 15123/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
49f58d10
JB		 15124 {
15125 { 0, 0, 0, 0 },
f75eb1c0 15126 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15127 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68900 }
15128 },
f75eb1c0 15129/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
49f58d10
JB		 15130 {
15131 { 0, 0, 0, 0 },
f75eb1c0 15132 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15133 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a900 }
15134 },
f75eb1c0 15135/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
49f58d10
JB		 15136 {
15137 { 0, 0, 0, 0 },
f75eb1c0 15138 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15139 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b900 }
15140 },
f75eb1c0 15141/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
49f58d10
JB		 15142 {
15143 { 0, 0, 0, 0 },
f75eb1c0 15144 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15145 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b900 }
15146 },
f75eb1c0 15147/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 15148 {
15149 { 0, 0, 0, 0 },
f75eb1c0 15150 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15151 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80900 }
15152 },
f75eb1c0 15153/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
49f58d10
JB		 15154 {
15155 { 0, 0, 0, 0 },
f75eb1c0 15156 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15157 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82900 }
15158 },
f75eb1c0 15159/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 15160 {
15161 { 0, 0, 0, 0 },
f75eb1c0 15162 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15163 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08900 }
15164 },
f75eb1c0 15165/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
49f58d10
JB		 15166 {
15167 { 0, 0, 0, 0 },
f75eb1c0 15168 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15169 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a900 }
15170 },
f75eb1c0 15171/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 15172 {
15173 { 0, 0, 0, 0 },
f75eb1c0 15174 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15175 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00900 }
15176 },
f75eb1c0 15177/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
49f58d10
JB		 15178 {
15179 { 0, 0, 0, 0 },
f75eb1c0 15180 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15181 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02900 }
15182 },
f75eb1c0 15183/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15184 {
15185 { 0, 0, 0, 0 },
f75eb1c0 15186 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15187 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20900 }
15188 },
f75eb1c0 15189/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15190 {
15191 { 0, 0, 0, 0 },
f75eb1c0 15192 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15193 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22900 }
15194 },
f75eb1c0 15195/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15196 {
15197 { 0, 0, 0, 0 },
f75eb1c0 15198 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15199 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40900 }
15200 },
f75eb1c0 15201/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15202 {
15203 { 0, 0, 0, 0 },
f75eb1c0 15204 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15205 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42900 }
15206 },
f75eb1c0 15207/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15208 {
15209 { 0, 0, 0, 0 },
f75eb1c0 15210 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15211 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60900 }
15212 },
f75eb1c0 15213/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15214 {
15215 { 0, 0, 0, 0 },
f75eb1c0 15216 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15217 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62900 }
15218 },
f75eb1c0 15219/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
49f58d10
JB		 15220 {
15221 { 0, 0, 0, 0 },
f75eb1c0 15222 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15223 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28900 }
15224 },
f75eb1c0 15225/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
49f58d10
JB		 15226 {
15227 { 0, 0, 0, 0 },
f75eb1c0 15228 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15229 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a900 }
15230 },
f75eb1c0 15231/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
49f58d10
JB		 15232 {
15233 { 0, 0, 0, 0 },
f75eb1c0 15234 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15235 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48900 }
15236 },
f75eb1c0 15237/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
49f58d10
JB		 15238 {
15239 { 0, 0, 0, 0 },
f75eb1c0 15240 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15241 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a900 }
15242 },
f75eb1c0 15243/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
49f58d10
JB		 15244 {
15245 { 0, 0, 0, 0 },
f75eb1c0 15246 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15247 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c900 }
15248 },
f75eb1c0 15249/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
49f58d10
JB		 15250 {
15251 { 0, 0, 0, 0 },
f75eb1c0 15252 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15253 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e900 }
15254 },
f75eb1c0 15255/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
49f58d10
JB		 15256 {
15257 { 0, 0, 0, 0 },
f75eb1c0 15258 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15259 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c900 }
15260 },
f75eb1c0 15261/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
49f58d10
JB		 15262 {
15263 { 0, 0, 0, 0 },
f75eb1c0 15264 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15265 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e900 }
15266 },
f75eb1c0 15267/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
49f58d10
JB		 15268 {
15269 { 0, 0, 0, 0 },
f75eb1c0 15270 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 15271 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c900 }
15272 },
f75eb1c0 15273/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
49f58d10
JB		 15274 {
15275 { 0, 0, 0, 0 },
f75eb1c0 15276 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 15277 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e900 }
15278 },
f75eb1c0 15279/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
49f58d10
JB		 15280 {
15281 { 0, 0, 0, 0 },
f75eb1c0 15282 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 15283 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68900 }
15284 },
f75eb1c0 15285/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
49f58d10
JB		 15286 {
15287 { 0, 0, 0, 0 },
f75eb1c0 15288 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 15289 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a900 }
15290 },
f75eb1c0 15291/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
49f58d10
JB		 15292 {
15293 { 0, 0, 0, 0 },
f75eb1c0 15294 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15295 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c809 }
15296 },
f75eb1c0 15297/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
49f58d10
JB		 15298 {
15299 { 0, 0, 0, 0 },
f75eb1c0 15300 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15301 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18829 }
15302 },
f75eb1c0 15303/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 15304 {
15305 { 0, 0, 0, 0 },
f75eb1c0 15306 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15307 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18809 }
15308 },
f75eb1c0 15309/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
49f58d10
JB		 15310 {
15311 { 0, 0, 0, 0 },
f75eb1c0 15312 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15313 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c089 }
15314 },
f75eb1c0 15315/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
49f58d10
JB		 15316 {
15317 { 0, 0, 0, 0 },
f75eb1c0 15318 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15319 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a9 }
15320 },
f75eb1c0 15321/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 15322 {
15323 { 0, 0, 0, 0 },
f75eb1c0 15324 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15325 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18089 }
15326 },
f75eb1c0 15327/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
49f58d10
JB		 15328 {
15329 { 0, 0, 0, 0 },
f75eb1c0 15330 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15331 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c009 }
15332 },
f75eb1c0 15333/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
49f58d10
JB		 15334 {
15335 { 0, 0, 0, 0 },
f75eb1c0 15336 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15337 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18029 }
15338 },
f75eb1c0 15339/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 15340 {
15341 { 0, 0, 0, 0 },
f75eb1c0 15342 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15343 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18009 }
15344 },
f75eb1c0 15345/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15346 {
15347 { 0, 0, 0, 0 },
f75eb1c0 15348 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15349 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20900 }
15350 },
f75eb1c0 15351/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15352 {
15353 { 0, 0, 0, 0 },
f75eb1c0 15354 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15355 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822900 }
15356 },
f75eb1c0 15357/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15358 {
15359 { 0, 0, 0, 0 },
f75eb1c0 15360 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15361 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820900 }
15362 },
f75eb1c0 15363/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15364 {
15365 { 0, 0, 0, 0 },
f75eb1c0 15366 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15367 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40900 }
15368 },
f75eb1c0 15369/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15370 {
15371 { 0, 0, 0, 0 },
f75eb1c0 15372 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15373 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842900 }
15374 },
f75eb1c0 15375/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15376 {
15377 { 0, 0, 0, 0 },
f75eb1c0 15378 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15379 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840900 }
15380 },
f75eb1c0 15381/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15382 {
15383 { 0, 0, 0, 0 },
f75eb1c0 15384 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15385 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60900 }
15386 },
f75eb1c0 15387/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15388 {
15389 { 0, 0, 0, 0 },
f75eb1c0 15390 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15391 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862900 }
15392 },
f75eb1c0 15393/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15394 {
15395 { 0, 0, 0, 0 },
f75eb1c0 15396 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15397 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860900 }
15398 },
f75eb1c0 15399/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
49f58d10
JB		 15400 {
15401 { 0, 0, 0, 0 },
f75eb1c0 15402 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15403 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28900 }
15404 },
f75eb1c0 15405/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
49f58d10
JB		 15406 {
15407 { 0, 0, 0, 0 },
f75eb1c0 15408 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15409 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a900 }
15410 },
f75eb1c0 15411/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
49f58d10
JB		 15412 {
15413 { 0, 0, 0, 0 },
f75eb1c0 15414 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15415 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828900 }
15416 },
f75eb1c0 15417/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
49f58d10
JB		 15418 {
15419 { 0, 0, 0, 0 },
f75eb1c0 15420 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15421 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48900 }
15422 },
f75eb1c0 15423/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
49f58d10
JB		 15424 {
15425 { 0, 0, 0, 0 },
f75eb1c0 15426 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15427 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a900 }
15428 },
f75eb1c0 15429/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
49f58d10
JB		 15430 {
15431 { 0, 0, 0, 0 },
f75eb1c0 15432 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15433 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848900 }
15434 },
f75eb1c0 15435/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
49f58d10
JB		 15436 {
15437 { 0, 0, 0, 0 },
f75eb1c0 15438 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15439 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c900 }
15440 },
f75eb1c0 15441/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
49f58d10
JB		 15442 {
15443 { 0, 0, 0, 0 },
f75eb1c0 15444 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15445 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e900 }
15446 },
f75eb1c0 15447/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
49f58d10
JB		 15448 {
15449 { 0, 0, 0, 0 },
f75eb1c0 15450 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15451 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c900 }
15452 },
f75eb1c0 15453/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
49f58d10
JB		 15454 {
15455 { 0, 0, 0, 0 },
f75eb1c0 15456 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15457 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c900 }
15458 },
f75eb1c0 15459/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
49f58d10
JB		 15460 {
15461 { 0, 0, 0, 0 },
f75eb1c0 15462 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15463 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e900 }
15464 },
f75eb1c0 15465/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
49f58d10
JB		 15466 {
15467 { 0, 0, 0, 0 },
f75eb1c0 15468 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15469 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c900 }
15470 },
f75eb1c0 15471/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
49f58d10
JB		 15472 {
15473 { 0, 0, 0, 0 },
f75eb1c0 15474 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 15475 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c900 }
15476 },
f75eb1c0 15477/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
49f58d10
JB		 15478 {
15479 { 0, 0, 0, 0 },
f75eb1c0 15480 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 15481 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e900 }
15482 },
f75eb1c0 15483/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
49f58d10
JB		 15484 {
15485 { 0, 0, 0, 0 },
f75eb1c0 15486 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 15487 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c900 }
15488 },
f75eb1c0 15489/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
49f58d10
JB		 15490 {
15491 { 0, 0, 0, 0 },
f75eb1c0 15492 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 15493 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68900 }
15494 },
f75eb1c0 15495/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
49f58d10
JB		 15496 {
15497 { 0, 0, 0, 0 },
f75eb1c0 15498 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 15499 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a900 }
15500 },
f75eb1c0 15501/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
49f58d10
JB		 15502 {
15503 { 0, 0, 0, 0 },
f75eb1c0 15504 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 15505 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868900 }
15506 },
15507/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
15508 {
15509 { 0, 0, 0, 0 },
15510 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
15511 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x818000 }
15512 },
15513/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
15514 {
15515 { 0, 0, 0, 0 },
15516 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
15517 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x81a000 }
15518 },
15519/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
15520 {
15521 { 0, 0, 0, 0 },
15522 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
15523 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x81b000 }
15524 },
15525/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
15526 {
15527 { 0, 0, 0, 0 },
15528 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
15529 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x818400 }
15530 },
15531/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
15532 {
15533 { 0, 0, 0, 0 },
15534 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
15535 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x81a400 }
15536 },
15537/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
15538 {
15539 { 0, 0, 0, 0 },
15540 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
15541 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x81b400 }
15542 },
15543/* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
15544 {
15545 { 0, 0, 0, 0 },
15546 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
15547 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x818600 }
15548 },
15549/* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
15550 {
15551 { 0, 0, 0, 0 },
15552 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15553 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x81a600 }
15554 },
15555/* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
15556 {
15557 { 0, 0, 0, 0 },
15558 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15559 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x81b600 }
15560 },
15561/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
15562 {
15563 { 0, 0, 0, 0 },
15564 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15565 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x81880000 }
15566 },
15567/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
15568 {
15569 { 0, 0, 0, 0 },
15570 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15571 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x81a80000 }
15572 },
15573/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
15574 {
15575 { 0, 0, 0, 0 },
15576 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15577 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x81b80000 }
15578 },
15579/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
15580 {
15581 { 0, 0, 0, 0 },
15582 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15583 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x818c0000 }
15584 },
15585/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
15586 {
15587 { 0, 0, 0, 0 },
15588 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15589 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x81ac0000 }
15590 },
15591/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
15592 {
15593 { 0, 0, 0, 0 },
15594 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15595 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x81bc0000 }
15596 },
15597/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
15598 {
15599 { 0, 0, 0, 0 },
15600 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15601 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x818a0000 }
15602 },
15603/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
15604 {
15605 { 0, 0, 0, 0 },
15606 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15607 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81aa0000 }
15608 },
15609/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
15610 {
15611 { 0, 0, 0, 0 },
15612 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15613 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81ba0000 }
15614 },
15615/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
15616 {
15617 { 0, 0, 0, 0 },
15618 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15619 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x818e0000 }
15620 },
15621/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
15622 {
15623 { 0, 0, 0, 0 },
15624 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15625 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81ae0000 }
15626 },
15627/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
15628 {
15629 { 0, 0, 0, 0 },
15630 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15631 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81be0000 }
15632 },
15633/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
15634 {
15635 { 0, 0, 0, 0 },
15636 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15637 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x818b0000 }
15638 },
15639/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
15640 {
15641 { 0, 0, 0, 0 },
15642 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15643 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81ab0000 }
15644 },
15645/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
15646 {
15647 { 0, 0, 0, 0 },
15648 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15649 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81bb0000 }
15650 },
15651/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
15652 {
15653 { 0, 0, 0, 0 },
15654 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
15655 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x818f0000 }
15656 },
15657/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
15658 {
15659 { 0, 0, 0, 0 },
15660 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
15661 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x81af0000 }
15662 },
15663/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
15664 {
15665 { 0, 0, 0, 0 },
15666 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
15667 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x81bf0000 }
15668 },
15669/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
15670 {
15671 { 0, 0, 0, 0 },
15672 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
15673 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x81c00000 }
15674 },
15675/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
15676 {
15677 { 0, 0, 0, 0 },
15678 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
15679 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x81e00000 }
15680 },
15681/* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
15682 {
15683 { 0, 0, 0, 0 },
15684 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
15685 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x81f00000 }
15686 },
15687/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
15688 {
15689 { 0, 0, 0, 0 },
15690 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
15691 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x81c40000 }
15692 },
15693/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
15694 {
15695 { 0, 0, 0, 0 },
15696 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
15697 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x81e40000 }
15698 },
15699/* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
15700 {
15701 { 0, 0, 0, 0 },
15702 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
15703 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x81f40000 }
15704 },
15705/* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
15706 {
15707 { 0, 0, 0, 0 },
15708 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
15709 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x81c60000 }
15710 },
15711/* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
15712 {
15713 { 0, 0, 0, 0 },
15714 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15715 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x81e60000 }
15716 },
15717/* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
15718 {
15719 { 0, 0, 0, 0 },
15720 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
15721 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x81f60000 }
15722 },
15723/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
15724 {
15725 { 0, 0, 0, 0 },
15726 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15727 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x81c80000 }
15728 },
15729/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
15730 {
15731 { 0, 0, 0, 0 },
15732 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15733 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x81e80000 }
15734 },
15735/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
15736 {
15737 { 0, 0, 0, 0 },
15738 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15739 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x81f80000 }
15740 },
15741/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
15742 {
15743 { 0, 0, 0, 0 },
15744 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15745 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x81cc0000 }
15746 },
15747/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
15748 {
15749 { 0, 0, 0, 0 },
15750 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15751 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x81ec0000 }
15752 },
15753/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
15754 {
15755 { 0, 0, 0, 0 },
15756 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15757 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x81fc0000 }
15758 },
15759/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
15760 {
15761 { 0, 0, 0, 0 },
15762 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15763 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ca0000 }
15764 },
15765/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
15766 {
15767 { 0, 0, 0, 0 },
15768 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15769 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ea0000 }
15770 },
15771/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
15772 {
15773 { 0, 0, 0, 0 },
15774 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15775 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x81fa0000 }
15776 },
15777/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
15778 {
15779 { 0, 0, 0, 0 },
15780 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15781 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ce0000 }
15782 },
15783/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
15784 {
15785 { 0, 0, 0, 0 },
15786 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15787 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ee0000 }
15788 },
15789/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
15790 {
15791 { 0, 0, 0, 0 },
15792 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15793 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x81fe0000 }
15794 },
15795/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
15796 {
15797 { 0, 0, 0, 0 },
15798 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15799 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x81cb0000 }
15800 },
15801/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
15802 {
15803 { 0, 0, 0, 0 },
15804 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15805 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x81eb0000 }
15806 },
15807/* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
15808 {
15809 { 0, 0, 0, 0 },
15810 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15811 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x81fb0000 }
15812 },
15813/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
15814 {
15815 { 0, 0, 0, 0 },
15816 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
15817 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x81cf0000 }
15818 },
15819/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
15820 {
15821 { 0, 0, 0, 0 },
15822 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
15823 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x81ef0000 }
15824 },
15825/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
15826 {
15827 { 0, 0, 0, 0 },
15828 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
15829 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x81ff0000 }
15830 },
15831/* tst.w${X} $Src16RnHI,$Dst16RnHI */
15832 {
15833 { 0, 0, 0, 0 },
15834 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
15835 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8100 }
15836 },
15837/* tst.w${X} $Src16AnHI,$Dst16RnHI */
15838 {
15839 { 0, 0, 0, 0 },
15840 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
15841 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8140 }
15842 },
15843/* tst.w${X} [$Src16An],$Dst16RnHI */
15844 {
15845 { 0, 0, 0, 0 },
15846 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
15847 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8160 }
15848 },
15849/* tst.w${X} $Src16RnHI,$Dst16AnHI */
15850 {
15851 { 0, 0, 0, 0 },
15852 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
15853 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8104 }
15854 },
15855/* tst.w${X} $Src16AnHI,$Dst16AnHI */
15856 {
15857 { 0, 0, 0, 0 },
15858 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
15859 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8144 }
15860 },
15861/* tst.w${X} [$Src16An],$Dst16AnHI */
15862 {
15863 { 0, 0, 0, 0 },
15864 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
15865 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8164 }
15866 },
15867/* tst.w${X} $Src16RnHI,[$Dst16An] */
15868 {
15869 { 0, 0, 0, 0 },
15870 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
15871 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8106 }
15872 },
15873/* tst.w${X} $Src16AnHI,[$Dst16An] */
15874 {
15875 { 0, 0, 0, 0 },
15876 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
15877 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8146 }
15878 },
15879/* tst.w${X} [$Src16An],[$Dst16An] */
15880 {
15881 { 0, 0, 0, 0 },
15882 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
15883 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8166 }
15884 },
15885/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
15886 {
15887 { 0, 0, 0, 0 },
15888 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
15889 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x810800 }
15890 },
15891/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
15892 {
15893 { 0, 0, 0, 0 },
15894 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
15895 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x814800 }
15896 },
15897/* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
15898 {
15899 { 0, 0, 0, 0 },
15900 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
15901 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x816800 }
15902 },
15903/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
15904 {
15905 { 0, 0, 0, 0 },
15906 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
15907 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x810c0000 }
15908 },
15909/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
15910 {
15911 { 0, 0, 0, 0 },
15912 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
15913 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x814c0000 }
15914 },
15915/* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
15916 {
15917 { 0, 0, 0, 0 },
15918 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
15919 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x816c0000 }
15920 },
15921/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
15922 {
15923 { 0, 0, 0, 0 },
15924 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
15925 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x810a00 }
15926 },
15927/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
15928 {
15929 { 0, 0, 0, 0 },
15930 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
15931 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x814a00 }
15932 },
15933/* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
15934 {
15935 { 0, 0, 0, 0 },
15936 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
15937 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x816a00 }
15938 },
15939/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
15940 {
15941 { 0, 0, 0, 0 },
15942 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
15943 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x810e0000 }
15944 },
15945/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
15946 {
15947 { 0, 0, 0, 0 },
15948 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
15949 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x814e0000 }
15950 },
15951/* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
15952 {
15953 { 0, 0, 0, 0 },
15954 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
15955 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x816e0000 }
15956 },
15957/* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
15958 {
15959 { 0, 0, 0, 0 },
15960 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
15961 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x810b00 }
15962 },
15963/* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
15964 {
15965 { 0, 0, 0, 0 },
15966 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
15967 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x814b00 }
15968 },
15969/* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
15970 {
15971 { 0, 0, 0, 0 },
15972 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
15973 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x816b00 }
15974 },
15975/* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
15976 {
15977 { 0, 0, 0, 0 },
15978 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
15979 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x810f0000 }
15980 },
15981/* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
15982 {
15983 { 0, 0, 0, 0 },
15984 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
15985 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x814f0000 }
15986 },
15987/* tst.w${X} [$Src16An],${Dsp-16-u16} */
15988 {
15989 { 0, 0, 0, 0 },
15990 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
15991 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x816f0000 }
15992 },
15993/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
15994 {
15995 { 0, 0, 0, 0 },
15996 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
15997 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x808000 }
15998 },
15999/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
16000 {
16001 { 0, 0, 0, 0 },
16002 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
16003 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x80a000 }
16004 },
16005/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
16006 {
16007 { 0, 0, 0, 0 },
16008 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
16009 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x80b000 }
16010 },
16011/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
16012 {
16013 { 0, 0, 0, 0 },
16014 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16015 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x808400 }
16016 },
16017/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
16018 {
16019 { 0, 0, 0, 0 },
16020 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
16021 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x80a400 }
16022 },
16023/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
16024 {
16025 { 0, 0, 0, 0 },
16026 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
16027 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x80b400 }
16028 },
16029/* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
16030 {
16031 { 0, 0, 0, 0 },
16032 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16033 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x808600 }
16034 },
16035/* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
16036 {
16037 { 0, 0, 0, 0 },
16038 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16039 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x80a600 }
16040 },
16041/* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
16042 {
16043 { 0, 0, 0, 0 },
16044 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16045 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x80b600 }
16046 },
16047/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
16048 {
16049 { 0, 0, 0, 0 },
16050 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16051 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x80880000 }
16052 },
16053/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
16054 {
16055 { 0, 0, 0, 0 },
16056 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16057 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x80a80000 }
16058 },
16059/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
16060 {
16061 { 0, 0, 0, 0 },
16062 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16063 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x80b80000 }
16064 },
16065/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
16066 {
16067 { 0, 0, 0, 0 },
16068 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16069 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x808c0000 }
16070 },
16071/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
16072 {
16073 { 0, 0, 0, 0 },
16074 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16075 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x80ac0000 }
16076 },
16077/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
16078 {
16079 { 0, 0, 0, 0 },
16080 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16081 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x80bc0000 }
16082 },
16083/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
16084 {
16085 { 0, 0, 0, 0 },
16086 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16087 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x808a0000 }
16088 },
16089/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16090 {
16091 { 0, 0, 0, 0 },
16092 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16093 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80aa0000 }
16094 },
16095/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16096 {
16097 { 0, 0, 0, 0 },
16098 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16099 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80ba0000 }
16100 },
16101/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
16102 {
16103 { 0, 0, 0, 0 },
16104 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16105 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x808e0000 }
16106 },
16107/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16108 {
16109 { 0, 0, 0, 0 },
16110 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16111 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80ae0000 }
16112 },
16113/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16114 {
16115 { 0, 0, 0, 0 },
16116 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16117 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80be0000 }
16118 },
16119/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
16120 {
16121 { 0, 0, 0, 0 },
16122 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16123 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x808b0000 }
16124 },
16125/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16126 {
16127 { 0, 0, 0, 0 },
16128 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16129 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80ab0000 }
16130 },
16131/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16132 {
16133 { 0, 0, 0, 0 },
16134 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16135 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80bb0000 }
16136 },
16137/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
16138 {
16139 { 0, 0, 0, 0 },
16140 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
16141 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x808f0000 }
16142 },
16143/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16144 {
16145 { 0, 0, 0, 0 },
16146 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16147 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x80af0000 }
16148 },
16149/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16150 {
16151 { 0, 0, 0, 0 },
16152 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16153 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x80bf0000 }
16154 },
16155/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
16156 {
16157 { 0, 0, 0, 0 },
16158 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16159 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x80c00000 }
16160 },
16161/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
16162 {
16163 { 0, 0, 0, 0 },
16164 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
16165 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x80e00000 }
16166 },
16167/* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
16168 {
16169 { 0, 0, 0, 0 },
16170 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
16171 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x80f00000 }
16172 },
16173/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
16174 {
16175 { 0, 0, 0, 0 },
16176 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16177 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x80c40000 }
16178 },
16179/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
16180 {
16181 { 0, 0, 0, 0 },
16182 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
16183 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x80e40000 }
16184 },
16185/* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
16186 {
16187 { 0, 0, 0, 0 },
16188 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
16189 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x80f40000 }
16190 },
16191/* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
16192 {
16193 { 0, 0, 0, 0 },
16194 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16195 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x80c60000 }
16196 },
16197/* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
16198 {
16199 { 0, 0, 0, 0 },
16200 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16201 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x80e60000 }
16202 },
16203/* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
16204 {
16205 { 0, 0, 0, 0 },
16206 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
16207 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x80f60000 }
16208 },
16209/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
16210 {
16211 { 0, 0, 0, 0 },
16212 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16213 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x80c80000 }
16214 },
16215/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
16216 {
16217 { 0, 0, 0, 0 },
16218 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16219 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x80e80000 }
16220 },
16221/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
16222 {
16223 { 0, 0, 0, 0 },
16224 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16225 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x80f80000 }
16226 },
16227/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
16228 {
16229 { 0, 0, 0, 0 },
16230 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16231 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x80cc0000 }
16232 },
16233/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
16234 {
16235 { 0, 0, 0, 0 },
16236 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16237 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x80ec0000 }
16238 },
16239/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
16240 {
16241 { 0, 0, 0, 0 },
16242 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16243 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x80fc0000 }
16244 },
16245/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
16246 {
16247 { 0, 0, 0, 0 },
16248 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16249 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ca0000 }
16250 },
16251/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
16252 {
16253 { 0, 0, 0, 0 },
16254 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16255 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ea0000 }
16256 },
16257/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
16258 {
16259 { 0, 0, 0, 0 },
16260 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16261 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x80fa0000 }
16262 },
16263/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
16264 {
16265 { 0, 0, 0, 0 },
16266 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16267 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ce0000 }
16268 },
16269/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
16270 {
16271 { 0, 0, 0, 0 },
16272 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16273 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ee0000 }
16274 },
16275/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
16276 {
16277 { 0, 0, 0, 0 },
16278 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16279 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x80fe0000 }
16280 },
16281/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
16282 {
16283 { 0, 0, 0, 0 },
16284 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16285 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x80cb0000 }
16286 },
16287/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
16288 {
16289 { 0, 0, 0, 0 },
16290 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16291 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x80eb0000 }
16292 },
16293/* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
16294 {
16295 { 0, 0, 0, 0 },
16296 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16297 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x80fb0000 }
16298 },
16299/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
16300 {
16301 { 0, 0, 0, 0 },
16302 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
16303 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x80cf0000 }
16304 },
16305/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
16306 {
16307 { 0, 0, 0, 0 },
16308 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
16309 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x80ef0000 }
16310 },
16311/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
16312 {
16313 { 0, 0, 0, 0 },
16314 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
16315 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x80ff0000 }
16316 },
16317/* tst.b${X} $Src16RnQI,$Dst16RnQI */
16318 {
16319 { 0, 0, 0, 0 },
16320 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
16321 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8000 }
16322 },
16323/* tst.b${X} $Src16AnQI,$Dst16RnQI */
16324 {
16325 { 0, 0, 0, 0 },
16326 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
16327 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8040 }
16328 },
16329/* tst.b${X} [$Src16An],$Dst16RnQI */
16330 {
16331 { 0, 0, 0, 0 },
16332 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16333 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8060 }
16334 },
16335/* tst.b${X} $Src16RnQI,$Dst16AnQI */
16336 {
16337 { 0, 0, 0, 0 },
16338 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
16339 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8004 }
16340 },
16341/* tst.b${X} $Src16AnQI,$Dst16AnQI */
16342 {
16343 { 0, 0, 0, 0 },
16344 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
16345 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8044 }
16346 },
16347/* tst.b${X} [$Src16An],$Dst16AnQI */
16348 {
16349 { 0, 0, 0, 0 },
16350 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16351 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8064 }
16352 },
16353/* tst.b${X} $Src16RnQI,[$Dst16An] */
16354 {
16355 { 0, 0, 0, 0 },
16356 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
16357 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8006 }
16358 },
16359/* tst.b${X} $Src16AnQI,[$Dst16An] */
16360 {
16361 { 0, 0, 0, 0 },
16362 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
16363 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8046 }
16364 },
16365/* tst.b${X} [$Src16An],[$Dst16An] */
16366 {
16367 { 0, 0, 0, 0 },
16368 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16369 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8066 }
16370 },
16371/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
16372 {
16373 { 0, 0, 0, 0 },
16374 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16375 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x800800 }
16376 },
16377/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
16378 {
16379 { 0, 0, 0, 0 },
16380 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16381 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x804800 }
16382 },
16383/* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
16384 {
16385 { 0, 0, 0, 0 },
16386 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16387 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x806800 }
16388 },
16389/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
16390 {
16391 { 0, 0, 0, 0 },
16392 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16393 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x800c0000 }
16394 },
16395/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
16396 {
16397 { 0, 0, 0, 0 },
16398 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16399 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x804c0000 }
16400 },
16401/* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
16402 {
16403 { 0, 0, 0, 0 },
16404 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16405 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x806c0000 }
16406 },
16407/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
16408 {
16409 { 0, 0, 0, 0 },
16410 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16411 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x800a00 }
16412 },
16413/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
16414 {
16415 { 0, 0, 0, 0 },
16416 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16417 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x804a00 }
16418 },
16419/* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
16420 {
16421 { 0, 0, 0, 0 },
16422 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16423 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x806a00 }
16424 },
16425/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
16426 {
16427 { 0, 0, 0, 0 },
16428 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16429 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x800e0000 }
16430 },
16431/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
16432 {
16433 { 0, 0, 0, 0 },
16434 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16435 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x804e0000 }
16436 },
16437/* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
16438 {
16439 { 0, 0, 0, 0 },
16440 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16441 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x806e0000 }
16442 },
16443/* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
16444 {
16445 { 0, 0, 0, 0 },
16446 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16447 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x800b00 }
16448 },
16449/* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
16450 {
16451 { 0, 0, 0, 0 },
16452 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16453 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x804b00 }
16454 },
16455/* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
16456 {
16457 { 0, 0, 0, 0 },
16458 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16459 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x806b00 }
16460 },
16461/* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
16462 {
16463 { 0, 0, 0, 0 },
16464 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
16465 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x800f0000 }
16466 },
16467/* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
16468 {
16469 { 0, 0, 0, 0 },
16470 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
16471 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x804f0000 }
16472 },
16473/* tst.b${X} [$Src16An],${Dsp-16-u16} */
16474 {
16475 { 0, 0, 0, 0 },
16476 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
16477 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x806f0000 }
16478 },
f75eb1c0 16479/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
49f58d10
JB		 16480 {
16481 { 0, 0, 0, 0 },
f75eb1c0 16482 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49f58d10
JB		 16483 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993e0000 }
16484 },
f75eb1c0 16485/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
49f58d10
JB		 16486 {
16487 { 0, 0, 0, 0 },
f75eb1c0 16488 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49f58d10
JB		 16489 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91be0000 }
16490 },
f75eb1c0 16491/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
49f58d10
JB		 16492 {
16493 { 0, 0, 0, 0 },
f75eb1c0 16494 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16495 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913e0000 }
16496 },
f75eb1c0 16497/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 16498 {
16499 { 0, 0, 0, 0 },
f75eb1c0 16500 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16501 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933e0000 }
16502 },
f75eb1c0 16503/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16504 {
16505 { 0, 0, 0, 0 },
f75eb1c0 16506 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16507 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93be0000 }
16508 },
f75eb1c0 16509/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16510 {
16511 { 0, 0, 0, 0 },
f75eb1c0 16512 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16513 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93fe0000 }
16514 },
f75eb1c0 16515/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 16516 {
16517 { 0, 0, 0, 0 },
f75eb1c0 16518 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16519 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953e0000 }
16520 },
f75eb1c0 16521/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16522 {
16523 { 0, 0, 0, 0 },
f75eb1c0 16524 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16525 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95be0000 }
16526 },
f75eb1c0 16527/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
49f58d10
JB		 16528 {
16529 { 0, 0, 0, 0 },
f75eb1c0 16530 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16531 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95fe0000 }
16532 },
f75eb1c0 16533/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
49f58d10
JB		 16534 {
16535 { 0, 0, 0, 0 },
f75eb1c0 16536 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16537 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97fe0000 }
16538 },
f75eb1c0 16539/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 16540 {
16541 { 0, 0, 0, 0 },
f75eb1c0 16542 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16543 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973e0000 }
16544 },
f75eb1c0 16545/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
49f58d10
JB		 16546 {
16547 { 0, 0, 0, 0 },
f75eb1c0 16548 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 16549 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97be0000 }
16550 },
f75eb1c0 16551/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
49f58d10
JB		 16552 {
16553 { 0, 0, 0, 0 },
f75eb1c0 16554 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49f58d10
JB		 16555 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983e00 }
16556 },
f75eb1c0 16557/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
49f58d10
JB		 16558 {
16559 { 0, 0, 0, 0 },
f75eb1c0 16560 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49f58d10
JB		 16561 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90be00 }
16562 },
f75eb1c0 16563/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
49f58d10
JB		 16564 {
16565 { 0, 0, 0, 0 },
f75eb1c0 16566 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16567 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903e00 }
16568 },
f75eb1c0 16569/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 16570 {
16571 { 0, 0, 0, 0 },
f75eb1c0 16572 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16573 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923e0000 }
16574 },
f75eb1c0 16575/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16576 {
16577 { 0, 0, 0, 0 },
f75eb1c0 16578 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16579 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92be0000 }
16580 },
f75eb1c0 16581/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16582 {
16583 { 0, 0, 0, 0 },
f75eb1c0 16584 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16585 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92fe0000 }
16586 },
f75eb1c0 16587/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 16588 {
16589 { 0, 0, 0, 0 },
f75eb1c0 16590 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16591 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943e0000 }
16592 },
f75eb1c0 16593/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16594 {
16595 { 0, 0, 0, 0 },
f75eb1c0 16596 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16597 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94be0000 }
16598 },
f75eb1c0 16599/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
49f58d10
JB		 16600 {
16601 { 0, 0, 0, 0 },
f75eb1c0 16602 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16603 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94fe0000 }
16604 },
f75eb1c0 16605/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 16606 {
16607 { 0, 0, 0, 0 },
f75eb1c0 16608 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16609 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96fe0000 }
16610 },
f75eb1c0 16611/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 16612 {
16613 { 0, 0, 0, 0 },
f75eb1c0 16614 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16615 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963e0000 }
16616 },
f75eb1c0 16617/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
49f58d10
JB		 16618 {
16619 { 0, 0, 0, 0 },
f75eb1c0 16620 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 16621 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96be0000 }
16622 },
f75eb1c0 16623/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
49f58d10
JB		 16624 {
16625 { 0, 0, 0, 0 },
f75eb1c0 16626 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
49f58d10
JB		 16627 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77000000 }
16628 },
f75eb1c0 16629/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
49f58d10
JB		 16630 {
16631 { 0, 0, 0, 0 },
f75eb1c0 16632 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
49f58d10
JB		 16633 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77040000 }
16634 },
f75eb1c0 16635/* tst.w${G} #${Imm-16-HI},[$Dst16An] */
49f58d10
JB		 16636 {
16637 { 0, 0, 0, 0 },
f75eb1c0 16638 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16639 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77060000 }
16640 },
f75eb1c0 16641/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 16642 {
16643 { 0, 0, 0, 0 },
f75eb1c0 16644 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16645 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77080000 }
16646 },
f75eb1c0 16647/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16648 {
16649 { 0, 0, 0, 0 },
f75eb1c0 16650 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16651 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x770a0000 }
16652 },
f75eb1c0 16653/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16654 {
16655 { 0, 0, 0, 0 },
f75eb1c0 16656 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16657 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x770b0000 }
16658 },
f75eb1c0 16659/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 16660 {
16661 { 0, 0, 0, 0 },
f75eb1c0 16662 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16663 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x770c0000 }
16664 },
f75eb1c0 16665/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16666 {
16667 { 0, 0, 0, 0 },
f75eb1c0 16668 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16669 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x770e0000 }
16670 },
f75eb1c0 16671/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
49f58d10
JB		 16672 {
16673 { 0, 0, 0, 0 },
f75eb1c0 16674 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16675 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x770f0000 }
16676 },
f75eb1c0 16677/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
49f58d10
JB		 16678 {
16679 { 0, 0, 0, 0 },
f75eb1c0 16680 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
49f58d10
JB		 16681 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x760000 }
16682 },
f75eb1c0 16683/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
49f58d10
JB		 16684 {
16685 { 0, 0, 0, 0 },
f75eb1c0 16686 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
49f58d10
JB		 16687 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x760400 }
16688 },
f75eb1c0 16689/* tst.b${G} #${Imm-16-QI},[$Dst16An] */
49f58d10
JB		 16690 {
16691 { 0, 0, 0, 0 },
f75eb1c0 16692 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16693 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x760600 }
16694 },
f75eb1c0 16695/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 16696 {
16697 { 0, 0, 0, 0 },
f75eb1c0 16698 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16699 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76080000 }
16700 },
f75eb1c0 16701/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16702 {
16703 { 0, 0, 0, 0 },
f75eb1c0 16704 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16705 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x760a0000 }
16706 },
f75eb1c0 16707/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16708 {
16709 { 0, 0, 0, 0 },
f75eb1c0 16710 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16711 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x760b0000 }
16712 },
f75eb1c0 16713/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 16714 {
16715 { 0, 0, 0, 0 },
f75eb1c0 16716 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16717 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x760c0000 }
16718 },
f75eb1c0 16719/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16720 {
16721 { 0, 0, 0, 0 },
f75eb1c0 16722 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16723 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x760e0000 }
16724 },
f75eb1c0 16725/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 16726 {
16727 { 0, 0, 0, 0 },
f75eb1c0 16728 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16729 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x760f0000 }
16730 },
16731/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
16732 {
16733 { 0, 0, 0, 0 },
16734 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16735 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980000 }
16736 },
16737/* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
16738 {
16739 { 0, 0, 0, 0 },
16740 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16741 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982000 }
16742 },
16743/* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
16744 {
16745 { 0, 0, 0, 0 },
16746 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16747 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983000 }
16748 },
16749/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
16750 {
16751 { 0, 0, 0, 0 },
16752 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16753 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908000 }
16754 },
16755/* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
16756 {
16757 { 0, 0, 0, 0 },
16758 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16759 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a000 }
16760 },
16761/* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
16762 {
16763 { 0, 0, 0, 0 },
16764 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16765 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b000 }
16766 },
16767/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16768 {
16769 { 0, 0, 0, 0 },
16770 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16771 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900000 }
16772 },
16773/* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16774 {
16775 { 0, 0, 0, 0 },
16776 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16777 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902000 }
16778 },
16779/* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16780 {
16781 { 0, 0, 0, 0 },
16782 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16783 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903000 }
16784 },
16785/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16786 {
16787 { 0, 0, 0, 0 },
16788 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16789 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92000000 }
16790 },
16791/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16792 {
16793 { 0, 0, 0, 0 },
16794 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16795 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92200000 }
16796 },
16797/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16798 {
16799 { 0, 0, 0, 0 },
16800 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16801 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92300000 }
16802 },
16803/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16804 {
16805 { 0, 0, 0, 0 },
16806 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16807 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94000000 }
16808 },
16809/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16810 {
16811 { 0, 0, 0, 0 },
16812 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16813 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94200000 }
16814 },
16815/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16816 {
16817 { 0, 0, 0, 0 },
16818 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16819 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94300000 }
16820 },
16821/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16822 {
16823 { 0, 0, 0, 0 },
16824 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16825 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96000000 }
16826 },
16827/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16828 {
16829 { 0, 0, 0, 0 },
16830 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16831 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96200000 }
16832 },
16833/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16834 {
16835 { 0, 0, 0, 0 },
16836 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16837 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96300000 }
16838 },
16839/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
16840 {
16841 { 0, 0, 0, 0 },
16842 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16843 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92800000 }
16844 },
16845/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16846 {
16847 { 0, 0, 0, 0 },
16848 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16849 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a00000 }
16850 },
16851/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16852 {
16853 { 0, 0, 0, 0 },
16854 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16855 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b00000 }
16856 },
16857/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
16858 {
16859 { 0, 0, 0, 0 },
16860 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16861 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94800000 }
16862 },
16863/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16864 {
16865 { 0, 0, 0, 0 },
16866 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16867 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a00000 }
16868 },
16869/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16870 {
16871 { 0, 0, 0, 0 },
16872 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16873 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b00000 }
16874 },
16875/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
16876 {
16877 { 0, 0, 0, 0 },
16878 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16879 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c00000 }
16880 },
16881/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16882 {
16883 { 0, 0, 0, 0 },
16884 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16885 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e00000 }
16886 },
16887/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16888 {
16889 { 0, 0, 0, 0 },
16890 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16891 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f00000 }
16892 },
16893/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
16894 {
16895 { 0, 0, 0, 0 },
16896 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
16897 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c00000 }
16898 },
16899/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
16900 {
16901 { 0, 0, 0, 0 },
16902 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
16903 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e00000 }
16904 },
16905/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
16906 {
16907 { 0, 0, 0, 0 },
16908 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
16909 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f00000 }
16910 },
16911/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
16912 {
16913 { 0, 0, 0, 0 },
16914 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
16915 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c00000 }
16916 },
16917/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16918 {
16919 { 0, 0, 0, 0 },
16920 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16921 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e00000 }
16922 },
16923/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16924 {
16925 { 0, 0, 0, 0 },
16926 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16927 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f00000 }
16928 },
16929/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
16930 {
16931 { 0, 0, 0, 0 },
16932 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
16933 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96800000 }
16934 },
16935/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
16936 {
16937 { 0, 0, 0, 0 },
16938 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
16939 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a00000 }
16940 },
16941/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
16942 {
16943 { 0, 0, 0, 0 },
16944 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
16945 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b00000 }
16946 },
16947/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
16948 {
16949 { 0, 0, 0, 0 },
16950 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16951 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8000000 }
16952 },
16953/* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
16954 {
16955 { 0, 0, 0, 0 },
16956 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16957 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8200000 }
16958 },
16959/* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
16960 {
16961 { 0, 0, 0, 0 },
16962 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16963 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8300000 }
16964 },
16965/* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
16966 {
16967 { 0, 0, 0, 0 },
16968 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16969 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8300000 }
16970 },
16971/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
16972 {
16973 { 0, 0, 0, 0 },
16974 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16975 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0800000 }
16976 },
16977/* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
16978 {
16979 { 0, 0, 0, 0 },
16980 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16981 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a00000 }
16982 },
16983/* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
16984 {
16985 { 0, 0, 0, 0 },
16986 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16987 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b00000 }
16988 },
16989/* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
16990 {
16991 { 0, 0, 0, 0 },
16992 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16993 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b00000 }
16994 },
16995/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16996 {
16997 { 0, 0, 0, 0 },
16998 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16999 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0000000 }
17000 },
17001/* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17002 {
17003 { 0, 0, 0, 0 },
17004 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17005 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0200000 }
17006 },
17007/* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17008 {
17009 { 0, 0, 0, 0 },
17010 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17011 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0300000 }
17012 },
17013/* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17014 {
17015 { 0, 0, 0, 0 },
17016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17017 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0300000 }
17018 },
17019/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17020 {
17021 { 0, 0, 0, 0 },
17022 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17023 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2000000 }
17024 },
17025/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17026 {
17027 { 0, 0, 0, 0 },
17028 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17029 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2200000 }
17030 },
17031/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17032 {
17033 { 0, 0, 0, 0 },
17034 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17035 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2300000 }
17036 },
17037/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17038 {
17039 { 0, 0, 0, 0 },
17040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17041 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2300000 }
17042 },
17043/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17044 {
17045 { 0, 0, 0, 0 },
17046 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17047 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4000000 }
17048 },
17049/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17050 {
17051 { 0, 0, 0, 0 },
17052 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17053 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4200000 }
17054 },
17055/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17056 {
17057 { 0, 0, 0, 0 },
17058 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17059 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4300000 }
17060 },
17061/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17062 {
17063 { 0, 0, 0, 0 },
17064 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17065 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4300000 }
17066 },
17067/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17068 {
17069 { 0, 0, 0, 0 },
17070 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17071 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6000000 }
17072 },
17073/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17074 {
17075 { 0, 0, 0, 0 },
17076 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17077 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6200000 }
17078 },
17079/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17080 {
17081 { 0, 0, 0, 0 },
17082 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17083 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6300000 }
17084 },
17085/* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17086 {
17087 { 0, 0, 0, 0 },
17088 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17089 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6300000 }
17090 },
17091/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17092 {
17093 { 0, 0, 0, 0 },
17094 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17095 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2800000 }
17096 },
17097/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17098 {
17099 { 0, 0, 0, 0 },
17100 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17101 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a00000 }
17102 },
17103/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17104 {
17105 { 0, 0, 0, 0 },
17106 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17107 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b00000 }
17108 },
17109/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17110 {
17111 { 0, 0, 0, 0 },
17112 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17113 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b00000 }
17114 },
17115/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17116 {
17117 { 0, 0, 0, 0 },
17118 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17119 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4800000 }
17120 },
17121/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17122 {
17123 { 0, 0, 0, 0 },
17124 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17125 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a00000 }
17126 },
17127/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17128 {
17129 { 0, 0, 0, 0 },
17130 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17131 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b00000 }
17132 },
17133/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17134 {
17135 { 0, 0, 0, 0 },
17136 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17137 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b00000 }
17138 },
17139/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17140 {
17141 { 0, 0, 0, 0 },
17142 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17143 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c00000 }
17144 },
17145/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17146 {
17147 { 0, 0, 0, 0 },
17148 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17149 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e00000 }
17150 },
17151/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17152 {
17153 { 0, 0, 0, 0 },
17154 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17155 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f00000 }
17156 },
17157/* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17158 {
17159 { 0, 0, 0, 0 },
17160 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17161 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f00000 }
17162 },
17163/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17164 {
17165 { 0, 0, 0, 0 },
17166 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17167 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c00000 }
17168 },
17169/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17170 {
17171 { 0, 0, 0, 0 },
17172 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17173 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e00000 }
17174 },
17175/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17176 {
17177 { 0, 0, 0, 0 },
17178 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17179 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f00000 }
17180 },
17181/* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17182 {
17183 { 0, 0, 0, 0 },
17184 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17185 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f00000 }
17186 },
17187/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17188 {
17189 { 0, 0, 0, 0 },
17190 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
17191 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c00000 }
17192 },
17193/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17194 {
17195 { 0, 0, 0, 0 },
17196 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
17197 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e00000 }
17198 },
17199/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17200 {
17201 { 0, 0, 0, 0 },
17202 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
17203 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f00000 }
17204 },
17205/* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
17206 {
17207 { 0, 0, 0, 0 },
17208 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
17209 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f00000 }
17210 },
17211/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17212 {
17213 { 0, 0, 0, 0 },
17214 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
17215 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6800000 }
17216 },
17217/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17218 {
17219 { 0, 0, 0, 0 },
17220 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
17221 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a00000 }
17222 },
17223/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17224 {
17225 { 0, 0, 0, 0 },
17226 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
17227 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b00000 }
17228 },
17229/* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
17230 {
17231 { 0, 0, 0, 0 },
17232 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
17233 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b00000 }
17234 },
17235/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17236 {
17237 { 0, 0, 0, 0 },
17238 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17239 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8000000 }
17240 },
17241/* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
17242 {
17243 { 0, 0, 0, 0 },
17244 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17245 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8200000 }
17246 },
17247/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17248 {
17249 { 0, 0, 0, 0 },
17250 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17251 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0800000 }
17252 },
17253/* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
17254 {
17255 { 0, 0, 0, 0 },
17256 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17257 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a00000 }
17258 },
17259/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17260 {
17261 { 0, 0, 0, 0 },
17262 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17263 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0000000 }
17264 },
17265/* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17266 {
17267 { 0, 0, 0, 0 },
17268 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17269 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0200000 }
17270 },
17271/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17272 {
17273 { 0, 0, 0, 0 },
17274 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17275 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2000000 }
17276 },
17277/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17278 {
17279 { 0, 0, 0, 0 },
17280 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17281 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2200000 }
17282 },
17283/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17284 {
17285 { 0, 0, 0, 0 },
17286 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17287 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4000000 }
17288 },
17289/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17290 {
17291 { 0, 0, 0, 0 },
17292 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17293 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4200000 }
17294 },
17295/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17296 {
17297 { 0, 0, 0, 0 },
17298 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17299 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6000000 }
17300 },
17301/* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17302 {
17303 { 0, 0, 0, 0 },
17304 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17305 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6200000 }
17306 },
17307/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17308 {
17309 { 0, 0, 0, 0 },
17310 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
17311 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2800000 }
17312 },
17313/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17314 {
17315 { 0, 0, 0, 0 },
17316 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
17317 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a00000 }
17318 },
17319/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17320 {
17321 { 0, 0, 0, 0 },
17322 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
17323 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4800000 }
17324 },
17325/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17326 {
17327 { 0, 0, 0, 0 },
17328 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
17329 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a00000 }
17330 },
17331/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17332 {
17333 { 0, 0, 0, 0 },
17334 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
17335 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c00000 }
17336 },
17337/* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17338 {
17339 { 0, 0, 0, 0 },
17340 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
17341 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e00000 }
17342 },
17343/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17344 {
17345 { 0, 0, 0, 0 },
17346 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
17347 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c00000 }
17348 },
17349/* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17350 {
17351 { 0, 0, 0, 0 },
17352 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
17353 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e00000 }
17354 },
17355/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17356 {
17357 { 0, 0, 0, 0 },
17358 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
17359 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c00000 }
17360 },
17361/* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
17362 {
17363 { 0, 0, 0, 0 },
17364 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
17365 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e00000 }
17366 },
17367/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17368 {
17369 { 0, 0, 0, 0 },
17370 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
17371 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6800000 }
17372 },
17373/* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
17374 {
17375 { 0, 0, 0, 0 },
17376 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
17377 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a00000 }
17378 },
17379/* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
17380 {
17381 { 0, 0, 0, 0 },
17382 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17383 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc800 }
17384 },
17385/* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
17386 {
17387 { 0, 0, 0, 0 },
17388 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17389 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8820 }
17390 },
17391/* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17392 {
17393 { 0, 0, 0, 0 },
17394 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17395 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8800 }
17396 },
17397/* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
17398 {
17399 { 0, 0, 0, 0 },
17400 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17401 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc080 }
17402 },
17403/* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
17404 {
17405 { 0, 0, 0, 0 },
17406 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17407 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a0 }
17408 },
17409/* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17410 {
17411 { 0, 0, 0, 0 },
17412 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17413 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8080 }
17414 },
17415/* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
17416 {
17417 { 0, 0, 0, 0 },
17418 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17419 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc000 }
17420 },
17421/* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
17422 {
17423 { 0, 0, 0, 0 },
17424 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17425 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8020 }
17426 },
17427/* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17428 {
17429 { 0, 0, 0, 0 },
17430 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17431 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8000 }
17432 },
17433/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17434 {
17435 { 0, 0, 0, 0 },
17436 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17437 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20000 }
17438 },
17439/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17440 {
17441 { 0, 0, 0, 0 },
17442 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17443 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822000 }
17444 },
17445/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17446 {
17447 { 0, 0, 0, 0 },
17448 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17449 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820000 }
17450 },
17451/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17452 {
17453 { 0, 0, 0, 0 },
17454 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17455 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4000000 }
17456 },
17457/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17458 {
17459 { 0, 0, 0, 0 },
17460 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17461 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84200000 }
17462 },
17463/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17464 {
17465 { 0, 0, 0, 0 },
17466 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17467 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84000000 }
17468 },
17469/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17470 {
17471 { 0, 0, 0, 0 },
17472 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17473 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6000000 }
17474 },
17475/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17476 {
17477 { 0, 0, 0, 0 },
17478 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17479 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86200000 }
17480 },
17481/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17482 {
17483 { 0, 0, 0, 0 },
17484 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17485 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86000000 }
17486 },
17487/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
17488 {
17489 { 0, 0, 0, 0 },
17490 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17491 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28000 }
17492 },
17493/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
17494 {
17495 { 0, 0, 0, 0 },
17496 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17497 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a000 }
17498 },
17499/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17500 {
17501 { 0, 0, 0, 0 },
17502 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17503 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828000 }
17504 },
17505/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
17506 {
17507 { 0, 0, 0, 0 },
17508 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17509 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4800000 }
17510 },
17511/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
17512 {
17513 { 0, 0, 0, 0 },
17514 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17515 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a00000 }
17516 },
17517/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17518 {
17519 { 0, 0, 0, 0 },
17520 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17521 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84800000 }
17522 },
17523/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
17524 {
17525 { 0, 0, 0, 0 },
17526 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17527 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c000 }
17528 },
17529/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
17530 {
17531 { 0, 0, 0, 0 },
17532 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17533 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e000 }
17534 },
17535/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17536 {
17537 { 0, 0, 0, 0 },
17538 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17539 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c000 }
17540 },
17541/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
17542 {
17543 { 0, 0, 0, 0 },
17544 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17545 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c00000 }
17546 },
17547/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
17548 {
17549 { 0, 0, 0, 0 },
17550 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17551 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e00000 }
17552 },
17553/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17554 {
17555 { 0, 0, 0, 0 },
17556 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17557 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c00000 }
17558 },
17559/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
17560 {
17561 { 0, 0, 0, 0 },
17562 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
17563 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c00000 }
17564 },
17565/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
17566 {
17567 { 0, 0, 0, 0 },
17568 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
17569 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e00000 }
17570 },
17571/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17572 {
17573 { 0, 0, 0, 0 },
17574 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
17575 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c00000 }
17576 },
17577/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
17578 {
17579 { 0, 0, 0, 0 },
17580 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
17581 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6800000 }
17582 },
17583/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
17584 {
17585 { 0, 0, 0, 0 },
17586 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
17587 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a00000 }
17588 },
17589/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17590 {
17591 { 0, 0, 0, 0 },
17592 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
17593 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86800000 }
17594 },
17595/* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
17596 {
17597 { 0, 0, 0, 0 },
17598 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17599 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x981100 }
17600 },
17601/* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
17602 {
17603 { 0, 0, 0, 0 },
17604 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17605 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x909100 }
17606 },
17607/* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
17608 {
17609 { 0, 0, 0, 0 },
17610 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17611 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x901100 }
17612 },
17613/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17614 {
17615 { 0, 0, 0, 0 },
17616 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17617 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92110000 }
17618 },
17619/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
17620 {
17621 { 0, 0, 0, 0 },
17622 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17623 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92910000 }
17624 },
17625/* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
17626 {
17627 { 0, 0, 0, 0 },
17628 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17629 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92d10000 }
17630 },
17631/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17632 {
17633 { 0, 0, 0, 0 },
17634 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17635 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94110000 }
17636 },
17637/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
17638 {
17639 { 0, 0, 0, 0 },
17640 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17641 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94910000 }
17642 },
17643/* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
17644 {
17645 { 0, 0, 0, 0 },
17646 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17647 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94d10000 }
17648 },
17649/* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
17650 {
17651 { 0, 0, 0, 0 },
17652 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
17653 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96d10000 }
17654 },
17655/* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17656 {
17657 { 0, 0, 0, 0 },
17658 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17659 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96110000 }
17660 },
17661/* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
17662 {
17663 { 0, 0, 0, 0 },
17664 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
17665 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96910000 }
17666 },
17667/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
17668 {
17669 { 0, 0, 0, 0 },
17670 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
17671 & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993f0000 }
17672 },
17673/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
17674 {
17675 { 0, 0, 0, 0 },
17676 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
17677 & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91bf0000 }
17678 },
17679/* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
17680 {
17681 { 0, 0, 0, 0 },
17682 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17683 & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913f0000 }
17684 },
17685/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17686 {
17687 { 0, 0, 0, 0 },
17688 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17689 & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933f0000 }
17690 },
17691/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
17692 {
17693 { 0, 0, 0, 0 },
17694 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17695 & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93bf0000 }
17696 },
17697/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
17698 {
17699 { 0, 0, 0, 0 },
17700 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17701 & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ff0000 }
17702 },
17703/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17704 {
17705 { 0, 0, 0, 0 },
17706 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17707 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953f0000 }
17708 },
17709/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
17710 {
17711 { 0, 0, 0, 0 },
17712 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17713 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95bf0000 }
17714 },
17715/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
17716 {
17717 { 0, 0, 0, 0 },
17718 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17719 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ff0000 }
17720 },
17721/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
17722 {
17723 { 0, 0, 0, 0 },
17724 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), 0 } },
17725 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ff0000 }
17726 },
17727/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17728 {
17729 { 0, 0, 0, 0 },
17730 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17731 & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973f0000 }
17732 },
17733/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
17734 {
17735 { 0, 0, 0, 0 },
17736 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), 0 } },
17737 & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97bf0000 }
17738 },
17739/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
17740 {
17741 { 0, 0, 0, 0 },
17742 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
17743 & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983f0000 }
17744 },
17745/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
17746 {
17747 { 0, 0, 0, 0 },
17748 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
17749 & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90bf0000 }
17750 },
17751/* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
17752 {
17753 { 0, 0, 0, 0 },
17754 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17755 & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903f0000 }
17756 },
17757/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17758 {
17759 { 0, 0, 0, 0 },
17760 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17761 & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923f0000 }
17762 },
17763/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
17764 {
17765 { 0, 0, 0, 0 },
17766 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17767 & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92bf0000 }
17768 },
17769/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
17770 {
17771 { 0, 0, 0, 0 },
17772 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17773 & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ff0000 }
17774 },
17775/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17776 {
17777 { 0, 0, 0, 0 },
17778 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17779 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943f0000 }
17780 },
17781/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
17782 {
17783 { 0, 0, 0, 0 },
17784 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17785 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94bf0000 }
17786 },
17787/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
17788 {
17789 { 0, 0, 0, 0 },
17790 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17791 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ff0000 }
17792 },
17793/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
17794 {
17795 { 0, 0, 0, 0 },
17796 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), 0 } },
17797 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ff0000 }
17798 },
17799/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17800 {
17801 { 0, 0, 0, 0 },
17802 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17803 & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963f0000 }
17804 },
17805/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
17806 {
17807 { 0, 0, 0, 0 },
17808 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), 0 } },
17809 & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96bf0000 }
17810 },
17811/* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
17812 {
17813 { 0, 0, 0, 0 },
17814 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
17815 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990f0000 }
17816 },
17817/* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
17818 {
17819 { 0, 0, 0, 0 },
17820 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
17821 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918f0000 }
17822 },
17823/* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
17824 {
17825 { 0, 0, 0, 0 },
17826 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17827 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910f0000 }
17828 },
17829/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17830 {
17831 { 0, 0, 0, 0 },
17832 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17833 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930f0000 }
17834 },
17835/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
17836 {
17837 { 0, 0, 0, 0 },
17838 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17839 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938f0000 }
17840 },
17841/* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
17842 {
17843 { 0, 0, 0, 0 },
17844 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17845 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93cf0000 }
17846 },
17847/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17848 {
17849 { 0, 0, 0, 0 },
17850 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17851 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950f0000 }
17852 },
17853/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
17854 {
17855 { 0, 0, 0, 0 },
17856 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17857 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958f0000 }
17858 },
17859/* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
17860 {
17861 { 0, 0, 0, 0 },
17862 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17863 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95cf0000 }
17864 },
17865/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
17866 {
17867 { 0, 0, 0, 0 },
17868 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
17869 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97cf0000 }
17870 },
17871/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17872 {
17873 { 0, 0, 0, 0 },
17874 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17875 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970f0000 }
17876 },
17877/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
17878 {
17879 { 0, 0, 0, 0 },
17880 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
17881 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978f0000 }
17882 },
17883/* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
17884 {
17885 { 0, 0, 0, 0 },
17886 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
17887 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980f00 }
17888 },
17889/* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
17890 {
17891 { 0, 0, 0, 0 },
17892 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
17893 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908f00 }
17894 },
17895/* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
17896 {
17897 { 0, 0, 0, 0 },
17898 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17899 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900f00 }
17900 },
17901/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17902 {
17903 { 0, 0, 0, 0 },
17904 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17905 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920f0000 }
17906 },
17907/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
17908 {
17909 { 0, 0, 0, 0 },
17910 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17911 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928f0000 }
17912 },
17913/* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
17914 {
17915 { 0, 0, 0, 0 },
17916 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17917 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92cf0000 }
17918 },
17919/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17920 {
17921 { 0, 0, 0, 0 },
17922 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17923 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940f0000 }
17924 },
17925/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
17926 {
17927 { 0, 0, 0, 0 },
17928 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17929 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948f0000 }
17930 },
17931/* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
17932 {
17933 { 0, 0, 0, 0 },
17934 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17935 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94cf0000 }
17936 },
17937/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
17938 {
17939 { 0, 0, 0, 0 },
17940 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
17941 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96cf0000 }
17942 },
17943/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17944 {
17945 { 0, 0, 0, 0 },
17946 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17947 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960f0000 }
17948 },
17949/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
17950 {
17951 { 0, 0, 0, 0 },
17952 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
17953 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968f0000 }
17954 },
17955/* stz${S} #${Imm-8-QI},r0l */
17956 {
17957 { 0, 0, 0, 0 },
17958 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
17959 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xcc00 }
17960 },
17961/* stz${S} #${Imm-8-QI},r0h */
17962 {
17963 { 0, 0, 0, 0 },
17964 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
17965 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xcb00 }
17966 },
17967/* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
17968 {
17969 { 0, 0, 0, 0 },
17970 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17971 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xcd0000 }
17972 },
17973/* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
17974 {
17975 { 0, 0, 0, 0 },
17976 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17977 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xce0000 }
17978 },
17979/* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
17980 {
17981 { 0, 0, 0, 0 },
17982 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
17983 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xcf000000 }
17984 },
17985/* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
17986 {
17987 { 0, 0, 0, 0 },
17988 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
17989 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x991f0000 }
17990 },
17991/* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
17992 {
17993 { 0, 0, 0, 0 },
17994 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
17995 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x919f0000 }
17996 },
17997/* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
17998 {
17999 { 0, 0, 0, 0 },
18000 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18001 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x911f0000 }
18002 },
18003/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18004 {
18005 { 0, 0, 0, 0 },
18006 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18007 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x931f0000 }
18008 },
18009/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
18010 {
18011 { 0, 0, 0, 0 },
18012 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18013 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939f0000 }
18014 },
18015/* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
18016 {
18017 { 0, 0, 0, 0 },
18018 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18019 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93df0000 }
18020 },
18021/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18022 {
18023 { 0, 0, 0, 0 },
18024 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18025 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x951f0000 }
18026 },
18027/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
18028 {
18029 { 0, 0, 0, 0 },
18030 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18031 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959f0000 }
18032 },
18033/* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
18034 {
18035 { 0, 0, 0, 0 },
18036 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18037 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95df0000 }
18038 },
18039/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
18040 {
18041 { 0, 0, 0, 0 },
18042 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
18043 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97df0000 }
18044 },
18045/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18046 {
18047 { 0, 0, 0, 0 },
18048 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18049 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x971f0000 }
18050 },
18051/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
18052 {
18053 { 0, 0, 0, 0 },
18054 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
18055 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x979f0000 }
18056 },
18057/* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
18058 {
18059 { 0, 0, 0, 0 },
18060 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18061 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x981f00 }
18062 },
18063/* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
18064 {
18065 { 0, 0, 0, 0 },
18066 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18067 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x909f00 }
18068 },
18069/* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18070 {
18071 { 0, 0, 0, 0 },
18072 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18073 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x901f00 }
18074 },
18075/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18076 {
18077 { 0, 0, 0, 0 },
18078 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18079 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x921f0000 }
18080 },
18081/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18082 {
18083 { 0, 0, 0, 0 },
18084 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18085 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929f0000 }
18086 },
18087/* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18088 {
18089 { 0, 0, 0, 0 },
18090 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18091 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92df0000 }
18092 },
18093/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18094 {
18095 { 0, 0, 0, 0 },
18096 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18097 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x941f0000 }
18098 },
18099/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18100 {
18101 { 0, 0, 0, 0 },
18102 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18103 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949f0000 }
18104 },
18105/* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18106 {
18107 { 0, 0, 0, 0 },
18108 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18109 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94df0000 }
18110 },
18111/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
18112 {
18113 { 0, 0, 0, 0 },
18114 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18115 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96df0000 }
18116 },
18117/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18118 {
18119 { 0, 0, 0, 0 },
18120 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18121 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x961f0000 }
18122 },
18123/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
18124 {
18125 { 0, 0, 0, 0 },
18126 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18127 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x969f0000 }
18128 },
18129/* stnz${S} #${Imm-8-QI},r0l */
18130 {
18131 { 0, 0, 0, 0 },
18132 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
18133 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xd400 }
18134 },
18135/* stnz${S} #${Imm-8-QI},r0h */
18136 {
18137 { 0, 0, 0, 0 },
18138 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
18139 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xd300 }
18140 },
18141/* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
18142 {
18143 { 0, 0, 0, 0 },
18144 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18145 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xd50000 }
18146 },
18147/* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
18148 {
18149 { 0, 0, 0, 0 },
18150 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18151 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xd60000 }
18152 },
18153/* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
18154 {
18155 { 0, 0, 0, 0 },
18156 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
18157 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xd7000000 }
18158 },
18159/* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
18160 {
18161 { 0, 0, 0, 0 },
18162 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18163 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x882100 }
18164 },
18165/* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
18166 {
18167 { 0, 0, 0, 0 },
18168 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18169 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80a100 }
18170 },
18171/* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18172 {
18173 { 0, 0, 0, 0 },
18174 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18175 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x802100 }
18176 },
18177/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18178 {
18179 { 0, 0, 0, 0 },
18180 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18181 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82210000 }
18182 },
18183/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18184 {
18185 { 0, 0, 0, 0 },
18186 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18187 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a10000 }
18188 },
18189/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18190 {
18191 { 0, 0, 0, 0 },
18192 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18193 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e10000 }
18194 },
18195/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18196 {
18197 { 0, 0, 0, 0 },
18198 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18199 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84210000 }
18200 },
18201/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18202 {
18203 { 0, 0, 0, 0 },
18204 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18205 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a10000 }
18206 },
18207/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18208 {
18209 { 0, 0, 0, 0 },
18210 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18211 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e10000 }
18212 },
18213/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
18214 {
18215 { 0, 0, 0, 0 },
18216 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18217 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86e10000 }
18218 },
18219/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18220 {
18221 { 0, 0, 0, 0 },
18222 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18223 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86210000 }
18224 },
18225/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
18226 {
18227 { 0, 0, 0, 0 },
18228 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18229 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86a10000 }
18230 },
18231/* shl.l r1h,$Dst32RnUnprefixedSI */
18232 {
18233 { 0, 0, 0, 0 },
18234 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18235 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc801 }
18236 },
18237/* shl.l r1h,$Dst32AnUnprefixedSI */
18238 {
18239 { 0, 0, 0, 0 },
18240 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18241 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc081 }
18242 },
18243/* shl.l r1h,[$Dst32AnUnprefixed] */
18244 {
18245 { 0, 0, 0, 0 },
18246 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18247 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc001 }
18248 },
18249/* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18250 {
18251 { 0, 0, 0, 0 },
18252 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18253 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20100 }
18254 },
18255/* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18256 {
18257 { 0, 0, 0, 0 },
18258 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18259 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4010000 }
18260 },
18261/* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18262 {
18263 { 0, 0, 0, 0 },
18264 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18265 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6010000 }
18266 },
18267/* shl.l r1h,${Dsp-16-u8}[sb] */
18268 {
18269 { 0, 0, 0, 0 },
18270 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18271 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28100 }
18272 },
18273/* shl.l r1h,${Dsp-16-u16}[sb] */
18274 {
18275 { 0, 0, 0, 0 },
18276 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18277 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4810000 }
18278 },
18279/* shl.l r1h,${Dsp-16-s8}[fb] */
18280 {
18281 { 0, 0, 0, 0 },
18282 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18283 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c100 }
18284 },
18285/* shl.l r1h,${Dsp-16-s16}[fb] */
18286 {
18287 { 0, 0, 0, 0 },
18288 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18289 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c10000 }
18290 },
18291/* shl.l r1h,${Dsp-16-u16} */
18292 {
18293 { 0, 0, 0, 0 },
18294 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18295 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c10000 }
18296 },
18297/* shl.l r1h,${Dsp-16-u24} */
18298 {
18299 { 0, 0, 0, 0 },
18300 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18301 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6810000 }
18302 },
18303/* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
18304 {
18305 { 0, 0, 0, 0 },
18306 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18307 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x982100 }
18308 },
18309/* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
18310 {
18311 { 0, 0, 0, 0 },
18312 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18313 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90a100 }
18314 },
18315/* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18316 {
18317 { 0, 0, 0, 0 },
18318 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18319 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x902100 }
18320 },
18321/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18322 {
18323 { 0, 0, 0, 0 },
18324 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18325 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92210000 }
18326 },
18327/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18328 {
18329 { 0, 0, 0, 0 },
18330 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18331 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92a10000 }
18332 },
18333/* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18334 {
18335 { 0, 0, 0, 0 },
18336 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18337 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92e10000 }
18338 },
18339/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18340 {
18341 { 0, 0, 0, 0 },
18342 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18343 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94210000 }
18344 },
18345/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18346 {
18347 { 0, 0, 0, 0 },
18348 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18349 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94a10000 }
18350 },
18351/* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18352 {
18353 { 0, 0, 0, 0 },
18354 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18355 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94e10000 }
18356 },
18357/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
18358 {
18359 { 0, 0, 0, 0 },
18360 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18361 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96e10000 }
18362 },
18363/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18364 {
18365 { 0, 0, 0, 0 },
18366 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18367 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96210000 }
18368 },
18369/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
18370 {
18371 { 0, 0, 0, 0 },
18372 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18373 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96a10000 }
18374 },
18375/* shl.w r1h,$Dst32RnUnprefixedHI */
18376 {
18377 { 0, 0, 0, 0 },
18378 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18379 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93e }
18380 },
18381/* shl.w r1h,$Dst32AnUnprefixedHI */
18382 {
18383 { 0, 0, 0, 0 },
18384 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18385 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1be }
18386 },
18387/* shl.w r1h,[$Dst32AnUnprefixed] */
18388 {
18389 { 0, 0, 0, 0 },
18390 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18391 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13e }
18392 },
18393/* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18394 {
18395 { 0, 0, 0, 0 },
18396 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18397 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33e00 }
18398 },
18399/* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18400 {
18401 { 0, 0, 0, 0 },
18402 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18403 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53e0000 }
18404 },
18405/* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18406 {
18407 { 0, 0, 0, 0 },
18408 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18409 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73e0000 }
18410 },
18411/* shl.w r1h,${Dsp-16-u8}[sb] */
18412 {
18413 { 0, 0, 0, 0 },
18414 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18415 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3be00 }
18416 },
18417/* shl.w r1h,${Dsp-16-u16}[sb] */
18418 {
18419 { 0, 0, 0, 0 },
18420 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18421 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5be0000 }
18422 },
18423/* shl.w r1h,${Dsp-16-s8}[fb] */
18424 {
18425 { 0, 0, 0, 0 },
18426 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18427 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3fe00 }
18428 },
18429/* shl.w r1h,${Dsp-16-s16}[fb] */
18430 {
18431 { 0, 0, 0, 0 },
18432 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18433 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5fe0000 }
18434 },
18435/* shl.w r1h,${Dsp-16-u16} */
18436 {
18437 { 0, 0, 0, 0 },
18438 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18439 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7fe0000 }
18440 },
18441/* shl.w r1h,${Dsp-16-u24} */
18442 {
18443 { 0, 0, 0, 0 },
18444 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18445 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7be0000 }
18446 },
18447/* shl.b r1h,$Dst32RnUnprefixedQI */
18448 {
18449 { 0, 0, 0, 0 },
18450 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18451 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83e }
18452 },
18453/* shl.b r1h,$Dst32AnUnprefixedQI */
18454 {
18455 { 0, 0, 0, 0 },
18456 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18457 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0be }
18458 },
18459/* shl.b r1h,[$Dst32AnUnprefixed] */
18460 {
18461 { 0, 0, 0, 0 },
18462 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18463 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03e }
18464 },
18465/* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18466 {
18467 { 0, 0, 0, 0 },
18468 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18469 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23e00 }
18470 },
18471/* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18472 {
18473 { 0, 0, 0, 0 },
18474 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18475 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43e0000 }
18476 },
18477/* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18478 {
18479 { 0, 0, 0, 0 },
18480 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18481 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63e0000 }
18482 },
18483/* shl.b r1h,${Dsp-16-u8}[sb] */
18484 {
18485 { 0, 0, 0, 0 },
18486 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18487 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2be00 }
18488 },
18489/* shl.b r1h,${Dsp-16-u16}[sb] */
18490 {
18491 { 0, 0, 0, 0 },
18492 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18493 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4be0000 }
18494 },
18495/* shl.b r1h,${Dsp-16-s8}[fb] */
18496 {
18497 { 0, 0, 0, 0 },
18498 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18499 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2fe00 }
18500 },
18501/* shl.b r1h,${Dsp-16-s16}[fb] */
18502 {
18503 { 0, 0, 0, 0 },
18504 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18505 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4fe0000 }
18506 },
18507/* shl.b r1h,${Dsp-16-u16} */
18508 {
18509 { 0, 0, 0, 0 },
18510 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18511 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6fe0000 }
18512 },
18513/* shl.b r1h,${Dsp-16-u24} */
18514 {
18515 { 0, 0, 0, 0 },
18516 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18517 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6be0000 }
18518 },
18519/* shl.w r1h,$Dst16RnHI */
18520 {
18521 { 0, 0, 0, 0 },
18522 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
18523 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75e0 }
18524 },
18525/* shl.w r1h,$Dst16AnHI */
18526 {
18527 { 0, 0, 0, 0 },
18528 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
18529 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75e4 }
18530 },
18531/* shl.w r1h,[$Dst16An] */
18532 {
18533 { 0, 0, 0, 0 },
18534 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
18535 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75e6 }
18536 },
18537/* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
18538 {
18539 { 0, 0, 0, 0 },
18540 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18541 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75e800 }
18542 },
18543/* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
18544 {
18545 { 0, 0, 0, 0 },
18546 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18547 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75ec0000 }
18548 },
18549/* shl.w r1h,${Dsp-16-u8}[sb] */
18550 {
18551 { 0, 0, 0, 0 },
18552 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18553 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75ea00 }
18554 },
18555/* shl.w r1h,${Dsp-16-u16}[sb] */
18556 {
18557 { 0, 0, 0, 0 },
18558 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18559 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75ee0000 }
18560 },
18561/* shl.w r1h,${Dsp-16-s8}[fb] */
18562 {
18563 { 0, 0, 0, 0 },
18564 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18565 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75eb00 }
18566 },
18567/* shl.w r1h,${Dsp-16-u16} */
18568 {
18569 { 0, 0, 0, 0 },
18570 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18571 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ef0000 }
18572 },
18573/* shl.b r1h,$Dst16RnQI */
18574 {
18575 { 0, 0, 0, 0 },
18576 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
18577 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74e0 }
18578 },
18579/* shl.b r1h,$Dst16AnQI */
18580 {
18581 { 0, 0, 0, 0 },
18582 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
18583 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74e4 }
18584 },
18585/* shl.b r1h,[$Dst16An] */
18586 {
18587 { 0, 0, 0, 0 },
18588 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
18589 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74e6 }
18590 },
18591/* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
18592 {
18593 { 0, 0, 0, 0 },
18594 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18595 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74e800 }
18596 },
18597/* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
18598 {
18599 { 0, 0, 0, 0 },
18600 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18601 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74ec0000 }
18602 },
18603/* shl.b r1h,${Dsp-16-u8}[sb] */
18604 {
18605 { 0, 0, 0, 0 },
18606 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18607 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74ea00 }
18608 },
18609/* shl.b r1h,${Dsp-16-u16}[sb] */
18610 {
18611 { 0, 0, 0, 0 },
18612 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18613 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74ee0000 }
18614 },
18615/* shl.b r1h,${Dsp-16-s8}[fb] */
18616 {
18617 { 0, 0, 0, 0 },
18618 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18619 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74eb00 }
18620 },
18621/* shl.b r1h,${Dsp-16-u16} */
18622 {
18623 { 0, 0, 0, 0 },
18624 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18625 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ef0000 }
18626 },
18627/* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
18628 {
18629 { 0, 0, 0, 0 },
18630 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18631 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe900 }
18632 },
18633/* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
18634 {
18635 { 0, 0, 0, 0 },
18636 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18637 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe180 }
18638 },
18639/* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
18640 {
18641 { 0, 0, 0, 0 },
18642 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18643 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe100 }
18644 },
18645/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18646 {
18647 { 0, 0, 0, 0 },
18648 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18649 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe30000 }
18650 },
18651/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18652 {
18653 { 0, 0, 0, 0 },
18654 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18655 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5000000 }
18656 },
18657/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18658 {
18659 { 0, 0, 0, 0 },
18660 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18661 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7000000 }
18662 },
18663/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
18664 {
18665 { 0, 0, 0, 0 },
18666 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18667 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe38000 }
18668 },
18669/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
18670 {
18671 { 0, 0, 0, 0 },
18672 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18673 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5800000 }
18674 },
18675/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
18676 {
18677 { 0, 0, 0, 0 },
18678 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18679 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3c000 }
18680 },
18681/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
18682 {
18683 { 0, 0, 0, 0 },
18684 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18685 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5c00000 }
18686 },
18687/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
18688 {
18689 { 0, 0, 0, 0 },
18690 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
18691 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7c00000 }
18692 },
18693/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
18694 {
18695 { 0, 0, 0, 0 },
18696 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
18697 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7800000 }
18698 },
18699/* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
18700 {
18701 { 0, 0, 0, 0 },
18702 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18703 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe800 }
18704 },
18705/* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
18706 {
18707 { 0, 0, 0, 0 },
18708 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18709 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe080 }
18710 },
18711/* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
18712 {
18713 { 0, 0, 0, 0 },
18714 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18715 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe000 }
18716 },
18717/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18718 {
18719 { 0, 0, 0, 0 },
18720 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18721 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe20000 }
18722 },
18723/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18724 {
18725 { 0, 0, 0, 0 },
18726 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18727 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4000000 }
18728 },
18729/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18730 {
18731 { 0, 0, 0, 0 },
18732 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18733 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6000000 }
18734 },
18735/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
18736 {
18737 { 0, 0, 0, 0 },
18738 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18739 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe28000 }
18740 },
18741/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
18742 {
18743 { 0, 0, 0, 0 },
18744 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18745 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4800000 }
18746 },
18747/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
18748 {
18749 { 0, 0, 0, 0 },
18750 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18751 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2c000 }
18752 },
18753/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
18754 {
18755 { 0, 0, 0, 0 },
18756 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18757 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4c00000 }
18758 },
18759/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
18760 {
18761 { 0, 0, 0, 0 },
18762 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
18763 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6c00000 }
18764 },
18765/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
18766 {
18767 { 0, 0, 0, 0 },
18768 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
18769 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6800000 }
18770 },
18771/* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
18772 {
18773 { 0, 0, 0, 0 },
18774 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
18775 & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe900 }
18776 },
18777/* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
18778 {
18779 { 0, 0, 0, 0 },
18780 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
18781 & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe904 }
18782 },
18783/* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
18784 {
18785 { 0, 0, 0, 0 },
18786 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
18787 & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe906 }
18788 },
18789/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
18790 {
18791 { 0, 0, 0, 0 },
18792 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18793 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe90800 }
18794 },
18795/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
18796 {
18797 { 0, 0, 0, 0 },
18798 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18799 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe90c0000 }
18800 },
18801/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
18802 {
18803 { 0, 0, 0, 0 },
18804 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18805 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe90a00 }
18806 },
18807/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
18808 {
18809 { 0, 0, 0, 0 },
18810 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18811 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe90e0000 }
18812 },
18813/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
18814 {
18815 { 0, 0, 0, 0 },
18816 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18817 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe90b00 }
18818 },
18819/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
18820 {
18821 { 0, 0, 0, 0 },
18822 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
18823 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe90f0000 }
18824 },
18825/* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
18826 {
18827 { 0, 0, 0, 0 },
18828 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
18829 & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe800 }
18830 },
18831/* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
18832 {
18833 { 0, 0, 0, 0 },
18834 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
18835 & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe804 }
18836 },
18837/* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
18838 {
18839 { 0, 0, 0, 0 },
18840 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
18841 & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe806 }
18842 },
18843/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
18844 {
18845 { 0, 0, 0, 0 },
18846 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18847 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe80800 }
18848 },
18849/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
18850 {
18851 { 0, 0, 0, 0 },
18852 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18853 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe80c0000 }
18854 },
18855/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
18856 {
18857 { 0, 0, 0, 0 },
18858 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18859 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe80a00 }
18860 },
18861/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
18862 {
18863 { 0, 0, 0, 0 },
18864 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18865 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe80e0000 }
18866 },
18867/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
18868 {
18869 { 0, 0, 0, 0 },
18870 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18871 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe80b00 }
18872 },
18873/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
18874 {
18875 { 0, 0, 0, 0 },
18876 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
18877 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe80f0000 }
18878 },
18879/* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
18880 {
18881 { 0, 0, 0, 0 },
18882 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18883 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xc82100 }
18884 },
18885/* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
18886 {
18887 { 0, 0, 0, 0 },
18888 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18889 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xc0a100 }
18890 },
18891/* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18892 {
18893 { 0, 0, 0, 0 },
18894 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18895 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xc02100 }
18896 },
18897/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18898 {
18899 { 0, 0, 0, 0 },
18900 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18901 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xc2210000 }
18902 },
18903/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18904 {
18905 { 0, 0, 0, 0 },
18906 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18907 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc2a10000 }
18908 },
18909/* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18910 {
18911 { 0, 0, 0, 0 },
18912 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18913 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2e10000 }
18914 },
18915/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18916 {
18917 { 0, 0, 0, 0 },
18918 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18919 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4210000 }
18920 },
18921/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18922 {
18923 { 0, 0, 0, 0 },
18924 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18925 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4a10000 }
18926 },
18927/* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18928 {
18929 { 0, 0, 0, 0 },
18930 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18931 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4e10000 }
18932 },
18933/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
18934 {
18935 { 0, 0, 0, 0 },
18936 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18937 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xc6e10000 }
18938 },
18939/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18940 {
18941 { 0, 0, 0, 0 },
18942 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18943 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6210000 }
18944 },
18945/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
18946 {
18947 { 0, 0, 0, 0 },
18948 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18949 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xc6a10000 }
18950 },
18951/* sha.l r1h,$Dst32RnUnprefixedSI */
18952 {
18953 { 0, 0, 0, 0 },
18954 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18955 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc811 }
18956 },
18957/* sha.l r1h,$Dst32AnUnprefixedSI */
18958 {
18959 { 0, 0, 0, 0 },
18960 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18961 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc091 }
18962 },
18963/* sha.l r1h,[$Dst32AnUnprefixed] */
18964 {
18965 { 0, 0, 0, 0 },
18966 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18967 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc011 }
18968 },
18969/* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18970 {
18971 { 0, 0, 0, 0 },
18972 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18973 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc21100 }
18974 },
18975/* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18976 {
18977 { 0, 0, 0, 0 },
18978 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18979 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4110000 }
18980 },
18981/* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18982 {
18983 { 0, 0, 0, 0 },
18984 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18985 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6110000 }
18986 },
18987/* sha.l r1h,${Dsp-16-u8}[sb] */
18988 {
18989 { 0, 0, 0, 0 },
18990 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18991 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc29100 }
18992 },
18993/* sha.l r1h,${Dsp-16-u16}[sb] */
18994 {
18995 { 0, 0, 0, 0 },
18996 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18997 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4910000 }
18998 },
18999/* sha.l r1h,${Dsp-16-s8}[fb] */
19000 {
19001 { 0, 0, 0, 0 },
19002 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19003 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2d100 }
19004 },
19005/* sha.l r1h,${Dsp-16-s16}[fb] */
19006 {
19007 { 0, 0, 0, 0 },
19008 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19009 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4d10000 }
19010 },
19011/* sha.l r1h,${Dsp-16-u16} */
19012 {
19013 { 0, 0, 0, 0 },
19014 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19015 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6d10000 }
19016 },
19017/* sha.l r1h,${Dsp-16-u24} */
19018 {
19019 { 0, 0, 0, 0 },
19020 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19021 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6910000 }
19022 },
19023/* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
19024 {
19025 { 0, 0, 0, 0 },
19026 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
19027 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa82100 }
19028 },
19029/* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
19030 {
19031 { 0, 0, 0, 0 },
19032 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
19033 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0a100 }
19034 },
19035/* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19036 {
19037 { 0, 0, 0, 0 },
19038 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19039 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa02100 }
19040 },
19041/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19042 {
19043 { 0, 0, 0, 0 },
19044 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19045 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2210000 }
19046 },
19047/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19048 {
19049 { 0, 0, 0, 0 },
19050 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19051 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2a10000 }
19052 },
19053/* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19054 {
19055 { 0, 0, 0, 0 },
19056 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19057 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2e10000 }
19058 },
19059/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19060 {
19061 { 0, 0, 0, 0 },
19062 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19063 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4210000 }
19064 },
19065/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19066 {
19067 { 0, 0, 0, 0 },
19068 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19069 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4a10000 }
19070 },
19071/* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19072 {
19073 { 0, 0, 0, 0 },
19074 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19075 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4e10000 }
19076 },
19077/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
19078 {
19079 { 0, 0, 0, 0 },
19080 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
19081 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6e10000 }
19082 },
19083/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19084 {
19085 { 0, 0, 0, 0 },
19086 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19087 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6210000 }
19088 },
19089/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
19090 {
19091 { 0, 0, 0, 0 },
19092 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
19093 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6a10000 }
19094 },
19095/* sha.w r1h,$Dst32RnUnprefixedHI */
19096 {
19097 { 0, 0, 0, 0 },
19098 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
19099 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb93e }
19100 },
19101/* sha.w r1h,$Dst32AnUnprefixedHI */
19102 {
19103 { 0, 0, 0, 0 },
19104 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
19105 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1be }
19106 },
19107/* sha.w r1h,[$Dst32AnUnprefixed] */
19108 {
19109 { 0, 0, 0, 0 },
19110 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19111 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb13e }
19112 },
19113/* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19114 {
19115 { 0, 0, 0, 0 },
19116 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19117 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33e00 }
19118 },
19119/* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19120 {
19121 { 0, 0, 0, 0 },
19122 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19123 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb53e0000 }
19124 },
19125/* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19126 {
19127 { 0, 0, 0, 0 },
19128 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19129 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb73e0000 }
19130 },
19131/* sha.w r1h,${Dsp-16-u8}[sb] */
19132 {
19133 { 0, 0, 0, 0 },
19134 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19135 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3be00 }
19136 },
19137/* sha.w r1h,${Dsp-16-u16}[sb] */
19138 {
19139 { 0, 0, 0, 0 },
19140 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19141 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5be0000 }
19142 },
19143/* sha.w r1h,${Dsp-16-s8}[fb] */
19144 {
19145 { 0, 0, 0, 0 },
19146 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19147 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3fe00 }
19148 },
19149/* sha.w r1h,${Dsp-16-s16}[fb] */
19150 {
19151 { 0, 0, 0, 0 },
19152 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19153 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5fe0000 }
19154 },
19155/* sha.w r1h,${Dsp-16-u16} */
19156 {
19157 { 0, 0, 0, 0 },
19158 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19159 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7fe0000 }
19160 },
19161/* sha.w r1h,${Dsp-16-u24} */
19162 {
19163 { 0, 0, 0, 0 },
19164 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19165 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7be0000 }
19166 },
19167/* sha.b r1h,$Dst32RnUnprefixedQI */
19168 {
19169 { 0, 0, 0, 0 },
19170 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
19171 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb83e }
19172 },
19173/* sha.b r1h,$Dst32AnUnprefixedQI */
19174 {
19175 { 0, 0, 0, 0 },
19176 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
19177 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0be }
19178 },
19179/* sha.b r1h,[$Dst32AnUnprefixed] */
19180 {
19181 { 0, 0, 0, 0 },
19182 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19183 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb03e }
19184 },
19185/* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19186 {
19187 { 0, 0, 0, 0 },
19188 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19189 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb23e00 }
19190 },
19191/* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19192 {
19193 { 0, 0, 0, 0 },
19194 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19195 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb43e0000 }
19196 },
19197/* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19198 {
19199 { 0, 0, 0, 0 },
19200 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19201 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb63e0000 }
19202 },
19203/* sha.b r1h,${Dsp-16-u8}[sb] */
19204 {
19205 { 0, 0, 0, 0 },
19206 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19207 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2be00 }
19208 },
19209/* sha.b r1h,${Dsp-16-u16}[sb] */
19210 {
19211 { 0, 0, 0, 0 },
19212 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19213 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4be0000 }
19214 },
19215/* sha.b r1h,${Dsp-16-s8}[fb] */
19216 {
19217 { 0, 0, 0, 0 },
19218 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19219 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2fe00 }
19220 },
19221/* sha.b r1h,${Dsp-16-s16}[fb] */
19222 {
19223 { 0, 0, 0, 0 },
19224 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19225 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4fe0000 }
19226 },
19227/* sha.b r1h,${Dsp-16-u16} */
19228 {
19229 { 0, 0, 0, 0 },
19230 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19231 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6fe0000 }
19232 },
19233/* sha.b r1h,${Dsp-16-u24} */
19234 {
19235 { 0, 0, 0, 0 },
19236 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19237 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6be0000 }
19238 },
19239/* sha.w r1h,$Dst16RnHI */
19240 {
19241 { 0, 0, 0, 0 },
19242 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
19243 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75f0 }
19244 },
19245/* sha.w r1h,$Dst16AnHI */
19246 {
19247 { 0, 0, 0, 0 },
19248 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
19249 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75f4 }
19250 },
19251/* sha.w r1h,[$Dst16An] */
19252 {
19253 { 0, 0, 0, 0 },
19254 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
19255 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75f6 }
19256 },
19257/* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
19258 {
19259 { 0, 0, 0, 0 },
19260 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19261 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75f800 }
19262 },
19263/* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
19264 {
19265 { 0, 0, 0, 0 },
19266 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19267 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75fc0000 }
19268 },
19269/* sha.w r1h,${Dsp-16-u8}[sb] */
19270 {
19271 { 0, 0, 0, 0 },
19272 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19273 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75fa00 }
19274 },
19275/* sha.w r1h,${Dsp-16-u16}[sb] */
19276 {
19277 { 0, 0, 0, 0 },
19278 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19279 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75fe0000 }
19280 },
19281/* sha.w r1h,${Dsp-16-s8}[fb] */
19282 {
19283 { 0, 0, 0, 0 },
19284 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19285 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75fb00 }
19286 },
19287/* sha.w r1h,${Dsp-16-u16} */
19288 {
19289 { 0, 0, 0, 0 },
19290 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19291 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ff0000 }
19292 },
19293/* sha.b r1h,$Dst16RnQI */
19294 {
19295 { 0, 0, 0, 0 },
19296 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
19297 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74f0 }
19298 },
19299/* sha.b r1h,$Dst16AnQI */
19300 {
19301 { 0, 0, 0, 0 },
19302 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
19303 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74f4 }
19304 },
19305/* sha.b r1h,[$Dst16An] */
19306 {
19307 { 0, 0, 0, 0 },
19308 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
19309 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74f6 }
19310 },
19311/* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
19312 {
19313 { 0, 0, 0, 0 },
19314 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19315 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74f800 }
19316 },
19317/* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
19318 {
19319 { 0, 0, 0, 0 },
19320 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19321 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74fc0000 }
19322 },
19323/* sha.b r1h,${Dsp-16-u8}[sb] */
19324 {
19325 { 0, 0, 0, 0 },
19326 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19327 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74fa00 }
19328 },
19329/* sha.b r1h,${Dsp-16-u16}[sb] */
19330 {
19331 { 0, 0, 0, 0 },
19332 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19333 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74fe0000 }
19334 },
19335/* sha.b r1h,${Dsp-16-s8}[fb] */
19336 {
19337 { 0, 0, 0, 0 },
19338 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19339 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74fb00 }
19340 },
19341/* sha.b r1h,${Dsp-16-u16} */
19342 {
19343 { 0, 0, 0, 0 },
19344 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19345 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ff0000 }
19346 },
19347/* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
19348 {
19349 { 0, 0, 0, 0 },
19350 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
19351 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf900 }
19352 },
19353/* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
19354 {
19355 { 0, 0, 0, 0 },
19356 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
19357 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf180 }
19358 },
19359/* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
19360 {
19361 { 0, 0, 0, 0 },
19362 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19363 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf100 }
19364 },
19365/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19366 {
19367 { 0, 0, 0, 0 },
19368 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19369 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf30000 }
19370 },
19371/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19372 {
19373 { 0, 0, 0, 0 },
19374 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19375 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5000000 }
19376 },
19377/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19378 {
19379 { 0, 0, 0, 0 },
19380 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19381 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7000000 }
19382 },
19383/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
19384 {
19385 { 0, 0, 0, 0 },
19386 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19387 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf38000 }
19388 },
19389/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
19390 {
19391 { 0, 0, 0, 0 },
19392 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19393 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5800000 }
19394 },
19395/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
19396 {
19397 { 0, 0, 0, 0 },
19398 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19399 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3c000 }
19400 },
19401/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
19402 {
19403 { 0, 0, 0, 0 },
19404 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19405 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5c00000 }
19406 },
19407/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
19408 {
19409 { 0, 0, 0, 0 },
19410 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
19411 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7c00000 }
19412 },
19413/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
19414 {
19415 { 0, 0, 0, 0 },
19416 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
19417 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7800000 }
19418 },
19419/* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
19420 {
19421 { 0, 0, 0, 0 },
19422 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
19423 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf800 }
19424 },
19425/* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
19426 {
19427 { 0, 0, 0, 0 },
19428 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
19429 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf080 }
19430 },
19431/* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
19432 {
19433 { 0, 0, 0, 0 },
19434 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19435 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf000 }
19436 },
19437/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19438 {
19439 { 0, 0, 0, 0 },
19440 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19441 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf20000 }
19442 },
19443/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19444 {
19445 { 0, 0, 0, 0 },
19446 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19447 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4000000 }
19448 },
19449/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19450 {
19451 { 0, 0, 0, 0 },
19452 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19453 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6000000 }
19454 },
19455/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
19456 {
19457 { 0, 0, 0, 0 },
19458 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19459 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf28000 }
19460 },
19461/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
19462 {
19463 { 0, 0, 0, 0 },
19464 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19465 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4800000 }
19466 },
19467/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
19468 {
19469 { 0, 0, 0, 0 },
19470 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19471 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2c000 }
19472 },
19473/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
19474 {
19475 { 0, 0, 0, 0 },
19476 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19477 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4c00000 }
19478 },
19479/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
19480 {
19481 { 0, 0, 0, 0 },
19482 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
19483 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6c00000 }
19484 },
19485/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
19486 {
19487 { 0, 0, 0, 0 },
19488 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
19489 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6800000 }
19490 },
19491/* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
19492 {
19493 { 0, 0, 0, 0 },
19494 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
19495 & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xf100 }
19496 },
19497/* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
19498 {
19499 { 0, 0, 0, 0 },
19500 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
19501 & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xf104 }
19502 },
19503/* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
19504 {
19505 { 0, 0, 0, 0 },
19506 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19507 & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xf106 }
19508 },
19509/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19510 {
19511 { 0, 0, 0, 0 },
19512 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19513 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xf10800 }
19514 },
19515/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19516 {
19517 { 0, 0, 0, 0 },
19518 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19519 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xf10c0000 }
19520 },
19521/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19522 {
19523 { 0, 0, 0, 0 },
19524 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19525 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xf10a00 }
19526 },
19527/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19528 {
19529 { 0, 0, 0, 0 },
19530 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19531 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xf10e0000 }
19532 },
19533/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19534 {
19535 { 0, 0, 0, 0 },
19536 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19537 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xf10b00 }
19538 },
19539/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19540 {
19541 { 0, 0, 0, 0 },
19542 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19543 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xf10f0000 }
19544 },
19545/* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
19546 {
19547 { 0, 0, 0, 0 },
19548 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
19549 & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xf000 }
19550 },
19551/* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
19552 {
19553 { 0, 0, 0, 0 },
19554 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
19555 & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xf004 }
19556 },
19557/* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
19558 {
19559 { 0, 0, 0, 0 },
19560 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19561 & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xf006 }
19562 },
19563/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19564 {
19565 { 0, 0, 0, 0 },
19566 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19567 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xf00800 }
19568 },
19569/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19570 {
19571 { 0, 0, 0, 0 },
19572 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19573 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xf00c0000 }
19574 },
19575/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19576 {
19577 { 0, 0, 0, 0 },
19578 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19579 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xf00a00 }
19580 },
19581/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19582 {
19583 { 0, 0, 0, 0 },
19584 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19585 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xf00e0000 }
19586 },
19587/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19588 {
19589 { 0, 0, 0, 0 },
19590 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19591 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xf00b00 }
19592 },
19593/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19594 {
19595 { 0, 0, 0, 0 },
19596 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19597 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xf00f0000 }
19598 },
19599/* sc${sccond32} $Dst32RnUnprefixedHI */
19600 {
19601 { 0, 0, 0, 0 },
19602 { { MNEM, OP (SCCOND32), ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
19603 & ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI, { 0xd930 }
19604 },
19605/* sc${sccond32} $Dst32AnUnprefixedHI */
19606 {
19607 { 0, 0, 0, 0 },
19608 { { MNEM, OP (SCCOND32), ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
19609 & ifmt_sccnd_dst32_An_direct_Unprefixed_HI, { 0xd1b0 }
19610 },
19611/* sc${sccond32} [$Dst32AnUnprefixed] */
19612 {
19613 { 0, 0, 0, 0 },
19614 { { MNEM, OP (SCCOND32), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19615 & ifmt_sccnd_dst32_An_indirect_Unprefixed_HI, { 0xd130 }
19616 },
19617/* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19618 {
19619 { 0, 0, 0, 0 },
19620 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19621 & ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI, { 0xd33000 }
19622 },
19623/* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19624 {
19625 { 0, 0, 0, 0 },
19626 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19627 & ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5300000 }
19628 },
19629/* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19630 {
19631 { 0, 0, 0, 0 },
19632 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19633 & ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7300000 }
19634 },
19635/* sc${sccond32} ${Dsp-16-u8}[sb] */
19636 {
19637 { 0, 0, 0, 0 },
19638 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19639 & ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd3b000 }
19640 },
19641/* sc${sccond32} ${Dsp-16-u16}[sb] */
19642 {
19643 { 0, 0, 0, 0 },
19644 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19645 & ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5b00000 }
19646 },
19647/* sc${sccond32} ${Dsp-16-s8}[fb] */
19648 {
19649 { 0, 0, 0, 0 },
19650 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19651 & ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3f000 }
19652 },
19653/* sc${sccond32} ${Dsp-16-s16}[fb] */
19654 {
19655 { 0, 0, 0, 0 },
19656 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19657 & ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5f00000 }
19658 },
19659/* sc${sccond32} ${Dsp-16-u16} */
19660 {
19661 { 0, 0, 0, 0 },
19662 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), 0 } },
19663 & ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI, { 0xd7f00000 }
19664 },
19665/* sc${sccond32} ${Dsp-16-u24} */
19666 {
19667 { 0, 0, 0, 0 },
19668 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), 0 } },
19669 & ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI, { 0xd7b00000 }
19670 },
19671/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
19672 {
19673 { 0, 0, 0, 0 },
19674 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
19675 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
19676 },
19677/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
19678 {
19679 { 0, 0, 0, 0 },
19680 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
19681 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
19682 },
19683/* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
19684 {
19685 { 0, 0, 0, 0 },
19686 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
19687 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
19688 },
19689/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
19690 {
19691 { 0, 0, 0, 0 },
19692 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
19693 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
19694 },
19695/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
19696 {
19697 { 0, 0, 0, 0 },
19698 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
19699 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
19700 },
19701/* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
19702 {
19703 { 0, 0, 0, 0 },
19704 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
19705 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
19706 },
19707/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
19708 {
19709 { 0, 0, 0, 0 },
19710 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
19711 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
19712 },
19713/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
19714 {
19715 { 0, 0, 0, 0 },
19716 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
19717 & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
19718 },
19719/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
19720 {
19721 { 0, 0, 0, 0 },
19722 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
19723 & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
19724 },
19725/* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
19726 {
19727 { 0, 0, 0, 0 },
19728 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
19729 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
19730 },
19731/* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
19732 {
19733 { 0, 0, 0, 0 },
19734 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
19735 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
19736 },
19737/* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
19738 {
19739 { 0, 0, 0, 0 },
19740 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
19741 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
19742 },
19743/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
19744 {
19745 { 0, 0, 0, 0 },
19746 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
19747 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
19748 },
19749/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
19750 {
19751 { 0, 0, 0, 0 },
19752 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
19753 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
19754 },
19755/* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
19756 {
19757 { 0, 0, 0, 0 },
19758 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
19759 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
19760 },
19761/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
19762 {
19763 { 0, 0, 0, 0 },
19764 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
19765 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
19766 },
19767/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
19768 {
19769 { 0, 0, 0, 0 },
19770 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
19771 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
19772 },
19773/* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
19774 {
19775 { 0, 0, 0, 0 },
19776 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
19777 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
19778 },
19779/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
19780 {
19781 { 0, 0, 0, 0 },
19782 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
19783 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
19784 },
19785/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
19786 {
19787 { 0, 0, 0, 0 },
19788 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
19789 & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
19790 },
19791/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
19792 {
19793 { 0, 0, 0, 0 },
19794 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
19795 & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
19796 },
19797/* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
19798 {
19799 { 0, 0, 0, 0 },
19800 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
19801 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
19802 },
19803/* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
19804 {
19805 { 0, 0, 0, 0 },
19806 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
19807 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
19808 },
19809/* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
19810 {
19811 { 0, 0, 0, 0 },
19812 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
19813 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
19814 },
19815/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
19816 {
19817 { 0, 0, 0, 0 },
19818 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
19819 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
19820 },
19821/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
19822 {
19823 { 0, 0, 0, 0 },
19824 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
19825 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
19826 },
19827/* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
19828 {
19829 { 0, 0, 0, 0 },
19830 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
19831 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
19832 },
19833/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
19834 {
19835 { 0, 0, 0, 0 },
19836 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
19837 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
19838 },
19839/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
19840 {
19841 { 0, 0, 0, 0 },
19842 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
19843 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
19844 },
19845/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
19846 {
19847 { 0, 0, 0, 0 },
19848 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
19849 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
19850 },
19851/* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
19852 {
19853 { 0, 0, 0, 0 },
19854 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
19855 & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
19856 },
19857/* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
19858 {
19859 { 0, 0, 0, 0 },
19860 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
19861 & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
19862 },
19863/* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
19864 {
19865 { 0, 0, 0, 0 },
19866 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
19867 & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
19868 },
19869/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
19870 {
19871 { 0, 0, 0, 0 },
19872 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
19873 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
19874 },
19875/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
19876 {
19877 { 0, 0, 0, 0 },
19878 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
19879 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
19880 },
19881/* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
19882 {
19883 { 0, 0, 0, 0 },
19884 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
19885 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
19886 },
19887/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
19888 {
19889 { 0, 0, 0, 0 },
19890 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
19891 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
19892 },
19893/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
19894 {
19895 { 0, 0, 0, 0 },
19896 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
19897 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
19898 },
19899/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
19900 {
19901 { 0, 0, 0, 0 },
19902 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
19903 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
19904 },
19905/* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
19906 {
19907 { 0, 0, 0, 0 },
19908 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
19909 & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
19910 },
19911/* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
19912 {
19913 { 0, 0, 0, 0 },
19914 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
19915 & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
19916 },
19917/* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
19918 {
19919 { 0, 0, 0, 0 },
19920 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
19921 & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
19922 },
19923/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
19924 {
19925 { 0, 0, 0, 0 },
19926 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
19927 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990600 }
19928 },
19929/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
19930 {
19931 { 0, 0, 0, 0 },
19932 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
19933 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992600 }
19934 },
19935/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
19936 {
19937 { 0, 0, 0, 0 },
19938 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
19939 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993600 }
19940 },
19941/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
19942 {
19943 { 0, 0, 0, 0 },
19944 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
19945 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918600 }
19946 },
19947/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
19948 {
19949 { 0, 0, 0, 0 },
19950 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
19951 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a600 }
19952 },
19953/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
19954 {
19955 { 0, 0, 0, 0 },
19956 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
19957 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b600 }
19958 },
19959/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
19960 {
19961 { 0, 0, 0, 0 },
19962 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
19963 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910600 }
19964 },
19965/* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
19966 {
19967 { 0, 0, 0, 0 },
19968 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
19969 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912600 }
19970 },
19971/* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
19972 {
19973 { 0, 0, 0, 0 },
19974 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
19975 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913600 }
19976 },
19977/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
19978 {
19979 { 0, 0, 0, 0 },
19980 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
19981 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930600 }
19982 },
19983/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
19984 {
19985 { 0, 0, 0, 0 },
19986 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
19987 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932600 }
19988 },
19989/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
19990 {
19991 { 0, 0, 0, 0 },
19992 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
19993 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933600 }
19994 },
19995/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
19996 {
19997 { 0, 0, 0, 0 },
19998 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
19999 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950600 }
20000 },
20001/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20002 {
20003 { 0, 0, 0, 0 },
20004 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20005 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952600 }
20006 },
20007/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20008 {
20009 { 0, 0, 0, 0 },
20010 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20011 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953600 }
20012 },
20013/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
20014 {
20015 { 0, 0, 0, 0 },
20016 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20017 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970600 }
20018 },
20019/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20020 {
20021 { 0, 0, 0, 0 },
20022 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20023 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972600 }
20024 },
20025/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20026 {
20027 { 0, 0, 0, 0 },
20028 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20029 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973600 }
20030 },
20031/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
20032 {
20033 { 0, 0, 0, 0 },
20034 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20035 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938600 }
20036 },
20037/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
20038 {
20039 { 0, 0, 0, 0 },
20040 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20041 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a600 }
20042 },
20043/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
20044 {
20045 { 0, 0, 0, 0 },
20046 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20047 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b600 }
20048 },
20049/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
20050 {
20051 { 0, 0, 0, 0 },
20052 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20053 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958600 }
20054 },
20055/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
20056 {
20057 { 0, 0, 0, 0 },
20058 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20059 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a600 }
20060 },
20061/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
20062 {
20063 { 0, 0, 0, 0 },
20064 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20065 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b600 }
20066 },
20067/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
20068 {
20069 { 0, 0, 0, 0 },
20070 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20071 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c600 }
20072 },
20073/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
20074 {
20075 { 0, 0, 0, 0 },
20076 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20077 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e600 }
20078 },
20079/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
20080 {
20081 { 0, 0, 0, 0 },
20082 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20083 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f600 }
20084 },
20085/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
20086 {
20087 { 0, 0, 0, 0 },
20088 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20089 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c600 }
20090 },
20091/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
20092 {
20093 { 0, 0, 0, 0 },
20094 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20095 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e600 }
20096 },
20097/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
20098 {
20099 { 0, 0, 0, 0 },
20100 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20101 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f600 }
20102 },
20103/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
20104 {
20105 { 0, 0, 0, 0 },
20106 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
20107 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c600 }
20108 },
20109/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
20110 {
20111 { 0, 0, 0, 0 },
20112 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20113 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e600 }
20114 },
20115/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
20116 {
20117 { 0, 0, 0, 0 },
20118 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20119 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f600 }
20120 },
20121/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
20122 {
20123 { 0, 0, 0, 0 },
20124 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
20125 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978600 }
20126 },
20127/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
20128 {
20129 { 0, 0, 0, 0 },
20130 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
20131 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a600 }
20132 },
20133/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
20134 {
20135 { 0, 0, 0, 0 },
20136 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
20137 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b600 }
20138 },
20139/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20140 {
20141 { 0, 0, 0, 0 },
20142 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20143 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90600 }
20144 },
20145/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
20146 {
20147 { 0, 0, 0, 0 },
20148 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20149 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92600 }
20150 },
20151/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
20152 {
20153 { 0, 0, 0, 0 },
20154 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20155 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93600 }
20156 },
20157/* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
20158 {
20159 { 0, 0, 0, 0 },
20160 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
20161 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93600 }
20162 },
20163/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20164 {
20165 { 0, 0, 0, 0 },
20166 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20167 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18600 }
20168 },
20169/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
20170 {
20171 { 0, 0, 0, 0 },
20172 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20173 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a600 }
20174 },
20175/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
20176 {
20177 { 0, 0, 0, 0 },
20178 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20179 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b600 }
20180 },
20181/* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
20182 {
20183 { 0, 0, 0, 0 },
20184 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
20185 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b600 }
20186 },
20187/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20188 {
20189 { 0, 0, 0, 0 },
20190 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20191 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10600 }
20192 },
20193/* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
20194 {
20195 { 0, 0, 0, 0 },
20196 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20197 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12600 }
20198 },
20199/* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
20200 {
20201 { 0, 0, 0, 0 },
20202 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20203 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13600 }
20204 },
20205/* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
20206 {
20207 { 0, 0, 0, 0 },
20208 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20209 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13600 }
20210 },
20211/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
20212 {
20213 { 0, 0, 0, 0 },
20214 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20215 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30600 }
20216 },
20217/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
20218 {
20219 { 0, 0, 0, 0 },
20220 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20221 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32600 }
20222 },
20223/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
20224 {
20225 { 0, 0, 0, 0 },
20226 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20227 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33600 }
20228 },
20229/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
20230 {
20231 { 0, 0, 0, 0 },
20232 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20233 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33600 }
20234 },
20235/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
20236 {
20237 { 0, 0, 0, 0 },
20238 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20239 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50600 }
20240 },
20241/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
20242 {
20243 { 0, 0, 0, 0 },
20244 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20245 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52600 }
20246 },
20247/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
20248 {
20249 { 0, 0, 0, 0 },
20250 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20251 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53600 }
20252 },
20253/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
20254 {
20255 { 0, 0, 0, 0 },
20256 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20257 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53600 }
20258 },
20259/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
20260 {
20261 { 0, 0, 0, 0 },
20262 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20263 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70600 }
20264 },
20265/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
20266 {
20267 { 0, 0, 0, 0 },
20268 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20269 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72600 }
20270 },
20271/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
20272 {
20273 { 0, 0, 0, 0 },
20274 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20275 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73600 }
20276 },
20277/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
20278 {
20279 { 0, 0, 0, 0 },
20280 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20281 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73600 }
20282 },
20283/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
20284 {
20285 { 0, 0, 0, 0 },
20286 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20287 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38600 }
20288 },
20289/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
20290 {
20291 { 0, 0, 0, 0 },
20292 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20293 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a600 }
20294 },
20295/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
20296 {
20297 { 0, 0, 0, 0 },
20298 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20299 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b600 }
20300 },
20301/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
20302 {
20303 { 0, 0, 0, 0 },
20304 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20305 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b600 }
20306 },
20307/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
20308 {
20309 { 0, 0, 0, 0 },
20310 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20311 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58600 }
20312 },
20313/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
20314 {
20315 { 0, 0, 0, 0 },
20316 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20317 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a600 }
20318 },
20319/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
20320 {
20321 { 0, 0, 0, 0 },
20322 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20323 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b600 }
20324 },
20325/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
20326 {
20327 { 0, 0, 0, 0 },
20328 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20329 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b600 }
20330 },
20331/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
20332 {
20333 { 0, 0, 0, 0 },
20334 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20335 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c600 }
20336 },
20337/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
20338 {
20339 { 0, 0, 0, 0 },
20340 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20341 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e600 }
20342 },
20343/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
20344 {
20345 { 0, 0, 0, 0 },
20346 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20347 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f600 }
20348 },
20349/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
20350 {
20351 { 0, 0, 0, 0 },
20352 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20353 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f600 }
20354 },
20355/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
20356 {
20357 { 0, 0, 0, 0 },
20358 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20359 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c600 }
20360 },
20361/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
20362 {
20363 { 0, 0, 0, 0 },
20364 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20365 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e600 }
20366 },
20367/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
20368 {
20369 { 0, 0, 0, 0 },
20370 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20371 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f600 }
20372 },
20373/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
20374 {
20375 { 0, 0, 0, 0 },
20376 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20377 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f600 }
20378 },
20379/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
20380 {
20381 { 0, 0, 0, 0 },
20382 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
20383 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c600 }
20384 },
20385/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
20386 {
20387 { 0, 0, 0, 0 },
20388 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
20389 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e600 }
20390 },
20391/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
20392 {
20393 { 0, 0, 0, 0 },
20394 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
20395 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f600 }
20396 },
20397/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
20398 {
20399 { 0, 0, 0, 0 },
20400 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
20401 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f600 }
20402 },
20403/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
20404 {
20405 { 0, 0, 0, 0 },
20406 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
20407 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78600 }
20408 },
20409/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
20410 {
20411 { 0, 0, 0, 0 },
20412 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
20413 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a600 }
20414 },
20415/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
20416 {
20417 { 0, 0, 0, 0 },
20418 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
20419 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b600 }
20420 },
20421/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
20422 {
20423 { 0, 0, 0, 0 },
20424 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
20425 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b600 }
20426 },
20427/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20428 {
20429 { 0, 0, 0, 0 },
20430 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20431 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90600 }
20432 },
20433/* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
20434 {
20435 { 0, 0, 0, 0 },
20436 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
20437 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92600 }
20438 },
20439/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20440 {
20441 { 0, 0, 0, 0 },
20442 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20443 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18600 }
20444 },
20445/* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
20446 {
20447 { 0, 0, 0, 0 },
20448 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
20449 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a600 }
20450 },
20451/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20452 {
20453 { 0, 0, 0, 0 },
20454 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20455 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10600 }
20456 },
20457/* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
20458 {
20459 { 0, 0, 0, 0 },
20460 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20461 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12600 }
20462 },
20463/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
20464 {
20465 { 0, 0, 0, 0 },
20466 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20467 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30600 }
20468 },
20469/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
20470 {
20471 { 0, 0, 0, 0 },
20472 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20473 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32600 }
20474 },
20475/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
20476 {
20477 { 0, 0, 0, 0 },
20478 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20479 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50600 }
20480 },
20481/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
20482 {
20483 { 0, 0, 0, 0 },
20484 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20485 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52600 }
20486 },
20487/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
20488 {
20489 { 0, 0, 0, 0 },
20490 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20491 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70600 }
20492 },
20493/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
20494 {
20495 { 0, 0, 0, 0 },
20496 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20497 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72600 }
20498 },
20499/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
20500 {
20501 { 0, 0, 0, 0 },
20502 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
20503 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38600 }
20504 },
20505/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
20506 {
20507 { 0, 0, 0, 0 },
20508 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
20509 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a600 }
20510 },
20511/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
20512 {
20513 { 0, 0, 0, 0 },
20514 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
20515 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58600 }
20516 },
20517/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
20518 {
20519 { 0, 0, 0, 0 },
20520 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
20521 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a600 }
20522 },
20523/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
20524 {
20525 { 0, 0, 0, 0 },
20526 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
20527 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c600 }
20528 },
20529/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
20530 {
20531 { 0, 0, 0, 0 },
20532 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
20533 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e600 }
20534 },
20535/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
20536 {
20537 { 0, 0, 0, 0 },
20538 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
20539 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c600 }
20540 },
20541/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
20542 {
20543 { 0, 0, 0, 0 },
20544 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
20545 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e600 }
20546 },
20547/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
20548 {
20549 { 0, 0, 0, 0 },
20550 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
20551 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c600 }
20552 },
20553/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
20554 {
20555 { 0, 0, 0, 0 },
20556 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
20557 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e600 }
20558 },
20559/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
20560 {
20561 { 0, 0, 0, 0 },
20562 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
20563 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78600 }
20564 },
20565/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
20566 {
20567 { 0, 0, 0, 0 },
20568 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
20569 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a600 }
20570 },
20571/* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
20572 {
20573 { 0, 0, 0, 0 },
20574 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
20575 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c906 }
20576 },
20577/* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
20578 {
20579 { 0, 0, 0, 0 },
20580 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
20581 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18926 }
20582 },
20583/* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
20584 {
20585 { 0, 0, 0, 0 },
20586 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20587 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18906 }
20588 },
20589/* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
20590 {
20591 { 0, 0, 0, 0 },
20592 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
20593 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c186 }
20594 },
20595/* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
20596 {
20597 { 0, 0, 0, 0 },
20598 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
20599 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a6 }
20600 },
20601/* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
20602 {
20603 { 0, 0, 0, 0 },
20604 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20605 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18186 }
20606 },
20607/* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
20608 {
20609 { 0, 0, 0, 0 },
20610 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20611 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c106 }
20612 },
20613/* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
20614 {
20615 { 0, 0, 0, 0 },
20616 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20617 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18126 }
20618 },
20619/* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
20620 {
20621 { 0, 0, 0, 0 },
20622 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20623 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18106 }
20624 },
20625/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
20626 {
20627 { 0, 0, 0, 0 },
20628 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20629 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30600 }
20630 },
20631/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
20632 {
20633 { 0, 0, 0, 0 },
20634 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20635 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832600 }
20636 },
20637/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
20638 {
20639 { 0, 0, 0, 0 },
20640 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20641 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830600 }
20642 },
20643/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
20644 {
20645 { 0, 0, 0, 0 },
20646 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20647 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50600 }
20648 },
20649/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
20650 {
20651 { 0, 0, 0, 0 },
20652 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20653 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852600 }
20654 },
20655/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
20656 {
20657 { 0, 0, 0, 0 },
20658 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20659 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850600 }
20660 },
20661/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
20662 {
20663 { 0, 0, 0, 0 },
20664 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20665 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70600 }
20666 },
20667/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
20668 {
20669 { 0, 0, 0, 0 },
20670 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20671 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872600 }
20672 },
20673/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
20674 {
20675 { 0, 0, 0, 0 },
20676 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20677 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870600 }
20678 },
20679/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
20680 {
20681 { 0, 0, 0, 0 },
20682 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20683 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38600 }
20684 },
20685/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
20686 {
20687 { 0, 0, 0, 0 },
20688 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20689 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a600 }
20690 },
20691/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
20692 {
20693 { 0, 0, 0, 0 },
20694 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20695 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838600 }
20696 },
20697/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
20698 {
20699 { 0, 0, 0, 0 },
20700 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20701 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58600 }
20702 },
20703/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
20704 {
20705 { 0, 0, 0, 0 },
20706 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20707 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a600 }
20708 },
20709/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
20710 {
20711 { 0, 0, 0, 0 },
20712 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20713 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858600 }
20714 },
20715/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
20716 {
20717 { 0, 0, 0, 0 },
20718 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20719 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c600 }
20720 },
20721/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
20722 {
20723 { 0, 0, 0, 0 },
20724 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20725 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e600 }
20726 },
20727/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
20728 {
20729 { 0, 0, 0, 0 },
20730 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20731 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c600 }
20732 },
20733/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
20734 {
20735 { 0, 0, 0, 0 },
20736 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20737 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c600 }
20738 },
20739/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
20740 {
20741 { 0, 0, 0, 0 },
20742 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20743 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e600 }
20744 },
20745/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
20746 {
20747 { 0, 0, 0, 0 },
20748 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20749 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c600 }
20750 },
20751/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
20752 {
20753 { 0, 0, 0, 0 },
20754 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
20755 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c600 }
20756 },
20757/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
20758 {
20759 { 0, 0, 0, 0 },
20760 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
20761 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e600 }
20762 },
20763/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
20764 {
20765 { 0, 0, 0, 0 },
20766 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
20767 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c600 }
20768 },
20769/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
20770 {
20771 { 0, 0, 0, 0 },
20772 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
20773 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78600 }
20774 },
20775/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
20776 {
20777 { 0, 0, 0, 0 },
20778 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
20779 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a600 }
20780 },
20781/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
20782 {
20783 { 0, 0, 0, 0 },
20784 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
20785 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878600 }
20786 },
20787/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
20788 {
20789 { 0, 0, 0, 0 },
20790 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20791 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980600 }
20792 },
20793/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
20794 {
20795 { 0, 0, 0, 0 },
20796 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20797 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982600 }
20798 },
20799/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
20800 {
20801 { 0, 0, 0, 0 },
20802 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20803 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983600 }
20804 },
20805/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
20806 {
20807 { 0, 0, 0, 0 },
20808 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
20809 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908600 }
20810 },
20811/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
20812 {
20813 { 0, 0, 0, 0 },
20814 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
20815 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a600 }
20816 },
20817/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
20818 {
20819 { 0, 0, 0, 0 },
20820 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
20821 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b600 }
20822 },
20823/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20824 {
20825 { 0, 0, 0, 0 },
20826 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20827 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900600 }
20828 },
20829/* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
20830 {
20831 { 0, 0, 0, 0 },
20832 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20833 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902600 }
20834 },
20835/* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
20836 {
20837 { 0, 0, 0, 0 },
20838 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20839 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903600 }
20840 },
20841/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
20842 {
20843 { 0, 0, 0, 0 },
20844 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20845 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920600 }
20846 },
20847/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
20848 {
20849 { 0, 0, 0, 0 },
20850 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20851 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922600 }
20852 },
20853/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
20854 {
20855 { 0, 0, 0, 0 },
20856 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20857 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923600 }
20858 },
20859/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
20860 {
20861 { 0, 0, 0, 0 },
20862 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20863 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940600 }
20864 },
20865/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20866 {
20867 { 0, 0, 0, 0 },
20868 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20869 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942600 }
20870 },
20871/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20872 {
20873 { 0, 0, 0, 0 },
20874 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20875 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943600 }
20876 },
20877/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
20878 {
20879 { 0, 0, 0, 0 },
20880 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20881 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960600 }
20882 },
20883/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20884 {
20885 { 0, 0, 0, 0 },
20886 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20887 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962600 }
20888 },
20889/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20890 {
20891 { 0, 0, 0, 0 },
20892 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20893 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963600 }
20894 },
20895/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
20896 {
20897 { 0, 0, 0, 0 },
20898 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20899 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928600 }
20900 },
20901/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
20902 {
20903 { 0, 0, 0, 0 },
20904 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20905 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a600 }
20906 },
20907/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
20908 {
20909 { 0, 0, 0, 0 },
20910 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20911 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b600 }
20912 },
20913/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
20914 {
20915 { 0, 0, 0, 0 },
20916 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20917 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948600 }
20918 },
20919/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
20920 {
20921 { 0, 0, 0, 0 },
20922 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20923 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a600 }
20924 },
20925/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
20926 {
20927 { 0, 0, 0, 0 },
20928 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20929 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b600 }
20930 },
20931/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
20932 {
20933 { 0, 0, 0, 0 },
20934 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20935 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c600 }
20936 },
20937/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
20938 {
20939 { 0, 0, 0, 0 },
20940 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20941 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e600 }
20942 },
20943/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
20944 {
20945 { 0, 0, 0, 0 },
20946 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20947 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f600 }
20948 },
20949/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
20950 {
20951 { 0, 0, 0, 0 },
20952 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20953 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c600 }
20954 },
20955/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
20956 {
20957 { 0, 0, 0, 0 },
20958 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20959 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e600 }
20960 },
20961/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
20962 {
20963 { 0, 0, 0, 0 },
20964 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20965 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f600 }
20966 },
20967/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
20968 {
20969 { 0, 0, 0, 0 },
20970 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
20971 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c600 }
20972 },
20973/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
20974 {
20975 { 0, 0, 0, 0 },
20976 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20977 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e600 }
20978 },
20979/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
20980 {
20981 { 0, 0, 0, 0 },
20982 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20983 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f600 }
20984 },
20985/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
20986 {
20987 { 0, 0, 0, 0 },
20988 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
20989 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968600 }
20990 },
20991/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
20992 {
20993 { 0, 0, 0, 0 },
20994 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
20995 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a600 }
20996 },
20997/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
20998 {
20999 { 0, 0, 0, 0 },
21000 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
21001 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b600 }
21002 },
21003/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
21004 {
21005 { 0, 0, 0, 0 },
21006 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21007 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80600 }
21008 },
21009/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
21010 {
21011 { 0, 0, 0, 0 },
21012 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21013 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82600 }
21014 },
21015/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
21016 {
21017 { 0, 0, 0, 0 },
21018 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21019 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83600 }
21020 },
21021/* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
21022 {
21023 { 0, 0, 0, 0 },
21024 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
21025 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83600 }
21026 },
21027/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
21028 {
21029 { 0, 0, 0, 0 },
21030 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21031 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08600 }
21032 },
21033/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
21034 {
21035 { 0, 0, 0, 0 },
21036 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21037 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a600 }
21038 },
21039/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
21040 {
21041 { 0, 0, 0, 0 },
21042 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21043 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b600 }
21044 },
21045/* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
21046 {
21047 { 0, 0, 0, 0 },
21048 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
21049 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b600 }
21050 },
21051/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21052 {
21053 { 0, 0, 0, 0 },
21054 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21055 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00600 }
21056 },
21057/* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
21058 {
21059 { 0, 0, 0, 0 },
21060 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21061 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02600 }
21062 },
21063/* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
21064 {
21065 { 0, 0, 0, 0 },
21066 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21067 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03600 }
21068 },
21069/* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
21070 {
21071 { 0, 0, 0, 0 },
21072 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21073 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03600 }
21074 },
21075/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
21076 {
21077 { 0, 0, 0, 0 },
21078 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21079 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20600 }
21080 },
21081/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
21082 {
21083 { 0, 0, 0, 0 },
21084 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21085 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22600 }
21086 },
21087/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
21088 {
21089 { 0, 0, 0, 0 },
21090 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21091 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23600 }
21092 },
21093/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
21094 {
21095 { 0, 0, 0, 0 },
21096 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21097 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23600 }
21098 },
21099/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
21100 {
21101 { 0, 0, 0, 0 },
21102 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21103 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40600 }
21104 },
21105/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
21106 {
21107 { 0, 0, 0, 0 },
21108 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21109 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42600 }
21110 },
21111/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
21112 {
21113 { 0, 0, 0, 0 },
21114 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21115 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43600 }
21116 },
21117/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
21118 {
21119 { 0, 0, 0, 0 },
21120 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21121 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43600 }
21122 },
21123/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
21124 {
21125 { 0, 0, 0, 0 },
21126 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21127 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60600 }
21128 },
21129/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
21130 {
21131 { 0, 0, 0, 0 },
21132 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21133 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62600 }
21134 },
21135/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
21136 {
21137 { 0, 0, 0, 0 },
21138 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21139 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63600 }
21140 },
21141/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
21142 {
21143 { 0, 0, 0, 0 },
21144 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21145 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63600 }
21146 },
21147/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
21148 {
21149 { 0, 0, 0, 0 },
21150 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21151 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28600 }
21152 },
21153/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
21154 {
21155 { 0, 0, 0, 0 },
21156 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21157 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a600 }
21158 },
21159/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
21160 {
21161 { 0, 0, 0, 0 },
21162 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21163 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b600 }
21164 },
21165/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
21166 {
21167 { 0, 0, 0, 0 },
21168 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21169 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b600 }
21170 },
21171/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
21172 {
21173 { 0, 0, 0, 0 },
21174 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21175 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48600 }
21176 },
21177/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
21178 {
21179 { 0, 0, 0, 0 },
21180 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21181 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a600 }
21182 },
21183/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
21184 {
21185 { 0, 0, 0, 0 },
21186 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21187 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b600 }
21188 },
21189/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
21190 {
21191 { 0, 0, 0, 0 },
21192 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21193 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b600 }
21194 },
21195/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
21196 {
21197 { 0, 0, 0, 0 },
21198 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21199 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c600 }
21200 },
21201/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
21202 {
21203 { 0, 0, 0, 0 },
21204 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21205 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e600 }
21206 },
21207/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
21208 {
21209 { 0, 0, 0, 0 },
21210 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21211 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f600 }
21212 },
21213/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
21214 {
21215 { 0, 0, 0, 0 },
21216 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21217 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f600 }
21218 },
21219/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
21220 {
21221 { 0, 0, 0, 0 },
21222 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21223 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c600 }
21224 },
21225/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
21226 {
21227 { 0, 0, 0, 0 },
21228 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21229 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e600 }
21230 },
21231/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
21232 {
21233 { 0, 0, 0, 0 },
21234 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21235 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f600 }
21236 },
21237/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
21238 {
21239 { 0, 0, 0, 0 },
21240 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21241 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f600 }
21242 },
21243/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
21244 {
21245 { 0, 0, 0, 0 },
21246 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
21247 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c600 }
21248 },
21249/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
21250 {
21251 { 0, 0, 0, 0 },
21252 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
21253 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e600 }
21254 },
21255/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
21256 {
21257 { 0, 0, 0, 0 },
21258 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
21259 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f600 }
21260 },
21261/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
21262 {
21263 { 0, 0, 0, 0 },
21264 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
21265 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f600 }
21266 },
21267/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
21268 {
21269 { 0, 0, 0, 0 },
21270 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
21271 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68600 }
21272 },
21273/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
21274 {
21275 { 0, 0, 0, 0 },
21276 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
21277 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a600 }
21278 },
21279/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
21280 {
21281 { 0, 0, 0, 0 },
21282 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
21283 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b600 }
21284 },
21285/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
21286 {
21287 { 0, 0, 0, 0 },
21288 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
21289 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b600 }
21290 },
21291/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
21292 {
21293 { 0, 0, 0, 0 },
21294 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21295 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80600 }
21296 },
21297/* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
21298 {
21299 { 0, 0, 0, 0 },
21300 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
21301 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82600 }
21302 },
21303/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
21304 {
21305 { 0, 0, 0, 0 },
21306 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21307 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08600 }
21308 },
21309/* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
21310 {
21311 { 0, 0, 0, 0 },
21312 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
21313 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a600 }
21314 },
21315/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21316 {
21317 { 0, 0, 0, 0 },
21318 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21319 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00600 }
21320 },
21321/* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
21322 {
21323 { 0, 0, 0, 0 },
21324 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21325 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02600 }
21326 },
21327/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
21328 {
21329 { 0, 0, 0, 0 },
21330 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21331 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20600 }
21332 },
21333/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
21334 {
21335 { 0, 0, 0, 0 },
21336 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21337 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22600 }
21338 },
21339/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
21340 {
21341 { 0, 0, 0, 0 },
21342 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21343 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40600 }
21344 },
21345/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
21346 {
21347 { 0, 0, 0, 0 },
21348 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21349 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42600 }
21350 },
21351/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
21352 {
21353 { 0, 0, 0, 0 },
21354 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21355 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60600 }
21356 },
21357/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
21358 {
21359 { 0, 0, 0, 0 },
21360 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21361 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62600 }
21362 },
21363/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
21364 {
21365 { 0, 0, 0, 0 },
21366 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
21367 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28600 }
21368 },
21369/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
21370 {
21371 { 0, 0, 0, 0 },
21372 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
21373 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a600 }
21374 },
21375/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
21376 {
21377 { 0, 0, 0, 0 },
21378 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
21379 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48600 }
21380 },
21381/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
21382 {
21383 { 0, 0, 0, 0 },
21384 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
21385 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a600 }
21386 },
21387/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
21388 {
21389 { 0, 0, 0, 0 },
21390 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
21391 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c600 }
21392 },
21393/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
21394 {
21395 { 0, 0, 0, 0 },
21396 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
21397 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e600 }
21398 },
21399/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
21400 {
21401 { 0, 0, 0, 0 },
21402 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
21403 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c600 }
21404 },
21405/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
21406 {
21407 { 0, 0, 0, 0 },
21408 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
21409 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e600 }
21410 },
21411/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
21412 {
21413 { 0, 0, 0, 0 },
21414 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
21415 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c600 }
21416 },
21417/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
21418 {
21419 { 0, 0, 0, 0 },
21420 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
21421 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e600 }
21422 },
21423/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
21424 {
21425 { 0, 0, 0, 0 },
21426 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
21427 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68600 }
21428 },
21429/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
21430 {
21431 { 0, 0, 0, 0 },
21432 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
21433 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a600 }
21434 },
21435/* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
21436 {
21437 { 0, 0, 0, 0 },
21438 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
21439 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c806 }
21440 },
21441/* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
21442 {
21443 { 0, 0, 0, 0 },
21444 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
21445 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18826 }
21446 },
21447/* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
21448 {
21449 { 0, 0, 0, 0 },
21450 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21451 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18806 }
21452 },
21453/* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
21454 {
21455 { 0, 0, 0, 0 },
21456 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
21457 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c086 }
21458 },
21459/* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
21460 {
21461 { 0, 0, 0, 0 },
21462 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
21463 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a6 }
21464 },
21465/* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
21466 {
21467 { 0, 0, 0, 0 },
21468 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21469 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18086 }
21470 },
21471/* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
21472 {
21473 { 0, 0, 0, 0 },
21474 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21475 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c006 }
21476 },
21477/* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
21478 {
21479 { 0, 0, 0, 0 },
21480 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21481 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18026 }
21482 },
21483/* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
21484 {
21485 { 0, 0, 0, 0 },
21486 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21487 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18006 }
21488 },
21489/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
21490 {
21491 { 0, 0, 0, 0 },
21492 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21493 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20600 }
21494 },
21495/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
21496 {
21497 { 0, 0, 0, 0 },
21498 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21499 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822600 }
21500 },
21501/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
21502 {
21503 { 0, 0, 0, 0 },
21504 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21505 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820600 }
21506 },
21507/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
21508 {
21509 { 0, 0, 0, 0 },
21510 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21511 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40600 }
21512 },
21513/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
21514 {
21515 { 0, 0, 0, 0 },
21516 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21517 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842600 }
21518 },
21519/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
21520 {
21521 { 0, 0, 0, 0 },
21522 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21523 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840600 }
21524 },
21525/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
21526 {
21527 { 0, 0, 0, 0 },
21528 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21529 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60600 }
21530 },
21531/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
21532 {
21533 { 0, 0, 0, 0 },
21534 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21535 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862600 }
21536 },
21537/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
21538 {
21539 { 0, 0, 0, 0 },
21540 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21541 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860600 }
21542 },
21543/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
21544 {
21545 { 0, 0, 0, 0 },
21546 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21547 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28600 }
21548 },
21549/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
21550 {
21551 { 0, 0, 0, 0 },
21552 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21553 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a600 }
21554 },
21555/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
21556 {
21557 { 0, 0, 0, 0 },
21558 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21559 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828600 }
21560 },
21561/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
21562 {
21563 { 0, 0, 0, 0 },
21564 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21565 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48600 }
21566 },
21567/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
21568 {
21569 { 0, 0, 0, 0 },
21570 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21571 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a600 }
21572 },
21573/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
21574 {
21575 { 0, 0, 0, 0 },
21576 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21577 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848600 }
21578 },
21579/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
21580 {
21581 { 0, 0, 0, 0 },
21582 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21583 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c600 }
21584 },
21585/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
21586 {
21587 { 0, 0, 0, 0 },
21588 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21589 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e600 }
21590 },
21591/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
21592 {
21593 { 0, 0, 0, 0 },
21594 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21595 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c600 }
21596 },
21597/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
21598 {
21599 { 0, 0, 0, 0 },
21600 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21601 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c600 }
21602 },
21603/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
21604 {
21605 { 0, 0, 0, 0 },
21606 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21607 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e600 }
21608 },
21609/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
21610 {
21611 { 0, 0, 0, 0 },
21612 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21613 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c600 }
21614 },
21615/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
21616 {
21617 { 0, 0, 0, 0 },
21618 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
21619 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c600 }
21620 },
21621/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
21622 {
21623 { 0, 0, 0, 0 },
21624 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
21625 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e600 }
21626 },
21627/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
21628 {
21629 { 0, 0, 0, 0 },
21630 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
21631 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c600 }
21632 },
21633/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
21634 {
21635 { 0, 0, 0, 0 },
21636 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
21637 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68600 }
21638 },
21639/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
21640 {
21641 { 0, 0, 0, 0 },
21642 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
21643 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a600 }
21644 },
21645/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
21646 {
21647 { 0, 0, 0, 0 },
21648 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
21649 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868600 }
21650 },
21651/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21652 {
21653 { 0, 0, 0, 0 },
21654 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
21655 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb98000 }
21656 },
21657/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
21658 {
21659 { 0, 0, 0, 0 },
21660 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
21661 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9a000 }
21662 },
21663/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
21664 {
21665 { 0, 0, 0, 0 },
21666 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
21667 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb9b000 }
21668 },
21669/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21670 {
21671 { 0, 0, 0, 0 },
21672 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
21673 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb98400 }
21674 },
21675/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
21676 {
21677 { 0, 0, 0, 0 },
21678 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
21679 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb9a400 }
21680 },
21681/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
21682 {
21683 { 0, 0, 0, 0 },
21684 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
21685 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb9b400 }
21686 },
21687/* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21688 {
21689 { 0, 0, 0, 0 },
21690 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
21691 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb98600 }
21692 },
21693/* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
21694 {
21695 { 0, 0, 0, 0 },
21696 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
21697 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb9a600 }
21698 },
21699/* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
21700 {
21701 { 0, 0, 0, 0 },
21702 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
21703 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb9b600 }
21704 },
21705/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21706 {
21707 { 0, 0, 0, 0 },
21708 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21709 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb9880000 }
21710 },
21711/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21712 {
21713 { 0, 0, 0, 0 },
21714 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21715 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9a80000 }
21716 },
21717/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21718 {
21719 { 0, 0, 0, 0 },
21720 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21721 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9b80000 }
21722 },
21723/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21724 {
21725 { 0, 0, 0, 0 },
21726 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21727 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb98c0000 }
21728 },
21729/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21730 {
21731 { 0, 0, 0, 0 },
21732 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21733 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9ac0000 }
21734 },
21735/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21736 {
21737 { 0, 0, 0, 0 },
21738 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21739 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9bc0000 }
21740 },
21741/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21742 {
21743 { 0, 0, 0, 0 },
21744 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21745 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb98a0000 }
21746 },
21747/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21748 {
21749 { 0, 0, 0, 0 },
21750 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21751 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9aa0000 }
21752 },
21753/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21754 {
21755 { 0, 0, 0, 0 },
21756 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21757 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9ba0000 }
21758 },
21759/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21760 {
21761 { 0, 0, 0, 0 },
21762 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21763 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb98e0000 }
21764 },
21765/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21766 {
21767 { 0, 0, 0, 0 },
21768 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21769 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9ae0000 }
21770 },
21771/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21772 {
21773 { 0, 0, 0, 0 },
21774 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21775 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9be0000 }
21776 },
21777/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21778 {
21779 { 0, 0, 0, 0 },
21780 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21781 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb98b0000 }
21782 },
21783/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21784 {
21785 { 0, 0, 0, 0 },
21786 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21787 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9ab0000 }
21788 },
21789/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21790 {
21791 { 0, 0, 0, 0 },
21792 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21793 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9bb0000 }
21794 },
21795/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21796 {
21797 { 0, 0, 0, 0 },
21798 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
21799 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb98f0000 }
21800 },
21801/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21802 {
21803 { 0, 0, 0, 0 },
21804 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
21805 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb9af0000 }
21806 },
21807/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21808 {
21809 { 0, 0, 0, 0 },
21810 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
21811 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb9bf0000 }
21812 },
21813/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
21814 {
21815 { 0, 0, 0, 0 },
21816 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
21817 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb9c00000 }
21818 },
21819/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
21820 {
21821 { 0, 0, 0, 0 },
21822 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
21823 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9e00000 }
21824 },
21825/* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
21826 {
21827 { 0, 0, 0, 0 },
21828 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
21829 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb9f00000 }
21830 },
21831/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
21832 {
21833 { 0, 0, 0, 0 },
21834 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
21835 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb9c40000 }
21836 },
21837/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
21838 {
21839 { 0, 0, 0, 0 },
21840 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
21841 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb9e40000 }
21842 },
21843/* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
21844 {
21845 { 0, 0, 0, 0 },
21846 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
21847 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb9f40000 }
21848 },
21849/* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21850 {
21851 { 0, 0, 0, 0 },
21852 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
21853 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb9c60000 }
21854 },
21855/* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
21856 {
21857 { 0, 0, 0, 0 },
21858 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
21859 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb9e60000 }
21860 },
21861/* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
21862 {
21863 { 0, 0, 0, 0 },
21864 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
21865 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb9f60000 }
21866 },
21867/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21868 {
21869 { 0, 0, 0, 0 },
21870 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
21871 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb9c80000 }
21872 },
21873/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21874 {
21875 { 0, 0, 0, 0 },
21876 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
21877 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb9e80000 }
21878 },
21879/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21880 {
21881 { 0, 0, 0, 0 },
21882 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
21883 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb9f80000 }
21884 },
21885/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21886 {
21887 { 0, 0, 0, 0 },
21888 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
21889 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb9cc0000 }
21890 },
21891/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21892 {
21893 { 0, 0, 0, 0 },
21894 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
21895 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb9ec0000 }
21896 },
21897/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21898 {
21899 { 0, 0, 0, 0 },
21900 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
21901 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb9fc0000 }
21902 },
21903/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21904 {
21905 { 0, 0, 0, 0 },
21906 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21907 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ca0000 }
21908 },
21909/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21910 {
21911 { 0, 0, 0, 0 },
21912 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21913 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ea0000 }
21914 },
21915/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21916 {
21917 { 0, 0, 0, 0 },
21918 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21919 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb9fa0000 }
21920 },
21921/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21922 {
21923 { 0, 0, 0, 0 },
21924 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21925 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ce0000 }
21926 },
21927/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21928 {
21929 { 0, 0, 0, 0 },
21930 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21931 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ee0000 }
21932 },
21933/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21934 {
21935 { 0, 0, 0, 0 },
21936 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21937 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb9fe0000 }
21938 },
21939/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21940 {
21941 { 0, 0, 0, 0 },
21942 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21943 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9cb0000 }
21944 },
21945/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21946 {
21947 { 0, 0, 0, 0 },
21948 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21949 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9eb0000 }
21950 },
21951/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21952 {
21953 { 0, 0, 0, 0 },
21954 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21955 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb9fb0000 }
21956 },
21957/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21958 {
21959 { 0, 0, 0, 0 },
21960 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
21961 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb9cf0000 }
21962 },
21963/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21964 {
21965 { 0, 0, 0, 0 },
21966 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
21967 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb9ef0000 }
21968 },
21969/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
21970 {
21971 { 0, 0, 0, 0 },
21972 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
21973 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb9ff0000 }
21974 },
21975/* sbb.w${X} $Src16RnHI,$Dst16RnHI */
21976 {
21977 { 0, 0, 0, 0 },
21978 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
21979 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb900 }
21980 },
21981/* sbb.w${X} $Src16AnHI,$Dst16RnHI */
21982 {
21983 { 0, 0, 0, 0 },
21984 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
21985 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb940 }
21986 },
21987/* sbb.w${X} [$Src16An],$Dst16RnHI */
21988 {
21989 { 0, 0, 0, 0 },
21990 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
21991 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb960 }
21992 },
21993/* sbb.w${X} $Src16RnHI,$Dst16AnHI */
21994 {
21995 { 0, 0, 0, 0 },
21996 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
21997 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb904 }
21998 },
21999/* sbb.w${X} $Src16AnHI,$Dst16AnHI */
22000 {
22001 { 0, 0, 0, 0 },
22002 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
22003 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb944 }
22004 },
22005/* sbb.w${X} [$Src16An],$Dst16AnHI */
22006 {
22007 { 0, 0, 0, 0 },
22008 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
22009 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb964 }
22010 },
22011/* sbb.w${X} $Src16RnHI,[$Dst16An] */
22012 {
22013 { 0, 0, 0, 0 },
22014 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
22015 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb906 }
22016 },
22017/* sbb.w${X} $Src16AnHI,[$Dst16An] */
22018 {
22019 { 0, 0, 0, 0 },
22020 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
22021 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb946 }
22022 },
22023/* sbb.w${X} [$Src16An],[$Dst16An] */
22024 {
22025 { 0, 0, 0, 0 },
22026 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22027 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb966 }
22028 },
22029/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
22030 {
22031 { 0, 0, 0, 0 },
22032 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22033 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb90800 }
22034 },
22035/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
22036 {
22037 { 0, 0, 0, 0 },
22038 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22039 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb94800 }
22040 },
22041/* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
22042 {
22043 { 0, 0, 0, 0 },
22044 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22045 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb96800 }
22046 },
22047/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
22048 {
22049 { 0, 0, 0, 0 },
22050 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22051 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb90c0000 }
22052 },
22053/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
22054 {
22055 { 0, 0, 0, 0 },
22056 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22057 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb94c0000 }
22058 },
22059/* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
22060 {
22061 { 0, 0, 0, 0 },
22062 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22063 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb96c0000 }
22064 },
22065/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
22066 {
22067 { 0, 0, 0, 0 },
22068 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22069 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb90a00 }
22070 },
22071/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
22072 {
22073 { 0, 0, 0, 0 },
22074 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22075 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb94a00 }
22076 },
22077/* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
22078 {
22079 { 0, 0, 0, 0 },
22080 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22081 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb96a00 }
22082 },
22083/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
22084 {
22085 { 0, 0, 0, 0 },
22086 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22087 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb90e0000 }
22088 },
22089/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
22090 {
22091 { 0, 0, 0, 0 },
22092 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22093 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb94e0000 }
22094 },
22095/* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
22096 {
22097 { 0, 0, 0, 0 },
22098 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22099 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb96e0000 }
22100 },
22101/* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
22102 {
22103 { 0, 0, 0, 0 },
22104 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22105 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb90b00 }
22106 },
22107/* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
22108 {
22109 { 0, 0, 0, 0 },
22110 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22111 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb94b00 }
22112 },
22113/* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
22114 {
22115 { 0, 0, 0, 0 },
22116 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22117 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb96b00 }
22118 },
22119/* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
22120 {
22121 { 0, 0, 0, 0 },
22122 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
22123 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb90f0000 }
22124 },
22125/* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
22126 {
22127 { 0, 0, 0, 0 },
22128 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
22129 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb94f0000 }
22130 },
22131/* sbb.w${X} [$Src16An],${Dsp-16-u16} */
22132 {
22133 { 0, 0, 0, 0 },
22134 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
22135 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb96f0000 }
22136 },
22137/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
22138 {
22139 { 0, 0, 0, 0 },
22140 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22141 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb88000 }
22142 },
22143/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
22144 {
22145 { 0, 0, 0, 0 },
22146 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
22147 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8a000 }
22148 },
22149/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
22150 {
22151 { 0, 0, 0, 0 },
22152 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
22153 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb8b000 }
22154 },
22155/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
22156 {
22157 { 0, 0, 0, 0 },
22158 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22159 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb88400 }
22160 },
22161/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
22162 {
22163 { 0, 0, 0, 0 },
22164 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
22165 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb8a400 }
22166 },
22167/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
22168 {
22169 { 0, 0, 0, 0 },
22170 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
22171 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb8b400 }
22172 },
22173/* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
22174 {
22175 { 0, 0, 0, 0 },
22176 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22177 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb88600 }
22178 },
22179/* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
22180 {
22181 { 0, 0, 0, 0 },
22182 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22183 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb8a600 }
22184 },
22185/* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
22186 {
22187 { 0, 0, 0, 0 },
22188 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22189 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb8b600 }
22190 },
22191/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
22192 {
22193 { 0, 0, 0, 0 },
22194 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22195 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb8880000 }
22196 },
22197/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
22198 {
22199 { 0, 0, 0, 0 },
22200 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22201 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8a80000 }
22202 },
22203/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
22204 {
22205 { 0, 0, 0, 0 },
22206 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22207 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8b80000 }
22208 },
22209/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
22210 {
22211 { 0, 0, 0, 0 },
22212 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22213 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb88c0000 }
22214 },
22215/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
22216 {
22217 { 0, 0, 0, 0 },
22218 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22219 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8ac0000 }
22220 },
22221/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
22222 {
22223 { 0, 0, 0, 0 },
22224 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22225 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8bc0000 }
22226 },
22227/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
22228 {
22229 { 0, 0, 0, 0 },
22230 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22231 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb88a0000 }
22232 },
22233/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22234 {
22235 { 0, 0, 0, 0 },
22236 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22237 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8aa0000 }
22238 },
22239/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22240 {
22241 { 0, 0, 0, 0 },
22242 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22243 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8ba0000 }
22244 },
22245/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
22246 {
22247 { 0, 0, 0, 0 },
22248 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22249 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb88e0000 }
22250 },
22251/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22252 {
22253 { 0, 0, 0, 0 },
22254 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22255 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8ae0000 }
22256 },
22257/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22258 {
22259 { 0, 0, 0, 0 },
22260 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22261 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8be0000 }
22262 },
22263/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
22264 {
22265 { 0, 0, 0, 0 },
22266 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22267 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb88b0000 }
22268 },
22269/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22270 {
22271 { 0, 0, 0, 0 },
22272 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22273 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8ab0000 }
22274 },
22275/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22276 {
22277 { 0, 0, 0, 0 },
22278 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22279 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8bb0000 }
22280 },
22281/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
22282 {
22283 { 0, 0, 0, 0 },
22284 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
22285 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb88f0000 }
22286 },
22287/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22288 {
22289 { 0, 0, 0, 0 },
22290 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
22291 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb8af0000 }
22292 },
22293/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22294 {
22295 { 0, 0, 0, 0 },
22296 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
22297 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb8bf0000 }
22298 },
22299/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
22300 {
22301 { 0, 0, 0, 0 },
22302 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22303 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb8c00000 }
22304 },
22305/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
22306 {
22307 { 0, 0, 0, 0 },
22308 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
22309 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8e00000 }
22310 },
22311/* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
22312 {
22313 { 0, 0, 0, 0 },
22314 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
22315 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb8f00000 }
22316 },
22317/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
22318 {
22319 { 0, 0, 0, 0 },
22320 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22321 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb8c40000 }
22322 },
22323/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
22324 {
22325 { 0, 0, 0, 0 },
22326 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
22327 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb8e40000 }
22328 },
22329/* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
22330 {
22331 { 0, 0, 0, 0 },
22332 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
22333 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb8f40000 }
22334 },
22335/* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
22336 {
22337 { 0, 0, 0, 0 },
22338 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22339 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb8c60000 }
22340 },
22341/* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
22342 {
22343 { 0, 0, 0, 0 },
22344 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22345 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb8e60000 }
22346 },
22347/* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
22348 {
22349 { 0, 0, 0, 0 },
22350 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
22351 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb8f60000 }
22352 },
22353/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
22354 {
22355 { 0, 0, 0, 0 },
22356 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22357 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb8c80000 }
22358 },
22359/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
22360 {
22361 { 0, 0, 0, 0 },
22362 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22363 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb8e80000 }
22364 },
22365/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
22366 {
22367 { 0, 0, 0, 0 },
22368 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22369 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb8f80000 }
22370 },
22371/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
22372 {
22373 { 0, 0, 0, 0 },
22374 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22375 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb8cc0000 }
22376 },
22377/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
22378 {
22379 { 0, 0, 0, 0 },
22380 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22381 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb8ec0000 }
22382 },
22383/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
22384 {
22385 { 0, 0, 0, 0 },
22386 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22387 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb8fc0000 }
22388 },
22389/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
22390 {
22391 { 0, 0, 0, 0 },
22392 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22393 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ca0000 }
22394 },
22395/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22396 {
22397 { 0, 0, 0, 0 },
22398 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22399 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ea0000 }
22400 },
22401/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22402 {
22403 { 0, 0, 0, 0 },
22404 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22405 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb8fa0000 }
22406 },
22407/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
22408 {
22409 { 0, 0, 0, 0 },
22410 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22411 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ce0000 }
22412 },
22413/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22414 {
22415 { 0, 0, 0, 0 },
22416 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22417 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ee0000 }
22418 },
22419/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22420 {
22421 { 0, 0, 0, 0 },
22422 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22423 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb8fe0000 }
22424 },
22425/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
22426 {
22427 { 0, 0, 0, 0 },
22428 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22429 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8cb0000 }
22430 },
22431/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22432 {
22433 { 0, 0, 0, 0 },
22434 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22435 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8eb0000 }
22436 },
22437/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22438 {
22439 { 0, 0, 0, 0 },
22440 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22441 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb8fb0000 }
22442 },
22443/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
22444 {
22445 { 0, 0, 0, 0 },
22446 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
22447 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb8cf0000 }
22448 },
22449/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22450 {
22451 { 0, 0, 0, 0 },
22452 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
22453 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb8ef0000 }
22454 },
22455/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
22456 {
22457 { 0, 0, 0, 0 },
22458 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
22459 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb8ff0000 }
22460 },
22461/* sbb.b${X} $Src16RnQI,$Dst16RnQI */
22462 {
22463 { 0, 0, 0, 0 },
22464 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
22465 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb800 }
22466 },
22467/* sbb.b${X} $Src16AnQI,$Dst16RnQI */
22468 {
22469 { 0, 0, 0, 0 },
22470 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
22471 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb840 }
22472 },
22473/* sbb.b${X} [$Src16An],$Dst16RnQI */
22474 {
22475 { 0, 0, 0, 0 },
22476 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22477 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb860 }
22478 },
22479/* sbb.b${X} $Src16RnQI,$Dst16AnQI */
22480 {
22481 { 0, 0, 0, 0 },
22482 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
22483 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb804 }
22484 },
22485/* sbb.b${X} $Src16AnQI,$Dst16AnQI */
22486 {
22487 { 0, 0, 0, 0 },
22488 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
22489 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb844 }
22490 },
22491/* sbb.b${X} [$Src16An],$Dst16AnQI */
22492 {
22493 { 0, 0, 0, 0 },
22494 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22495 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb864 }
22496 },
22497/* sbb.b${X} $Src16RnQI,[$Dst16An] */
22498 {
22499 { 0, 0, 0, 0 },
22500 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
22501 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb806 }
22502 },
22503/* sbb.b${X} $Src16AnQI,[$Dst16An] */
22504 {
22505 { 0, 0, 0, 0 },
22506 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
22507 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb846 }
22508 },
22509/* sbb.b${X} [$Src16An],[$Dst16An] */
22510 {
22511 { 0, 0, 0, 0 },
22512 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22513 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb866 }
22514 },
22515/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
22516 {
22517 { 0, 0, 0, 0 },
22518 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22519 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb80800 }
22520 },
22521/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
22522 {
22523 { 0, 0, 0, 0 },
22524 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22525 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb84800 }
22526 },
22527/* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
22528 {
22529 { 0, 0, 0, 0 },
22530 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22531 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb86800 }
22532 },
22533/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
22534 {
22535 { 0, 0, 0, 0 },
22536 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22537 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb80c0000 }
22538 },
22539/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
22540 {
22541 { 0, 0, 0, 0 },
22542 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22543 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb84c0000 }
22544 },
22545/* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
22546 {
22547 { 0, 0, 0, 0 },
22548 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22549 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb86c0000 }
22550 },
22551/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
22552 {
22553 { 0, 0, 0, 0 },
22554 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22555 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb80a00 }
22556 },
22557/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
22558 {
22559 { 0, 0, 0, 0 },
22560 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22561 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb84a00 }
22562 },
22563/* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
22564 {
22565 { 0, 0, 0, 0 },
22566 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22567 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb86a00 }
22568 },
22569/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
22570 {
22571 { 0, 0, 0, 0 },
22572 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22573 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb80e0000 }
22574 },
22575/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
22576 {
22577 { 0, 0, 0, 0 },
22578 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22579 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb84e0000 }
22580 },
22581/* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
22582 {
22583 { 0, 0, 0, 0 },
22584 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22585 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb86e0000 }
22586 },
22587/* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
22588 {
22589 { 0, 0, 0, 0 },
22590 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22591 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb80b00 }
22592 },
22593/* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
22594 {
22595 { 0, 0, 0, 0 },
22596 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22597 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb84b00 }
22598 },
22599/* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
22600 {
22601 { 0, 0, 0, 0 },
22602 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22603 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb86b00 }
22604 },
22605/* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
22606 {
22607 { 0, 0, 0, 0 },
22608 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
22609 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb80f0000 }
22610 },
22611/* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
22612 {
22613 { 0, 0, 0, 0 },
22614 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
22615 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb84f0000 }
22616 },
22617/* sbb.b${X} [$Src16An],${Dsp-16-u16} */
22618 {
22619 { 0, 0, 0, 0 },
22620 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
22621 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb86f0000 }
22622 },
22623/* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
22624 {
22625 { 0, 0, 0, 0 },
22626 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
22627 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1992e00 }
22628 },
22629/* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
22630 {
22631 { 0, 0, 0, 0 },
22632 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
22633 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x191ae00 }
22634 },
22635/* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
22636 {
22637 { 0, 0, 0, 0 },
22638 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
22639 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1912e00 }
22640 },
22641/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
22642 {
22643 { 0, 0, 0, 0 },
22644 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
22645 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1932e00 }
22646 },
22647/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
22648 {
22649 { 0, 0, 0, 0 },
22650 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22651 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x193ae00 }
22652 },
22653/* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
22654 {
22655 { 0, 0, 0, 0 },
22656 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22657 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ee00 }
22658 },
22659/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
22660 {
22661 { 0, 0, 0, 0 },
22662 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
22663 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1952e00 }
22664 },
22665/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
22666 {
22667 { 0, 0, 0, 0 },
22668 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22669 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x195ae00 }
22670 },
22671/* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
22672 {
22673 { 0, 0, 0, 0 },
22674 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
22675 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ee00 }
22676 },
22677/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
22678 {
22679 { 0, 0, 0, 0 },
22680 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
22681 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ee00 }
22682 },
22683/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
22684 {
22685 { 0, 0, 0, 0 },
22686 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
22687 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1972e00 }
22688 },
22689/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
22690 {
22691 { 0, 0, 0, 0 },
22692 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
22693 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x197ae00 }
22694 },
22695/* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
22696 {
22697 { 0, 0, 0, 0 },
22698 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
22699 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1982e00 }
22700 },
22701/* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
22702 {
22703 { 0, 0, 0, 0 },
22704 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
22705 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x190ae00 }
22706 },
22707/* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
22708 {
22709 { 0, 0, 0, 0 },
22710 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
22711 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1902e00 }
22712 },
22713/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
22714 {
22715 { 0, 0, 0, 0 },
22716 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
22717 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1922e00 }
22718 },
22719/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
22720 {
22721 { 0, 0, 0, 0 },
22722 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22723 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x192ae00 }
22724 },
22725/* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
22726 {
22727 { 0, 0, 0, 0 },
22728 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22729 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ee00 }
22730 },
22731/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
22732 {
22733 { 0, 0, 0, 0 },
22734 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
22735 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1942e00 }
22736 },
22737/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
22738 {
22739 { 0, 0, 0, 0 },
22740 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22741 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x194ae00 }
22742 },
22743/* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
22744 {
22745 { 0, 0, 0, 0 },
22746 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
22747 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ee00 }
22748 },
22749/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
22750 {
22751 { 0, 0, 0, 0 },
22752 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
22753 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ee00 }
22754 },
22755/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
22756 {
22757 { 0, 0, 0, 0 },
22758 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
22759 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1962e00 }
22760 },
22761/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
22762 {
22763 { 0, 0, 0, 0 },
22764 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
22765 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x196ae00 }
22766 },
22767/* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
22768 {
22769 { 0, 0, 0, 0 },
22770 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
22771 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77700000 }
22772 },
22773/* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
22774 {
22775 { 0, 0, 0, 0 },
22776 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
22777 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77740000 }
22778 },
22779/* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
22780 {
22781 { 0, 0, 0, 0 },
22782 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
22783 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77760000 }
22784 },
22785/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22786 {
22787 { 0, 0, 0, 0 },
22788 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22789 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77780000 }
22790 },
22791/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22792 {
22793 { 0, 0, 0, 0 },
22794 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22795 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x777a0000 }
22796 },
22797/* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22798 {
22799 { 0, 0, 0, 0 },
22800 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22801 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x777b0000 }
22802 },
22803/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22804 {
22805 { 0, 0, 0, 0 },
22806 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22807 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x777c0000 }
22808 },
22809/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22810 {
22811 { 0, 0, 0, 0 },
22812 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22813 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x777e0000 }
22814 },
22815/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
22816 {
22817 { 0, 0, 0, 0 },
22818 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
22819 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x777f0000 }
22820 },
22821/* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
22822 {
22823 { 0, 0, 0, 0 },
22824 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
22825 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x767000 }
22826 },
22827/* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
22828 {
22829 { 0, 0, 0, 0 },
22830 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
22831 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x767400 }
22832 },
22833/* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
22834 {
22835 { 0, 0, 0, 0 },
22836 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
22837 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x767600 }
22838 },
22839/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
22840 {
22841 { 0, 0, 0, 0 },
22842 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22843 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76780000 }
22844 },
22845/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22846 {
22847 { 0, 0, 0, 0 },
22848 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22849 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x767a0000 }
22850 },
22851/* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22852 {
22853 { 0, 0, 0, 0 },
22854 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22855 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x767b0000 }
22856 },
22857/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
22858 {
22859 { 0, 0, 0, 0 },
22860 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22861 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x767c0000 }
22862 },
22863/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22864 {
22865 { 0, 0, 0, 0 },
22866 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22867 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x767e0000 }
22868 },
22869/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
22870 {
22871 { 0, 0, 0, 0 },
22872 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
22873 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x767f0000 }
22874 },
a1a280bb 22875/* rot.w r1h,$Dst32RnUnprefixedHI */
49f58d10
JB		 22876 {
22877 { 0, 0, 0, 0 },
a1a280bb
DD		 22878 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
22879 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93f }
49f58d10 22880 },
a1a280bb 22881/* rot.w r1h,$Dst32AnUnprefixedHI */
49f58d10
JB		 22882 {
22883 { 0, 0, 0, 0 },
a1a280bb
DD		 22884 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
22885 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1bf }
49f58d10
JB		 22886 },
22887/* rot.w r1h,[$Dst32AnUnprefixed] */
22888 {
22889 { 0, 0, 0, 0 },
22890 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22891 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13f }
49f58d10
JB		 22892 },
22893/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22894 {
22895 { 0, 0, 0, 0 },
22896 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22897 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33f00 }
49f58d10
JB		 22898 },
22899/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22900 {
22901 { 0, 0, 0, 0 },
22902 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22903 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53f0000 }
49f58d10
JB		 22904 },
22905/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22906 {
22907 { 0, 0, 0, 0 },
22908 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22909 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73f0000 }
49f58d10
JB		 22910 },
22911/* rot.w r1h,${Dsp-16-u8}[sb] */
22912 {
22913 { 0, 0, 0, 0 },
22914 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 22915 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3bf00 }
49f58d10
JB		 22916 },
22917/* rot.w r1h,${Dsp-16-u16}[sb] */
22918 {
22919 { 0, 0, 0, 0 },
22920 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 22921 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5bf0000 }
49f58d10
JB		 22922 },
22923/* rot.w r1h,${Dsp-16-s8}[fb] */
22924 {
22925 { 0, 0, 0, 0 },
22926 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 22927 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ff00 }
49f58d10
JB		 22928 },
22929/* rot.w r1h,${Dsp-16-s16}[fb] */
22930 {
22931 { 0, 0, 0, 0 },
22932 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 22933 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ff0000 }
49f58d10
JB		 22934 },
22935/* rot.w r1h,${Dsp-16-u16} */
22936 {
22937 { 0, 0, 0, 0 },
22938 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 22939 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ff0000 }
49f58d10
JB		 22940 },
22941/* rot.w r1h,${Dsp-16-u24} */
22942 {
22943 { 0, 0, 0, 0 },
22944 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
a1a280bb 22945 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7bf0000 }
49f58d10 22946 },
a1a280bb 22947/* rot.b r1h,$Dst32RnUnprefixedQI */
49f58d10
JB		 22948 {
22949 { 0, 0, 0, 0 },
a1a280bb
DD		 22950 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
22951 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83f }
49f58d10 22952 },
a1a280bb 22953/* rot.b r1h,$Dst32AnUnprefixedQI */
49f58d10
JB		 22954 {
22955 { 0, 0, 0, 0 },
a1a280bb
DD		 22956 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
22957 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0bf }
49f58d10
JB		 22958 },
22959/* rot.b r1h,[$Dst32AnUnprefixed] */
22960 {
22961 { 0, 0, 0, 0 },
22962 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22963 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03f }
49f58d10
JB		 22964 },
22965/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22966 {
22967 { 0, 0, 0, 0 },
22968 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22969 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23f00 }
49f58d10
JB		 22970 },
22971/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22972 {
22973 { 0, 0, 0, 0 },
22974 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22975 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43f0000 }
49f58d10
JB		 22976 },
22977/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22978 {
22979 { 0, 0, 0, 0 },
22980 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 22981 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63f0000 }
49f58d10
JB		 22982 },
22983/* rot.b r1h,${Dsp-16-u8}[sb] */
22984 {
22985 { 0, 0, 0, 0 },
22986 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 22987 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2bf00 }
49f58d10
JB		 22988 },
22989/* rot.b r1h,${Dsp-16-u16}[sb] */
22990 {
22991 { 0, 0, 0, 0 },
22992 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 22993 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4bf0000 }
49f58d10
JB		 22994 },
22995/* rot.b r1h,${Dsp-16-s8}[fb] */
22996 {
22997 { 0, 0, 0, 0 },
22998 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 22999 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ff00 }
49f58d10
JB		 23000 },
23001/* rot.b r1h,${Dsp-16-s16}[fb] */
23002 {
23003 { 0, 0, 0, 0 },
23004 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 23005 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ff0000 }
49f58d10
JB		 23006 },
23007/* rot.b r1h,${Dsp-16-u16} */
23008 {
23009 { 0, 0, 0, 0 },
23010 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 23011 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ff0000 }
49f58d10
JB		 23012 },
23013/* rot.b r1h,${Dsp-16-u24} */
23014 {
23015 { 0, 0, 0, 0 },
23016 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
a1a280bb 23017 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6bf0000 }
49f58d10
JB		 23018 },
23019/* rot.w r1h,$Dst16RnHI */
23020 {
23021 { 0, 0, 0, 0 },
23022 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
23023 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7560 }
23024 },
23025/* rot.w r1h,$Dst16AnHI */
23026 {
23027 { 0, 0, 0, 0 },
23028 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
23029 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7564 }
23030 },
23031/* rot.w r1h,[$Dst16An] */
23032 {
23033 { 0, 0, 0, 0 },
23034 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
23035 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7566 }
23036 },
23037/* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
23038 {
23039 { 0, 0, 0, 0 },
23040 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23041 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x756800 }
23042 },
23043/* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
23044 {
23045 { 0, 0, 0, 0 },
23046 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23047 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x756c0000 }
23048 },
23049/* rot.w r1h,${Dsp-16-u8}[sb] */
23050 {
23051 { 0, 0, 0, 0 },
23052 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23053 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x756a00 }
23054 },
23055/* rot.w r1h,${Dsp-16-u16}[sb] */
23056 {
23057 { 0, 0, 0, 0 },
23058 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23059 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x756e0000 }
23060 },
23061/* rot.w r1h,${Dsp-16-s8}[fb] */
23062 {
23063 { 0, 0, 0, 0 },
23064 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23065 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x756b00 }
23066 },
23067/* rot.w r1h,${Dsp-16-u16} */
23068 {
23069 { 0, 0, 0, 0 },
23070 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
23071 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x756f0000 }
23072 },
a1a280bb 23073/* rot.b r1h,$Dst16RnQI */
49f58d10
JB		 23074 {
23075 { 0, 0, 0, 0 },
a1a280bb
DD		 23076 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
23077 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7460 }
49f58d10 23078 },
a1a280bb 23079/* rot.b r1h,$Dst16AnQI */
49f58d10
JB		 23080 {
23081 { 0, 0, 0, 0 },
a1a280bb
DD		 23082 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
23083 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7464 }
49f58d10
JB		 23084 },
23085/* rot.b r1h,[$Dst16An] */
23086 {
23087 { 0, 0, 0, 0 },
23088 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 23089 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7466 }
49f58d10
JB		 23090 },
23091/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
23092 {
23093 { 0, 0, 0, 0 },
23094 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 23095 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x746800 }
49f58d10
JB		 23096 },
23097/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
23098 {
23099 { 0, 0, 0, 0 },
23100 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 23101 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x746c0000 }
49f58d10
JB		 23102 },
23103/* rot.b r1h,${Dsp-16-u8}[sb] */
23104 {
23105 { 0, 0, 0, 0 },
23106 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 23107 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x746a00 }
49f58d10
JB		 23108 },
23109/* rot.b r1h,${Dsp-16-u16}[sb] */
23110 {
23111 { 0, 0, 0, 0 },
23112 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 23113 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x746e0000 }
49f58d10
JB		 23114 },
23115/* rot.b r1h,${Dsp-16-s8}[fb] */
23116 {
23117 { 0, 0, 0, 0 },
23118 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 23119 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x746b00 }
49f58d10
JB		 23120 },
23121/* rot.b r1h,${Dsp-16-u16} */
23122 {
23123 { 0, 0, 0, 0 },
23124 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 23125 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x746f0000 }
49f58d10
JB		 23126 },
23127/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
23128 {
23129 { 0, 0, 0, 0 },
23130 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
23131 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe920 }
23132 },
23133/* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
23134 {
23135 { 0, 0, 0, 0 },
23136 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
23137 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1a0 }
23138 },
23139/* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
23140 {
23141 { 0, 0, 0, 0 },
23142 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23143 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe120 }
23144 },
23145/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
23146 {
23147 { 0, 0, 0, 0 },
23148 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23149 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe32000 }
23150 },
23151/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
23152 {
23153 { 0, 0, 0, 0 },
23154 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23155 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5200000 }
23156 },
23157/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
23158 {
23159 { 0, 0, 0, 0 },
23160 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23161 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7200000 }
23162 },
23163/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
23164 {
23165 { 0, 0, 0, 0 },
23166 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23167 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3a000 }
23168 },
23169/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
23170 {
23171 { 0, 0, 0, 0 },
23172 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23173 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5a00000 }
23174 },
23175/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
23176 {
23177 { 0, 0, 0, 0 },
23178 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23179 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3e000 }
23180 },
23181/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
23182 {
23183 { 0, 0, 0, 0 },
23184 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23185 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5e00000 }
23186 },
23187/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
23188 {
23189 { 0, 0, 0, 0 },
23190 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
23191 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7e00000 }
23192 },
23193/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
23194 {
23195 { 0, 0, 0, 0 },
23196 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
23197 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7a00000 }
23198 },
23199/* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
23200 {
23201 { 0, 0, 0, 0 },
23202 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
23203 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe820 }
23204 },
23205/* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
23206 {
23207 { 0, 0, 0, 0 },
23208 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
23209 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0a0 }
23210 },
23211/* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
23212 {
23213 { 0, 0, 0, 0 },
23214 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23215 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe020 }
23216 },
23217/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
23218 {
23219 { 0, 0, 0, 0 },
23220 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23221 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe22000 }
23222 },
23223/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
23224 {
23225 { 0, 0, 0, 0 },
23226 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23227 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4200000 }
23228 },
23229/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
23230 {
23231 { 0, 0, 0, 0 },
23232 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23233 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6200000 }
23234 },
23235/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
23236 {
23237 { 0, 0, 0, 0 },
23238 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23239 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2a000 }
23240 },
23241/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
23242 {
23243 { 0, 0, 0, 0 },
23244 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23245 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4a00000 }
23246 },
23247/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
23248 {
23249 { 0, 0, 0, 0 },
23250 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23251 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2e000 }
23252 },
23253/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
23254 {
23255 { 0, 0, 0, 0 },
23256 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23257 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4e00000 }
23258 },
23259/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
23260 {
23261 { 0, 0, 0, 0 },
23262 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
23263 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6e00000 }
23264 },
23265/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
23266 {
23267 { 0, 0, 0, 0 },
23268 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
23269 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6a00000 }
23270 },
23271/* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
23272 {
23273 { 0, 0, 0, 0 },
23274 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
23275 & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe100 }
23276 },
23277/* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
23278 {
23279 { 0, 0, 0, 0 },
23280 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
23281 & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe104 }
23282 },
23283/* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
23284 {
23285 { 0, 0, 0, 0 },
23286 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
23287 & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe106 }
23288 },
23289/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
23290 {
23291 { 0, 0, 0, 0 },
23292 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23293 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe10800 }
23294 },
23295/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
23296 {
23297 { 0, 0, 0, 0 },
23298 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23299 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe10c0000 }
23300 },
23301/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
23302 {
23303 { 0, 0, 0, 0 },
23304 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23305 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe10a00 }
23306 },
23307/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
23308 {
23309 { 0, 0, 0, 0 },
23310 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23311 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe10e0000 }
23312 },
23313/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
23314 {
23315 { 0, 0, 0, 0 },
23316 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23317 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe10b00 }
23318 },
23319/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
23320 {
23321 { 0, 0, 0, 0 },
23322 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
23323 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe10f0000 }
23324 },
23325/* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
23326 {
23327 { 0, 0, 0, 0 },
23328 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
23329 & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe000 }
23330 },
23331/* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
23332 {
23333 { 0, 0, 0, 0 },
23334 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
23335 & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe004 }
23336 },
23337/* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
23338 {
23339 { 0, 0, 0, 0 },
23340 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
23341 & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe006 }
23342 },
23343/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
23344 {
23345 { 0, 0, 0, 0 },
23346 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23347 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe00800 }
23348 },
23349/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
23350 {
23351 { 0, 0, 0, 0 },
23352 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23353 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe00c0000 }
23354 },
23355/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
23356 {
23357 { 0, 0, 0, 0 },
23358 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23359 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe00a00 }
23360 },
23361/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
23362 {
23363 { 0, 0, 0, 0 },
23364 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23365 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe00e0000 }
23366 },
23367/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
23368 {
23369 { 0, 0, 0, 0 },
23370 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23371 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe00b00 }
23372 },
23373/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
23374 {
23375 { 0, 0, 0, 0 },
23376 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
23377 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe00f0000 }
23378 },
23379/* rorc.w $Dst32RnUnprefixedHI */
23380 {
23381 { 0, 0, 0, 0 },
23382 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
23383 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92e }
23384 },
23385/* rorc.w $Dst32AnUnprefixedHI */
23386 {
23387 { 0, 0, 0, 0 },
23388 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
23389 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1ae }
23390 },
23391/* rorc.w [$Dst32AnUnprefixed] */
23392 {
23393 { 0, 0, 0, 0 },
23394 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23395 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12e }
23396 },
23397/* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23398 {
23399 { 0, 0, 0, 0 },
23400 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23401 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32e00 }
23402 },
23403/* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23404 {
23405 { 0, 0, 0, 0 },
23406 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23407 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52e0000 }
23408 },
23409/* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23410 {
23411 { 0, 0, 0, 0 },
23412 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23413 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72e0000 }
23414 },
23415/* rorc.w ${Dsp-16-u8}[sb] */
23416 {
23417 { 0, 0, 0, 0 },
23418 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23419 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3ae00 }
23420 },
23421/* rorc.w ${Dsp-16-u16}[sb] */
23422 {
23423 { 0, 0, 0, 0 },
23424 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23425 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5ae0000 }
23426 },
23427/* rorc.w ${Dsp-16-s8}[fb] */
23428 {
23429 { 0, 0, 0, 0 },
23430 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23431 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ee00 }
23432 },
23433/* rorc.w ${Dsp-16-s16}[fb] */
23434 {
23435 { 0, 0, 0, 0 },
23436 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23437 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ee0000 }
23438 },
23439/* rorc.w ${Dsp-16-u16} */
23440 {
23441 { 0, 0, 0, 0 },
23442 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23443 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ee0000 }
23444 },
23445/* rorc.w ${Dsp-16-u24} */
23446 {
23447 { 0, 0, 0, 0 },
23448 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23449 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7ae0000 }
23450 },
23451/* rorc.b $Dst32RnUnprefixedQI */
23452 {
23453 { 0, 0, 0, 0 },
23454 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
23455 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82e }
23456 },
23457/* rorc.b $Dst32AnUnprefixedQI */
23458 {
23459 { 0, 0, 0, 0 },
23460 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
23461 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0ae }
23462 },
23463/* rorc.b [$Dst32AnUnprefixed] */
23464 {
23465 { 0, 0, 0, 0 },
23466 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23467 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02e }
23468 },
23469/* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23470 {
23471 { 0, 0, 0, 0 },
23472 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23473 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22e00 }
23474 },
23475/* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23476 {
23477 { 0, 0, 0, 0 },
23478 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23479 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42e0000 }
23480 },
23481/* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23482 {
23483 { 0, 0, 0, 0 },
23484 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23485 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62e0000 }
23486 },
23487/* rorc.b ${Dsp-16-u8}[sb] */
23488 {
23489 { 0, 0, 0, 0 },
23490 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23491 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2ae00 }
23492 },
23493/* rorc.b ${Dsp-16-u16}[sb] */
23494 {
23495 { 0, 0, 0, 0 },
23496 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23497 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4ae0000 }
23498 },
23499/* rorc.b ${Dsp-16-s8}[fb] */
23500 {
23501 { 0, 0, 0, 0 },
23502 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23503 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ee00 }
23504 },
23505/* rorc.b ${Dsp-16-s16}[fb] */
23506 {
23507 { 0, 0, 0, 0 },
23508 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23509 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ee0000 }
23510 },
23511/* rorc.b ${Dsp-16-u16} */
23512 {
23513 { 0, 0, 0, 0 },
23514 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23515 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ee0000 }
23516 },
23517/* rorc.b ${Dsp-16-u24} */
23518 {
23519 { 0, 0, 0, 0 },
23520 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23521 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6ae0000 }
23522 },
23523/* rorc.w $Dst16RnHI */
23524 {
23525 { 0, 0, 0, 0 },
23526 { { MNEM, ' ', OP (DST16RNHI), 0 } },
23527 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77b0 }
23528 },
23529/* rorc.w $Dst16AnHI */
23530 {
23531 { 0, 0, 0, 0 },
23532 { { MNEM, ' ', OP (DST16ANHI), 0 } },
23533 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77b4 }
23534 },
23535/* rorc.w [$Dst16An] */
23536 {
23537 { 0, 0, 0, 0 },
23538 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23539 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77b6 }
23540 },
23541/* rorc.w ${Dsp-16-u8}[$Dst16An] */
23542 {
23543 { 0, 0, 0, 0 },
23544 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23545 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77b800 }
23546 },
23547/* rorc.w ${Dsp-16-u16}[$Dst16An] */
23548 {
23549 { 0, 0, 0, 0 },
23550 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23551 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77bc0000 }
23552 },
23553/* rorc.w ${Dsp-16-u8}[sb] */
23554 {
23555 { 0, 0, 0, 0 },
23556 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23557 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ba00 }
23558 },
23559/* rorc.w ${Dsp-16-u16}[sb] */
23560 {
23561 { 0, 0, 0, 0 },
23562 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23563 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77be0000 }
23564 },
23565/* rorc.w ${Dsp-16-s8}[fb] */
23566 {
23567 { 0, 0, 0, 0 },
23568 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23569 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77bb00 }
23570 },
23571/* rorc.w ${Dsp-16-u16} */
23572 {
23573 { 0, 0, 0, 0 },
23574 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23575 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77bf0000 }
23576 },
23577/* rorc.b $Dst16RnQI */
23578 {
23579 { 0, 0, 0, 0 },
23580 { { MNEM, ' ', OP (DST16RNQI), 0 } },
23581 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76b0 }
23582 },
23583/* rorc.b $Dst16AnQI */
23584 {
23585 { 0, 0, 0, 0 },
23586 { { MNEM, ' ', OP (DST16ANQI), 0 } },
23587 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76b4 }
23588 },
23589/* rorc.b [$Dst16An] */
23590 {
23591 { 0, 0, 0, 0 },
23592 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23593 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76b6 }
23594 },
23595/* rorc.b ${Dsp-16-u8}[$Dst16An] */
23596 {
23597 { 0, 0, 0, 0 },
23598 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23599 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76b800 }
23600 },
23601/* rorc.b ${Dsp-16-u16}[$Dst16An] */
23602 {
23603 { 0, 0, 0, 0 },
23604 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23605 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76bc0000 }
23606 },
23607/* rorc.b ${Dsp-16-u8}[sb] */
23608 {
23609 { 0, 0, 0, 0 },
23610 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23611 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ba00 }
23612 },
23613/* rorc.b ${Dsp-16-u16}[sb] */
23614 {
23615 { 0, 0, 0, 0 },
23616 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23617 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76be0000 }
23618 },
23619/* rorc.b ${Dsp-16-s8}[fb] */
23620 {
23621 { 0, 0, 0, 0 },
23622 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23623 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76bb00 }
23624 },
23625/* rorc.b ${Dsp-16-u16} */
23626 {
23627 { 0, 0, 0, 0 },
23628 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23629 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76bf0000 }
23630 },
23631/* rolc.w $Dst32RnUnprefixedHI */
23632 {
23633 { 0, 0, 0, 0 },
23634 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
23635 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92e }
23636 },
23637/* rolc.w $Dst32AnUnprefixedHI */
23638 {
23639 { 0, 0, 0, 0 },
23640 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
23641 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1ae }
23642 },
23643/* rolc.w [$Dst32AnUnprefixed] */
23644 {
23645 { 0, 0, 0, 0 },
23646 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23647 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12e }
23648 },
23649/* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23650 {
23651 { 0, 0, 0, 0 },
23652 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23653 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32e00 }
23654 },
23655/* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23656 {
23657 { 0, 0, 0, 0 },
23658 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23659 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52e0000 }
23660 },
23661/* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23662 {
23663 { 0, 0, 0, 0 },
23664 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23665 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72e0000 }
23666 },
23667/* rolc.w ${Dsp-16-u8}[sb] */
23668 {
23669 { 0, 0, 0, 0 },
23670 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23671 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3ae00 }
23672 },
23673/* rolc.w ${Dsp-16-u16}[sb] */
23674 {
23675 { 0, 0, 0, 0 },
23676 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23677 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5ae0000 }
23678 },
23679/* rolc.w ${Dsp-16-s8}[fb] */
23680 {
23681 { 0, 0, 0, 0 },
23682 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23683 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ee00 }
23684 },
23685/* rolc.w ${Dsp-16-s16}[fb] */
23686 {
23687 { 0, 0, 0, 0 },
23688 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23689 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ee0000 }
23690 },
23691/* rolc.w ${Dsp-16-u16} */
23692 {
23693 { 0, 0, 0, 0 },
23694 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23695 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ee0000 }
23696 },
23697/* rolc.w ${Dsp-16-u24} */
23698 {
23699 { 0, 0, 0, 0 },
23700 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23701 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7ae0000 }
23702 },
23703/* rolc.b $Dst32RnUnprefixedQI */
23704 {
23705 { 0, 0, 0, 0 },
23706 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
23707 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82e }
23708 },
23709/* rolc.b $Dst32AnUnprefixedQI */
23710 {
23711 { 0, 0, 0, 0 },
23712 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
23713 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0ae }
23714 },
23715/* rolc.b [$Dst32AnUnprefixed] */
23716 {
23717 { 0, 0, 0, 0 },
23718 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23719 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02e }
23720 },
23721/* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23722 {
23723 { 0, 0, 0, 0 },
23724 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23725 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22e00 }
23726 },
23727/* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23728 {
23729 { 0, 0, 0, 0 },
23730 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23731 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42e0000 }
23732 },
23733/* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23734 {
23735 { 0, 0, 0, 0 },
23736 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23737 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62e0000 }
23738 },
23739/* rolc.b ${Dsp-16-u8}[sb] */
23740 {
23741 { 0, 0, 0, 0 },
23742 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23743 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2ae00 }
23744 },
23745/* rolc.b ${Dsp-16-u16}[sb] */
23746 {
23747 { 0, 0, 0, 0 },
23748 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23749 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4ae0000 }
23750 },
23751/* rolc.b ${Dsp-16-s8}[fb] */
23752 {
23753 { 0, 0, 0, 0 },
23754 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23755 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ee00 }
23756 },
23757/* rolc.b ${Dsp-16-s16}[fb] */
23758 {
23759 { 0, 0, 0, 0 },
23760 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23761 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ee0000 }
23762 },
23763/* rolc.b ${Dsp-16-u16} */
23764 {
23765 { 0, 0, 0, 0 },
23766 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23767 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ee0000 }
23768 },
23769/* rolc.b ${Dsp-16-u24} */
23770 {
23771 { 0, 0, 0, 0 },
23772 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23773 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6ae0000 }
23774 },
23775/* rolc.w $Dst16RnHI */
23776 {
23777 { 0, 0, 0, 0 },
23778 { { MNEM, ' ', OP (DST16RNHI), 0 } },
23779 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77a0 }
23780 },
23781/* rolc.w $Dst16AnHI */
23782 {
23783 { 0, 0, 0, 0 },
23784 { { MNEM, ' ', OP (DST16ANHI), 0 } },
23785 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77a4 }
23786 },
23787/* rolc.w [$Dst16An] */
23788 {
23789 { 0, 0, 0, 0 },
23790 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23791 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77a6 }
23792 },
23793/* rolc.w ${Dsp-16-u8}[$Dst16An] */
23794 {
23795 { 0, 0, 0, 0 },
23796 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23797 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77a800 }
23798 },
23799/* rolc.w ${Dsp-16-u16}[$Dst16An] */
23800 {
23801 { 0, 0, 0, 0 },
23802 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23803 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ac0000 }
23804 },
23805/* rolc.w ${Dsp-16-u8}[sb] */
23806 {
23807 { 0, 0, 0, 0 },
23808 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23809 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77aa00 }
23810 },
23811/* rolc.w ${Dsp-16-u16}[sb] */
23812 {
23813 { 0, 0, 0, 0 },
23814 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23815 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ae0000 }
23816 },
23817/* rolc.w ${Dsp-16-s8}[fb] */
23818 {
23819 { 0, 0, 0, 0 },
23820 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23821 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77ab00 }
23822 },
23823/* rolc.w ${Dsp-16-u16} */
23824 {
23825 { 0, 0, 0, 0 },
23826 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23827 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77af0000 }
23828 },
23829/* rolc.b $Dst16RnQI */
23830 {
23831 { 0, 0, 0, 0 },
23832 { { MNEM, ' ', OP (DST16RNQI), 0 } },
23833 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76a0 }
23834 },
23835/* rolc.b $Dst16AnQI */
23836 {
23837 { 0, 0, 0, 0 },
23838 { { MNEM, ' ', OP (DST16ANQI), 0 } },
23839 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76a4 }
23840 },
23841/* rolc.b [$Dst16An] */
23842 {
23843 { 0, 0, 0, 0 },
23844 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23845 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76a6 }
23846 },
23847/* rolc.b ${Dsp-16-u8}[$Dst16An] */
23848 {
23849 { 0, 0, 0, 0 },
23850 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23851 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76a800 }
23852 },
23853/* rolc.b ${Dsp-16-u16}[$Dst16An] */
23854 {
23855 { 0, 0, 0, 0 },
23856 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23857 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ac0000 }
23858 },
23859/* rolc.b ${Dsp-16-u8}[sb] */
23860 {
23861 { 0, 0, 0, 0 },
23862 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23863 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76aa00 }
23864 },
23865/* rolc.b ${Dsp-16-u16}[sb] */
23866 {
23867 { 0, 0, 0, 0 },
23868 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23869 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ae0000 }
23870 },
23871/* rolc.b ${Dsp-16-s8}[fb] */
23872 {
23873 { 0, 0, 0, 0 },
23874 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23875 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76ab00 }
23876 },
23877/* rolc.b ${Dsp-16-u16} */
23878 {
23879 { 0, 0, 0, 0 },
23880 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23881 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76af0000 }
23882 },
23883/* pusha [$Dst32AnUnprefixed] */
23884 {
23885 { 0, 0, 0, 0 },
23886 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23887 & ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI, { 0xb001 }
23888 },
23889/* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23890 {
23891 { 0, 0, 0, 0 },
23892 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23893 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xb20100 }
23894 },
23895/* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23896 {
23897 { 0, 0, 0, 0 },
23898 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23899 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xb4010000 }
23900 },
23901/* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23902 {
23903 { 0, 0, 0, 0 },
23904 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23905 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xb6010000 }
23906 },
23907/* pusha ${Dsp-16-u8}[sb] */
23908 {
23909 { 0, 0, 0, 0 },
23910 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23911 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xb28100 }
23912 },
23913/* pusha ${Dsp-16-u16}[sb] */
23914 {
23915 { 0, 0, 0, 0 },
23916 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23917 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xb4810000 }
23918 },
23919/* pusha ${Dsp-16-s8}[fb] */
23920 {
23921 { 0, 0, 0, 0 },
23922 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23923 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xb2c100 }
23924 },
23925/* pusha ${Dsp-16-s16}[fb] */
23926 {
23927 { 0, 0, 0, 0 },
23928 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23929 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xb4c10000 }
23930 },
23931/* pusha ${Dsp-16-u16} */
23932 {
23933 { 0, 0, 0, 0 },
23934 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23935 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xb6c10000 }
23936 },
23937/* pusha ${Dsp-16-u24} */
23938 {
23939 { 0, 0, 0, 0 },
23940 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23941 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xb6810000 }
23942 },
23943/* pusha [$Dst16An] */
23944 {
23945 { 0, 0, 0, 0 },
23946 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23947 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0x7d96 }
23948 },
23949/* pusha ${Dsp-16-u8}[$Dst16An] */
23950 {
23951 { 0, 0, 0, 0 },
23952 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23953 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0x7d9800 }
23954 },
23955/* pusha ${Dsp-16-u16}[$Dst16An] */
23956 {
23957 { 0, 0, 0, 0 },
23958 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23959 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0x7d9c0000 }
23960 },
23961/* pusha ${Dsp-16-u8}[sb] */
23962 {
23963 { 0, 0, 0, 0 },
23964 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23965 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0x7d9a00 }
23966 },
23967/* pusha ${Dsp-16-u16}[sb] */
23968 {
23969 { 0, 0, 0, 0 },
23970 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23971 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0x7d9e0000 }
23972 },
23973/* pusha ${Dsp-16-s8}[fb] */
23974 {
23975 { 0, 0, 0, 0 },
23976 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23977 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0x7d9b00 }
23978 },
23979/* pusha ${Dsp-16-u16} */
23980 {
23981 { 0, 0, 0, 0 },
23982 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23983 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0x7d9f0000 }
23984 },
23985/* push.l $Dst32RnUnprefixedSI */
23986 {
23987 { 0, 0, 0, 0 },
23988 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
23989 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa801 }
23990 },
23991/* push.l $Dst32AnUnprefixedSI */
23992 {
23993 { 0, 0, 0, 0 },
23994 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
23995 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa081 }
23996 },
23997/* push.l [$Dst32AnUnprefixed] */
23998 {
23999 { 0, 0, 0, 0 },
24000 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24001 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa001 }
24002 },
24003/* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24004 {
24005 { 0, 0, 0, 0 },
24006 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24007 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa20100 }
24008 },
24009/* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24010 {
24011 { 0, 0, 0, 0 },
24012 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24013 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4010000 }
24014 },
24015/* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24016 {
24017 { 0, 0, 0, 0 },
24018 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24019 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6010000 }
24020 },
24021/* push.l ${Dsp-16-u8}[sb] */
24022 {
24023 { 0, 0, 0, 0 },
24024 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24025 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa28100 }
24026 },
24027/* push.l ${Dsp-16-u16}[sb] */
24028 {
24029 { 0, 0, 0, 0 },
24030 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24031 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4810000 }
24032 },
24033/* push.l ${Dsp-16-s8}[fb] */
24034 {
24035 { 0, 0, 0, 0 },
24036 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24037 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2c100 }
24038 },
24039/* push.l ${Dsp-16-s16}[fb] */
24040 {
24041 { 0, 0, 0, 0 },
24042 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24043 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4c10000 }
24044 },
24045/* push.l ${Dsp-16-u16} */
24046 {
24047 { 0, 0, 0, 0 },
24048 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24049 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6c10000 }
24050 },
24051/* push.l ${Dsp-16-u24} */
24052 {
24053 { 0, 0, 0, 0 },
24054 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24055 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6810000 }
24056 },
24057/* push.w${S} ${An16-push-S} */
24058 {
24059 { 0, 0, 0, 0 },
24060 { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } },
24061 & ifmt_push16_b_s_an_An16_push_S_derived, { 0xc2 }
24062 },
24063/* push.b${S} ${Rn16-push-S} */
24064 {
24065 { 0, 0, 0, 0 },
24066 { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } },
24067 & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x82 }
24068 },
24069/* push.w $Dst32RnUnprefixedHI */
24070 {
24071 { 0, 0, 0, 0 },
24072 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
24073 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90e }
24074 },
24075/* push.w $Dst32AnUnprefixedHI */
24076 {
24077 { 0, 0, 0, 0 },
24078 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
24079 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18e }
24080 },
24081/* push.w [$Dst32AnUnprefixed] */
24082 {
24083 { 0, 0, 0, 0 },
24084 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24085 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10e }
24086 },
24087/* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24088 {
24089 { 0, 0, 0, 0 },
24090 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24091 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30e00 }
24092 },
24093/* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24094 {
24095 { 0, 0, 0, 0 },
24096 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24097 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50e0000 }
24098 },
24099/* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24100 {
24101 { 0, 0, 0, 0 },
24102 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24103 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70e0000 }
24104 },
24105/* push.w ${Dsp-16-u8}[sb] */
24106 {
24107 { 0, 0, 0, 0 },
24108 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24109 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38e00 }
24110 },
24111/* push.w ${Dsp-16-u16}[sb] */
24112 {
24113 { 0, 0, 0, 0 },
24114 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24115 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58e0000 }
24116 },
24117/* push.w ${Dsp-16-s8}[fb] */
24118 {
24119 { 0, 0, 0, 0 },
24120 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24121 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ce00 }
24122 },
24123/* push.w ${Dsp-16-s16}[fb] */
24124 {
24125 { 0, 0, 0, 0 },
24126 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24127 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ce0000 }
24128 },
24129/* push.w ${Dsp-16-u16} */
24130 {
24131 { 0, 0, 0, 0 },
24132 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24133 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ce0000 }
24134 },
24135/* push.w ${Dsp-16-u24} */
24136 {
24137 { 0, 0, 0, 0 },
24138 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24139 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78e0000 }
24140 },
24141/* push.b $Dst32RnUnprefixedQI */
24142 {
24143 { 0, 0, 0, 0 },
24144 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
24145 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc80e }
24146 },
24147/* push.b $Dst32AnUnprefixedQI */
24148 {
24149 { 0, 0, 0, 0 },
24150 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
24151 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc08e }
24152 },
24153/* push.b [$Dst32AnUnprefixed] */
24154 {
24155 { 0, 0, 0, 0 },
24156 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24157 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc00e }
24158 },
24159/* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24160 {
24161 { 0, 0, 0, 0 },
24162 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24163 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20e00 }
24164 },
24165/* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24166 {
24167 { 0, 0, 0, 0 },
24168 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24169 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40e0000 }
24170 },
24171/* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24172 {
24173 { 0, 0, 0, 0 },
24174 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24175 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60e0000 }
24176 },
24177/* push.b ${Dsp-16-u8}[sb] */
24178 {
24179 { 0, 0, 0, 0 },
24180 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24181 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28e00 }
24182 },
24183/* push.b ${Dsp-16-u16}[sb] */
24184 {
24185 { 0, 0, 0, 0 },
24186 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24187 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48e0000 }
24188 },
24189/* push.b ${Dsp-16-s8}[fb] */
24190 {
24191 { 0, 0, 0, 0 },
24192 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24193 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ce00 }
24194 },
24195/* push.b ${Dsp-16-s16}[fb] */
24196 {
24197 { 0, 0, 0, 0 },
24198 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24199 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ce0000 }
24200 },
24201/* push.b ${Dsp-16-u16} */
24202 {
24203 { 0, 0, 0, 0 },
24204 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24205 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ce0000 }
24206 },
24207/* push.b ${Dsp-16-u24} */
24208 {
24209 { 0, 0, 0, 0 },
24210 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24211 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc68e0000 }
24212 },
24213/* push.w $Dst16RnHI */
24214 {
24215 { 0, 0, 0, 0 },
24216 { { MNEM, ' ', OP (DST16RNHI), 0 } },
24217 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7540 }
24218 },
24219/* push.w $Dst16AnHI */
24220 {
24221 { 0, 0, 0, 0 },
24222 { { MNEM, ' ', OP (DST16ANHI), 0 } },
24223 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7544 }
24224 },
24225/* push.w [$Dst16An] */
24226 {
24227 { 0, 0, 0, 0 },
24228 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24229 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7546 }
24230 },
24231/* push.w ${Dsp-16-u8}[$Dst16An] */
24232 {
24233 { 0, 0, 0, 0 },
24234 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24235 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x754800 }
24236 },
24237/* push.w ${Dsp-16-u16}[$Dst16An] */
24238 {
24239 { 0, 0, 0, 0 },
24240 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24241 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x754c0000 }
24242 },
24243/* push.w ${Dsp-16-u8}[sb] */
24244 {
24245 { 0, 0, 0, 0 },
24246 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24247 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x754a00 }
24248 },
24249/* push.w ${Dsp-16-u16}[sb] */
24250 {
24251 { 0, 0, 0, 0 },
24252 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24253 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x754e0000 }
24254 },
24255/* push.w ${Dsp-16-s8}[fb] */
24256 {
24257 { 0, 0, 0, 0 },
24258 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24259 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x754b00 }
24260 },
24261/* push.w ${Dsp-16-u16} */
24262 {
24263 { 0, 0, 0, 0 },
24264 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24265 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x754f0000 }
24266 },
24267/* push.b $Dst16RnQI */
24268 {
24269 { 0, 0, 0, 0 },
24270 { { MNEM, ' ', OP (DST16RNQI), 0 } },
24271 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7440 }
24272 },
24273/* push.b $Dst16AnQI */
24274 {
24275 { 0, 0, 0, 0 },
24276 { { MNEM, ' ', OP (DST16ANQI), 0 } },
24277 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7444 }
24278 },
24279/* push.b [$Dst16An] */
24280 {
24281 { 0, 0, 0, 0 },
24282 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24283 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7446 }
24284 },
24285/* push.b ${Dsp-16-u8}[$Dst16An] */
24286 {
24287 { 0, 0, 0, 0 },
24288 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24289 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x744800 }
24290 },
24291/* push.b ${Dsp-16-u16}[$Dst16An] */
24292 {
24293 { 0, 0, 0, 0 },
24294 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24295 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x744c0000 }
24296 },
24297/* push.b ${Dsp-16-u8}[sb] */
24298 {
24299 { 0, 0, 0, 0 },
24300 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24301 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x744a00 }
24302 },
24303/* push.b ${Dsp-16-u16}[sb] */
24304 {
24305 { 0, 0, 0, 0 },
24306 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24307 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x744e0000 }
24308 },
24309/* push.b ${Dsp-16-s8}[fb] */
24310 {
24311 { 0, 0, 0, 0 },
24312 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24313 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x744b00 }
24314 },
24315/* push.b ${Dsp-16-u16} */
24316 {
24317 { 0, 0, 0, 0 },
24318 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24319 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x744f0000 }
24320 },
24321/* pop.w${S} ${An16-push-S} */
24322 {
24323 { 0, 0, 0, 0 },
24324 { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } },
24325 & ifmt_push16_b_s_an_An16_push_S_derived, { 0xd2 }
24326 },
24327/* pop.b${S} ${Rn16-push-S} */
24328 {
24329 { 0, 0, 0, 0 },
24330 { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } },
24331 & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x92 }
24332 },
24333/* pop.w $Dst32RnUnprefixedHI */
24334 {
24335 { 0, 0, 0, 0 },
24336 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
24337 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92f }
24338 },
24339/* pop.w $Dst32AnUnprefixedHI */
24340 {
24341 { 0, 0, 0, 0 },
24342 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
24343 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1af }
24344 },
24345/* pop.w [$Dst32AnUnprefixed] */
24346 {
24347 { 0, 0, 0, 0 },
24348 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24349 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12f }
24350 },
24351/* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24352 {
24353 { 0, 0, 0, 0 },
24354 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24355 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32f00 }
24356 },
24357/* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24358 {
24359 { 0, 0, 0, 0 },
24360 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24361 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52f0000 }
24362 },
24363/* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24364 {
24365 { 0, 0, 0, 0 },
24366 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24367 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72f0000 }
24368 },
24369/* pop.w ${Dsp-16-u8}[sb] */
24370 {
24371 { 0, 0, 0, 0 },
24372 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24373 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3af00 }
24374 },
24375/* pop.w ${Dsp-16-u16}[sb] */
24376 {
24377 { 0, 0, 0, 0 },
24378 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24379 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5af0000 }
24380 },
24381/* pop.w ${Dsp-16-s8}[fb] */
24382 {
24383 { 0, 0, 0, 0 },
24384 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24385 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ef00 }
24386 },
24387/* pop.w ${Dsp-16-s16}[fb] */
24388 {
24389 { 0, 0, 0, 0 },
24390 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24391 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ef0000 }
24392 },
24393/* pop.w ${Dsp-16-u16} */
24394 {
24395 { 0, 0, 0, 0 },
24396 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24397 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ef0000 }
24398 },
24399/* pop.w ${Dsp-16-u24} */
24400 {
24401 { 0, 0, 0, 0 },
24402 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24403 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7af0000 }
24404 },
24405/* pop.b $Dst32RnUnprefixedQI */
24406 {
24407 { 0, 0, 0, 0 },
24408 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
24409 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82f }
24410 },
24411/* pop.b $Dst32AnUnprefixedQI */
24412 {
24413 { 0, 0, 0, 0 },
24414 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
24415 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0af }
24416 },
24417/* pop.b [$Dst32AnUnprefixed] */
24418 {
24419 { 0, 0, 0, 0 },
24420 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24421 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02f }
24422 },
24423/* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24424 {
24425 { 0, 0, 0, 0 },
24426 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24427 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22f00 }
24428 },
24429/* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24430 {
24431 { 0, 0, 0, 0 },
24432 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24433 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42f0000 }
24434 },
24435/* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24436 {
24437 { 0, 0, 0, 0 },
24438 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24439 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62f0000 }
24440 },
24441/* pop.b ${Dsp-16-u8}[sb] */
24442 {
24443 { 0, 0, 0, 0 },
24444 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24445 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2af00 }
24446 },
24447/* pop.b ${Dsp-16-u16}[sb] */
24448 {
24449 { 0, 0, 0, 0 },
24450 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24451 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4af0000 }
24452 },
24453/* pop.b ${Dsp-16-s8}[fb] */
24454 {
24455 { 0, 0, 0, 0 },
24456 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24457 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ef00 }
24458 },
24459/* pop.b ${Dsp-16-s16}[fb] */
24460 {
24461 { 0, 0, 0, 0 },
24462 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24463 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ef0000 }
24464 },
24465/* pop.b ${Dsp-16-u16} */
24466 {
24467 { 0, 0, 0, 0 },
24468 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24469 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ef0000 }
24470 },
24471/* pop.b ${Dsp-16-u24} */
24472 {
24473 { 0, 0, 0, 0 },
24474 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24475 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6af0000 }
24476 },
24477/* pop.w $Dst16RnHI */
24478 {
24479 { 0, 0, 0, 0 },
24480 { { MNEM, ' ', OP (DST16RNHI), 0 } },
24481 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75d0 }
24482 },
24483/* pop.w $Dst16AnHI */
24484 {
24485 { 0, 0, 0, 0 },
24486 { { MNEM, ' ', OP (DST16ANHI), 0 } },
24487 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75d4 }
24488 },
24489/* pop.w [$Dst16An] */
24490 {
24491 { 0, 0, 0, 0 },
24492 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24493 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75d6 }
24494 },
24495/* pop.w ${Dsp-16-u8}[$Dst16An] */
24496 {
24497 { 0, 0, 0, 0 },
24498 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24499 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75d800 }
24500 },
24501/* pop.w ${Dsp-16-u16}[$Dst16An] */
24502 {
24503 { 0, 0, 0, 0 },
24504 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24505 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75dc0000 }
24506 },
24507/* pop.w ${Dsp-16-u8}[sb] */
24508 {
24509 { 0, 0, 0, 0 },
24510 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24511 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75da00 }
24512 },
24513/* pop.w ${Dsp-16-u16}[sb] */
24514 {
24515 { 0, 0, 0, 0 },
24516 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24517 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75de0000 }
24518 },
24519/* pop.w ${Dsp-16-s8}[fb] */
24520 {
24521 { 0, 0, 0, 0 },
24522 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24523 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75db00 }
24524 },
24525/* pop.w ${Dsp-16-u16} */
24526 {
24527 { 0, 0, 0, 0 },
24528 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24529 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75df0000 }
24530 },
24531/* pop.b $Dst16RnQI */
24532 {
24533 { 0, 0, 0, 0 },
24534 { { MNEM, ' ', OP (DST16RNQI), 0 } },
24535 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74d0 }
24536 },
24537/* pop.b $Dst16AnQI */
24538 {
24539 { 0, 0, 0, 0 },
24540 { { MNEM, ' ', OP (DST16ANQI), 0 } },
24541 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74d4 }
24542 },
24543/* pop.b [$Dst16An] */
24544 {
24545 { 0, 0, 0, 0 },
24546 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24547 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74d6 }
24548 },
24549/* pop.b ${Dsp-16-u8}[$Dst16An] */
24550 {
24551 { 0, 0, 0, 0 },
24552 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24553 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74d800 }
24554 },
24555/* pop.b ${Dsp-16-u16}[$Dst16An] */
24556 {
24557 { 0, 0, 0, 0 },
24558 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24559 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74dc0000 }
24560 },
24561/* pop.b ${Dsp-16-u8}[sb] */
24562 {
24563 { 0, 0, 0, 0 },
24564 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24565 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74da00 }
24566 },
24567/* pop.b ${Dsp-16-u16}[sb] */
24568 {
24569 { 0, 0, 0, 0 },
24570 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24571 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74de0000 }
24572 },
24573/* pop.b ${Dsp-16-s8}[fb] */
24574 {
24575 { 0, 0, 0, 0 },
24576 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24577 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74db00 }
24578 },
24579/* pop.b ${Dsp-16-u16} */
24580 {
24581 { 0, 0, 0, 0 },
24582 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24583 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74df0000 }
24584 },
24585/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
24586 {
24587 { 0, 0, 0, 0 },
24588 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24589 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990500 }
24590 },
24591/* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
24592 {
24593 { 0, 0, 0, 0 },
24594 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24595 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992500 }
24596 },
24597/* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
24598 {
24599 { 0, 0, 0, 0 },
24600 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24601 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993500 }
24602 },
24603/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
24604 {
24605 { 0, 0, 0, 0 },
24606 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24607 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918500 }
24608 },
24609/* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
24610 {
24611 { 0, 0, 0, 0 },
24612 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24613 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a500 }
24614 },
24615/* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
24616 {
24617 { 0, 0, 0, 0 },
24618 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24619 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b500 }
24620 },
24621/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
24622 {
24623 { 0, 0, 0, 0 },
24624 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24625 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910500 }
24626 },
24627/* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
24628 {
24629 { 0, 0, 0, 0 },
24630 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24631 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912500 }
24632 },
24633/* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
24634 {
24635 { 0, 0, 0, 0 },
24636 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24637 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913500 }
24638 },
24639/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24640 {
24641 { 0, 0, 0, 0 },
24642 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24643 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93050000 }
24644 },
24645/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24646 {
24647 { 0, 0, 0, 0 },
24648 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24649 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93250000 }
24650 },
24651/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24652 {
24653 { 0, 0, 0, 0 },
24654 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24655 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93350000 }
24656 },
24657/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24658 {
24659 { 0, 0, 0, 0 },
24660 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24661 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95050000 }
24662 },
24663/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24664 {
24665 { 0, 0, 0, 0 },
24666 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24667 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95250000 }
24668 },
24669/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24670 {
24671 { 0, 0, 0, 0 },
24672 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24673 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95350000 }
24674 },
24675/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24676 {
24677 { 0, 0, 0, 0 },
24678 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24679 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97050000 }
24680 },
24681/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24682 {
24683 { 0, 0, 0, 0 },
24684 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24685 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97250000 }
24686 },
24687/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24688 {
24689 { 0, 0, 0, 0 },
24690 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24691 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97350000 }
24692 },
24693/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
24694 {
24695 { 0, 0, 0, 0 },
24696 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24697 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93850000 }
24698 },
24699/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24700 {
24701 { 0, 0, 0, 0 },
24702 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24703 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a50000 }
24704 },
24705/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24706 {
24707 { 0, 0, 0, 0 },
24708 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24709 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b50000 }
24710 },
24711/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
24712 {
24713 { 0, 0, 0, 0 },
24714 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24715 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95850000 }
24716 },
24717/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24718 {
24719 { 0, 0, 0, 0 },
24720 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24721 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a50000 }
24722 },
24723/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24724 {
24725 { 0, 0, 0, 0 },
24726 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24727 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b50000 }
24728 },
24729/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
24730 {
24731 { 0, 0, 0, 0 },
24732 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24733 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c50000 }
24734 },
24735/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24736 {
24737 { 0, 0, 0, 0 },
24738 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24739 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e50000 }
24740 },
24741/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24742 {
24743 { 0, 0, 0, 0 },
24744 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24745 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f50000 }
24746 },
24747/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
24748 {
24749 { 0, 0, 0, 0 },
24750 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24751 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c50000 }
24752 },
24753/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
24754 {
24755 { 0, 0, 0, 0 },
24756 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24757 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e50000 }
24758 },
24759/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
24760 {
24761 { 0, 0, 0, 0 },
24762 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24763 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f50000 }
24764 },
24765/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
24766 {
24767 { 0, 0, 0, 0 },
24768 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
24769 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c50000 }
24770 },
24771/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24772 {
24773 { 0, 0, 0, 0 },
24774 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
24775 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e50000 }
24776 },
24777/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24778 {
24779 { 0, 0, 0, 0 },
24780 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
24781 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f50000 }
24782 },
24783/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
24784 {
24785 { 0, 0, 0, 0 },
24786 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
24787 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97850000 }
24788 },
24789/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
24790 {
24791 { 0, 0, 0, 0 },
24792 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
24793 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a50000 }
24794 },
24795/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
24796 {
24797 { 0, 0, 0, 0 },
24798 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
24799 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b50000 }
24800 },
24801/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
24802 {
24803 { 0, 0, 0, 0 },
24804 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24805 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9050000 }
24806 },
24807/* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
24808 {
24809 { 0, 0, 0, 0 },
24810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24811 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9250000 }
24812 },
24813/* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
24814 {
24815 { 0, 0, 0, 0 },
24816 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24817 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9350000 }
24818 },
24819/* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
24820 {
24821 { 0, 0, 0, 0 },
24822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24823 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9350000 }
24824 },
24825/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
24826 {
24827 { 0, 0, 0, 0 },
24828 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24829 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1850000 }
24830 },
24831/* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
24832 {
24833 { 0, 0, 0, 0 },
24834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24835 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a50000 }
24836 },
24837/* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
24838 {
24839 { 0, 0, 0, 0 },
24840 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24841 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b50000 }
24842 },
24843/* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
24844 {
24845 { 0, 0, 0, 0 },
24846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24847 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b50000 }
24848 },
24849/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
24850 {
24851 { 0, 0, 0, 0 },
24852 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24853 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1050000 }
24854 },
24855/* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
24856 {
24857 { 0, 0, 0, 0 },
24858 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24859 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1250000 }
24860 },
24861/* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
24862 {
24863 { 0, 0, 0, 0 },
24864 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24865 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1350000 }
24866 },
24867/* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
24868 {
24869 { 0, 0, 0, 0 },
24870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24871 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1350000 }
24872 },
24873/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
24874 {
24875 { 0, 0, 0, 0 },
24876 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24877 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3050000 }
24878 },
24879/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
24880 {
24881 { 0, 0, 0, 0 },
24882 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24883 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3250000 }
24884 },
24885/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
24886 {
24887 { 0, 0, 0, 0 },
24888 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24889 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3350000 }
24890 },
24891/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
24892 {
24893 { 0, 0, 0, 0 },
24894 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24895 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3350000 }
24896 },
24897/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
24898 {
24899 { 0, 0, 0, 0 },
24900 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24901 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5050000 }
24902 },
24903/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
24904 {
24905 { 0, 0, 0, 0 },
24906 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24907 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5250000 }
24908 },
24909/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
24910 {
24911 { 0, 0, 0, 0 },
24912 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24913 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5350000 }
24914 },
24915/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
24916 {
24917 { 0, 0, 0, 0 },
24918 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24919 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5350000 }
24920 },
24921/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
24922 {
24923 { 0, 0, 0, 0 },
24924 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24925 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7050000 }
24926 },
24927/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
24928 {
24929 { 0, 0, 0, 0 },
24930 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24931 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7250000 }
24932 },
24933/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
24934 {
24935 { 0, 0, 0, 0 },
24936 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24937 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7350000 }
24938 },
24939/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
24940 {
24941 { 0, 0, 0, 0 },
24942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24943 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7350000 }
24944 },
24945/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
24946 {
24947 { 0, 0, 0, 0 },
24948 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
24949 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3850000 }
24950 },
24951/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
24952 {
24953 { 0, 0, 0, 0 },
24954 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
24955 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a50000 }
24956 },
24957/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
24958 {
24959 { 0, 0, 0, 0 },
24960 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
24961 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b50000 }
24962 },
24963/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
24964 {
24965 { 0, 0, 0, 0 },
24966 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
24967 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b50000 }
24968 },
24969/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
24970 {
24971 { 0, 0, 0, 0 },
24972 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
24973 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5850000 }
24974 },
24975/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
24976 {
24977 { 0, 0, 0, 0 },
24978 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
24979 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a50000 }
24980 },
24981/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
24982 {
24983 { 0, 0, 0, 0 },
24984 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
24985 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b50000 }
24986 },
24987/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
24988 {
24989 { 0, 0, 0, 0 },
24990 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
24991 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b50000 }
24992 },
24993/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
24994 {
24995 { 0, 0, 0, 0 },
24996 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
24997 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c50000 }
24998 },
24999/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
25000 {
25001 { 0, 0, 0, 0 },
25002 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25003 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e50000 }
25004 },
25005/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
25006 {
25007 { 0, 0, 0, 0 },
25008 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25009 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f50000 }
25010 },
25011/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
25012 {
25013 { 0, 0, 0, 0 },
25014 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25015 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f50000 }
25016 },
25017/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
25018 {
25019 { 0, 0, 0, 0 },
25020 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25021 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c50000 }
25022 },
25023/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
25024 {
25025 { 0, 0, 0, 0 },
25026 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25027 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e50000 }
25028 },
25029/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
25030 {
25031 { 0, 0, 0, 0 },
25032 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25033 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f50000 }
25034 },
25035/* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
25036 {
25037 { 0, 0, 0, 0 },
25038 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25039 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f50000 }
25040 },
25041/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
25042 {
25043 { 0, 0, 0, 0 },
25044 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
25045 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c50000 }
25046 },
25047/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
25048 {
25049 { 0, 0, 0, 0 },
25050 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25051 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e50000 }
25052 },
25053/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
25054 {
25055 { 0, 0, 0, 0 },
25056 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25057 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f50000 }
25058 },
25059/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
25060 {
25061 { 0, 0, 0, 0 },
25062 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
25063 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f50000 }
25064 },
25065/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
25066 {
25067 { 0, 0, 0, 0 },
25068 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
25069 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7850000 }
25070 },
25071/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
25072 {
25073 { 0, 0, 0, 0 },
25074 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25075 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a50000 }
25076 },
25077/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
25078 {
25079 { 0, 0, 0, 0 },
25080 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25081 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b50000 }
25082 },
25083/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
25084 {
25085 { 0, 0, 0, 0 },
25086 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
25087 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b50000 }
25088 },
25089/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25090 {
25091 { 0, 0, 0, 0 },
25092 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25093 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9050000 }
25094 },
25095/* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
25096 {
25097 { 0, 0, 0, 0 },
25098 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25099 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9250000 }
25100 },
25101/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25102 {
25103 { 0, 0, 0, 0 },
25104 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25105 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1850000 }
25106 },
25107/* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
25108 {
25109 { 0, 0, 0, 0 },
25110 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25111 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a50000 }
25112 },
25113/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25114 {
25115 { 0, 0, 0, 0 },
25116 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25117 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1050000 }
25118 },
25119/* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
25120 {
25121 { 0, 0, 0, 0 },
25122 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25123 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1250000 }
25124 },
25125/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
25126 {
25127 { 0, 0, 0, 0 },
25128 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25129 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3050000 }
25130 },
25131/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
25132 {
25133 { 0, 0, 0, 0 },
25134 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25135 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3250000 }
25136 },
25137/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
25138 {
25139 { 0, 0, 0, 0 },
25140 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25141 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5050000 }
25142 },
25143/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
25144 {
25145 { 0, 0, 0, 0 },
25146 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25147 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5250000 }
25148 },
25149/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
25150 {
25151 { 0, 0, 0, 0 },
25152 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25153 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7050000 }
25154 },
25155/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
25156 {
25157 { 0, 0, 0, 0 },
25158 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25159 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7250000 }
25160 },
25161/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
25162 {
25163 { 0, 0, 0, 0 },
25164 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
25165 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3850000 }
25166 },
25167/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
25168 {
25169 { 0, 0, 0, 0 },
25170 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
25171 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a50000 }
25172 },
25173/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
25174 {
25175 { 0, 0, 0, 0 },
25176 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
25177 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5850000 }
25178 },
25179/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
25180 {
25181 { 0, 0, 0, 0 },
25182 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
25183 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a50000 }
25184 },
25185/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
25186 {
25187 { 0, 0, 0, 0 },
25188 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
25189 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c50000 }
25190 },
25191/* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
25192 {
25193 { 0, 0, 0, 0 },
25194 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
25195 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e50000 }
25196 },
25197/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
25198 {
25199 { 0, 0, 0, 0 },
25200 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
25201 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c50000 }
25202 },
25203/* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
25204 {
25205 { 0, 0, 0, 0 },
25206 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
25207 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e50000 }
25208 },
25209/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
25210 {
25211 { 0, 0, 0, 0 },
25212 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
25213 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c50000 }
25214 },
25215/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
25216 {
25217 { 0, 0, 0, 0 },
25218 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
25219 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e50000 }
25220 },
25221/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
25222 {
25223 { 0, 0, 0, 0 },
25224 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
25225 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7850000 }
25226 },
25227/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
25228 {
25229 { 0, 0, 0, 0 },
25230 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
25231 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a50000 }
25232 },
25233/* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
25234 {
25235 { 0, 0, 0, 0 },
25236 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25237 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc905 }
25238 },
25239/* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
25240 {
25241 { 0, 0, 0, 0 },
25242 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25243 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8925 }
25244 },
25245/* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25246 {
25247 { 0, 0, 0, 0 },
25248 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25249 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8905 }
25250 },
25251/* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
25252 {
25253 { 0, 0, 0, 0 },
25254 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25255 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc185 }
25256 },
25257/* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
25258 {
25259 { 0, 0, 0, 0 },
25260 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25261 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a5 }
25262 },
25263/* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25264 {
25265 { 0, 0, 0, 0 },
25266 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25267 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8185 }
25268 },
25269/* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
25270 {
25271 { 0, 0, 0, 0 },
25272 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25273 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc105 }
25274 },
25275/* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
25276 {
25277 { 0, 0, 0, 0 },
25278 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25279 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8125 }
25280 },
25281/* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25282 {
25283 { 0, 0, 0, 0 },
25284 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25285 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8105 }
25286 },
25287/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
25288 {
25289 { 0, 0, 0, 0 },
25290 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25291 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30500 }
25292 },
25293/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
25294 {
25295 { 0, 0, 0, 0 },
25296 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25297 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832500 }
25298 },
25299/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
25300 {
25301 { 0, 0, 0, 0 },
25302 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25303 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830500 }
25304 },
25305/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
25306 {
25307 { 0, 0, 0, 0 },
25308 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25309 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5050000 }
25310 },
25311/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
25312 {
25313 { 0, 0, 0, 0 },
25314 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25315 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85250000 }
25316 },
25317/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
25318 {
25319 { 0, 0, 0, 0 },
25320 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25321 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85050000 }
25322 },
25323/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
25324 {
25325 { 0, 0, 0, 0 },
25326 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25327 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7050000 }
25328 },
25329/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
25330 {
25331 { 0, 0, 0, 0 },
25332 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25333 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87250000 }
25334 },
25335/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
25336 {
25337 { 0, 0, 0, 0 },
25338 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25339 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87050000 }
25340 },
25341/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
25342 {
25343 { 0, 0, 0, 0 },
25344 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25345 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38500 }
25346 },
25347/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
25348 {
25349 { 0, 0, 0, 0 },
25350 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25351 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a500 }
25352 },
25353/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
25354 {
25355 { 0, 0, 0, 0 },
25356 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25357 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838500 }
25358 },
25359/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
25360 {
25361 { 0, 0, 0, 0 },
25362 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25363 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5850000 }
25364 },
25365/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
25366 {
25367 { 0, 0, 0, 0 },
25368 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25369 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a50000 }
25370 },
25371/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
25372 {
25373 { 0, 0, 0, 0 },
25374 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25375 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85850000 }
25376 },
25377/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
25378 {
25379 { 0, 0, 0, 0 },
25380 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25381 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c500 }
25382 },
25383/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
25384 {
25385 { 0, 0, 0, 0 },
25386 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25387 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e500 }
25388 },
25389/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
25390 {
25391 { 0, 0, 0, 0 },
25392 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25393 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c500 }
25394 },
25395/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
25396 {
25397 { 0, 0, 0, 0 },
25398 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25399 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c50000 }
25400 },
25401/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
25402 {
25403 { 0, 0, 0, 0 },
25404 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25405 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e50000 }
25406 },
25407/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
25408 {
25409 { 0, 0, 0, 0 },
25410 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25411 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c50000 }
25412 },
25413/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
25414 {
25415 { 0, 0, 0, 0 },
25416 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
25417 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c50000 }
25418 },
25419/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
25420 {
25421 { 0, 0, 0, 0 },
25422 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
25423 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e50000 }
25424 },
25425/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
25426 {
25427 { 0, 0, 0, 0 },
25428 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
25429 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c50000 }
25430 },
25431/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
25432 {
25433 { 0, 0, 0, 0 },
25434 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
25435 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7850000 }
25436 },
25437/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
25438 {
25439 { 0, 0, 0, 0 },
25440 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
25441 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a50000 }
25442 },
25443/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
25444 {
25445 { 0, 0, 0, 0 },
25446 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
25447 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87850000 }
25448 },
25449/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
25450 {
25451 { 0, 0, 0, 0 },
25452 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25453 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980500 }
25454 },
25455/* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
25456 {
25457 { 0, 0, 0, 0 },
25458 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25459 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982500 }
25460 },
25461/* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
25462 {
25463 { 0, 0, 0, 0 },
25464 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25465 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983500 }
25466 },
25467/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
25468 {
25469 { 0, 0, 0, 0 },
25470 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25471 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908500 }
25472 },
25473/* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
25474 {
25475 { 0, 0, 0, 0 },
25476 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25477 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a500 }
25478 },
25479/* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
25480 {
25481 { 0, 0, 0, 0 },
25482 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25483 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b500 }
25484 },
25485/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25486 {
25487 { 0, 0, 0, 0 },
25488 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25489 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900500 }
25490 },
25491/* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
25492 {
25493 { 0, 0, 0, 0 },
25494 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25495 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902500 }
25496 },
25497/* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
25498 {
25499 { 0, 0, 0, 0 },
25500 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25501 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903500 }
25502 },
25503/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25504 {
25505 { 0, 0, 0, 0 },
25506 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25507 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92050000 }
25508 },
25509/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25510 {
25511 { 0, 0, 0, 0 },
25512 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25513 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92250000 }
25514 },
25515/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25516 {
25517 { 0, 0, 0, 0 },
25518 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25519 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92350000 }
25520 },
25521/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25522 {
25523 { 0, 0, 0, 0 },
25524 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25525 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94050000 }
25526 },
25527/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25528 {
25529 { 0, 0, 0, 0 },
25530 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25531 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94250000 }
25532 },
25533/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25534 {
25535 { 0, 0, 0, 0 },
25536 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25537 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94350000 }
25538 },
25539/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25540 {
25541 { 0, 0, 0, 0 },
25542 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25543 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96050000 }
25544 },
25545/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25546 {
25547 { 0, 0, 0, 0 },
25548 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25549 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96250000 }
25550 },
25551/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25552 {
25553 { 0, 0, 0, 0 },
25554 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25555 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96350000 }
25556 },
25557/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
25558 {
25559 { 0, 0, 0, 0 },
25560 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25561 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92850000 }
25562 },
25563/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
25564 {
25565 { 0, 0, 0, 0 },
25566 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25567 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a50000 }
25568 },
25569/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
25570 {
25571 { 0, 0, 0, 0 },
25572 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25573 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b50000 }
25574 },
25575/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
25576 {
25577 { 0, 0, 0, 0 },
25578 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25579 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94850000 }
25580 },
25581/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
25582 {
25583 { 0, 0, 0, 0 },
25584 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25585 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a50000 }
25586 },
25587/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
25588 {
25589 { 0, 0, 0, 0 },
25590 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25591 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b50000 }
25592 },
25593/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
25594 {
25595 { 0, 0, 0, 0 },
25596 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25597 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c50000 }
25598 },
25599/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
25600 {
25601 { 0, 0, 0, 0 },
25602 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25603 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e50000 }
25604 },
25605/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
25606 {
25607 { 0, 0, 0, 0 },
25608 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25609 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f50000 }
25610 },
25611/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
25612 {
25613 { 0, 0, 0, 0 },
25614 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25615 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c50000 }
25616 },
25617/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
25618 {
25619 { 0, 0, 0, 0 },
25620 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25621 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e50000 }
25622 },
25623/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
25624 {
25625 { 0, 0, 0, 0 },
25626 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25627 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f50000 }
25628 },
25629/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
25630 {
25631 { 0, 0, 0, 0 },
25632 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
25633 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c50000 }
25634 },
25635/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
25636 {
25637 { 0, 0, 0, 0 },
25638 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
25639 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e50000 }
25640 },
25641/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
25642 {
25643 { 0, 0, 0, 0 },
25644 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
25645 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f50000 }
25646 },
25647/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
25648 {
25649 { 0, 0, 0, 0 },
25650 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
25651 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96850000 }
25652 },
25653/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
25654 {
25655 { 0, 0, 0, 0 },
25656 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25657 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a50000 }
25658 },
25659/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
25660 {
25661 { 0, 0, 0, 0 },
25662 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25663 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b50000 }
25664 },
25665/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
25666 {
25667 { 0, 0, 0, 0 },
25668 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25669 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8050000 }
25670 },
25671/* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
25672 {
25673 { 0, 0, 0, 0 },
25674 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25675 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8250000 }
25676 },
25677/* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
25678 {
25679 { 0, 0, 0, 0 },
25680 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25681 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8350000 }
25682 },
25683/* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
25684 {
25685 { 0, 0, 0, 0 },
25686 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25687 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8350000 }
25688 },
25689/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
25690 {
25691 { 0, 0, 0, 0 },
25692 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25693 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0850000 }
25694 },
25695/* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
25696 {
25697 { 0, 0, 0, 0 },
25698 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25699 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a50000 }
25700 },
25701/* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
25702 {
25703 { 0, 0, 0, 0 },
25704 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25705 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b50000 }
25706 },
25707/* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
25708 {
25709 { 0, 0, 0, 0 },
25710 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25711 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b50000 }
25712 },
25713/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25714 {
25715 { 0, 0, 0, 0 },
25716 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25717 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0050000 }
25718 },
25719/* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
25720 {
25721 { 0, 0, 0, 0 },
25722 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25723 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0250000 }
25724 },
25725/* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
25726 {
25727 { 0, 0, 0, 0 },
25728 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25729 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0350000 }
25730 },
25731/* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
25732 {
25733 { 0, 0, 0, 0 },
25734 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25735 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0350000 }
25736 },
25737/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25738 {
25739 { 0, 0, 0, 0 },
25740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25741 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2050000 }
25742 },
25743/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25744 {
25745 { 0, 0, 0, 0 },
25746 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25747 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2250000 }
25748 },
25749/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25750 {
25751 { 0, 0, 0, 0 },
25752 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25753 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2350000 }
25754 },
25755/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
25756 {
25757 { 0, 0, 0, 0 },
25758 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25759 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2350000 }
25760 },
25761/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25762 {
25763 { 0, 0, 0, 0 },
25764 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25765 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4050000 }
25766 },
25767/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25768 {
25769 { 0, 0, 0, 0 },
25770 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25771 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4250000 }
25772 },
25773/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25774 {
25775 { 0, 0, 0, 0 },
25776 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25777 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4350000 }
25778 },
25779/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
25780 {
25781 { 0, 0, 0, 0 },
25782 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25783 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4350000 }
25784 },
25785/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25786 {
25787 { 0, 0, 0, 0 },
25788 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25789 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6050000 }
25790 },
25791/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25792 {
25793 { 0, 0, 0, 0 },
25794 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25795 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6250000 }
25796 },
25797/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25798 {
25799 { 0, 0, 0, 0 },
25800 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25801 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6350000 }
25802 },
25803/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
25804 {
25805 { 0, 0, 0, 0 },
25806 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25807 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6350000 }
25808 },
25809/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
25810 {
25811 { 0, 0, 0, 0 },
25812 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25813 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2850000 }
25814 },
25815/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
25816 {
25817 { 0, 0, 0, 0 },
25818 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25819 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a50000 }
25820 },
25821/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
25822 {
25823 { 0, 0, 0, 0 },
25824 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25825 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b50000 }
25826 },
25827/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
25828 {
25829 { 0, 0, 0, 0 },
25830 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25831 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b50000 }
25832 },
25833/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
25834 {
25835 { 0, 0, 0, 0 },
25836 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25837 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4850000 }
25838 },
25839/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
25840 {
25841 { 0, 0, 0, 0 },
25842 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25843 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a50000 }
25844 },
25845/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
25846 {
25847 { 0, 0, 0, 0 },
25848 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25849 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b50000 }
25850 },
25851/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
25852 {
25853 { 0, 0, 0, 0 },
25854 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25855 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b50000 }
25856 },
25857/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
25858 {
25859 { 0, 0, 0, 0 },
25860 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25861 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c50000 }
25862 },
25863/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
25864 {
25865 { 0, 0, 0, 0 },
25866 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25867 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e50000 }
25868 },
25869/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
25870 {
25871 { 0, 0, 0, 0 },
25872 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25873 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f50000 }
25874 },
25875/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
25876 {
25877 { 0, 0, 0, 0 },
25878 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25879 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f50000 }
25880 },
25881/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
25882 {
25883 { 0, 0, 0, 0 },
25884 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25885 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c50000 }
25886 },
25887/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
25888 {
25889 { 0, 0, 0, 0 },
25890 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25891 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e50000 }
25892 },
25893/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
25894 {
25895 { 0, 0, 0, 0 },
25896 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25897 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f50000 }
25898 },
25899/* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
25900 {
25901 { 0, 0, 0, 0 },
25902 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25903 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f50000 }
25904 },
25905/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
25906 {
25907 { 0, 0, 0, 0 },
25908 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
25909 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c50000 }
25910 },
25911/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
25912 {
25913 { 0, 0, 0, 0 },
25914 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25915 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e50000 }
25916 },
25917/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
25918 {
25919 { 0, 0, 0, 0 },
25920 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25921 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f50000 }
25922 },
25923/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
25924 {
25925 { 0, 0, 0, 0 },
25926 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
25927 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f50000 }
25928 },
25929/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
25930 {
25931 { 0, 0, 0, 0 },
25932 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
25933 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6850000 }
25934 },
25935/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
25936 {
25937 { 0, 0, 0, 0 },
25938 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25939 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a50000 }
25940 },
25941/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
25942 {
25943 { 0, 0, 0, 0 },
25944 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25945 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b50000 }
25946 },
25947/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
25948 {
25949 { 0, 0, 0, 0 },
25950 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
25951 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b50000 }
25952 },
25953/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
25954 {
25955 { 0, 0, 0, 0 },
25956 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25957 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8050000 }
25958 },
25959/* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
25960 {
25961 { 0, 0, 0, 0 },
25962 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25963 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8250000 }
25964 },
25965/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
25966 {
25967 { 0, 0, 0, 0 },
25968 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25969 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0850000 }
25970 },
25971/* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
25972 {
25973 { 0, 0, 0, 0 },
25974 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25975 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a50000 }
25976 },
25977/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25978 {
25979 { 0, 0, 0, 0 },
25980 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25981 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0050000 }
25982 },
25983/* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
25984 {
25985 { 0, 0, 0, 0 },
25986 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25987 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0250000 }
25988 },
25989/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
25990 {
25991 { 0, 0, 0, 0 },
25992 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25993 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2050000 }
25994 },
25995/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
25996 {
25997 { 0, 0, 0, 0 },
25998 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25999 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2250000 }
26000 },
26001/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
26002 {
26003 { 0, 0, 0, 0 },
26004 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26005 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4050000 }
26006 },
26007/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
26008 {
26009 { 0, 0, 0, 0 },
26010 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26011 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4250000 }
26012 },
26013/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
26014 {
26015 { 0, 0, 0, 0 },
26016 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26017 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6050000 }
26018 },
26019/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
26020 {
26021 { 0, 0, 0, 0 },
26022 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26023 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6250000 }
26024 },
26025/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
26026 {
26027 { 0, 0, 0, 0 },
26028 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
26029 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2850000 }
26030 },
26031/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
26032 {
26033 { 0, 0, 0, 0 },
26034 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
26035 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a50000 }
26036 },
26037/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
26038 {
26039 { 0, 0, 0, 0 },
26040 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
26041 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4850000 }
26042 },
26043/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
26044 {
26045 { 0, 0, 0, 0 },
26046 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
26047 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a50000 }
26048 },
26049/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
26050 {
26051 { 0, 0, 0, 0 },
26052 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
26053 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c50000 }
26054 },
26055/* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
26056 {
26057 { 0, 0, 0, 0 },
26058 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
26059 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e50000 }
26060 },
26061/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
26062 {
26063 { 0, 0, 0, 0 },
26064 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
26065 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c50000 }
26066 },
26067/* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
26068 {
26069 { 0, 0, 0, 0 },
26070 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
26071 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e50000 }
26072 },
26073/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
26074 {
26075 { 0, 0, 0, 0 },
26076 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
26077 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c50000 }
26078 },
26079/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
26080 {
26081 { 0, 0, 0, 0 },
26082 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
26083 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e50000 }
26084 },
26085/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
26086 {
26087 { 0, 0, 0, 0 },
26088 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
26089 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6850000 }
26090 },
26091/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
26092 {
26093 { 0, 0, 0, 0 },
26094 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
26095 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a50000 }
26096 },
26097/* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
26098 {
26099 { 0, 0, 0, 0 },
26100 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26101 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc805 }
26102 },
26103/* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
26104 {
26105 { 0, 0, 0, 0 },
26106 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26107 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8825 }
26108 },
26109/* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
26110 {
26111 { 0, 0, 0, 0 },
26112 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26113 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8805 }
26114 },
26115/* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
26116 {
26117 { 0, 0, 0, 0 },
26118 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26119 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc085 }
26120 },
26121/* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
26122 {
26123 { 0, 0, 0, 0 },
26124 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26125 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a5 }
26126 },
26127/* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
26128 {
26129 { 0, 0, 0, 0 },
26130 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26131 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8085 }
26132 },
26133/* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
26134 {
26135 { 0, 0, 0, 0 },
26136 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26137 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc005 }
26138 },
26139/* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
26140 {
26141 { 0, 0, 0, 0 },
26142 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26143 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8025 }
26144 },
26145/* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26146 {
26147 { 0, 0, 0, 0 },
26148 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26149 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8005 }
26150 },
26151/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
26152 {
26153 { 0, 0, 0, 0 },
26154 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26155 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20500 }
26156 },
26157/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
26158 {
26159 { 0, 0, 0, 0 },
26160 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26161 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822500 }
26162 },
26163/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26164 {
26165 { 0, 0, 0, 0 },
26166 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26167 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820500 }
26168 },
26169/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
26170 {
26171 { 0, 0, 0, 0 },
26172 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26173 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4050000 }
26174 },
26175/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
26176 {
26177 { 0, 0, 0, 0 },
26178 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26179 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84250000 }
26180 },
26181/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26182 {
26183 { 0, 0, 0, 0 },
26184 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26185 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84050000 }
26186 },
26187/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
26188 {
26189 { 0, 0, 0, 0 },
26190 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26191 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6050000 }
26192 },
26193/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
26194 {
26195 { 0, 0, 0, 0 },
26196 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26197 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86250000 }
26198 },
26199/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26200 {
26201 { 0, 0, 0, 0 },
26202 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26203 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86050000 }
26204 },
26205/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
26206 {
26207 { 0, 0, 0, 0 },
26208 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26209 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28500 }
26210 },
26211/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
26212 {
26213 { 0, 0, 0, 0 },
26214 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26215 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a500 }
26216 },
26217/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
26218 {
26219 { 0, 0, 0, 0 },
26220 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26221 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828500 }
26222 },
26223/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
26224 {
26225 { 0, 0, 0, 0 },
26226 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26227 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4850000 }
26228 },
26229/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
26230 {
26231 { 0, 0, 0, 0 },
26232 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26233 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a50000 }
26234 },
26235/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
26236 {
26237 { 0, 0, 0, 0 },
26238 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26239 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84850000 }
26240 },
26241/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
26242 {
26243 { 0, 0, 0, 0 },
26244 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26245 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c500 }
26246 },
26247/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
26248 {
26249 { 0, 0, 0, 0 },
26250 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26251 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e500 }
26252 },
26253/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
26254 {
26255 { 0, 0, 0, 0 },
26256 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26257 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c500 }
26258 },
26259/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
26260 {
26261 { 0, 0, 0, 0 },
26262 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26263 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c50000 }
26264 },
26265/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
26266 {
26267 { 0, 0, 0, 0 },
26268 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26269 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e50000 }
26270 },
26271/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
26272 {
26273 { 0, 0, 0, 0 },
26274 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26275 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c50000 }
26276 },
26277/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
26278 {
26279 { 0, 0, 0, 0 },
26280 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
26281 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c50000 }
26282 },
26283/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
26284 {
26285 { 0, 0, 0, 0 },
26286 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
26287 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e50000 }
26288 },
26289/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
26290 {
26291 { 0, 0, 0, 0 },
26292 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
26293 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c50000 }
26294 },
26295/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
26296 {
26297 { 0, 0, 0, 0 },
26298 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
26299 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6850000 }
26300 },
26301/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
26302 {
26303 { 0, 0, 0, 0 },
26304 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
26305 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a50000 }
26306 },
26307/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
26308 {
26309 { 0, 0, 0, 0 },
26310 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
26311 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86850000 }
26312 },
26313/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
26314 {
26315 { 0, 0, 0, 0 },
26316 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26317 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x998000 }
26318 },
26319/* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
26320 {
26321 { 0, 0, 0, 0 },
26322 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
26323 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x99a000 }
26324 },
26325/* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
26326 {
26327 { 0, 0, 0, 0 },
26328 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
26329 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x99b000 }
26330 },
26331/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
26332 {
26333 { 0, 0, 0, 0 },
26334 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26335 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x998400 }
26336 },
26337/* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
26338 {
26339 { 0, 0, 0, 0 },
26340 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
26341 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x99a400 }
26342 },
26343/* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
26344 {
26345 { 0, 0, 0, 0 },
26346 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
26347 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x99b400 }
26348 },
26349/* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
26350 {
26351 { 0, 0, 0, 0 },
26352 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26353 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x998600 }
26354 },
26355/* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
26356 {
26357 { 0, 0, 0, 0 },
26358 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26359 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x99a600 }
26360 },
26361/* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
26362 {
26363 { 0, 0, 0, 0 },
26364 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26365 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x99b600 }
26366 },
26367/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
26368 {
26369 { 0, 0, 0, 0 },
26370 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26371 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x99880000 }
26372 },
26373/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
26374 {
26375 { 0, 0, 0, 0 },
26376 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26377 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x99a80000 }
26378 },
26379/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
26380 {
26381 { 0, 0, 0, 0 },
26382 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26383 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x99b80000 }
26384 },
26385/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
26386 {
26387 { 0, 0, 0, 0 },
26388 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26389 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x998c0000 }
26390 },
26391/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
26392 {
26393 { 0, 0, 0, 0 },
26394 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26395 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x99ac0000 }
26396 },
26397/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
26398 {
26399 { 0, 0, 0, 0 },
26400 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26401 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x99bc0000 }
26402 },
26403/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
26404 {
26405 { 0, 0, 0, 0 },
26406 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26407 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x998a0000 }
26408 },
26409/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26410 {
26411 { 0, 0, 0, 0 },
26412 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26413 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99aa0000 }
26414 },
26415/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26416 {
26417 { 0, 0, 0, 0 },
26418 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26419 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99ba0000 }
26420 },
26421/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
26422 {
26423 { 0, 0, 0, 0 },
26424 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26425 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x998e0000 }
26426 },
26427/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26428 {
26429 { 0, 0, 0, 0 },
26430 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26431 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99ae0000 }
26432 },
26433/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26434 {
26435 { 0, 0, 0, 0 },
26436 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26437 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99be0000 }
26438 },
26439/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
26440 {
26441 { 0, 0, 0, 0 },
26442 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26443 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x998b0000 }
26444 },
26445/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26446 {
26447 { 0, 0, 0, 0 },
26448 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26449 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99ab0000 }
26450 },
26451/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26452 {
26453 { 0, 0, 0, 0 },
26454 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26455 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99bb0000 }
26456 },
26457/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
26458 {
26459 { 0, 0, 0, 0 },
26460 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
26461 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x998f0000 }
26462 },
26463/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26464 {
26465 { 0, 0, 0, 0 },
26466 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26467 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x99af0000 }
26468 },
26469/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26470 {
26471 { 0, 0, 0, 0 },
26472 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26473 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x99bf0000 }
26474 },
26475/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
26476 {
26477 { 0, 0, 0, 0 },
26478 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26479 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x99c00000 }
26480 },
26481/* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
26482 {
26483 { 0, 0, 0, 0 },
26484 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
26485 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x99e00000 }
26486 },
26487/* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
26488 {
26489 { 0, 0, 0, 0 },
26490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
26491 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x99f00000 }
26492 },
26493/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
26494 {
26495 { 0, 0, 0, 0 },
26496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26497 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x99c40000 }
26498 },
26499/* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
26500 {
26501 { 0, 0, 0, 0 },
26502 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
26503 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x99e40000 }
26504 },
26505/* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
26506 {
26507 { 0, 0, 0, 0 },
26508 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
26509 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x99f40000 }
26510 },
26511/* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
26512 {
26513 { 0, 0, 0, 0 },
26514 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26515 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x99c60000 }
26516 },
26517/* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
26518 {
26519 { 0, 0, 0, 0 },
26520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26521 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x99e60000 }
26522 },
26523/* or.w${G} ${Dsp-16-u16},[$Dst16An] */
26524 {
26525 { 0, 0, 0, 0 },
26526 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
26527 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x99f60000 }
26528 },
26529/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
26530 {
26531 { 0, 0, 0, 0 },
26532 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26533 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x99c80000 }
26534 },
26535/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
26536 {
26537 { 0, 0, 0, 0 },
26538 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26539 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x99e80000 }
26540 },
26541/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
26542 {
26543 { 0, 0, 0, 0 },
26544 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26545 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x99f80000 }
26546 },
26547/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
26548 {
26549 { 0, 0, 0, 0 },
26550 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26551 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x99cc0000 }
26552 },
26553/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
26554 {
26555 { 0, 0, 0, 0 },
26556 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26557 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x99ec0000 }
26558 },
26559/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
26560 {
26561 { 0, 0, 0, 0 },
26562 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26563 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x99fc0000 }
26564 },
26565/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
26566 {
26567 { 0, 0, 0, 0 },
26568 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26569 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ca0000 }
26570 },
26571/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26572 {
26573 { 0, 0, 0, 0 },
26574 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26575 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ea0000 }
26576 },
26577/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26578 {
26579 { 0, 0, 0, 0 },
26580 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26581 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x99fa0000 }
26582 },
26583/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
26584 {
26585 { 0, 0, 0, 0 },
26586 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26587 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ce0000 }
26588 },
26589/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26590 {
26591 { 0, 0, 0, 0 },
26592 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26593 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ee0000 }
26594 },
26595/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26596 {
26597 { 0, 0, 0, 0 },
26598 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26599 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x99fe0000 }
26600 },
26601/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
26602 {
26603 { 0, 0, 0, 0 },
26604 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26605 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x99cb0000 }
26606 },
26607/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26608 {
26609 { 0, 0, 0, 0 },
26610 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26611 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x99eb0000 }
26612 },
26613/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26614 {
26615 { 0, 0, 0, 0 },
26616 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26617 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x99fb0000 }
26618 },
26619/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
26620 {
26621 { 0, 0, 0, 0 },
26622 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
26623 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x99cf0000 }
26624 },
26625/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26626 {
26627 { 0, 0, 0, 0 },
26628 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
26629 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x99ef0000 }
26630 },
26631/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
26632 {
26633 { 0, 0, 0, 0 },
26634 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
26635 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x99ff0000 }
26636 },
26637/* or.w${G} $Src16RnHI,$Dst16RnHI */
26638 {
26639 { 0, 0, 0, 0 },
26640 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
26641 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9900 }
26642 },
26643/* or.w${G} $Src16AnHI,$Dst16RnHI */
26644 {
26645 { 0, 0, 0, 0 },
26646 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
26647 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9940 }
26648 },
26649/* or.w${G} [$Src16An],$Dst16RnHI */
26650 {
26651 { 0, 0, 0, 0 },
26652 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26653 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9960 }
26654 },
26655/* or.w${G} $Src16RnHI,$Dst16AnHI */
26656 {
26657 { 0, 0, 0, 0 },
26658 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
26659 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9904 }
26660 },
26661/* or.w${G} $Src16AnHI,$Dst16AnHI */
26662 {
26663 { 0, 0, 0, 0 },
26664 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
26665 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9944 }
26666 },
26667/* or.w${G} [$Src16An],$Dst16AnHI */
26668 {
26669 { 0, 0, 0, 0 },
26670 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26671 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9964 }
26672 },
26673/* or.w${G} $Src16RnHI,[$Dst16An] */
26674 {
26675 { 0, 0, 0, 0 },
26676 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
26677 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9906 }
26678 },
26679/* or.w${G} $Src16AnHI,[$Dst16An] */
26680 {
26681 { 0, 0, 0, 0 },
26682 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
26683 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9946 }
26684 },
26685/* or.w${G} [$Src16An],[$Dst16An] */
26686 {
26687 { 0, 0, 0, 0 },
26688 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26689 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9966 }
26690 },
26691/* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
26692 {
26693 { 0, 0, 0, 0 },
26694 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26695 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x990800 }
26696 },
26697/* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
26698 {
26699 { 0, 0, 0, 0 },
26700 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26701 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x994800 }
26702 },
26703/* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
26704 {
26705 { 0, 0, 0, 0 },
26706 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26707 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x996800 }
26708 },
26709/* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
26710 {
26711 { 0, 0, 0, 0 },
26712 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26713 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x990c0000 }
26714 },
26715/* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
26716 {
26717 { 0, 0, 0, 0 },
26718 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26719 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x994c0000 }
26720 },
26721/* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
26722 {
26723 { 0, 0, 0, 0 },
26724 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26725 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x996c0000 }
26726 },
26727/* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
26728 {
26729 { 0, 0, 0, 0 },
26730 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26731 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x990a00 }
26732 },
26733/* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
26734 {
26735 { 0, 0, 0, 0 },
26736 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26737 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x994a00 }
26738 },
26739/* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
26740 {
26741 { 0, 0, 0, 0 },
26742 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26743 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x996a00 }
26744 },
26745/* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
26746 {
26747 { 0, 0, 0, 0 },
26748 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26749 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x990e0000 }
26750 },
26751/* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
26752 {
26753 { 0, 0, 0, 0 },
26754 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26755 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x994e0000 }
26756 },
26757/* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
26758 {
26759 { 0, 0, 0, 0 },
26760 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26761 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x996e0000 }
26762 },
26763/* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
26764 {
26765 { 0, 0, 0, 0 },
26766 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26767 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x990b00 }
26768 },
26769/* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
26770 {
26771 { 0, 0, 0, 0 },
26772 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26773 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x994b00 }
26774 },
26775/* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
26776 {
26777 { 0, 0, 0, 0 },
26778 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26779 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x996b00 }
26780 },
26781/* or.w${G} $Src16RnHI,${Dsp-16-u16} */
26782 {
26783 { 0, 0, 0, 0 },
26784 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
26785 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x990f0000 }
26786 },
26787/* or.w${G} $Src16AnHI,${Dsp-16-u16} */
26788 {
26789 { 0, 0, 0, 0 },
26790 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
26791 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x994f0000 }
26792 },
26793/* or.w${G} [$Src16An],${Dsp-16-u16} */
26794 {
26795 { 0, 0, 0, 0 },
26796 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
26797 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x996f0000 }
26798 },
26799/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
26800 {
26801 { 0, 0, 0, 0 },
26802 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
26803 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x988000 }
26804 },
26805/* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
26806 {
26807 { 0, 0, 0, 0 },
26808 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
26809 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x98a000 }
26810 },
26811/* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
26812 {
26813 { 0, 0, 0, 0 },
26814 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
26815 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x98b000 }
26816 },
26817/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
26818 {
26819 { 0, 0, 0, 0 },
26820 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
26821 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x988400 }
26822 },
26823/* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
26824 {
26825 { 0, 0, 0, 0 },
26826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
26827 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x98a400 }
26828 },
26829/* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
26830 {
26831 { 0, 0, 0, 0 },
26832 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
26833 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x98b400 }
26834 },
26835/* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
26836 {
26837 { 0, 0, 0, 0 },
26838 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26839 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x988600 }
26840 },
26841/* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
26842 {
26843 { 0, 0, 0, 0 },
26844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26845 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x98a600 }
26846 },
26847/* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
26848 {
26849 { 0, 0, 0, 0 },
26850 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26851 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x98b600 }
26852 },
26853/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
26854 {
26855 { 0, 0, 0, 0 },
26856 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26857 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x98880000 }
26858 },
26859/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
26860 {
26861 { 0, 0, 0, 0 },
26862 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26863 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x98a80000 }
26864 },
26865/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
26866 {
26867 { 0, 0, 0, 0 },
26868 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26869 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x98b80000 }
26870 },
26871/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
26872 {
26873 { 0, 0, 0, 0 },
26874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26875 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x988c0000 }
26876 },
26877/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
26878 {
26879 { 0, 0, 0, 0 },
26880 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26881 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x98ac0000 }
26882 },
26883/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
26884 {
26885 { 0, 0, 0, 0 },
26886 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26887 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x98bc0000 }
26888 },
26889/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
26890 {
26891 { 0, 0, 0, 0 },
26892 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26893 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x988a0000 }
26894 },
26895/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26896 {
26897 { 0, 0, 0, 0 },
26898 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26899 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98aa0000 }
26900 },
26901/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26902 {
26903 { 0, 0, 0, 0 },
26904 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26905 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98ba0000 }
26906 },
26907/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
26908 {
26909 { 0, 0, 0, 0 },
26910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26911 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x988e0000 }
26912 },
26913/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26914 {
26915 { 0, 0, 0, 0 },
26916 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26917 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98ae0000 }
26918 },
26919/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26920 {
26921 { 0, 0, 0, 0 },
26922 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26923 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98be0000 }
26924 },
26925/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
26926 {
26927 { 0, 0, 0, 0 },
26928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26929 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x988b0000 }
26930 },
26931/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26932 {
26933 { 0, 0, 0, 0 },
26934 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26935 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98ab0000 }
26936 },
26937/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26938 {
26939 { 0, 0, 0, 0 },
26940 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26941 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98bb0000 }
26942 },
26943/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
26944 {
26945 { 0, 0, 0, 0 },
26946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
26947 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x988f0000 }
26948 },
26949/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26950 {
26951 { 0, 0, 0, 0 },
26952 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26953 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x98af0000 }
26954 },
26955/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26956 {
26957 { 0, 0, 0, 0 },
26958 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26959 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x98bf0000 }
26960 },
26961/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
26962 {
26963 { 0, 0, 0, 0 },
26964 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
26965 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x98c00000 }
26966 },
26967/* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
26968 {
26969 { 0, 0, 0, 0 },
26970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
26971 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x98e00000 }
26972 },
26973/* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
26974 {
26975 { 0, 0, 0, 0 },
26976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
26977 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x98f00000 }
26978 },
26979/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
26980 {
26981 { 0, 0, 0, 0 },
26982 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
26983 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x98c40000 }
26984 },
26985/* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
26986 {
26987 { 0, 0, 0, 0 },
26988 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
26989 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x98e40000 }
26990 },
26991/* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
26992 {
26993 { 0, 0, 0, 0 },
26994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
26995 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x98f40000 }
26996 },
26997/* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
26998 {
26999 { 0, 0, 0, 0 },
27000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27001 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x98c60000 }
27002 },
27003/* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
27004 {
27005 { 0, 0, 0, 0 },
27006 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
27007 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x98e60000 }
27008 },
27009/* or.b${G} ${Dsp-16-u16},[$Dst16An] */
27010 {
27011 { 0, 0, 0, 0 },
27012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
27013 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x98f60000 }
27014 },
27015/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
27016 {
27017 { 0, 0, 0, 0 },
27018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27019 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x98c80000 }
27020 },
27021/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
27022 {
27023 { 0, 0, 0, 0 },
27024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27025 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x98e80000 }
27026 },
27027/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
27028 {
27029 { 0, 0, 0, 0 },
27030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27031 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x98f80000 }
27032 },
27033/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
27034 {
27035 { 0, 0, 0, 0 },
27036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27037 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x98cc0000 }
27038 },
27039/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
27040 {
27041 { 0, 0, 0, 0 },
27042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27043 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x98ec0000 }
27044 },
27045/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
27046 {
27047 { 0, 0, 0, 0 },
27048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27049 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x98fc0000 }
27050 },
27051/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
27052 {
27053 { 0, 0, 0, 0 },
27054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27055 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ca0000 }
27056 },
27057/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27058 {
27059 { 0, 0, 0, 0 },
27060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27061 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ea0000 }
27062 },
27063/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27064 {
27065 { 0, 0, 0, 0 },
27066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27067 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x98fa0000 }
27068 },
27069/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
27070 {
27071 { 0, 0, 0, 0 },
27072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27073 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ce0000 }
27074 },
27075/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27076 {
27077 { 0, 0, 0, 0 },
27078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27079 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ee0000 }
27080 },
27081/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27082 {
27083 { 0, 0, 0, 0 },
27084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27085 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x98fe0000 }
27086 },
27087/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
27088 {
27089 { 0, 0, 0, 0 },
27090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27091 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x98cb0000 }
27092 },
27093/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27094 {
27095 { 0, 0, 0, 0 },
27096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27097 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x98eb0000 }
27098 },
27099/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27100 {
27101 { 0, 0, 0, 0 },
27102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27103 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x98fb0000 }
27104 },
27105/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
27106 {
27107 { 0, 0, 0, 0 },
27108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
27109 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x98cf0000 }
27110 },
27111/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27112 {
27113 { 0, 0, 0, 0 },
27114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
27115 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x98ef0000 }
27116 },
27117/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
27118 {
27119 { 0, 0, 0, 0 },
27120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
27121 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x98ff0000 }
27122 },
27123/* or.b${G} $Src16RnQI,$Dst16RnQI */
27124 {
27125 { 0, 0, 0, 0 },
27126 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
27127 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9800 }
27128 },
27129/* or.b${G} $Src16AnQI,$Dst16RnQI */
27130 {
27131 { 0, 0, 0, 0 },
27132 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
27133 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9840 }
27134 },
27135/* or.b${G} [$Src16An],$Dst16RnQI */
27136 {
27137 { 0, 0, 0, 0 },
27138 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
27139 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9860 }
27140 },
27141/* or.b${G} $Src16RnQI,$Dst16AnQI */
27142 {
27143 { 0, 0, 0, 0 },
27144 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
27145 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9804 }
27146 },
27147/* or.b${G} $Src16AnQI,$Dst16AnQI */
27148 {
27149 { 0, 0, 0, 0 },
27150 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
27151 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9844 }
27152 },
27153/* or.b${G} [$Src16An],$Dst16AnQI */
27154 {
27155 { 0, 0, 0, 0 },
27156 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
27157 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9864 }
27158 },
27159/* or.b${G} $Src16RnQI,[$Dst16An] */
27160 {
27161 { 0, 0, 0, 0 },
27162 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
27163 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9806 }
27164 },
27165/* or.b${G} $Src16AnQI,[$Dst16An] */
27166 {
27167 { 0, 0, 0, 0 },
27168 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
27169 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9846 }
27170 },
27171/* or.b${G} [$Src16An],[$Dst16An] */
27172 {
27173 { 0, 0, 0, 0 },
27174 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27175 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9866 }
27176 },
27177/* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
27178 {
27179 { 0, 0, 0, 0 },
27180 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27181 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x980800 }
27182 },
27183/* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
27184 {
27185 { 0, 0, 0, 0 },
27186 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27187 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x984800 }
27188 },
27189/* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
27190 {
27191 { 0, 0, 0, 0 },
27192 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27193 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x986800 }
27194 },
27195/* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
27196 {
27197 { 0, 0, 0, 0 },
27198 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27199 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x980c0000 }
27200 },
27201/* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
27202 {
27203 { 0, 0, 0, 0 },
27204 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27205 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x984c0000 }
27206 },
27207/* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
27208 {
27209 { 0, 0, 0, 0 },
27210 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27211 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x986c0000 }
27212 },
27213/* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
27214 {
27215 { 0, 0, 0, 0 },
27216 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27217 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x980a00 }
27218 },
27219/* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
27220 {
27221 { 0, 0, 0, 0 },
27222 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27223 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x984a00 }
27224 },
27225/* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
27226 {
27227 { 0, 0, 0, 0 },
27228 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27229 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x986a00 }
27230 },
27231/* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
27232 {
27233 { 0, 0, 0, 0 },
27234 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27235 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x980e0000 }
27236 },
27237/* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
27238 {
27239 { 0, 0, 0, 0 },
27240 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27241 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x984e0000 }
27242 },
27243/* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
27244 {
27245 { 0, 0, 0, 0 },
27246 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27247 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x986e0000 }
27248 },
27249/* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
27250 {
27251 { 0, 0, 0, 0 },
27252 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27253 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x980b00 }
27254 },
27255/* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
27256 {
27257 { 0, 0, 0, 0 },
27258 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27259 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x984b00 }
27260 },
27261/* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
27262 {
27263 { 0, 0, 0, 0 },
27264 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27265 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x986b00 }
27266 },
27267/* or.b${G} $Src16RnQI,${Dsp-16-u16} */
27268 {
27269 { 0, 0, 0, 0 },
27270 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
27271 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x980f0000 }
27272 },
27273/* or.b${G} $Src16AnQI,${Dsp-16-u16} */
27274 {
27275 { 0, 0, 0, 0 },
27276 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
27277 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x984f0000 }
27278 },
27279/* or.b${G} [$Src16An],${Dsp-16-u16} */
27280 {
27281 { 0, 0, 0, 0 },
27282 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
27283 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x986f0000 }
27284 },
27285/* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
27286 {
27287 { 0, 0, 0, 0 },
27288 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27289 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x65000000 }
27290 },
27291/* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
27292 {
27293 { 0, 0, 0, 0 },
27294 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27295 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x75000000 }
27296 },
27297/* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
27298 {
27299 { 0, 0, 0, 0 },
27300 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
27301 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x55000000 }
27302 },
27303/* or.w${S} #${Imm-8-HI},r0 */
27304 {
27305 { 0, 0, 0, 0 },
27306 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
27307 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x450000 }
27308 },
27309/* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
27310 {
27311 { 0, 0, 0, 0 },
27312 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27313 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x640000 }
27314 },
27315/* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
27316 {
27317 { 0, 0, 0, 0 },
27318 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27319 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x740000 }
27320 },
27321/* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
27322 {
27323 { 0, 0, 0, 0 },
27324 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
27325 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x54000000 }
27326 },
27327/* or.b${S} #${Imm-8-QI},r0l */
27328 {
27329 { 0, 0, 0, 0 },
27330 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
27331 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4400 }
27332 },
27333/* or.b${S} #${Imm-8-QI},r0l */
27334 {
27335 { 0, 0, 0, 0 },
27336 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
27337 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9c00 }
27338 },
27339/* or.b${S} #${Imm-8-QI},r0h */
27340 {
27341 { 0, 0, 0, 0 },
27342 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
27343 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9b00 }
27344 },
27345/* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
27346 {
27347 { 0, 0, 0, 0 },
27348 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27349 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x9d0000 }
27350 },
27351/* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
27352 {
27353 { 0, 0, 0, 0 },
27354 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27355 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x9e0000 }
27356 },
27357/* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
27358 {
27359 { 0, 0, 0, 0 },
27360 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
27361 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x9f000000 }
27362 },
27363/* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
27364 {
27365 { 0, 0, 0, 0 },
27366 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
27367 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892f0000 }
27368 },
27369/* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
27370 {
27371 { 0, 0, 0, 0 },
27372 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
27373 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81af0000 }
27374 },
27375/* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
27376 {
27377 { 0, 0, 0, 0 },
27378 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27379 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812f0000 }
27380 },
27381/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
27382 {
27383 { 0, 0, 0, 0 },
27384 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27385 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832f0000 }
27386 },
27387/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
27388 {
27389 { 0, 0, 0, 0 },
27390 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27391 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83af0000 }
27392 },
27393/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
27394 {
27395 { 0, 0, 0, 0 },
27396 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27397 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ef0000 }
27398 },
27399/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
27400 {
27401 { 0, 0, 0, 0 },
27402 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27403 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852f0000 }
27404 },
27405/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
27406 {
27407 { 0, 0, 0, 0 },
27408 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27409 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85af0000 }
27410 },
27411/* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
27412 {
27413 { 0, 0, 0, 0 },
27414 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27415 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ef0000 }
27416 },
27417/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
27418 {
27419 { 0, 0, 0, 0 },
27420 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
27421 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ef0000 }
27422 },
27423/* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
27424 {
27425 { 0, 0, 0, 0 },
27426 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27427 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872f0000 }
27428 },
27429/* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
27430 {
27431 { 0, 0, 0, 0 },
27432 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
27433 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87af0000 }
27434 },
27435/* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
27436 {
27437 { 0, 0, 0, 0 },
27438 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
27439 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882f00 }
27440 },
27441/* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
27442 {
27443 { 0, 0, 0, 0 },
27444 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
27445 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80af00 }
27446 },
27447/* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
27448 {
27449 { 0, 0, 0, 0 },
27450 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27451 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802f00 }
27452 },
27453/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
27454 {
27455 { 0, 0, 0, 0 },
27456 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27457 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822f0000 }
27458 },
27459/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
27460 {
27461 { 0, 0, 0, 0 },
27462 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27463 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82af0000 }
27464 },
27465/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
27466 {
27467 { 0, 0, 0, 0 },
27468 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27469 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ef0000 }
27470 },
27471/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
27472 {
27473 { 0, 0, 0, 0 },
27474 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27475 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842f0000 }
27476 },
27477/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
27478 {
27479 { 0, 0, 0, 0 },
27480 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27481 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84af0000 }
27482 },
27483/* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
27484 {
27485 { 0, 0, 0, 0 },
27486 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27487 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ef0000 }
27488 },
27489/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
27490 {
27491 { 0, 0, 0, 0 },
27492 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
27493 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ef0000 }
27494 },
27495/* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
27496 {
27497 { 0, 0, 0, 0 },
27498 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27499 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862f0000 }
27500 },
27501/* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
27502 {
27503 { 0, 0, 0, 0 },
27504 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
27505 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86af0000 }
27506 },
27507/* or.w${G} #${Imm-16-HI},$Dst16RnHI */
27508 {
27509 { 0, 0, 0, 0 },
27510 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
27511 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77300000 }
27512 },
27513/* or.w${G} #${Imm-16-HI},$Dst16AnHI */
27514 {
27515 { 0, 0, 0, 0 },
27516 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
27517 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77340000 }
27518 },
27519/* or.w${G} #${Imm-16-HI},[$Dst16An] */
27520 {
27521 { 0, 0, 0, 0 },
27522 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
27523 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77360000 }
27524 },
27525/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
27526 {
27527 { 0, 0, 0, 0 },
27528 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27529 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77380000 }
27530 },
27531/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
27532 {
27533 { 0, 0, 0, 0 },
27534 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27535 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x773a0000 }
27536 },
27537/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
27538 {
27539 { 0, 0, 0, 0 },
27540 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27541 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x773b0000 }
27542 },
27543/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
27544 {
27545 { 0, 0, 0, 0 },
27546 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27547 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x773c0000 }
27548 },
27549/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
27550 {
27551 { 0, 0, 0, 0 },
27552 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27553 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x773e0000 }
27554 },
27555/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
27556 {
27557 { 0, 0, 0, 0 },
27558 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
27559 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x773f0000 }
27560 },
27561/* or.b${G} #${Imm-16-QI},$Dst16RnQI */
27562 {
27563 { 0, 0, 0, 0 },
27564 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
27565 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x763000 }
27566 },
27567/* or.b${G} #${Imm-16-QI},$Dst16AnQI */
27568 {
27569 { 0, 0, 0, 0 },
27570 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
27571 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x763400 }
27572 },
27573/* or.b${G} #${Imm-16-QI},[$Dst16An] */
27574 {
27575 { 0, 0, 0, 0 },
27576 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
27577 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x763600 }
27578 },
27579/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
27580 {
27581 { 0, 0, 0, 0 },
27582 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27583 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76380000 }
27584 },
27585/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
27586 {
27587 { 0, 0, 0, 0 },
27588 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27589 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x763a0000 }
27590 },
27591/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
27592 {
27593 { 0, 0, 0, 0 },
27594 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27595 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x763b0000 }
27596 },
27597/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
27598 {
27599 { 0, 0, 0, 0 },
27600 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27601 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x763c0000 }
27602 },
27603/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
27604 {
27605 { 0, 0, 0, 0 },
27606 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27607 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x763e0000 }
27608 },
27609/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
27610 {
27611 { 0, 0, 0, 0 },
27612 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
27613 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x763f0000 }
27614 },
27615/* not.w $Dst32RnUnprefixedHI */
27616 {
27617 { 0, 0, 0, 0 },
27618 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
27619 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91e }
27620 },
27621/* not.w $Dst32AnUnprefixedHI */
27622 {
27623 { 0, 0, 0, 0 },
27624 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
27625 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19e }
27626 },
27627/* not.w [$Dst32AnUnprefixed] */
27628 {
27629 { 0, 0, 0, 0 },
27630 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27631 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11e }
27632 },
27633/* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
27634 {
27635 { 0, 0, 0, 0 },
27636 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27637 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31e00 }
27638 },
27639/* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
27640 {
27641 { 0, 0, 0, 0 },
27642 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27643 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51e0000 }
27644 },
27645/* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
27646 {
27647 { 0, 0, 0, 0 },
27648 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27649 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71e0000 }
27650 },
27651/* not.w ${Dsp-16-u8}[sb] */
27652 {
27653 { 0, 0, 0, 0 },
27654 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27655 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39e00 }
27656 },
27657/* not.w ${Dsp-16-u16}[sb] */
27658 {
27659 { 0, 0, 0, 0 },
27660 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27661 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59e0000 }
27662 },
27663/* not.w ${Dsp-16-s8}[fb] */
27664 {
27665 { 0, 0, 0, 0 },
27666 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27667 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3de00 }
27668 },
27669/* not.w ${Dsp-16-s16}[fb] */
27670 {
27671 { 0, 0, 0, 0 },
27672 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27673 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5de0000 }
27674 },
27675/* not.w ${Dsp-16-u16} */
27676 {
27677 { 0, 0, 0, 0 },
27678 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
27679 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7de0000 }
27680 },
27681/* not.w ${Dsp-16-u24} */
27682 {
27683 { 0, 0, 0, 0 },
27684 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
27685 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79e0000 }
27686 },
27687/* not.b $Dst32RnUnprefixedQI */
27688 {
27689 { 0, 0, 0, 0 },
27690 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
27691 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81e }
27692 },
27693/* not.b $Dst32AnUnprefixedQI */
27694 {
27695 { 0, 0, 0, 0 },
27696 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
27697 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09e }
27698 },
27699/* not.b [$Dst32AnUnprefixed] */
27700 {
27701 { 0, 0, 0, 0 },
27702 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27703 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01e }
27704 },
27705/* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
27706 {
27707 { 0, 0, 0, 0 },
27708 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27709 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21e00 }
27710 },
27711/* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
27712 {
27713 { 0, 0, 0, 0 },
27714 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27715 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41e0000 }
27716 },
27717/* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
27718 {
27719 { 0, 0, 0, 0 },
27720 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27721 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61e0000 }
27722 },
27723/* not.b ${Dsp-16-u8}[sb] */
27724 {
27725 { 0, 0, 0, 0 },
27726 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27727 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29e00 }
27728 },
27729/* not.b ${Dsp-16-u16}[sb] */
27730 {
27731 { 0, 0, 0, 0 },
27732 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27733 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49e0000 }
27734 },
27735/* not.b ${Dsp-16-s8}[fb] */
27736 {
27737 { 0, 0, 0, 0 },
27738 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27739 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2de00 }
27740 },
27741/* not.b ${Dsp-16-s16}[fb] */
27742 {
27743 { 0, 0, 0, 0 },
27744 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27745 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4de0000 }
27746 },
27747/* not.b ${Dsp-16-u16} */
27748 {
27749 { 0, 0, 0, 0 },
27750 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
27751 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6de0000 }
27752 },
27753/* not.b ${Dsp-16-u24} */
27754 {
27755 { 0, 0, 0, 0 },
27756 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
27757 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69e0000 }
27758 },
27759/* not.w $Dst16RnHI */
27760 {
27761 { 0, 0, 0, 0 },
27762 { { MNEM, ' ', OP (DST16RNHI), 0 } },
27763 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7570 }
27764 },
27765/* not.w $Dst16AnHI */
27766 {
27767 { 0, 0, 0, 0 },
27768 { { MNEM, ' ', OP (DST16ANHI), 0 } },
27769 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7574 }
27770 },
27771/* not.w [$Dst16An] */
27772 {
27773 { 0, 0, 0, 0 },
27774 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
27775 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7576 }
27776 },
27777/* not.w ${Dsp-16-u8}[$Dst16An] */
27778 {
27779 { 0, 0, 0, 0 },
27780 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27781 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x757800 }
27782 },
27783/* not.w ${Dsp-16-u16}[$Dst16An] */
27784 {
27785 { 0, 0, 0, 0 },
27786 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27787 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x757c0000 }
27788 },
27789/* not.w ${Dsp-16-u8}[sb] */
27790 {
27791 { 0, 0, 0, 0 },
27792 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27793 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x757a00 }
27794 },
27795/* not.w ${Dsp-16-u16}[sb] */
27796 {
27797 { 0, 0, 0, 0 },
27798 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27799 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x757e0000 }
27800 },
27801/* not.w ${Dsp-16-s8}[fb] */
27802 {
27803 { 0, 0, 0, 0 },
27804 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27805 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x757b00 }
27806 },
27807/* not.w ${Dsp-16-u16} */
27808 {
27809 { 0, 0, 0, 0 },
27810 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
27811 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x757f0000 }
27812 },
27813/* not.b $Dst16RnQI */
27814 {
27815 { 0, 0, 0, 0 },
27816 { { MNEM, ' ', OP (DST16RNQI), 0 } },
27817 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7470 }
27818 },
27819/* not.b $Dst16AnQI */
27820 {
27821 { 0, 0, 0, 0 },
27822 { { MNEM, ' ', OP (DST16ANQI), 0 } },
27823 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7474 }
27824 },
27825/* not.b [$Dst16An] */
27826 {
27827 { 0, 0, 0, 0 },
27828 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
27829 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7476 }
27830 },
27831/* not.b ${Dsp-16-u8}[$Dst16An] */
27832 {
27833 { 0, 0, 0, 0 },
27834 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27835 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x747800 }
27836 },
27837/* not.b ${Dsp-16-u16}[$Dst16An] */
27838 {
27839 { 0, 0, 0, 0 },
27840 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27841 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x747c0000 }
27842 },
27843/* not.b ${Dsp-16-u8}[sb] */
27844 {
27845 { 0, 0, 0, 0 },
27846 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27847 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x747a00 }
27848 },
27849/* not.b ${Dsp-16-u16}[sb] */
27850 {
27851 { 0, 0, 0, 0 },
27852 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27853 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x747e0000 }
27854 },
27855/* not.b ${Dsp-16-s8}[fb] */
27856 {
27857 { 0, 0, 0, 0 },
27858 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27859 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x747b00 }
27860 },
27861/* not.b ${Dsp-16-u16} */
27862 {
27863 { 0, 0, 0, 0 },
27864 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
27865 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x747f0000 }
27866 },
27867/* neg.w $Dst32RnUnprefixedHI */
27868 {
27869 { 0, 0, 0, 0 },
27870 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
27871 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92f }
27872 },
27873/* neg.w $Dst32AnUnprefixedHI */
27874 {
27875 { 0, 0, 0, 0 },
27876 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
27877 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1af }
27878 },
27879/* neg.w [$Dst32AnUnprefixed] */
27880 {
27881 { 0, 0, 0, 0 },
27882 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27883 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12f }
27884 },
27885/* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
27886 {
27887 { 0, 0, 0, 0 },
27888 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27889 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32f00 }
27890 },
27891/* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
27892 {
27893 { 0, 0, 0, 0 },
27894 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27895 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52f0000 }
27896 },
27897/* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
27898 {
27899 { 0, 0, 0, 0 },
27900 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27901 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72f0000 }
27902 },
27903/* neg.w ${Dsp-16-u8}[sb] */
27904 {
27905 { 0, 0, 0, 0 },
27906 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27907 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3af00 }
27908 },
27909/* neg.w ${Dsp-16-u16}[sb] */
27910 {
27911 { 0, 0, 0, 0 },
27912 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27913 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5af0000 }
27914 },
27915/* neg.w ${Dsp-16-s8}[fb] */
27916 {
27917 { 0, 0, 0, 0 },
27918 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27919 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ef00 }
27920 },
27921/* neg.w ${Dsp-16-s16}[fb] */
27922 {
27923 { 0, 0, 0, 0 },
27924 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27925 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ef0000 }
27926 },
27927/* neg.w ${Dsp-16-u16} */
27928 {
27929 { 0, 0, 0, 0 },
27930 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
27931 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ef0000 }
27932 },
27933/* neg.w ${Dsp-16-u24} */
27934 {
27935 { 0, 0, 0, 0 },
27936 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
27937 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7af0000 }
27938 },
27939/* neg.b $Dst32RnUnprefixedQI */
27940 {
27941 { 0, 0, 0, 0 },
27942 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
27943 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82f }
27944 },
27945/* neg.b $Dst32AnUnprefixedQI */
27946 {
27947 { 0, 0, 0, 0 },
27948 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
27949 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0af }
27950 },
27951/* neg.b [$Dst32AnUnprefixed] */
27952 {
27953 { 0, 0, 0, 0 },
27954 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27955 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02f }
27956 },
27957/* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
27958 {
27959 { 0, 0, 0, 0 },
27960 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27961 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22f00 }
27962 },
27963/* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
27964 {
27965 { 0, 0, 0, 0 },
27966 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27967 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42f0000 }
27968 },
27969/* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
27970 {
27971 { 0, 0, 0, 0 },
27972 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27973 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62f0000 }
27974 },
27975/* neg.b ${Dsp-16-u8}[sb] */
27976 {
27977 { 0, 0, 0, 0 },
27978 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27979 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2af00 }
27980 },
27981/* neg.b ${Dsp-16-u16}[sb] */
27982 {
27983 { 0, 0, 0, 0 },
27984 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27985 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4af0000 }
27986 },
27987/* neg.b ${Dsp-16-s8}[fb] */
27988 {
27989 { 0, 0, 0, 0 },
27990 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27991 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ef00 }
27992 },
27993/* neg.b ${Dsp-16-s16}[fb] */
27994 {
27995 { 0, 0, 0, 0 },
27996 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27997 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ef0000 }
27998 },
27999/* neg.b ${Dsp-16-u16} */
28000 {
28001 { 0, 0, 0, 0 },
28002 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28003 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ef0000 }
28004 },
28005/* neg.b ${Dsp-16-u24} */
28006 {
28007 { 0, 0, 0, 0 },
28008 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
28009 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6af0000 }
28010 },
28011/* neg.w $Dst16RnHI */
28012 {
28013 { 0, 0, 0, 0 },
28014 { { MNEM, ' ', OP (DST16RNHI), 0 } },
28015 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7550 }
28016 },
28017/* neg.w $Dst16AnHI */
28018 {
28019 { 0, 0, 0, 0 },
28020 { { MNEM, ' ', OP (DST16ANHI), 0 } },
28021 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7554 }
28022 },
28023/* neg.w [$Dst16An] */
28024 {
28025 { 0, 0, 0, 0 },
28026 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
28027 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7556 }
28028 },
28029/* neg.w ${Dsp-16-u8}[$Dst16An] */
28030 {
28031 { 0, 0, 0, 0 },
28032 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28033 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x755800 }
28034 },
28035/* neg.w ${Dsp-16-u16}[$Dst16An] */
28036 {
28037 { 0, 0, 0, 0 },
28038 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28039 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x755c0000 }
28040 },
28041/* neg.w ${Dsp-16-u8}[sb] */
28042 {
28043 { 0, 0, 0, 0 },
28044 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28045 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x755a00 }
28046 },
28047/* neg.w ${Dsp-16-u16}[sb] */
28048 {
28049 { 0, 0, 0, 0 },
28050 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28051 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x755e0000 }
28052 },
28053/* neg.w ${Dsp-16-s8}[fb] */
28054 {
28055 { 0, 0, 0, 0 },
28056 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28057 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x755b00 }
28058 },
28059/* neg.w ${Dsp-16-u16} */
28060 {
28061 { 0, 0, 0, 0 },
28062 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28063 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x755f0000 }
28064 },
28065/* neg.b $Dst16RnQI */
28066 {
28067 { 0, 0, 0, 0 },
28068 { { MNEM, ' ', OP (DST16RNQI), 0 } },
28069 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7450 }
28070 },
28071/* neg.b $Dst16AnQI */
28072 {
28073 { 0, 0, 0, 0 },
28074 { { MNEM, ' ', OP (DST16ANQI), 0 } },
28075 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7454 }
28076 },
28077/* neg.b [$Dst16An] */
28078 {
28079 { 0, 0, 0, 0 },
28080 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
28081 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7456 }
28082 },
28083/* neg.b ${Dsp-16-u8}[$Dst16An] */
28084 {
28085 { 0, 0, 0, 0 },
28086 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28087 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x745800 }
28088 },
28089/* neg.b ${Dsp-16-u16}[$Dst16An] */
28090 {
28091 { 0, 0, 0, 0 },
28092 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28093 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x745c0000 }
28094 },
28095/* neg.b ${Dsp-16-u8}[sb] */
28096 {
28097 { 0, 0, 0, 0 },
28098 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28099 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x745a00 }
28100 },
28101/* neg.b ${Dsp-16-u16}[sb] */
28102 {
28103 { 0, 0, 0, 0 },
28104 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28105 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x745e0000 }
28106 },
28107/* neg.b ${Dsp-16-s8}[fb] */
28108 {
28109 { 0, 0, 0, 0 },
28110 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28111 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x745b00 }
28112 },
28113/* neg.b ${Dsp-16-u16} */
28114 {
28115 { 0, 0, 0, 0 },
28116 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28117 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x745f0000 }
28118 },
28119/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28120 {
28121 { 0, 0, 0, 0 },
28122 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28123 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990400 }
28124 },
28125/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
28126 {
28127 { 0, 0, 0, 0 },
28128 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28129 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992400 }
28130 },
28131/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
28132 {
28133 { 0, 0, 0, 0 },
28134 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28135 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993400 }
28136 },
28137/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28138 {
28139 { 0, 0, 0, 0 },
28140 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28141 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918400 }
28142 },
28143/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
28144 {
28145 { 0, 0, 0, 0 },
28146 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28147 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a400 }
28148 },
28149/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
28150 {
28151 { 0, 0, 0, 0 },
28152 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28153 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b400 }
28154 },
28155/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28156 {
28157 { 0, 0, 0, 0 },
28158 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28159 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910400 }
28160 },
28161/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28162 {
28163 { 0, 0, 0, 0 },
28164 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28165 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912400 }
28166 },
28167/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28168 {
28169 { 0, 0, 0, 0 },
28170 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28171 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913400 }
28172 },
28173/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28174 {
28175 { 0, 0, 0, 0 },
28176 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28177 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93040000 }
28178 },
28179/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28180 {
28181 { 0, 0, 0, 0 },
28182 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28183 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93240000 }
28184 },
28185/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28186 {
28187 { 0, 0, 0, 0 },
28188 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28189 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93340000 }
28190 },
28191/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28192 {
28193 { 0, 0, 0, 0 },
28194 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28195 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95040000 }
28196 },
28197/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28198 {
28199 { 0, 0, 0, 0 },
28200 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28201 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95240000 }
28202 },
28203/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28204 {
28205 { 0, 0, 0, 0 },
28206 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28207 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95340000 }
28208 },
28209/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28210 {
28211 { 0, 0, 0, 0 },
28212 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28213 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97040000 }
28214 },
28215/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28216 {
28217 { 0, 0, 0, 0 },
28218 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28219 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97240000 }
28220 },
28221/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28222 {
28223 { 0, 0, 0, 0 },
28224 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28225 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97340000 }
28226 },
28227/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28228 {
28229 { 0, 0, 0, 0 },
28230 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28231 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93840000 }
28232 },
28233/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28234 {
28235 { 0, 0, 0, 0 },
28236 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28237 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a40000 }
28238 },
28239/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28240 {
28241 { 0, 0, 0, 0 },
28242 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28243 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b40000 }
28244 },
28245/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28246 {
28247 { 0, 0, 0, 0 },
28248 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28249 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95840000 }
28250 },
28251/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28252 {
28253 { 0, 0, 0, 0 },
28254 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28255 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a40000 }
28256 },
28257/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28258 {
28259 { 0, 0, 0, 0 },
28260 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28261 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b40000 }
28262 },
28263/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28264 {
28265 { 0, 0, 0, 0 },
28266 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28267 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c40000 }
28268 },
28269/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28270 {
28271 { 0, 0, 0, 0 },
28272 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28273 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e40000 }
28274 },
28275/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28276 {
28277 { 0, 0, 0, 0 },
28278 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28279 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f40000 }
28280 },
28281/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28282 {
28283 { 0, 0, 0, 0 },
28284 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28285 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c40000 }
28286 },
28287/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28288 {
28289 { 0, 0, 0, 0 },
28290 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28291 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e40000 }
28292 },
28293/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28294 {
28295 { 0, 0, 0, 0 },
28296 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28297 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f40000 }
28298 },
28299/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28300 {
28301 { 0, 0, 0, 0 },
28302 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
28303 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c40000 }
28304 },
28305/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28306 {
28307 { 0, 0, 0, 0 },
28308 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
28309 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e40000 }
28310 },
28311/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28312 {
28313 { 0, 0, 0, 0 },
28314 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
28315 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f40000 }
28316 },
28317/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28318 {
28319 { 0, 0, 0, 0 },
28320 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
28321 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97840000 }
28322 },
28323/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28324 {
28325 { 0, 0, 0, 0 },
28326 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
28327 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a40000 }
28328 },
28329/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28330 {
28331 { 0, 0, 0, 0 },
28332 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
28333 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b40000 }
28334 },
28335/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28336 {
28337 { 0, 0, 0, 0 },
28338 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28339 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9040000 }
28340 },
28341/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
28342 {
28343 { 0, 0, 0, 0 },
28344 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28345 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9240000 }
28346 },
28347/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
28348 {
28349 { 0, 0, 0, 0 },
28350 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28351 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9340000 }
28352 },
28353/* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
28354 {
28355 { 0, 0, 0, 0 },
28356 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28357 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9340000 }
28358 },
28359/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28360 {
28361 { 0, 0, 0, 0 },
28362 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28363 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1840000 }
28364 },
28365/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
28366 {
28367 { 0, 0, 0, 0 },
28368 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28369 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a40000 }
28370 },
28371/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
28372 {
28373 { 0, 0, 0, 0 },
28374 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28375 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b40000 }
28376 },
28377/* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
28378 {
28379 { 0, 0, 0, 0 },
28380 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28381 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b40000 }
28382 },
28383/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28384 {
28385 { 0, 0, 0, 0 },
28386 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28387 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1040000 }
28388 },
28389/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28390 {
28391 { 0, 0, 0, 0 },
28392 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28393 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1240000 }
28394 },
28395/* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28396 {
28397 { 0, 0, 0, 0 },
28398 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28399 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1340000 }
28400 },
28401/* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28402 {
28403 { 0, 0, 0, 0 },
28404 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28405 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1340000 }
28406 },
28407/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28408 {
28409 { 0, 0, 0, 0 },
28410 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28411 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3040000 }
28412 },
28413/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28414 {
28415 { 0, 0, 0, 0 },
28416 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28417 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3240000 }
28418 },
28419/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28420 {
28421 { 0, 0, 0, 0 },
28422 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28423 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3340000 }
28424 },
28425/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28426 {
28427 { 0, 0, 0, 0 },
28428 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28429 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3340000 }
28430 },
28431/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28432 {
28433 { 0, 0, 0, 0 },
28434 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28435 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5040000 }
28436 },
28437/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28438 {
28439 { 0, 0, 0, 0 },
28440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28441 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5240000 }
28442 },
28443/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28444 {
28445 { 0, 0, 0, 0 },
28446 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28447 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5340000 }
28448 },
28449/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28450 {
28451 { 0, 0, 0, 0 },
28452 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28453 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5340000 }
28454 },
28455/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28456 {
28457 { 0, 0, 0, 0 },
28458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28459 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7040000 }
28460 },
28461/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28462 {
28463 { 0, 0, 0, 0 },
28464 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28465 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7240000 }
28466 },
28467/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28468 {
28469 { 0, 0, 0, 0 },
28470 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28471 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7340000 }
28472 },
28473/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28474 {
28475 { 0, 0, 0, 0 },
28476 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28477 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7340000 }
28478 },
28479/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28480 {
28481 { 0, 0, 0, 0 },
28482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28483 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3840000 }
28484 },
28485/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28486 {
28487 { 0, 0, 0, 0 },
28488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28489 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a40000 }
28490 },
28491/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28492 {
28493 { 0, 0, 0, 0 },
28494 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28495 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b40000 }
28496 },
28497/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28498 {
28499 { 0, 0, 0, 0 },
28500 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28501 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b40000 }
28502 },
28503/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28504 {
28505 { 0, 0, 0, 0 },
28506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28507 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5840000 }
28508 },
28509/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28510 {
28511 { 0, 0, 0, 0 },
28512 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28513 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a40000 }
28514 },
28515/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28516 {
28517 { 0, 0, 0, 0 },
28518 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28519 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b40000 }
28520 },
28521/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28522 {
28523 { 0, 0, 0, 0 },
28524 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28525 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b40000 }
28526 },
28527/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28528 {
28529 { 0, 0, 0, 0 },
28530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28531 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c40000 }
28532 },
28533/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28534 {
28535 { 0, 0, 0, 0 },
28536 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28537 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e40000 }
28538 },
28539/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28540 {
28541 { 0, 0, 0, 0 },
28542 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28543 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f40000 }
28544 },
28545/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28546 {
28547 { 0, 0, 0, 0 },
28548 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28549 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f40000 }
28550 },
28551/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28552 {
28553 { 0, 0, 0, 0 },
28554 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28555 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c40000 }
28556 },
28557/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28558 {
28559 { 0, 0, 0, 0 },
28560 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28561 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e40000 }
28562 },
28563/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28564 {
28565 { 0, 0, 0, 0 },
28566 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28567 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f40000 }
28568 },
28569/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28570 {
28571 { 0, 0, 0, 0 },
28572 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28573 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f40000 }
28574 },
28575/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28576 {
28577 { 0, 0, 0, 0 },
28578 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
28579 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c40000 }
28580 },
28581/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28582 {
28583 { 0, 0, 0, 0 },
28584 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
28585 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e40000 }
28586 },
28587/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28588 {
28589 { 0, 0, 0, 0 },
28590 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
28591 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f40000 }
28592 },
28593/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
28594 {
28595 { 0, 0, 0, 0 },
28596 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
28597 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f40000 }
28598 },
28599/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28600 {
28601 { 0, 0, 0, 0 },
28602 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
28603 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7840000 }
28604 },
28605/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28606 {
28607 { 0, 0, 0, 0 },
28608 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
28609 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a40000 }
28610 },
28611/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28612 {
28613 { 0, 0, 0, 0 },
28614 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
28615 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b40000 }
28616 },
28617/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
28618 {
28619 { 0, 0, 0, 0 },
28620 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
28621 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b40000 }
28622 },
28623/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28624 {
28625 { 0, 0, 0, 0 },
28626 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28627 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9040000 }
28628 },
28629/* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
28630 {
28631 { 0, 0, 0, 0 },
28632 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28633 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9240000 }
28634 },
28635/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28636 {
28637 { 0, 0, 0, 0 },
28638 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28639 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1840000 }
28640 },
28641/* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
28642 {
28643 { 0, 0, 0, 0 },
28644 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28645 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a40000 }
28646 },
28647/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28648 {
28649 { 0, 0, 0, 0 },
28650 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28651 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1040000 }
28652 },
28653/* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28654 {
28655 { 0, 0, 0, 0 },
28656 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28657 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1240000 }
28658 },
28659/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28660 {
28661 { 0, 0, 0, 0 },
28662 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28663 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3040000 }
28664 },
28665/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28666 {
28667 { 0, 0, 0, 0 },
28668 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28669 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3240000 }
28670 },
28671/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28672 {
28673 { 0, 0, 0, 0 },
28674 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28675 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5040000 }
28676 },
28677/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28678 {
28679 { 0, 0, 0, 0 },
28680 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28681 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5240000 }
28682 },
28683/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28684 {
28685 { 0, 0, 0, 0 },
28686 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28687 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7040000 }
28688 },
28689/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28690 {
28691 { 0, 0, 0, 0 },
28692 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28693 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7240000 }
28694 },
28695/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28696 {
28697 { 0, 0, 0, 0 },
28698 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
28699 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3840000 }
28700 },
28701/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28702 {
28703 { 0, 0, 0, 0 },
28704 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
28705 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a40000 }
28706 },
28707/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28708 {
28709 { 0, 0, 0, 0 },
28710 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
28711 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5840000 }
28712 },
28713/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28714 {
28715 { 0, 0, 0, 0 },
28716 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
28717 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a40000 }
28718 },
28719/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28720 {
28721 { 0, 0, 0, 0 },
28722 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
28723 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c40000 }
28724 },
28725/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28726 {
28727 { 0, 0, 0, 0 },
28728 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
28729 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e40000 }
28730 },
28731/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28732 {
28733 { 0, 0, 0, 0 },
28734 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
28735 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c40000 }
28736 },
28737/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28738 {
28739 { 0, 0, 0, 0 },
28740 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
28741 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e40000 }
28742 },
28743/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28744 {
28745 { 0, 0, 0, 0 },
28746 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
28747 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c40000 }
28748 },
28749/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
28750 {
28751 { 0, 0, 0, 0 },
28752 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
28753 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e40000 }
28754 },
28755/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28756 {
28757 { 0, 0, 0, 0 },
28758 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
28759 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7840000 }
28760 },
28761/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
28762 {
28763 { 0, 0, 0, 0 },
28764 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
28765 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a40000 }
28766 },
28767/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
28768 {
28769 { 0, 0, 0, 0 },
28770 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28771 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc904 }
28772 },
28773/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
28774 {
28775 { 0, 0, 0, 0 },
28776 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28777 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8924 }
28778 },
28779/* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28780 {
28781 { 0, 0, 0, 0 },
28782 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28783 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8904 }
28784 },
28785/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
28786 {
28787 { 0, 0, 0, 0 },
28788 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28789 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc184 }
28790 },
28791/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
28792 {
28793 { 0, 0, 0, 0 },
28794 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28795 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a4 }
28796 },
28797/* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28798 {
28799 { 0, 0, 0, 0 },
28800 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28801 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8184 }
28802 },
28803/* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
28804 {
28805 { 0, 0, 0, 0 },
28806 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28807 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc104 }
28808 },
28809/* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
28810 {
28811 { 0, 0, 0, 0 },
28812 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28813 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8124 }
28814 },
28815/* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28816 {
28817 { 0, 0, 0, 0 },
28818 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28819 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8104 }
28820 },
28821/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28822 {
28823 { 0, 0, 0, 0 },
28824 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28825 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30400 }
28826 },
28827/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28828 {
28829 { 0, 0, 0, 0 },
28830 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28831 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832400 }
28832 },
28833/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
28834 {
28835 { 0, 0, 0, 0 },
28836 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28837 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830400 }
28838 },
28839/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28840 {
28841 { 0, 0, 0, 0 },
28842 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28843 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5040000 }
28844 },
28845/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28846 {
28847 { 0, 0, 0, 0 },
28848 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28849 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85240000 }
28850 },
28851/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
28852 {
28853 { 0, 0, 0, 0 },
28854 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28855 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85040000 }
28856 },
28857/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28858 {
28859 { 0, 0, 0, 0 },
28860 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28861 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7040000 }
28862 },
28863/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28864 {
28865 { 0, 0, 0, 0 },
28866 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28867 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87240000 }
28868 },
28869/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
28870 {
28871 { 0, 0, 0, 0 },
28872 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28873 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87040000 }
28874 },
28875/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
28876 {
28877 { 0, 0, 0, 0 },
28878 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28879 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38400 }
28880 },
28881/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
28882 {
28883 { 0, 0, 0, 0 },
28884 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28885 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a400 }
28886 },
28887/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
28888 {
28889 { 0, 0, 0, 0 },
28890 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28891 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838400 }
28892 },
28893/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
28894 {
28895 { 0, 0, 0, 0 },
28896 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28897 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5840000 }
28898 },
28899/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
28900 {
28901 { 0, 0, 0, 0 },
28902 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28903 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a40000 }
28904 },
28905/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
28906 {
28907 { 0, 0, 0, 0 },
28908 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28909 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85840000 }
28910 },
28911/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
28912 {
28913 { 0, 0, 0, 0 },
28914 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28915 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c400 }
28916 },
28917/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
28918 {
28919 { 0, 0, 0, 0 },
28920 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28921 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e400 }
28922 },
28923/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
28924 {
28925 { 0, 0, 0, 0 },
28926 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28927 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c400 }
28928 },
28929/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
28930 {
28931 { 0, 0, 0, 0 },
28932 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
28933 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c40000 }
28934 },
28935/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
28936 {
28937 { 0, 0, 0, 0 },
28938 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
28939 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e40000 }
28940 },
28941/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28942 {
28943 { 0, 0, 0, 0 },
28944 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
28945 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c40000 }
28946 },
28947/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
28948 {
28949 { 0, 0, 0, 0 },
28950 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
28951 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c40000 }
28952 },
28953/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
28954 {
28955 { 0, 0, 0, 0 },
28956 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
28957 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e40000 }
28958 },
28959/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28960 {
28961 { 0, 0, 0, 0 },
28962 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
28963 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c40000 }
28964 },
28965/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
28966 {
28967 { 0, 0, 0, 0 },
28968 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
28969 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7840000 }
28970 },
28971/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
28972 {
28973 { 0, 0, 0, 0 },
28974 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
28975 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a40000 }
28976 },
28977/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28978 {
28979 { 0, 0, 0, 0 },
28980 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
28981 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87840000 }
28982 },
28983/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28984 {
28985 { 0, 0, 0, 0 },
28986 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
28987 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980400 }
28988 },
28989/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
28990 {
28991 { 0, 0, 0, 0 },
28992 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
28993 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982400 }
28994 },
28995/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
28996 {
28997 { 0, 0, 0, 0 },
28998 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
28999 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983400 }
29000 },
29001/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29002 {
29003 { 0, 0, 0, 0 },
29004 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29005 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908400 }
29006 },
29007/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
29008 {
29009 { 0, 0, 0, 0 },
29010 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29011 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a400 }
29012 },
29013/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
29014 {
29015 { 0, 0, 0, 0 },
29016 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29017 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b400 }
29018 },
29019/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29020 {
29021 { 0, 0, 0, 0 },
29022 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29023 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900400 }
29024 },
29025/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
29026 {
29027 { 0, 0, 0, 0 },
29028 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29029 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902400 }
29030 },
29031/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
29032 {
29033 { 0, 0, 0, 0 },
29034 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29035 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903400 }
29036 },
29037/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29038 {
29039 { 0, 0, 0, 0 },
29040 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29041 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92040000 }
29042 },
29043/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29044 {
29045 { 0, 0, 0, 0 },
29046 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29047 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92240000 }
29048 },
29049/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29050 {
29051 { 0, 0, 0, 0 },
29052 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29053 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92340000 }
29054 },
29055/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29056 {
29057 { 0, 0, 0, 0 },
29058 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29059 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94040000 }
29060 },
29061/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29062 {
29063 { 0, 0, 0, 0 },
29064 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29065 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94240000 }
29066 },
29067/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29068 {
29069 { 0, 0, 0, 0 },
29070 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29071 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94340000 }
29072 },
29073/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29074 {
29075 { 0, 0, 0, 0 },
29076 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29077 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96040000 }
29078 },
29079/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29080 {
29081 { 0, 0, 0, 0 },
29082 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29083 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96240000 }
29084 },
29085/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29086 {
29087 { 0, 0, 0, 0 },
29088 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29089 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96340000 }
29090 },
29091/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
29092 {
29093 { 0, 0, 0, 0 },
29094 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29095 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92840000 }
29096 },
29097/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29098 {
29099 { 0, 0, 0, 0 },
29100 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29101 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a40000 }
29102 },
29103/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29104 {
29105 { 0, 0, 0, 0 },
29106 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29107 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b40000 }
29108 },
29109/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
29110 {
29111 { 0, 0, 0, 0 },
29112 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29113 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94840000 }
29114 },
29115/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29116 {
29117 { 0, 0, 0, 0 },
29118 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29119 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a40000 }
29120 },
29121/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29122 {
29123 { 0, 0, 0, 0 },
29124 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29125 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b40000 }
29126 },
29127/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
29128 {
29129 { 0, 0, 0, 0 },
29130 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29131 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c40000 }
29132 },
29133/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29134 {
29135 { 0, 0, 0, 0 },
29136 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29137 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e40000 }
29138 },
29139/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29140 {
29141 { 0, 0, 0, 0 },
29142 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29143 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f40000 }
29144 },
29145/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
29146 {
29147 { 0, 0, 0, 0 },
29148 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29149 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c40000 }
29150 },
29151/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
29152 {
29153 { 0, 0, 0, 0 },
29154 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29155 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e40000 }
29156 },
29157/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
29158 {
29159 { 0, 0, 0, 0 },
29160 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29161 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f40000 }
29162 },
29163/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
29164 {
29165 { 0, 0, 0, 0 },
29166 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
29167 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c40000 }
29168 },
29169/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29170 {
29171 { 0, 0, 0, 0 },
29172 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
29173 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e40000 }
29174 },
29175/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29176 {
29177 { 0, 0, 0, 0 },
29178 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
29179 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f40000 }
29180 },
29181/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
29182 {
29183 { 0, 0, 0, 0 },
29184 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
29185 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96840000 }
29186 },
29187/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
29188 {
29189 { 0, 0, 0, 0 },
29190 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
29191 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a40000 }
29192 },
29193/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
29194 {
29195 { 0, 0, 0, 0 },
29196 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
29197 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b40000 }
29198 },
29199/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29200 {
29201 { 0, 0, 0, 0 },
29202 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29203 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8040000 }
29204 },
29205/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
29206 {
29207 { 0, 0, 0, 0 },
29208 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29209 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8240000 }
29210 },
29211/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
29212 {
29213 { 0, 0, 0, 0 },
29214 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29215 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8340000 }
29216 },
29217/* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
29218 {
29219 { 0, 0, 0, 0 },
29220 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29221 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8340000 }
29222 },
29223/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29224 {
29225 { 0, 0, 0, 0 },
29226 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29227 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0840000 }
29228 },
29229/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
29230 {
29231 { 0, 0, 0, 0 },
29232 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29233 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a40000 }
29234 },
29235/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
29236 {
29237 { 0, 0, 0, 0 },
29238 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29239 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b40000 }
29240 },
29241/* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
29242 {
29243 { 0, 0, 0, 0 },
29244 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29245 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b40000 }
29246 },
29247/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29248 {
29249 { 0, 0, 0, 0 },
29250 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29251 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0040000 }
29252 },
29253/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
29254 {
29255 { 0, 0, 0, 0 },
29256 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29257 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0240000 }
29258 },
29259/* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
29260 {
29261 { 0, 0, 0, 0 },
29262 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29263 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0340000 }
29264 },
29265/* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
29266 {
29267 { 0, 0, 0, 0 },
29268 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29269 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0340000 }
29270 },
29271/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29272 {
29273 { 0, 0, 0, 0 },
29274 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29275 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2040000 }
29276 },
29277/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29278 {
29279 { 0, 0, 0, 0 },
29280 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29281 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2240000 }
29282 },
29283/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29284 {
29285 { 0, 0, 0, 0 },
29286 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29287 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2340000 }
29288 },
29289/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
29290 {
29291 { 0, 0, 0, 0 },
29292 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29293 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2340000 }
29294 },
29295/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29296 {
29297 { 0, 0, 0, 0 },
29298 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29299 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4040000 }
29300 },
29301/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29302 {
29303 { 0, 0, 0, 0 },
29304 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29305 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4240000 }
29306 },
29307/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29308 {
29309 { 0, 0, 0, 0 },
29310 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29311 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4340000 }
29312 },
29313/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
29314 {
29315 { 0, 0, 0, 0 },
29316 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29317 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4340000 }
29318 },
29319/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29320 {
29321 { 0, 0, 0, 0 },
29322 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29323 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6040000 }
29324 },
29325/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29326 {
29327 { 0, 0, 0, 0 },
29328 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29329 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6240000 }
29330 },
29331/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29332 {
29333 { 0, 0, 0, 0 },
29334 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29335 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6340000 }
29336 },
29337/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
29338 {
29339 { 0, 0, 0, 0 },
29340 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29341 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6340000 }
29342 },
29343/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
29344 {
29345 { 0, 0, 0, 0 },
29346 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29347 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2840000 }
29348 },
29349/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29350 {
29351 { 0, 0, 0, 0 },
29352 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29353 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a40000 }
29354 },
29355/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
29356 {
29357 { 0, 0, 0, 0 },
29358 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29359 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b40000 }
29360 },
29361/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29362 {
29363 { 0, 0, 0, 0 },
29364 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29365 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b40000 }
29366 },
29367/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
29368 {
29369 { 0, 0, 0, 0 },
29370 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29371 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4840000 }
29372 },
29373/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29374 {
29375 { 0, 0, 0, 0 },
29376 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29377 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a40000 }
29378 },
29379/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
29380 {
29381 { 0, 0, 0, 0 },
29382 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29383 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b40000 }
29384 },
29385/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29386 {
29387 { 0, 0, 0, 0 },
29388 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29389 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b40000 }
29390 },
29391/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
29392 {
29393 { 0, 0, 0, 0 },
29394 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29395 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c40000 }
29396 },
29397/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29398 {
29399 { 0, 0, 0, 0 },
29400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29401 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e40000 }
29402 },
29403/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
29404 {
29405 { 0, 0, 0, 0 },
29406 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29407 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f40000 }
29408 },
29409/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29410 {
29411 { 0, 0, 0, 0 },
29412 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29413 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f40000 }
29414 },
29415/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
29416 {
29417 { 0, 0, 0, 0 },
29418 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29419 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c40000 }
29420 },
29421/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
29422 {
29423 { 0, 0, 0, 0 },
29424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29425 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e40000 }
29426 },
29427/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
29428 {
29429 { 0, 0, 0, 0 },
29430 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29431 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f40000 }
29432 },
29433/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
29434 {
29435 { 0, 0, 0, 0 },
29436 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29437 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f40000 }
29438 },
29439/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
29440 {
29441 { 0, 0, 0, 0 },
29442 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
29443 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c40000 }
29444 },
29445/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29446 {
29447 { 0, 0, 0, 0 },
29448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
29449 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e40000 }
29450 },
29451/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
29452 {
29453 { 0, 0, 0, 0 },
29454 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
29455 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f40000 }
29456 },
29457/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29458 {
29459 { 0, 0, 0, 0 },
29460 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
29461 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f40000 }
29462 },
29463/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
29464 {
29465 { 0, 0, 0, 0 },
29466 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
29467 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6840000 }
29468 },
29469/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
29470 {
29471 { 0, 0, 0, 0 },
29472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
29473 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a40000 }
29474 },
29475/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
29476 {
29477 { 0, 0, 0, 0 },
29478 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
29479 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b40000 }
29480 },
29481/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
29482 {
29483 { 0, 0, 0, 0 },
29484 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
29485 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b40000 }
29486 },
29487/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29488 {
29489 { 0, 0, 0, 0 },
29490 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29491 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8040000 }
29492 },
29493/* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
29494 {
29495 { 0, 0, 0, 0 },
29496 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29497 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8240000 }
29498 },
29499/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29500 {
29501 { 0, 0, 0, 0 },
29502 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29503 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0840000 }
29504 },
29505/* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
29506 {
29507 { 0, 0, 0, 0 },
29508 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29509 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a40000 }
29510 },
29511/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29512 {
29513 { 0, 0, 0, 0 },
29514 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29515 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0040000 }
29516 },
29517/* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
29518 {
29519 { 0, 0, 0, 0 },
29520 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29521 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0240000 }
29522 },
29523/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
29524 {
29525 { 0, 0, 0, 0 },
29526 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29527 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2040000 }
29528 },
29529/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
29530 {
29531 { 0, 0, 0, 0 },
29532 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29533 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2240000 }
29534 },
29535/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
29536 {
29537 { 0, 0, 0, 0 },
29538 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29539 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4040000 }
29540 },
29541/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
29542 {
29543 { 0, 0, 0, 0 },
29544 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29545 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4240000 }
29546 },
29547/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
29548 {
29549 { 0, 0, 0, 0 },
29550 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29551 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6040000 }
29552 },
29553/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
29554 {
29555 { 0, 0, 0, 0 },
29556 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29557 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6240000 }
29558 },
29559/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
29560 {
29561 { 0, 0, 0, 0 },
29562 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
29563 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2840000 }
29564 },
29565/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
29566 {
29567 { 0, 0, 0, 0 },
29568 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
29569 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a40000 }
29570 },
29571/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
29572 {
29573 { 0, 0, 0, 0 },
29574 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
29575 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4840000 }
29576 },
29577/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
29578 {
29579 { 0, 0, 0, 0 },
29580 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
29581 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a40000 }
29582 },
29583/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
29584 {
29585 { 0, 0, 0, 0 },
29586 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
29587 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c40000 }
29588 },
29589/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
29590 {
29591 { 0, 0, 0, 0 },
29592 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
29593 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e40000 }
29594 },
29595/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
29596 {
29597 { 0, 0, 0, 0 },
29598 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
29599 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c40000 }
29600 },
29601/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
29602 {
29603 { 0, 0, 0, 0 },
29604 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
29605 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e40000 }
29606 },
29607/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
29608 {
29609 { 0, 0, 0, 0 },
29610 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
29611 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c40000 }
29612 },
29613/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
29614 {
29615 { 0, 0, 0, 0 },
29616 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
29617 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e40000 }
29618 },
29619/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
29620 {
29621 { 0, 0, 0, 0 },
29622 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
29623 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6840000 }
29624 },
29625/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
29626 {
29627 { 0, 0, 0, 0 },
29628 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
29629 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a40000 }
29630 },
29631/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
29632 {
29633 { 0, 0, 0, 0 },
29634 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29635 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc804 }
29636 },
29637/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
29638 {
29639 { 0, 0, 0, 0 },
29640 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29641 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8824 }
29642 },
29643/* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29644 {
29645 { 0, 0, 0, 0 },
29646 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29647 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8804 }
29648 },
29649/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
29650 {
29651 { 0, 0, 0, 0 },
29652 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29653 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc084 }
29654 },
29655/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
29656 {
29657 { 0, 0, 0, 0 },
29658 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29659 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a4 }
29660 },
29661/* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29662 {
29663 { 0, 0, 0, 0 },
29664 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29665 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8084 }
29666 },
29667/* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
29668 {
29669 { 0, 0, 0, 0 },
29670 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29671 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc004 }
29672 },
29673/* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
29674 {
29675 { 0, 0, 0, 0 },
29676 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29677 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8024 }
29678 },
29679/* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29680 {
29681 { 0, 0, 0, 0 },
29682 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29683 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8004 }
29684 },
29685/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29686 {
29687 { 0, 0, 0, 0 },
29688 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29689 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20400 }
29690 },
29691/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29692 {
29693 { 0, 0, 0, 0 },
29694 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29695 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822400 }
29696 },
29697/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
29698 {
29699 { 0, 0, 0, 0 },
29700 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29701 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820400 }
29702 },
29703/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29704 {
29705 { 0, 0, 0, 0 },
29706 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29707 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4040000 }
29708 },
29709/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29710 {
29711 { 0, 0, 0, 0 },
29712 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29713 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84240000 }
29714 },
29715/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
29716 {
29717 { 0, 0, 0, 0 },
29718 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29719 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84040000 }
29720 },
29721/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29722 {
29723 { 0, 0, 0, 0 },
29724 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29725 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6040000 }
29726 },
29727/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29728 {
29729 { 0, 0, 0, 0 },
29730 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29731 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86240000 }
29732 },
29733/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
29734 {
29735 { 0, 0, 0, 0 },
29736 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29737 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86040000 }
29738 },
29739/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
29740 {
29741 { 0, 0, 0, 0 },
29742 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29743 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28400 }
29744 },
29745/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
29746 {
29747 { 0, 0, 0, 0 },
29748 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29749 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a400 }
29750 },
29751/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
29752 {
29753 { 0, 0, 0, 0 },
29754 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29755 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828400 }
29756 },
29757/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
29758 {
29759 { 0, 0, 0, 0 },
29760 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29761 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4840000 }
29762 },
29763/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
29764 {
29765 { 0, 0, 0, 0 },
29766 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29767 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a40000 }
29768 },
29769/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
29770 {
29771 { 0, 0, 0, 0 },
29772 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29773 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84840000 }
29774 },
29775/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
29776 {
29777 { 0, 0, 0, 0 },
29778 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29779 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c400 }
29780 },
29781/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
29782 {
29783 { 0, 0, 0, 0 },
29784 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29785 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e400 }
29786 },
29787/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
29788 {
29789 { 0, 0, 0, 0 },
29790 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29791 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c400 }
29792 },
29793/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
29794 {
29795 { 0, 0, 0, 0 },
29796 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29797 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c40000 }
29798 },
29799/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
29800 {
29801 { 0, 0, 0, 0 },
29802 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29803 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e40000 }
29804 },
29805/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
29806 {
29807 { 0, 0, 0, 0 },
29808 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29809 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c40000 }
29810 },
29811/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
29812 {
29813 { 0, 0, 0, 0 },
29814 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
29815 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c40000 }
29816 },
29817/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
29818 {
29819 { 0, 0, 0, 0 },
29820 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
29821 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e40000 }
29822 },
29823/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
29824 {
29825 { 0, 0, 0, 0 },
29826 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
29827 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c40000 }
29828 },
29829/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
29830 {
29831 { 0, 0, 0, 0 },
29832 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
29833 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6840000 }
29834 },
29835/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
29836 {
29837 { 0, 0, 0, 0 },
29838 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
29839 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a40000 }
29840 },
29841/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
29842 {
29843 { 0, 0, 0, 0 },
29844 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
29845 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86840000 }
29846 },
29847/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
29848 {
29849 { 0, 0, 0, 0 },
29850 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
29851 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x718000 }
29852 },
29853/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
29854 {
29855 { 0, 0, 0, 0 },
29856 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
29857 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x71a000 }
29858 },
29859/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
29860 {
29861 { 0, 0, 0, 0 },
29862 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
29863 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x71b000 }
29864 },
29865/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
29866 {
29867 { 0, 0, 0, 0 },
29868 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
29869 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x718400 }
29870 },
29871/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
29872 {
29873 { 0, 0, 0, 0 },
29874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
29875 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x71a400 }
29876 },
29877/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
29878 {
29879 { 0, 0, 0, 0 },
29880 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
29881 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x71b400 }
29882 },
29883/* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
29884 {
29885 { 0, 0, 0, 0 },
29886 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
29887 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x718600 }
29888 },
29889/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
29890 {
29891 { 0, 0, 0, 0 },
29892 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
29893 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x71a600 }
29894 },
29895/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
29896 {
29897 { 0, 0, 0, 0 },
29898 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
29899 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x71b600 }
29900 },
29901/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
29902 {
29903 { 0, 0, 0, 0 },
29904 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
29905 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x71880000 }
29906 },
29907/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
29908 {
29909 { 0, 0, 0, 0 },
29910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
29911 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x71a80000 }
29912 },
29913/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
29914 {
29915 { 0, 0, 0, 0 },
29916 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
29917 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x71b80000 }
29918 },
29919/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
29920 {
29921 { 0, 0, 0, 0 },
29922 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
29923 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x718c0000 }
29924 },
29925/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
29926 {
29927 { 0, 0, 0, 0 },
29928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
29929 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x71ac0000 }
29930 },
29931/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
29932 {
29933 { 0, 0, 0, 0 },
29934 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
29935 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x71bc0000 }
29936 },
29937/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
29938 {
29939 { 0, 0, 0, 0 },
29940 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29941 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x718a0000 }
29942 },
29943/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29944 {
29945 { 0, 0, 0, 0 },
29946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29947 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71aa0000 }
29948 },
29949/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29950 {
29951 { 0, 0, 0, 0 },
29952 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29953 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71ba0000 }
29954 },
29955/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
29956 {
29957 { 0, 0, 0, 0 },
29958 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29959 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x718e0000 }
29960 },
29961/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29962 {
29963 { 0, 0, 0, 0 },
29964 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29965 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71ae0000 }
29966 },
29967/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29968 {
29969 { 0, 0, 0, 0 },
29970 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29971 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71be0000 }
29972 },
29973/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
29974 {
29975 { 0, 0, 0, 0 },
29976 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29977 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x718b0000 }
29978 },
29979/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29980 {
29981 { 0, 0, 0, 0 },
29982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29983 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71ab0000 }
29984 },
29985/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29986 {
29987 { 0, 0, 0, 0 },
29988 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29989 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71bb0000 }
29990 },
29991/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
29992 {
29993 { 0, 0, 0, 0 },
29994 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
29995 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x718f0000 }
29996 },
29997/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29998 {
29999 { 0, 0, 0, 0 },
30000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30001 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x71af0000 }
30002 },
30003/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
30004 {
30005 { 0, 0, 0, 0 },
30006 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30007 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x71bf0000 }
30008 },
30009/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
30010 {
30011 { 0, 0, 0, 0 },
30012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30013 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x71c00000 }
30014 },
30015/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
30016 {
30017 { 0, 0, 0, 0 },
30018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
30019 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x71e00000 }
30020 },
30021/* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
30022 {
30023 { 0, 0, 0, 0 },
30024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
30025 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x71f00000 }
30026 },
30027/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
30028 {
30029 { 0, 0, 0, 0 },
30030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30031 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x71c40000 }
30032 },
30033/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
30034 {
30035 { 0, 0, 0, 0 },
30036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
30037 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x71e40000 }
30038 },
30039/* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
30040 {
30041 { 0, 0, 0, 0 },
30042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
30043 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x71f40000 }
30044 },
30045/* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
30046 {
30047 { 0, 0, 0, 0 },
30048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30049 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x71c60000 }
30050 },
30051/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
30052 {
30053 { 0, 0, 0, 0 },
30054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30055 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x71e60000 }
30056 },
30057/* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
30058 {
30059 { 0, 0, 0, 0 },
30060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
30061 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x71f60000 }
30062 },
30063/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
30064 {
30065 { 0, 0, 0, 0 },
30066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30067 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x71c80000 }
30068 },
30069/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
30070 {
30071 { 0, 0, 0, 0 },
30072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30073 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x71e80000 }
30074 },
30075/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
30076 {
30077 { 0, 0, 0, 0 },
30078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30079 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x71f80000 }
30080 },
30081/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
30082 {
30083 { 0, 0, 0, 0 },
30084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30085 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x71cc0000 }
30086 },
30087/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
30088 {
30089 { 0, 0, 0, 0 },
30090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30091 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x71ec0000 }
30092 },
30093/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
30094 {
30095 { 0, 0, 0, 0 },
30096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30097 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x71fc0000 }
30098 },
30099/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
30100 {
30101 { 0, 0, 0, 0 },
30102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30103 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ca0000 }
30104 },
30105/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
30106 {
30107 { 0, 0, 0, 0 },
30108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30109 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ea0000 }
30110 },
30111/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
30112 {
30113 { 0, 0, 0, 0 },
30114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30115 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x71fa0000 }
30116 },
30117/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
30118 {
30119 { 0, 0, 0, 0 },
30120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30121 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ce0000 }
30122 },
30123/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
30124 {
30125 { 0, 0, 0, 0 },
30126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30127 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ee0000 }
30128 },
30129/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
30130 {
30131 { 0, 0, 0, 0 },
30132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30133 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x71fe0000 }
30134 },
30135/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
30136 {
30137 { 0, 0, 0, 0 },
30138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30139 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x71cb0000 }
30140 },
30141/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
30142 {
30143 { 0, 0, 0, 0 },
30144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30145 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x71eb0000 }
30146 },
30147/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
30148 {
30149 { 0, 0, 0, 0 },
30150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30151 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x71fb0000 }
30152 },
30153/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
30154 {
30155 { 0, 0, 0, 0 },
30156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
30157 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x71cf0000 }
30158 },
30159/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
30160 {
30161 { 0, 0, 0, 0 },
30162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
30163 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x71ef0000 }
30164 },
30165/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
30166 {
30167 { 0, 0, 0, 0 },
30168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
30169 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x71ff0000 }
30170 },
30171/* mulu.w${G} $Src16RnHI,$Dst16RnHI */
30172 {
30173 { 0, 0, 0, 0 },
30174 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
30175 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7100 }
30176 },
30177/* mulu.w${G} $Src16AnHI,$Dst16RnHI */
30178 {
30179 { 0, 0, 0, 0 },
30180 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
30181 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7140 }
30182 },
30183/* mulu.w${G} [$Src16An],$Dst16RnHI */
30184 {
30185 { 0, 0, 0, 0 },
30186 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30187 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7160 }
30188 },
30189/* mulu.w${G} $Src16RnHI,$Dst16AnHI */
30190 {
30191 { 0, 0, 0, 0 },
30192 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
30193 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7104 }
30194 },
30195/* mulu.w${G} $Src16AnHI,$Dst16AnHI */
30196 {
30197 { 0, 0, 0, 0 },
30198 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
30199 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7144 }
30200 },
30201/* mulu.w${G} [$Src16An],$Dst16AnHI */
30202 {
30203 { 0, 0, 0, 0 },
30204 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30205 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7164 }
30206 },
30207/* mulu.w${G} $Src16RnHI,[$Dst16An] */
30208 {
30209 { 0, 0, 0, 0 },
30210 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
30211 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7106 }
30212 },
30213/* mulu.w${G} $Src16AnHI,[$Dst16An] */
30214 {
30215 { 0, 0, 0, 0 },
30216 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
30217 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7146 }
30218 },
30219/* mulu.w${G} [$Src16An],[$Dst16An] */
30220 {
30221 { 0, 0, 0, 0 },
30222 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30223 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7166 }
30224 },
30225/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
30226 {
30227 { 0, 0, 0, 0 },
30228 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30229 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x710800 }
30230 },
30231/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
30232 {
30233 { 0, 0, 0, 0 },
30234 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30235 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x714800 }
30236 },
30237/* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
30238 {
30239 { 0, 0, 0, 0 },
30240 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30241 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x716800 }
30242 },
30243/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
30244 {
30245 { 0, 0, 0, 0 },
30246 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30247 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x710c0000 }
30248 },
30249/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
30250 {
30251 { 0, 0, 0, 0 },
30252 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30253 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x714c0000 }
30254 },
30255/* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
30256 {
30257 { 0, 0, 0, 0 },
30258 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30259 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x716c0000 }
30260 },
30261/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
30262 {
30263 { 0, 0, 0, 0 },
30264 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30265 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x710a00 }
30266 },
30267/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
30268 {
30269 { 0, 0, 0, 0 },
30270 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30271 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x714a00 }
30272 },
30273/* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
30274 {
30275 { 0, 0, 0, 0 },
30276 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30277 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x716a00 }
30278 },
30279/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
30280 {
30281 { 0, 0, 0, 0 },
30282 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30283 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x710e0000 }
30284 },
30285/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
30286 {
30287 { 0, 0, 0, 0 },
30288 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30289 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x714e0000 }
30290 },
30291/* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
30292 {
30293 { 0, 0, 0, 0 },
30294 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30295 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x716e0000 }
30296 },
30297/* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
30298 {
30299 { 0, 0, 0, 0 },
30300 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30301 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x710b00 }
30302 },
30303/* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
30304 {
30305 { 0, 0, 0, 0 },
30306 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30307 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x714b00 }
30308 },
30309/* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
30310 {
30311 { 0, 0, 0, 0 },
30312 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30313 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x716b00 }
30314 },
30315/* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
30316 {
30317 { 0, 0, 0, 0 },
30318 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
30319 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x710f0000 }
30320 },
30321/* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
30322 {
30323 { 0, 0, 0, 0 },
30324 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
30325 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x714f0000 }
30326 },
30327/* mulu.w${G} [$Src16An],${Dsp-16-u16} */
30328 {
30329 { 0, 0, 0, 0 },
30330 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
30331 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x716f0000 }
30332 },
30333/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
30334 {
30335 { 0, 0, 0, 0 },
30336 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30337 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x708000 }
30338 },
30339/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
30340 {
30341 { 0, 0, 0, 0 },
30342 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
30343 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x70a000 }
30344 },
30345/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
30346 {
30347 { 0, 0, 0, 0 },
30348 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
30349 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x70b000 }
30350 },
30351/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
30352 {
30353 { 0, 0, 0, 0 },
30354 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30355 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x708400 }
30356 },
30357/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
30358 {
30359 { 0, 0, 0, 0 },
30360 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
30361 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x70a400 }
30362 },
30363/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
30364 {
30365 { 0, 0, 0, 0 },
30366 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
30367 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x70b400 }
30368 },
30369/* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
30370 {
30371 { 0, 0, 0, 0 },
30372 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30373 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x708600 }
30374 },
30375/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
30376 {
30377 { 0, 0, 0, 0 },
30378 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30379 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x70a600 }
30380 },
30381/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
30382 {
30383 { 0, 0, 0, 0 },
30384 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30385 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x70b600 }
30386 },
30387/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
30388 {
30389 { 0, 0, 0, 0 },
30390 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30391 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x70880000 }
30392 },
30393/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
30394 {
30395 { 0, 0, 0, 0 },
30396 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30397 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x70a80000 }
30398 },
30399/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
30400 {
30401 { 0, 0, 0, 0 },
30402 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30403 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x70b80000 }
30404 },
30405/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
30406 {
30407 { 0, 0, 0, 0 },
30408 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30409 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x708c0000 }
30410 },
30411/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
30412 {
30413 { 0, 0, 0, 0 },
30414 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30415 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x70ac0000 }
30416 },
30417/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
30418 {
30419 { 0, 0, 0, 0 },
30420 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30421 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x70bc0000 }
30422 },
30423/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
30424 {
30425 { 0, 0, 0, 0 },
30426 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30427 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x708a0000 }
30428 },
30429/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
30430 {
30431 { 0, 0, 0, 0 },
30432 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30433 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70aa0000 }
30434 },
30435/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
30436 {
30437 { 0, 0, 0, 0 },
30438 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30439 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70ba0000 }
30440 },
30441/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
30442 {
30443 { 0, 0, 0, 0 },
30444 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30445 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x708e0000 }
30446 },
30447/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
30448 {
30449 { 0, 0, 0, 0 },
30450 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30451 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70ae0000 }
30452 },
30453/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
30454 {
30455 { 0, 0, 0, 0 },
30456 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30457 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70be0000 }
30458 },
30459/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
30460 {
30461 { 0, 0, 0, 0 },
30462 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30463 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x708b0000 }
30464 },
30465/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
30466 {
30467 { 0, 0, 0, 0 },
30468 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30469 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70ab0000 }
30470 },
30471/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
30472 {
30473 { 0, 0, 0, 0 },
30474 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30475 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70bb0000 }
30476 },
30477/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
30478 {
30479 { 0, 0, 0, 0 },
30480 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
30481 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x708f0000 }
30482 },
30483/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
30484 {
30485 { 0, 0, 0, 0 },
30486 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30487 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x70af0000 }
30488 },
30489/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
30490 {
30491 { 0, 0, 0, 0 },
30492 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30493 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x70bf0000 }
30494 },
30495/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
30496 {
30497 { 0, 0, 0, 0 },
30498 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30499 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x70c00000 }
30500 },
30501/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
30502 {
30503 { 0, 0, 0, 0 },
30504 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
30505 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x70e00000 }
30506 },
30507/* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
30508 {
30509 { 0, 0, 0, 0 },
30510 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
30511 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x70f00000 }
30512 },
30513/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
30514 {
30515 { 0, 0, 0, 0 },
30516 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30517 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x70c40000 }
30518 },
30519/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
30520 {
30521 { 0, 0, 0, 0 },
30522 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
30523 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x70e40000 }
30524 },
30525/* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
30526 {
30527 { 0, 0, 0, 0 },
30528 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
30529 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x70f40000 }
30530 },
30531/* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
30532 {
30533 { 0, 0, 0, 0 },
30534 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30535 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x70c60000 }
30536 },
30537/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
30538 {
30539 { 0, 0, 0, 0 },
30540 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30541 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x70e60000 }
30542 },
30543/* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
30544 {
30545 { 0, 0, 0, 0 },
30546 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
30547 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x70f60000 }
30548 },
30549/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
30550 {
30551 { 0, 0, 0, 0 },
30552 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30553 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x70c80000 }
30554 },
30555/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
30556 {
30557 { 0, 0, 0, 0 },
30558 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30559 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x70e80000 }
30560 },
30561/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
30562 {
30563 { 0, 0, 0, 0 },
30564 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30565 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x70f80000 }
30566 },
30567/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
30568 {
30569 { 0, 0, 0, 0 },
30570 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30571 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x70cc0000 }
30572 },
30573/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
30574 {
30575 { 0, 0, 0, 0 },
30576 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30577 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x70ec0000 }
30578 },
30579/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
30580 {
30581 { 0, 0, 0, 0 },
30582 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30583 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x70fc0000 }
30584 },
30585/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
30586 {
30587 { 0, 0, 0, 0 },
30588 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30589 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ca0000 }
30590 },
30591/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
30592 {
30593 { 0, 0, 0, 0 },
30594 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30595 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ea0000 }
30596 },
30597/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
30598 {
30599 { 0, 0, 0, 0 },
30600 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30601 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x70fa0000 }
30602 },
30603/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
30604 {
30605 { 0, 0, 0, 0 },
30606 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30607 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ce0000 }
30608 },
30609/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
30610 {
30611 { 0, 0, 0, 0 },
30612 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30613 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ee0000 }
30614 },
30615/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
30616 {
30617 { 0, 0, 0, 0 },
30618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30619 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x70fe0000 }
30620 },
30621/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
30622 {
30623 { 0, 0, 0, 0 },
30624 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30625 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x70cb0000 }
30626 },
30627/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
30628 {
30629 { 0, 0, 0, 0 },
30630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30631 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x70eb0000 }
30632 },
30633/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
30634 {
30635 { 0, 0, 0, 0 },
30636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30637 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x70fb0000 }
30638 },
30639/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
30640 {
30641 { 0, 0, 0, 0 },
30642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
30643 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x70cf0000 }
30644 },
30645/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
30646 {
30647 { 0, 0, 0, 0 },
30648 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
30649 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x70ef0000 }
30650 },
30651/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
30652 {
30653 { 0, 0, 0, 0 },
30654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
30655 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x70ff0000 }
30656 },
30657/* mulu.b${G} $Src16RnQI,$Dst16RnQI */
30658 {
30659 { 0, 0, 0, 0 },
30660 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
30661 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7000 }
30662 },
30663/* mulu.b${G} $Src16AnQI,$Dst16RnQI */
30664 {
30665 { 0, 0, 0, 0 },
30666 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
30667 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7040 }
30668 },
30669/* mulu.b${G} [$Src16An],$Dst16RnQI */
30670 {
30671 { 0, 0, 0, 0 },
30672 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30673 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7060 }
30674 },
30675/* mulu.b${G} $Src16RnQI,$Dst16AnQI */
30676 {
30677 { 0, 0, 0, 0 },
30678 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
30679 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7004 }
30680 },
30681/* mulu.b${G} $Src16AnQI,$Dst16AnQI */
30682 {
30683 { 0, 0, 0, 0 },
30684 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
30685 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7044 }
30686 },
30687/* mulu.b${G} [$Src16An],$Dst16AnQI */
30688 {
30689 { 0, 0, 0, 0 },
30690 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30691 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7064 }
30692 },
30693/* mulu.b${G} $Src16RnQI,[$Dst16An] */
30694 {
30695 { 0, 0, 0, 0 },
30696 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
30697 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7006 }
30698 },
30699/* mulu.b${G} $Src16AnQI,[$Dst16An] */
30700 {
30701 { 0, 0, 0, 0 },
30702 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
30703 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7046 }
30704 },
30705/* mulu.b${G} [$Src16An],[$Dst16An] */
30706 {
30707 { 0, 0, 0, 0 },
30708 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30709 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7066 }
30710 },
30711/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
30712 {
30713 { 0, 0, 0, 0 },
30714 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30715 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x700800 }
30716 },
30717/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
30718 {
30719 { 0, 0, 0, 0 },
30720 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30721 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x704800 }
30722 },
30723/* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
30724 {
30725 { 0, 0, 0, 0 },
30726 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30727 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x706800 }
30728 },
30729/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
30730 {
30731 { 0, 0, 0, 0 },
30732 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30733 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x700c0000 }
30734 },
30735/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
30736 {
30737 { 0, 0, 0, 0 },
30738 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30739 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x704c0000 }
30740 },
30741/* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
30742 {
30743 { 0, 0, 0, 0 },
30744 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30745 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x706c0000 }
30746 },
30747/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
30748 {
30749 { 0, 0, 0, 0 },
30750 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30751 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x700a00 }
30752 },
30753/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
30754 {
30755 { 0, 0, 0, 0 },
30756 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30757 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x704a00 }
30758 },
30759/* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
30760 {
30761 { 0, 0, 0, 0 },
30762 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30763 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x706a00 }
30764 },
30765/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
30766 {
30767 { 0, 0, 0, 0 },
30768 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30769 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x700e0000 }
30770 },
30771/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
30772 {
30773 { 0, 0, 0, 0 },
30774 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30775 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x704e0000 }
30776 },
30777/* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
30778 {
30779 { 0, 0, 0, 0 },
30780 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30781 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x706e0000 }
30782 },
30783/* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
30784 {
30785 { 0, 0, 0, 0 },
30786 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30787 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x700b00 }
30788 },
30789/* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
30790 {
30791 { 0, 0, 0, 0 },
30792 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30793 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x704b00 }
30794 },
30795/* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
30796 {
30797 { 0, 0, 0, 0 },
30798 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30799 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x706b00 }
30800 },
30801/* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
30802 {
30803 { 0, 0, 0, 0 },
30804 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
30805 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x700f0000 }
30806 },
30807/* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
30808 {
30809 { 0, 0, 0, 0 },
30810 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
30811 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x704f0000 }
30812 },
30813/* mulu.b${G} [$Src16An],${Dsp-16-u16} */
30814 {
30815 { 0, 0, 0, 0 },
30816 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
30817 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x706f0000 }
30818 },
30819/* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
30820 {
30821 { 0, 0, 0, 0 },
30822 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
30823 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x890f0000 }
30824 },
30825/* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
30826 {
30827 { 0, 0, 0, 0 },
30828 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
30829 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x818f0000 }
30830 },
30831/* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
30832 {
30833 { 0, 0, 0, 0 },
30834 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30835 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x810f0000 }
30836 },
30837/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
30838 {
30839 { 0, 0, 0, 0 },
30840 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30841 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x830f0000 }
30842 },
30843/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30844 {
30845 { 0, 0, 0, 0 },
30846 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30847 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838f0000 }
30848 },
30849/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30850 {
30851 { 0, 0, 0, 0 },
30852 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30853 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cf0000 }
30854 },
30855/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30856 {
30857 { 0, 0, 0, 0 },
30858 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30859 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x850f0000 }
30860 },
30861/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30862 {
30863 { 0, 0, 0, 0 },
30864 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30865 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858f0000 }
30866 },
30867/* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
30868 {
30869 { 0, 0, 0, 0 },
30870 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30871 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cf0000 }
30872 },
30873/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30874 {
30875 { 0, 0, 0, 0 },
30876 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
30877 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87cf0000 }
30878 },
30879/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30880 {
30881 { 0, 0, 0, 0 },
30882 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30883 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x870f0000 }
30884 },
30885/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
30886 {
30887 { 0, 0, 0, 0 },
30888 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
30889 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x878f0000 }
30890 },
30891/* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
30892 {
30893 { 0, 0, 0, 0 },
30894 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
30895 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x880f00 }
30896 },
30897/* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
30898 {
30899 { 0, 0, 0, 0 },
30900 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
30901 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x808f00 }
30902 },
30903/* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
30904 {
30905 { 0, 0, 0, 0 },
30906 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30907 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x800f00 }
30908 },
30909/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
30910 {
30911 { 0, 0, 0, 0 },
30912 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30913 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x820f0000 }
30914 },
30915/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30916 {
30917 { 0, 0, 0, 0 },
30918 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30919 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828f0000 }
30920 },
30921/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30922 {
30923 { 0, 0, 0, 0 },
30924 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30925 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cf0000 }
30926 },
30927/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30928 {
30929 { 0, 0, 0, 0 },
30930 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30931 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x840f0000 }
30932 },
30933/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30934 {
30935 { 0, 0, 0, 0 },
30936 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30937 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848f0000 }
30938 },
30939/* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
30940 {
30941 { 0, 0, 0, 0 },
30942 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30943 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cf0000 }
30944 },
30945/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30946 {
30947 { 0, 0, 0, 0 },
30948 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
30949 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86cf0000 }
30950 },
30951/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30952 {
30953 { 0, 0, 0, 0 },
30954 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
30955 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x860f0000 }
30956 },
30957/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
30958 {
30959 { 0, 0, 0, 0 },
30960 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
30961 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x868f0000 }
30962 },
30963/* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
30964 {
30965 { 0, 0, 0, 0 },
30966 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
30967 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d400000 }
30968 },
30969/* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
30970 {
30971 { 0, 0, 0, 0 },
30972 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
30973 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d440000 }
30974 },
30975/* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
30976 {
30977 { 0, 0, 0, 0 },
30978 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
30979 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d460000 }
30980 },
30981/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
30982 {
30983 { 0, 0, 0, 0 },
30984 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30985 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d480000 }
30986 },
30987/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30988 {
30989 { 0, 0, 0, 0 },
30990 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30991 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d4a0000 }
30992 },
30993/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30994 {
30995 { 0, 0, 0, 0 },
30996 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30997 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d4b0000 }
30998 },
30999/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
31000 {
31001 { 0, 0, 0, 0 },
31002 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
31003 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d4c0000 }
31004 },
31005/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
31006 {
31007 { 0, 0, 0, 0 },
31008 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31009 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d4e0000 }
31010 },
31011/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
31012 {
31013 { 0, 0, 0, 0 },
31014 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
31015 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d4f0000 }
31016 },
31017/* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
31018 {
31019 { 0, 0, 0, 0 },
31020 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
31021 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c4000 }
31022 },
31023/* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
31024 {
31025 { 0, 0, 0, 0 },
31026 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
31027 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c4400 }
31028 },
31029/* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
31030 {
31031 { 0, 0, 0, 0 },
31032 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
31033 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c4600 }
31034 },
31035/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
31036 {
31037 { 0, 0, 0, 0 },
31038 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
31039 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c480000 }
31040 },
31041/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
31042 {
31043 { 0, 0, 0, 0 },
31044 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31045 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c4a0000 }
31046 },
31047/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
31048 {
31049 { 0, 0, 0, 0 },
31050 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31051 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c4b0000 }
31052 },
31053/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
31054 {
31055 { 0, 0, 0, 0 },
31056 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
31057 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c4c0000 }
31058 },
31059/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
31060 {
31061 { 0, 0, 0, 0 },
31062 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31063 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c4e0000 }
31064 },
31065/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
31066 {
31067 { 0, 0, 0, 0 },
31068 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
31069 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c4f0000 }
31070 },
31071/* mulex $R3 */
31072 {
31073 { 0, 0, 0, 0 },
31074 { { MNEM, ' ', OP (R3), 0 } },
31075 & ifmt_mulex_dst32_R3_direct_Unprefixed_HI, { 0xc97e }
31076 },
31077/* mulex $Dst32AnUnprefixedHI */
31078 {
31079 { 0, 0, 0, 0 },
31080 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
31081 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1be }
31082 },
31083/* mulex [$Dst32AnUnprefixed] */
31084 {
31085 { 0, 0, 0, 0 },
31086 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31087 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc13e }
31088 },
31089/* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
31090 {
31091 { 0, 0, 0, 0 },
31092 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31093 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33e00 }
31094 },
31095/* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
31096 {
31097 { 0, 0, 0, 0 },
31098 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31099 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc53e0000 }
31100 },
31101/* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
31102 {
31103 { 0, 0, 0, 0 },
31104 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31105 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc73e0000 }
31106 },
31107/* mulex ${Dsp-16-u8}[sb] */
31108 {
31109 { 0, 0, 0, 0 },
31110 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31111 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3be00 }
31112 },
31113/* mulex ${Dsp-16-u16}[sb] */
31114 {
31115 { 0, 0, 0, 0 },
31116 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31117 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5be0000 }
31118 },
31119/* mulex ${Dsp-16-s8}[fb] */
31120 {
31121 { 0, 0, 0, 0 },
31122 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31123 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3fe00 }
31124 },
31125/* mulex ${Dsp-16-s16}[fb] */
31126 {
31127 { 0, 0, 0, 0 },
31128 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31129 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5fe0000 }
31130 },
31131/* mulex ${Dsp-16-u16} */
31132 {
31133 { 0, 0, 0, 0 },
31134 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
31135 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7fe0000 }
31136 },
31137/* mulex ${Dsp-16-u24} */
31138 {
31139 { 0, 0, 0, 0 },
31140 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
31141 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7be0000 }
31142 },
31143/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31144 {
31145 { 0, 0, 0, 0 },
31146 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31147 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990c00 }
31148 },
31149/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
31150 {
31151 { 0, 0, 0, 0 },
31152 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31153 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992c00 }
31154 },
31155/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
31156 {
31157 { 0, 0, 0, 0 },
31158 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31159 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993c00 }
31160 },
31161/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31162 {
31163 { 0, 0, 0, 0 },
31164 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31165 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918c00 }
31166 },
31167/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
31168 {
31169 { 0, 0, 0, 0 },
31170 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31171 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ac00 }
31172 },
31173/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
31174 {
31175 { 0, 0, 0, 0 },
31176 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31177 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bc00 }
31178 },
31179/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31180 {
31181 { 0, 0, 0, 0 },
31182 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31183 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910c00 }
31184 },
31185/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
31186 {
31187 { 0, 0, 0, 0 },
31188 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31189 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912c00 }
31190 },
31191/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
31192 {
31193 { 0, 0, 0, 0 },
31194 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31195 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913c00 }
31196 },
31197/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31198 {
31199 { 0, 0, 0, 0 },
31200 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31201 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930c0000 }
31202 },
31203/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31204 {
31205 { 0, 0, 0, 0 },
31206 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31207 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932c0000 }
31208 },
31209/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31210 {
31211 { 0, 0, 0, 0 },
31212 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31213 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933c0000 }
31214 },
31215/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31216 {
31217 { 0, 0, 0, 0 },
31218 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31219 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950c0000 }
31220 },
31221/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31222 {
31223 { 0, 0, 0, 0 },
31224 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31225 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952c0000 }
31226 },
31227/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31228 {
31229 { 0, 0, 0, 0 },
31230 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31231 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953c0000 }
31232 },
31233/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31234 {
31235 { 0, 0, 0, 0 },
31236 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31237 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970c0000 }
31238 },
31239/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31240 {
31241 { 0, 0, 0, 0 },
31242 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31243 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972c0000 }
31244 },
31245/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31246 {
31247 { 0, 0, 0, 0 },
31248 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31249 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973c0000 }
31250 },
31251/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
31252 {
31253 { 0, 0, 0, 0 },
31254 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31255 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938c0000 }
31256 },
31257/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
31258 {
31259 { 0, 0, 0, 0 },
31260 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31261 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ac0000 }
31262 },
31263/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
31264 {
31265 { 0, 0, 0, 0 },
31266 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31267 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bc0000 }
31268 },
31269/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
31270 {
31271 { 0, 0, 0, 0 },
31272 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31273 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958c0000 }
31274 },
31275/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
31276 {
31277 { 0, 0, 0, 0 },
31278 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31279 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ac0000 }
31280 },
31281/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
31282 {
31283 { 0, 0, 0, 0 },
31284 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31285 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bc0000 }
31286 },
31287/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
31288 {
31289 { 0, 0, 0, 0 },
31290 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31291 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cc0000 }
31292 },
31293/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
31294 {
31295 { 0, 0, 0, 0 },
31296 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31297 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ec0000 }
31298 },
31299/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
31300 {
31301 { 0, 0, 0, 0 },
31302 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31303 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fc0000 }
31304 },
31305/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
31306 {
31307 { 0, 0, 0, 0 },
31308 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31309 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cc0000 }
31310 },
31311/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
31312 {
31313 { 0, 0, 0, 0 },
31314 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31315 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ec0000 }
31316 },
31317/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
31318 {
31319 { 0, 0, 0, 0 },
31320 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31321 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fc0000 }
31322 },
31323/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
31324 {
31325 { 0, 0, 0, 0 },
31326 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
31327 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cc0000 }
31328 },
31329/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
31330 {
31331 { 0, 0, 0, 0 },
31332 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
31333 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ec0000 }
31334 },
31335/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
31336 {
31337 { 0, 0, 0, 0 },
31338 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
31339 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fc0000 }
31340 },
31341/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
31342 {
31343 { 0, 0, 0, 0 },
31344 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
31345 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978c0000 }
31346 },
31347/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
31348 {
31349 { 0, 0, 0, 0 },
31350 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
31351 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ac0000 }
31352 },
31353/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
31354 {
31355 { 0, 0, 0, 0 },
31356 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
31357 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bc0000 }
31358 },
31359/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31360 {
31361 { 0, 0, 0, 0 },
31362 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31363 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90c0000 }
31364 },
31365/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
31366 {
31367 { 0, 0, 0, 0 },
31368 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31369 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92c0000 }
31370 },
31371/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
31372 {
31373 { 0, 0, 0, 0 },
31374 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31375 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93c0000 }
31376 },
31377/* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
31378 {
31379 { 0, 0, 0, 0 },
31380 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31381 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93c0000 }
31382 },
31383/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31384 {
31385 { 0, 0, 0, 0 },
31386 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31387 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18c0000 }
31388 },
31389/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
31390 {
31391 { 0, 0, 0, 0 },
31392 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31393 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ac0000 }
31394 },
31395/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
31396 {
31397 { 0, 0, 0, 0 },
31398 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31399 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bc0000 }
31400 },
31401/* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
31402 {
31403 { 0, 0, 0, 0 },
31404 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31405 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bc0000 }
31406 },
31407/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31408 {
31409 { 0, 0, 0, 0 },
31410 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31411 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10c0000 }
31412 },
31413/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
31414 {
31415 { 0, 0, 0, 0 },
31416 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31417 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12c0000 }
31418 },
31419/* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
31420 {
31421 { 0, 0, 0, 0 },
31422 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31423 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13c0000 }
31424 },
31425/* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
31426 {
31427 { 0, 0, 0, 0 },
31428 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31429 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13c0000 }
31430 },
31431/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31432 {
31433 { 0, 0, 0, 0 },
31434 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31435 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30c0000 }
31436 },
31437/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31438 {
31439 { 0, 0, 0, 0 },
31440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31441 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32c0000 }
31442 },
31443/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31444 {
31445 { 0, 0, 0, 0 },
31446 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31447 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33c0000 }
31448 },
31449/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
31450 {
31451 { 0, 0, 0, 0 },
31452 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31453 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33c0000 }
31454 },
31455/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31456 {
31457 { 0, 0, 0, 0 },
31458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31459 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50c0000 }
31460 },
31461/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31462 {
31463 { 0, 0, 0, 0 },
31464 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31465 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52c0000 }
31466 },
31467/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31468 {
31469 { 0, 0, 0, 0 },
31470 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31471 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53c0000 }
31472 },
31473/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
31474 {
31475 { 0, 0, 0, 0 },
31476 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31477 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53c0000 }
31478 },
31479/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31480 {
31481 { 0, 0, 0, 0 },
31482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31483 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70c0000 }
31484 },
31485/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31486 {
31487 { 0, 0, 0, 0 },
31488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31489 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72c0000 }
31490 },
31491/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31492 {
31493 { 0, 0, 0, 0 },
31494 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31495 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73c0000 }
31496 },
31497/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
31498 {
31499 { 0, 0, 0, 0 },
31500 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31501 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73c0000 }
31502 },
31503/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
31504 {
31505 { 0, 0, 0, 0 },
31506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31507 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38c0000 }
31508 },
31509/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
31510 {
31511 { 0, 0, 0, 0 },
31512 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31513 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ac0000 }
31514 },
31515/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
31516 {
31517 { 0, 0, 0, 0 },
31518 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31519 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bc0000 }
31520 },
31521/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
31522 {
31523 { 0, 0, 0, 0 },
31524 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31525 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bc0000 }
31526 },
31527/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
31528 {
31529 { 0, 0, 0, 0 },
31530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31531 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58c0000 }
31532 },
31533/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
31534 {
31535 { 0, 0, 0, 0 },
31536 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31537 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ac0000 }
31538 },
31539/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
31540 {
31541 { 0, 0, 0, 0 },
31542 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31543 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bc0000 }
31544 },
31545/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
31546 {
31547 { 0, 0, 0, 0 },
31548 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31549 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bc0000 }
31550 },
31551/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
31552 {
31553 { 0, 0, 0, 0 },
31554 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31555 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cc0000 }
31556 },
31557/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
31558 {
31559 { 0, 0, 0, 0 },
31560 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31561 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ec0000 }
31562 },
31563/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
31564 {
31565 { 0, 0, 0, 0 },
31566 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31567 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fc0000 }
31568 },
31569/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
31570 {
31571 { 0, 0, 0, 0 },
31572 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31573 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fc0000 }
31574 },
31575/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
31576 {
31577 { 0, 0, 0, 0 },
31578 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31579 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cc0000 }
31580 },
31581/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
31582 {
31583 { 0, 0, 0, 0 },
31584 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31585 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ec0000 }
31586 },
31587/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
31588 {
31589 { 0, 0, 0, 0 },
31590 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31591 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fc0000 }
31592 },
31593/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
31594 {
31595 { 0, 0, 0, 0 },
31596 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31597 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fc0000 }
31598 },
31599/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
31600 {
31601 { 0, 0, 0, 0 },
31602 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
31603 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cc0000 }
31604 },
31605/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
31606 {
31607 { 0, 0, 0, 0 },
31608 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
31609 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ec0000 }
31610 },
31611/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
31612 {
31613 { 0, 0, 0, 0 },
31614 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
31615 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fc0000 }
31616 },
31617/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
31618 {
31619 { 0, 0, 0, 0 },
31620 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
31621 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fc0000 }
31622 },
31623/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
31624 {
31625 { 0, 0, 0, 0 },
31626 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
31627 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78c0000 }
31628 },
31629/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
31630 {
31631 { 0, 0, 0, 0 },
31632 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
31633 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ac0000 }
31634 },
31635/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
31636 {
31637 { 0, 0, 0, 0 },
31638 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
31639 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bc0000 }
31640 },
31641/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
31642 {
31643 { 0, 0, 0, 0 },
31644 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
31645 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bc0000 }
31646 },
31647/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31648 {
31649 { 0, 0, 0, 0 },
31650 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31651 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90c0000 }
31652 },
31653/* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
31654 {
31655 { 0, 0, 0, 0 },
31656 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31657 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92c0000 }
31658 },
31659/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31660 {
31661 { 0, 0, 0, 0 },
31662 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31663 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18c0000 }
31664 },
31665/* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
31666 {
31667 { 0, 0, 0, 0 },
31668 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31669 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ac0000 }
31670 },
31671/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31672 {
31673 { 0, 0, 0, 0 },
31674 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31675 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10c0000 }
31676 },
31677/* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
31678 {
31679 { 0, 0, 0, 0 },
31680 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31681 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12c0000 }
31682 },
31683/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
31684 {
31685 { 0, 0, 0, 0 },
31686 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31687 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30c0000 }
31688 },
31689/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
31690 {
31691 { 0, 0, 0, 0 },
31692 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31693 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32c0000 }
31694 },
31695/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
31696 {
31697 { 0, 0, 0, 0 },
31698 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31699 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50c0000 }
31700 },
31701/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
31702 {
31703 { 0, 0, 0, 0 },
31704 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31705 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52c0000 }
31706 },
31707/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
31708 {
31709 { 0, 0, 0, 0 },
31710 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31711 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70c0000 }
31712 },
31713/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
31714 {
31715 { 0, 0, 0, 0 },
31716 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31717 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72c0000 }
31718 },
31719/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
31720 {
31721 { 0, 0, 0, 0 },
31722 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
31723 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38c0000 }
31724 },
31725/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
31726 {
31727 { 0, 0, 0, 0 },
31728 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
31729 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ac0000 }
31730 },
31731/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
31732 {
31733 { 0, 0, 0, 0 },
31734 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
31735 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58c0000 }
31736 },
31737/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
31738 {
31739 { 0, 0, 0, 0 },
31740 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
31741 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ac0000 }
31742 },
31743/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
31744 {
31745 { 0, 0, 0, 0 },
31746 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
31747 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cc0000 }
31748 },
31749/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
31750 {
31751 { 0, 0, 0, 0 },
31752 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
31753 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ec0000 }
31754 },
31755/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
31756 {
31757 { 0, 0, 0, 0 },
31758 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
31759 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cc0000 }
31760 },
31761/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
31762 {
31763 { 0, 0, 0, 0 },
31764 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
31765 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ec0000 }
31766 },
31767/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
31768 {
31769 { 0, 0, 0, 0 },
31770 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
31771 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cc0000 }
31772 },
31773/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
31774 {
31775 { 0, 0, 0, 0 },
31776 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
31777 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ec0000 }
31778 },
31779/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
31780 {
31781 { 0, 0, 0, 0 },
31782 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
31783 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78c0000 }
31784 },
31785/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
31786 {
31787 { 0, 0, 0, 0 },
31788 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
31789 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ac0000 }
31790 },
31791/* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
31792 {
31793 { 0, 0, 0, 0 },
31794 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31795 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90c }
31796 },
31797/* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
31798 {
31799 { 0, 0, 0, 0 },
31800 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31801 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892c }
31802 },
31803/* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31804 {
31805 { 0, 0, 0, 0 },
31806 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31807 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890c }
31808 },
31809/* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
31810 {
31811 { 0, 0, 0, 0 },
31812 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31813 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18c }
31814 },
31815/* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
31816 {
31817 { 0, 0, 0, 0 },
31818 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31819 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ac }
31820 },
31821/* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31822 {
31823 { 0, 0, 0, 0 },
31824 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31825 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818c }
31826 },
31827/* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
31828 {
31829 { 0, 0, 0, 0 },
31830 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31831 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10c }
31832 },
31833/* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
31834 {
31835 { 0, 0, 0, 0 },
31836 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31837 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812c }
31838 },
31839/* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31840 {
31841 { 0, 0, 0, 0 },
31842 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31843 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810c }
31844 },
31845/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
31846 {
31847 { 0, 0, 0, 0 },
31848 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31849 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30c00 }
31850 },
31851/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
31852 {
31853 { 0, 0, 0, 0 },
31854 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31855 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832c00 }
31856 },
31857/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
31858 {
31859 { 0, 0, 0, 0 },
31860 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31861 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830c00 }
31862 },
31863/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
31864 {
31865 { 0, 0, 0, 0 },
31866 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31867 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50c0000 }
31868 },
31869/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
31870 {
31871 { 0, 0, 0, 0 },
31872 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31873 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852c0000 }
31874 },
31875/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
31876 {
31877 { 0, 0, 0, 0 },
31878 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31879 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850c0000 }
31880 },
31881/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
31882 {
31883 { 0, 0, 0, 0 },
31884 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31885 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70c0000 }
31886 },
31887/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
31888 {
31889 { 0, 0, 0, 0 },
31890 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31891 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872c0000 }
31892 },
31893/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
31894 {
31895 { 0, 0, 0, 0 },
31896 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31897 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870c0000 }
31898 },
31899/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
31900 {
31901 { 0, 0, 0, 0 },
31902 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31903 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38c00 }
31904 },
31905/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
31906 {
31907 { 0, 0, 0, 0 },
31908 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31909 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ac00 }
31910 },
31911/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
31912 {
31913 { 0, 0, 0, 0 },
31914 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31915 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838c00 }
31916 },
31917/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
31918 {
31919 { 0, 0, 0, 0 },
31920 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31921 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58c0000 }
31922 },
31923/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
31924 {
31925 { 0, 0, 0, 0 },
31926 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31927 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ac0000 }
31928 },
31929/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
31930 {
31931 { 0, 0, 0, 0 },
31932 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31933 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858c0000 }
31934 },
31935/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
31936 {
31937 { 0, 0, 0, 0 },
31938 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31939 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cc00 }
31940 },
31941/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
31942 {
31943 { 0, 0, 0, 0 },
31944 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31945 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ec00 }
31946 },
31947/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
31948 {
31949 { 0, 0, 0, 0 },
31950 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31951 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cc00 }
31952 },
31953/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
31954 {
31955 { 0, 0, 0, 0 },
31956 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31957 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cc0000 }
31958 },
31959/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
31960 {
31961 { 0, 0, 0, 0 },
31962 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31963 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ec0000 }
31964 },
31965/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
31966 {
31967 { 0, 0, 0, 0 },
31968 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31969 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cc0000 }
31970 },
31971/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
31972 {
31973 { 0, 0, 0, 0 },
31974 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
31975 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cc0000 }
31976 },
31977/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
31978 {
31979 { 0, 0, 0, 0 },
31980 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
31981 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ec0000 }
31982 },
31983/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
31984 {
31985 { 0, 0, 0, 0 },
31986 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
31987 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cc0000 }
31988 },
31989/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
31990 {
31991 { 0, 0, 0, 0 },
31992 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
31993 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78c0000 }
31994 },
31995/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
31996 {
31997 { 0, 0, 0, 0 },
31998 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
31999 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ac0000 }
32000 },
32001/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
32002 {
32003 { 0, 0, 0, 0 },
32004 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
32005 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878c0000 }
32006 },
32007/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32008 {
32009 { 0, 0, 0, 0 },
32010 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32011 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980c00 }
32012 },
32013/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
32014 {
32015 { 0, 0, 0, 0 },
32016 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32017 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982c00 }
32018 },
32019/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
32020 {
32021 { 0, 0, 0, 0 },
32022 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32023 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983c00 }
32024 },
32025/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32026 {
32027 { 0, 0, 0, 0 },
32028 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32029 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908c00 }
32030 },
32031/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
32032 {
32033 { 0, 0, 0, 0 },
32034 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32035 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ac00 }
32036 },
32037/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
32038 {
32039 { 0, 0, 0, 0 },
32040 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32041 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bc00 }
32042 },
32043/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32044 {
32045 { 0, 0, 0, 0 },
32046 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32047 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900c00 }
32048 },
32049/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
32050 {
32051 { 0, 0, 0, 0 },
32052 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32053 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902c00 }
32054 },
32055/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
32056 {
32057 { 0, 0, 0, 0 },
32058 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32059 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903c00 }
32060 },
32061/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32062 {
32063 { 0, 0, 0, 0 },
32064 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32065 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920c0000 }
32066 },
32067/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32068 {
32069 { 0, 0, 0, 0 },
32070 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32071 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922c0000 }
32072 },
32073/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32074 {
32075 { 0, 0, 0, 0 },
32076 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32077 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923c0000 }
32078 },
32079/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32080 {
32081 { 0, 0, 0, 0 },
32082 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32083 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940c0000 }
32084 },
32085/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32086 {
32087 { 0, 0, 0, 0 },
32088 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32089 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942c0000 }
32090 },
32091/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32092 {
32093 { 0, 0, 0, 0 },
32094 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32095 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943c0000 }
32096 },
32097/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32098 {
32099 { 0, 0, 0, 0 },
32100 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32101 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960c0000 }
32102 },
32103/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32104 {
32105 { 0, 0, 0, 0 },
32106 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32107 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962c0000 }
32108 },
32109/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32110 {
32111 { 0, 0, 0, 0 },
32112 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32113 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963c0000 }
32114 },
32115/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
32116 {
32117 { 0, 0, 0, 0 },
32118 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32119 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928c0000 }
32120 },
32121/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
32122 {
32123 { 0, 0, 0, 0 },
32124 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32125 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ac0000 }
32126 },
32127/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
32128 {
32129 { 0, 0, 0, 0 },
32130 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32131 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bc0000 }
32132 },
32133/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
32134 {
32135 { 0, 0, 0, 0 },
32136 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32137 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948c0000 }
32138 },
32139/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
32140 {
32141 { 0, 0, 0, 0 },
32142 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32143 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ac0000 }
32144 },
32145/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
32146 {
32147 { 0, 0, 0, 0 },
32148 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32149 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bc0000 }
32150 },
32151/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
32152 {
32153 { 0, 0, 0, 0 },
32154 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32155 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cc0000 }
32156 },
32157/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
32158 {
32159 { 0, 0, 0, 0 },
32160 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32161 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ec0000 }
32162 },
32163/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
32164 {
32165 { 0, 0, 0, 0 },
32166 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32167 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fc0000 }
32168 },
32169/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
32170 {
32171 { 0, 0, 0, 0 },
32172 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32173 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cc0000 }
32174 },
32175/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
32176 {
32177 { 0, 0, 0, 0 },
32178 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32179 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ec0000 }
32180 },
32181/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
32182 {
32183 { 0, 0, 0, 0 },
32184 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32185 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fc0000 }
32186 },
32187/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
32188 {
32189 { 0, 0, 0, 0 },
32190 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
32191 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cc0000 }
32192 },
32193/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
32194 {
32195 { 0, 0, 0, 0 },
32196 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
32197 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ec0000 }
32198 },
32199/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
32200 {
32201 { 0, 0, 0, 0 },
32202 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
32203 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fc0000 }
32204 },
32205/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
32206 {
32207 { 0, 0, 0, 0 },
32208 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
32209 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968c0000 }
32210 },
32211/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
32212 {
32213 { 0, 0, 0, 0 },
32214 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
32215 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ac0000 }
32216 },
32217/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
32218 {
32219 { 0, 0, 0, 0 },
32220 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
32221 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bc0000 }
32222 },
32223/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32224 {
32225 { 0, 0, 0, 0 },
32226 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32227 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80c0000 }
32228 },
32229/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
32230 {
32231 { 0, 0, 0, 0 },
32232 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32233 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82c0000 }
32234 },
32235/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
32236 {
32237 { 0, 0, 0, 0 },
32238 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32239 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83c0000 }
32240 },
32241/* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
32242 {
32243 { 0, 0, 0, 0 },
32244 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32245 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83c0000 }
32246 },
32247/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32248 {
32249 { 0, 0, 0, 0 },
32250 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32251 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08c0000 }
32252 },
32253/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
32254 {
32255 { 0, 0, 0, 0 },
32256 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32257 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ac0000 }
32258 },
32259/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
32260 {
32261 { 0, 0, 0, 0 },
32262 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32263 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bc0000 }
32264 },
32265/* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
32266 {
32267 { 0, 0, 0, 0 },
32268 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32269 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bc0000 }
32270 },
32271/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32272 {
32273 { 0, 0, 0, 0 },
32274 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32275 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00c0000 }
32276 },
32277/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
32278 {
32279 { 0, 0, 0, 0 },
32280 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32281 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02c0000 }
32282 },
32283/* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
32284 {
32285 { 0, 0, 0, 0 },
32286 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32287 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03c0000 }
32288 },
32289/* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
32290 {
32291 { 0, 0, 0, 0 },
32292 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32293 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03c0000 }
32294 },
32295/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32296 {
32297 { 0, 0, 0, 0 },
32298 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32299 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20c0000 }
32300 },
32301/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32302 {
32303 { 0, 0, 0, 0 },
32304 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32305 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22c0000 }
32306 },
32307/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32308 {
32309 { 0, 0, 0, 0 },
32310 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32311 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23c0000 }
32312 },
32313/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
32314 {
32315 { 0, 0, 0, 0 },
32316 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32317 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23c0000 }
32318 },
32319/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32320 {
32321 { 0, 0, 0, 0 },
32322 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32323 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40c0000 }
32324 },
32325/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32326 {
32327 { 0, 0, 0, 0 },
32328 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32329 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42c0000 }
32330 },
32331/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32332 {
32333 { 0, 0, 0, 0 },
32334 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32335 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43c0000 }
32336 },
32337/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
32338 {
32339 { 0, 0, 0, 0 },
32340 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32341 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43c0000 }
32342 },
32343/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32344 {
32345 { 0, 0, 0, 0 },
32346 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32347 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60c0000 }
32348 },
32349/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32350 {
32351 { 0, 0, 0, 0 },
32352 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32353 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62c0000 }
32354 },
32355/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32356 {
32357 { 0, 0, 0, 0 },
32358 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32359 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63c0000 }
32360 },
32361/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
32362 {
32363 { 0, 0, 0, 0 },
32364 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32365 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63c0000 }
32366 },
32367/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
32368 {
32369 { 0, 0, 0, 0 },
32370 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32371 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28c0000 }
32372 },
32373/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
32374 {
32375 { 0, 0, 0, 0 },
32376 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32377 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ac0000 }
32378 },
32379/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
32380 {
32381 { 0, 0, 0, 0 },
32382 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32383 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bc0000 }
32384 },
32385/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
32386 {
32387 { 0, 0, 0, 0 },
32388 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32389 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bc0000 }
32390 },
32391/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
32392 {
32393 { 0, 0, 0, 0 },
32394 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32395 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48c0000 }
32396 },
32397/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
32398 {
32399 { 0, 0, 0, 0 },
32400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32401 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ac0000 }
32402 },
32403/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
32404 {
32405 { 0, 0, 0, 0 },
32406 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32407 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bc0000 }
32408 },
32409/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
32410 {
32411 { 0, 0, 0, 0 },
32412 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32413 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bc0000 }
32414 },
32415/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
32416 {
32417 { 0, 0, 0, 0 },
32418 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32419 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cc0000 }
32420 },
32421/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
32422 {
32423 { 0, 0, 0, 0 },
32424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32425 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ec0000 }
32426 },
32427/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
32428 {
32429 { 0, 0, 0, 0 },
32430 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32431 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fc0000 }
32432 },
32433/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
32434 {
32435 { 0, 0, 0, 0 },
32436 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32437 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fc0000 }
32438 },
32439/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
32440 {
32441 { 0, 0, 0, 0 },
32442 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32443 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cc0000 }
32444 },
32445/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
32446 {
32447 { 0, 0, 0, 0 },
32448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32449 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ec0000 }
32450 },
32451/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
32452 {
32453 { 0, 0, 0, 0 },
32454 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32455 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fc0000 }
32456 },
32457/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
32458 {
32459 { 0, 0, 0, 0 },
32460 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32461 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fc0000 }
32462 },
32463/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
32464 {
32465 { 0, 0, 0, 0 },
32466 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
32467 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cc0000 }
32468 },
32469/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
32470 {
32471 { 0, 0, 0, 0 },
32472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
32473 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ec0000 }
32474 },
32475/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
32476 {
32477 { 0, 0, 0, 0 },
32478 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
32479 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fc0000 }
32480 },
32481/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
32482 {
32483 { 0, 0, 0, 0 },
32484 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
32485 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fc0000 }
32486 },
32487/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
32488 {
32489 { 0, 0, 0, 0 },
32490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
32491 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68c0000 }
32492 },
32493/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
32494 {
32495 { 0, 0, 0, 0 },
32496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32497 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ac0000 }
32498 },
32499/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
32500 {
32501 { 0, 0, 0, 0 },
32502 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32503 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bc0000 }
32504 },
32505/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
32506 {
32507 { 0, 0, 0, 0 },
32508 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
32509 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bc0000 }
32510 },
32511/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32512 {
32513 { 0, 0, 0, 0 },
32514 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32515 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80c0000 }
32516 },
32517/* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
32518 {
32519 { 0, 0, 0, 0 },
32520 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32521 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82c0000 }
32522 },
32523/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32524 {
32525 { 0, 0, 0, 0 },
32526 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32527 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08c0000 }
32528 },
32529/* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
32530 {
32531 { 0, 0, 0, 0 },
32532 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32533 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ac0000 }
32534 },
32535/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32536 {
32537 { 0, 0, 0, 0 },
32538 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32539 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00c0000 }
32540 },
32541/* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
32542 {
32543 { 0, 0, 0, 0 },
32544 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32545 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02c0000 }
32546 },
32547/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
32548 {
32549 { 0, 0, 0, 0 },
32550 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32551 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20c0000 }
32552 },
32553/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
32554 {
32555 { 0, 0, 0, 0 },
32556 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32557 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22c0000 }
32558 },
32559/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
32560 {
32561 { 0, 0, 0, 0 },
32562 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32563 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40c0000 }
32564 },
32565/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
32566 {
32567 { 0, 0, 0, 0 },
32568 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32569 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42c0000 }
32570 },
32571/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
32572 {
32573 { 0, 0, 0, 0 },
32574 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32575 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60c0000 }
32576 },
32577/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
32578 {
32579 { 0, 0, 0, 0 },
32580 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32581 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62c0000 }
32582 },
32583/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
32584 {
32585 { 0, 0, 0, 0 },
32586 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32587 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28c0000 }
32588 },
32589/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
32590 {
32591 { 0, 0, 0, 0 },
32592 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32593 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ac0000 }
32594 },
32595/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
32596 {
32597 { 0, 0, 0, 0 },
32598 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32599 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48c0000 }
32600 },
32601/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
32602 {
32603 { 0, 0, 0, 0 },
32604 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32605 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ac0000 }
32606 },
32607/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
32608 {
32609 { 0, 0, 0, 0 },
32610 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32611 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cc0000 }
32612 },
32613/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
32614 {
32615 { 0, 0, 0, 0 },
32616 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32617 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ec0000 }
32618 },
32619/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
32620 {
32621 { 0, 0, 0, 0 },
32622 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
32623 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cc0000 }
32624 },
32625/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
32626 {
32627 { 0, 0, 0, 0 },
32628 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
32629 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ec0000 }
32630 },
32631/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
32632 {
32633 { 0, 0, 0, 0 },
32634 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
32635 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cc0000 }
32636 },
32637/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
32638 {
32639 { 0, 0, 0, 0 },
32640 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
32641 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ec0000 }
32642 },
32643/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
32644 {
32645 { 0, 0, 0, 0 },
32646 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
32647 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68c0000 }
32648 },
32649/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
32650 {
32651 { 0, 0, 0, 0 },
32652 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
32653 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ac0000 }
32654 },
32655/* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
32656 {
32657 { 0, 0, 0, 0 },
32658 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32659 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80c }
32660 },
32661/* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
32662 {
32663 { 0, 0, 0, 0 },
32664 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32665 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882c }
32666 },
32667/* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32668 {
32669 { 0, 0, 0, 0 },
32670 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32671 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880c }
32672 },
32673/* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
32674 {
32675 { 0, 0, 0, 0 },
32676 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32677 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08c }
32678 },
32679/* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
32680 {
32681 { 0, 0, 0, 0 },
32682 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32683 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ac }
32684 },
32685/* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32686 {
32687 { 0, 0, 0, 0 },
32688 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32689 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808c }
32690 },
32691/* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
32692 {
32693 { 0, 0, 0, 0 },
32694 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32695 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00c }
32696 },
32697/* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
32698 {
32699 { 0, 0, 0, 0 },
32700 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32701 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802c }
32702 },
32703/* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32704 {
32705 { 0, 0, 0, 0 },
32706 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32707 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800c }
32708 },
32709/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
32710 {
32711 { 0, 0, 0, 0 },
32712 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32713 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20c00 }
32714 },
32715/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
32716 {
32717 { 0, 0, 0, 0 },
32718 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32719 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822c00 }
32720 },
32721/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
32722 {
32723 { 0, 0, 0, 0 },
32724 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32725 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820c00 }
32726 },
32727/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
32728 {
32729 { 0, 0, 0, 0 },
32730 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32731 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40c0000 }
32732 },
32733/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
32734 {
32735 { 0, 0, 0, 0 },
32736 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32737 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842c0000 }
32738 },
32739/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
32740 {
32741 { 0, 0, 0, 0 },
32742 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32743 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840c0000 }
32744 },
32745/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
32746 {
32747 { 0, 0, 0, 0 },
32748 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32749 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60c0000 }
32750 },
32751/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
32752 {
32753 { 0, 0, 0, 0 },
32754 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32755 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862c0000 }
32756 },
32757/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
32758 {
32759 { 0, 0, 0, 0 },
32760 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32761 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860c0000 }
32762 },
32763/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
32764 {
32765 { 0, 0, 0, 0 },
32766 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32767 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28c00 }
32768 },
32769/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
32770 {
32771 { 0, 0, 0, 0 },
32772 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32773 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ac00 }
32774 },
32775/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
32776 {
32777 { 0, 0, 0, 0 },
32778 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32779 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828c00 }
32780 },
32781/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
32782 {
32783 { 0, 0, 0, 0 },
32784 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32785 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48c0000 }
32786 },
32787/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
32788 {
32789 { 0, 0, 0, 0 },
32790 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32791 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ac0000 }
32792 },
32793/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
32794 {
32795 { 0, 0, 0, 0 },
32796 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32797 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848c0000 }
32798 },
32799/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
32800 {
32801 { 0, 0, 0, 0 },
32802 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32803 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cc00 }
32804 },
32805/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
32806 {
32807 { 0, 0, 0, 0 },
32808 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32809 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ec00 }
32810 },
32811/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
32812 {
32813 { 0, 0, 0, 0 },
32814 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32815 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cc00 }
32816 },
32817/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
32818 {
32819 { 0, 0, 0, 0 },
32820 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32821 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cc0000 }
32822 },
32823/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
32824 {
32825 { 0, 0, 0, 0 },
32826 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32827 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ec0000 }
32828 },
32829/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
32830 {
32831 { 0, 0, 0, 0 },
32832 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32833 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cc0000 }
32834 },
32835/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
32836 {
32837 { 0, 0, 0, 0 },
32838 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
32839 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cc0000 }
32840 },
32841/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
32842 {
32843 { 0, 0, 0, 0 },
32844 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
32845 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ec0000 }
32846 },
32847/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
32848 {
32849 { 0, 0, 0, 0 },
32850 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
32851 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cc0000 }
32852 },
32853/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
32854 {
32855 { 0, 0, 0, 0 },
32856 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
32857 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68c0000 }
32858 },
32859/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
32860 {
32861 { 0, 0, 0, 0 },
32862 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
32863 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ac0000 }
32864 },
32865/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
32866 {
32867 { 0, 0, 0, 0 },
32868 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
32869 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868c0000 }
32870 },
32871/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
32872 {
32873 { 0, 0, 0, 0 },
32874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
32875 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x798000 }
32876 },
32877/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
32878 {
32879 { 0, 0, 0, 0 },
32880 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
32881 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x79a000 }
32882 },
32883/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
32884 {
32885 { 0, 0, 0, 0 },
32886 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
32887 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x79b000 }
32888 },
32889/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
32890 {
32891 { 0, 0, 0, 0 },
32892 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
32893 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x798400 }
32894 },
32895/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
32896 {
32897 { 0, 0, 0, 0 },
32898 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
32899 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x79a400 }
32900 },
32901/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
32902 {
32903 { 0, 0, 0, 0 },
32904 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
32905 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x79b400 }
32906 },
32907/* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
32908 {
32909 { 0, 0, 0, 0 },
32910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
32911 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x798600 }
32912 },
32913/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
32914 {
32915 { 0, 0, 0, 0 },
32916 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
32917 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x79a600 }
32918 },
32919/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
32920 {
32921 { 0, 0, 0, 0 },
32922 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
32923 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x79b600 }
32924 },
32925/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
32926 {
32927 { 0, 0, 0, 0 },
32928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
32929 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x79880000 }
32930 },
32931/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
32932 {
32933 { 0, 0, 0, 0 },
32934 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
32935 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x79a80000 }
32936 },
32937/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
32938 {
32939 { 0, 0, 0, 0 },
32940 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
32941 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x79b80000 }
32942 },
32943/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
32944 {
32945 { 0, 0, 0, 0 },
32946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
32947 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x798c0000 }
32948 },
32949/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
32950 {
32951 { 0, 0, 0, 0 },
32952 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
32953 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x79ac0000 }
32954 },
32955/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
32956 {
32957 { 0, 0, 0, 0 },
32958 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
32959 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x79bc0000 }
32960 },
32961/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
32962 {
32963 { 0, 0, 0, 0 },
32964 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32965 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x798a0000 }
32966 },
32967/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
32968 {
32969 { 0, 0, 0, 0 },
32970 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32971 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79aa0000 }
32972 },
32973/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
32974 {
32975 { 0, 0, 0, 0 },
32976 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32977 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79ba0000 }
32978 },
32979/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
32980 {
32981 { 0, 0, 0, 0 },
32982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32983 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x798e0000 }
32984 },
32985/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
32986 {
32987 { 0, 0, 0, 0 },
32988 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32989 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79ae0000 }
32990 },
32991/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
32992 {
32993 { 0, 0, 0, 0 },
32994 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32995 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79be0000 }
32996 },
32997/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
32998 {
32999 { 0, 0, 0, 0 },
33000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33001 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x798b0000 }
33002 },
33003/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
33004 {
33005 { 0, 0, 0, 0 },
33006 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33007 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79ab0000 }
33008 },
33009/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
33010 {
33011 { 0, 0, 0, 0 },
33012 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33013 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79bb0000 }
33014 },
33015/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
33016 {
33017 { 0, 0, 0, 0 },
33018 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
33019 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x798f0000 }
33020 },
33021/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
33022 {
33023 { 0, 0, 0, 0 },
33024 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33025 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x79af0000 }
33026 },
33027/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
33028 {
33029 { 0, 0, 0, 0 },
33030 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33031 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x79bf0000 }
33032 },
33033/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
33034 {
33035 { 0, 0, 0, 0 },
33036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33037 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x79c00000 }
33038 },
33039/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
33040 {
33041 { 0, 0, 0, 0 },
33042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
33043 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x79e00000 }
33044 },
33045/* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
33046 {
33047 { 0, 0, 0, 0 },
33048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
33049 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x79f00000 }
33050 },
33051/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
33052 {
33053 { 0, 0, 0, 0 },
33054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33055 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x79c40000 }
33056 },
33057/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
33058 {
33059 { 0, 0, 0, 0 },
33060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
33061 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x79e40000 }
33062 },
33063/* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
33064 {
33065 { 0, 0, 0, 0 },
33066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
33067 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x79f40000 }
33068 },
33069/* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
33070 {
33071 { 0, 0, 0, 0 },
33072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33073 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x79c60000 }
33074 },
33075/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
33076 {
33077 { 0, 0, 0, 0 },
33078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33079 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x79e60000 }
33080 },
33081/* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
33082 {
33083 { 0, 0, 0, 0 },
33084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
33085 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x79f60000 }
33086 },
33087/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
33088 {
33089 { 0, 0, 0, 0 },
33090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33091 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x79c80000 }
33092 },
33093/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
33094 {
33095 { 0, 0, 0, 0 },
33096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33097 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x79e80000 }
33098 },
33099/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
33100 {
33101 { 0, 0, 0, 0 },
33102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33103 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x79f80000 }
33104 },
33105/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
33106 {
33107 { 0, 0, 0, 0 },
33108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33109 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x79cc0000 }
33110 },
33111/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
33112 {
33113 { 0, 0, 0, 0 },
33114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33115 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x79ec0000 }
33116 },
33117/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
33118 {
33119 { 0, 0, 0, 0 },
33120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33121 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x79fc0000 }
33122 },
33123/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
33124 {
33125 { 0, 0, 0, 0 },
33126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33127 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ca0000 }
33128 },
33129/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
33130 {
33131 { 0, 0, 0, 0 },
33132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33133 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ea0000 }
33134 },
33135/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
33136 {
33137 { 0, 0, 0, 0 },
33138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33139 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x79fa0000 }
33140 },
33141/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
33142 {
33143 { 0, 0, 0, 0 },
33144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33145 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ce0000 }
33146 },
33147/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
33148 {
33149 { 0, 0, 0, 0 },
33150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33151 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ee0000 }
33152 },
33153/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
33154 {
33155 { 0, 0, 0, 0 },
33156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33157 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x79fe0000 }
33158 },
33159/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
33160 {
33161 { 0, 0, 0, 0 },
33162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33163 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x79cb0000 }
33164 },
33165/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
33166 {
33167 { 0, 0, 0, 0 },
33168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33169 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x79eb0000 }
33170 },
33171/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
33172 {
33173 { 0, 0, 0, 0 },
33174 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33175 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x79fb0000 }
33176 },
33177/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
33178 {
33179 { 0, 0, 0, 0 },
33180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
33181 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x79cf0000 }
33182 },
33183/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
33184 {
33185 { 0, 0, 0, 0 },
33186 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
33187 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x79ef0000 }
33188 },
33189/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
33190 {
33191 { 0, 0, 0, 0 },
33192 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
33193 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x79ff0000 }
33194 },
33195/* mul.w${G} $Src16RnHI,$Dst16RnHI */
33196 {
33197 { 0, 0, 0, 0 },
33198 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
33199 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7900 }
33200 },
33201/* mul.w${G} $Src16AnHI,$Dst16RnHI */
33202 {
33203 { 0, 0, 0, 0 },
33204 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
33205 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7940 }
33206 },
33207/* mul.w${G} [$Src16An],$Dst16RnHI */
33208 {
33209 { 0, 0, 0, 0 },
33210 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33211 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7960 }
33212 },
33213/* mul.w${G} $Src16RnHI,$Dst16AnHI */
33214 {
33215 { 0, 0, 0, 0 },
33216 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
33217 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7904 }
33218 },
33219/* mul.w${G} $Src16AnHI,$Dst16AnHI */
33220 {
33221 { 0, 0, 0, 0 },
33222 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
33223 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7944 }
33224 },
33225/* mul.w${G} [$Src16An],$Dst16AnHI */
33226 {
33227 { 0, 0, 0, 0 },
33228 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33229 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7964 }
33230 },
33231/* mul.w${G} $Src16RnHI,[$Dst16An] */
33232 {
33233 { 0, 0, 0, 0 },
33234 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
33235 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7906 }
33236 },
33237/* mul.w${G} $Src16AnHI,[$Dst16An] */
33238 {
33239 { 0, 0, 0, 0 },
33240 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
33241 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7946 }
33242 },
33243/* mul.w${G} [$Src16An],[$Dst16An] */
33244 {
33245 { 0, 0, 0, 0 },
33246 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33247 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7966 }
33248 },
33249/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
33250 {
33251 { 0, 0, 0, 0 },
33252 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33253 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x790800 }
33254 },
33255/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
33256 {
33257 { 0, 0, 0, 0 },
33258 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33259 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x794800 }
33260 },
33261/* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
33262 {
33263 { 0, 0, 0, 0 },
33264 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33265 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x796800 }
33266 },
33267/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
33268 {
33269 { 0, 0, 0, 0 },
33270 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33271 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x790c0000 }
33272 },
33273/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
33274 {
33275 { 0, 0, 0, 0 },
33276 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33277 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x794c0000 }
33278 },
33279/* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
33280 {
33281 { 0, 0, 0, 0 },
33282 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33283 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x796c0000 }
33284 },
33285/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
33286 {
33287 { 0, 0, 0, 0 },
33288 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33289 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x790a00 }
33290 },
33291/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
33292 {
33293 { 0, 0, 0, 0 },
33294 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33295 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x794a00 }
33296 },
33297/* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
33298 {
33299 { 0, 0, 0, 0 },
33300 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33301 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x796a00 }
33302 },
33303/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
33304 {
33305 { 0, 0, 0, 0 },
33306 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33307 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x790e0000 }
33308 },
33309/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
33310 {
33311 { 0, 0, 0, 0 },
33312 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33313 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x794e0000 }
33314 },
33315/* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
33316 {
33317 { 0, 0, 0, 0 },
33318 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33319 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x796e0000 }
33320 },
33321/* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
33322 {
33323 { 0, 0, 0, 0 },
33324 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33325 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x790b00 }
33326 },
33327/* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
33328 {
33329 { 0, 0, 0, 0 },
33330 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33331 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x794b00 }
33332 },
33333/* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
33334 {
33335 { 0, 0, 0, 0 },
33336 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33337 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x796b00 }
33338 },
33339/* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
33340 {
33341 { 0, 0, 0, 0 },
33342 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
33343 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x790f0000 }
33344 },
33345/* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
33346 {
33347 { 0, 0, 0, 0 },
33348 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
33349 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x794f0000 }
33350 },
33351/* mul.w${G} [$Src16An],${Dsp-16-u16} */
33352 {
33353 { 0, 0, 0, 0 },
33354 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
33355 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x796f0000 }
33356 },
33357/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
33358 {
33359 { 0, 0, 0, 0 },
33360 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
33361 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x788000 }
33362 },
33363/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
33364 {
33365 { 0, 0, 0, 0 },
33366 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
33367 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x78a000 }
33368 },
33369/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
33370 {
33371 { 0, 0, 0, 0 },
33372 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
33373 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x78b000 }
33374 },
33375/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
33376 {
33377 { 0, 0, 0, 0 },
33378 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
33379 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x788400 }
33380 },
33381/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
33382 {
33383 { 0, 0, 0, 0 },
33384 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
33385 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x78a400 }
33386 },
33387/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
33388 {
33389 { 0, 0, 0, 0 },
33390 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
33391 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x78b400 }
33392 },
33393/* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
33394 {
33395 { 0, 0, 0, 0 },
33396 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33397 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x788600 }
33398 },
33399/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
33400 {
33401 { 0, 0, 0, 0 },
33402 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33403 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x78a600 }
33404 },
33405/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
33406 {
33407 { 0, 0, 0, 0 },
33408 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33409 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x78b600 }
33410 },
33411/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
33412 {
33413 { 0, 0, 0, 0 },
33414 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33415 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x78880000 }
33416 },
33417/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
33418 {
33419 { 0, 0, 0, 0 },
33420 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33421 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x78a80000 }
33422 },
33423/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
33424 {
33425 { 0, 0, 0, 0 },
33426 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33427 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x78b80000 }
33428 },
33429/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
33430 {
33431 { 0, 0, 0, 0 },
33432 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33433 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x788c0000 }
33434 },
33435/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
33436 {
33437 { 0, 0, 0, 0 },
33438 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33439 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x78ac0000 }
33440 },
33441/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
33442 {
33443 { 0, 0, 0, 0 },
33444 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33445 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x78bc0000 }
33446 },
33447/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
33448 {
33449 { 0, 0, 0, 0 },
33450 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33451 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x788a0000 }
33452 },
33453/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
33454 {
33455 { 0, 0, 0, 0 },
33456 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33457 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78aa0000 }
33458 },
33459/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
33460 {
33461 { 0, 0, 0, 0 },
33462 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33463 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78ba0000 }
33464 },
33465/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
33466 {
33467 { 0, 0, 0, 0 },
33468 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33469 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x788e0000 }
33470 },
33471/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
33472 {
33473 { 0, 0, 0, 0 },
33474 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33475 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78ae0000 }
33476 },
33477/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
33478 {
33479 { 0, 0, 0, 0 },
33480 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33481 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78be0000 }
33482 },
33483/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
33484 {
33485 { 0, 0, 0, 0 },
33486 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33487 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x788b0000 }
33488 },
33489/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
33490 {
33491 { 0, 0, 0, 0 },
33492 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33493 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78ab0000 }
33494 },
33495/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
33496 {
33497 { 0, 0, 0, 0 },
33498 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33499 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78bb0000 }
33500 },
33501/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
33502 {
33503 { 0, 0, 0, 0 },
33504 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
33505 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x788f0000 }
33506 },
33507/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
33508 {
33509 { 0, 0, 0, 0 },
33510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33511 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x78af0000 }
33512 },
33513/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
33514 {
33515 { 0, 0, 0, 0 },
33516 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33517 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x78bf0000 }
33518 },
33519/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
33520 {
33521 { 0, 0, 0, 0 },
33522 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
33523 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x78c00000 }
33524 },
33525/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
33526 {
33527 { 0, 0, 0, 0 },
33528 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
33529 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x78e00000 }
33530 },
33531/* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
33532 {
33533 { 0, 0, 0, 0 },
33534 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
33535 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x78f00000 }
33536 },
33537/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
33538 {
33539 { 0, 0, 0, 0 },
33540 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
33541 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x78c40000 }
33542 },
33543/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
33544 {
33545 { 0, 0, 0, 0 },
33546 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
33547 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x78e40000 }
33548 },
33549/* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
33550 {
33551 { 0, 0, 0, 0 },
33552 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
33553 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x78f40000 }
33554 },
33555/* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
33556 {
33557 { 0, 0, 0, 0 },
33558 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33559 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x78c60000 }
33560 },
33561/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
33562 {
33563 { 0, 0, 0, 0 },
33564 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33565 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x78e60000 }
33566 },
33567/* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
33568 {
33569 { 0, 0, 0, 0 },
33570 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
33571 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x78f60000 }
33572 },
33573/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
33574 {
33575 { 0, 0, 0, 0 },
33576 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33577 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x78c80000 }
33578 },
33579/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
33580 {
33581 { 0, 0, 0, 0 },
33582 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33583 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x78e80000 }
33584 },
33585/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
33586 {
33587 { 0, 0, 0, 0 },
33588 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33589 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x78f80000 }
33590 },
33591/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
33592 {
33593 { 0, 0, 0, 0 },
33594 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33595 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x78cc0000 }
33596 },
33597/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
33598 {
33599 { 0, 0, 0, 0 },
33600 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33601 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x78ec0000 }
33602 },
33603/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
33604 {
33605 { 0, 0, 0, 0 },
33606 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33607 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x78fc0000 }
33608 },
33609/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
33610 {
33611 { 0, 0, 0, 0 },
33612 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33613 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ca0000 }
33614 },
33615/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
33616 {
33617 { 0, 0, 0, 0 },
33618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33619 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ea0000 }
33620 },
33621/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
33622 {
33623 { 0, 0, 0, 0 },
33624 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33625 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x78fa0000 }
33626 },
33627/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
33628 {
33629 { 0, 0, 0, 0 },
33630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33631 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ce0000 }
33632 },
33633/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
33634 {
33635 { 0, 0, 0, 0 },
33636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33637 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ee0000 }
33638 },
33639/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
33640 {
33641 { 0, 0, 0, 0 },
33642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33643 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x78fe0000 }
33644 },
33645/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
33646 {
33647 { 0, 0, 0, 0 },
33648 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33649 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x78cb0000 }
33650 },
33651/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
33652 {
33653 { 0, 0, 0, 0 },
33654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33655 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x78eb0000 }
33656 },
33657/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
33658 {
33659 { 0, 0, 0, 0 },
33660 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33661 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x78fb0000 }
33662 },
33663/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
33664 {
33665 { 0, 0, 0, 0 },
33666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
33667 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x78cf0000 }
33668 },
33669/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
33670 {
33671 { 0, 0, 0, 0 },
33672 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
33673 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x78ef0000 }
33674 },
33675/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
33676 {
33677 { 0, 0, 0, 0 },
33678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
33679 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x78ff0000 }
33680 },
33681/* mul.b${G} $Src16RnQI,$Dst16RnQI */
33682 {
33683 { 0, 0, 0, 0 },
33684 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
33685 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7800 }
33686 },
33687/* mul.b${G} $Src16AnQI,$Dst16RnQI */
33688 {
33689 { 0, 0, 0, 0 },
33690 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
33691 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7840 }
33692 },
33693/* mul.b${G} [$Src16An],$Dst16RnQI */
33694 {
33695 { 0, 0, 0, 0 },
33696 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
33697 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7860 }
33698 },
33699/* mul.b${G} $Src16RnQI,$Dst16AnQI */
33700 {
33701 { 0, 0, 0, 0 },
33702 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
33703 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7804 }
33704 },
33705/* mul.b${G} $Src16AnQI,$Dst16AnQI */
33706 {
33707 { 0, 0, 0, 0 },
33708 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
33709 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7844 }
33710 },
33711/* mul.b${G} [$Src16An],$Dst16AnQI */
33712 {
33713 { 0, 0, 0, 0 },
33714 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
33715 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7864 }
33716 },
33717/* mul.b${G} $Src16RnQI,[$Dst16An] */
33718 {
33719 { 0, 0, 0, 0 },
33720 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
33721 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7806 }
33722 },
33723/* mul.b${G} $Src16AnQI,[$Dst16An] */
33724 {
33725 { 0, 0, 0, 0 },
33726 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
33727 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7846 }
33728 },
33729/* mul.b${G} [$Src16An],[$Dst16An] */
33730 {
33731 { 0, 0, 0, 0 },
33732 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33733 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7866 }
33734 },
33735/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
33736 {
33737 { 0, 0, 0, 0 },
33738 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33739 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x780800 }
33740 },
33741/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
33742 {
33743 { 0, 0, 0, 0 },
33744 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33745 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x784800 }
33746 },
33747/* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
33748 {
33749 { 0, 0, 0, 0 },
33750 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33751 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x786800 }
33752 },
33753/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
33754 {
33755 { 0, 0, 0, 0 },
33756 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33757 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x780c0000 }
33758 },
33759/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
33760 {
33761 { 0, 0, 0, 0 },
33762 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33763 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x784c0000 }
33764 },
33765/* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
33766 {
33767 { 0, 0, 0, 0 },
33768 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33769 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x786c0000 }
33770 },
33771/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
33772 {
33773 { 0, 0, 0, 0 },
33774 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33775 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x780a00 }
33776 },
33777/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
33778 {
33779 { 0, 0, 0, 0 },
33780 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33781 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x784a00 }
33782 },
33783/* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
33784 {
33785 { 0, 0, 0, 0 },
33786 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33787 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x786a00 }
33788 },
33789/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
33790 {
33791 { 0, 0, 0, 0 },
33792 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33793 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x780e0000 }
33794 },
33795/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
33796 {
33797 { 0, 0, 0, 0 },
33798 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33799 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x784e0000 }
33800 },
33801/* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
33802 {
33803 { 0, 0, 0, 0 },
33804 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33805 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x786e0000 }
33806 },
33807/* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
33808 {
33809 { 0, 0, 0, 0 },
33810 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33811 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x780b00 }
33812 },
33813/* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
33814 {
33815 { 0, 0, 0, 0 },
33816 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33817 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x784b00 }
33818 },
33819/* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
33820 {
33821 { 0, 0, 0, 0 },
33822 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33823 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x786b00 }
33824 },
33825/* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
33826 {
33827 { 0, 0, 0, 0 },
33828 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
33829 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x780f0000 }
33830 },
33831/* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
33832 {
33833 { 0, 0, 0, 0 },
33834 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
33835 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x784f0000 }
33836 },
33837/* mul.b${G} [$Src16An],${Dsp-16-u16} */
33838 {
33839 { 0, 0, 0, 0 },
33840 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
33841 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x786f0000 }
33842 },
33843/* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
33844 {
33845 { 0, 0, 0, 0 },
33846 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
33847 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x891f0000 }
33848 },
33849/* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
33850 {
33851 { 0, 0, 0, 0 },
33852 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
33853 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x819f0000 }
33854 },
33855/* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
33856 {
33857 { 0, 0, 0, 0 },
33858 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33859 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x811f0000 }
33860 },
33861/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
33862 {
33863 { 0, 0, 0, 0 },
33864 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33865 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x831f0000 }
33866 },
33867/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
33868 {
33869 { 0, 0, 0, 0 },
33870 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33871 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839f0000 }
33872 },
33873/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
33874 {
33875 { 0, 0, 0, 0 },
33876 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33877 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83df0000 }
33878 },
33879/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
33880 {
33881 { 0, 0, 0, 0 },
33882 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33883 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x851f0000 }
33884 },
33885/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
33886 {
33887 { 0, 0, 0, 0 },
33888 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33889 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859f0000 }
33890 },
33891/* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
33892 {
33893 { 0, 0, 0, 0 },
33894 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33895 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85df0000 }
33896 },
33897/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
33898 {
33899 { 0, 0, 0, 0 },
33900 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
33901 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87df0000 }
33902 },
33903/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
33904 {
33905 { 0, 0, 0, 0 },
33906 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33907 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x871f0000 }
33908 },
33909/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
33910 {
33911 { 0, 0, 0, 0 },
33912 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
33913 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x879f0000 }
33914 },
33915/* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
33916 {
33917 { 0, 0, 0, 0 },
33918 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
33919 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x881f00 }
33920 },
33921/* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
33922 {
33923 { 0, 0, 0, 0 },
33924 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
33925 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x809f00 }
33926 },
33927/* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
33928 {
33929 { 0, 0, 0, 0 },
33930 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33931 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x801f00 }
33932 },
33933/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
33934 {
33935 { 0, 0, 0, 0 },
33936 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33937 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x821f0000 }
33938 },
33939/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
33940 {
33941 { 0, 0, 0, 0 },
33942 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33943 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829f0000 }
33944 },
33945/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
33946 {
33947 { 0, 0, 0, 0 },
33948 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33949 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82df0000 }
33950 },
33951/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
33952 {
33953 { 0, 0, 0, 0 },
33954 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33955 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x841f0000 }
33956 },
33957/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
33958 {
33959 { 0, 0, 0, 0 },
33960 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33961 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849f0000 }
33962 },
33963/* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
33964 {
33965 { 0, 0, 0, 0 },
33966 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33967 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84df0000 }
33968 },
33969/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
33970 {
33971 { 0, 0, 0, 0 },
33972 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
33973 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86df0000 }
33974 },
33975/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
33976 {
33977 { 0, 0, 0, 0 },
33978 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33979 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x861f0000 }
33980 },
33981/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
33982 {
33983 { 0, 0, 0, 0 },
33984 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
33985 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x869f0000 }
33986 },
33987/* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
33988 {
33989 { 0, 0, 0, 0 },
33990 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
33991 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d500000 }
33992 },
33993/* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
33994 {
33995 { 0, 0, 0, 0 },
33996 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
33997 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d540000 }
33998 },
33999/* mul.w${G} #${Imm-16-HI},[$Dst16An] */
34000 {
34001 { 0, 0, 0, 0 },
34002 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
34003 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d560000 }
34004 },
34005/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
34006 {
34007 { 0, 0, 0, 0 },
34008 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34009 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d580000 }
34010 },
34011/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
34012 {
34013 { 0, 0, 0, 0 },
34014 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34015 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d5a0000 }
34016 },
34017/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
34018 {
34019 { 0, 0, 0, 0 },
34020 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34021 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d5b0000 }
34022 },
34023/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
34024 {
34025 { 0, 0, 0, 0 },
34026 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34027 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d5c0000 }
34028 },
34029/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
34030 {
34031 { 0, 0, 0, 0 },
34032 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34033 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d5e0000 }
34034 },
34035/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
34036 {
34037 { 0, 0, 0, 0 },
34038 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
34039 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d5f0000 }
34040 },
34041/* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
34042 {
34043 { 0, 0, 0, 0 },
34044 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
34045 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c5000 }
34046 },
34047/* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
34048 {
34049 { 0, 0, 0, 0 },
34050 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
34051 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c5400 }
34052 },
34053/* mul.b${G} #${Imm-16-QI},[$Dst16An] */
34054 {
34055 { 0, 0, 0, 0 },
34056 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
34057 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c5600 }
34058 },
34059/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
34060 {
34061 { 0, 0, 0, 0 },
34062 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34063 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c580000 }
34064 },
34065/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34066 {
34067 { 0, 0, 0, 0 },
34068 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34069 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c5a0000 }
34070 },
34071/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34072 {
34073 { 0, 0, 0, 0 },
34074 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34075 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c5b0000 }
34076 },
34077/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
34078 {
34079 { 0, 0, 0, 0 },
34080 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34081 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c5c0000 }
34082 },
34083/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34084 {
34085 { 0, 0, 0, 0 },
34086 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34087 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c5e0000 }
34088 },
34089/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
34090 {
34091 { 0, 0, 0, 0 },
34092 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34093 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c5f0000 }
34094 },
34095/* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
34096 {
34097 { 0, 0, 0, 0 },
34098 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
34099 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb81100 }
34100 },
34101/* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
34102 {
34103 { 0, 0, 0, 0 },
34104 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
34105 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb09100 }
34106 },
34107/* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
34108 {
34109 { 0, 0, 0, 0 },
34110 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34111 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb01100 }
34112 },
34113/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
34114 {
34115 { 0, 0, 0, 0 },
34116 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34117 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2110000 }
34118 },
34119/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34120 {
34121 { 0, 0, 0, 0 },
34122 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34123 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2910000 }
34124 },
34125/* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34126 {
34127 { 0, 0, 0, 0 },
34128 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34129 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2d10000 }
34130 },
34131/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
34132 {
34133 { 0, 0, 0, 0 },
34134 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34135 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4110000 }
34136 },
34137/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34138 {
34139 { 0, 0, 0, 0 },
34140 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34141 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4910000 }
34142 },
34143/* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
34144 {
34145 { 0, 0, 0, 0 },
34146 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
34147 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4d10000 }
34148 },
34149/* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
34150 {
34151 { 0, 0, 0, 0 },
34152 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34153 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6d10000 }
34154 },
34155/* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
34156 {
34157 { 0, 0, 0, 0 },
34158 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34159 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6110000 }
34160 },
34161/* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
34162 {
34163 { 0, 0, 0, 0 },
34164 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
34165 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6910000 }
34166 },
34167/* movhh $Dst32RnPrefixedQI,r0l */
34168 {
34169 { 0, 0, 0, 0 },
34170 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34171 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a83e }
34172 },
34173/* movhh $Dst32AnPrefixedQI,r0l */
34174 {
34175 { 0, 0, 0, 0 },
34176 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34177 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0be }
34178 },
34179/* movhh [$Dst32AnPrefixed],r0l */
34180 {
34181 { 0, 0, 0, 0 },
34182 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34183 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a03e }
34184 },
34185/* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34186 {
34187 { 0, 0, 0, 0 },
34188 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34189 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a23e00 }
34190 },
34191/* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34192 {
34193 { 0, 0, 0, 0 },
34194 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34195 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a43e00 }
34196 },
34197/* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34198 {
34199 { 0, 0, 0, 0 },
34200 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34201 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a63e00 }
34202 },
34203/* movhh ${Dsp-24-u8}[sb],r0l */
34204 {
34205 { 0, 0, 0, 0 },
34206 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34207 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2be00 }
34208 },
34209/* movhh ${Dsp-24-u16}[sb],r0l */
34210 {
34211 { 0, 0, 0, 0 },
34212 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34213 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4be00 }
34214 },
34215/* movhh ${Dsp-24-s8}[fb],r0l */
34216 {
34217 { 0, 0, 0, 0 },
34218 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34219 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2fe00 }
34220 },
34221/* movhh ${Dsp-24-s16}[fb],r0l */
34222 {
34223 { 0, 0, 0, 0 },
34224 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34225 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4fe00 }
34226 },
34227/* movhh ${Dsp-24-u16},r0l */
34228 {
34229 { 0, 0, 0, 0 },
34230 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34231 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6fe00 }
34232 },
34233/* movhh ${Dsp-24-u24},r0l */
34234 {
34235 { 0, 0, 0, 0 },
34236 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34237 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6be00 }
34238 },
34239/* movhl $Dst32RnPrefixedQI,r0l */
34240 {
34241 { 0, 0, 0, 0 },
34242 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34243 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a82e }
34244 },
34245/* movhl $Dst32AnPrefixedQI,r0l */
34246 {
34247 { 0, 0, 0, 0 },
34248 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34249 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0ae }
34250 },
34251/* movhl [$Dst32AnPrefixed],r0l */
34252 {
34253 { 0, 0, 0, 0 },
34254 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34255 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a02e }
34256 },
34257/* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34258 {
34259 { 0, 0, 0, 0 },
34260 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34261 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a22e00 }
34262 },
34263/* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34264 {
34265 { 0, 0, 0, 0 },
34266 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34267 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a42e00 }
34268 },
34269/* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34270 {
34271 { 0, 0, 0, 0 },
34272 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34273 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a62e00 }
34274 },
34275/* movhl ${Dsp-24-u8}[sb],r0l */
34276 {
34277 { 0, 0, 0, 0 },
34278 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34279 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2ae00 }
34280 },
34281/* movhl ${Dsp-24-u16}[sb],r0l */
34282 {
34283 { 0, 0, 0, 0 },
34284 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34285 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4ae00 }
34286 },
34287/* movhl ${Dsp-24-s8}[fb],r0l */
34288 {
34289 { 0, 0, 0, 0 },
34290 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34291 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ee00 }
34292 },
34293/* movhl ${Dsp-24-s16}[fb],r0l */
34294 {
34295 { 0, 0, 0, 0 },
34296 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34297 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ee00 }
34298 },
34299/* movhl ${Dsp-24-u16},r0l */
34300 {
34301 { 0, 0, 0, 0 },
34302 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34303 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ee00 }
34304 },
34305/* movhl ${Dsp-24-u24},r0l */
34306 {
34307 { 0, 0, 0, 0 },
34308 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34309 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6ae00 }
34310 },
34311/* movlh $Dst32RnPrefixedQI,r0l */
34312 {
34313 { 0, 0, 0, 0 },
34314 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34315 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a81e }
34316 },
34317/* movlh $Dst32AnPrefixedQI,r0l */
34318 {
34319 { 0, 0, 0, 0 },
34320 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34321 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a09e }
34322 },
34323/* movlh [$Dst32AnPrefixed],r0l */
34324 {
34325 { 0, 0, 0, 0 },
34326 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34327 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a01e }
34328 },
34329/* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34330 {
34331 { 0, 0, 0, 0 },
34332 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34333 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a21e00 }
34334 },
34335/* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34336 {
34337 { 0, 0, 0, 0 },
34338 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34339 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a41e00 }
34340 },
34341/* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34342 {
34343 { 0, 0, 0, 0 },
34344 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34345 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a61e00 }
34346 },
34347/* movlh ${Dsp-24-u8}[sb],r0l */
34348 {
34349 { 0, 0, 0, 0 },
34350 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34351 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a29e00 }
34352 },
34353/* movlh ${Dsp-24-u16}[sb],r0l */
34354 {
34355 { 0, 0, 0, 0 },
34356 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34357 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a49e00 }
34358 },
34359/* movlh ${Dsp-24-s8}[fb],r0l */
34360 {
34361 { 0, 0, 0, 0 },
34362 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34363 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2de00 }
34364 },
34365/* movlh ${Dsp-24-s16}[fb],r0l */
34366 {
34367 { 0, 0, 0, 0 },
34368 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34369 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4de00 }
34370 },
34371/* movlh ${Dsp-24-u16},r0l */
34372 {
34373 { 0, 0, 0, 0 },
34374 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34375 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6de00 }
34376 },
34377/* movlh ${Dsp-24-u24},r0l */
34378 {
34379 { 0, 0, 0, 0 },
34380 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34381 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a69e00 }
34382 },
34383/* movll $Dst32RnPrefixedQI,r0l */
34384 {
34385 { 0, 0, 0, 0 },
34386 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34387 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a80e }
34388 },
34389/* movll $Dst32AnPrefixedQI,r0l */
34390 {
34391 { 0, 0, 0, 0 },
34392 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34393 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a08e }
34394 },
34395/* movll [$Dst32AnPrefixed],r0l */
34396 {
34397 { 0, 0, 0, 0 },
34398 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34399 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a00e }
34400 },
34401/* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34402 {
34403 { 0, 0, 0, 0 },
34404 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34405 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a20e00 }
34406 },
34407/* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34408 {
34409 { 0, 0, 0, 0 },
34410 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34411 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a40e00 }
34412 },
34413/* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34414 {
34415 { 0, 0, 0, 0 },
34416 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34417 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a60e00 }
34418 },
34419/* movll ${Dsp-24-u8}[sb],r0l */
34420 {
34421 { 0, 0, 0, 0 },
34422 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34423 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a28e00 }
34424 },
34425/* movll ${Dsp-24-u16}[sb],r0l */
34426 {
34427 { 0, 0, 0, 0 },
34428 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34429 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a48e00 }
34430 },
34431/* movll ${Dsp-24-s8}[fb],r0l */
34432 {
34433 { 0, 0, 0, 0 },
34434 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34435 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ce00 }
34436 },
34437/* movll ${Dsp-24-s16}[fb],r0l */
34438 {
34439 { 0, 0, 0, 0 },
34440 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34441 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ce00 }
34442 },
34443/* movll ${Dsp-24-u16},r0l */
34444 {
34445 { 0, 0, 0, 0 },
34446 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34447 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ce00 }
34448 },
34449/* movll ${Dsp-24-u24},r0l */
34450 {
34451 { 0, 0, 0, 0 },
34452 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34453 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a68e00 }
34454 },
34455/* movhh r0l,$Dst32RnPrefixedQI */
34456 {
34457 { 0, 0, 0, 0 },
34458 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34459 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b83e }
34460 },
34461/* movhh r0l,$Dst32AnPrefixedQI */
34462 {
34463 { 0, 0, 0, 0 },
34464 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34465 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0be }
34466 },
34467/* movhh r0l,[$Dst32AnPrefixed] */
34468 {
34469 { 0, 0, 0, 0 },
34470 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34471 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b03e }
34472 },
34473/* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34474 {
34475 { 0, 0, 0, 0 },
34476 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34477 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b23e00 }
34478 },
34479/* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34480 {
34481 { 0, 0, 0, 0 },
34482 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34483 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b43e00 }
34484 },
34485/* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34486 {
34487 { 0, 0, 0, 0 },
34488 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34489 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b63e00 }
34490 },
34491/* movhh r0l,${Dsp-24-u8}[sb] */
34492 {
34493 { 0, 0, 0, 0 },
34494 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34495 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2be00 }
34496 },
34497/* movhh r0l,${Dsp-24-u16}[sb] */
34498 {
34499 { 0, 0, 0, 0 },
34500 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34501 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4be00 }
34502 },
34503/* movhh r0l,${Dsp-24-s8}[fb] */
34504 {
34505 { 0, 0, 0, 0 },
34506 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34507 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2fe00 }
34508 },
34509/* movhh r0l,${Dsp-24-s16}[fb] */
34510 {
34511 { 0, 0, 0, 0 },
34512 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34513 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4fe00 }
34514 },
34515/* movhh r0l,${Dsp-24-u16} */
34516 {
34517 { 0, 0, 0, 0 },
34518 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34519 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6fe00 }
34520 },
34521/* movhh r0l,${Dsp-24-u24} */
34522 {
34523 { 0, 0, 0, 0 },
34524 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34525 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6be00 }
34526 },
34527/* movhl r0l,$Dst32RnPrefixedQI */
34528 {
34529 { 0, 0, 0, 0 },
34530 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34531 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b82e }
34532 },
34533/* movhl r0l,$Dst32AnPrefixedQI */
34534 {
34535 { 0, 0, 0, 0 },
34536 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34537 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0ae }
34538 },
34539/* movhl r0l,[$Dst32AnPrefixed] */
34540 {
34541 { 0, 0, 0, 0 },
34542 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34543 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b02e }
34544 },
34545/* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34546 {
34547 { 0, 0, 0, 0 },
34548 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34549 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b22e00 }
34550 },
34551/* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34552 {
34553 { 0, 0, 0, 0 },
34554 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34555 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b42e00 }
34556 },
34557/* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34558 {
34559 { 0, 0, 0, 0 },
34560 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34561 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b62e00 }
34562 },
34563/* movhl r0l,${Dsp-24-u8}[sb] */
34564 {
34565 { 0, 0, 0, 0 },
34566 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34567 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2ae00 }
34568 },
34569/* movhl r0l,${Dsp-24-u16}[sb] */
34570 {
34571 { 0, 0, 0, 0 },
34572 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34573 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4ae00 }
34574 },
34575/* movhl r0l,${Dsp-24-s8}[fb] */
34576 {
34577 { 0, 0, 0, 0 },
34578 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34579 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ee00 }
34580 },
34581/* movhl r0l,${Dsp-24-s16}[fb] */
34582 {
34583 { 0, 0, 0, 0 },
34584 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34585 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ee00 }
34586 },
34587/* movhl r0l,${Dsp-24-u16} */
34588 {
34589 { 0, 0, 0, 0 },
34590 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34591 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ee00 }
34592 },
34593/* movhl r0l,${Dsp-24-u24} */
34594 {
34595 { 0, 0, 0, 0 },
34596 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34597 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6ae00 }
34598 },
34599/* movlh r0l,$Dst32RnPrefixedQI */
34600 {
34601 { 0, 0, 0, 0 },
34602 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34603 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b81e }
34604 },
34605/* movlh r0l,$Dst32AnPrefixedQI */
34606 {
34607 { 0, 0, 0, 0 },
34608 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34609 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b09e }
34610 },
34611/* movlh r0l,[$Dst32AnPrefixed] */
34612 {
34613 { 0, 0, 0, 0 },
34614 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34615 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b01e }
34616 },
34617/* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34618 {
34619 { 0, 0, 0, 0 },
34620 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34621 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b21e00 }
34622 },
34623/* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34624 {
34625 { 0, 0, 0, 0 },
34626 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34627 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b41e00 }
34628 },
34629/* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34630 {
34631 { 0, 0, 0, 0 },
34632 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34633 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b61e00 }
34634 },
34635/* movlh r0l,${Dsp-24-u8}[sb] */
34636 {
34637 { 0, 0, 0, 0 },
34638 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34639 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b29e00 }
34640 },
34641/* movlh r0l,${Dsp-24-u16}[sb] */
34642 {
34643 { 0, 0, 0, 0 },
34644 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34645 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b49e00 }
34646 },
34647/* movlh r0l,${Dsp-24-s8}[fb] */
34648 {
34649 { 0, 0, 0, 0 },
34650 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34651 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2de00 }
34652 },
34653/* movlh r0l,${Dsp-24-s16}[fb] */
34654 {
34655 { 0, 0, 0, 0 },
34656 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34657 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4de00 }
34658 },
34659/* movlh r0l,${Dsp-24-u16} */
34660 {
34661 { 0, 0, 0, 0 },
34662 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34663 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6de00 }
34664 },
34665/* movlh r0l,${Dsp-24-u24} */
34666 {
34667 { 0, 0, 0, 0 },
34668 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34669 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b69e00 }
34670 },
34671/* movll r0l,$Dst32RnPrefixedQI */
34672 {
34673 { 0, 0, 0, 0 },
34674 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34675 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b80e }
34676 },
34677/* movll r0l,$Dst32AnPrefixedQI */
34678 {
34679 { 0, 0, 0, 0 },
34680 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34681 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b08e }
34682 },
34683/* movll r0l,[$Dst32AnPrefixed] */
34684 {
34685 { 0, 0, 0, 0 },
34686 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34687 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b00e }
34688 },
34689/* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34690 {
34691 { 0, 0, 0, 0 },
34692 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34693 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b20e00 }
34694 },
34695/* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34696 {
34697 { 0, 0, 0, 0 },
34698 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34699 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b40e00 }
34700 },
34701/* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34702 {
34703 { 0, 0, 0, 0 },
34704 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34705 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b60e00 }
34706 },
34707/* movll r0l,${Dsp-24-u8}[sb] */
34708 {
34709 { 0, 0, 0, 0 },
34710 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34711 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b28e00 }
34712 },
34713/* movll r0l,${Dsp-24-u16}[sb] */
34714 {
34715 { 0, 0, 0, 0 },
34716 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34717 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b48e00 }
34718 },
34719/* movll r0l,${Dsp-24-s8}[fb] */
34720 {
34721 { 0, 0, 0, 0 },
34722 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34723 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ce00 }
34724 },
34725/* movll r0l,${Dsp-24-s16}[fb] */
34726 {
34727 { 0, 0, 0, 0 },
34728 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34729 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ce00 }
34730 },
34731/* movll r0l,${Dsp-24-u16} */
34732 {
34733 { 0, 0, 0, 0 },
34734 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34735 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ce00 }
34736 },
34737/* movll r0l,${Dsp-24-u24} */
34738 {
34739 { 0, 0, 0, 0 },
34740 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34741 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b68e00 }
34742 },
34743/* movhh $Dst16RnQI,r0l */
34744 {
34745 { 0, 0, 0, 0 },
34746 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
34747 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c30 }
34748 },
34749/* movhh $Dst16AnQI,r0l */
34750 {
34751 { 0, 0, 0, 0 },
34752 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
34753 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c34 }
34754 },
34755/* movhh [$Dst16An],r0l */
34756 {
34757 { 0, 0, 0, 0 },
34758 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34759 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c36 }
34760 },
34761/* movhh ${Dsp-16-u8}[$Dst16An],r0l */
34762 {
34763 { 0, 0, 0, 0 },
34764 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34765 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c3800 }
34766 },
34767/* movhh ${Dsp-16-u16}[$Dst16An],r0l */
34768 {
34769 { 0, 0, 0, 0 },
34770 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34771 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c3c0000 }
34772 },
34773/* movhh ${Dsp-16-u8}[sb],r0l */
34774 {
34775 { 0, 0, 0, 0 },
34776 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34777 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c3a00 }
34778 },
34779/* movhh ${Dsp-16-u16}[sb],r0l */
34780 {
34781 { 0, 0, 0, 0 },
34782 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34783 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c3e0000 }
34784 },
34785/* movhh ${Dsp-16-s8}[fb],r0l */
34786 {
34787 { 0, 0, 0, 0 },
34788 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34789 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c3b00 }
34790 },
34791/* movhh ${Dsp-16-u16},r0l */
34792 {
34793 { 0, 0, 0, 0 },
34794 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
34795 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c3f0000 }
34796 },
34797/* movhl $Dst16RnQI,r0l */
34798 {
34799 { 0, 0, 0, 0 },
34800 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
34801 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c10 }
34802 },
34803/* movhl $Dst16AnQI,r0l */
34804 {
34805 { 0, 0, 0, 0 },
34806 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
34807 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c14 }
34808 },
34809/* movhl [$Dst16An],r0l */
34810 {
34811 { 0, 0, 0, 0 },
34812 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34813 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c16 }
34814 },
34815/* movhl ${Dsp-16-u8}[$Dst16An],r0l */
34816 {
34817 { 0, 0, 0, 0 },
34818 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34819 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c1800 }
34820 },
34821/* movhl ${Dsp-16-u16}[$Dst16An],r0l */
34822 {
34823 { 0, 0, 0, 0 },
34824 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34825 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c1c0000 }
34826 },
34827/* movhl ${Dsp-16-u8}[sb],r0l */
34828 {
34829 { 0, 0, 0, 0 },
34830 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34831 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c1a00 }
34832 },
34833/* movhl ${Dsp-16-u16}[sb],r0l */
34834 {
34835 { 0, 0, 0, 0 },
34836 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34837 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c1e0000 }
34838 },
34839/* movhl ${Dsp-16-s8}[fb],r0l */
34840 {
34841 { 0, 0, 0, 0 },
34842 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34843 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c1b00 }
34844 },
34845/* movhl ${Dsp-16-u16},r0l */
34846 {
34847 { 0, 0, 0, 0 },
34848 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
34849 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c1f0000 }
34850 },
34851/* movlh $Dst16RnQI,r0l */
34852 {
34853 { 0, 0, 0, 0 },
34854 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
34855 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c20 }
34856 },
34857/* movlh $Dst16AnQI,r0l */
34858 {
34859 { 0, 0, 0, 0 },
34860 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
34861 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c24 }
34862 },
34863/* movlh [$Dst16An],r0l */
34864 {
34865 { 0, 0, 0, 0 },
34866 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34867 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c26 }
34868 },
34869/* movlh ${Dsp-16-u8}[$Dst16An],r0l */
34870 {
34871 { 0, 0, 0, 0 },
34872 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34873 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c2800 }
34874 },
34875/* movlh ${Dsp-16-u16}[$Dst16An],r0l */
34876 {
34877 { 0, 0, 0, 0 },
34878 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34879 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c2c0000 }
34880 },
34881/* movlh ${Dsp-16-u8}[sb],r0l */
34882 {
34883 { 0, 0, 0, 0 },
34884 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34885 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c2a00 }
34886 },
34887/* movlh ${Dsp-16-u16}[sb],r0l */
34888 {
34889 { 0, 0, 0, 0 },
34890 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34891 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c2e0000 }
34892 },
34893/* movlh ${Dsp-16-s8}[fb],r0l */
34894 {
34895 { 0, 0, 0, 0 },
34896 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34897 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c2b00 }
34898 },
34899/* movlh ${Dsp-16-u16},r0l */
34900 {
34901 { 0, 0, 0, 0 },
34902 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
34903 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c2f0000 }
34904 },
34905/* movll $Dst16RnQI,r0l */
34906 {
34907 { 0, 0, 0, 0 },
34908 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
34909 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c00 }
34910 },
34911/* movll $Dst16AnQI,r0l */
34912 {
34913 { 0, 0, 0, 0 },
34914 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
34915 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c04 }
34916 },
34917/* movll [$Dst16An],r0l */
34918 {
34919 { 0, 0, 0, 0 },
34920 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34921 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c06 }
34922 },
34923/* movll ${Dsp-16-u8}[$Dst16An],r0l */
34924 {
34925 { 0, 0, 0, 0 },
34926 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34927 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c0800 }
34928 },
34929/* movll ${Dsp-16-u16}[$Dst16An],r0l */
34930 {
34931 { 0, 0, 0, 0 },
34932 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
34933 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c0c0000 }
34934 },
34935/* movll ${Dsp-16-u8}[sb],r0l */
34936 {
34937 { 0, 0, 0, 0 },
34938 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34939 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c0a00 }
34940 },
34941/* movll ${Dsp-16-u16}[sb],r0l */
34942 {
34943 { 0, 0, 0, 0 },
34944 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34945 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c0e0000 }
34946 },
34947/* movll ${Dsp-16-s8}[fb],r0l */
34948 {
34949 { 0, 0, 0, 0 },
34950 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34951 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c0b00 }
34952 },
34953/* movll ${Dsp-16-u16},r0l */
34954 {
34955 { 0, 0, 0, 0 },
34956 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
34957 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c0f0000 }
34958 },
34959/* movhh r0l,$Dst16RnQI */
34960 {
34961 { 0, 0, 0, 0 },
34962 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
34963 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7cb0 }
34964 },
34965/* movhh r0l,$Dst16AnQI */
34966 {
34967 { 0, 0, 0, 0 },
34968 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
34969 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7cb4 }
34970 },
34971/* movhh r0l,[$Dst16An] */
34972 {
34973 { 0, 0, 0, 0 },
34974 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
34975 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7cb6 }
34976 },
34977/* movhh r0l,${Dsp-16-u8}[$Dst16An] */
34978 {
34979 { 0, 0, 0, 0 },
34980 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34981 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7cb800 }
34982 },
34983/* movhh r0l,${Dsp-16-u16}[$Dst16An] */
34984 {
34985 { 0, 0, 0, 0 },
34986 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34987 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cbc0000 }
34988 },
34989/* movhh r0l,${Dsp-16-u8}[sb] */
34990 {
34991 { 0, 0, 0, 0 },
34992 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34993 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7cba00 }
34994 },
34995/* movhh r0l,${Dsp-16-u16}[sb] */
34996 {
34997 { 0, 0, 0, 0 },
34998 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34999 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cbe0000 }
35000 },
35001/* movhh r0l,${Dsp-16-s8}[fb] */
35002 {
35003 { 0, 0, 0, 0 },
35004 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35005 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cbb00 }
35006 },
35007/* movhh r0l,${Dsp-16-u16} */
35008 {
35009 { 0, 0, 0, 0 },
35010 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35011 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7cbf0000 }
35012 },
35013/* movhl r0l,$Dst16RnQI */
35014 {
35015 { 0, 0, 0, 0 },
35016 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35017 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c90 }
35018 },
35019/* movhl r0l,$Dst16AnQI */
35020 {
35021 { 0, 0, 0, 0 },
35022 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35023 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c94 }
35024 },
35025/* movhl r0l,[$Dst16An] */
35026 {
35027 { 0, 0, 0, 0 },
35028 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35029 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c96 }
35030 },
35031/* movhl r0l,${Dsp-16-u8}[$Dst16An] */
35032 {
35033 { 0, 0, 0, 0 },
35034 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35035 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c9800 }
35036 },
35037/* movhl r0l,${Dsp-16-u16}[$Dst16An] */
35038 {
35039 { 0, 0, 0, 0 },
35040 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35041 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c9c0000 }
35042 },
35043/* movhl r0l,${Dsp-16-u8}[sb] */
35044 {
35045 { 0, 0, 0, 0 },
35046 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35047 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c9a00 }
35048 },
35049/* movhl r0l,${Dsp-16-u16}[sb] */
35050 {
35051 { 0, 0, 0, 0 },
35052 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35053 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c9e0000 }
35054 },
35055/* movhl r0l,${Dsp-16-s8}[fb] */
35056 {
35057 { 0, 0, 0, 0 },
35058 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35059 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c9b00 }
35060 },
35061/* movhl r0l,${Dsp-16-u16} */
35062 {
35063 { 0, 0, 0, 0 },
35064 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35065 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c9f0000 }
35066 },
35067/* movlh r0l,$Dst16RnQI */
35068 {
35069 { 0, 0, 0, 0 },
35070 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35071 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7ca0 }
35072 },
35073/* movlh r0l,$Dst16AnQI */
35074 {
35075 { 0, 0, 0, 0 },
35076 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35077 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7ca4 }
35078 },
35079/* movlh r0l,[$Dst16An] */
35080 {
35081 { 0, 0, 0, 0 },
35082 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35083 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7ca6 }
35084 },
35085/* movlh r0l,${Dsp-16-u8}[$Dst16An] */
35086 {
35087 { 0, 0, 0, 0 },
35088 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35089 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7ca800 }
35090 },
35091/* movlh r0l,${Dsp-16-u16}[$Dst16An] */
35092 {
35093 { 0, 0, 0, 0 },
35094 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35095 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cac0000 }
35096 },
35097/* movlh r0l,${Dsp-16-u8}[sb] */
35098 {
35099 { 0, 0, 0, 0 },
35100 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35101 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7caa00 }
35102 },
35103/* movlh r0l,${Dsp-16-u16}[sb] */
35104 {
35105 { 0, 0, 0, 0 },
35106 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35107 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cae0000 }
35108 },
35109/* movlh r0l,${Dsp-16-s8}[fb] */
35110 {
35111 { 0, 0, 0, 0 },
35112 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35113 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cab00 }
35114 },
35115/* movlh r0l,${Dsp-16-u16} */
35116 {
35117 { 0, 0, 0, 0 },
35118 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35119 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7caf0000 }
35120 },
35121/* movll r0l,$Dst16RnQI */
35122 {
35123 { 0, 0, 0, 0 },
35124 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35125 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c80 }
35126 },
35127/* movll r0l,$Dst16AnQI */
35128 {
35129 { 0, 0, 0, 0 },
35130 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35131 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c84 }
35132 },
35133/* movll r0l,[$Dst16An] */
35134 {
35135 { 0, 0, 0, 0 },
35136 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35137 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c86 }
35138 },
35139/* movll r0l,${Dsp-16-u8}[$Dst16An] */
35140 {
35141 { 0, 0, 0, 0 },
35142 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35143 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c8800 }
35144 },
35145/* movll r0l,${Dsp-16-u16}[$Dst16An] */
35146 {
35147 { 0, 0, 0, 0 },
35148 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35149 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c8c0000 }
35150 },
35151/* movll r0l,${Dsp-16-u8}[sb] */
35152 {
35153 { 0, 0, 0, 0 },
35154 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35155 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c8a00 }
35156 },
35157/* movll r0l,${Dsp-16-u16}[sb] */
35158 {
35159 { 0, 0, 0, 0 },
35160 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35161 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c8e0000 }
35162 },
35163/* movll r0l,${Dsp-16-s8}[fb] */
35164 {
35165 { 0, 0, 0, 0 },
35166 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35167 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c8b00 }
35168 },
35169/* movll r0l,${Dsp-16-u16} */
35170 {
35171 { 0, 0, 0, 0 },
35172 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35173 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c8f0000 }
35174 },
35175/* mova [$Dst32AnUnprefixed],a1 */
35176 {
35177 { 0, 0, 0, 0 },
35178 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35179 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11b }
35180 },
35181/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
35182 {
35183 { 0, 0, 0, 0 },
35184 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35185 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31b00 }
35186 },
35187/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
35188 {
35189 { 0, 0, 0, 0 },
35190 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35191 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51b0000 }
35192 },
35193/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
35194 {
35195 { 0, 0, 0, 0 },
35196 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35197 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71b0000 }
35198 },
35199/* mova ${Dsp-16-u8}[sb],a1 */
35200 {
35201 { 0, 0, 0, 0 },
35202 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35203 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39b00 }
35204 },
35205/* mova ${Dsp-16-u16}[sb],a1 */
35206 {
35207 { 0, 0, 0, 0 },
35208 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35209 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59b0000 }
35210 },
35211/* mova ${Dsp-16-s8}[fb],a1 */
35212 {
35213 { 0, 0, 0, 0 },
35214 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35215 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3db00 }
35216 },
35217/* mova ${Dsp-16-s16}[fb],a1 */
35218 {
35219 { 0, 0, 0, 0 },
35220 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35221 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5db0000 }
35222 },
35223/* mova ${Dsp-16-u16},a1 */
35224 {
35225 { 0, 0, 0, 0 },
35226 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } },
35227 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7db0000 }
35228 },
35229/* mova ${Dsp-16-u24},a1 */
35230 {
35231 { 0, 0, 0, 0 },
35232 { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '1', 0 } },
35233 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79b0000 }
35234 },
35235/* mova [$Dst32AnUnprefixed],a0 */
35236 {
35237 { 0, 0, 0, 0 },
35238 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35239 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11a }
35240 },
35241/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
35242 {
35243 { 0, 0, 0, 0 },
35244 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35245 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31a00 }
35246 },
35247/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
35248 {
35249 { 0, 0, 0, 0 },
35250 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35251 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51a0000 }
35252 },
35253/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
35254 {
35255 { 0, 0, 0, 0 },
35256 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35257 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71a0000 }
35258 },
35259/* mova ${Dsp-16-u8}[sb],a0 */
35260 {
35261 { 0, 0, 0, 0 },
35262 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35263 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39a00 }
35264 },
35265/* mova ${Dsp-16-u16}[sb],a0 */
35266 {
35267 { 0, 0, 0, 0 },
35268 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35269 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59a0000 }
35270 },
35271/* mova ${Dsp-16-s8}[fb],a0 */
35272 {
35273 { 0, 0, 0, 0 },
35274 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35275 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3da00 }
35276 },
35277/* mova ${Dsp-16-s16}[fb],a0 */
35278 {
35279 { 0, 0, 0, 0 },
35280 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35281 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5da0000 }
35282 },
35283/* mova ${Dsp-16-u16},a0 */
35284 {
35285 { 0, 0, 0, 0 },
35286 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } },
35287 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7da0000 }
35288 },
35289/* mova ${Dsp-16-u24},a0 */
35290 {
35291 { 0, 0, 0, 0 },
35292 { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '0', 0 } },
35293 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79a0000 }
35294 },
35295/* mova [$Dst32AnUnprefixed],r3r1 */
35296 {
35297 { 0, 0, 0, 0 },
35298 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35299 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd119 }
35300 },
35301/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
35302 {
35303 { 0, 0, 0, 0 },
35304 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35305 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31900 }
35306 },
35307/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
35308 {
35309 { 0, 0, 0, 0 },
35310 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35311 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5190000 }
35312 },
35313/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
35314 {
35315 { 0, 0, 0, 0 },
35316 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35317 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7190000 }
35318 },
35319/* mova ${Dsp-16-u8}[sb],r3r1 */
35320 {
35321 { 0, 0, 0, 0 },
35322 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35323 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39900 }
35324 },
35325/* mova ${Dsp-16-u16}[sb],r3r1 */
35326 {
35327 { 0, 0, 0, 0 },
35328 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35329 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5990000 }
35330 },
35331/* mova ${Dsp-16-s8}[fb],r3r1 */
35332 {
35333 { 0, 0, 0, 0 },
35334 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35335 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d900 }
35336 },
35337/* mova ${Dsp-16-s16}[fb],r3r1 */
35338 {
35339 { 0, 0, 0, 0 },
35340 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35341 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d90000 }
35342 },
35343/* mova ${Dsp-16-u16},r3r1 */
35344 {
35345 { 0, 0, 0, 0 },
35346 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 'r', '1', 0 } },
35347 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d90000 }
35348 },
35349/* mova ${Dsp-16-u24},r3r1 */
35350 {
35351 { 0, 0, 0, 0 },
35352 { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '3', 'r', '1', 0 } },
35353 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7990000 }
35354 },
35355/* mova [$Dst32AnUnprefixed],r2r0 */
35356 {
35357 { 0, 0, 0, 0 },
35358 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35359 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd118 }
35360 },
35361/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
35362 {
35363 { 0, 0, 0, 0 },
35364 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35365 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31800 }
35366 },
35367/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
35368 {
35369 { 0, 0, 0, 0 },
35370 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35371 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5180000 }
35372 },
35373/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
35374 {
35375 { 0, 0, 0, 0 },
35376 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35377 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7180000 }
35378 },
35379/* mova ${Dsp-16-u8}[sb],r2r0 */
35380 {
35381 { 0, 0, 0, 0 },
35382 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35383 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39800 }
35384 },
35385/* mova ${Dsp-16-u16}[sb],r2r0 */
35386 {
35387 { 0, 0, 0, 0 },
35388 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35389 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5980000 }
35390 },
35391/* mova ${Dsp-16-s8}[fb],r2r0 */
35392 {
35393 { 0, 0, 0, 0 },
35394 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35395 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d800 }
35396 },
35397/* mova ${Dsp-16-s16}[fb],r2r0 */
35398 {
35399 { 0, 0, 0, 0 },
35400 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35401 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d80000 }
35402 },
35403/* mova ${Dsp-16-u16},r2r0 */
35404 {
35405 { 0, 0, 0, 0 },
35406 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 'r', '0', 0 } },
35407 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d80000 }
35408 },
35409/* mova ${Dsp-16-u24},r2r0 */
35410 {
35411 { 0, 0, 0, 0 },
35412 { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '2', 'r', '0', 0 } },
35413 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7980000 }
35414 },
35415/* mova [$Dst16An],a1 */
35416 {
35417 { 0, 0, 0, 0 },
35418 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35419 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb56 }
35420 },
35421/* mova ${Dsp-16-u8}[$Dst16An],a1 */
35422 {
35423 { 0, 0, 0, 0 },
35424 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35425 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb5800 }
35426 },
35427/* mova ${Dsp-16-u16}[$Dst16An],a1 */
35428 {
35429 { 0, 0, 0, 0 },
35430 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35431 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb5c0000 }
35432 },
35433/* mova ${Dsp-16-u8}[sb],a1 */
35434 {
35435 { 0, 0, 0, 0 },
35436 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35437 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb5a00 }
35438 },
35439/* mova ${Dsp-16-u16}[sb],a1 */
35440 {
35441 { 0, 0, 0, 0 },
35442 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35443 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb5e0000 }
35444 },
35445/* mova ${Dsp-16-s8}[fb],a1 */
35446 {
35447 { 0, 0, 0, 0 },
35448 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35449 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb5b00 }
35450 },
35451/* mova ${Dsp-16-u16},a1 */
35452 {
35453 { 0, 0, 0, 0 },
35454 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } },
35455 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb5f0000 }
35456 },
35457/* mova [$Dst16An],a0 */
35458 {
35459 { 0, 0, 0, 0 },
35460 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35461 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb46 }
35462 },
35463/* mova ${Dsp-16-u8}[$Dst16An],a0 */
35464 {
35465 { 0, 0, 0, 0 },
35466 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35467 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb4800 }
35468 },
35469/* mova ${Dsp-16-u16}[$Dst16An],a0 */
35470 {
35471 { 0, 0, 0, 0 },
35472 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35473 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb4c0000 }
35474 },
35475/* mova ${Dsp-16-u8}[sb],a0 */
35476 {
35477 { 0, 0, 0, 0 },
35478 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35479 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb4a00 }
35480 },
35481/* mova ${Dsp-16-u16}[sb],a0 */
35482 {
35483 { 0, 0, 0, 0 },
35484 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35485 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb4e0000 }
35486 },
35487/* mova ${Dsp-16-s8}[fb],a0 */
35488 {
35489 { 0, 0, 0, 0 },
35490 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35491 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb4b00 }
35492 },
35493/* mova ${Dsp-16-u16},a0 */
35494 {
35495 { 0, 0, 0, 0 },
35496 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } },
35497 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb4f0000 }
35498 },
35499/* mova [$Dst16An],r3 */
35500 {
35501 { 0, 0, 0, 0 },
35502 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35503 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb36 }
35504 },
35505/* mova ${Dsp-16-u8}[$Dst16An],r3 */
35506 {
35507 { 0, 0, 0, 0 },
35508 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35509 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb3800 }
35510 },
35511/* mova ${Dsp-16-u16}[$Dst16An],r3 */
35512 {
35513 { 0, 0, 0, 0 },
35514 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35515 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb3c0000 }
35516 },
35517/* mova ${Dsp-16-u8}[sb],r3 */
35518 {
35519 { 0, 0, 0, 0 },
35520 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 0 } },
35521 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb3a00 }
35522 },
35523/* mova ${Dsp-16-u16}[sb],r3 */
35524 {
35525 { 0, 0, 0, 0 },
35526 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 0 } },
35527 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb3e0000 }
35528 },
35529/* mova ${Dsp-16-s8}[fb],r3 */
35530 {
35531 { 0, 0, 0, 0 },
35532 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 0 } },
35533 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb3b00 }
35534 },
35535/* mova ${Dsp-16-u16},r3 */
35536 {
35537 { 0, 0, 0, 0 },
35538 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 0 } },
35539 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb3f0000 }
35540 },
35541/* mova [$Dst16An],r2 */
35542 {
35543 { 0, 0, 0, 0 },
35544 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35545 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb26 }
35546 },
35547/* mova ${Dsp-16-u8}[$Dst16An],r2 */
35548 {
35549 { 0, 0, 0, 0 },
35550 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35551 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb2800 }
35552 },
35553/* mova ${Dsp-16-u16}[$Dst16An],r2 */
35554 {
35555 { 0, 0, 0, 0 },
35556 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35557 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb2c0000 }
35558 },
35559/* mova ${Dsp-16-u8}[sb],r2 */
35560 {
35561 { 0, 0, 0, 0 },
35562 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 0 } },
35563 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb2a00 }
35564 },
35565/* mova ${Dsp-16-u16}[sb],r2 */
35566 {
35567 { 0, 0, 0, 0 },
35568 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 0 } },
35569 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb2e0000 }
35570 },
35571/* mova ${Dsp-16-s8}[fb],r2 */
35572 {
35573 { 0, 0, 0, 0 },
35574 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 0 } },
35575 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb2b00 }
35576 },
35577/* mova ${Dsp-16-u16},r2 */
35578 {
35579 { 0, 0, 0, 0 },
35580 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 0 } },
35581 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb2f0000 }
35582 },
35583/* mova [$Dst16An],r1 */
35584 {
35585 { 0, 0, 0, 0 },
35586 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35587 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb16 }
35588 },
35589/* mova ${Dsp-16-u8}[$Dst16An],r1 */
35590 {
35591 { 0, 0, 0, 0 },
35592 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35593 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb1800 }
35594 },
35595/* mova ${Dsp-16-u16}[$Dst16An],r1 */
35596 {
35597 { 0, 0, 0, 0 },
35598 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35599 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb1c0000 }
35600 },
35601/* mova ${Dsp-16-u8}[sb],r1 */
35602 {
35603 { 0, 0, 0, 0 },
35604 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
35605 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb1a00 }
35606 },
35607/* mova ${Dsp-16-u16}[sb],r1 */
35608 {
35609 { 0, 0, 0, 0 },
35610 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
35611 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb1e0000 }
35612 },
35613/* mova ${Dsp-16-s8}[fb],r1 */
35614 {
35615 { 0, 0, 0, 0 },
35616 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } },
35617 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb1b00 }
35618 },
35619/* mova ${Dsp-16-u16},r1 */
35620 {
35621 { 0, 0, 0, 0 },
35622 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '1', 0 } },
35623 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb1f0000 }
35624 },
35625/* mova [$Dst16An],r0 */
35626 {
35627 { 0, 0, 0, 0 },
35628 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
35629 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb06 }
35630 },
35631/* mova ${Dsp-16-u8}[$Dst16An],r0 */
35632 {
35633 { 0, 0, 0, 0 },
35634 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
35635 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb0800 }
35636 },
35637/* mova ${Dsp-16-u16}[$Dst16An],r0 */
35638 {
35639 { 0, 0, 0, 0 },
35640 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
35641 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb0c0000 }
35642 },
35643/* mova ${Dsp-16-u8}[sb],r0 */
35644 {
35645 { 0, 0, 0, 0 },
35646 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
35647 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb0a00 }
35648 },
35649/* mova ${Dsp-16-u16}[sb],r0 */
35650 {
35651 { 0, 0, 0, 0 },
35652 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
35653 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb0e0000 }
35654 },
35655/* mova ${Dsp-16-s8}[fb],r0 */
35656 {
35657 { 0, 0, 0, 0 },
35658 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } },
35659 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb0b00 }
35660 },
35661/* mova ${Dsp-16-u16},r0 */
35662 {
35663 { 0, 0, 0, 0 },
35664 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 0 } },
35665 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb0f0000 }
35666 },
f75eb1c0 35667/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
49f58d10
JB		 35668 {
35669 { 0, 0, 0, 0 },
f75eb1c0 35670 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35671 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30f0000 }
35672 },
f75eb1c0 35673/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35674 {
35675 { 0, 0, 0, 0 },
f75eb1c0 35676 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35677 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38f0000 }
35678 },
f75eb1c0 35679/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35680 {
35681 { 0, 0, 0, 0 },
f75eb1c0 35682 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35683 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3cf0000 }
35684 },
f75eb1c0 35685/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
49f58d10
JB		 35686 {
35687 { 0, 0, 0, 0 },
f75eb1c0 35688 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35689 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50f0000 }
35690 },
f75eb1c0 35691/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 35692 {
35693 { 0, 0, 0, 0 },
f75eb1c0 35694 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35695 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58f0000 }
35696 },
f75eb1c0 35697/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
49f58d10
JB		 35698 {
35699 { 0, 0, 0, 0 },
f75eb1c0 35700 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35701 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5cf0000 }
35702 },
f75eb1c0 35703/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 35704 {
35705 { 0, 0, 0, 0 },
f75eb1c0 35706 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35707 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xa7cf0000 }
35708 },
f75eb1c0 35709/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
49f58d10
JB		 35710 {
35711 { 0, 0, 0, 0 },
f75eb1c0 35712 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35713 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70f0000 }
35714 },
f75eb1c0 35715/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
49f58d10
JB		 35716 {
35717 { 0, 0, 0, 0 },
f75eb1c0 35718 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35719 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xa78f0000 }
35720 },
f75eb1c0 35721/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35722 {
35723 { 0, 0, 0, 0 },
f75eb1c0 35724 { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35725 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xa90f00 }
35726 },
f75eb1c0 35727/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35728 {
35729 { 0, 0, 0, 0 },
f75eb1c0 35730 { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35731 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18f00 }
35732 },
f75eb1c0 35733/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
49f58d10
JB		 35734 {
35735 { 0, 0, 0, 0 },
f75eb1c0 35736 { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35737 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xa10f00 }
35738 },
f75eb1c0 35739/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
49f58d10
JB		 35740 {
35741 { 0, 0, 0, 0 },
f75eb1c0 35742 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35743 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20f0000 }
35744 },
f75eb1c0 35745/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35746 {
35747 { 0, 0, 0, 0 },
f75eb1c0 35748 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35749 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28f0000 }
35750 },
f75eb1c0 35751/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35752 {
35753 { 0, 0, 0, 0 },
f75eb1c0 35754 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35755 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2cf0000 }
35756 },
f75eb1c0 35757/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
49f58d10
JB		 35758 {
35759 { 0, 0, 0, 0 },
f75eb1c0 35760 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35761 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40f0000 }
35762 },
f75eb1c0 35763/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 35764 {
35765 { 0, 0, 0, 0 },
f75eb1c0 35766 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35767 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48f0000 }
35768 },
f75eb1c0 35769/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
49f58d10
JB		 35770 {
35771 { 0, 0, 0, 0 },
f75eb1c0 35772 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35773 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4cf0000 }
35774 },
f75eb1c0 35775/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 35776 {
35777 { 0, 0, 0, 0 },
f75eb1c0 35778 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35779 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xa6cf0000 }
35780 },
f75eb1c0 35781/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
49f58d10
JB		 35782 {
35783 { 0, 0, 0, 0 },
f75eb1c0 35784 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35785 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60f0000 }
35786 },
f75eb1c0 35787/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
49f58d10
JB		 35788 {
35789 { 0, 0, 0, 0 },
f75eb1c0 35790 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35791 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xa68f0000 }
35792 },
f75eb1c0 35793/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35794 {
35795 { 0, 0, 0, 0 },
f75eb1c0 35796 { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35797 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xa80f00 }
35798 },
f75eb1c0 35799/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35800 {
35801 { 0, 0, 0, 0 },
f75eb1c0 35802 { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35803 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xa08f00 }
35804 },
f75eb1c0 35805/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
49f58d10
JB		 35806 {
35807 { 0, 0, 0, 0 },
f75eb1c0 35808 { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35809 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xa00f00 }
35810 },
f75eb1c0 35811/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
49f58d10
JB		 35812 {
35813 { 0, 0, 0, 0 },
f75eb1c0 35814 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35815 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75380000 }
35816 },
f75eb1c0 35817/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35818 {
35819 { 0, 0, 0, 0 },
f75eb1c0 35820 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35821 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x753a0000 }
35822 },
f75eb1c0 35823/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35824 {
35825 { 0, 0, 0, 0 },
f75eb1c0 35826 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35827 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x753b0000 }
35828 },
f75eb1c0 35829/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
49f58d10
JB		 35830 {
35831 { 0, 0, 0, 0 },
f75eb1c0 35832 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35833 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x753c0000 }
35834 },
f75eb1c0 35835/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 35836 {
35837 { 0, 0, 0, 0 },
f75eb1c0 35838 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35839 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x753e0000 }
35840 },
f75eb1c0 35841/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 35842 {
35843 { 0, 0, 0, 0 },
f75eb1c0 35844 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35845 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x753f0000 }
35846 },
f75eb1c0 35847/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35848 {
35849 { 0, 0, 0, 0 },
f75eb1c0 35850 { { MNEM, OP (G), ' ', OP (DST16RNHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35851 & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x753000 }
35852 },
f75eb1c0 35853/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35854 {
35855 { 0, 0, 0, 0 },
f75eb1c0 35856 { { MNEM, OP (G), ' ', OP (DST16ANHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35857 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x753400 }
35858 },
f75eb1c0 35859/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
49f58d10
JB		 35860 {
35861 { 0, 0, 0, 0 },
f75eb1c0 35862 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35863 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x753600 }
35864 },
f75eb1c0 35865/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
49f58d10
JB		 35866 {
35867 { 0, 0, 0, 0 },
f75eb1c0 35868 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35869 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74380000 }
35870 },
f75eb1c0 35871/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35872 {
35873 { 0, 0, 0, 0 },
f75eb1c0 35874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35875 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x743a0000 }
35876 },
f75eb1c0 35877/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 35878 {
35879 { 0, 0, 0, 0 },
f75eb1c0 35880 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35881 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x743b0000 }
35882 },
f75eb1c0 35883/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
49f58d10
JB		 35884 {
35885 { 0, 0, 0, 0 },
f75eb1c0 35886 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35887 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x743c0000 }
35888 },
f75eb1c0 35889/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 35890 {
35891 { 0, 0, 0, 0 },
f75eb1c0 35892 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35893 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x743e0000 }
35894 },
f75eb1c0 35895/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 35896 {
35897 { 0, 0, 0, 0 },
f75eb1c0 35898 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35899 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x743f0000 }
35900 },
f75eb1c0 35901/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35902 {
35903 { 0, 0, 0, 0 },
f75eb1c0 35904 { { MNEM, OP (G), ' ', OP (DST16RNQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35905 & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x743000 }
35906 },
f75eb1c0 35907/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 35908 {
35909 { 0, 0, 0, 0 },
f75eb1c0 35910 { { MNEM, OP (G), ' ', OP (DST16ANQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35911 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x743400 }
35912 },
f75eb1c0 35913/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
49f58d10
JB		 35914 {
35915 { 0, 0, 0, 0 },
f75eb1c0 35916 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 35917 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x743600 }
35918 },
f75eb1c0 35919/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 35920 {
35921 { 0, 0, 0, 0 },
f75eb1c0 35922 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 35923 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30f0000 }
35924 },
f75eb1c0 35925/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 35926 {
35927 { 0, 0, 0, 0 },
f75eb1c0 35928 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 35929 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38f0000 }
35930 },
f75eb1c0 35931/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 35932 {
35933 { 0, 0, 0, 0 },
f75eb1c0 35934 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 35935 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3cf0000 }
35936 },
f75eb1c0 35937/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 35938 {
35939 { 0, 0, 0, 0 },
f75eb1c0 35940 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 35941 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50f0000 }
35942 },
f75eb1c0 35943/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 35944 {
35945 { 0, 0, 0, 0 },
f75eb1c0 35946 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 35947 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58f0000 }
35948 },
f75eb1c0 35949/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
49f58d10
JB		 35950 {
35951 { 0, 0, 0, 0 },
f75eb1c0 35952 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 35953 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5cf0000 }
35954 },
f75eb1c0 35955/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 35956 {
35957 { 0, 0, 0, 0 },
f75eb1c0 35958 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 35959 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xb7cf0000 }
35960 },
f75eb1c0 35961/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 35962 {
35963 { 0, 0, 0, 0 },
f75eb1c0 35964 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 35965 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70f0000 }
35966 },
f75eb1c0 35967/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
49f58d10
JB		 35968 {
35969 { 0, 0, 0, 0 },
f75eb1c0 35970 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 35971 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xb78f0000 }
35972 },
f75eb1c0 35973/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
49f58d10
JB		 35974 {
35975 { 0, 0, 0, 0 },
f75eb1c0 35976 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49f58d10
JB		 35977 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xb90f00 }
35978 },
f75eb1c0 35979/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
49f58d10
JB		 35980 {
35981 { 0, 0, 0, 0 },
f75eb1c0 35982 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49f58d10
JB		 35983 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18f00 }
35984 },
f75eb1c0 35985/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
49f58d10
JB		 35986 {
35987 { 0, 0, 0, 0 },
f75eb1c0 35988 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 35989 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xb10f00 }
35990 },
f75eb1c0 35991/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 35992 {
35993 { 0, 0, 0, 0 },
f75eb1c0 35994 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 35995 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20f0000 }
35996 },
f75eb1c0 35997/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 35998 {
35999 { 0, 0, 0, 0 },
f75eb1c0 36000 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36001 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28f0000 }
36002 },
f75eb1c0 36003/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 36004 {
36005 { 0, 0, 0, 0 },
f75eb1c0 36006 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36007 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2cf0000 }
36008 },
f75eb1c0 36009/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 36010 {
36011 { 0, 0, 0, 0 },
f75eb1c0 36012 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36013 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40f0000 }
36014 },
f75eb1c0 36015/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 36016 {
36017 { 0, 0, 0, 0 },
f75eb1c0 36018 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36019 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48f0000 }
36020 },
f75eb1c0 36021/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
49f58d10
JB		 36022 {
36023 { 0, 0, 0, 0 },
f75eb1c0 36024 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36025 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4cf0000 }
36026 },
f75eb1c0 36027/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 36028 {
36029 { 0, 0, 0, 0 },
f75eb1c0 36030 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 36031 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xb6cf0000 }
36032 },
f75eb1c0 36033/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 36034 {
36035 { 0, 0, 0, 0 },
f75eb1c0 36036 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36037 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60f0000 }
36038 },
f75eb1c0 36039/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
49f58d10
JB		 36040 {
36041 { 0, 0, 0, 0 },
f75eb1c0 36042 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 36043 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xb68f0000 }
36044 },
f75eb1c0 36045/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
49f58d10
JB		 36046 {
36047 { 0, 0, 0, 0 },
f75eb1c0 36048 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49f58d10
JB		 36049 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xb80f00 }
36050 },
f75eb1c0 36051/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
49f58d10
JB		 36052 {
36053 { 0, 0, 0, 0 },
f75eb1c0 36054 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49f58d10
JB		 36055 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xb08f00 }
36056 },
f75eb1c0 36057/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
49f58d10
JB		 36058 {
36059 { 0, 0, 0, 0 },
f75eb1c0 36060 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36061 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xb00f00 }
36062 },
f75eb1c0 36063/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 36064 {
36065 { 0, 0, 0, 0 },
f75eb1c0 36066 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36067 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75b80000 }
36068 },
f75eb1c0 36069/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 36070 {
36071 { 0, 0, 0, 0 },
f75eb1c0 36072 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36073 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x75ba0000 }
36074 },
f75eb1c0 36075/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 36076 {
36077 { 0, 0, 0, 0 },
f75eb1c0 36078 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36079 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x75bb0000 }
36080 },
f75eb1c0 36081/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 36082 {
36083 { 0, 0, 0, 0 },
f75eb1c0 36084 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36085 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x75bc0000 }
36086 },
f75eb1c0 36087/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 36088 {
36089 { 0, 0, 0, 0 },
f75eb1c0 36090 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36091 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x75be0000 }
36092 },
f75eb1c0 36093/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 36094 {
36095 { 0, 0, 0, 0 },
f75eb1c0 36096 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 36097 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x75bf0000 }
36098 },
f75eb1c0 36099/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
49f58d10
JB		 36100 {
36101 { 0, 0, 0, 0 },
f75eb1c0 36102 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNHI), 0 } },
49f58d10
JB		 36103 & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75b000 }
36104 },
f75eb1c0 36105/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
49f58d10
JB		 36106 {
36107 { 0, 0, 0, 0 },
f75eb1c0 36108 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANHI), 0 } },
49f58d10
JB		 36109 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75b400 }
36110 },
f75eb1c0 36111/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
49f58d10
JB		 36112 {
36113 { 0, 0, 0, 0 },
f75eb1c0 36114 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36115 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75b600 }
36116 },
f75eb1c0 36117/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 36118 {
36119 { 0, 0, 0, 0 },
f75eb1c0 36120 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36121 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74b80000 }
36122 },
f75eb1c0 36123/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 36124 {
36125 { 0, 0, 0, 0 },
f75eb1c0 36126 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36127 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x74ba0000 }
36128 },
f75eb1c0 36129/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 36130 {
36131 { 0, 0, 0, 0 },
f75eb1c0 36132 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36133 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x74bb0000 }
36134 },
f75eb1c0 36135/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 36136 {
36137 { 0, 0, 0, 0 },
f75eb1c0 36138 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36139 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x74bc0000 }
36140 },
f75eb1c0 36141/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 36142 {
36143 { 0, 0, 0, 0 },
f75eb1c0 36144 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36145 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x74be0000 }
36146 },
f75eb1c0 36147/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 36148 {
36149 { 0, 0, 0, 0 },
f75eb1c0 36150 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 36151 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x74bf0000 }
36152 },
f75eb1c0 36153/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
49f58d10
JB		 36154 {
36155 { 0, 0, 0, 0 },
f75eb1c0 36156 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNQI), 0 } },
49f58d10
JB		 36157 & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74b000 }
36158 },
f75eb1c0 36159/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
49f58d10
JB		 36160 {
36161 { 0, 0, 0, 0 },
f75eb1c0 36162 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANQI), 0 } },
49f58d10
JB		 36163 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74b400 }
36164 },
f75eb1c0 36165/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
49f58d10
JB		 36166 {
36167 { 0, 0, 0, 0 },
f75eb1c0 36168 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36169 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74b600 }
36170 },
36171/* mov.l${S} ${Dsp-8-u8}[sb],a1 */
36172 {
36173 { 0, 0, 0, 0 },
36174 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
36175 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6900 }
36176 },
36177/* mov.l${S} ${Dsp-8-s8}[fb],a1 */
36178 {
36179 { 0, 0, 0, 0 },
36180 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
36181 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7900 }
36182 },
36183/* mov.l${S} ${Dsp-8-u8}[sb],a0 */
36184 {
36185 { 0, 0, 0, 0 },
36186 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
36187 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6800 }
36188 },
36189/* mov.l${S} ${Dsp-8-s8}[fb],a0 */
36190 {
36191 { 0, 0, 0, 0 },
36192 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
36193 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7800 }
36194 },
36195/* mov.l${S} ${Dsp-8-u16},a1 */
36196 {
36197 { 0, 0, 0, 0 },
36198 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '1', 0 } },
36199 & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x590000 }
36200 },
36201/* mov.l${S} ${Dsp-8-u16},a0 */
36202 {
36203 { 0, 0, 0, 0 },
36204 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '0', 0 } },
36205 & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x580000 }
36206 },
36207/* mov.w${S} r0,${Dsp-8-u8}[sb] */
36208 {
36209 { 0, 0, 0, 0 },
36210 { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36211 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2100 }
36212 },
36213/* mov.w${S} r0,${Dsp-8-s8}[fb] */
36214 {
36215 { 0, 0, 0, 0 },
36216 { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36217 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3100 }
36218 },
36219/* mov.b${S} r0l,${Dsp-8-u8}[sb] */
36220 {
36221 { 0, 0, 0, 0 },
36222 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36223 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2000 }
36224 },
36225/* mov.b${S} r0l,${Dsp-8-s8}[fb] */
36226 {
36227 { 0, 0, 0, 0 },
36228 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36229 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3000 }
36230 },
36231/* mov.w${S} r0,${Dsp-8-u16} */
36232 {
36233 { 0, 0, 0, 0 },
36234 { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U16), 0 } },
36235 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x110000 }
36236 },
36237/* mov.b${S} r0l,${Dsp-8-u16} */
36238 {
36239 { 0, 0, 0, 0 },
36240 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U16), 0 } },
36241 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x100000 }
36242 },
36243/* mov.w${S} ${Dsp-8-u8}[sb],r1 */
36244 {
36245 { 0, 0, 0, 0 },
36246 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
36247 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6f00 }
36248 },
36249/* mov.w${S} ${Dsp-8-s8}[fb],r1 */
36250 {
36251 { 0, 0, 0, 0 },
36252 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } },
36253 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7f00 }
36254 },
36255/* mov.b${S} ${Dsp-8-u8}[sb],r1l */
36256 {
36257 { 0, 0, 0, 0 },
36258 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 'l', 0 } },
36259 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6e00 }
36260 },
36261/* mov.b${S} ${Dsp-8-s8}[fb],r1l */
36262 {
36263 { 0, 0, 0, 0 },
36264 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 'l', 0 } },
36265 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7e00 }
36266 },
36267/* mov.w${S} ${Dsp-8-u16},r1 */
36268 {
36269 { 0, 0, 0, 0 },
36270 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 0 } },
36271 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x5f0000 }
36272 },
36273/* mov.b${S} ${Dsp-8-u16},r1l */
36274 {
36275 { 0, 0, 0, 0 },
36276 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 'l', 0 } },
36277 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x5e0000 }
36278 },
f75eb1c0 36279/* mov.w${S} r0,r1 */
49f58d10
JB		 36280 {
36281 { 0, 0, 0, 0 },
f75eb1c0
DD		 36282 { { MNEM, OP (S), ' ', 'r', '0', ',', 'r', '1', 0 } },
36283 & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x4f }
49f58d10
JB		 36284 },
36285/* mov.b${S} r0l,r1l */
36286 {
36287 { 0, 0, 0, 0 },
36288 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'r', '1', 'l', 0 } },
36289 & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x4e }
36290 },
36291/* mov.w${S} ${Dsp-8-u8}[sb],r0 */
36292 {
36293 { 0, 0, 0, 0 },
36294 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
36295 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2900 }
36296 },
36297/* mov.w${S} ${Dsp-8-s8}[fb],r0 */
36298 {
36299 { 0, 0, 0, 0 },
36300 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } },
36301 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3900 }
36302 },
36303/* mov.b${S} ${Dsp-8-u8}[sb],r0l */
36304 {
36305 { 0, 0, 0, 0 },
36306 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
36307 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2800 }
36308 },
36309/* mov.b${S} ${Dsp-8-s8}[fb],r0l */
36310 {
36311 { 0, 0, 0, 0 },
36312 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
36313 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3800 }
36314 },
36315/* mov.w${S} ${Dsp-8-u16},r0 */
36316 {
36317 { 0, 0, 0, 0 },
36318 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 0 } },
36319 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x190000 }
36320 },
36321/* mov.b${S} ${Dsp-8-u16},r0l */
36322 {
36323 { 0, 0, 0, 0 },
36324 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 'l', 0 } },
36325 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x180000 }
36326 },
36327/* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36328 {
36329 { 0, 0, 0, 0 },
36330 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
36331 & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x8 }
36332 },
36333/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36334 {
36335 { 0, 0, 0, 0 },
36336 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
36337 & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x900 }
36338 },
36339/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36340 {
36341 { 0, 0, 0, 0 },
36342 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
36343 & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0xa00 }
36344 },
36345/* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36346 {
36347 { 0, 0, 0, 0 },
36348 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
36349 & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0xb0000 }
36350 },
36351/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
36352 {
36353 { 0, 0, 0, 0 },
36354 { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36355 & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x100 }
36356 },
36357/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
36358 {
36359 { 0, 0, 0, 0 },
36360 { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36361 & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x200 }
36362 },
36363/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
36364 {
36365 { 0, 0, 0, 0 },
36366 { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U16), 0 } },
36367 & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x30000 }
36368 },
36369/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36370 {
36371 { 0, 0, 0, 0 },
36372 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36373 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990300 }
36374 },
36375/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
36376 {
36377 { 0, 0, 0, 0 },
36378 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36379 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992300 }
36380 },
36381/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
36382 {
36383 { 0, 0, 0, 0 },
36384 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36385 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993300 }
36386 },
36387/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36388 {
36389 { 0, 0, 0, 0 },
36390 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36391 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918300 }
36392 },
36393/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
36394 {
36395 { 0, 0, 0, 0 },
36396 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36397 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a300 }
36398 },
36399/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
36400 {
36401 { 0, 0, 0, 0 },
36402 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36403 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b300 }
36404 },
36405/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36406 {
36407 { 0, 0, 0, 0 },
36408 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36409 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910300 }
36410 },
36411/* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36412 {
36413 { 0, 0, 0, 0 },
36414 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36415 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912300 }
36416 },
36417/* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36418 {
36419 { 0, 0, 0, 0 },
36420 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36421 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913300 }
36422 },
36423/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36424 {
36425 { 0, 0, 0, 0 },
36426 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36427 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93030000 }
36428 },
36429/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36430 {
36431 { 0, 0, 0, 0 },
36432 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36433 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93230000 }
36434 },
36435/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36436 {
36437 { 0, 0, 0, 0 },
36438 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36439 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93330000 }
36440 },
36441/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36442 {
36443 { 0, 0, 0, 0 },
36444 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36445 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95030000 }
36446 },
36447/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36448 {
36449 { 0, 0, 0, 0 },
36450 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36451 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95230000 }
36452 },
36453/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36454 {
36455 { 0, 0, 0, 0 },
36456 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36457 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95330000 }
36458 },
36459/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36460 {
36461 { 0, 0, 0, 0 },
36462 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36463 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97030000 }
36464 },
36465/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36466 {
36467 { 0, 0, 0, 0 },
36468 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36469 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97230000 }
36470 },
36471/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36472 {
36473 { 0, 0, 0, 0 },
36474 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36475 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97330000 }
36476 },
36477/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36478 {
36479 { 0, 0, 0, 0 },
36480 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36481 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93830000 }
36482 },
36483/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36484 {
36485 { 0, 0, 0, 0 },
36486 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36487 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a30000 }
36488 },
36489/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36490 {
36491 { 0, 0, 0, 0 },
36492 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36493 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b30000 }
36494 },
36495/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36496 {
36497 { 0, 0, 0, 0 },
36498 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36499 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95830000 }
36500 },
36501/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36502 {
36503 { 0, 0, 0, 0 },
36504 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36505 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a30000 }
36506 },
36507/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36508 {
36509 { 0, 0, 0, 0 },
36510 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36511 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b30000 }
36512 },
36513/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36514 {
36515 { 0, 0, 0, 0 },
36516 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36517 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c30000 }
36518 },
36519/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36520 {
36521 { 0, 0, 0, 0 },
36522 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36523 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e30000 }
36524 },
36525/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36526 {
36527 { 0, 0, 0, 0 },
36528 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36529 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f30000 }
36530 },
36531/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36532 {
36533 { 0, 0, 0, 0 },
36534 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36535 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c30000 }
36536 },
36537/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36538 {
36539 { 0, 0, 0, 0 },
36540 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36541 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e30000 }
36542 },
36543/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36544 {
36545 { 0, 0, 0, 0 },
36546 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36547 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f30000 }
36548 },
36549/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36550 {
36551 { 0, 0, 0, 0 },
36552 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
36553 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c30000 }
36554 },
36555/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36556 {
36557 { 0, 0, 0, 0 },
36558 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
36559 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e30000 }
36560 },
36561/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36562 {
36563 { 0, 0, 0, 0 },
36564 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
36565 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f30000 }
36566 },
36567/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36568 {
36569 { 0, 0, 0, 0 },
36570 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
36571 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97830000 }
36572 },
36573/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36574 {
36575 { 0, 0, 0, 0 },
36576 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
36577 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a30000 }
36578 },
36579/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36580 {
36581 { 0, 0, 0, 0 },
36582 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
36583 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b30000 }
36584 },
36585/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36586 {
36587 { 0, 0, 0, 0 },
36588 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36589 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9030000 }
36590 },
36591/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
36592 {
36593 { 0, 0, 0, 0 },
36594 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36595 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9230000 }
36596 },
36597/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
36598 {
36599 { 0, 0, 0, 0 },
36600 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36601 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9330000 }
36602 },
36603/* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
36604 {
36605 { 0, 0, 0, 0 },
36606 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36607 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9330000 }
36608 },
36609/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36610 {
36611 { 0, 0, 0, 0 },
36612 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36613 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1830000 }
36614 },
36615/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
36616 {
36617 { 0, 0, 0, 0 },
36618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36619 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a30000 }
36620 },
36621/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
36622 {
36623 { 0, 0, 0, 0 },
36624 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36625 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b30000 }
36626 },
36627/* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
36628 {
36629 { 0, 0, 0, 0 },
36630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36631 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b30000 }
36632 },
36633/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36634 {
36635 { 0, 0, 0, 0 },
36636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36637 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1030000 }
36638 },
36639/* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
36640 {
36641 { 0, 0, 0, 0 },
36642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36643 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1230000 }
36644 },
36645/* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
36646 {
36647 { 0, 0, 0, 0 },
36648 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36649 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1330000 }
36650 },
36651/* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
36652 {
36653 { 0, 0, 0, 0 },
36654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36655 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1330000 }
36656 },
36657/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36658 {
36659 { 0, 0, 0, 0 },
36660 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36661 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3030000 }
36662 },
36663/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36664 {
36665 { 0, 0, 0, 0 },
36666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36667 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3230000 }
36668 },
36669/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36670 {
36671 { 0, 0, 0, 0 },
36672 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36673 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3330000 }
36674 },
36675/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
36676 {
36677 { 0, 0, 0, 0 },
36678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36679 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3330000 }
36680 },
36681/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36682 {
36683 { 0, 0, 0, 0 },
36684 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36685 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5030000 }
36686 },
36687/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36688 {
36689 { 0, 0, 0, 0 },
36690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36691 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5230000 }
36692 },
36693/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36694 {
36695 { 0, 0, 0, 0 },
36696 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36697 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5330000 }
36698 },
36699/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
36700 {
36701 { 0, 0, 0, 0 },
36702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36703 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5330000 }
36704 },
36705/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36706 {
36707 { 0, 0, 0, 0 },
36708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36709 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7030000 }
36710 },
36711/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36712 {
36713 { 0, 0, 0, 0 },
36714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36715 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7230000 }
36716 },
36717/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36718 {
36719 { 0, 0, 0, 0 },
36720 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36721 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7330000 }
36722 },
36723/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
36724 {
36725 { 0, 0, 0, 0 },
36726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36727 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7330000 }
36728 },
36729/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
36730 {
36731 { 0, 0, 0, 0 },
36732 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
36733 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3830000 }
36734 },
36735/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
36736 {
36737 { 0, 0, 0, 0 },
36738 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
36739 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a30000 }
36740 },
36741/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
36742 {
36743 { 0, 0, 0, 0 },
36744 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
36745 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b30000 }
36746 },
36747/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
36748 {
36749 { 0, 0, 0, 0 },
36750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
36751 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b30000 }
36752 },
36753/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
36754 {
36755 { 0, 0, 0, 0 },
36756 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
36757 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5830000 }
36758 },
36759/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
36760 {
36761 { 0, 0, 0, 0 },
36762 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
36763 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a30000 }
36764 },
36765/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
36766 {
36767 { 0, 0, 0, 0 },
36768 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
36769 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b30000 }
36770 },
36771/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
36772 {
36773 { 0, 0, 0, 0 },
36774 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
36775 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b30000 }
36776 },
36777/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
36778 {
36779 { 0, 0, 0, 0 },
36780 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
36781 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c30000 }
36782 },
36783/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
36784 {
36785 { 0, 0, 0, 0 },
36786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
36787 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e30000 }
36788 },
36789/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
36790 {
36791 { 0, 0, 0, 0 },
36792 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
36793 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f30000 }
36794 },
36795/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
36796 {
36797 { 0, 0, 0, 0 },
36798 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
36799 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f30000 }
36800 },
36801/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
36802 {
36803 { 0, 0, 0, 0 },
36804 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
36805 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c30000 }
36806 },
36807/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
36808 {
36809 { 0, 0, 0, 0 },
36810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
36811 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e30000 }
36812 },
36813/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
36814 {
36815 { 0, 0, 0, 0 },
36816 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
36817 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f30000 }
36818 },
36819/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
36820 {
36821 { 0, 0, 0, 0 },
36822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
36823 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f30000 }
36824 },
36825/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
36826 {
36827 { 0, 0, 0, 0 },
36828 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
36829 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c30000 }
36830 },
36831/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
36832 {
36833 { 0, 0, 0, 0 },
36834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
36835 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e30000 }
36836 },
36837/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
36838 {
36839 { 0, 0, 0, 0 },
36840 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
36841 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f30000 }
36842 },
36843/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
36844 {
36845 { 0, 0, 0, 0 },
36846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
36847 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f30000 }
36848 },
36849/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
36850 {
36851 { 0, 0, 0, 0 },
36852 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
36853 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7830000 }
36854 },
36855/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
36856 {
36857 { 0, 0, 0, 0 },
36858 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
36859 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a30000 }
36860 },
36861/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
36862 {
36863 { 0, 0, 0, 0 },
36864 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
36865 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b30000 }
36866 },
36867/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
36868 {
36869 { 0, 0, 0, 0 },
36870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
36871 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b30000 }
36872 },
36873/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36874 {
36875 { 0, 0, 0, 0 },
36876 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36877 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9030000 }
36878 },
36879/* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
36880 {
36881 { 0, 0, 0, 0 },
36882 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36883 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9230000 }
36884 },
36885/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36886 {
36887 { 0, 0, 0, 0 },
36888 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36889 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1830000 }
36890 },
36891/* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
36892 {
36893 { 0, 0, 0, 0 },
36894 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36895 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a30000 }
36896 },
36897/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36898 {
36899 { 0, 0, 0, 0 },
36900 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36901 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1030000 }
36902 },
36903/* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
36904 {
36905 { 0, 0, 0, 0 },
36906 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36907 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1230000 }
36908 },
36909/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
36910 {
36911 { 0, 0, 0, 0 },
36912 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36913 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3030000 }
36914 },
36915/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
36916 {
36917 { 0, 0, 0, 0 },
36918 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36919 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3230000 }
36920 },
36921/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
36922 {
36923 { 0, 0, 0, 0 },
36924 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36925 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5030000 }
36926 },
36927/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
36928 {
36929 { 0, 0, 0, 0 },
36930 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36931 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5230000 }
36932 },
36933/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
36934 {
36935 { 0, 0, 0, 0 },
36936 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36937 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7030000 }
36938 },
36939/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
36940 {
36941 { 0, 0, 0, 0 },
36942 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36943 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7230000 }
36944 },
36945/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
36946 {
36947 { 0, 0, 0, 0 },
36948 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
36949 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3830000 }
36950 },
36951/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
36952 {
36953 { 0, 0, 0, 0 },
36954 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
36955 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a30000 }
36956 },
36957/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
36958 {
36959 { 0, 0, 0, 0 },
36960 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
36961 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5830000 }
36962 },
36963/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
36964 {
36965 { 0, 0, 0, 0 },
36966 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
36967 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a30000 }
36968 },
36969/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
36970 {
36971 { 0, 0, 0, 0 },
36972 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
36973 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c30000 }
36974 },
36975/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
36976 {
36977 { 0, 0, 0, 0 },
36978 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
36979 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e30000 }
36980 },
36981/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
36982 {
36983 { 0, 0, 0, 0 },
36984 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
36985 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c30000 }
36986 },
36987/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
36988 {
36989 { 0, 0, 0, 0 },
36990 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
36991 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e30000 }
36992 },
36993/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
36994 {
36995 { 0, 0, 0, 0 },
36996 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
36997 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c30000 }
36998 },
36999/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
37000 {
37001 { 0, 0, 0, 0 },
37002 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
37003 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e30000 }
37004 },
37005/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37006 {
37007 { 0, 0, 0, 0 },
37008 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
37009 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7830000 }
37010 },
37011/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
37012 {
37013 { 0, 0, 0, 0 },
37014 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
37015 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a30000 }
37016 },
37017/* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
37018 {
37019 { 0, 0, 0, 0 },
37020 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37021 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc903 }
37022 },
37023/* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
37024 {
37025 { 0, 0, 0, 0 },
37026 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37027 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8923 }
37028 },
37029/* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
37030 {
37031 { 0, 0, 0, 0 },
37032 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37033 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8903 }
37034 },
37035/* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
37036 {
37037 { 0, 0, 0, 0 },
37038 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37039 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc183 }
37040 },
37041/* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
37042 {
37043 { 0, 0, 0, 0 },
37044 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37045 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a3 }
37046 },
37047/* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
37048 {
37049 { 0, 0, 0, 0 },
37050 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37051 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8183 }
37052 },
37053/* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
37054 {
37055 { 0, 0, 0, 0 },
37056 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37057 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc103 }
37058 },
37059/* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
37060 {
37061 { 0, 0, 0, 0 },
37062 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37063 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8123 }
37064 },
37065/* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37066 {
37067 { 0, 0, 0, 0 },
37068 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37069 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8103 }
37070 },
37071/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37072 {
37073 { 0, 0, 0, 0 },
37074 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37075 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30300 }
37076 },
37077/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37078 {
37079 { 0, 0, 0, 0 },
37080 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37081 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832300 }
37082 },
37083/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37084 {
37085 { 0, 0, 0, 0 },
37086 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37087 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830300 }
37088 },
37089/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37090 {
37091 { 0, 0, 0, 0 },
37092 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37093 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5030000 }
37094 },
37095/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37096 {
37097 { 0, 0, 0, 0 },
37098 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37099 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85230000 }
37100 },
37101/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37102 {
37103 { 0, 0, 0, 0 },
37104 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37105 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85030000 }
37106 },
37107/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37108 {
37109 { 0, 0, 0, 0 },
37110 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37111 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7030000 }
37112 },
37113/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37114 {
37115 { 0, 0, 0, 0 },
37116 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37117 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87230000 }
37118 },
37119/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37120 {
37121 { 0, 0, 0, 0 },
37122 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37123 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87030000 }
37124 },
37125/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
37126 {
37127 { 0, 0, 0, 0 },
37128 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37129 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38300 }
37130 },
37131/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
37132 {
37133 { 0, 0, 0, 0 },
37134 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37135 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a300 }
37136 },
37137/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37138 {
37139 { 0, 0, 0, 0 },
37140 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37141 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838300 }
37142 },
37143/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
37144 {
37145 { 0, 0, 0, 0 },
37146 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37147 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5830000 }
37148 },
37149/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
37150 {
37151 { 0, 0, 0, 0 },
37152 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37153 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a30000 }
37154 },
37155/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37156 {
37157 { 0, 0, 0, 0 },
37158 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37159 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85830000 }
37160 },
37161/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
37162 {
37163 { 0, 0, 0, 0 },
37164 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37165 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c300 }
37166 },
37167/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
37168 {
37169 { 0, 0, 0, 0 },
37170 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37171 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e300 }
37172 },
37173/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37174 {
37175 { 0, 0, 0, 0 },
37176 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37177 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c300 }
37178 },
37179/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
37180 {
37181 { 0, 0, 0, 0 },
37182 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37183 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c30000 }
37184 },
37185/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
37186 {
37187 { 0, 0, 0, 0 },
37188 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37189 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e30000 }
37190 },
37191/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37192 {
37193 { 0, 0, 0, 0 },
37194 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37195 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c30000 }
37196 },
37197/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
37198 {
37199 { 0, 0, 0, 0 },
37200 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
37201 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c30000 }
37202 },
37203/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
37204 {
37205 { 0, 0, 0, 0 },
37206 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
37207 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e30000 }
37208 },
37209/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37210 {
37211 { 0, 0, 0, 0 },
37212 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
37213 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c30000 }
37214 },
37215/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
37216 {
37217 { 0, 0, 0, 0 },
37218 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
37219 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7830000 }
37220 },
37221/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
37222 {
37223 { 0, 0, 0, 0 },
37224 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
37225 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a30000 }
37226 },
37227/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37228 {
37229 { 0, 0, 0, 0 },
37230 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
37231 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87830000 }
37232 },
37233/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
37234 {
37235 { 0, 0, 0, 0 },
37236 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI_S), 0 } },
37237 & ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI, { 0x3100 }
37238 },
37239/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
37240 {
37241 { 0, 0, 0, 0 },
37242 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI_S), 0 } },
37243 & ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI, { 0x3200 }
37244 },
37245/* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
37246 {
37247 { 0, 0, 0, 0 },
37248 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16ANQI_S), 0 } },
37249 & ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI, { 0x330000 }
37250 },
37251/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37252 {
37253 { 0, 0, 0, 0 },
37254 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37255 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990b00 }
37256 },
37257/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
37258 {
37259 { 0, 0, 0, 0 },
37260 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37261 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992b00 }
37262 },
37263/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
37264 {
37265 { 0, 0, 0, 0 },
37266 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37267 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993b00 }
37268 },
37269/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37270 {
37271 { 0, 0, 0, 0 },
37272 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37273 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918b00 }
37274 },
37275/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
37276 {
37277 { 0, 0, 0, 0 },
37278 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37279 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ab00 }
37280 },
37281/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
37282 {
37283 { 0, 0, 0, 0 },
37284 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37285 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bb00 }
37286 },
37287/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37288 {
37289 { 0, 0, 0, 0 },
37290 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37291 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910b00 }
37292 },
37293/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37294 {
37295 { 0, 0, 0, 0 },
37296 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37297 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912b00 }
37298 },
37299/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37300 {
37301 { 0, 0, 0, 0 },
37302 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37303 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913b00 }
37304 },
37305/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37306 {
37307 { 0, 0, 0, 0 },
37308 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37309 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930b0000 }
37310 },
37311/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37312 {
37313 { 0, 0, 0, 0 },
37314 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37315 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932b0000 }
37316 },
37317/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37318 {
37319 { 0, 0, 0, 0 },
37320 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37321 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933b0000 }
37322 },
37323/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37324 {
37325 { 0, 0, 0, 0 },
37326 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37327 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950b0000 }
37328 },
37329/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37330 {
37331 { 0, 0, 0, 0 },
37332 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37333 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952b0000 }
37334 },
37335/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37336 {
37337 { 0, 0, 0, 0 },
37338 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37339 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953b0000 }
37340 },
37341/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37342 {
37343 { 0, 0, 0, 0 },
37344 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37345 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970b0000 }
37346 },
37347/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37348 {
37349 { 0, 0, 0, 0 },
37350 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37351 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972b0000 }
37352 },
37353/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37354 {
37355 { 0, 0, 0, 0 },
37356 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37357 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973b0000 }
37358 },
37359/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37360 {
37361 { 0, 0, 0, 0 },
37362 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37363 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938b0000 }
37364 },
37365/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37366 {
37367 { 0, 0, 0, 0 },
37368 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37369 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ab0000 }
37370 },
37371/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37372 {
37373 { 0, 0, 0, 0 },
37374 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37375 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bb0000 }
37376 },
37377/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37378 {
37379 { 0, 0, 0, 0 },
37380 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37381 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958b0000 }
37382 },
37383/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37384 {
37385 { 0, 0, 0, 0 },
37386 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37387 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ab0000 }
37388 },
37389/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37390 {
37391 { 0, 0, 0, 0 },
37392 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37393 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bb0000 }
37394 },
37395/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37396 {
37397 { 0, 0, 0, 0 },
37398 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37399 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cb0000 }
37400 },
37401/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37402 {
37403 { 0, 0, 0, 0 },
37404 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37405 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93eb0000 }
37406 },
37407/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37408 {
37409 { 0, 0, 0, 0 },
37410 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37411 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fb0000 }
37412 },
37413/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37414 {
37415 { 0, 0, 0, 0 },
37416 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37417 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cb0000 }
37418 },
37419/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37420 {
37421 { 0, 0, 0, 0 },
37422 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37423 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95eb0000 }
37424 },
37425/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37426 {
37427 { 0, 0, 0, 0 },
37428 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37429 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fb0000 }
37430 },
37431/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37432 {
37433 { 0, 0, 0, 0 },
37434 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
37435 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cb0000 }
37436 },
37437/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37438 {
37439 { 0, 0, 0, 0 },
37440 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
37441 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97eb0000 }
37442 },
37443/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37444 {
37445 { 0, 0, 0, 0 },
37446 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
37447 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fb0000 }
37448 },
37449/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37450 {
37451 { 0, 0, 0, 0 },
37452 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
37453 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978b0000 }
37454 },
37455/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37456 {
37457 { 0, 0, 0, 0 },
37458 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
37459 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ab0000 }
37460 },
37461/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37462 {
37463 { 0, 0, 0, 0 },
37464 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
37465 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bb0000 }
37466 },
37467/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37468 {
37469 { 0, 0, 0, 0 },
37470 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37471 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90b0000 }
37472 },
37473/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
37474 {
37475 { 0, 0, 0, 0 },
37476 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37477 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92b0000 }
37478 },
37479/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
37480 {
37481 { 0, 0, 0, 0 },
37482 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37483 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93b0000 }
37484 },
37485/* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
37486 {
37487 { 0, 0, 0, 0 },
37488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37489 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93b0000 }
37490 },
37491/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37492 {
37493 { 0, 0, 0, 0 },
37494 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37495 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18b0000 }
37496 },
37497/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
37498 {
37499 { 0, 0, 0, 0 },
37500 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37501 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ab0000 }
37502 },
37503/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
37504 {
37505 { 0, 0, 0, 0 },
37506 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37507 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bb0000 }
37508 },
37509/* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
37510 {
37511 { 0, 0, 0, 0 },
37512 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37513 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bb0000 }
37514 },
37515/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37516 {
37517 { 0, 0, 0, 0 },
37518 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37519 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10b0000 }
37520 },
37521/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37522 {
37523 { 0, 0, 0, 0 },
37524 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37525 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12b0000 }
37526 },
37527/* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37528 {
37529 { 0, 0, 0, 0 },
37530 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37531 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13b0000 }
37532 },
37533/* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37534 {
37535 { 0, 0, 0, 0 },
37536 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37537 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13b0000 }
37538 },
37539/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37540 {
37541 { 0, 0, 0, 0 },
37542 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37543 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30b0000 }
37544 },
37545/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37546 {
37547 { 0, 0, 0, 0 },
37548 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37549 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32b0000 }
37550 },
37551/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37552 {
37553 { 0, 0, 0, 0 },
37554 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37555 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33b0000 }
37556 },
37557/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37558 {
37559 { 0, 0, 0, 0 },
37560 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37561 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33b0000 }
37562 },
37563/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37564 {
37565 { 0, 0, 0, 0 },
37566 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37567 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50b0000 }
37568 },
37569/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37570 {
37571 { 0, 0, 0, 0 },
37572 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37573 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52b0000 }
37574 },
37575/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37576 {
37577 { 0, 0, 0, 0 },
37578 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37579 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53b0000 }
37580 },
37581/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37582 {
37583 { 0, 0, 0, 0 },
37584 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37585 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53b0000 }
37586 },
37587/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37588 {
37589 { 0, 0, 0, 0 },
37590 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37591 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70b0000 }
37592 },
37593/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37594 {
37595 { 0, 0, 0, 0 },
37596 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37597 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72b0000 }
37598 },
37599/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37600 {
37601 { 0, 0, 0, 0 },
37602 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37603 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73b0000 }
37604 },
37605/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37606 {
37607 { 0, 0, 0, 0 },
37608 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37609 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73b0000 }
37610 },
37611/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37612 {
37613 { 0, 0, 0, 0 },
37614 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37615 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38b0000 }
37616 },
37617/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37618 {
37619 { 0, 0, 0, 0 },
37620 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37621 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ab0000 }
37622 },
37623/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37624 {
37625 { 0, 0, 0, 0 },
37626 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37627 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bb0000 }
37628 },
37629/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37630 {
37631 { 0, 0, 0, 0 },
37632 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37633 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bb0000 }
37634 },
37635/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37636 {
37637 { 0, 0, 0, 0 },
37638 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37639 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58b0000 }
37640 },
37641/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37642 {
37643 { 0, 0, 0, 0 },
37644 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37645 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ab0000 }
37646 },
37647/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37648 {
37649 { 0, 0, 0, 0 },
37650 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37651 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bb0000 }
37652 },
37653/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37654 {
37655 { 0, 0, 0, 0 },
37656 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37657 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bb0000 }
37658 },
37659/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37660 {
37661 { 0, 0, 0, 0 },
37662 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37663 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cb0000 }
37664 },
37665/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37666 {
37667 { 0, 0, 0, 0 },
37668 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37669 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3eb0000 }
37670 },
37671/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37672 {
37673 { 0, 0, 0, 0 },
37674 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37675 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fb0000 }
37676 },
37677/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37678 {
37679 { 0, 0, 0, 0 },
37680 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37681 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fb0000 }
37682 },
37683/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37684 {
37685 { 0, 0, 0, 0 },
37686 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37687 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cb0000 }
37688 },
37689/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37690 {
37691 { 0, 0, 0, 0 },
37692 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37693 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5eb0000 }
37694 },
37695/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37696 {
37697 { 0, 0, 0, 0 },
37698 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37699 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fb0000 }
37700 },
37701/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37702 {
37703 { 0, 0, 0, 0 },
37704 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37705 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fb0000 }
37706 },
37707/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37708 {
37709 { 0, 0, 0, 0 },
37710 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
37711 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cb0000 }
37712 },
37713/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37714 {
37715 { 0, 0, 0, 0 },
37716 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
37717 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7eb0000 }
37718 },
37719/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37720 {
37721 { 0, 0, 0, 0 },
37722 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
37723 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fb0000 }
37724 },
37725/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
37726 {
37727 { 0, 0, 0, 0 },
37728 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
37729 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fb0000 }
37730 },
37731/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37732 {
37733 { 0, 0, 0, 0 },
37734 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
37735 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78b0000 }
37736 },
37737/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37738 {
37739 { 0, 0, 0, 0 },
37740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
37741 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ab0000 }
37742 },
37743/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37744 {
37745 { 0, 0, 0, 0 },
37746 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
37747 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bb0000 }
37748 },
37749/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
37750 {
37751 { 0, 0, 0, 0 },
37752 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
37753 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bb0000 }
37754 },
37755/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37756 {
37757 { 0, 0, 0, 0 },
37758 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37759 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90b0000 }
37760 },
37761/* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
37762 {
37763 { 0, 0, 0, 0 },
37764 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37765 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92b0000 }
37766 },
37767/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37768 {
37769 { 0, 0, 0, 0 },
37770 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37771 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18b0000 }
37772 },
37773/* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
37774 {
37775 { 0, 0, 0, 0 },
37776 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37777 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ab0000 }
37778 },
37779/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37780 {
37781 { 0, 0, 0, 0 },
37782 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37783 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10b0000 }
37784 },
37785/* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37786 {
37787 { 0, 0, 0, 0 },
37788 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37789 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12b0000 }
37790 },
37791/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37792 {
37793 { 0, 0, 0, 0 },
37794 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37795 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30b0000 }
37796 },
37797/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37798 {
37799 { 0, 0, 0, 0 },
37800 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37801 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32b0000 }
37802 },
37803/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37804 {
37805 { 0, 0, 0, 0 },
37806 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37807 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50b0000 }
37808 },
37809/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37810 {
37811 { 0, 0, 0, 0 },
37812 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37813 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52b0000 }
37814 },
37815/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37816 {
37817 { 0, 0, 0, 0 },
37818 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37819 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70b0000 }
37820 },
37821/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37822 {
37823 { 0, 0, 0, 0 },
37824 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37825 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72b0000 }
37826 },
37827/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37828 {
37829 { 0, 0, 0, 0 },
37830 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
37831 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38b0000 }
37832 },
37833/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37834 {
37835 { 0, 0, 0, 0 },
37836 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
37837 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ab0000 }
37838 },
37839/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37840 {
37841 { 0, 0, 0, 0 },
37842 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
37843 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58b0000 }
37844 },
37845/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37846 {
37847 { 0, 0, 0, 0 },
37848 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
37849 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ab0000 }
37850 },
37851/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37852 {
37853 { 0, 0, 0, 0 },
37854 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
37855 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cb0000 }
37856 },
37857/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37858 {
37859 { 0, 0, 0, 0 },
37860 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
37861 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3eb0000 }
37862 },
37863/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37864 {
37865 { 0, 0, 0, 0 },
37866 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
37867 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cb0000 }
37868 },
37869/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37870 {
37871 { 0, 0, 0, 0 },
37872 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
37873 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5eb0000 }
37874 },
37875/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37876 {
37877 { 0, 0, 0, 0 },
37878 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
37879 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cb0000 }
37880 },
37881/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
37882 {
37883 { 0, 0, 0, 0 },
37884 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
37885 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7eb0000 }
37886 },
37887/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37888 {
37889 { 0, 0, 0, 0 },
37890 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
37891 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78b0000 }
37892 },
37893/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
37894 {
37895 { 0, 0, 0, 0 },
37896 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
37897 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ab0000 }
37898 },
37899/* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
37900 {
37901 { 0, 0, 0, 0 },
37902 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37903 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90b }
37904 },
37905/* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
37906 {
37907 { 0, 0, 0, 0 },
37908 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37909 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892b }
37910 },
37911/* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37912 {
37913 { 0, 0, 0, 0 },
37914 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37915 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890b }
37916 },
37917/* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
37918 {
37919 { 0, 0, 0, 0 },
37920 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37921 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18b }
37922 },
37923/* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
37924 {
37925 { 0, 0, 0, 0 },
37926 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37927 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ab }
37928 },
37929/* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37930 {
37931 { 0, 0, 0, 0 },
37932 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37933 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818b }
37934 },
37935/* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
37936 {
37937 { 0, 0, 0, 0 },
37938 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37939 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10b }
37940 },
37941/* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
37942 {
37943 { 0, 0, 0, 0 },
37944 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37945 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812b }
37946 },
37947/* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37948 {
37949 { 0, 0, 0, 0 },
37950 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37951 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810b }
37952 },
37953/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37954 {
37955 { 0, 0, 0, 0 },
37956 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37957 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30b00 }
37958 },
37959/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37960 {
37961 { 0, 0, 0, 0 },
37962 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37963 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832b00 }
37964 },
37965/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37966 {
37967 { 0, 0, 0, 0 },
37968 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37969 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830b00 }
37970 },
37971/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37972 {
37973 { 0, 0, 0, 0 },
37974 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37975 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50b0000 }
37976 },
37977/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37978 {
37979 { 0, 0, 0, 0 },
37980 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37981 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852b0000 }
37982 },
37983/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37984 {
37985 { 0, 0, 0, 0 },
37986 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37987 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850b0000 }
37988 },
37989/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37990 {
37991 { 0, 0, 0, 0 },
37992 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37993 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70b0000 }
37994 },
37995/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37996 {
37997 { 0, 0, 0, 0 },
37998 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37999 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872b0000 }
38000 },
38001/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38002 {
38003 { 0, 0, 0, 0 },
38004 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38005 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870b0000 }
38006 },
38007/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
38008 {
38009 { 0, 0, 0, 0 },
38010 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38011 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38b00 }
38012 },
38013/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
38014 {
38015 { 0, 0, 0, 0 },
38016 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38017 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ab00 }
38018 },
38019/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38020 {
38021 { 0, 0, 0, 0 },
38022 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38023 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838b00 }
38024 },
38025/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
38026 {
38027 { 0, 0, 0, 0 },
38028 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38029 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58b0000 }
38030 },
38031/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
38032 {
38033 { 0, 0, 0, 0 },
38034 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38035 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ab0000 }
38036 },
38037/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38038 {
38039 { 0, 0, 0, 0 },
38040 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38041 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858b0000 }
38042 },
38043/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
38044 {
38045 { 0, 0, 0, 0 },
38046 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38047 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cb00 }
38048 },
38049/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
38050 {
38051 { 0, 0, 0, 0 },
38052 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38053 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83eb00 }
38054 },
38055/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38056 {
38057 { 0, 0, 0, 0 },
38058 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38059 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cb00 }
38060 },
38061/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
38062 {
38063 { 0, 0, 0, 0 },
38064 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38065 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cb0000 }
38066 },
38067/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
38068 {
38069 { 0, 0, 0, 0 },
38070 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38071 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85eb0000 }
38072 },
38073/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38074 {
38075 { 0, 0, 0, 0 },
38076 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38077 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cb0000 }
38078 },
38079/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
38080 {
38081 { 0, 0, 0, 0 },
38082 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
38083 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cb0000 }
38084 },
38085/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
38086 {
38087 { 0, 0, 0, 0 },
38088 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
38089 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87eb0000 }
38090 },
38091/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38092 {
38093 { 0, 0, 0, 0 },
38094 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
38095 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cb0000 }
38096 },
38097/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
38098 {
38099 { 0, 0, 0, 0 },
38100 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
38101 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78b0000 }
38102 },
38103/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
38104 {
38105 { 0, 0, 0, 0 },
38106 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
38107 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ab0000 }
38108 },
38109/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38110 {
38111 { 0, 0, 0, 0 },
38112 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
38113 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878b0000 }
38114 },
38115/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38116 {
38117 { 0, 0, 0, 0 },
38118 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38119 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980b00 }
38120 },
38121/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
38122 {
38123 { 0, 0, 0, 0 },
38124 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38125 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982b00 }
38126 },
38127/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
38128 {
38129 { 0, 0, 0, 0 },
38130 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38131 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983b00 }
38132 },
38133/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38134 {
38135 { 0, 0, 0, 0 },
38136 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38137 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908b00 }
38138 },
38139/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
38140 {
38141 { 0, 0, 0, 0 },
38142 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38143 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ab00 }
38144 },
38145/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
38146 {
38147 { 0, 0, 0, 0 },
38148 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38149 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bb00 }
38150 },
38151/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38152 {
38153 { 0, 0, 0, 0 },
38154 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38155 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900b00 }
38156 },
38157/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
38158 {
38159 { 0, 0, 0, 0 },
38160 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38161 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902b00 }
38162 },
38163/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
38164 {
38165 { 0, 0, 0, 0 },
38166 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38167 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903b00 }
38168 },
38169/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38170 {
38171 { 0, 0, 0, 0 },
38172 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38173 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920b0000 }
38174 },
38175/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38176 {
38177 { 0, 0, 0, 0 },
38178 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38179 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922b0000 }
38180 },
38181/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38182 {
38183 { 0, 0, 0, 0 },
38184 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38185 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923b0000 }
38186 },
38187/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38188 {
38189 { 0, 0, 0, 0 },
38190 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38191 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940b0000 }
38192 },
38193/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38194 {
38195 { 0, 0, 0, 0 },
38196 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38197 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942b0000 }
38198 },
38199/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38200 {
38201 { 0, 0, 0, 0 },
38202 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38203 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943b0000 }
38204 },
38205/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38206 {
38207 { 0, 0, 0, 0 },
38208 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38209 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960b0000 }
38210 },
38211/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38212 {
38213 { 0, 0, 0, 0 },
38214 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38215 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962b0000 }
38216 },
38217/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38218 {
38219 { 0, 0, 0, 0 },
38220 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38221 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963b0000 }
38222 },
38223/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
38224 {
38225 { 0, 0, 0, 0 },
38226 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38227 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928b0000 }
38228 },
38229/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38230 {
38231 { 0, 0, 0, 0 },
38232 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38233 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ab0000 }
38234 },
38235/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38236 {
38237 { 0, 0, 0, 0 },
38238 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38239 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bb0000 }
38240 },
38241/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
38242 {
38243 { 0, 0, 0, 0 },
38244 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38245 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948b0000 }
38246 },
38247/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38248 {
38249 { 0, 0, 0, 0 },
38250 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38251 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ab0000 }
38252 },
38253/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38254 {
38255 { 0, 0, 0, 0 },
38256 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38257 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bb0000 }
38258 },
38259/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
38260 {
38261 { 0, 0, 0, 0 },
38262 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38263 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cb0000 }
38264 },
38265/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38266 {
38267 { 0, 0, 0, 0 },
38268 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38269 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92eb0000 }
38270 },
38271/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38272 {
38273 { 0, 0, 0, 0 },
38274 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38275 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fb0000 }
38276 },
38277/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
38278 {
38279 { 0, 0, 0, 0 },
38280 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38281 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cb0000 }
38282 },
38283/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
38284 {
38285 { 0, 0, 0, 0 },
38286 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38287 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94eb0000 }
38288 },
38289/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
38290 {
38291 { 0, 0, 0, 0 },
38292 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38293 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fb0000 }
38294 },
38295/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
38296 {
38297 { 0, 0, 0, 0 },
38298 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
38299 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cb0000 }
38300 },
38301/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38302 {
38303 { 0, 0, 0, 0 },
38304 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
38305 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96eb0000 }
38306 },
38307/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38308 {
38309 { 0, 0, 0, 0 },
38310 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
38311 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fb0000 }
38312 },
38313/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
38314 {
38315 { 0, 0, 0, 0 },
38316 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
38317 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968b0000 }
38318 },
38319/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
38320 {
38321 { 0, 0, 0, 0 },
38322 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
38323 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ab0000 }
38324 },
38325/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
38326 {
38327 { 0, 0, 0, 0 },
38328 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
38329 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bb0000 }
38330 },
38331/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38332 {
38333 { 0, 0, 0, 0 },
38334 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38335 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80b0000 }
38336 },
38337/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
38338 {
38339 { 0, 0, 0, 0 },
38340 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38341 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82b0000 }
38342 },
38343/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
38344 {
38345 { 0, 0, 0, 0 },
38346 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38347 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83b0000 }
38348 },
38349/* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
38350 {
38351 { 0, 0, 0, 0 },
38352 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38353 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83b0000 }
38354 },
38355/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38356 {
38357 { 0, 0, 0, 0 },
38358 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38359 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08b0000 }
38360 },
38361/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
38362 {
38363 { 0, 0, 0, 0 },
38364 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38365 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ab0000 }
38366 },
38367/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
38368 {
38369 { 0, 0, 0, 0 },
38370 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38371 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bb0000 }
38372 },
38373/* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
38374 {
38375 { 0, 0, 0, 0 },
38376 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38377 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bb0000 }
38378 },
38379/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38380 {
38381 { 0, 0, 0, 0 },
38382 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38383 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00b0000 }
38384 },
38385/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
38386 {
38387 { 0, 0, 0, 0 },
38388 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38389 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02b0000 }
38390 },
38391/* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
38392 {
38393 { 0, 0, 0, 0 },
38394 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38395 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03b0000 }
38396 },
38397/* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
38398 {
38399 { 0, 0, 0, 0 },
38400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38401 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03b0000 }
38402 },
38403/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38404 {
38405 { 0, 0, 0, 0 },
38406 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38407 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20b0000 }
38408 },
38409/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38410 {
38411 { 0, 0, 0, 0 },
38412 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38413 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22b0000 }
38414 },
38415/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38416 {
38417 { 0, 0, 0, 0 },
38418 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38419 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23b0000 }
38420 },
38421/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
38422 {
38423 { 0, 0, 0, 0 },
38424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38425 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23b0000 }
38426 },
38427/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38428 {
38429 { 0, 0, 0, 0 },
38430 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38431 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40b0000 }
38432 },
38433/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38434 {
38435 { 0, 0, 0, 0 },
38436 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38437 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42b0000 }
38438 },
38439/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38440 {
38441 { 0, 0, 0, 0 },
38442 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38443 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43b0000 }
38444 },
38445/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
38446 {
38447 { 0, 0, 0, 0 },
38448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38449 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43b0000 }
38450 },
38451/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38452 {
38453 { 0, 0, 0, 0 },
38454 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38455 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60b0000 }
38456 },
38457/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38458 {
38459 { 0, 0, 0, 0 },
38460 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38461 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62b0000 }
38462 },
38463/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38464 {
38465 { 0, 0, 0, 0 },
38466 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38467 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63b0000 }
38468 },
38469/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
38470 {
38471 { 0, 0, 0, 0 },
38472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38473 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63b0000 }
38474 },
38475/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
38476 {
38477 { 0, 0, 0, 0 },
38478 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38479 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28b0000 }
38480 },
38481/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38482 {
38483 { 0, 0, 0, 0 },
38484 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38485 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ab0000 }
38486 },
38487/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
38488 {
38489 { 0, 0, 0, 0 },
38490 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38491 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bb0000 }
38492 },
38493/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38494 {
38495 { 0, 0, 0, 0 },
38496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38497 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bb0000 }
38498 },
38499/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
38500 {
38501 { 0, 0, 0, 0 },
38502 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38503 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48b0000 }
38504 },
38505/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38506 {
38507 { 0, 0, 0, 0 },
38508 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38509 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ab0000 }
38510 },
38511/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
38512 {
38513 { 0, 0, 0, 0 },
38514 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38515 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bb0000 }
38516 },
38517/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38518 {
38519 { 0, 0, 0, 0 },
38520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38521 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bb0000 }
38522 },
38523/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
38524 {
38525 { 0, 0, 0, 0 },
38526 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38527 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cb0000 }
38528 },
38529/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38530 {
38531 { 0, 0, 0, 0 },
38532 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38533 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2eb0000 }
38534 },
38535/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
38536 {
38537 { 0, 0, 0, 0 },
38538 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38539 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fb0000 }
38540 },
38541/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38542 {
38543 { 0, 0, 0, 0 },
38544 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38545 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fb0000 }
38546 },
38547/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
38548 {
38549 { 0, 0, 0, 0 },
38550 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38551 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cb0000 }
38552 },
38553/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
38554 {
38555 { 0, 0, 0, 0 },
38556 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38557 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4eb0000 }
38558 },
38559/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
38560 {
38561 { 0, 0, 0, 0 },
38562 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38563 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fb0000 }
38564 },
38565/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
38566 {
38567 { 0, 0, 0, 0 },
38568 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38569 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fb0000 }
38570 },
38571/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
38572 {
38573 { 0, 0, 0, 0 },
38574 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
38575 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cb0000 }
38576 },
38577/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38578 {
38579 { 0, 0, 0, 0 },
38580 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38581 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6eb0000 }
38582 },
38583/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
38584 {
38585 { 0, 0, 0, 0 },
38586 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38587 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fb0000 }
38588 },
38589/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38590 {
38591 { 0, 0, 0, 0 },
38592 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
38593 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fb0000 }
38594 },
38595/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
38596 {
38597 { 0, 0, 0, 0 },
38598 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
38599 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68b0000 }
38600 },
38601/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
38602 {
38603 { 0, 0, 0, 0 },
38604 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38605 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ab0000 }
38606 },
38607/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
38608 {
38609 { 0, 0, 0, 0 },
38610 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38611 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bb0000 }
38612 },
38613/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
38614 {
38615 { 0, 0, 0, 0 },
38616 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
38617 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bb0000 }
38618 },
38619/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38620 {
38621 { 0, 0, 0, 0 },
38622 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38623 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80b0000 }
38624 },
38625/* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
38626 {
38627 { 0, 0, 0, 0 },
38628 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38629 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82b0000 }
38630 },
38631/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38632 {
38633 { 0, 0, 0, 0 },
38634 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38635 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08b0000 }
38636 },
38637/* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
38638 {
38639 { 0, 0, 0, 0 },
38640 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38641 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ab0000 }
38642 },
38643/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38644 {
38645 { 0, 0, 0, 0 },
38646 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38647 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00b0000 }
38648 },
38649/* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
38650 {
38651 { 0, 0, 0, 0 },
38652 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38653 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02b0000 }
38654 },
38655/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
38656 {
38657 { 0, 0, 0, 0 },
38658 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38659 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20b0000 }
38660 },
38661/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
38662 {
38663 { 0, 0, 0, 0 },
38664 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38665 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22b0000 }
38666 },
38667/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
38668 {
38669 { 0, 0, 0, 0 },
38670 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38671 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40b0000 }
38672 },
38673/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
38674 {
38675 { 0, 0, 0, 0 },
38676 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38677 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42b0000 }
38678 },
38679/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
38680 {
38681 { 0, 0, 0, 0 },
38682 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38683 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60b0000 }
38684 },
38685/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
38686 {
38687 { 0, 0, 0, 0 },
38688 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38689 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62b0000 }
38690 },
38691/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
38692 {
38693 { 0, 0, 0, 0 },
38694 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
38695 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28b0000 }
38696 },
38697/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
38698 {
38699 { 0, 0, 0, 0 },
38700 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
38701 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ab0000 }
38702 },
38703/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
38704 {
38705 { 0, 0, 0, 0 },
38706 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
38707 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48b0000 }
38708 },
38709/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
38710 {
38711 { 0, 0, 0, 0 },
38712 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
38713 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ab0000 }
38714 },
38715/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
38716 {
38717 { 0, 0, 0, 0 },
38718 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
38719 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cb0000 }
38720 },
38721/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
38722 {
38723 { 0, 0, 0, 0 },
38724 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
38725 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2eb0000 }
38726 },
38727/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
38728 {
38729 { 0, 0, 0, 0 },
38730 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
38731 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cb0000 }
38732 },
38733/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
38734 {
38735 { 0, 0, 0, 0 },
38736 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
38737 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4eb0000 }
38738 },
38739/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
38740 {
38741 { 0, 0, 0, 0 },
38742 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
38743 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cb0000 }
38744 },
38745/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
38746 {
38747 { 0, 0, 0, 0 },
38748 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
38749 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6eb0000 }
38750 },
38751/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
38752 {
38753 { 0, 0, 0, 0 },
38754 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
38755 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68b0000 }
38756 },
38757/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
38758 {
38759 { 0, 0, 0, 0 },
38760 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
38761 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ab0000 }
38762 },
38763/* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
38764 {
38765 { 0, 0, 0, 0 },
38766 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38767 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80b }
38768 },
38769/* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
38770 {
38771 { 0, 0, 0, 0 },
38772 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38773 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882b }
38774 },
38775/* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38776 {
38777 { 0, 0, 0, 0 },
38778 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38779 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880b }
38780 },
38781/* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
38782 {
38783 { 0, 0, 0, 0 },
38784 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38785 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08b }
38786 },
38787/* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
38788 {
38789 { 0, 0, 0, 0 },
38790 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38791 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ab }
38792 },
38793/* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38794 {
38795 { 0, 0, 0, 0 },
38796 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38797 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808b }
38798 },
38799/* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
38800 {
38801 { 0, 0, 0, 0 },
38802 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38803 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00b }
38804 },
38805/* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
38806 {
38807 { 0, 0, 0, 0 },
38808 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38809 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802b }
38810 },
38811/* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38812 {
38813 { 0, 0, 0, 0 },
38814 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38815 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800b }
38816 },
38817/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38818 {
38819 { 0, 0, 0, 0 },
38820 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38821 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20b00 }
38822 },
38823/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38824 {
38825 { 0, 0, 0, 0 },
38826 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38827 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822b00 }
38828 },
38829/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
38830 {
38831 { 0, 0, 0, 0 },
38832 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38833 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820b00 }
38834 },
38835/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38836 {
38837 { 0, 0, 0, 0 },
38838 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38839 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40b0000 }
38840 },
38841/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38842 {
38843 { 0, 0, 0, 0 },
38844 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38845 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842b0000 }
38846 },
38847/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
38848 {
38849 { 0, 0, 0, 0 },
38850 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38851 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840b0000 }
38852 },
38853/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38854 {
38855 { 0, 0, 0, 0 },
38856 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38857 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60b0000 }
38858 },
38859/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38860 {
38861 { 0, 0, 0, 0 },
38862 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38863 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862b0000 }
38864 },
38865/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38866 {
38867 { 0, 0, 0, 0 },
38868 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38869 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860b0000 }
38870 },
38871/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
38872 {
38873 { 0, 0, 0, 0 },
38874 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38875 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28b00 }
38876 },
38877/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
38878 {
38879 { 0, 0, 0, 0 },
38880 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38881 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ab00 }
38882 },
38883/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38884 {
38885 { 0, 0, 0, 0 },
38886 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38887 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828b00 }
38888 },
38889/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
38890 {
38891 { 0, 0, 0, 0 },
38892 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38893 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48b0000 }
38894 },
38895/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
38896 {
38897 { 0, 0, 0, 0 },
38898 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38899 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ab0000 }
38900 },
38901/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38902 {
38903 { 0, 0, 0, 0 },
38904 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38905 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848b0000 }
38906 },
38907/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
38908 {
38909 { 0, 0, 0, 0 },
38910 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38911 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cb00 }
38912 },
38913/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
38914 {
38915 { 0, 0, 0, 0 },
38916 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38917 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82eb00 }
38918 },
38919/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38920 {
38921 { 0, 0, 0, 0 },
38922 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38923 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cb00 }
38924 },
38925/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
38926 {
38927 { 0, 0, 0, 0 },
38928 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38929 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cb0000 }
38930 },
38931/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
38932 {
38933 { 0, 0, 0, 0 },
38934 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38935 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84eb0000 }
38936 },
38937/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38938 {
38939 { 0, 0, 0, 0 },
38940 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38941 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cb0000 }
38942 },
38943/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
38944 {
38945 { 0, 0, 0, 0 },
38946 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
38947 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cb0000 }
38948 },
38949/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
38950 {
38951 { 0, 0, 0, 0 },
38952 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
38953 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86eb0000 }
38954 },
38955/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38956 {
38957 { 0, 0, 0, 0 },
38958 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
38959 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cb0000 }
38960 },
38961/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
38962 {
38963 { 0, 0, 0, 0 },
38964 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
38965 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68b0000 }
38966 },
38967/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
38968 {
38969 { 0, 0, 0, 0 },
38970 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
38971 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ab0000 }
38972 },
38973/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38974 {
38975 { 0, 0, 0, 0 },
38976 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
38977 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868b0000 }
38978 },
38979/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
38980 {
38981 { 0, 0, 0, 0 },
38982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
38983 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x738000 }
38984 },
38985/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
38986 {
38987 { 0, 0, 0, 0 },
38988 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
38989 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x73a000 }
38990 },
38991/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
38992 {
38993 { 0, 0, 0, 0 },
38994 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
38995 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x73b000 }
38996 },
38997/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
38998 {
38999 { 0, 0, 0, 0 },
39000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39001 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x738400 }
39002 },
39003/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
39004 {
39005 { 0, 0, 0, 0 },
39006 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
39007 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x73a400 }
39008 },
39009/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
39010 {
39011 { 0, 0, 0, 0 },
39012 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
39013 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x73b400 }
39014 },
39015/* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
39016 {
39017 { 0, 0, 0, 0 },
39018 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39019 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x738600 }
39020 },
39021/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
39022 {
39023 { 0, 0, 0, 0 },
39024 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39025 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x73a600 }
39026 },
39027/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
39028 {
39029 { 0, 0, 0, 0 },
39030 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39031 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x73b600 }
39032 },
39033/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
39034 {
39035 { 0, 0, 0, 0 },
39036 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39037 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x73880000 }
39038 },
39039/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
39040 {
39041 { 0, 0, 0, 0 },
39042 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39043 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x73a80000 }
39044 },
39045/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
39046 {
39047 { 0, 0, 0, 0 },
39048 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39049 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x73b80000 }
39050 },
39051/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
39052 {
39053 { 0, 0, 0, 0 },
39054 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39055 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x738c0000 }
39056 },
39057/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
39058 {
39059 { 0, 0, 0, 0 },
39060 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39061 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x73ac0000 }
39062 },
39063/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
39064 {
39065 { 0, 0, 0, 0 },
39066 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39067 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x73bc0000 }
39068 },
39069/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
39070 {
39071 { 0, 0, 0, 0 },
39072 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39073 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x738a0000 }
39074 },
39075/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
39076 {
39077 { 0, 0, 0, 0 },
39078 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39079 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73aa0000 }
39080 },
39081/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
39082 {
39083 { 0, 0, 0, 0 },
39084 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39085 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73ba0000 }
39086 },
39087/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
39088 {
39089 { 0, 0, 0, 0 },
39090 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39091 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x738e0000 }
39092 },
39093/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
39094 {
39095 { 0, 0, 0, 0 },
39096 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39097 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73ae0000 }
39098 },
39099/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
39100 {
39101 { 0, 0, 0, 0 },
39102 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39103 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73be0000 }
39104 },
39105/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
39106 {
39107 { 0, 0, 0, 0 },
39108 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39109 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x738b0000 }
39110 },
39111/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
39112 {
39113 { 0, 0, 0, 0 },
39114 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39115 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73ab0000 }
39116 },
39117/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
39118 {
39119 { 0, 0, 0, 0 },
39120 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39121 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73bb0000 }
39122 },
39123/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
39124 {
39125 { 0, 0, 0, 0 },
39126 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
39127 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x738f0000 }
39128 },
39129/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
39130 {
39131 { 0, 0, 0, 0 },
39132 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39133 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x73af0000 }
39134 },
39135/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
39136 {
39137 { 0, 0, 0, 0 },
39138 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39139 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x73bf0000 }
39140 },
39141/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
39142 {
39143 { 0, 0, 0, 0 },
39144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39145 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x73c00000 }
39146 },
39147/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
39148 {
39149 { 0, 0, 0, 0 },
39150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
39151 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x73e00000 }
39152 },
39153/* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
39154 {
39155 { 0, 0, 0, 0 },
39156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
39157 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x73f00000 }
39158 },
39159/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
39160 {
39161 { 0, 0, 0, 0 },
39162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39163 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x73c40000 }
39164 },
39165/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
39166 {
39167 { 0, 0, 0, 0 },
39168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
39169 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x73e40000 }
39170 },
39171/* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
39172 {
39173 { 0, 0, 0, 0 },
39174 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
39175 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x73f40000 }
39176 },
39177/* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
39178 {
39179 { 0, 0, 0, 0 },
39180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39181 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x73c60000 }
39182 },
39183/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
39184 {
39185 { 0, 0, 0, 0 },
39186 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39187 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x73e60000 }
39188 },
39189/* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
39190 {
39191 { 0, 0, 0, 0 },
39192 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
39193 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x73f60000 }
39194 },
39195/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
39196 {
39197 { 0, 0, 0, 0 },
39198 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39199 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x73c80000 }
39200 },
39201/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
39202 {
39203 { 0, 0, 0, 0 },
39204 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39205 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x73e80000 }
39206 },
39207/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
39208 {
39209 { 0, 0, 0, 0 },
39210 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39211 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x73f80000 }
39212 },
39213/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
39214 {
39215 { 0, 0, 0, 0 },
39216 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39217 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x73cc0000 }
39218 },
39219/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
39220 {
39221 { 0, 0, 0, 0 },
39222 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39223 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x73ec0000 }
39224 },
39225/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
39226 {
39227 { 0, 0, 0, 0 },
39228 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39229 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x73fc0000 }
39230 },
39231/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
39232 {
39233 { 0, 0, 0, 0 },
39234 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39235 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ca0000 }
39236 },
39237/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
39238 {
39239 { 0, 0, 0, 0 },
39240 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39241 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ea0000 }
39242 },
39243/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
39244 {
39245 { 0, 0, 0, 0 },
39246 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39247 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x73fa0000 }
39248 },
39249/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
39250 {
39251 { 0, 0, 0, 0 },
39252 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39253 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ce0000 }
39254 },
39255/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
39256 {
39257 { 0, 0, 0, 0 },
39258 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39259 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ee0000 }
39260 },
39261/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
39262 {
39263 { 0, 0, 0, 0 },
39264 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39265 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x73fe0000 }
39266 },
39267/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
39268 {
39269 { 0, 0, 0, 0 },
39270 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39271 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x73cb0000 }
39272 },
39273/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
39274 {
39275 { 0, 0, 0, 0 },
39276 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39277 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x73eb0000 }
39278 },
39279/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
39280 {
39281 { 0, 0, 0, 0 },
39282 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39283 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x73fb0000 }
39284 },
39285/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
39286 {
39287 { 0, 0, 0, 0 },
39288 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
39289 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x73cf0000 }
39290 },
39291/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
39292 {
39293 { 0, 0, 0, 0 },
39294 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
39295 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x73ef0000 }
39296 },
39297/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
39298 {
39299 { 0, 0, 0, 0 },
39300 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
39301 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x73ff0000 }
39302 },
39303/* mov.w${G} $Src16RnHI,$Dst16RnHI */
39304 {
39305 { 0, 0, 0, 0 },
39306 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
39307 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7300 }
39308 },
39309/* mov.w${G} $Src16AnHI,$Dst16RnHI */
39310 {
39311 { 0, 0, 0, 0 },
39312 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
39313 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7340 }
39314 },
39315/* mov.w${G} [$Src16An],$Dst16RnHI */
39316 {
39317 { 0, 0, 0, 0 },
39318 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39319 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7360 }
39320 },
39321/* mov.w${G} $Src16RnHI,$Dst16AnHI */
39322 {
39323 { 0, 0, 0, 0 },
39324 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
39325 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7304 }
39326 },
39327/* mov.w${G} $Src16AnHI,$Dst16AnHI */
39328 {
39329 { 0, 0, 0, 0 },
39330 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
39331 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7344 }
39332 },
39333/* mov.w${G} [$Src16An],$Dst16AnHI */
39334 {
39335 { 0, 0, 0, 0 },
39336 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39337 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7364 }
39338 },
39339/* mov.w${G} $Src16RnHI,[$Dst16An] */
39340 {
39341 { 0, 0, 0, 0 },
39342 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
39343 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7306 }
39344 },
39345/* mov.w${G} $Src16AnHI,[$Dst16An] */
39346 {
39347 { 0, 0, 0, 0 },
39348 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
39349 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7346 }
39350 },
39351/* mov.w${G} [$Src16An],[$Dst16An] */
39352 {
39353 { 0, 0, 0, 0 },
39354 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39355 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7366 }
39356 },
39357/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
39358 {
39359 { 0, 0, 0, 0 },
39360 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39361 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x730800 }
39362 },
39363/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
39364 {
39365 { 0, 0, 0, 0 },
39366 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39367 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x734800 }
39368 },
39369/* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
39370 {
39371 { 0, 0, 0, 0 },
39372 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39373 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x736800 }
39374 },
39375/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
39376 {
39377 { 0, 0, 0, 0 },
39378 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39379 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x730c0000 }
39380 },
39381/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
39382 {
39383 { 0, 0, 0, 0 },
39384 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39385 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x734c0000 }
39386 },
39387/* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
39388 {
39389 { 0, 0, 0, 0 },
39390 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39391 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x736c0000 }
39392 },
39393/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
39394 {
39395 { 0, 0, 0, 0 },
39396 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39397 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x730a00 }
39398 },
39399/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
39400 {
39401 { 0, 0, 0, 0 },
39402 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39403 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x734a00 }
39404 },
39405/* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
39406 {
39407 { 0, 0, 0, 0 },
39408 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39409 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x736a00 }
39410 },
39411/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
39412 {
39413 { 0, 0, 0, 0 },
39414 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39415 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x730e0000 }
39416 },
39417/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
39418 {
39419 { 0, 0, 0, 0 },
39420 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39421 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x734e0000 }
39422 },
39423/* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
39424 {
39425 { 0, 0, 0, 0 },
39426 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39427 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x736e0000 }
39428 },
39429/* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
39430 {
39431 { 0, 0, 0, 0 },
39432 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39433 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x730b00 }
39434 },
39435/* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
39436 {
39437 { 0, 0, 0, 0 },
39438 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39439 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x734b00 }
39440 },
39441/* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
39442 {
39443 { 0, 0, 0, 0 },
39444 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39445 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x736b00 }
39446 },
39447/* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
39448 {
39449 { 0, 0, 0, 0 },
39450 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
39451 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x730f0000 }
39452 },
39453/* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
39454 {
39455 { 0, 0, 0, 0 },
39456 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
39457 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x734f0000 }
39458 },
39459/* mov.w${G} [$Src16An],${Dsp-16-u16} */
39460 {
39461 { 0, 0, 0, 0 },
39462 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
39463 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x736f0000 }
39464 },
39465/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
39466 {
39467 { 0, 0, 0, 0 },
39468 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
39469 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x728000 }
39470 },
39471/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
39472 {
39473 { 0, 0, 0, 0 },
39474 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
39475 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x72a000 }
39476 },
39477/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
39478 {
39479 { 0, 0, 0, 0 },
39480 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
39481 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x72b000 }
39482 },
39483/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
39484 {
39485 { 0, 0, 0, 0 },
39486 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
39487 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x728400 }
39488 },
39489/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
39490 {
39491 { 0, 0, 0, 0 },
39492 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
39493 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x72a400 }
39494 },
39495/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
39496 {
39497 { 0, 0, 0, 0 },
39498 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
39499 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x72b400 }
39500 },
39501/* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
39502 {
39503 { 0, 0, 0, 0 },
39504 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39505 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x728600 }
39506 },
39507/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
39508 {
39509 { 0, 0, 0, 0 },
39510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39511 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x72a600 }
39512 },
39513/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
39514 {
39515 { 0, 0, 0, 0 },
39516 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39517 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x72b600 }
39518 },
39519/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
39520 {
39521 { 0, 0, 0, 0 },
39522 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39523 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x72880000 }
39524 },
39525/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
39526 {
39527 { 0, 0, 0, 0 },
39528 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39529 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x72a80000 }
39530 },
39531/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
39532 {
39533 { 0, 0, 0, 0 },
39534 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39535 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x72b80000 }
39536 },
39537/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
39538 {
39539 { 0, 0, 0, 0 },
39540 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39541 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x728c0000 }
39542 },
39543/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
39544 {
39545 { 0, 0, 0, 0 },
39546 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39547 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x72ac0000 }
39548 },
39549/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
39550 {
39551 { 0, 0, 0, 0 },
39552 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39553 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x72bc0000 }
39554 },
39555/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
39556 {
39557 { 0, 0, 0, 0 },
39558 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39559 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x728a0000 }
39560 },
39561/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
39562 {
39563 { 0, 0, 0, 0 },
39564 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39565 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72aa0000 }
39566 },
39567/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
39568 {
39569 { 0, 0, 0, 0 },
39570 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39571 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72ba0000 }
39572 },
39573/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
39574 {
39575 { 0, 0, 0, 0 },
39576 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39577 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x728e0000 }
39578 },
39579/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
39580 {
39581 { 0, 0, 0, 0 },
39582 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39583 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72ae0000 }
39584 },
39585/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
39586 {
39587 { 0, 0, 0, 0 },
39588 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39589 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72be0000 }
39590 },
39591/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
39592 {
39593 { 0, 0, 0, 0 },
39594 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39595 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x728b0000 }
39596 },
39597/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
39598 {
39599 { 0, 0, 0, 0 },
39600 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39601 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72ab0000 }
39602 },
39603/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
39604 {
39605 { 0, 0, 0, 0 },
39606 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39607 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72bb0000 }
39608 },
39609/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
39610 {
39611 { 0, 0, 0, 0 },
39612 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
39613 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x728f0000 }
39614 },
39615/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
39616 {
39617 { 0, 0, 0, 0 },
39618 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39619 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x72af0000 }
39620 },
39621/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
39622 {
39623 { 0, 0, 0, 0 },
39624 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39625 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x72bf0000 }
39626 },
39627/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
39628 {
39629 { 0, 0, 0, 0 },
39630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
39631 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x72c00000 }
39632 },
39633/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
39634 {
39635 { 0, 0, 0, 0 },
39636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
39637 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x72e00000 }
39638 },
39639/* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
39640 {
39641 { 0, 0, 0, 0 },
39642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
39643 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x72f00000 }
39644 },
39645/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
39646 {
39647 { 0, 0, 0, 0 },
39648 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
39649 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x72c40000 }
39650 },
39651/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
39652 {
39653 { 0, 0, 0, 0 },
39654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
39655 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x72e40000 }
39656 },
39657/* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
39658 {
39659 { 0, 0, 0, 0 },
39660 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
39661 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x72f40000 }
39662 },
39663/* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
39664 {
39665 { 0, 0, 0, 0 },
39666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39667 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x72c60000 }
39668 },
39669/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
39670 {
39671 { 0, 0, 0, 0 },
39672 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39673 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x72e60000 }
39674 },
39675/* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
39676 {
39677 { 0, 0, 0, 0 },
39678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
39679 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x72f60000 }
39680 },
39681/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
39682 {
39683 { 0, 0, 0, 0 },
39684 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39685 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x72c80000 }
39686 },
39687/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
39688 {
39689 { 0, 0, 0, 0 },
39690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39691 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x72e80000 }
39692 },
39693/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
39694 {
39695 { 0, 0, 0, 0 },
39696 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39697 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x72f80000 }
39698 },
39699/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
39700 {
39701 { 0, 0, 0, 0 },
39702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39703 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x72cc0000 }
39704 },
39705/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
39706 {
39707 { 0, 0, 0, 0 },
39708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39709 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x72ec0000 }
39710 },
39711/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
39712 {
39713 { 0, 0, 0, 0 },
39714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39715 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x72fc0000 }
39716 },
39717/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
39718 {
39719 { 0, 0, 0, 0 },
39720 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39721 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ca0000 }
39722 },
39723/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
39724 {
39725 { 0, 0, 0, 0 },
39726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39727 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ea0000 }
39728 },
39729/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
39730 {
39731 { 0, 0, 0, 0 },
39732 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39733 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x72fa0000 }
39734 },
39735/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
39736 {
39737 { 0, 0, 0, 0 },
39738 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39739 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ce0000 }
39740 },
39741/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
39742 {
39743 { 0, 0, 0, 0 },
39744 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39745 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ee0000 }
39746 },
39747/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
39748 {
39749 { 0, 0, 0, 0 },
39750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39751 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x72fe0000 }
39752 },
39753/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
39754 {
39755 { 0, 0, 0, 0 },
39756 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39757 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x72cb0000 }
39758 },
39759/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
39760 {
39761 { 0, 0, 0, 0 },
39762 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39763 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x72eb0000 }
39764 },
39765/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
39766 {
39767 { 0, 0, 0, 0 },
39768 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39769 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x72fb0000 }
39770 },
39771/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
39772 {
39773 { 0, 0, 0, 0 },
39774 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
39775 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x72cf0000 }
39776 },
39777/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
39778 {
39779 { 0, 0, 0, 0 },
39780 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
39781 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x72ef0000 }
39782 },
39783/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
39784 {
39785 { 0, 0, 0, 0 },
39786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
39787 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x72ff0000 }
39788 },
39789/* mov.b${G} $Src16RnQI,$Dst16RnQI */
39790 {
39791 { 0, 0, 0, 0 },
39792 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
39793 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7200 }
39794 },
39795/* mov.b${G} $Src16AnQI,$Dst16RnQI */
39796 {
39797 { 0, 0, 0, 0 },
39798 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
39799 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7240 }
39800 },
39801/* mov.b${G} [$Src16An],$Dst16RnQI */
39802 {
39803 { 0, 0, 0, 0 },
39804 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
39805 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7260 }
39806 },
39807/* mov.b${G} $Src16RnQI,$Dst16AnQI */
39808 {
39809 { 0, 0, 0, 0 },
39810 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
39811 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7204 }
39812 },
39813/* mov.b${G} $Src16AnQI,$Dst16AnQI */
39814 {
39815 { 0, 0, 0, 0 },
39816 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
39817 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7244 }
39818 },
39819/* mov.b${G} [$Src16An],$Dst16AnQI */
39820 {
39821 { 0, 0, 0, 0 },
39822 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
39823 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7264 }
39824 },
39825/* mov.b${G} $Src16RnQI,[$Dst16An] */
39826 {
39827 { 0, 0, 0, 0 },
39828 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
39829 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7206 }
39830 },
39831/* mov.b${G} $Src16AnQI,[$Dst16An] */
39832 {
39833 { 0, 0, 0, 0 },
39834 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
39835 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7246 }
39836 },
39837/* mov.b${G} [$Src16An],[$Dst16An] */
39838 {
39839 { 0, 0, 0, 0 },
39840 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39841 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7266 }
39842 },
39843/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
39844 {
39845 { 0, 0, 0, 0 },
39846 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39847 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x720800 }
39848 },
39849/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
39850 {
39851 { 0, 0, 0, 0 },
39852 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39853 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x724800 }
39854 },
39855/* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
39856 {
39857 { 0, 0, 0, 0 },
39858 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39859 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x726800 }
39860 },
39861/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
39862 {
39863 { 0, 0, 0, 0 },
39864 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39865 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x720c0000 }
39866 },
39867/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
39868 {
39869 { 0, 0, 0, 0 },
39870 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39871 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x724c0000 }
39872 },
39873/* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
39874 {
39875 { 0, 0, 0, 0 },
39876 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39877 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x726c0000 }
39878 },
39879/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
39880 {
39881 { 0, 0, 0, 0 },
39882 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39883 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x720a00 }
39884 },
39885/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
39886 {
39887 { 0, 0, 0, 0 },
39888 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39889 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x724a00 }
39890 },
39891/* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
39892 {
39893 { 0, 0, 0, 0 },
39894 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39895 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x726a00 }
39896 },
39897/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
39898 {
39899 { 0, 0, 0, 0 },
39900 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39901 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x720e0000 }
39902 },
39903/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
39904 {
39905 { 0, 0, 0, 0 },
39906 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39907 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x724e0000 }
39908 },
39909/* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
39910 {
39911 { 0, 0, 0, 0 },
39912 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39913 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x726e0000 }
39914 },
39915/* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
39916 {
39917 { 0, 0, 0, 0 },
39918 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39919 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x720b00 }
39920 },
39921/* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
39922 {
39923 { 0, 0, 0, 0 },
39924 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39925 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x724b00 }
39926 },
39927/* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
39928 {
39929 { 0, 0, 0, 0 },
39930 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39931 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x726b00 }
39932 },
39933/* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
39934 {
39935 { 0, 0, 0, 0 },
39936 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
39937 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x720f0000 }
39938 },
39939/* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
39940 {
39941 { 0, 0, 0, 0 },
39942 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
39943 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x724f0000 }
39944 },
39945/* mov.b${G} [$Src16An],${Dsp-16-u16} */
39946 {
39947 { 0, 0, 0, 0 },
39948 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
39949 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x726f0000 }
39950 },
39951/* mov.w${Z} #0,${Dsp-8-u8}[sb] */
39952 {
39953 { 0, 0, 0, 0 },
39954 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
39955 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2300 }
39956 },
39957/* mov.w${Z} #0,${Dsp-8-s8}[fb] */
39958 {
39959 { 0, 0, 0, 0 },
39960 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
39961 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3300 }
39962 },
39963/* mov.w${Z} #0,${Dsp-8-u16} */
39964 {
39965 { 0, 0, 0, 0 },
39966 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
39967 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x130000 }
39968 },
39969/* mov.w${Z} #0,r0 */
39970 {
39971 { 0, 0, 0, 0 },
39972 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 0 } },
f75eb1c0 39973 & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x3 }
49f58d10
JB		 39974 },
39975/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
39976 {
39977 { 0, 0, 0, 0 },
39978 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
39979 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2200 }
39980 },
39981/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
39982 {
39983 { 0, 0, 0, 0 },
39984 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
39985 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3200 }
39986 },
39987/* mov.b${Z} #0,${Dsp-8-u16} */
39988 {
39989 { 0, 0, 0, 0 },
39990 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
39991 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x120000 }
39992 },
39993/* mov.b${Z} #0,r0l */
39994 {
39995 { 0, 0, 0, 0 },
39996 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } },
39997 & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x2 }
39998 },
39999/* mov.b${Z} #0,r0l */
40000 {
40001 { 0, 0, 0, 0 },
40002 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } },
40003 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xb4 }
40004 },
40005/* mov.b${Z} #0,r0h */
40006 {
40007 { 0, 0, 0, 0 },
40008 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'h', 0 } },
40009 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xb3 }
40010 },
40011/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
40012 {
40013 { 0, 0, 0, 0 },
40014 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40015 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xb500 }
40016 },
40017/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
40018 {
40019 { 0, 0, 0, 0 },
40020 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40021 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xb600 }
40022 },
40023/* mov.b${Z} #0,${Dsp-8-u16} */
40024 {
40025 { 0, 0, 0, 0 },
40026 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
40027 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xb70000 }
40028 },
49f58d10
JB		 40029/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
40030 {
40031 { 0, 0, 0, 0 },
40032 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
40033 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf920 }
40034 },
40035/* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
40036 {
40037 { 0, 0, 0, 0 },
40038 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
40039 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf1a0 }
40040 },
40041/* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
40042 {
40043 { 0, 0, 0, 0 },
40044 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40045 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf120 }
40046 },
40047/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40048 {
40049 { 0, 0, 0, 0 },
40050 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40051 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf32000 }
40052 },
40053/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40054 {
40055 { 0, 0, 0, 0 },
40056 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40057 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5200000 }
40058 },
40059/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40060 {
40061 { 0, 0, 0, 0 },
40062 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40063 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7200000 }
40064 },
40065/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
40066 {
40067 { 0, 0, 0, 0 },
40068 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40069 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3a000 }
40070 },
40071/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
40072 {
40073 { 0, 0, 0, 0 },
40074 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40075 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5a00000 }
40076 },
40077/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
40078 {
40079 { 0, 0, 0, 0 },
40080 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40081 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3e000 }
40082 },
40083/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
40084 {
40085 { 0, 0, 0, 0 },
40086 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40087 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5e00000 }
40088 },
40089/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
40090 {
40091 { 0, 0, 0, 0 },
40092 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
40093 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7e00000 }
40094 },
40095/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
40096 {
40097 { 0, 0, 0, 0 },
40098 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
40099 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7a00000 }
40100 },
40101/* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
40102 {
40103 { 0, 0, 0, 0 },
40104 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
40105 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf820 }
40106 },
40107/* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
40108 {
40109 { 0, 0, 0, 0 },
40110 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
40111 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf0a0 }
40112 },
40113/* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
40114 {
40115 { 0, 0, 0, 0 },
40116 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40117 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf020 }
40118 },
40119/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40120 {
40121 { 0, 0, 0, 0 },
40122 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40123 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf22000 }
40124 },
40125/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40126 {
40127 { 0, 0, 0, 0 },
40128 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40129 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4200000 }
40130 },
40131/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40132 {
40133 { 0, 0, 0, 0 },
40134 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40135 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6200000 }
40136 },
40137/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
40138 {
40139 { 0, 0, 0, 0 },
40140 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40141 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2a000 }
40142 },
40143/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
40144 {
40145 { 0, 0, 0, 0 },
40146 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40147 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4a00000 }
40148 },
40149/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
40150 {
40151 { 0, 0, 0, 0 },
40152 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40153 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2e000 }
40154 },
40155/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
40156 {
40157 { 0, 0, 0, 0 },
40158 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40159 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4e00000 }
40160 },
40161/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
40162 {
40163 { 0, 0, 0, 0 },
40164 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
40165 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6e00000 }
40166 },
40167/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
40168 {
40169 { 0, 0, 0, 0 },
40170 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
40171 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6a00000 }
40172 },
40173/* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */
40174 {
40175 { 0, 0, 0, 0 },
40176 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
40177 & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xd900 }
40178 },
40179/* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */
40180 {
40181 { 0, 0, 0, 0 },
40182 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
40183 & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xd904 }
40184 },
40185/* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
40186 {
40187 { 0, 0, 0, 0 },
40188 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
40189 & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xd906 }
40190 },
40191/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
40192 {
40193 { 0, 0, 0, 0 },
40194 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40195 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd90800 }
40196 },
40197/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
40198 {
40199 { 0, 0, 0, 0 },
40200 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40201 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd90c0000 }
40202 },
40203/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
40204 {
40205 { 0, 0, 0, 0 },
40206 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40207 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd90a00 }
40208 },
40209/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
40210 {
40211 { 0, 0, 0, 0 },
40212 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40213 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd90e0000 }
40214 },
40215/* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
40216 {
40217 { 0, 0, 0, 0 },
40218 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40219 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd90b00 }
40220 },
40221/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
40222 {
40223 { 0, 0, 0, 0 },
40224 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
40225 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd90f0000 }
40226 },
40227/* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
40228 {
40229 { 0, 0, 0, 0 },
40230 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
40231 & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xd800 }
40232 },
40233/* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
40234 {
40235 { 0, 0, 0, 0 },
40236 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
40237 & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xd804 }
40238 },
40239/* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
40240 {
40241 { 0, 0, 0, 0 },
40242 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
40243 & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xd806 }
40244 },
40245/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
40246 {
40247 { 0, 0, 0, 0 },
40248 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40249 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd80800 }
40250 },
40251/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
40252 {
40253 { 0, 0, 0, 0 },
40254 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40255 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd80c0000 }
40256 },
40257/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
40258 {
40259 { 0, 0, 0, 0 },
40260 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40261 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd80a00 }
40262 },
40263/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
40264 {
40265 { 0, 0, 0, 0 },
40266 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40267 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd80e0000 }
40268 },
40269/* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
40270 {
40271 { 0, 0, 0, 0 },
40272 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40273 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd80b00 }
40274 },
40275/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
40276 {
40277 { 0, 0, 0, 0 },
40278 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
40279 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd80f0000 }
40280 },
e729279b
NC		 40281/* mov.b${S} #${Imm-8-QI},r0l */
40282 {
40283 { 0, 0, 0, 0 },
40284 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
40285 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 }
40286 },
40287/* mov.b${S} #${Imm-8-QI},r0h */
40288 {
40289 { 0, 0, 0, 0 },
40290 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
40291 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 }
40292 },
40293/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
40294 {
40295 { 0, 0, 0, 0 },
40296 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40297 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 }
40298 },
40299/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
40300 {
40301 { 0, 0, 0, 0 },
40302 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40303 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 }
40304 },
40305/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
40306 {
40307 { 0, 0, 0, 0 },
40308 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
40309 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 }
40310 },
40311/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
40312 {
40313 { 0, 0, 0, 0 },
40314 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40315 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 }
40316 },
40317/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
40318 {
40319 { 0, 0, 0, 0 },
40320 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40321 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 }
40322 },
40323/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
40324 {
40325 { 0, 0, 0, 0 },
40326 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
40327 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 }
40328 },
40329/* mov.w${S} #${Imm-8-HI},r0 */
40330 {
40331 { 0, 0, 0, 0 },
40332 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
40333 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 }
40334 },
40335/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
40336 {
40337 { 0, 0, 0, 0 },
40338 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40339 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 }
40340 },
40341/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
40342 {
40343 { 0, 0, 0, 0 },
40344 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40345 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 }
40346 },
40347/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
40348 {
40349 { 0, 0, 0, 0 },
40350 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
40351 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 }
40352 },
40353/* mov.b${S} #${Imm-8-QI},r0l */
40354 {
40355 { 0, 0, 0, 0 },
40356 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
40357 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 }
40358 },
49f58d10
JB		 40359/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
40360 {
40361 { 0, 0, 0, 0 },
40362 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
40363 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb8310000 }
40364 },
40365/* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
40366 {
40367 { 0, 0, 0, 0 },
40368 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
40369 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb0b10000 }
40370 },
40371/* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
40372 {
40373 { 0, 0, 0, 0 },
40374 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40375 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb0310000 }
40376 },
40377/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40378 {
40379 { 0, 0, 0, 0 },
40380 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40381 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2310000 }
40382 },
40383/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
40384 {
40385 { 0, 0, 0, 0 },
40386 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40387 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2b10000 }
40388 },
40389/* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
40390 {
40391 { 0, 0, 0, 0 },
40392 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40393 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2f10000 }
40394 },
40395/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40396 {
40397 { 0, 0, 0, 0 },
40398 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40399 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4310000 }
40400 },
40401/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
40402 {
40403 { 0, 0, 0, 0 },
40404 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40405 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4b10000 }
40406 },
40407/* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
40408 {
40409 { 0, 0, 0, 0 },
40410 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40411 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4f10000 }
40412 },
40413/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
40414 {
40415 { 0, 0, 0, 0 },
40416 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
40417 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6f10000 }
40418 },
40419/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40420 {
40421 { 0, 0, 0, 0 },
40422 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40423 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6310000 }
40424 },
40425/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
40426 {
40427 { 0, 0, 0, 0 },
40428 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
40429 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6b10000 }
40430 },
40431/* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
40432 {
40433 { 0, 0, 0, 0 },
40434 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
40435 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992f0000 }
40436 },
40437/* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
40438 {
40439 { 0, 0, 0, 0 },
40440 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
40441 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91af0000 }
40442 },
40443/* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
40444 {
40445 { 0, 0, 0, 0 },
40446 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40447 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912f0000 }
40448 },
40449/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40450 {
40451 { 0, 0, 0, 0 },
40452 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40453 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932f0000 }
40454 },
40455/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
40456 {
40457 { 0, 0, 0, 0 },
40458 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40459 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93af0000 }
40460 },
40461/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
40462 {
40463 { 0, 0, 0, 0 },
40464 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40465 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ef0000 }
40466 },
40467/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40468 {
40469 { 0, 0, 0, 0 },
40470 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40471 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952f0000 }
40472 },
40473/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
40474 {
40475 { 0, 0, 0, 0 },
40476 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40477 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95af0000 }
40478 },
40479/* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
40480 {
40481 { 0, 0, 0, 0 },
40482 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40483 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ef0000 }
40484 },
40485/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
40486 {
40487 { 0, 0, 0, 0 },
40488 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
40489 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ef0000 }
40490 },
40491/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40492 {
40493 { 0, 0, 0, 0 },
40494 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40495 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972f0000 }
40496 },
40497/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
40498 {
40499 { 0, 0, 0, 0 },
40500 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
40501 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97af0000 }
40502 },
40503/* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
40504 {
40505 { 0, 0, 0, 0 },
40506 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
40507 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982f00 }
40508 },
40509/* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
40510 {
40511 { 0, 0, 0, 0 },
40512 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
40513 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90af00 }
40514 },
40515/* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
40516 {
40517 { 0, 0, 0, 0 },
40518 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40519 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902f00 }
40520 },
40521/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40522 {
40523 { 0, 0, 0, 0 },
40524 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40525 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922f0000 }
40526 },
40527/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
40528 {
40529 { 0, 0, 0, 0 },
40530 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40531 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92af0000 }
40532 },
40533/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
40534 {
40535 { 0, 0, 0, 0 },
40536 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40537 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ef0000 }
40538 },
40539/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40540 {
40541 { 0, 0, 0, 0 },
40542 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40543 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942f0000 }
40544 },
40545/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
40546 {
40547 { 0, 0, 0, 0 },
40548 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40549 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94af0000 }
40550 },
40551/* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
40552 {
40553 { 0, 0, 0, 0 },
40554 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40555 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ef0000 }
40556 },
40557/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
40558 {
40559 { 0, 0, 0, 0 },
40560 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
40561 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ef0000 }
40562 },
40563/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40564 {
40565 { 0, 0, 0, 0 },
40566 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40567 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962f0000 }
40568 },
40569/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
40570 {
40571 { 0, 0, 0, 0 },
40572 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
40573 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96af0000 }
40574 },
40575/* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
40576 {
40577 { 0, 0, 0, 0 },
40578 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
40579 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x75c00000 }
40580 },
40581/* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
40582 {
40583 { 0, 0, 0, 0 },
40584 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
40585 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x75c40000 }
40586 },
40587/* mov.w${G} #${Imm-16-HI},[$Dst16An] */
40588 {
40589 { 0, 0, 0, 0 },
40590 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
40591 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x75c60000 }
40592 },
40593/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
40594 {
40595 { 0, 0, 0, 0 },
40596 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40597 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x75c80000 }
40598 },
40599/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
40600 {
40601 { 0, 0, 0, 0 },
40602 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40603 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x75ca0000 }
40604 },
40605/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
40606 {
40607 { 0, 0, 0, 0 },
40608 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40609 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x75cb0000 }
40610 },
40611/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
40612 {
40613 { 0, 0, 0, 0 },
40614 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40615 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x75cc0000 }
40616 },
40617/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
40618 {
40619 { 0, 0, 0, 0 },
40620 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40621 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x75ce0000 }
40622 },
40623/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
40624 {
40625 { 0, 0, 0, 0 },
40626 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
40627 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x75cf0000 }
40628 },
40629/* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
40630 {
40631 { 0, 0, 0, 0 },
40632 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
40633 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x74c000 }
40634 },
40635/* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
40636 {
40637 { 0, 0, 0, 0 },
40638 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
40639 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x74c400 }
40640 },
40641/* mov.b${G} #${Imm-16-QI},[$Dst16An] */
40642 {
40643 { 0, 0, 0, 0 },
40644 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
40645 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x74c600 }
40646 },
40647/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
40648 {
40649 { 0, 0, 0, 0 },
40650 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40651 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x74c80000 }
40652 },
40653/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
40654 {
40655 { 0, 0, 0, 0 },
40656 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40657 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x74ca0000 }
40658 },
40659/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
40660 {
40661 { 0, 0, 0, 0 },
40662 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40663 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x74cb0000 }
40664 },
40665/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
40666 {
40667 { 0, 0, 0, 0 },
40668 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40669 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x74cc0000 }
40670 },
40671/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
40672 {
40673 { 0, 0, 0, 0 },
40674 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40675 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x74ce0000 }
40676 },
40677/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
40678 {
40679 { 0, 0, 0, 0 },
40680 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
40681 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x74cf0000 }
40682 },
40683/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40684 {
40685 { 0, 0, 0, 0 },
40686 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
40687 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990c00 }
40688 },
40689/* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
40690 {
40691 { 0, 0, 0, 0 },
40692 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
40693 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992c00 }
40694 },
40695/* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
40696 {
40697 { 0, 0, 0, 0 },
40698 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
40699 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993c00 }
40700 },
40701/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40702 {
40703 { 0, 0, 0, 0 },
40704 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
40705 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918c00 }
40706 },
40707/* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
40708 {
40709 { 0, 0, 0, 0 },
40710 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
40711 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ac00 }
40712 },
40713/* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
40714 {
40715 { 0, 0, 0, 0 },
40716 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
40717 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bc00 }
40718 },
40719/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40720 {
40721 { 0, 0, 0, 0 },
40722 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
40723 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910c00 }
40724 },
40725/* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40726 {
40727 { 0, 0, 0, 0 },
40728 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
40729 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912c00 }
40730 },
40731/* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40732 {
40733 { 0, 0, 0, 0 },
40734 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
40735 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913c00 }
40736 },
40737/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40738 {
40739 { 0, 0, 0, 0 },
40740 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
40741 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930c00 }
40742 },
40743/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40744 {
40745 { 0, 0, 0, 0 },
40746 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
40747 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932c00 }
40748 },
40749/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40750 {
40751 { 0, 0, 0, 0 },
40752 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
40753 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933c00 }
40754 },
40755/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40756 {
40757 { 0, 0, 0, 0 },
40758 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
40759 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950c00 }
40760 },
40761/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40762 {
40763 { 0, 0, 0, 0 },
40764 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
40765 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952c00 }
40766 },
40767/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40768 {
40769 { 0, 0, 0, 0 },
40770 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
40771 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953c00 }
40772 },
40773/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40774 {
40775 { 0, 0, 0, 0 },
40776 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
40777 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970c00 }
40778 },
40779/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40780 {
40781 { 0, 0, 0, 0 },
40782 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
40783 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972c00 }
40784 },
40785/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40786 {
40787 { 0, 0, 0, 0 },
40788 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
40789 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973c00 }
40790 },
40791/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40792 {
40793 { 0, 0, 0, 0 },
40794 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40795 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938c00 }
40796 },
40797/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40798 {
40799 { 0, 0, 0, 0 },
40800 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40801 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ac00 }
40802 },
40803/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40804 {
40805 { 0, 0, 0, 0 },
40806 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40807 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bc00 }
40808 },
40809/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40810 {
40811 { 0, 0, 0, 0 },
40812 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40813 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958c00 }
40814 },
40815/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40816 {
40817 { 0, 0, 0, 0 },
40818 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40819 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ac00 }
40820 },
40821/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40822 {
40823 { 0, 0, 0, 0 },
40824 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40825 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bc00 }
40826 },
40827/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40828 {
40829 { 0, 0, 0, 0 },
40830 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40831 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cc00 }
40832 },
40833/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40834 {
40835 { 0, 0, 0, 0 },
40836 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40837 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ec00 }
40838 },
40839/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40840 {
40841 { 0, 0, 0, 0 },
40842 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40843 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fc00 }
40844 },
40845/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40846 {
40847 { 0, 0, 0, 0 },
40848 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
40849 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cc00 }
40850 },
40851/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40852 {
40853 { 0, 0, 0, 0 },
40854 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
40855 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ec00 }
40856 },
40857/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40858 {
40859 { 0, 0, 0, 0 },
40860 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
40861 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fc00 }
40862 },
40863/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40864 {
40865 { 0, 0, 0, 0 },
40866 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
40867 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cc00 }
40868 },
40869/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
40870 {
40871 { 0, 0, 0, 0 },
40872 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
40873 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ec00 }
40874 },
40875/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
40876 {
40877 { 0, 0, 0, 0 },
40878 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
40879 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fc00 }
40880 },
40881/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
40882 {
40883 { 0, 0, 0, 0 },
40884 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
40885 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978c00 }
40886 },
40887/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
40888 {
40889 { 0, 0, 0, 0 },
40890 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
40891 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ac00 }
40892 },
40893/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
40894 {
40895 { 0, 0, 0, 0 },
40896 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
40897 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bc00 }
40898 },
40899/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40900 {
40901 { 0, 0, 0, 0 },
40902 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
40903 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90c00 }
40904 },
40905/* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
40906 {
40907 { 0, 0, 0, 0 },
40908 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
40909 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92c00 }
40910 },
40911/* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
40912 {
40913 { 0, 0, 0, 0 },
40914 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
40915 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93c00 }
40916 },
40917/* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
40918 {
40919 { 0, 0, 0, 0 },
40920 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
40921 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93c00 }
40922 },
40923/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40924 {
40925 { 0, 0, 0, 0 },
40926 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
40927 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18c00 }
40928 },
40929/* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
40930 {
40931 { 0, 0, 0, 0 },
40932 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
40933 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ac00 }
40934 },
40935/* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
40936 {
40937 { 0, 0, 0, 0 },
40938 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
40939 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bc00 }
40940 },
40941/* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
40942 {
40943 { 0, 0, 0, 0 },
40944 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
40945 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bc00 }
40946 },
40947/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40948 {
40949 { 0, 0, 0, 0 },
40950 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
40951 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10c00 }
40952 },
40953/* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
40954 {
40955 { 0, 0, 0, 0 },
40956 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
40957 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12c00 }
40958 },
40959/* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
40960 {
40961 { 0, 0, 0, 0 },
40962 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
40963 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13c00 }
40964 },
40965/* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
40966 {
40967 { 0, 0, 0, 0 },
40968 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
40969 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13c00 }
40970 },
40971/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
40972 {
40973 { 0, 0, 0, 0 },
40974 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
40975 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30c00 }
40976 },
40977/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40978 {
40979 { 0, 0, 0, 0 },
40980 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
40981 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32c00 }
40982 },
40983/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40984 {
40985 { 0, 0, 0, 0 },
40986 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
40987 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33c00 }
40988 },
40989/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
40990 {
40991 { 0, 0, 0, 0 },
40992 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
40993 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33c00 }
40994 },
40995/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
40996 {
40997 { 0, 0, 0, 0 },
40998 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
40999 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50c00 }
41000 },
41001/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41002 {
41003 { 0, 0, 0, 0 },
41004 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41005 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52c00 }
41006 },
41007/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41008 {
41009 { 0, 0, 0, 0 },
41010 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41011 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53c00 }
41012 },
41013/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41014 {
41015 { 0, 0, 0, 0 },
41016 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41017 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53c00 }
41018 },
41019/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41020 {
41021 { 0, 0, 0, 0 },
41022 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41023 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70c00 }
41024 },
41025/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41026 {
41027 { 0, 0, 0, 0 },
41028 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41029 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72c00 }
41030 },
41031/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41032 {
41033 { 0, 0, 0, 0 },
41034 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41035 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73c00 }
41036 },
41037/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41038 {
41039 { 0, 0, 0, 0 },
41040 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41041 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73c00 }
41042 },
41043/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41044 {
41045 { 0, 0, 0, 0 },
41046 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41047 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38c00 }
41048 },
41049/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41050 {
41051 { 0, 0, 0, 0 },
41052 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41053 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ac00 }
41054 },
41055/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41056 {
41057 { 0, 0, 0, 0 },
41058 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41059 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bc00 }
41060 },
41061/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41062 {
41063 { 0, 0, 0, 0 },
41064 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41065 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bc00 }
41066 },
41067/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41068 {
41069 { 0, 0, 0, 0 },
41070 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41071 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58c00 }
41072 },
41073/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41074 {
41075 { 0, 0, 0, 0 },
41076 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41077 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ac00 }
41078 },
41079/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41080 {
41081 { 0, 0, 0, 0 },
41082 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41083 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bc00 }
41084 },
41085/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41086 {
41087 { 0, 0, 0, 0 },
41088 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41089 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bc00 }
41090 },
41091/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41092 {
41093 { 0, 0, 0, 0 },
41094 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41095 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cc00 }
41096 },
41097/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41098 {
41099 { 0, 0, 0, 0 },
41100 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41101 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ec00 }
41102 },
41103/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41104 {
41105 { 0, 0, 0, 0 },
41106 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41107 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fc00 }
41108 },
41109/* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41110 {
41111 { 0, 0, 0, 0 },
41112 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41113 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fc00 }
41114 },
41115/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41116 {
41117 { 0, 0, 0, 0 },
41118 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41119 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cc00 }
41120 },
41121/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41122 {
41123 { 0, 0, 0, 0 },
41124 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41125 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ec00 }
41126 },
41127/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41128 {
41129 { 0, 0, 0, 0 },
41130 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41131 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fc00 }
41132 },
41133/* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41134 {
41135 { 0, 0, 0, 0 },
41136 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41137 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fc00 }
41138 },
41139/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41140 {
41141 { 0, 0, 0, 0 },
41142 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
41143 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cc00 }
41144 },
41145/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41146 {
41147 { 0, 0, 0, 0 },
41148 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
41149 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ec00 }
41150 },
41151/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41152 {
41153 { 0, 0, 0, 0 },
41154 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
41155 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fc00 }
41156 },
41157/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
41158 {
41159 { 0, 0, 0, 0 },
41160 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
41161 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fc00 }
41162 },
41163/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41164 {
41165 { 0, 0, 0, 0 },
41166 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
41167 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78c00 }
41168 },
41169/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41170 {
41171 { 0, 0, 0, 0 },
41172 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
41173 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ac00 }
41174 },
41175/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41176 {
41177 { 0, 0, 0, 0 },
41178 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
41179 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bc00 }
41180 },
41181/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
41182 {
41183 { 0, 0, 0, 0 },
41184 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
41185 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bc00 }
41186 },
41187/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41188 {
41189 { 0, 0, 0, 0 },
41190 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41191 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90c00 }
41192 },
41193/* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
41194 {
41195 { 0, 0, 0, 0 },
41196 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
41197 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92c00 }
41198 },
41199/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41200 {
41201 { 0, 0, 0, 0 },
41202 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41203 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18c00 }
41204 },
41205/* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
41206 {
41207 { 0, 0, 0, 0 },
41208 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
41209 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ac00 }
41210 },
41211/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41212 {
41213 { 0, 0, 0, 0 },
41214 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41215 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10c00 }
41216 },
41217/* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41218 {
41219 { 0, 0, 0, 0 },
41220 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41221 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12c00 }
41222 },
41223/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41224 {
41225 { 0, 0, 0, 0 },
41226 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41227 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30c00 }
41228 },
41229/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41230 {
41231 { 0, 0, 0, 0 },
41232 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41233 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32c00 }
41234 },
41235/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41236 {
41237 { 0, 0, 0, 0 },
41238 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41239 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50c00 }
41240 },
41241/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41242 {
41243 { 0, 0, 0, 0 },
41244 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41245 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52c00 }
41246 },
41247/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41248 {
41249 { 0, 0, 0, 0 },
41250 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41251 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70c00 }
41252 },
41253/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41254 {
41255 { 0, 0, 0, 0 },
41256 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41257 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72c00 }
41258 },
41259/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41260 {
41261 { 0, 0, 0, 0 },
41262 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
41263 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38c00 }
41264 },
41265/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41266 {
41267 { 0, 0, 0, 0 },
41268 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
41269 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ac00 }
41270 },
41271/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41272 {
41273 { 0, 0, 0, 0 },
41274 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
41275 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58c00 }
41276 },
41277/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41278 {
41279 { 0, 0, 0, 0 },
41280 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
41281 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ac00 }
41282 },
41283/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41284 {
41285 { 0, 0, 0, 0 },
41286 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
41287 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cc00 }
41288 },
41289/* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41290 {
41291 { 0, 0, 0, 0 },
41292 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
41293 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ec00 }
41294 },
41295/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41296 {
41297 { 0, 0, 0, 0 },
41298 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
41299 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cc00 }
41300 },
41301/* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41302 {
41303 { 0, 0, 0, 0 },
41304 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
41305 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ec00 }
41306 },
41307/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41308 {
41309 { 0, 0, 0, 0 },
41310 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
41311 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cc00 }
41312 },
41313/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
41314 {
41315 { 0, 0, 0, 0 },
41316 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
41317 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ec00 }
41318 },
41319/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41320 {
41321 { 0, 0, 0, 0 },
41322 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
41323 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78c00 }
41324 },
41325/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
41326 {
41327 { 0, 0, 0, 0 },
41328 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
41329 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ac00 }
41330 },
41331/* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
41332 {
41333 { 0, 0, 0, 0 },
41334 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
41335 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90c }
41336 },
41337/* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41338 {
41339 { 0, 0, 0, 0 },
41340 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
41341 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892c }
41342 },
41343/* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41344 {
41345 { 0, 0, 0, 0 },
41346 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41347 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890c }
41348 },
41349/* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41350 {
41351 { 0, 0, 0, 0 },
41352 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
41353 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18c }
41354 },
41355/* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41356 {
41357 { 0, 0, 0, 0 },
41358 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
41359 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ac }
41360 },
41361/* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41362 {
41363 { 0, 0, 0, 0 },
41364 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41365 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818c }
41366 },
41367/* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41368 {
41369 { 0, 0, 0, 0 },
41370 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41371 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10c }
41372 },
41373/* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41374 {
41375 { 0, 0, 0, 0 },
41376 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41377 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812c }
41378 },
41379/* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41380 {
41381 { 0, 0, 0, 0 },
41382 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41383 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810c }
41384 },
41385/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41386 {
41387 { 0, 0, 0, 0 },
41388 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41389 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30c00 }
41390 },
41391/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41392 {
41393 { 0, 0, 0, 0 },
41394 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41395 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832c00 }
41396 },
41397/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41398 {
41399 { 0, 0, 0, 0 },
41400 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41401 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830c00 }
41402 },
41403/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41404 {
41405 { 0, 0, 0, 0 },
41406 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41407 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50c00 }
41408 },
41409/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41410 {
41411 { 0, 0, 0, 0 },
41412 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41413 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852c00 }
41414 },
41415/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41416 {
41417 { 0, 0, 0, 0 },
41418 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41419 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850c00 }
41420 },
41421/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41422 {
41423 { 0, 0, 0, 0 },
41424 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41425 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70c00 }
41426 },
41427/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41428 {
41429 { 0, 0, 0, 0 },
41430 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41431 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872c00 }
41432 },
41433/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41434 {
41435 { 0, 0, 0, 0 },
41436 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41437 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870c00 }
41438 },
41439/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41440 {
41441 { 0, 0, 0, 0 },
41442 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41443 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38c00 }
41444 },
41445/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41446 {
41447 { 0, 0, 0, 0 },
41448 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41449 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ac00 }
41450 },
41451/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41452 {
41453 { 0, 0, 0, 0 },
41454 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41455 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838c00 }
41456 },
41457/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41458 {
41459 { 0, 0, 0, 0 },
41460 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41461 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58c00 }
41462 },
41463/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41464 {
41465 { 0, 0, 0, 0 },
41466 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41467 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ac00 }
41468 },
41469/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41470 {
41471 { 0, 0, 0, 0 },
41472 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41473 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858c00 }
41474 },
41475/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41476 {
41477 { 0, 0, 0, 0 },
41478 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41479 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cc00 }
41480 },
41481/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41482 {
41483 { 0, 0, 0, 0 },
41484 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41485 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ec00 }
41486 },
41487/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41488 {
41489 { 0, 0, 0, 0 },
41490 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41491 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cc00 }
41492 },
41493/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41494 {
41495 { 0, 0, 0, 0 },
41496 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41497 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cc00 }
41498 },
41499/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41500 {
41501 { 0, 0, 0, 0 },
41502 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41503 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ec00 }
41504 },
41505/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41506 {
41507 { 0, 0, 0, 0 },
41508 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41509 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cc00 }
41510 },
41511/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41512 {
41513 { 0, 0, 0, 0 },
41514 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
41515 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cc00 }
41516 },
41517/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41518 {
41519 { 0, 0, 0, 0 },
41520 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
41521 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ec00 }
41522 },
41523/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41524 {
41525 { 0, 0, 0, 0 },
41526 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
41527 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cc00 }
41528 },
41529/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41530 {
41531 { 0, 0, 0, 0 },
41532 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
41533 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78c00 }
41534 },
41535/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41536 {
41537 { 0, 0, 0, 0 },
41538 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
41539 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ac00 }
41540 },
41541/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41542 {
41543 { 0, 0, 0, 0 },
41544 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
41545 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878c00 }
41546 },
41547/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41548 {
41549 { 0, 0, 0, 0 },
41550 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41551 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980c00 }
41552 },
41553/* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41554 {
41555 { 0, 0, 0, 0 },
41556 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41557 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982c00 }
41558 },
41559/* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41560 {
41561 { 0, 0, 0, 0 },
41562 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41563 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983c00 }
41564 },
41565/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41566 {
41567 { 0, 0, 0, 0 },
41568 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41569 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908c00 }
41570 },
41571/* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41572 {
41573 { 0, 0, 0, 0 },
41574 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41575 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ac00 }
41576 },
41577/* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41578 {
41579 { 0, 0, 0, 0 },
41580 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41581 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bc00 }
41582 },
41583/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41584 {
41585 { 0, 0, 0, 0 },
41586 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41587 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900c00 }
41588 },
41589/* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41590 {
41591 { 0, 0, 0, 0 },
41592 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41593 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902c00 }
41594 },
41595/* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41596 {
41597 { 0, 0, 0, 0 },
41598 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41599 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903c00 }
41600 },
41601/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41602 {
41603 { 0, 0, 0, 0 },
41604 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41605 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920c00 }
41606 },
41607/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41608 {
41609 { 0, 0, 0, 0 },
41610 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41611 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922c00 }
41612 },
41613/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41614 {
41615 { 0, 0, 0, 0 },
41616 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41617 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923c00 }
41618 },
41619/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41620 {
41621 { 0, 0, 0, 0 },
41622 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41623 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940c00 }
41624 },
41625/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41626 {
41627 { 0, 0, 0, 0 },
41628 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41629 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942c00 }
41630 },
41631/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41632 {
41633 { 0, 0, 0, 0 },
41634 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41635 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943c00 }
41636 },
41637/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41638 {
41639 { 0, 0, 0, 0 },
41640 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41641 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960c00 }
41642 },
41643/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41644 {
41645 { 0, 0, 0, 0 },
41646 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41647 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962c00 }
41648 },
41649/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41650 {
41651 { 0, 0, 0, 0 },
41652 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41653 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963c00 }
41654 },
41655/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41656 {
41657 { 0, 0, 0, 0 },
41658 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41659 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928c00 }
41660 },
41661/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41662 {
41663 { 0, 0, 0, 0 },
41664 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41665 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ac00 }
41666 },
41667/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41668 {
41669 { 0, 0, 0, 0 },
41670 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41671 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bc00 }
41672 },
41673/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41674 {
41675 { 0, 0, 0, 0 },
41676 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41677 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948c00 }
41678 },
41679/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41680 {
41681 { 0, 0, 0, 0 },
41682 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41683 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ac00 }
41684 },
41685/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41686 {
41687 { 0, 0, 0, 0 },
41688 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41689 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bc00 }
41690 },
41691/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41692 {
41693 { 0, 0, 0, 0 },
41694 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41695 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cc00 }
41696 },
41697/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41698 {
41699 { 0, 0, 0, 0 },
41700 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41701 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ec00 }
41702 },
41703/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41704 {
41705 { 0, 0, 0, 0 },
41706 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41707 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fc00 }
41708 },
41709/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41710 {
41711 { 0, 0, 0, 0 },
41712 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41713 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cc00 }
41714 },
41715/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41716 {
41717 { 0, 0, 0, 0 },
41718 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41719 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ec00 }
41720 },
41721/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41722 {
41723 { 0, 0, 0, 0 },
41724 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41725 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fc00 }
41726 },
41727/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41728 {
41729 { 0, 0, 0, 0 },
41730 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
41731 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cc00 }
41732 },
41733/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41734 {
41735 { 0, 0, 0, 0 },
41736 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
41737 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ec00 }
41738 },
41739/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41740 {
41741 { 0, 0, 0, 0 },
41742 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
41743 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fc00 }
41744 },
41745/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41746 {
41747 { 0, 0, 0, 0 },
41748 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
41749 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968c00 }
41750 },
41751/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41752 {
41753 { 0, 0, 0, 0 },
41754 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
41755 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ac00 }
41756 },
41757/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41758 {
41759 { 0, 0, 0, 0 },
41760 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
41761 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bc00 }
41762 },
41763/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41764 {
41765 { 0, 0, 0, 0 },
41766 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41767 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80c00 }
41768 },
41769/* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
41770 {
41771 { 0, 0, 0, 0 },
41772 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41773 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82c00 }
41774 },
41775/* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
41776 {
41777 { 0, 0, 0, 0 },
41778 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41779 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83c00 }
41780 },
41781/* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
41782 {
41783 { 0, 0, 0, 0 },
41784 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
41785 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83c00 }
41786 },
41787/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41788 {
41789 { 0, 0, 0, 0 },
41790 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41791 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08c00 }
41792 },
41793/* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
41794 {
41795 { 0, 0, 0, 0 },
41796 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41797 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ac00 }
41798 },
41799/* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
41800 {
41801 { 0, 0, 0, 0 },
41802 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41803 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bc00 }
41804 },
41805/* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
41806 {
41807 { 0, 0, 0, 0 },
41808 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
41809 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bc00 }
41810 },
41811/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41812 {
41813 { 0, 0, 0, 0 },
41814 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41815 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00c00 }
41816 },
41817/* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41818 {
41819 { 0, 0, 0, 0 },
41820 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41821 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02c00 }
41822 },
41823/* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41824 {
41825 { 0, 0, 0, 0 },
41826 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41827 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03c00 }
41828 },
41829/* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41830 {
41831 { 0, 0, 0, 0 },
41832 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41833 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03c00 }
41834 },
41835/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41836 {
41837 { 0, 0, 0, 0 },
41838 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41839 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20c00 }
41840 },
41841/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41842 {
41843 { 0, 0, 0, 0 },
41844 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41845 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22c00 }
41846 },
41847/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41848 {
41849 { 0, 0, 0, 0 },
41850 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41851 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23c00 }
41852 },
41853/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41854 {
41855 { 0, 0, 0, 0 },
41856 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41857 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23c00 }
41858 },
41859/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41860 {
41861 { 0, 0, 0, 0 },
41862 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41863 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40c00 }
41864 },
41865/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41866 {
41867 { 0, 0, 0, 0 },
41868 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41869 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42c00 }
41870 },
41871/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41872 {
41873 { 0, 0, 0, 0 },
41874 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41875 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43c00 }
41876 },
41877/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41878 {
41879 { 0, 0, 0, 0 },
41880 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41881 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43c00 }
41882 },
41883/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41884 {
41885 { 0, 0, 0, 0 },
41886 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41887 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60c00 }
41888 },
41889/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41890 {
41891 { 0, 0, 0, 0 },
41892 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41893 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62c00 }
41894 },
41895/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41896 {
41897 { 0, 0, 0, 0 },
41898 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41899 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63c00 }
41900 },
41901/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41902 {
41903 { 0, 0, 0, 0 },
41904 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41905 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63c00 }
41906 },
41907/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41908 {
41909 { 0, 0, 0, 0 },
41910 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41911 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28c00 }
41912 },
41913/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41914 {
41915 { 0, 0, 0, 0 },
41916 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41917 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ac00 }
41918 },
41919/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41920 {
41921 { 0, 0, 0, 0 },
41922 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41923 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bc00 }
41924 },
41925/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41926 {
41927 { 0, 0, 0, 0 },
41928 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41929 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bc00 }
41930 },
41931/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41932 {
41933 { 0, 0, 0, 0 },
41934 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41935 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48c00 }
41936 },
41937/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41938 {
41939 { 0, 0, 0, 0 },
41940 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41941 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ac00 }
41942 },
41943/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41944 {
41945 { 0, 0, 0, 0 },
41946 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41947 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bc00 }
41948 },
41949/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41950 {
41951 { 0, 0, 0, 0 },
41952 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41953 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bc00 }
41954 },
41955/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41956 {
41957 { 0, 0, 0, 0 },
41958 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41959 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cc00 }
41960 },
41961/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41962 {
41963 { 0, 0, 0, 0 },
41964 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41965 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ec00 }
41966 },
41967/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41968 {
41969 { 0, 0, 0, 0 },
41970 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41971 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fc00 }
41972 },
41973/* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41974 {
41975 { 0, 0, 0, 0 },
41976 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41977 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fc00 }
41978 },
41979/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41980 {
41981 { 0, 0, 0, 0 },
41982 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41983 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cc00 }
41984 },
41985/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41986 {
41987 { 0, 0, 0, 0 },
41988 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41989 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ec00 }
41990 },
41991/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41992 {
41993 { 0, 0, 0, 0 },
41994 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41995 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fc00 }
41996 },
41997/* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41998 {
41999 { 0, 0, 0, 0 },
42000 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42001 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fc00 }
42002 },
42003/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
42004 {
42005 { 0, 0, 0, 0 },
42006 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
42007 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cc00 }
42008 },
42009/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
42010 {
42011 { 0, 0, 0, 0 },
42012 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
42013 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ec00 }
42014 },
42015/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
42016 {
42017 { 0, 0, 0, 0 },
42018 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
42019 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fc00 }
42020 },
42021/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
42022 {
42023 { 0, 0, 0, 0 },
42024 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
42025 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fc00 }
42026 },
42027/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
42028 {
42029 { 0, 0, 0, 0 },
42030 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
42031 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68c00 }
42032 },
42033/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
42034 {
42035 { 0, 0, 0, 0 },
42036 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
42037 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ac00 }
42038 },
42039/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
42040 {
42041 { 0, 0, 0, 0 },
42042 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
42043 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bc00 }
42044 },
42045/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
42046 {
42047 { 0, 0, 0, 0 },
42048 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
42049 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bc00 }
42050 },
42051/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
42052 {
42053 { 0, 0, 0, 0 },
42054 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42055 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80c00 }
42056 },
42057/* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
42058 {
42059 { 0, 0, 0, 0 },
42060 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
42061 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82c00 }
42062 },
42063/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
42064 {
42065 { 0, 0, 0, 0 },
42066 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42067 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08c00 }
42068 },
42069/* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
42070 {
42071 { 0, 0, 0, 0 },
42072 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
42073 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ac00 }
42074 },
42075/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42076 {
42077 { 0, 0, 0, 0 },
42078 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42079 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00c00 }
42080 },
42081/* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
42082 {
42083 { 0, 0, 0, 0 },
42084 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42085 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02c00 }
42086 },
42087/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
42088 {
42089 { 0, 0, 0, 0 },
42090 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42091 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20c00 }
42092 },
42093/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
42094 {
42095 { 0, 0, 0, 0 },
42096 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42097 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22c00 }
42098 },
42099/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
42100 {
42101 { 0, 0, 0, 0 },
42102 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42103 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40c00 }
42104 },
42105/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
42106 {
42107 { 0, 0, 0, 0 },
42108 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42109 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42c00 }
42110 },
42111/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
42112 {
42113 { 0, 0, 0, 0 },
42114 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42115 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60c00 }
42116 },
42117/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
42118 {
42119 { 0, 0, 0, 0 },
42120 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42121 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62c00 }
42122 },
42123/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
42124 {
42125 { 0, 0, 0, 0 },
42126 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
42127 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28c00 }
42128 },
42129/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
42130 {
42131 { 0, 0, 0, 0 },
42132 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
42133 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ac00 }
42134 },
42135/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
42136 {
42137 { 0, 0, 0, 0 },
42138 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
42139 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48c00 }
42140 },
42141/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
42142 {
42143 { 0, 0, 0, 0 },
42144 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
42145 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ac00 }
42146 },
42147/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
42148 {
42149 { 0, 0, 0, 0 },
42150 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
42151 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cc00 }
42152 },
42153/* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
42154 {
42155 { 0, 0, 0, 0 },
42156 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
42157 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ec00 }
42158 },
42159/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
42160 {
42161 { 0, 0, 0, 0 },
42162 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
42163 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cc00 }
42164 },
42165/* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
42166 {
42167 { 0, 0, 0, 0 },
42168 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
42169 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ec00 }
42170 },
42171/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
42172 {
42173 { 0, 0, 0, 0 },
42174 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
42175 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cc00 }
42176 },
42177/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
42178 {
42179 { 0, 0, 0, 0 },
42180 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
42181 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ec00 }
42182 },
42183/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
42184 {
42185 { 0, 0, 0, 0 },
42186 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
42187 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68c00 }
42188 },
42189/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
42190 {
42191 { 0, 0, 0, 0 },
42192 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
42193 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ac00 }
42194 },
42195/* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
42196 {
42197 { 0, 0, 0, 0 },
42198 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42199 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80c }
42200 },
42201/* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
42202 {
42203 { 0, 0, 0, 0 },
42204 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42205 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882c }
42206 },
42207/* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
42208 {
42209 { 0, 0, 0, 0 },
42210 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42211 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880c }
42212 },
42213/* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
42214 {
42215 { 0, 0, 0, 0 },
42216 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42217 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08c }
42218 },
42219/* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
42220 {
42221 { 0, 0, 0, 0 },
42222 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42223 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ac }
42224 },
42225/* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
42226 {
42227 { 0, 0, 0, 0 },
42228 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42229 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808c }
42230 },
42231/* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
42232 {
42233 { 0, 0, 0, 0 },
42234 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42235 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00c }
42236 },
42237/* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
42238 {
42239 { 0, 0, 0, 0 },
42240 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42241 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802c }
42242 },
42243/* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
42244 {
42245 { 0, 0, 0, 0 },
42246 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42247 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800c }
42248 },
42249/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42250 {
42251 { 0, 0, 0, 0 },
42252 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42253 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20c00 }
42254 },
42255/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42256 {
42257 { 0, 0, 0, 0 },
42258 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42259 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822c00 }
42260 },
42261/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
42262 {
42263 { 0, 0, 0, 0 },
42264 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42265 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820c00 }
42266 },
42267/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42268 {
42269 { 0, 0, 0, 0 },
42270 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42271 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40c00 }
42272 },
42273/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42274 {
42275 { 0, 0, 0, 0 },
42276 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42277 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842c00 }
42278 },
42279/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
42280 {
42281 { 0, 0, 0, 0 },
42282 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42283 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840c00 }
42284 },
42285/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42286 {
42287 { 0, 0, 0, 0 },
42288 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42289 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60c00 }
42290 },
42291/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42292 {
42293 { 0, 0, 0, 0 },
42294 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42295 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862c00 }
42296 },
42297/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
42298 {
42299 { 0, 0, 0, 0 },
42300 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42301 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860c00 }
42302 },
42303/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
42304 {
42305 { 0, 0, 0, 0 },
42306 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42307 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28c00 }
42308 },
42309/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
42310 {
42311 { 0, 0, 0, 0 },
42312 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42313 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ac00 }
42314 },
42315/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
42316 {
42317 { 0, 0, 0, 0 },
42318 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42319 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828c00 }
42320 },
42321/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
42322 {
42323 { 0, 0, 0, 0 },
42324 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42325 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48c00 }
42326 },
42327/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
42328 {
42329 { 0, 0, 0, 0 },
42330 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42331 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ac00 }
42332 },
42333/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
42334 {
42335 { 0, 0, 0, 0 },
42336 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42337 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848c00 }
42338 },
42339/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
42340 {
42341 { 0, 0, 0, 0 },
42342 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42343 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cc00 }
42344 },
42345/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
42346 {
42347 { 0, 0, 0, 0 },
42348 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42349 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ec00 }
42350 },
42351/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
42352 {
42353 { 0, 0, 0, 0 },
42354 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42355 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cc00 }
42356 },
42357/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
42358 {
42359 { 0, 0, 0, 0 },
42360 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42361 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cc00 }
42362 },
42363/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
42364 {
42365 { 0, 0, 0, 0 },
42366 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42367 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ec00 }
42368 },
42369/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
42370 {
42371 { 0, 0, 0, 0 },
42372 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42373 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cc00 }
42374 },
42375/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
42376 {
42377 { 0, 0, 0, 0 },
42378 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
42379 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cc00 }
42380 },
42381/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
42382 {
42383 { 0, 0, 0, 0 },
42384 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
42385 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ec00 }
42386 },
42387/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
42388 {
42389 { 0, 0, 0, 0 },
42390 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
42391 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cc00 }
42392 },
42393/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
42394 {
42395 { 0, 0, 0, 0 },
42396 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
42397 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68c00 }
42398 },
42399/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
42400 {
42401 { 0, 0, 0, 0 },
42402 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
42403 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ac00 }
42404 },
42405/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
42406 {
42407 { 0, 0, 0, 0 },
42408 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
42409 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868c00 }
42410 },
42411/* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
42412 {
42413 { 0, 0, 0, 0 },
42414 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
42415 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892f00 }
42416 },
42417/* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
42418 {
42419 { 0, 0, 0, 0 },
42420 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
42421 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181af00 }
42422 },
42423/* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
42424 {
42425 { 0, 0, 0, 0 },
42426 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42427 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812f00 }
42428 },
42429/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42430 {
42431 { 0, 0, 0, 0 },
42432 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42433 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832f00 }
42434 },
42435/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
42436 {
42437 { 0, 0, 0, 0 },
42438 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42439 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183af00 }
42440 },
42441/* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
42442 {
42443 { 0, 0, 0, 0 },
42444 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42445 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ef00 }
42446 },
42447/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42448 {
42449 { 0, 0, 0, 0 },
42450 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42451 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852f00 }
42452 },
42453/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
42454 {
42455 { 0, 0, 0, 0 },
42456 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42457 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185af00 }
42458 },
42459/* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
42460 {
42461 { 0, 0, 0, 0 },
42462 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42463 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ef00 }
42464 },
42465/* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
42466 {
42467 { 0, 0, 0, 0 },
42468 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
42469 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ef00 }
42470 },
42471/* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42472 {
42473 { 0, 0, 0, 0 },
42474 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42475 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872f00 }
42476 },
42477/* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
42478 {
42479 { 0, 0, 0, 0 },
42480 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
42481 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187af00 }
42482 },
42483/* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
42484 {
42485 { 0, 0, 0, 0 },
42486 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42487 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882f00 }
42488 },
42489/* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
42490 {
42491 { 0, 0, 0, 0 },
42492 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42493 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180af00 }
42494 },
42495/* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
42496 {
42497 { 0, 0, 0, 0 },
42498 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42499 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802f00 }
42500 },
42501/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42502 {
42503 { 0, 0, 0, 0 },
42504 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42505 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822f00 }
42506 },
42507/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
42508 {
42509 { 0, 0, 0, 0 },
42510 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42511 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182af00 }
42512 },
42513/* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
42514 {
42515 { 0, 0, 0, 0 },
42516 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42517 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ef00 }
42518 },
42519/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42520 {
42521 { 0, 0, 0, 0 },
42522 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42523 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842f00 }
42524 },
42525/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
42526 {
42527 { 0, 0, 0, 0 },
42528 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42529 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184af00 }
42530 },
42531/* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
42532 {
42533 { 0, 0, 0, 0 },
42534 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42535 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ef00 }
42536 },
42537/* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42538 {
42539 { 0, 0, 0, 0 },
42540 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
42541 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ef00 }
42542 },
42543/* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42544 {
42545 { 0, 0, 0, 0 },
42546 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42547 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862f00 }
42548 },
42549/* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42550 {
42551 { 0, 0, 0, 0 },
42552 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
42553 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186af00 }
42554 },
42555/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
42556 {
42557 { 0, 0, 0, 0 },
42558 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42559 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990d00 }
42560 },
42561/* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
42562 {
42563 { 0, 0, 0, 0 },
42564 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42565 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992d00 }
42566 },
42567/* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
42568 {
42569 { 0, 0, 0, 0 },
42570 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42571 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993d00 }
42572 },
42573/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
42574 {
42575 { 0, 0, 0, 0 },
42576 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42577 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918d00 }
42578 },
42579/* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
42580 {
42581 { 0, 0, 0, 0 },
42582 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42583 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ad00 }
42584 },
42585/* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
42586 {
42587 { 0, 0, 0, 0 },
42588 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42589 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bd00 }
42590 },
42591/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42592 {
42593 { 0, 0, 0, 0 },
42594 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42595 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910d00 }
42596 },
42597/* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
42598 {
42599 { 0, 0, 0, 0 },
42600 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42601 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912d00 }
42602 },
42603/* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
42604 {
42605 { 0, 0, 0, 0 },
42606 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42607 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913d00 }
42608 },
42609/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
42610 {
42611 { 0, 0, 0, 0 },
42612 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42613 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930d00 }
42614 },
42615/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
42616 {
42617 { 0, 0, 0, 0 },
42618 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42619 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932d00 }
42620 },
42621/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
42622 {
42623 { 0, 0, 0, 0 },
42624 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42625 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933d00 }
42626 },
42627/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
42628 {
42629 { 0, 0, 0, 0 },
42630 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42631 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950d00 }
42632 },
42633/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
42634 {
42635 { 0, 0, 0, 0 },
42636 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42637 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952d00 }
42638 },
42639/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
42640 {
42641 { 0, 0, 0, 0 },
42642 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42643 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953d00 }
42644 },
42645/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
42646 {
42647 { 0, 0, 0, 0 },
42648 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42649 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970d00 }
42650 },
42651/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
42652 {
42653 { 0, 0, 0, 0 },
42654 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42655 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972d00 }
42656 },
42657/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
42658 {
42659 { 0, 0, 0, 0 },
42660 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42661 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973d00 }
42662 },
42663/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
42664 {
42665 { 0, 0, 0, 0 },
42666 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42667 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938d00 }
42668 },
42669/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
42670 {
42671 { 0, 0, 0, 0 },
42672 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42673 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ad00 }
42674 },
42675/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
42676 {
42677 { 0, 0, 0, 0 },
42678 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42679 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bd00 }
42680 },
42681/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
42682 {
42683 { 0, 0, 0, 0 },
42684 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42685 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958d00 }
42686 },
42687/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
42688 {
42689 { 0, 0, 0, 0 },
42690 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42691 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ad00 }
42692 },
42693/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
42694 {
42695 { 0, 0, 0, 0 },
42696 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42697 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bd00 }
42698 },
42699/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
42700 {
42701 { 0, 0, 0, 0 },
42702 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42703 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cd00 }
42704 },
42705/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
42706 {
42707 { 0, 0, 0, 0 },
42708 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42709 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ed00 }
42710 },
42711/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
42712 {
42713 { 0, 0, 0, 0 },
42714 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42715 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fd00 }
42716 },
42717/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
42718 {
42719 { 0, 0, 0, 0 },
42720 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42721 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cd00 }
42722 },
42723/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
42724 {
42725 { 0, 0, 0, 0 },
42726 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42727 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ed00 }
42728 },
42729/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
42730 {
42731 { 0, 0, 0, 0 },
42732 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42733 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fd00 }
42734 },
42735/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
42736 {
42737 { 0, 0, 0, 0 },
42738 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
42739 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cd00 }
42740 },
42741/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
42742 {
42743 { 0, 0, 0, 0 },
42744 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
42745 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ed00 }
42746 },
42747/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
42748 {
42749 { 0, 0, 0, 0 },
42750 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
42751 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fd00 }
42752 },
42753/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
42754 {
42755 { 0, 0, 0, 0 },
42756 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
42757 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978d00 }
42758 },
42759/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
42760 {
42761 { 0, 0, 0, 0 },
42762 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
42763 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ad00 }
42764 },
42765/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
42766 {
42767 { 0, 0, 0, 0 },
42768 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
42769 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bd00 }
42770 },
42771/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
42772 {
42773 { 0, 0, 0, 0 },
42774 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42775 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90d00 }
42776 },
42777/* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
42778 {
42779 { 0, 0, 0, 0 },
42780 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42781 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92d00 }
42782 },
42783/* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
42784 {
42785 { 0, 0, 0, 0 },
42786 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42787 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93d00 }
42788 },
42789/* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
42790 {
42791 { 0, 0, 0, 0 },
42792 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
42793 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93d00 }
42794 },
42795/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
42796 {
42797 { 0, 0, 0, 0 },
42798 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42799 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18d00 }
42800 },
42801/* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
42802 {
42803 { 0, 0, 0, 0 },
42804 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42805 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ad00 }
42806 },
42807/* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
42808 {
42809 { 0, 0, 0, 0 },
42810 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42811 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bd00 }
42812 },
42813/* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
42814 {
42815 { 0, 0, 0, 0 },
42816 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
42817 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bd00 }
42818 },
42819/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42820 {
42821 { 0, 0, 0, 0 },
42822 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42823 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10d00 }
42824 },
42825/* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
42826 {
42827 { 0, 0, 0, 0 },
42828 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42829 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12d00 }
42830 },
42831/* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
42832 {
42833 { 0, 0, 0, 0 },
42834 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42835 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13d00 }
42836 },
42837/* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
42838 {
42839 { 0, 0, 0, 0 },
42840 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42841 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13d00 }
42842 },
42843/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
42844 {
42845 { 0, 0, 0, 0 },
42846 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42847 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30d00 }
42848 },
42849/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
42850 {
42851 { 0, 0, 0, 0 },
42852 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42853 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32d00 }
42854 },
42855/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
42856 {
42857 { 0, 0, 0, 0 },
42858 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42859 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33d00 }
42860 },
42861/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
42862 {
42863 { 0, 0, 0, 0 },
42864 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42865 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33d00 }
42866 },
42867/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
42868 {
42869 { 0, 0, 0, 0 },
42870 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42871 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50d00 }
42872 },
42873/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
42874 {
42875 { 0, 0, 0, 0 },
42876 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42877 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52d00 }
42878 },
42879/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
42880 {
42881 { 0, 0, 0, 0 },
42882 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42883 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53d00 }
42884 },
42885/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
42886 {
42887 { 0, 0, 0, 0 },
42888 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42889 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53d00 }
42890 },
42891/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
42892 {
42893 { 0, 0, 0, 0 },
42894 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42895 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70d00 }
42896 },
42897/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
42898 {
42899 { 0, 0, 0, 0 },
42900 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42901 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72d00 }
42902 },
42903/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
42904 {
42905 { 0, 0, 0, 0 },
42906 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42907 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73d00 }
42908 },
42909/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
42910 {
42911 { 0, 0, 0, 0 },
42912 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42913 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73d00 }
42914 },
42915/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
42916 {
42917 { 0, 0, 0, 0 },
42918 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42919 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38d00 }
42920 },
42921/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
42922 {
42923 { 0, 0, 0, 0 },
42924 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42925 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ad00 }
42926 },
42927/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
42928 {
42929 { 0, 0, 0, 0 },
42930 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42931 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bd00 }
42932 },
42933/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
42934 {
42935 { 0, 0, 0, 0 },
42936 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42937 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bd00 }
42938 },
42939/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
42940 {
42941 { 0, 0, 0, 0 },
42942 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42943 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58d00 }
42944 },
42945/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
42946 {
42947 { 0, 0, 0, 0 },
42948 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42949 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ad00 }
42950 },
42951/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
42952 {
42953 { 0, 0, 0, 0 },
42954 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42955 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bd00 }
42956 },
42957/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
42958 {
42959 { 0, 0, 0, 0 },
42960 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42961 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bd00 }
42962 },
42963/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
42964 {
42965 { 0, 0, 0, 0 },
42966 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42967 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cd00 }
42968 },
42969/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
42970 {
42971 { 0, 0, 0, 0 },
42972 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42973 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ed00 }
42974 },
42975/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
42976 {
42977 { 0, 0, 0, 0 },
42978 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42979 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fd00 }
42980 },
42981/* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
42982 {
42983 { 0, 0, 0, 0 },
42984 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42985 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fd00 }
42986 },
42987/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
42988 {
42989 { 0, 0, 0, 0 },
42990 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42991 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cd00 }
42992 },
42993/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
42994 {
42995 { 0, 0, 0, 0 },
42996 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42997 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ed00 }
42998 },
42999/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
43000 {
43001 { 0, 0, 0, 0 },
43002 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43003 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fd00 }
43004 },
43005/* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
43006 {
43007 { 0, 0, 0, 0 },
43008 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43009 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fd00 }
43010 },
43011/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
43012 {
43013 { 0, 0, 0, 0 },
43014 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
43015 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cd00 }
43016 },
43017/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
43018 {
43019 { 0, 0, 0, 0 },
43020 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43021 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ed00 }
43022 },
43023/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
43024 {
43025 { 0, 0, 0, 0 },
43026 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43027 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fd00 }
43028 },
43029/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
43030 {
43031 { 0, 0, 0, 0 },
43032 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
43033 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fd00 }
43034 },
43035/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
43036 {
43037 { 0, 0, 0, 0 },
43038 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
43039 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78d00 }
43040 },
43041/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
43042 {
43043 { 0, 0, 0, 0 },
43044 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43045 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ad00 }
43046 },
43047/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
43048 {
43049 { 0, 0, 0, 0 },
43050 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43051 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bd00 }
43052 },
43053/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
43054 {
43055 { 0, 0, 0, 0 },
43056 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
43057 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bd00 }
43058 },
43059/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
43060 {
43061 { 0, 0, 0, 0 },
43062 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43063 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90d00 }
43064 },
43065/* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
43066 {
43067 { 0, 0, 0, 0 },
43068 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
43069 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92d00 }
43070 },
43071/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
43072 {
43073 { 0, 0, 0, 0 },
43074 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43075 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18d00 }
43076 },
43077/* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
43078 {
43079 { 0, 0, 0, 0 },
43080 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
43081 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ad00 }
43082 },
43083/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43084 {
43085 { 0, 0, 0, 0 },
43086 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43087 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10d00 }
43088 },
43089/* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
43090 {
43091 { 0, 0, 0, 0 },
43092 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43093 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12d00 }
43094 },
43095/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
43096 {
43097 { 0, 0, 0, 0 },
43098 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43099 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30d00 }
43100 },
43101/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
43102 {
43103 { 0, 0, 0, 0 },
43104 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43105 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32d00 }
43106 },
43107/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
43108 {
43109 { 0, 0, 0, 0 },
43110 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43111 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50d00 }
43112 },
43113/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
43114 {
43115 { 0, 0, 0, 0 },
43116 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43117 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52d00 }
43118 },
43119/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
43120 {
43121 { 0, 0, 0, 0 },
43122 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43123 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70d00 }
43124 },
43125/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
43126 {
43127 { 0, 0, 0, 0 },
43128 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43129 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72d00 }
43130 },
43131/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
43132 {
43133 { 0, 0, 0, 0 },
43134 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
43135 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38d00 }
43136 },
43137/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
43138 {
43139 { 0, 0, 0, 0 },
43140 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
43141 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ad00 }
43142 },
43143/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
43144 {
43145 { 0, 0, 0, 0 },
43146 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
43147 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58d00 }
43148 },
43149/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
43150 {
43151 { 0, 0, 0, 0 },
43152 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
43153 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ad00 }
43154 },
43155/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
43156 {
43157 { 0, 0, 0, 0 },
43158 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
43159 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cd00 }
43160 },
43161/* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
43162 {
43163 { 0, 0, 0, 0 },
43164 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
43165 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ed00 }
43166 },
43167/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
43168 {
43169 { 0, 0, 0, 0 },
43170 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
43171 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cd00 }
43172 },
43173/* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
43174 {
43175 { 0, 0, 0, 0 },
43176 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
43177 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ed00 }
43178 },
43179/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
43180 {
43181 { 0, 0, 0, 0 },
43182 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
43183 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cd00 }
43184 },
43185/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
43186 {
43187 { 0, 0, 0, 0 },
43188 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
43189 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ed00 }
43190 },
43191/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
43192 {
43193 { 0, 0, 0, 0 },
43194 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
43195 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78d00 }
43196 },
43197/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
43198 {
43199 { 0, 0, 0, 0 },
43200 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
43201 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ad00 }
43202 },
43203/* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
43204 {
43205 { 0, 0, 0, 0 },
43206 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
43207 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90d }
43208 },
43209/* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
43210 {
43211 { 0, 0, 0, 0 },
43212 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
43213 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892d }
43214 },
43215/* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
43216 {
43217 { 0, 0, 0, 0 },
43218 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43219 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890d }
43220 },
43221/* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
43222 {
43223 { 0, 0, 0, 0 },
43224 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
43225 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18d }
43226 },
43227/* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
43228 {
43229 { 0, 0, 0, 0 },
43230 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
43231 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ad }
43232 },
43233/* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
43234 {
43235 { 0, 0, 0, 0 },
43236 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43237 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818d }
43238 },
43239/* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
43240 {
43241 { 0, 0, 0, 0 },
43242 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43243 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10d }
43244 },
43245/* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
43246 {
43247 { 0, 0, 0, 0 },
43248 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43249 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812d }
43250 },
43251/* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
43252 {
43253 { 0, 0, 0, 0 },
43254 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43255 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810d }
43256 },
43257/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
43258 {
43259 { 0, 0, 0, 0 },
43260 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43261 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30d00 }
43262 },
43263/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
43264 {
43265 { 0, 0, 0, 0 },
43266 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43267 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832d00 }
43268 },
43269/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
43270 {
43271 { 0, 0, 0, 0 },
43272 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43273 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830d00 }
43274 },
43275/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
43276 {
43277 { 0, 0, 0, 0 },
43278 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43279 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50d00 }
43280 },
43281/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
43282 {
43283 { 0, 0, 0, 0 },
43284 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43285 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852d00 }
43286 },
43287/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
43288 {
43289 { 0, 0, 0, 0 },
43290 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43291 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850d00 }
43292 },
43293/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
43294 {
43295 { 0, 0, 0, 0 },
43296 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43297 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70d00 }
43298 },
43299/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
43300 {
43301 { 0, 0, 0, 0 },
43302 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43303 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872d00 }
43304 },
43305/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
43306 {
43307 { 0, 0, 0, 0 },
43308 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43309 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870d00 }
43310 },
43311/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
43312 {
43313 { 0, 0, 0, 0 },
43314 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43315 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38d00 }
43316 },
43317/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
43318 {
43319 { 0, 0, 0, 0 },
43320 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43321 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ad00 }
43322 },
43323/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
43324 {
43325 { 0, 0, 0, 0 },
43326 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43327 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838d00 }
43328 },
43329/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
43330 {
43331 { 0, 0, 0, 0 },
43332 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43333 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58d00 }
43334 },
43335/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
43336 {
43337 { 0, 0, 0, 0 },
43338 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43339 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ad00 }
43340 },
43341/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
43342 {
43343 { 0, 0, 0, 0 },
43344 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43345 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858d00 }
43346 },
43347/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
43348 {
43349 { 0, 0, 0, 0 },
43350 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43351 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cd00 }
43352 },
43353/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
43354 {
43355 { 0, 0, 0, 0 },
43356 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43357 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ed00 }
43358 },
43359/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
43360 {
43361 { 0, 0, 0, 0 },
43362 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43363 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cd00 }
43364 },
43365/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
43366 {
43367 { 0, 0, 0, 0 },
43368 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43369 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cd00 }
43370 },
43371/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
43372 {
43373 { 0, 0, 0, 0 },
43374 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43375 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ed00 }
43376 },
43377/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
43378 {
43379 { 0, 0, 0, 0 },
43380 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43381 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cd00 }
43382 },
43383/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
43384 {
43385 { 0, 0, 0, 0 },
43386 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
43387 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cd00 }
43388 },
43389/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
43390 {
43391 { 0, 0, 0, 0 },
43392 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
43393 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ed00 }
43394 },
43395/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
43396 {
43397 { 0, 0, 0, 0 },
43398 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
43399 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cd00 }
43400 },
43401/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
43402 {
43403 { 0, 0, 0, 0 },
43404 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
43405 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78d00 }
43406 },
43407/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
43408 {
43409 { 0, 0, 0, 0 },
43410 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
43411 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ad00 }
43412 },
43413/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
43414 {
43415 { 0, 0, 0, 0 },
43416 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
43417 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878d00 }
43418 },
43419/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
43420 {
43421 { 0, 0, 0, 0 },
43422 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43423 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980d00 }
43424 },
43425/* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
43426 {
43427 { 0, 0, 0, 0 },
43428 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43429 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982d00 }
43430 },
43431/* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
43432 {
43433 { 0, 0, 0, 0 },
43434 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43435 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983d00 }
43436 },
43437/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
43438 {
43439 { 0, 0, 0, 0 },
43440 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43441 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908d00 }
43442 },
43443/* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
43444 {
43445 { 0, 0, 0, 0 },
43446 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43447 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ad00 }
43448 },
43449/* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
43450 {
43451 { 0, 0, 0, 0 },
43452 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43453 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bd00 }
43454 },
43455/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43456 {
43457 { 0, 0, 0, 0 },
43458 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43459 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900d00 }
43460 },
43461/* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
43462 {
43463 { 0, 0, 0, 0 },
43464 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43465 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902d00 }
43466 },
43467/* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
43468 {
43469 { 0, 0, 0, 0 },
43470 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43471 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903d00 }
43472 },
43473/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
43474 {
43475 { 0, 0, 0, 0 },
43476 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43477 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920d00 }
43478 },
43479/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43480 {
43481 { 0, 0, 0, 0 },
43482 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43483 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922d00 }
43484 },
43485/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43486 {
43487 { 0, 0, 0, 0 },
43488 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43489 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923d00 }
43490 },
43491/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
43492 {
43493 { 0, 0, 0, 0 },
43494 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43495 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940d00 }
43496 },
43497/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43498 {
43499 { 0, 0, 0, 0 },
43500 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43501 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942d00 }
43502 },
43503/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43504 {
43505 { 0, 0, 0, 0 },
43506 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43507 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943d00 }
43508 },
43509/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
43510 {
43511 { 0, 0, 0, 0 },
43512 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43513 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960d00 }
43514 },
43515/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43516 {
43517 { 0, 0, 0, 0 },
43518 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43519 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962d00 }
43520 },
43521/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43522 {
43523 { 0, 0, 0, 0 },
43524 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43525 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963d00 }
43526 },
43527/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
43528 {
43529 { 0, 0, 0, 0 },
43530 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43531 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928d00 }
43532 },
43533/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
43534 {
43535 { 0, 0, 0, 0 },
43536 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43537 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ad00 }
43538 },
43539/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
43540 {
43541 { 0, 0, 0, 0 },
43542 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43543 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bd00 }
43544 },
43545/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
43546 {
43547 { 0, 0, 0, 0 },
43548 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43549 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948d00 }
43550 },
43551/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
43552 {
43553 { 0, 0, 0, 0 },
43554 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43555 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ad00 }
43556 },
43557/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
43558 {
43559 { 0, 0, 0, 0 },
43560 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43561 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bd00 }
43562 },
43563/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
43564 {
43565 { 0, 0, 0, 0 },
43566 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43567 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cd00 }
43568 },
43569/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
43570 {
43571 { 0, 0, 0, 0 },
43572 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43573 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ed00 }
43574 },
43575/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
43576 {
43577 { 0, 0, 0, 0 },
43578 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43579 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fd00 }
43580 },
43581/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
43582 {
43583 { 0, 0, 0, 0 },
43584 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43585 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cd00 }
43586 },
43587/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
43588 {
43589 { 0, 0, 0, 0 },
43590 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43591 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ed00 }
43592 },
43593/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
43594 {
43595 { 0, 0, 0, 0 },
43596 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43597 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fd00 }
43598 },
43599/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
43600 {
43601 { 0, 0, 0, 0 },
43602 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
43603 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cd00 }
43604 },
43605/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
43606 {
43607 { 0, 0, 0, 0 },
43608 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43609 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ed00 }
43610 },
43611/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
43612 {
43613 { 0, 0, 0, 0 },
43614 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43615 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fd00 }
43616 },
43617/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
43618 {
43619 { 0, 0, 0, 0 },
43620 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
43621 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968d00 }
43622 },
43623/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
43624 {
43625 { 0, 0, 0, 0 },
43626 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
43627 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ad00 }
43628 },
43629/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
43630 {
43631 { 0, 0, 0, 0 },
43632 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
43633 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bd00 }
43634 },
43635/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
43636 {
43637 { 0, 0, 0, 0 },
43638 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43639 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80d00 }
43640 },
43641/* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
43642 {
43643 { 0, 0, 0, 0 },
43644 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43645 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82d00 }
43646 },
43647/* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
43648 {
43649 { 0, 0, 0, 0 },
43650 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43651 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83d00 }
43652 },
43653/* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
43654 {
43655 { 0, 0, 0, 0 },
43656 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
43657 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83d00 }
43658 },
43659/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
43660 {
43661 { 0, 0, 0, 0 },
43662 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43663 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08d00 }
43664 },
43665/* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
43666 {
43667 { 0, 0, 0, 0 },
43668 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43669 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ad00 }
43670 },
43671/* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
43672 {
43673 { 0, 0, 0, 0 },
43674 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43675 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bd00 }
43676 },
43677/* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
43678 {
43679 { 0, 0, 0, 0 },
43680 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
43681 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bd00 }
43682 },
43683/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43684 {
43685 { 0, 0, 0, 0 },
43686 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43687 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00d00 }
43688 },
43689/* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
43690 {
43691 { 0, 0, 0, 0 },
43692 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43693 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02d00 }
43694 },
43695/* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
43696 {
43697 { 0, 0, 0, 0 },
43698 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43699 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03d00 }
43700 },
43701/* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
43702 {
43703 { 0, 0, 0, 0 },
43704 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43705 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03d00 }
43706 },
43707/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
43708 {
43709 { 0, 0, 0, 0 },
43710 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43711 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20d00 }
43712 },
43713/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
43714 {
43715 { 0, 0, 0, 0 },
43716 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43717 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22d00 }
43718 },
43719/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
43720 {
43721 { 0, 0, 0, 0 },
43722 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43723 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23d00 }
43724 },
43725/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
43726 {
43727 { 0, 0, 0, 0 },
43728 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43729 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23d00 }
43730 },
43731/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
43732 {
43733 { 0, 0, 0, 0 },
43734 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43735 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40d00 }
43736 },
43737/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
43738 {
43739 { 0, 0, 0, 0 },
43740 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43741 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42d00 }
43742 },
43743/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
43744 {
43745 { 0, 0, 0, 0 },
43746 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43747 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43d00 }
43748 },
43749/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
43750 {
43751 { 0, 0, 0, 0 },
43752 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43753 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43d00 }
43754 },
43755/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
43756 {
43757 { 0, 0, 0, 0 },
43758 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43759 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60d00 }
43760 },
43761/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
43762 {
43763 { 0, 0, 0, 0 },
43764 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43765 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62d00 }
43766 },
43767/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
43768 {
43769 { 0, 0, 0, 0 },
43770 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43771 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63d00 }
43772 },
43773/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
43774 {
43775 { 0, 0, 0, 0 },
43776 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43777 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63d00 }
43778 },
43779/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
43780 {
43781 { 0, 0, 0, 0 },
43782 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43783 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28d00 }
43784 },
43785/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
43786 {
43787 { 0, 0, 0, 0 },
43788 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43789 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ad00 }
43790 },
43791/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
43792 {
43793 { 0, 0, 0, 0 },
43794 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43795 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bd00 }
43796 },
43797/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
43798 {
43799 { 0, 0, 0, 0 },
43800 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43801 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bd00 }
43802 },
43803/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
43804 {
43805 { 0, 0, 0, 0 },
43806 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43807 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48d00 }
43808 },
43809/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
43810 {
43811 { 0, 0, 0, 0 },
43812 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43813 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ad00 }
43814 },
43815/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
43816 {
43817 { 0, 0, 0, 0 },
43818 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43819 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bd00 }
43820 },
43821/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
43822 {
43823 { 0, 0, 0, 0 },
43824 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43825 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bd00 }
43826 },
43827/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
43828 {
43829 { 0, 0, 0, 0 },
43830 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43831 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cd00 }
43832 },
43833/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
43834 {
43835 { 0, 0, 0, 0 },
43836 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43837 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ed00 }
43838 },
43839/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
43840 {
43841 { 0, 0, 0, 0 },
43842 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43843 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fd00 }
43844 },
43845/* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
43846 {
43847 { 0, 0, 0, 0 },
43848 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43849 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fd00 }
43850 },
43851/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
43852 {
43853 { 0, 0, 0, 0 },
43854 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43855 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cd00 }
43856 },
43857/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
43858 {
43859 { 0, 0, 0, 0 },
43860 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43861 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ed00 }
43862 },
43863/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
43864 {
43865 { 0, 0, 0, 0 },
43866 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43867 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fd00 }
43868 },
43869/* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
43870 {
43871 { 0, 0, 0, 0 },
43872 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43873 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fd00 }
43874 },
43875/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
43876 {
43877 { 0, 0, 0, 0 },
43878 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
43879 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cd00 }
43880 },
43881/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
43882 {
43883 { 0, 0, 0, 0 },
43884 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43885 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ed00 }
43886 },
43887/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
43888 {
43889 { 0, 0, 0, 0 },
43890 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43891 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fd00 }
43892 },
43893/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
43894 {
43895 { 0, 0, 0, 0 },
43896 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
43897 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fd00 }
43898 },
43899/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
43900 {
43901 { 0, 0, 0, 0 },
43902 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
43903 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68d00 }
43904 },
43905/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
43906 {
43907 { 0, 0, 0, 0 },
43908 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43909 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ad00 }
43910 },
43911/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
43912 {
43913 { 0, 0, 0, 0 },
43914 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43915 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bd00 }
43916 },
43917/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
43918 {
43919 { 0, 0, 0, 0 },
43920 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
43921 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bd00 }
43922 },
43923/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
43924 {
43925 { 0, 0, 0, 0 },
43926 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43927 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80d00 }
43928 },
43929/* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
43930 {
43931 { 0, 0, 0, 0 },
43932 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
43933 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82d00 }
43934 },
43935/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
43936 {
43937 { 0, 0, 0, 0 },
43938 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43939 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08d00 }
43940 },
43941/* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
43942 {
43943 { 0, 0, 0, 0 },
43944 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
43945 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ad00 }
43946 },
43947/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43948 {
43949 { 0, 0, 0, 0 },
43950 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43951 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00d00 }
43952 },
43953/* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
43954 {
43955 { 0, 0, 0, 0 },
43956 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43957 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02d00 }
43958 },
43959/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
43960 {
43961 { 0, 0, 0, 0 },
43962 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43963 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20d00 }
43964 },
43965/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
43966 {
43967 { 0, 0, 0, 0 },
43968 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43969 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22d00 }
43970 },
43971/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
43972 {
43973 { 0, 0, 0, 0 },
43974 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43975 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40d00 }
43976 },
43977/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
43978 {
43979 { 0, 0, 0, 0 },
43980 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43981 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42d00 }
43982 },
43983/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
43984 {
43985 { 0, 0, 0, 0 },
43986 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43987 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60d00 }
43988 },
43989/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
43990 {
43991 { 0, 0, 0, 0 },
43992 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43993 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62d00 }
43994 },
43995/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
43996 {
43997 { 0, 0, 0, 0 },
43998 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
43999 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28d00 }
44000 },
44001/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
44002 {
44003 { 0, 0, 0, 0 },
44004 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
44005 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ad00 }
44006 },
44007/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
44008 {
44009 { 0, 0, 0, 0 },
44010 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
44011 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48d00 }
44012 },
44013/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
44014 {
44015 { 0, 0, 0, 0 },
44016 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
44017 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ad00 }
44018 },
44019/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
44020 {
44021 { 0, 0, 0, 0 },
44022 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
44023 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cd00 }
44024 },
44025/* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
44026 {
44027 { 0, 0, 0, 0 },
44028 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
44029 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ed00 }
44030 },
44031/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
44032 {
44033 { 0, 0, 0, 0 },
44034 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
44035 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cd00 }
44036 },
44037/* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
44038 {
44039 { 0, 0, 0, 0 },
44040 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
44041 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ed00 }
44042 },
44043/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
44044 {
44045 { 0, 0, 0, 0 },
44046 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
44047 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cd00 }
44048 },
44049/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
44050 {
44051 { 0, 0, 0, 0 },
44052 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
44053 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ed00 }
44054 },
44055/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
44056 {
44057 { 0, 0, 0, 0 },
44058 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
44059 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68d00 }
44060 },
44061/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
44062 {
44063 { 0, 0, 0, 0 },
44064 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
44065 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ad00 }
44066 },
44067/* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
44068 {
44069 { 0, 0, 0, 0 },
44070 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44071 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80d }
44072 },
44073/* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
44074 {
44075 { 0, 0, 0, 0 },
44076 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44077 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882d }
44078 },
44079/* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
44080 {
44081 { 0, 0, 0, 0 },
44082 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44083 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880d }
44084 },
44085/* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
44086 {
44087 { 0, 0, 0, 0 },
44088 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44089 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08d }
44090 },
44091/* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
44092 {
44093 { 0, 0, 0, 0 },
44094 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44095 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ad }
44096 },
44097/* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
44098 {
44099 { 0, 0, 0, 0 },
44100 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44101 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808d }
44102 },
44103/* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
44104 {
44105 { 0, 0, 0, 0 },
44106 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44107 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00d }
44108 },
44109/* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
44110 {
44111 { 0, 0, 0, 0 },
44112 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44113 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802d }
44114 },
44115/* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
44116 {
44117 { 0, 0, 0, 0 },
44118 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44119 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800d }
44120 },
44121/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
44122 {
44123 { 0, 0, 0, 0 },
44124 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44125 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20d00 }
44126 },
44127/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
44128 {
44129 { 0, 0, 0, 0 },
44130 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44131 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822d00 }
44132 },
44133/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
44134 {
44135 { 0, 0, 0, 0 },
44136 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44137 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820d00 }
44138 },
44139/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
44140 {
44141 { 0, 0, 0, 0 },
44142 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44143 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40d00 }
44144 },
44145/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
44146 {
44147 { 0, 0, 0, 0 },
44148 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44149 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842d00 }
44150 },
44151/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
44152 {
44153 { 0, 0, 0, 0 },
44154 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44155 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840d00 }
44156 },
44157/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
44158 {
44159 { 0, 0, 0, 0 },
44160 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44161 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60d00 }
44162 },
44163/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
44164 {
44165 { 0, 0, 0, 0 },
44166 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44167 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862d00 }
44168 },
44169/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
44170 {
44171 { 0, 0, 0, 0 },
44172 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44173 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860d00 }
44174 },
44175/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
44176 {
44177 { 0, 0, 0, 0 },
44178 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44179 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28d00 }
44180 },
44181/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
44182 {
44183 { 0, 0, 0, 0 },
44184 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44185 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ad00 }
44186 },
44187/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
44188 {
44189 { 0, 0, 0, 0 },
44190 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44191 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828d00 }
44192 },
44193/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
44194 {
44195 { 0, 0, 0, 0 },
44196 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44197 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48d00 }
44198 },
44199/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
44200 {
44201 { 0, 0, 0, 0 },
44202 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44203 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ad00 }
44204 },
44205/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
44206 {
44207 { 0, 0, 0, 0 },
44208 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44209 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848d00 }
44210 },
44211/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
44212 {
44213 { 0, 0, 0, 0 },
44214 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44215 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cd00 }
44216 },
44217/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
44218 {
44219 { 0, 0, 0, 0 },
44220 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44221 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ed00 }
44222 },
44223/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
44224 {
44225 { 0, 0, 0, 0 },
44226 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44227 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cd00 }
44228 },
44229/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
44230 {
44231 { 0, 0, 0, 0 },
44232 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44233 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cd00 }
44234 },
44235/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
44236 {
44237 { 0, 0, 0, 0 },
44238 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44239 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ed00 }
44240 },
44241/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
44242 {
44243 { 0, 0, 0, 0 },
44244 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44245 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cd00 }
44246 },
44247/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
44248 {
44249 { 0, 0, 0, 0 },
44250 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
44251 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cd00 }
44252 },
44253/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
44254 {
44255 { 0, 0, 0, 0 },
44256 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
44257 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ed00 }
44258 },
44259/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
44260 {
44261 { 0, 0, 0, 0 },
44262 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
44263 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cd00 }
44264 },
44265/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
44266 {
44267 { 0, 0, 0, 0 },
44268 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
44269 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68d00 }
44270 },
44271/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
44272 {
44273 { 0, 0, 0, 0 },
44274 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
44275 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ad00 }
44276 },
44277/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
44278 {
44279 { 0, 0, 0, 0 },
44280 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
44281 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868d00 }
44282 },
44283/* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
44284 {
44285 { 0, 0, 0, 0 },
44286 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
44287 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893f00 }
44288 },
44289/* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
44290 {
44291 { 0, 0, 0, 0 },
44292 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
44293 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181bf00 }
44294 },
44295/* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
44296 {
44297 { 0, 0, 0, 0 },
44298 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44299 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813f00 }
44300 },
44301/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
44302 {
44303 { 0, 0, 0, 0 },
44304 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44305 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833f00 }
44306 },
44307/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
44308 {
44309 { 0, 0, 0, 0 },
44310 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44311 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183bf00 }
44312 },
44313/* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
44314 {
44315 { 0, 0, 0, 0 },
44316 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44317 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ff00 }
44318 },
44319/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
44320 {
44321 { 0, 0, 0, 0 },
44322 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44323 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853f00 }
44324 },
44325/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
44326 {
44327 { 0, 0, 0, 0 },
44328 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44329 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185bf00 }
44330 },
44331/* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
44332 {
44333 { 0, 0, 0, 0 },
44334 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44335 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ff00 }
44336 },
44337/* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
44338 {
44339 { 0, 0, 0, 0 },
44340 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
44341 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ff00 }
44342 },
44343/* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
44344 {
44345 { 0, 0, 0, 0 },
44346 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44347 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873f00 }
44348 },
44349/* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
44350 {
44351 { 0, 0, 0, 0 },
44352 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
44353 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187bf00 }
44354 },
44355/* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
44356 {
44357 { 0, 0, 0, 0 },
44358 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44359 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883f00 }
44360 },
44361/* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
44362 {
44363 { 0, 0, 0, 0 },
44364 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44365 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180bf00 }
44366 },
44367/* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
44368 {
44369 { 0, 0, 0, 0 },
44370 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44371 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803f00 }
44372 },
44373/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
44374 {
44375 { 0, 0, 0, 0 },
44376 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44377 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823f00 }
44378 },
44379/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
44380 {
44381 { 0, 0, 0, 0 },
44382 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44383 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182bf00 }
44384 },
44385/* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
44386 {
44387 { 0, 0, 0, 0 },
44388 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44389 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ff00 }
44390 },
44391/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
44392 {
44393 { 0, 0, 0, 0 },
44394 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44395 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843f00 }
44396 },
44397/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
44398 {
44399 { 0, 0, 0, 0 },
44400 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44401 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184bf00 }
44402 },
44403/* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
44404 {
44405 { 0, 0, 0, 0 },
44406 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44407 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ff00 }
44408 },
44409/* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
44410 {
44411 { 0, 0, 0, 0 },
44412 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
44413 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ff00 }
44414 },
44415/* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
44416 {
44417 { 0, 0, 0, 0 },
44418 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44419 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863f00 }
44420 },
44421/* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
44422 {
44423 { 0, 0, 0, 0 },
44424 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
44425 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186bf00 }
44426 },
a1a280bb 44427/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
49f58d10
JB		 44428 {
44429 { 0, 0, 0, 0 },
a1a280bb
DD		 44430 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44431 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x752c0000 }
49f58d10 44432 },
a1a280bb 44433/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
49f58d10
JB		 44434 {
44435 { 0, 0, 0, 0 },
a1a280bb
DD		 44436 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44437 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x752e0000 }
49f58d10 44438 },
a1a280bb 44439/* ste.w ${Dsp-16-u16},[a1a0] */
49f58d10
JB		 44440 {
44441 { 0, 0, 0, 0 },
a1a280bb
DD		 44442 { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44443 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x752f0000 }
44444 },
44445/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
44446 {
44447 { 0, 0, 0, 0 },
44448 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44449 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x751c0000 }
44450 },
44451/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
44452 {
44453 { 0, 0, 0, 0 },
44454 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44455 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x751e0000 }
44456 },
44457/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
44458 {
44459 { 0, 0, 0, 0 },
44460 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44461 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x751f0000 }
49f58d10
JB		 44462 },
44463/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
44464 {
44465 { 0, 0, 0, 0 },
44466 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 44467 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x750c0000 }
49f58d10
JB		 44468 },
44469/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
44470 {
44471 { 0, 0, 0, 0 },
44472 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 44473 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x750e0000 }
49f58d10
JB		 44474 },
44475/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
44476 {
44477 { 0, 0, 0, 0 },
44478 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
a1a280bb
DD		 44479 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x750f0000 }
44480 },
44481/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
44482 {
44483 { 0, 0, 0, 0 },
44484 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44485 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x752800 }
44486 },
44487/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
44488 {
44489 { 0, 0, 0, 0 },
44490 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44491 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x752a00 }
44492 },
44493/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
44494 {
44495 { 0, 0, 0, 0 },
44496 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44497 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x752b00 }
44498 },
44499/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
44500 {
44501 { 0, 0, 0, 0 },
44502 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44503 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75180000 }
44504 },
44505/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
44506 {
44507 { 0, 0, 0, 0 },
44508 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44509 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x751a0000 }
44510 },
44511/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
44512 {
44513 { 0, 0, 0, 0 },
44514 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44515 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x751b0000 }
44516 },
44517/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
44518 {
44519 { 0, 0, 0, 0 },
44520 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
44521 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75080000 }
44522 },
44523/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
44524 {
44525 { 0, 0, 0, 0 },
44526 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44527 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x750a0000 }
44528 },
44529/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
44530 {
44531 { 0, 0, 0, 0 },
44532 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44533 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x750b0000 }
44534 },
44535/* ste.w $Dst16RnHI,[a1a0] */
44536 {
44537 { 0, 0, 0, 0 },
44538 { { MNEM, ' ', OP (DST16RNHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44539 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7520 }
44540 },
44541/* ste.w $Dst16AnHI,[a1a0] */
44542 {
44543 { 0, 0, 0, 0 },
44544 { { MNEM, ' ', OP (DST16ANHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44545 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7524 }
44546 },
44547/* ste.w [$Dst16An],[a1a0] */
44548 {
44549 { 0, 0, 0, 0 },
44550 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44551 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7526 }
44552 },
44553/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
44554 {
44555 { 0, 0, 0, 0 },
44556 { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44557 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75100000 }
44558 },
44559/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
44560 {
44561 { 0, 0, 0, 0 },
44562 { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44563 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75140000 }
44564 },
44565/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
44566 {
44567 { 0, 0, 0, 0 },
44568 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44569 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75160000 }
49f58d10
JB		 44570 },
44571/* ste.w $Dst16RnHI,${Dsp-16-u20} */
44572 {
44573 { 0, 0, 0, 0 },
44574 { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 44575 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75000000 }
49f58d10
JB		 44576 },
44577/* ste.w $Dst16AnHI,${Dsp-16-u20} */
44578 {
44579 { 0, 0, 0, 0 },
44580 { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 44581 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75040000 }
49f58d10
JB		 44582 },
44583/* ste.w [$Dst16An],${Dsp-16-u20} */
44584 {
44585 { 0, 0, 0, 0 },
44586 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
a1a280bb 44587 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75060000 }
49f58d10 44588 },
a1a280bb 44589/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
49f58d10
JB		 44590 {
44591 { 0, 0, 0, 0 },
a1a280bb
DD		 44592 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44593 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x742c0000 }
49f58d10 44594 },
a1a280bb 44595/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
49f58d10
JB		 44596 {
44597 { 0, 0, 0, 0 },
a1a280bb
DD		 44598 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44599 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x742e0000 }
49f58d10 44600 },
a1a280bb 44601/* ste.b ${Dsp-16-u16},[a1a0] */
49f58d10
JB		 44602 {
44603 { 0, 0, 0, 0 },
a1a280bb
DD		 44604 { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44605 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x742f0000 }
44606 },
44607/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
44608 {
44609 { 0, 0, 0, 0 },
44610 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44611 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x741c0000 }
44612 },
44613/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
44614 {
44615 { 0, 0, 0, 0 },
44616 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44617 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x741e0000 }
44618 },
44619/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
44620 {
44621 { 0, 0, 0, 0 },
44622 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44623 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x741f0000 }
49f58d10
JB		 44624 },
44625/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
44626 {
44627 { 0, 0, 0, 0 },
44628 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 44629 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x740c0000 }
49f58d10
JB		 44630 },
44631/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
44632 {
44633 { 0, 0, 0, 0 },
44634 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 44635 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x740e0000 }
49f58d10
JB		 44636 },
44637/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
44638 {
44639 { 0, 0, 0, 0 },
44640 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
a1a280bb
DD		 44641 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x740f0000 }
44642 },
44643/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
44644 {
44645 { 0, 0, 0, 0 },
44646 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44647 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x742800 }
44648 },
44649/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
44650 {
44651 { 0, 0, 0, 0 },
44652 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44653 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x742a00 }
44654 },
44655/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
44656 {
44657 { 0, 0, 0, 0 },
44658 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44659 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x742b00 }
44660 },
44661/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
44662 {
44663 { 0, 0, 0, 0 },
44664 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44665 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74180000 }
44666 },
44667/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
44668 {
44669 { 0, 0, 0, 0 },
44670 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44671 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x741a0000 }
44672 },
44673/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
44674 {
44675 { 0, 0, 0, 0 },
44676 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44677 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x741b0000 }
44678 },
44679/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
44680 {
44681 { 0, 0, 0, 0 },
44682 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
44683 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74080000 }
44684 },
44685/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
44686 {
44687 { 0, 0, 0, 0 },
44688 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44689 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x740a0000 }
44690 },
44691/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
44692 {
44693 { 0, 0, 0, 0 },
44694 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44695 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x740b0000 }
44696 },
44697/* ste.b $Dst16RnQI,[a1a0] */
44698 {
44699 { 0, 0, 0, 0 },
44700 { { MNEM, ' ', OP (DST16RNQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44701 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7420 }
44702 },
44703/* ste.b $Dst16AnQI,[a1a0] */
44704 {
44705 { 0, 0, 0, 0 },
44706 { { MNEM, ' ', OP (DST16ANQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44707 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7424 }
44708 },
44709/* ste.b [$Dst16An],[a1a0] */
44710 {
44711 { 0, 0, 0, 0 },
44712 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44713 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7426 }
44714 },
44715/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
44716 {
44717 { 0, 0, 0, 0 },
44718 { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44719 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74100000 }
44720 },
44721/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
44722 {
44723 { 0, 0, 0, 0 },
44724 { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44725 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74140000 }
44726 },
44727/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
44728 {
44729 { 0, 0, 0, 0 },
44730 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44731 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74160000 }
49f58d10
JB		 44732 },
44733/* ste.b $Dst16RnQI,${Dsp-16-u20} */
44734 {
44735 { 0, 0, 0, 0 },
44736 { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 44737 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74000000 }
49f58d10
JB		 44738 },
44739/* ste.b $Dst16AnQI,${Dsp-16-u20} */
44740 {
44741 { 0, 0, 0, 0 },
44742 { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 44743 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74040000 }
49f58d10
JB		 44744 },
44745/* ste.b [$Dst16An],${Dsp-16-u20} */
44746 {
44747 { 0, 0, 0, 0 },
44748 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
a1a280bb 44749 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74060000 }
49f58d10 44750 },
a1a280bb 44751/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 44752 {
44753 { 0, 0, 0, 0 },
a1a280bb
DD		 44754 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
44755 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75ac0000 }
49f58d10 44756 },
a1a280bb 44757/* lde.w [a1a0],${Dsp-16-u16}[sb] */
49f58d10
JB		 44758 {
44759 { 0, 0, 0, 0 },
a1a280bb
DD		 44760 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
44761 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75ae0000 }
49f58d10 44762 },
a1a280bb 44763/* lde.w [a1a0],${Dsp-16-u16} */
49f58d10
JB		 44764 {
44765 { 0, 0, 0, 0 },
a1a280bb
DD		 44766 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
44767 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75af0000 }
44768 },
44769/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
44770 {
44771 { 0, 0, 0, 0 },
44772 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
44773 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x759c0000 }
44774 },
44775/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
44776 {
44777 { 0, 0, 0, 0 },
44778 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
44779 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x759e0000 }
44780 },
44781/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
44782 {
44783 { 0, 0, 0, 0 },
44784 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
44785 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x759f0000 }
49f58d10
JB		 44786 },
44787/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
44788 {
44789 { 0, 0, 0, 0 },
44790 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 44791 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x758c0000 }
49f58d10
JB		 44792 },
44793/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
44794 {
44795 { 0, 0, 0, 0 },
44796 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 44797 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x758e0000 }
49f58d10
JB		 44798 },
44799/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
44800 {
44801 { 0, 0, 0, 0 },
44802 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
a1a280bb
DD		 44803 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x758f0000 }
44804 },
44805/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
44806 {
44807 { 0, 0, 0, 0 },
44808 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
44809 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75a800 }
44810 },
44811/* lde.w [a1a0],${Dsp-16-u8}[sb] */
44812 {
44813 { 0, 0, 0, 0 },
44814 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
44815 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75aa00 }
44816 },
44817/* lde.w [a1a0],${Dsp-16-s8}[fb] */
44818 {
44819 { 0, 0, 0, 0 },
44820 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
44821 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75ab00 }
44822 },
44823/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
44824 {
44825 { 0, 0, 0, 0 },
44826 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
44827 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75980000 }
44828 },
44829/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
44830 {
44831 { 0, 0, 0, 0 },
44832 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
44833 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x759a0000 }
44834 },
44835/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
44836 {
44837 { 0, 0, 0, 0 },
44838 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
44839 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x759b0000 }
44840 },
44841/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
44842 {
44843 { 0, 0, 0, 0 },
44844 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
44845 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75880000 }
44846 },
44847/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
44848 {
44849 { 0, 0, 0, 0 },
44850 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
44851 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x758a0000 }
44852 },
44853/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
44854 {
44855 { 0, 0, 0, 0 },
44856 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
44857 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x758b0000 }
44858 },
44859/* lde.w [a1a0],$Dst16RnHI */
44860 {
44861 { 0, 0, 0, 0 },
44862 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
44863 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75a0 }
44864 },
44865/* lde.w [a1a0],$Dst16AnHI */
44866 {
44867 { 0, 0, 0, 0 },
44868 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
44869 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75a4 }
44870 },
44871/* lde.w [a1a0],[$Dst16An] */
44872 {
44873 { 0, 0, 0, 0 },
44874 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
44875 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75a6 }
44876 },
44877/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
44878 {
44879 { 0, 0, 0, 0 },
44880 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
44881 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75900000 }
44882 },
44883/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
44884 {
44885 { 0, 0, 0, 0 },
44886 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
44887 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75940000 }
44888 },
44889/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
44890 {
44891 { 0, 0, 0, 0 },
44892 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
44893 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75960000 }
49f58d10
JB		 44894 },
44895/* lde.w ${Dsp-16-u20},$Dst16RnHI */
44896 {
44897 { 0, 0, 0, 0 },
44898 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNHI), 0 } },
a1a280bb 44899 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75800000 }
49f58d10
JB		 44900 },
44901/* lde.w ${Dsp-16-u20},$Dst16AnHI */
44902 {
44903 { 0, 0, 0, 0 },
44904 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANHI), 0 } },
a1a280bb 44905 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75840000 }
49f58d10
JB		 44906 },
44907/* lde.w ${Dsp-16-u20},[$Dst16An] */
44908 {
44909 { 0, 0, 0, 0 },
44910 { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 44911 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75860000 }
49f58d10 44912 },
a1a280bb 44913/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 44914 {
44915 { 0, 0, 0, 0 },
a1a280bb
DD		 44916 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
44917 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74ac0000 }
49f58d10 44918 },
a1a280bb 44919/* lde.b [a1a0],${Dsp-16-u16}[sb] */
49f58d10
JB		 44920 {
44921 { 0, 0, 0, 0 },
a1a280bb
DD		 44922 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
44923 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74ae0000 }
49f58d10 44924 },
a1a280bb 44925/* lde.b [a1a0],${Dsp-16-u16} */
49f58d10
JB		 44926 {
44927 { 0, 0, 0, 0 },
a1a280bb
DD		 44928 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
44929 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74af0000 }
44930 },
44931/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
44932 {
44933 { 0, 0, 0, 0 },
44934 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
44935 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x749c0000 }
44936 },
44937/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
44938 {
44939 { 0, 0, 0, 0 },
44940 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
44941 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x749e0000 }
44942 },
44943/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
44944 {
44945 { 0, 0, 0, 0 },
44946 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
44947 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x749f0000 }
49f58d10
JB		 44948 },
44949/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
44950 {
44951 { 0, 0, 0, 0 },
44952 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 44953 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x748c0000 }
49f58d10
JB		 44954 },
44955/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
44956 {
44957 { 0, 0, 0, 0 },
44958 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 44959 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x748e0000 }
49f58d10
JB		 44960 },
44961/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
44962 {
44963 { 0, 0, 0, 0 },
44964 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
a1a280bb
DD		 44965 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x748f0000 }
44966 },
44967/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
44968 {
44969 { 0, 0, 0, 0 },
44970 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
44971 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74a800 }
44972 },
44973/* lde.b [a1a0],${Dsp-16-u8}[sb] */
44974 {
44975 { 0, 0, 0, 0 },
44976 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
44977 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74aa00 }
44978 },
44979/* lde.b [a1a0],${Dsp-16-s8}[fb] */
44980 {
44981 { 0, 0, 0, 0 },
44982 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
44983 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74ab00 }
44984 },
44985/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
44986 {
44987 { 0, 0, 0, 0 },
44988 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
44989 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74980000 }
44990 },
44991/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
44992 {
44993 { 0, 0, 0, 0 },
44994 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
44995 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x749a0000 }
44996 },
44997/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
44998 {
44999 { 0, 0, 0, 0 },
45000 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45001 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x749b0000 }
45002 },
45003/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
45004 {
45005 { 0, 0, 0, 0 },
45006 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45007 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74880000 }
45008 },
45009/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
45010 {
45011 { 0, 0, 0, 0 },
45012 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45013 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x748a0000 }
45014 },
45015/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
45016 {
45017 { 0, 0, 0, 0 },
45018 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45019 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x748b0000 }
45020 },
45021/* lde.b [a1a0],$Dst16RnQI */
45022 {
45023 { 0, 0, 0, 0 },
45024 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
45025 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74a0 }
45026 },
45027/* lde.b [a1a0],$Dst16AnQI */
45028 {
45029 { 0, 0, 0, 0 },
45030 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
45031 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74a4 }
45032 },
45033/* lde.b [a1a0],[$Dst16An] */
45034 {
45035 { 0, 0, 0, 0 },
45036 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45037 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74a6 }
45038 },
45039/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
45040 {
45041 { 0, 0, 0, 0 },
45042 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
45043 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74900000 }
45044 },
45045/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
45046 {
45047 { 0, 0, 0, 0 },
45048 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
45049 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74940000 }
45050 },
45051/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
45052 {
45053 { 0, 0, 0, 0 },
45054 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45055 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74960000 }
49f58d10
JB		 45056 },
45057/* lde.b ${Dsp-16-u20},$Dst16RnQI */
45058 {
45059 { 0, 0, 0, 0 },
45060 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNQI), 0 } },
a1a280bb 45061 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74800000 }
49f58d10
JB		 45062 },
45063/* lde.b ${Dsp-16-u20},$Dst16AnQI */
45064 {
45065 { 0, 0, 0, 0 },
45066 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANQI), 0 } },
a1a280bb 45067 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74840000 }
49f58d10
JB		 45068 },
45069/* lde.b ${Dsp-16-u20},[$Dst16An] */
45070 {
45071 { 0, 0, 0, 0 },
45072 { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 45073 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74860000 }
49f58d10
JB		 45074 },
45075/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
45076 {
45077 { 0, 0, 0, 0 },
45078 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32RNPREFIXEDSI), 0 } },
45079 & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d910 }
45080 },
45081/* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
45082 {
45083 { 0, 0, 0, 0 },
45084 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32ANPREFIXEDSI), 0 } },
45085 & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d190 }
45086 },
45087/* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
45088 {
45089 { 0, 0, 0, 0 },
45090 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
45091 & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d110 }
45092 },
45093/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
45094 {
45095 { 0, 0, 0, 0 },
45096 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
45097 & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d31000 }
45098 },
45099/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
45100 {
45101 { 0, 0, 0, 0 },
45102 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
45103 & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d51000 }
45104 },
45105/* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
45106 {
45107 { 0, 0, 0, 0 },
45108 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
45109 & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d71000 }
45110 },
45111/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
45112 {
45113 { 0, 0, 0, 0 },
45114 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
45115 & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d39000 }
45116 },
45117/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
45118 {
45119 { 0, 0, 0, 0 },
45120 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
45121 & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d59000 }
45122 },
45123/* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
45124 {
45125 { 0, 0, 0, 0 },
45126 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
45127 & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3d000 }
45128 },
45129/* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
45130 {
45131 { 0, 0, 0, 0 },
45132 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
45133 & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5d000 }
45134 },
45135/* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
45136 {
45137 { 0, 0, 0, 0 },
45138 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), 0 } },
45139 & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7d000 }
45140 },
45141/* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
45142 {
45143 { 0, 0, 0, 0 },
45144 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), 0 } },
45145 & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d79000 }
45146 },
45147/* stc ${cr2-32},$Dst32RnUnprefixedSI */
45148 {
45149 { 0, 0, 0, 0 },
45150 { { MNEM, ' ', OP (CR2_32), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
45151 & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd910 }
45152 },
45153/* stc ${cr2-32},$Dst32AnUnprefixedSI */
45154 {
45155 { 0, 0, 0, 0 },
45156 { { MNEM, ' ', OP (CR2_32), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
45157 & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd190 }
45158 },
45159/* stc ${cr2-32},[$Dst32AnUnprefixed] */
45160 {
45161 { 0, 0, 0, 0 },
45162 { { MNEM, ' ', OP (CR2_32), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45163 & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd110 }
45164 },
45165/* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
45166 {
45167 { 0, 0, 0, 0 },
45168 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45169 & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd31000 }
45170 },
45171/* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
45172 {
45173 { 0, 0, 0, 0 },
45174 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45175 & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5100000 }
45176 },
45177/* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
45178 {
45179 { 0, 0, 0, 0 },
45180 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45181 & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7100000 }
45182 },
45183/* stc ${cr2-32},${Dsp-16-u8}[sb] */
45184 {
45185 { 0, 0, 0, 0 },
45186 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45187 & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd39000 }
45188 },
45189/* stc ${cr2-32},${Dsp-16-u16}[sb] */
45190 {
45191 { 0, 0, 0, 0 },
45192 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45193 & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5900000 }
45194 },
45195/* stc ${cr2-32},${Dsp-16-s8}[fb] */
45196 {
45197 { 0, 0, 0, 0 },
45198 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45199 & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3d000 }
45200 },
45201/* stc ${cr2-32},${Dsp-16-s16}[fb] */
45202 {
45203 { 0, 0, 0, 0 },
45204 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
45205 & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5d00000 }
45206 },
45207/* stc ${cr2-32},${Dsp-16-u16} */
45208 {
45209 { 0, 0, 0, 0 },
45210 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), 0 } },
45211 & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7d00000 }
45212 },
45213/* stc ${cr2-32},${Dsp-16-u24} */
45214 {
45215 { 0, 0, 0, 0 },
45216 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), 0 } },
45217 & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7900000 }
45218 },
45219/* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
45220 {
45221 { 0, 0, 0, 0 },
45222 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32RNPREFIXEDHI), 0 } },
45223 & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d918 }
45224 },
45225/* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
45226 {
45227 { 0, 0, 0, 0 },
45228 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32ANPREFIXEDHI), 0 } },
45229 & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d198 }
45230 },
45231/* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
45232 {
45233 { 0, 0, 0, 0 },
45234 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
45235 & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d118 }
45236 },
45237/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
45238 {
45239 { 0, 0, 0, 0 },
45240 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
45241 & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d31800 }
45242 },
45243/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
45244 {
45245 { 0, 0, 0, 0 },
45246 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
45247 & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d51800 }
45248 },
45249/* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
45250 {
45251 { 0, 0, 0, 0 },
45252 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
45253 & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d71800 }
45254 },
45255/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
45256 {
45257 { 0, 0, 0, 0 },
45258 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
45259 & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d39800 }
45260 },
45261/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
45262 {
45263 { 0, 0, 0, 0 },
45264 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
45265 & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d59800 }
45266 },
45267/* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
45268 {
45269 { 0, 0, 0, 0 },
45270 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
45271 & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3d800 }
45272 },
45273/* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
45274 {
45275 { 0, 0, 0, 0 },
45276 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
45277 & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5d800 }
45278 },
45279/* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
45280 {
45281 { 0, 0, 0, 0 },
45282 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), 0 } },
45283 & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7d800 }
45284 },
45285/* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
45286 {
45287 { 0, 0, 0, 0 },
45288 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), 0 } },
45289 & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d79800 }
45290 },
45291/* stc pc,$Dst16RnHI */
45292 {
45293 { 0, 0, 0, 0 },
45294 { { MNEM, ' ', 'p', 'c', ',', OP (DST16RNHI), 0 } },
45295 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7cc0 }
45296 },
45297/* stc pc,$Dst16AnHI */
45298 {
45299 { 0, 0, 0, 0 },
45300 { { MNEM, ' ', 'p', 'c', ',', OP (DST16ANHI), 0 } },
45301 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7cc4 }
45302 },
45303/* stc pc,[$Dst16An] */
45304 {
45305 { 0, 0, 0, 0 },
45306 { { MNEM, ' ', 'p', 'c', ',', '[', OP (DST16AN), ']', 0 } },
45307 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7cc6 }
45308 },
45309/* stc pc,${Dsp-16-u8}[$Dst16An] */
45310 {
45311 { 0, 0, 0, 0 },
45312 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45313 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7cc800 }
45314 },
45315/* stc pc,${Dsp-16-u16}[$Dst16An] */
45316 {
45317 { 0, 0, 0, 0 },
45318 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45319 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7ccc0000 }
45320 },
45321/* stc pc,${Dsp-16-u8}[sb] */
45322 {
45323 { 0, 0, 0, 0 },
45324 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45325 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7cca00 }
45326 },
45327/* stc pc,${Dsp-16-u16}[sb] */
45328 {
45329 { 0, 0, 0, 0 },
45330 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45331 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7cce0000 }
45332 },
45333/* stc pc,${Dsp-16-s8}[fb] */
45334 {
45335 { 0, 0, 0, 0 },
45336 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45337 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7ccb00 }
45338 },
45339/* stc pc,${Dsp-16-u16} */
45340 {
45341 { 0, 0, 0, 0 },
45342 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), 0 } },
45343 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7ccf0000 }
45344 },
45345/* stc ${cr16},$Dst16RnHI */
45346 {
45347 { 0, 0, 0, 0 },
45348 { { MNEM, ' ', OP (CR16), ',', OP (DST16RNHI), 0 } },
45349 & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7b80 }
45350 },
45351/* stc ${cr16},$Dst16AnHI */
45352 {
45353 { 0, 0, 0, 0 },
45354 { { MNEM, ' ', OP (CR16), ',', OP (DST16ANHI), 0 } },
45355 & ifmt_stc16_src_dst16_An_direct_HI, { 0x7b84 }
45356 },
45357/* stc ${cr16},[$Dst16An] */
45358 {
45359 { 0, 0, 0, 0 },
45360 { { MNEM, ' ', OP (CR16), ',', '[', OP (DST16AN), ']', 0 } },
45361 & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7b86 }
45362 },
45363/* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
45364 {
45365 { 0, 0, 0, 0 },
45366 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45367 & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7b8800 }
45368 },
45369/* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
45370 {
45371 { 0, 0, 0, 0 },
45372 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45373 & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7b8c0000 }
45374 },
45375/* stc ${cr16},${Dsp-16-u8}[sb] */
45376 {
45377 { 0, 0, 0, 0 },
45378 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45379 & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7b8a00 }
45380 },
45381/* stc ${cr16},${Dsp-16-u16}[sb] */
45382 {
45383 { 0, 0, 0, 0 },
45384 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45385 & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7b8e0000 }
45386 },
45387/* stc ${cr16},${Dsp-16-s8}[fb] */
45388 {
45389 { 0, 0, 0, 0 },
45390 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45391 & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7b8b00 }
45392 },
45393/* stc ${cr16},${Dsp-16-u16} */
45394 {
45395 { 0, 0, 0, 0 },
45396 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), 0 } },
45397 & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7b8f0000 }
45398 },
45399/* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
45400 {
45401 { 0, 0, 0, 0 },
45402 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } },
45403 & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d900 }
45404 },
45405/* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
45406 {
45407 { 0, 0, 0, 0 },
45408 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } },
45409 & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d180 }
45410 },
45411/* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
45412 {
45413 { 0, 0, 0, 0 },
45414 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45415 & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d100 }
45416 },
45417/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45418 {
45419 { 0, 0, 0, 0 },
45420 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45421 & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d30000 }
45422 },
45423/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45424 {
45425 { 0, 0, 0, 0 },
45426 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45427 & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d50000 }
45428 },
45429/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45430 {
45431 { 0, 0, 0, 0 },
45432 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45433 & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d70000 }
45434 },
45435/* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
45436 {
45437 { 0, 0, 0, 0 },
45438 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45439 & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d38000 }
45440 },
45441/* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
45442 {
45443 { 0, 0, 0, 0 },
45444 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45445 & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d58000 }
45446 },
45447/* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
45448 {
45449 { 0, 0, 0, 0 },
45450 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45451 & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3c000 }
45452 },
45453/* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
45454 {
45455 { 0, 0, 0, 0 },
45456 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45457 & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5c000 }
45458 },
45459/* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
45460 {
45461 { 0, 0, 0, 0 },
45462 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR3_PREFIXED_32), 0 } },
45463 & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7c000 }
45464 },
45465/* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
45466 {
45467 { 0, 0, 0, 0 },
45468 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR3_PREFIXED_32), 0 } },
45469 & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d78000 }
45470 },
45471/* ldc $Dst32RnUnprefixedSI,${cr2-32} */
45472 {
45473 { 0, 0, 0, 0 },
45474 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), ',', OP (CR2_32), 0 } },
45475 & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd900 }
45476 },
45477/* ldc $Dst32AnUnprefixedSI,${cr2-32} */
45478 {
45479 { 0, 0, 0, 0 },
45480 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), ',', OP (CR2_32), 0 } },
45481 & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd180 }
45482 },
45483/* ldc [$Dst32AnUnprefixed],${cr2-32} */
45484 {
45485 { 0, 0, 0, 0 },
45486 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45487 & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd100 }
45488 },
45489/* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
45490 {
45491 { 0, 0, 0, 0 },
45492 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45493 & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd30000 }
45494 },
45495/* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
45496 {
45497 { 0, 0, 0, 0 },
45498 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45499 & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5000000 }
45500 },
45501/* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
45502 {
45503 { 0, 0, 0, 0 },
45504 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45505 & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7000000 }
45506 },
45507/* ldc ${Dsp-16-u8}[sb],${cr2-32} */
45508 {
45509 { 0, 0, 0, 0 },
45510 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } },
45511 & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd38000 }
45512 },
45513/* ldc ${Dsp-16-u16}[sb],${cr2-32} */
45514 {
45515 { 0, 0, 0, 0 },
45516 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } },
45517 & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5800000 }
45518 },
45519/* ldc ${Dsp-16-s8}[fb],${cr2-32} */
45520 {
45521 { 0, 0, 0, 0 },
45522 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } },
45523 & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3c000 }
45524 },
45525/* ldc ${Dsp-16-s16}[fb],${cr2-32} */
45526 {
45527 { 0, 0, 0, 0 },
45528 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } },
45529 & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5c00000 }
45530 },
45531/* ldc ${Dsp-16-u16},${cr2-32} */
45532 {
45533 { 0, 0, 0, 0 },
45534 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR2_32), 0 } },
45535 & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7c00000 }
45536 },
45537/* ldc ${Dsp-16-u24},${cr2-32} */
45538 {
45539 { 0, 0, 0, 0 },
45540 { { MNEM, ' ', OP (DSP_16_U24), ',', OP (CR2_32), 0 } },
45541 & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7800000 }
45542 },
45543/* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
45544 {
45545 { 0, 0, 0, 0 },
45546 { { MNEM, ' ', OP (DST32RNPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } },
45547 & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d908 }
45548 },
45549/* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
45550 {
45551 { 0, 0, 0, 0 },
45552 { { MNEM, ' ', OP (DST32ANPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } },
45553 & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d188 }
45554 },
45555/* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
45556 {
45557 { 0, 0, 0, 0 },
45558 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45559 & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d108 }
45560 },
45561/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45562 {
45563 { 0, 0, 0, 0 },
45564 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45565 & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d30800 }
45566 },
45567/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45568 {
45569 { 0, 0, 0, 0 },
45570 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45571 & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d50800 }
45572 },
45573/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45574 {
45575 { 0, 0, 0, 0 },
45576 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45577 & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d70800 }
45578 },
45579/* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
45580 {
45581 { 0, 0, 0, 0 },
45582 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45583 & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d38800 }
45584 },
45585/* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
45586 {
45587 { 0, 0, 0, 0 },
45588 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45589 & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d58800 }
45590 },
45591/* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
45592 {
45593 { 0, 0, 0, 0 },
45594 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45595 & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3c800 }
45596 },
45597/* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
45598 {
45599 { 0, 0, 0, 0 },
45600 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45601 & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5c800 }
45602 },
45603/* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
45604 {
45605 { 0, 0, 0, 0 },
45606 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR1_PREFIXED_32), 0 } },
45607 & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7c800 }
45608 },
45609/* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
45610 {
45611 { 0, 0, 0, 0 },
45612 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR1_PREFIXED_32), 0 } },
45613 & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d78800 }
45614 },
45615/* ldc $Dst16RnHI,${cr16} */
45616 {
45617 { 0, 0, 0, 0 },
45618 { { MNEM, ' ', OP (DST16RNHI), ',', OP (CR16), 0 } },
45619 & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7a80 }
45620 },
45621/* ldc $Dst16AnHI,${cr16} */
45622 {
45623 { 0, 0, 0, 0 },
45624 { { MNEM, ' ', OP (DST16ANHI), ',', OP (CR16), 0 } },
45625 & ifmt_stc16_src_dst16_An_direct_HI, { 0x7a84 }
45626 },
45627/* ldc [$Dst16An],${cr16} */
45628 {
45629 { 0, 0, 0, 0 },
45630 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
45631 & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7a86 }
45632 },
45633/* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
45634 {
45635 { 0, 0, 0, 0 },
45636 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
45637 & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7a8800 }
45638 },
45639/* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
45640 {
45641 { 0, 0, 0, 0 },
45642 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
45643 & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7a8c0000 }
45644 },
45645/* ldc ${Dsp-16-u8}[sb],${cr16} */
45646 {
45647 { 0, 0, 0, 0 },
45648 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR16), 0 } },
45649 & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7a8a00 }
45650 },
45651/* ldc ${Dsp-16-u16}[sb],${cr16} */
45652 {
45653 { 0, 0, 0, 0 },
45654 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR16), 0 } },
45655 & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7a8e0000 }
45656 },
45657/* ldc ${Dsp-16-s8}[fb],${cr16} */
45658 {
45659 { 0, 0, 0, 0 },
45660 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR16), 0 } },
45661 & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7a8b00 }
45662 },
45663/* ldc ${Dsp-16-u16},${cr16} */
45664 {
45665 { 0, 0, 0, 0 },
45666 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR16), 0 } },
45667 & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7a8f0000 }
45668 },
45669/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
45670 {
45671 { 0, 0, 0, 0 },
45672 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45673 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 }
45674 },
45675/* jsri.w ${Dsp-16-u24} */
45676 {
45677 { 0, 0, 0, 0 },
45678 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
45679 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 }
45680 },
45681/* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
45682 {
45683 { 0, 0, 0, 0 },
45684 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45685 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x94010000 }
45686 },
45687/* jsri.a ${Dsp-16-u16}[sb] */
45688 {
45689 { 0, 0, 0, 0 },
45690 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45691 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94810000 }
45692 },
45693/* jsri.a ${Dsp-16-s16}[fb] */
45694 {
45695 { 0, 0, 0, 0 },
45696 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
45697 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94c10000 }
45698 },
45699/* jsri.a ${Dsp-16-u16} */
45700 {
45701 { 0, 0, 0, 0 },
45702 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
45703 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x96c10000 }
45704 },
45705/* jsri.a ${Dsp-16-u16}[$Dst16An] */
45706 {
45707 { 0, 0, 0, 0 },
45708 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45709 & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI, { 0x7d1c0000 }
45710 },
45711/* jsri.a ${Dsp-16-u16}[sb] */
45712 {
45713 { 0, 0, 0, 0 },
45714 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45715 & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI, { 0x7d1e0000 }
45716 },
45717/* jsri.a ${Dsp-16-u16} */
45718 {
45719 { 0, 0, 0, 0 },
45720 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
45721 & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI, { 0x7d1f0000 }
45722 },
45723/* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
45724 {
45725 { 0, 0, 0, 0 },
45726 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45727 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x920100 }
45728 },
45729/* jsri.a ${Dsp-16-u8}[sb] */
45730 {
45731 { 0, 0, 0, 0 },
45732 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45733 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x928100 }
45734 },
45735/* jsri.a ${Dsp-16-s8}[fb] */
45736 {
45737 { 0, 0, 0, 0 },
45738 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45739 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92c100 }
45740 },
45741/* jsri.a ${Dsp-16-u8}[$Dst16An] */
45742 {
45743 { 0, 0, 0, 0 },
45744 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45745 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d1800 }
45746 },
45747/* jsri.a ${Dsp-16-u8}[sb] */
45748 {
45749 { 0, 0, 0, 0 },
45750 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45751 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d1a00 }
45752 },
45753/* jsri.a ${Dsp-16-s8}[fb] */
45754 {
45755 { 0, 0, 0, 0 },
45756 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45757 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d1b00 }
45758 },
45759/* jsri.a $Dst32RnUnprefixedSI */
45760 {
45761 { 0, 0, 0, 0 },
45762 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
45763 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x9801 }
45764 },
45765/* jsri.a $Dst32AnUnprefixedSI */
45766 {
45767 { 0, 0, 0, 0 },
45768 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
45769 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x9081 }
45770 },
45771/* jsri.a [$Dst32AnUnprefixed] */
45772 {
45773 { 0, 0, 0, 0 },
45774 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45775 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x9001 }
45776 },
45777/* jsri.a $Dst16RnSI */
45778 {
45779 { 0, 0, 0, 0 },
45780 { { MNEM, ' ', OP (DST16RNSI), 0 } },
45781 & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d10 }
45782 },
45783/* jsri.a $Dst16AnSI */
45784 {
45785 { 0, 0, 0, 0 },
45786 { { MNEM, ' ', OP (DST16ANSI), 0 } },
45787 & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d14 }
45788 },
45789/* jsri.a [$Dst16An] */
45790 {
45791 { 0, 0, 0, 0 },
45792 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
45793 & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 }
45794 },
45795/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
45796 {
45797 { 0, 0, 0, 0 },
45798 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45799 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 }
45800 },
45801/* jsri.w ${Dsp-16-u24} */
45802 {
45803 { 0, 0, 0, 0 },
45804 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
45805 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 }
45806 },
45807/* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
45808 {
45809 { 0, 0, 0, 0 },
45810 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45811 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc51f0000 }
45812 },
45813/* jsri.w ${Dsp-16-u16}[sb] */
45814 {
45815 { 0, 0, 0, 0 },
45816 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45817 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc59f0000 }
45818 },
45819/* jsri.w ${Dsp-16-s16}[fb] */
45820 {
45821 { 0, 0, 0, 0 },
45822 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
45823 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5df0000 }
45824 },
45825/* jsri.w ${Dsp-16-u16} */
45826 {
45827 { 0, 0, 0, 0 },
45828 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
45829 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7df0000 }
45830 },
45831/* jsri.w ${Dsp-16-u16}[$Dst16An] */
45832 {
45833 { 0, 0, 0, 0 },
45834 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45835 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d3c0000 }
45836 },
45837/* jsri.w ${Dsp-16-u16}[sb] */
45838 {
45839 { 0, 0, 0, 0 },
45840 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45841 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d3e0000 }
45842 },
45843/* jsri.w ${Dsp-16-u16} */
45844 {
45845 { 0, 0, 0, 0 },
45846 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
45847 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d3f0000 }
45848 },
45849/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
45850 {
45851 { 0, 0, 0, 0 },
45852 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45853 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31f00 }
45854 },
45855/* jsri.w ${Dsp-16-u8}[sb] */
45856 {
45857 { 0, 0, 0, 0 },
45858 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45859 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39f00 }
45860 },
45861/* jsri.w ${Dsp-16-s8}[fb] */
45862 {
45863 { 0, 0, 0, 0 },
45864 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45865 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3df00 }
45866 },
45867/* jsri.w ${Dsp-16-u8}[$Dst16An] */
45868 {
45869 { 0, 0, 0, 0 },
45870 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45871 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d3800 }
45872 },
45873/* jsri.w ${Dsp-16-u8}[sb] */
45874 {
45875 { 0, 0, 0, 0 },
45876 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45877 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d3a00 }
45878 },
45879/* jsri.w ${Dsp-16-s8}[fb] */
45880 {
45881 { 0, 0, 0, 0 },
45882 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45883 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 }
45884 },
45885/* jsri.w $Dst32RnUnprefixedHI */
45886 {
45887 { 0, 0, 0, 0 },
45888 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
45889 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc91f }
45890 },
45891/* jsri.w $Dst32AnUnprefixedHI */
45892 {
45893 { 0, 0, 0, 0 },
45894 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
45895 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc19f }
45896 },
45897/* jsri.w [$Dst32AnUnprefixed] */
45898 {
45899 { 0, 0, 0, 0 },
45900 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45901 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc11f }
45902 },
45903/* jsri.w $Dst16RnHI */
45904 {
45905 { 0, 0, 0, 0 },
45906 { { MNEM, ' ', OP (DST16RNHI), 0 } },
45907 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d30 }
45908 },
45909/* jsri.w $Dst16AnHI */
45910 {
45911 { 0, 0, 0, 0 },
45912 { { MNEM, ' ', OP (DST16ANHI), 0 } },
45913 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d34 }
45914 },
45915/* jsri.w [$Dst16An] */
45916 {
45917 { 0, 0, 0, 0 },
45918 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
45919 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 }
45920 },
45921/* jmpi.a $Dst32RnUnprefixedSI */
45922 {
45923 { 0, 0, 0, 0 },
45924 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
45925 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x8801 }
45926 },
45927/* jmpi.a $Dst32AnUnprefixedSI */
45928 {
45929 { 0, 0, 0, 0 },
45930 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
45931 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x8081 }
45932 },
45933/* jmpi.a [$Dst32AnUnprefixed] */
45934 {
45935 { 0, 0, 0, 0 },
45936 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45937 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x8001 }
45938 },
45939/* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
45940 {
45941 { 0, 0, 0, 0 },
45942 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45943 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x820100 }
45944 },
45945/* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
45946 {
45947 { 0, 0, 0, 0 },
45948 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45949 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x84010000 }
45950 },
45951/* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
45952 {
45953 { 0, 0, 0, 0 },
45954 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45955 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x86010000 }
45956 },
45957/* jmpi.a ${Dsp-16-u8}[sb] */
45958 {
45959 { 0, 0, 0, 0 },
45960 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45961 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828100 }
45962 },
45963/* jmpi.a ${Dsp-16-u16}[sb] */
45964 {
45965 { 0, 0, 0, 0 },
45966 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45967 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84810000 }
45968 },
45969/* jmpi.a ${Dsp-16-s8}[fb] */
45970 {
45971 { 0, 0, 0, 0 },
45972 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45973 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c100 }
45974 },
45975/* jmpi.a ${Dsp-16-s16}[fb] */
45976 {
45977 { 0, 0, 0, 0 },
45978 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
45979 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c10000 }
45980 },
45981/* jmpi.a ${Dsp-16-u16} */
45982 {
45983 { 0, 0, 0, 0 },
45984 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
45985 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x86c10000 }
45986 },
45987/* jmpi.a ${Dsp-16-u24} */
45988 {
45989 { 0, 0, 0, 0 },
45990 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
45991 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x86810000 }
45992 },
45993/* jmpi.a $Dst16RnSI */
45994 {
45995 { 0, 0, 0, 0 },
45996 { { MNEM, ' ', OP (DST16RNSI), 0 } },
45997 & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d00 }
45998 },
45999/* jmpi.a $Dst16AnSI */
46000 {
46001 { 0, 0, 0, 0 },
46002 { { MNEM, ' ', OP (DST16ANSI), 0 } },
46003 & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d04 }
46004 },
46005/* jmpi.a [$Dst16An] */
46006 {
46007 { 0, 0, 0, 0 },
46008 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46009 & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d06 }
46010 },
46011/* jmpi.a ${Dsp-16-u8}[$Dst16An] */
46012 {
46013 { 0, 0, 0, 0 },
46014 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46015 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d0800 }
46016 },
46017/* jmpi.a ${Dsp-16-u16}[$Dst16An] */
46018 {
46019 { 0, 0, 0, 0 },
46020 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
46021 & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI, { 0x7d0c0000 }
46022 },
46023/* jmpi.a ${Dsp-16-u8}[sb] */
46024 {
46025 { 0, 0, 0, 0 },
46026 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46027 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d0a00 }
46028 },
46029/* jmpi.a ${Dsp-16-u16}[sb] */
46030 {
46031 { 0, 0, 0, 0 },
46032 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46033 & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI, { 0x7d0e0000 }
46034 },
46035/* jmpi.a ${Dsp-16-s8}[fb] */
46036 {
46037 { 0, 0, 0, 0 },
46038 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46039 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d0b00 }
46040 },
46041/* jmpi.a ${Dsp-16-u16} */
46042 {
46043 { 0, 0, 0, 0 },
46044 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46045 & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI, { 0x7d0f0000 }
46046 },
46047/* jmpi.w $Dst32RnUnprefixedHI */
46048 {
46049 { 0, 0, 0, 0 },
46050 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46051 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90f }
46052 },
46053/* jmpi.w $Dst32AnUnprefixedHI */
46054 {
46055 { 0, 0, 0, 0 },
46056 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46057 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18f }
46058 },
46059/* jmpi.w [$Dst32AnUnprefixed] */
46060 {
46061 { 0, 0, 0, 0 },
46062 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46063 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10f }
46064 },
46065/* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46066 {
46067 { 0, 0, 0, 0 },
46068 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46069 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30f00 }
46070 },
46071/* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46072 {
46073 { 0, 0, 0, 0 },
46074 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46075 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50f0000 }
46076 },
46077/* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46078 {
46079 { 0, 0, 0, 0 },
46080 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46081 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70f0000 }
46082 },
46083/* jmpi.w ${Dsp-16-u8}[sb] */
46084 {
46085 { 0, 0, 0, 0 },
46086 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46087 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38f00 }
46088 },
46089/* jmpi.w ${Dsp-16-u16}[sb] */
46090 {
46091 { 0, 0, 0, 0 },
46092 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46093 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58f0000 }
46094 },
46095/* jmpi.w ${Dsp-16-s8}[fb] */
46096 {
46097 { 0, 0, 0, 0 },
46098 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46099 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cf00 }
46100 },
46101/* jmpi.w ${Dsp-16-s16}[fb] */
46102 {
46103 { 0, 0, 0, 0 },
46104 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46105 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cf0000 }
46106 },
46107/* jmpi.w ${Dsp-16-u16} */
46108 {
46109 { 0, 0, 0, 0 },
46110 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46111 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cf0000 }
46112 },
46113/* jmpi.w ${Dsp-16-u24} */
46114 {
46115 { 0, 0, 0, 0 },
46116 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46117 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78f0000 }
46118 },
46119/* jmpi.w $Dst16RnHI */
46120 {
46121 { 0, 0, 0, 0 },
46122 { { MNEM, ' ', OP (DST16RNHI), 0 } },
46123 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d20 }
46124 },
46125/* jmpi.w $Dst16AnHI */
46126 {
46127 { 0, 0, 0, 0 },
46128 { { MNEM, ' ', OP (DST16ANHI), 0 } },
46129 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d24 }
46130 },
46131/* jmpi.w [$Dst16An] */
46132 {
46133 { 0, 0, 0, 0 },
46134 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46135 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d26 }
46136 },
46137/* jmpi.w ${Dsp-16-u8}[$Dst16An] */
46138 {
46139 { 0, 0, 0, 0 },
46140 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46141 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d2800 }
46142 },
46143/* jmpi.w ${Dsp-16-u16}[$Dst16An] */
46144 {
46145 { 0, 0, 0, 0 },
46146 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
46147 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d2c0000 }
46148 },
46149/* jmpi.w ${Dsp-16-u8}[sb] */
46150 {
46151 { 0, 0, 0, 0 },
46152 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46153 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d2a00 }
46154 },
46155/* jmpi.w ${Dsp-16-u16}[sb] */
46156 {
46157 { 0, 0, 0, 0 },
46158 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46159 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d2e0000 }
46160 },
46161/* jmpi.w ${Dsp-16-s8}[fb] */
46162 {
46163 { 0, 0, 0, 0 },
46164 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46165 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d2b00 }
46166 },
46167/* jmpi.w ${Dsp-16-u16} */
46168 {
46169 { 0, 0, 0, 0 },
46170 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46171 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d2f0000 }
46172 },
46173/* indexws.w $Dst32RnUnprefixedHI */
46174 {
46175 { 0, 0, 0, 0 },
46176 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 46177 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc933 }
49f58d10
JB		 46178 },
46179/* indexws.w $Dst32AnUnprefixedHI */
46180 {
46181 { 0, 0, 0, 0 },
46182 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 46183 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1b3 }
49f58d10
JB		 46184 },
46185/* indexws.w [$Dst32AnUnprefixed] */
46186 {
46187 { 0, 0, 0, 0 },
46188 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46189 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc133 }
49f58d10
JB		 46190 },
46191/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46192 {
46193 { 0, 0, 0, 0 },
46194 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46195 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33300 }
49f58d10
JB		 46196 },
46197/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46198 {
46199 { 0, 0, 0, 0 },
46200 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46201 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5330000 }
49f58d10
JB		 46202 },
46203/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46204 {
46205 { 0, 0, 0, 0 },
46206 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46207 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7330000 }
49f58d10
JB		 46208 },
46209/* indexws.w ${Dsp-16-u8}[sb] */
46210 {
46211 { 0, 0, 0, 0 },
46212 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 46213 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3b300 }
49f58d10
JB		 46214 },
46215/* indexws.w ${Dsp-16-u16}[sb] */
46216 {
46217 { 0, 0, 0, 0 },
46218 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 46219 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5b30000 }
49f58d10
JB		 46220 },
46221/* indexws.w ${Dsp-16-s8}[fb] */
46222 {
46223 { 0, 0, 0, 0 },
46224 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 46225 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3f300 }
49f58d10
JB		 46226 },
46227/* indexws.w ${Dsp-16-s16}[fb] */
46228 {
46229 { 0, 0, 0, 0 },
46230 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 46231 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5f30000 }
49f58d10
JB		 46232 },
46233/* indexws.w ${Dsp-16-u16} */
46234 {
46235 { 0, 0, 0, 0 },
46236 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 46237 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7f30000 }
49f58d10
JB		 46238 },
46239/* indexws.w ${Dsp-16-u24} */
46240 {
46241 { 0, 0, 0, 0 },
46242 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 46243 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7b30000 }
49f58d10
JB		 46244 },
46245/* indexws.b $Dst32RnUnprefixedQI */
46246 {
46247 { 0, 0, 0, 0 },
46248 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46249 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc823 }
46250 },
46251/* indexws.b $Dst32AnUnprefixedQI */
46252 {
46253 { 0, 0, 0, 0 },
46254 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46255 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0a3 }
46256 },
46257/* indexws.b [$Dst32AnUnprefixed] */
46258 {
46259 { 0, 0, 0, 0 },
46260 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46261 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc023 }
46262 },
46263/* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46264 {
46265 { 0, 0, 0, 0 },
46266 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46267 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22300 }
46268 },
46269/* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46270 {
46271 { 0, 0, 0, 0 },
46272 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46273 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4230000 }
46274 },
46275/* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46276 {
46277 { 0, 0, 0, 0 },
46278 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46279 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6230000 }
46280 },
46281/* indexws.b ${Dsp-16-u8}[sb] */
46282 {
46283 { 0, 0, 0, 0 },
46284 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46285 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2a300 }
46286 },
46287/* indexws.b ${Dsp-16-u16}[sb] */
46288 {
46289 { 0, 0, 0, 0 },
46290 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46291 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4a30000 }
46292 },
46293/* indexws.b ${Dsp-16-s8}[fb] */
46294 {
46295 { 0, 0, 0, 0 },
46296 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46297 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2e300 }
46298 },
46299/* indexws.b ${Dsp-16-s16}[fb] */
46300 {
46301 { 0, 0, 0, 0 },
46302 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46303 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4e30000 }
46304 },
46305/* indexws.b ${Dsp-16-u16} */
46306 {
46307 { 0, 0, 0, 0 },
46308 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46309 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6e30000 }
46310 },
46311/* indexws.b ${Dsp-16-u24} */
46312 {
46313 { 0, 0, 0, 0 },
46314 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46315 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6a30000 }
46316 },
46317/* indexwd.w $Dst32RnUnprefixedHI */
46318 {
46319 { 0, 0, 0, 0 },
46320 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 46321 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa933 }
49f58d10
JB		 46322 },
46323/* indexwd.w $Dst32AnUnprefixedHI */
46324 {
46325 { 0, 0, 0, 0 },
46326 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 46327 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1b3 }
49f58d10
JB		 46328 },
46329/* indexwd.w [$Dst32AnUnprefixed] */
46330 {
46331 { 0, 0, 0, 0 },
46332 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46333 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa133 }
49f58d10
JB		 46334 },
46335/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46336 {
46337 { 0, 0, 0, 0 },
46338 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46339 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33300 }
49f58d10
JB		 46340 },
46341/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46342 {
46343 { 0, 0, 0, 0 },
46344 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46345 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5330000 }
49f58d10
JB		 46346 },
46347/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46348 {
46349 { 0, 0, 0, 0 },
46350 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46351 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7330000 }
49f58d10
JB		 46352 },
46353/* indexwd.w ${Dsp-16-u8}[sb] */
46354 {
46355 { 0, 0, 0, 0 },
46356 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 46357 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3b300 }
49f58d10
JB		 46358 },
46359/* indexwd.w ${Dsp-16-u16}[sb] */
46360 {
46361 { 0, 0, 0, 0 },
46362 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 46363 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5b30000 }
49f58d10
JB		 46364 },
46365/* indexwd.w ${Dsp-16-s8}[fb] */
46366 {
46367 { 0, 0, 0, 0 },
46368 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 46369 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3f300 }
49f58d10
JB		 46370 },
46371/* indexwd.w ${Dsp-16-s16}[fb] */
46372 {
46373 { 0, 0, 0, 0 },
46374 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 46375 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5f30000 }
49f58d10
JB		 46376 },
46377/* indexwd.w ${Dsp-16-u16} */
46378 {
46379 { 0, 0, 0, 0 },
46380 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 46381 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7f30000 }
49f58d10
JB		 46382 },
46383/* indexwd.w ${Dsp-16-u24} */
46384 {
46385 { 0, 0, 0, 0 },
46386 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 46387 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7b30000 }
49f58d10
JB		 46388 },
46389/* indexwd.b $Dst32RnUnprefixedQI */
46390 {
46391 { 0, 0, 0, 0 },
46392 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46393 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa823 }
46394 },
46395/* indexwd.b $Dst32AnUnprefixedQI */
46396 {
46397 { 0, 0, 0, 0 },
46398 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46399 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0a3 }
46400 },
46401/* indexwd.b [$Dst32AnUnprefixed] */
46402 {
46403 { 0, 0, 0, 0 },
46404 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46405 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa023 }
46406 },
46407/* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46408 {
46409 { 0, 0, 0, 0 },
46410 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46411 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22300 }
46412 },
46413/* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46414 {
46415 { 0, 0, 0, 0 },
46416 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46417 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4230000 }
46418 },
46419/* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46420 {
46421 { 0, 0, 0, 0 },
46422 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46423 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6230000 }
46424 },
46425/* indexwd.b ${Dsp-16-u8}[sb] */
46426 {
46427 { 0, 0, 0, 0 },
46428 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46429 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2a300 }
46430 },
46431/* indexwd.b ${Dsp-16-u16}[sb] */
46432 {
46433 { 0, 0, 0, 0 },
46434 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46435 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4a30000 }
46436 },
46437/* indexwd.b ${Dsp-16-s8}[fb] */
46438 {
46439 { 0, 0, 0, 0 },
46440 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46441 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2e300 }
46442 },
46443/* indexwd.b ${Dsp-16-s16}[fb] */
46444 {
46445 { 0, 0, 0, 0 },
46446 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46447 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4e30000 }
46448 },
46449/* indexwd.b ${Dsp-16-u16} */
46450 {
46451 { 0, 0, 0, 0 },
46452 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46453 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6e30000 }
46454 },
46455/* indexwd.b ${Dsp-16-u24} */
46456 {
46457 { 0, 0, 0, 0 },
46458 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46459 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6a30000 }
46460 },
46461/* indexw.w $Dst32RnUnprefixedHI */
46462 {
46463 { 0, 0, 0, 0 },
46464 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 46465 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8933 }
49f58d10
JB		 46466 },
46467/* indexw.w $Dst32AnUnprefixedHI */
46468 {
46469 { 0, 0, 0, 0 },
46470 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 46471 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x81b3 }
49f58d10
JB		 46472 },
46473/* indexw.w [$Dst32AnUnprefixed] */
46474 {
46475 { 0, 0, 0, 0 },
46476 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46477 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8133 }
49f58d10
JB		 46478 },
46479/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46480 {
46481 { 0, 0, 0, 0 },
46482 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46483 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x833300 }
49f58d10
JB		 46484 },
46485/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46486 {
46487 { 0, 0, 0, 0 },
46488 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46489 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85330000 }
49f58d10
JB		 46490 },
46491/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46492 {
46493 { 0, 0, 0, 0 },
46494 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46495 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87330000 }
49f58d10
JB		 46496 },
46497/* indexw.w ${Dsp-16-u8}[sb] */
46498 {
46499 { 0, 0, 0, 0 },
46500 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 46501 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83b300 }
49f58d10
JB		 46502 },
46503/* indexw.w ${Dsp-16-u16}[sb] */
46504 {
46505 { 0, 0, 0, 0 },
46506 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 46507 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85b30000 }
49f58d10
JB		 46508 },
46509/* indexw.w ${Dsp-16-s8}[fb] */
46510 {
46511 { 0, 0, 0, 0 },
46512 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 46513 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83f300 }
49f58d10
JB		 46514 },
46515/* indexw.w ${Dsp-16-s16}[fb] */
46516 {
46517 { 0, 0, 0, 0 },
46518 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 46519 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85f30000 }
49f58d10
JB		 46520 },
46521/* indexw.w ${Dsp-16-u16} */
46522 {
46523 { 0, 0, 0, 0 },
46524 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 46525 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87f30000 }
49f58d10
JB		 46526 },
46527/* indexw.w ${Dsp-16-u24} */
46528 {
46529 { 0, 0, 0, 0 },
46530 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 46531 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87b30000 }
49f58d10
JB		 46532 },
46533/* indexw.b $Dst32RnUnprefixedQI */
46534 {
46535 { 0, 0, 0, 0 },
46536 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46537 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8823 }
46538 },
46539/* indexw.b $Dst32AnUnprefixedQI */
46540 {
46541 { 0, 0, 0, 0 },
46542 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46543 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x80a3 }
46544 },
46545/* indexw.b [$Dst32AnUnprefixed] */
46546 {
46547 { 0, 0, 0, 0 },
46548 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46549 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8023 }
46550 },
46551/* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46552 {
46553 { 0, 0, 0, 0 },
46554 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46555 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x822300 }
46556 },
46557/* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46558 {
46559 { 0, 0, 0, 0 },
46560 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46561 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84230000 }
46562 },
46563/* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46564 {
46565 { 0, 0, 0, 0 },
46566 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46567 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86230000 }
46568 },
46569/* indexw.b ${Dsp-16-u8}[sb] */
46570 {
46571 { 0, 0, 0, 0 },
46572 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46573 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a300 }
46574 },
46575/* indexw.b ${Dsp-16-u16}[sb] */
46576 {
46577 { 0, 0, 0, 0 },
46578 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46579 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a30000 }
46580 },
46581/* indexw.b ${Dsp-16-s8}[fb] */
46582 {
46583 { 0, 0, 0, 0 },
46584 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46585 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e300 }
46586 },
46587/* indexw.b ${Dsp-16-s16}[fb] */
46588 {
46589 { 0, 0, 0, 0 },
46590 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46591 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e30000 }
46592 },
46593/* indexw.b ${Dsp-16-u16} */
46594 {
46595 { 0, 0, 0, 0 },
46596 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46597 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86e30000 }
46598 },
46599/* indexw.b ${Dsp-16-u24} */
46600 {
46601 { 0, 0, 0, 0 },
46602 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46603 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86a30000 }
46604 },
46605/* indexls.w $Dst32RnUnprefixedHI */
46606 {
46607 { 0, 0, 0, 0 },
46608 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 46609 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9913 }
49f58d10
JB		 46610 },
46611/* indexls.w $Dst32AnUnprefixedHI */
46612 {
46613 { 0, 0, 0, 0 },
46614 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 46615 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9193 }
49f58d10
JB		 46616 },
46617/* indexls.w [$Dst32AnUnprefixed] */
46618 {
46619 { 0, 0, 0, 0 },
46620 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46621 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9113 }
49f58d10
JB		 46622 },
46623/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46624 {
46625 { 0, 0, 0, 0 },
46626 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46627 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931300 }
49f58d10
JB		 46628 },
46629/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46630 {
46631 { 0, 0, 0, 0 },
46632 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46633 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95130000 }
49f58d10
JB		 46634 },
46635/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46636 {
46637 { 0, 0, 0, 0 },
46638 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46639 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97130000 }
49f58d10
JB		 46640 },
46641/* indexls.w ${Dsp-16-u8}[sb] */
46642 {
46643 { 0, 0, 0, 0 },
46644 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 46645 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939300 }
49f58d10
JB		 46646 },
46647/* indexls.w ${Dsp-16-u16}[sb] */
46648 {
46649 { 0, 0, 0, 0 },
46650 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 46651 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95930000 }
49f58d10
JB		 46652 },
46653/* indexls.w ${Dsp-16-s8}[fb] */
46654 {
46655 { 0, 0, 0, 0 },
46656 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 46657 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93d300 }
49f58d10
JB		 46658 },
46659/* indexls.w ${Dsp-16-s16}[fb] */
46660 {
46661 { 0, 0, 0, 0 },
46662 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 46663 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95d30000 }
49f58d10
JB		 46664 },
46665/* indexls.w ${Dsp-16-u16} */
46666 {
46667 { 0, 0, 0, 0 },
46668 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 46669 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97d30000 }
49f58d10
JB		 46670 },
46671/* indexls.w ${Dsp-16-u24} */
46672 {
46673 { 0, 0, 0, 0 },
46674 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 46675 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97930000 }
49f58d10
JB		 46676 },
46677/* indexls.b $Dst32RnUnprefixedQI */
46678 {
46679 { 0, 0, 0, 0 },
46680 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46681 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9803 }
46682 },
46683/* indexls.b $Dst32AnUnprefixedQI */
46684 {
46685 { 0, 0, 0, 0 },
46686 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46687 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x9083 }
46688 },
46689/* indexls.b [$Dst32AnUnprefixed] */
46690 {
46691 { 0, 0, 0, 0 },
46692 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46693 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9003 }
46694 },
46695/* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46696 {
46697 { 0, 0, 0, 0 },
46698 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46699 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x920300 }
46700 },
46701/* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46702 {
46703 { 0, 0, 0, 0 },
46704 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46705 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94030000 }
46706 },
46707/* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46708 {
46709 { 0, 0, 0, 0 },
46710 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46711 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96030000 }
46712 },
46713/* indexls.b ${Dsp-16-u8}[sb] */
46714 {
46715 { 0, 0, 0, 0 },
46716 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46717 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928300 }
46718 },
46719/* indexls.b ${Dsp-16-u16}[sb] */
46720 {
46721 { 0, 0, 0, 0 },
46722 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46723 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94830000 }
46724 },
46725/* indexls.b ${Dsp-16-s8}[fb] */
46726 {
46727 { 0, 0, 0, 0 },
46728 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46729 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92c300 }
46730 },
46731/* indexls.b ${Dsp-16-s16}[fb] */
46732 {
46733 { 0, 0, 0, 0 },
46734 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46735 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94c30000 }
46736 },
46737/* indexls.b ${Dsp-16-u16} */
46738 {
46739 { 0, 0, 0, 0 },
46740 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46741 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96c30000 }
46742 },
46743/* indexls.b ${Dsp-16-u24} */
46744 {
46745 { 0, 0, 0, 0 },
46746 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46747 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96830000 }
46748 },
46749/* indexld.w $Dst32RnUnprefixedHI */
46750 {
46751 { 0, 0, 0, 0 },
46752 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 46753 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb933 }
49f58d10
JB		 46754 },
46755/* indexld.w $Dst32AnUnprefixedHI */
46756 {
46757 { 0, 0, 0, 0 },
46758 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 46759 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1b3 }
49f58d10
JB		 46760 },
46761/* indexld.w [$Dst32AnUnprefixed] */
46762 {
46763 { 0, 0, 0, 0 },
46764 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46765 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb133 }
49f58d10
JB		 46766 },
46767/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46768 {
46769 { 0, 0, 0, 0 },
46770 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46771 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33300 }
49f58d10
JB		 46772 },
46773/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46774 {
46775 { 0, 0, 0, 0 },
46776 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46777 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb5330000 }
49f58d10
JB		 46778 },
46779/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46780 {
46781 { 0, 0, 0, 0 },
46782 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46783 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb7330000 }
49f58d10
JB		 46784 },
46785/* indexld.w ${Dsp-16-u8}[sb] */
46786 {
46787 { 0, 0, 0, 0 },
46788 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 46789 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3b300 }
49f58d10
JB		 46790 },
46791/* indexld.w ${Dsp-16-u16}[sb] */
46792 {
46793 { 0, 0, 0, 0 },
46794 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 46795 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5b30000 }
49f58d10
JB		 46796 },
46797/* indexld.w ${Dsp-16-s8}[fb] */
46798 {
46799 { 0, 0, 0, 0 },
46800 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 46801 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3f300 }
49f58d10
JB		 46802 },
46803/* indexld.w ${Dsp-16-s16}[fb] */
46804 {
46805 { 0, 0, 0, 0 },
46806 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 46807 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5f30000 }
49f58d10
JB		 46808 },
46809/* indexld.w ${Dsp-16-u16} */
46810 {
46811 { 0, 0, 0, 0 },
46812 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 46813 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7f30000 }
49f58d10
JB		 46814 },
46815/* indexld.w ${Dsp-16-u24} */
46816 {
46817 { 0, 0, 0, 0 },
46818 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 46819 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7b30000 }
49f58d10
JB		 46820 },
46821/* indexld.b $Dst32RnUnprefixedQI */
46822 {
46823 { 0, 0, 0, 0 },
46824 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46825 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb823 }
46826 },
46827/* indexld.b $Dst32AnUnprefixedQI */
46828 {
46829 { 0, 0, 0, 0 },
46830 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46831 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0a3 }
46832 },
46833/* indexld.b [$Dst32AnUnprefixed] */
46834 {
46835 { 0, 0, 0, 0 },
46836 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46837 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb023 }
46838 },
46839/* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46840 {
46841 { 0, 0, 0, 0 },
46842 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46843 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22300 }
46844 },
46845/* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46846 {
46847 { 0, 0, 0, 0 },
46848 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46849 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb4230000 }
46850 },
46851/* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46852 {
46853 { 0, 0, 0, 0 },
46854 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46855 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb6230000 }
46856 },
46857/* indexld.b ${Dsp-16-u8}[sb] */
46858 {
46859 { 0, 0, 0, 0 },
46860 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46861 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2a300 }
46862 },
46863/* indexld.b ${Dsp-16-u16}[sb] */
46864 {
46865 { 0, 0, 0, 0 },
46866 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46867 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4a30000 }
46868 },
46869/* indexld.b ${Dsp-16-s8}[fb] */
46870 {
46871 { 0, 0, 0, 0 },
46872 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46873 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2e300 }
46874 },
46875/* indexld.b ${Dsp-16-s16}[fb] */
46876 {
46877 { 0, 0, 0, 0 },
46878 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46879 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4e30000 }
46880 },
46881/* indexld.b ${Dsp-16-u16} */
46882 {
46883 { 0, 0, 0, 0 },
46884 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46885 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6e30000 }
46886 },
46887/* indexld.b ${Dsp-16-u24} */
46888 {
46889 { 0, 0, 0, 0 },
46890 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46891 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6a30000 }
46892 },
46893/* indexl.w $Dst32RnUnprefixedHI */
46894 {
46895 { 0, 0, 0, 0 },
46896 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 46897 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9933 }
49f58d10
JB		 46898 },
46899/* indexl.w $Dst32AnUnprefixedHI */
46900 {
46901 { 0, 0, 0, 0 },
46902 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 46903 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x91b3 }
49f58d10
JB		 46904 },
46905/* indexl.w [$Dst32AnUnprefixed] */
46906 {
46907 { 0, 0, 0, 0 },
46908 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46909 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9133 }
49f58d10
JB		 46910 },
46911/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46912 {
46913 { 0, 0, 0, 0 },
46914 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46915 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x933300 }
49f58d10
JB		 46916 },
46917/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46918 {
46919 { 0, 0, 0, 0 },
46920 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46921 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95330000 }
49f58d10
JB		 46922 },
46923/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46924 {
46925 { 0, 0, 0, 0 },
46926 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 46927 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97330000 }
49f58d10
JB		 46928 },
46929/* indexl.w ${Dsp-16-u8}[sb] */
46930 {
46931 { 0, 0, 0, 0 },
46932 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 46933 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93b300 }
49f58d10
JB		 46934 },
46935/* indexl.w ${Dsp-16-u16}[sb] */
46936 {
46937 { 0, 0, 0, 0 },
46938 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 46939 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95b30000 }
49f58d10
JB		 46940 },
46941/* indexl.w ${Dsp-16-s8}[fb] */
46942 {
46943 { 0, 0, 0, 0 },
46944 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 46945 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93f300 }
49f58d10
JB		 46946 },
46947/* indexl.w ${Dsp-16-s16}[fb] */
46948 {
46949 { 0, 0, 0, 0 },
46950 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 46951 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95f30000 }
49f58d10
JB		 46952 },
46953/* indexl.w ${Dsp-16-u16} */
46954 {
46955 { 0, 0, 0, 0 },
46956 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 46957 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97f30000 }
49f58d10
JB		 46958 },
46959/* indexl.w ${Dsp-16-u24} */
46960 {
46961 { 0, 0, 0, 0 },
46962 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 46963 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97b30000 }
49f58d10
JB		 46964 },
46965/* indexl.b $Dst32RnUnprefixedQI */
46966 {
46967 { 0, 0, 0, 0 },
46968 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46969 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9823 }
46970 },
46971/* indexl.b $Dst32AnUnprefixedQI */
46972 {
46973 { 0, 0, 0, 0 },
46974 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46975 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x90a3 }
46976 },
46977/* indexl.b [$Dst32AnUnprefixed] */
46978 {
46979 { 0, 0, 0, 0 },
46980 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46981 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9023 }
46982 },
46983/* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46984 {
46985 { 0, 0, 0, 0 },
46986 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46987 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x922300 }
46988 },
46989/* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46990 {
46991 { 0, 0, 0, 0 },
46992 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46993 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94230000 }
46994 },
46995/* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46996 {
46997 { 0, 0, 0, 0 },
46998 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46999 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96230000 }
47000 },
47001/* indexl.b ${Dsp-16-u8}[sb] */
47002 {
47003 { 0, 0, 0, 0 },
47004 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47005 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92a300 }
47006 },
47007/* indexl.b ${Dsp-16-u16}[sb] */
47008 {
47009 { 0, 0, 0, 0 },
47010 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47011 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94a30000 }
47012 },
47013/* indexl.b ${Dsp-16-s8}[fb] */
47014 {
47015 { 0, 0, 0, 0 },
47016 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47017 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92e300 }
47018 },
47019/* indexl.b ${Dsp-16-s16}[fb] */
47020 {
47021 { 0, 0, 0, 0 },
47022 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47023 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94e30000 }
47024 },
47025/* indexl.b ${Dsp-16-u16} */
47026 {
47027 { 0, 0, 0, 0 },
47028 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47029 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96e30000 }
47030 },
47031/* indexl.b ${Dsp-16-u24} */
47032 {
47033 { 0, 0, 0, 0 },
47034 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47035 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96a30000 }
47036 },
47037/* indexbs.w $Dst32RnUnprefixedHI */
47038 {
47039 { 0, 0, 0, 0 },
47040 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 47041 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc913 }
49f58d10
JB		 47042 },
47043/* indexbs.w $Dst32AnUnprefixedHI */
47044 {
47045 { 0, 0, 0, 0 },
47046 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 47047 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc193 }
49f58d10
JB		 47048 },
47049/* indexbs.w [$Dst32AnUnprefixed] */
47050 {
47051 { 0, 0, 0, 0 },
47052 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47053 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc113 }
49f58d10
JB		 47054 },
47055/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47056 {
47057 { 0, 0, 0, 0 },
47058 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47059 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31300 }
49f58d10
JB		 47060 },
47061/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47062 {
47063 { 0, 0, 0, 0 },
47064 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47065 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5130000 }
49f58d10
JB		 47066 },
47067/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47068 {
47069 { 0, 0, 0, 0 },
47070 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47071 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7130000 }
49f58d10
JB		 47072 },
47073/* indexbs.w ${Dsp-16-u8}[sb] */
47074 {
47075 { 0, 0, 0, 0 },
47076 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 47077 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39300 }
49f58d10
JB		 47078 },
47079/* indexbs.w ${Dsp-16-u16}[sb] */
47080 {
47081 { 0, 0, 0, 0 },
47082 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 47083 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5930000 }
49f58d10
JB		 47084 },
47085/* indexbs.w ${Dsp-16-s8}[fb] */
47086 {
47087 { 0, 0, 0, 0 },
47088 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 47089 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3d300 }
49f58d10
JB		 47090 },
47091/* indexbs.w ${Dsp-16-s16}[fb] */
47092 {
47093 { 0, 0, 0, 0 },
47094 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 47095 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5d30000 }
49f58d10
JB		 47096 },
47097/* indexbs.w ${Dsp-16-u16} */
47098 {
47099 { 0, 0, 0, 0 },
47100 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 47101 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7d30000 }
49f58d10
JB		 47102 },
47103/* indexbs.w ${Dsp-16-u24} */
47104 {
47105 { 0, 0, 0, 0 },
47106 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 47107 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7930000 }
49f58d10
JB		 47108 },
47109/* indexbs.b $Dst32RnUnprefixedQI */
47110 {
47111 { 0, 0, 0, 0 },
47112 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47113 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc803 }
47114 },
47115/* indexbs.b $Dst32AnUnprefixedQI */
47116 {
47117 { 0, 0, 0, 0 },
47118 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47119 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc083 }
47120 },
47121/* indexbs.b [$Dst32AnUnprefixed] */
47122 {
47123 { 0, 0, 0, 0 },
47124 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47125 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc003 }
47126 },
47127/* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47128 {
47129 { 0, 0, 0, 0 },
47130 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47131 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20300 }
47132 },
47133/* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47134 {
47135 { 0, 0, 0, 0 },
47136 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47137 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4030000 }
47138 },
47139/* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47140 {
47141 { 0, 0, 0, 0 },
47142 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47143 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6030000 }
47144 },
47145/* indexbs.b ${Dsp-16-u8}[sb] */
47146 {
47147 { 0, 0, 0, 0 },
47148 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47149 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28300 }
47150 },
47151/* indexbs.b ${Dsp-16-u16}[sb] */
47152 {
47153 { 0, 0, 0, 0 },
47154 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47155 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4830000 }
47156 },
47157/* indexbs.b ${Dsp-16-s8}[fb] */
47158 {
47159 { 0, 0, 0, 0 },
47160 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47161 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c300 }
47162 },
47163/* indexbs.b ${Dsp-16-s16}[fb] */
47164 {
47165 { 0, 0, 0, 0 },
47166 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47167 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c30000 }
47168 },
47169/* indexbs.b ${Dsp-16-u16} */
47170 {
47171 { 0, 0, 0, 0 },
47172 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47173 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c30000 }
47174 },
47175/* indexbs.b ${Dsp-16-u24} */
47176 {
47177 { 0, 0, 0, 0 },
47178 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47179 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6830000 }
47180 },
47181/* indexbd.w $Dst32RnUnprefixedHI */
47182 {
47183 { 0, 0, 0, 0 },
47184 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 47185 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa913 }
49f58d10
JB		 47186 },
47187/* indexbd.w $Dst32AnUnprefixedHI */
47188 {
47189 { 0, 0, 0, 0 },
47190 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 47191 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa193 }
49f58d10
JB		 47192 },
47193/* indexbd.w [$Dst32AnUnprefixed] */
47194 {
47195 { 0, 0, 0, 0 },
47196 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47197 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa113 }
49f58d10
JB		 47198 },
47199/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47200 {
47201 { 0, 0, 0, 0 },
47202 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47203 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31300 }
49f58d10
JB		 47204 },
47205/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47206 {
47207 { 0, 0, 0, 0 },
47208 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47209 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5130000 }
49f58d10
JB		 47210 },
47211/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47212 {
47213 { 0, 0, 0, 0 },
47214 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47215 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7130000 }
49f58d10
JB		 47216 },
47217/* indexbd.w ${Dsp-16-u8}[sb] */
47218 {
47219 { 0, 0, 0, 0 },
47220 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 47221 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39300 }
49f58d10
JB		 47222 },
47223/* indexbd.w ${Dsp-16-u16}[sb] */
47224 {
47225 { 0, 0, 0, 0 },
47226 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 47227 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5930000 }
49f58d10
JB		 47228 },
47229/* indexbd.w ${Dsp-16-s8}[fb] */
47230 {
47231 { 0, 0, 0, 0 },
47232 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 47233 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3d300 }
49f58d10
JB		 47234 },
47235/* indexbd.w ${Dsp-16-s16}[fb] */
47236 {
47237 { 0, 0, 0, 0 },
47238 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 47239 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5d30000 }
49f58d10
JB		 47240 },
47241/* indexbd.w ${Dsp-16-u16} */
47242 {
47243 { 0, 0, 0, 0 },
47244 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 47245 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7d30000 }
49f58d10
JB		 47246 },
47247/* indexbd.w ${Dsp-16-u24} */
47248 {
47249 { 0, 0, 0, 0 },
47250 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 47251 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7930000 }
49f58d10
JB		 47252 },
47253/* indexbd.b $Dst32RnUnprefixedQI */
47254 {
47255 { 0, 0, 0, 0 },
47256 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47257 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa803 }
47258 },
47259/* indexbd.b $Dst32AnUnprefixedQI */
47260 {
47261 { 0, 0, 0, 0 },
47262 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47263 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa083 }
47264 },
47265/* indexbd.b [$Dst32AnUnprefixed] */
47266 {
47267 { 0, 0, 0, 0 },
47268 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47269 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa003 }
47270 },
47271/* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47272 {
47273 { 0, 0, 0, 0 },
47274 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47275 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20300 }
47276 },
47277/* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47278 {
47279 { 0, 0, 0, 0 },
47280 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47281 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4030000 }
47282 },
47283/* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47284 {
47285 { 0, 0, 0, 0 },
47286 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47287 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6030000 }
47288 },
47289/* indexbd.b ${Dsp-16-u8}[sb] */
47290 {
47291 { 0, 0, 0, 0 },
47292 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47293 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28300 }
47294 },
47295/* indexbd.b ${Dsp-16-u16}[sb] */
47296 {
47297 { 0, 0, 0, 0 },
47298 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47299 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4830000 }
47300 },
47301/* indexbd.b ${Dsp-16-s8}[fb] */
47302 {
47303 { 0, 0, 0, 0 },
47304 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47305 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2c300 }
47306 },
47307/* indexbd.b ${Dsp-16-s16}[fb] */
47308 {
47309 { 0, 0, 0, 0 },
47310 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47311 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4c30000 }
47312 },
47313/* indexbd.b ${Dsp-16-u16} */
47314 {
47315 { 0, 0, 0, 0 },
47316 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47317 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6c30000 }
47318 },
47319/* indexbd.b ${Dsp-16-u24} */
47320 {
47321 { 0, 0, 0, 0 },
47322 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47323 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6830000 }
47324 },
47325/* indexb.w $Dst32RnUnprefixedHI */
47326 {
47327 { 0, 0, 0, 0 },
47328 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
a1a280bb 47329 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8913 }
49f58d10
JB		 47330 },
47331/* indexb.w $Dst32AnUnprefixedHI */
47332 {
47333 { 0, 0, 0, 0 },
47334 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
a1a280bb 47335 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8193 }
49f58d10
JB		 47336 },
47337/* indexb.w [$Dst32AnUnprefixed] */
47338 {
47339 { 0, 0, 0, 0 },
47340 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47341 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8113 }
49f58d10
JB		 47342 },
47343/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47344 {
47345 { 0, 0, 0, 0 },
47346 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47347 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831300 }
49f58d10
JB		 47348 },
47349/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47350 {
47351 { 0, 0, 0, 0 },
47352 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47353 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85130000 }
49f58d10
JB		 47354 },
47355/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47356 {
47357 { 0, 0, 0, 0 },
47358 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 47359 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87130000 }
49f58d10
JB		 47360 },
47361/* indexb.w ${Dsp-16-u8}[sb] */
47362 {
47363 { 0, 0, 0, 0 },
47364 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 47365 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839300 }
49f58d10
JB		 47366 },
47367/* indexb.w ${Dsp-16-u16}[sb] */
47368 {
47369 { 0, 0, 0, 0 },
47370 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 47371 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85930000 }
49f58d10
JB		 47372 },
47373/* indexb.w ${Dsp-16-s8}[fb] */
47374 {
47375 { 0, 0, 0, 0 },
47376 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 47377 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83d300 }
49f58d10
JB		 47378 },
47379/* indexb.w ${Dsp-16-s16}[fb] */
47380 {
47381 { 0, 0, 0, 0 },
47382 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 47383 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85d30000 }
49f58d10
JB		 47384 },
47385/* indexb.w ${Dsp-16-u16} */
47386 {
47387 { 0, 0, 0, 0 },
47388 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
a1a280bb 47389 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87d30000 }
49f58d10
JB		 47390 },
47391/* indexb.w ${Dsp-16-u24} */
47392 {
47393 { 0, 0, 0, 0 },
47394 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
a1a280bb 47395 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87930000 }
49f58d10
JB		 47396 },
47397/* indexb.b $Dst32RnUnprefixedQI */
47398 {
47399 { 0, 0, 0, 0 },
47400 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47401 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8803 }
47402 },
47403/* indexb.b $Dst32AnUnprefixedQI */
47404 {
47405 { 0, 0, 0, 0 },
47406 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47407 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x8083 }
47408 },
47409/* indexb.b [$Dst32AnUnprefixed] */
47410 {
47411 { 0, 0, 0, 0 },
47412 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47413 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8003 }
47414 },
47415/* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47416 {
47417 { 0, 0, 0, 0 },
47418 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47419 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820300 }
47420 },
47421/* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47422 {
47423 { 0, 0, 0, 0 },
47424 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47425 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84030000 }
47426 },
47427/* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47428 {
47429 { 0, 0, 0, 0 },
47430 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47431 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86030000 }
47432 },
47433/* indexb.b ${Dsp-16-u8}[sb] */
47434 {
47435 { 0, 0, 0, 0 },
47436 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47437 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828300 }
47438 },
47439/* indexb.b ${Dsp-16-u16}[sb] */
47440 {
47441 { 0, 0, 0, 0 },
47442 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47443 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84830000 }
47444 },
47445/* indexb.b ${Dsp-16-s8}[fb] */
47446 {
47447 { 0, 0, 0, 0 },
47448 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47449 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c300 }
47450 },
47451/* indexb.b ${Dsp-16-s16}[fb] */
47452 {
47453 { 0, 0, 0, 0 },
47454 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47455 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c30000 }
47456 },
47457/* indexb.b ${Dsp-16-u16} */
47458 {
47459 { 0, 0, 0, 0 },
47460 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47461 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86c30000 }
47462 },
47463/* indexb.b ${Dsp-16-u24} */
47464 {
47465 { 0, 0, 0, 0 },
47466 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47467 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86830000 }
47468 },
47469/* inc.w $Dst32RnUnprefixedHI */
47470 {
47471 { 0, 0, 0, 0 },
47472 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47473 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa90e }
47474 },
47475/* inc.w $Dst32AnUnprefixedHI */
47476 {
47477 { 0, 0, 0, 0 },
47478 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47479 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18e }
47480 },
47481/* inc.w [$Dst32AnUnprefixed] */
47482 {
47483 { 0, 0, 0, 0 },
47484 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47485 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa10e }
47486 },
47487/* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47488 {
47489 { 0, 0, 0, 0 },
47490 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47491 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30e00 }
47492 },
47493/* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47494 {
47495 { 0, 0, 0, 0 },
47496 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47497 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50e0000 }
47498 },
47499/* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47500 {
47501 { 0, 0, 0, 0 },
47502 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47503 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70e0000 }
47504 },
47505/* inc.w ${Dsp-16-u8}[sb] */
47506 {
47507 { 0, 0, 0, 0 },
47508 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47509 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38e00 }
47510 },
47511/* inc.w ${Dsp-16-u16}[sb] */
47512 {
47513 { 0, 0, 0, 0 },
47514 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47515 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58e0000 }
47516 },
47517/* inc.w ${Dsp-16-s8}[fb] */
47518 {
47519 { 0, 0, 0, 0 },
47520 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47521 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ce00 }
47522 },
47523/* inc.w ${Dsp-16-s16}[fb] */
47524 {
47525 { 0, 0, 0, 0 },
47526 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47527 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ce0000 }
47528 },
47529/* inc.w ${Dsp-16-u16} */
47530 {
47531 { 0, 0, 0, 0 },
47532 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47533 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ce0000 }
47534 },
47535/* inc.w ${Dsp-16-u24} */
47536 {
47537 { 0, 0, 0, 0 },
47538 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47539 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa78e0000 }
47540 },
47541/* inc.b $Dst32RnUnprefixedQI */
47542 {
47543 { 0, 0, 0, 0 },
47544 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47545 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa80e }
47546 },
47547/* inc.b $Dst32AnUnprefixedQI */
47548 {
47549 { 0, 0, 0, 0 },
47550 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47551 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa08e }
47552 },
47553/* inc.b [$Dst32AnUnprefixed] */
47554 {
47555 { 0, 0, 0, 0 },
47556 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47557 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa00e }
47558 },
47559/* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47560 {
47561 { 0, 0, 0, 0 },
47562 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47563 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20e00 }
47564 },
47565/* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47566 {
47567 { 0, 0, 0, 0 },
47568 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47569 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40e0000 }
47570 },
47571/* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47572 {
47573 { 0, 0, 0, 0 },
47574 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47575 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60e0000 }
47576 },
47577/* inc.b ${Dsp-16-u8}[sb] */
47578 {
47579 { 0, 0, 0, 0 },
47580 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47581 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28e00 }
47582 },
47583/* inc.b ${Dsp-16-u16}[sb] */
47584 {
47585 { 0, 0, 0, 0 },
47586 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47587 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48e0000 }
47588 },
47589/* inc.b ${Dsp-16-s8}[fb] */
47590 {
47591 { 0, 0, 0, 0 },
47592 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47593 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ce00 }
47594 },
47595/* inc.b ${Dsp-16-s16}[fb] */
47596 {
47597 { 0, 0, 0, 0 },
47598 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47599 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ce0000 }
47600 },
47601/* inc.b ${Dsp-16-u16} */
47602 {
47603 { 0, 0, 0, 0 },
47604 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47605 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ce0000 }
47606 },
47607/* inc.b ${Dsp-16-u24} */
47608 {
47609 { 0, 0, 0, 0 },
47610 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47611 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa68e0000 }
47612 },
47613/* inc.b r0l */
47614 {
47615 { 0, 0, 0, 0 },
47616 { { MNEM, ' ', 'r', '0', 'l', 0 } },
47617 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xa4 }
47618 },
47619/* inc.b r0h */
47620 {
47621 { 0, 0, 0, 0 },
47622 { { MNEM, ' ', 'r', '0', 'h', 0 } },
47623 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xa3 }
47624 },
47625/* inc.b ${Dsp-8-u8}[sb] */
47626 {
47627 { 0, 0, 0, 0 },
47628 { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
47629 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xa500 }
47630 },
47631/* inc.b ${Dsp-8-s8}[fb] */
47632 {
47633 { 0, 0, 0, 0 },
47634 { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
47635 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xa600 }
47636 },
47637/* inc.b ${Dsp-8-u16} */
47638 {
47639 { 0, 0, 0, 0 },
47640 { { MNEM, ' ', OP (DSP_8_U16), 0 } },
47641 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xa70000 }
47642 },
47643/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
47644 {
47645 { 0, 0, 0, 0 },
47646 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
47647 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990000 }
47648 },
47649/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
47650 {
47651 { 0, 0, 0, 0 },
47652 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
47653 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992000 }
47654 },
47655/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
47656 {
47657 { 0, 0, 0, 0 },
47658 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
47659 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993000 }
47660 },
47661/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
47662 {
47663 { 0, 0, 0, 0 },
47664 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
47665 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918000 }
47666 },
47667/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
47668 {
47669 { 0, 0, 0, 0 },
47670 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
47671 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a000 }
47672 },
47673/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
47674 {
47675 { 0, 0, 0, 0 },
47676 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
47677 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b000 }
47678 },
47679/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
47680 {
47681 { 0, 0, 0, 0 },
47682 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47683 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910000 }
47684 },
47685/* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
47686 {
47687 { 0, 0, 0, 0 },
47688 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47689 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912000 }
47690 },
47691/* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
47692 {
47693 { 0, 0, 0, 0 },
47694 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47695 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913000 }
47696 },
47697/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
47698 {
47699 { 0, 0, 0, 0 },
47700 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47701 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93000000 }
47702 },
47703/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
47704 {
47705 { 0, 0, 0, 0 },
47706 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47707 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93200000 }
47708 },
47709/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
47710 {
47711 { 0, 0, 0, 0 },
47712 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47713 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93300000 }
47714 },
47715/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
47716 {
47717 { 0, 0, 0, 0 },
47718 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47719 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95000000 }
47720 },
47721/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
47722 {
47723 { 0, 0, 0, 0 },
47724 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47725 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95200000 }
47726 },
47727/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
47728 {
47729 { 0, 0, 0, 0 },
47730 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47731 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95300000 }
47732 },
47733/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
47734 {
47735 { 0, 0, 0, 0 },
47736 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47737 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97000000 }
47738 },
47739/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
47740 {
47741 { 0, 0, 0, 0 },
47742 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47743 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97200000 }
47744 },
47745/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
47746 {
47747 { 0, 0, 0, 0 },
47748 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47749 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97300000 }
47750 },
47751/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
47752 {
47753 { 0, 0, 0, 0 },
47754 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
47755 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93800000 }
47756 },
47757/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
47758 {
47759 { 0, 0, 0, 0 },
47760 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
47761 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a00000 }
47762 },
47763/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
47764 {
47765 { 0, 0, 0, 0 },
47766 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
47767 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b00000 }
47768 },
47769/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
47770 {
47771 { 0, 0, 0, 0 },
47772 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
47773 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95800000 }
47774 },
47775/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
47776 {
47777 { 0, 0, 0, 0 },
47778 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
47779 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a00000 }
47780 },
47781/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
47782 {
47783 { 0, 0, 0, 0 },
47784 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
47785 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b00000 }
47786 },
47787/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
47788 {
47789 { 0, 0, 0, 0 },
47790 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
47791 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c00000 }
47792 },
47793/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
47794 {
47795 { 0, 0, 0, 0 },
47796 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
47797 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e00000 }
47798 },
47799/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
47800 {
47801 { 0, 0, 0, 0 },
47802 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
47803 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f00000 }
47804 },
47805/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
47806 {
47807 { 0, 0, 0, 0 },
47808 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
47809 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c00000 }
47810 },
47811/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
47812 {
47813 { 0, 0, 0, 0 },
47814 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
47815 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e00000 }
47816 },
47817/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
47818 {
47819 { 0, 0, 0, 0 },
47820 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
47821 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f00000 }
47822 },
47823/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
47824 {
47825 { 0, 0, 0, 0 },
47826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
47827 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c00000 }
47828 },
47829/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
47830 {
47831 { 0, 0, 0, 0 },
47832 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
47833 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e00000 }
47834 },
47835/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
47836 {
47837 { 0, 0, 0, 0 },
47838 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
47839 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f00000 }
47840 },
47841/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
47842 {
47843 { 0, 0, 0, 0 },
47844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
47845 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97800000 }
47846 },
47847/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
47848 {
47849 { 0, 0, 0, 0 },
47850 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
47851 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a00000 }
47852 },
47853/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
47854 {
47855 { 0, 0, 0, 0 },
47856 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
47857 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b00000 }
47858 },
47859/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
47860 {
47861 { 0, 0, 0, 0 },
47862 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
47863 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9000000 }
47864 },
47865/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
47866 {
47867 { 0, 0, 0, 0 },
47868 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
47869 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9200000 }
47870 },
47871/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
47872 {
47873 { 0, 0, 0, 0 },
47874 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
47875 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9300000 }
47876 },
47877/* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
47878 {
47879 { 0, 0, 0, 0 },
47880 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
47881 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9300000 }
47882 },
47883/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
47884 {
47885 { 0, 0, 0, 0 },
47886 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
47887 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1800000 }
47888 },
47889/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
47890 {
47891 { 0, 0, 0, 0 },
47892 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
47893 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a00000 }
47894 },
47895/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
47896 {
47897 { 0, 0, 0, 0 },
47898 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
47899 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b00000 }
47900 },
47901/* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
47902 {
47903 { 0, 0, 0, 0 },
47904 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
47905 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b00000 }
47906 },
47907/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
47908 {
47909 { 0, 0, 0, 0 },
47910 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47911 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1000000 }
47912 },
47913/* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
47914 {
47915 { 0, 0, 0, 0 },
47916 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47917 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1200000 }
47918 },
47919/* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
47920 {
47921 { 0, 0, 0, 0 },
47922 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47923 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1300000 }
47924 },
47925/* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
47926 {
47927 { 0, 0, 0, 0 },
47928 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47929 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1300000 }
47930 },
47931/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
47932 {
47933 { 0, 0, 0, 0 },
47934 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47935 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3000000 }
47936 },
47937/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
47938 {
47939 { 0, 0, 0, 0 },
47940 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47941 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3200000 }
47942 },
47943/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
47944 {
47945 { 0, 0, 0, 0 },
47946 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47947 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3300000 }
47948 },
47949/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
47950 {
47951 { 0, 0, 0, 0 },
47952 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47953 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3300000 }
47954 },
47955/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
47956 {
47957 { 0, 0, 0, 0 },
47958 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47959 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5000000 }
47960 },
47961/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
47962 {
47963 { 0, 0, 0, 0 },
47964 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47965 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5200000 }
47966 },
47967/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
47968 {
47969 { 0, 0, 0, 0 },
47970 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47971 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5300000 }
47972 },
47973/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
47974 {
47975 { 0, 0, 0, 0 },
47976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47977 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5300000 }
47978 },
47979/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
47980 {
47981 { 0, 0, 0, 0 },
47982 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47983 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7000000 }
47984 },
47985/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
47986 {
47987 { 0, 0, 0, 0 },
47988 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47989 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7200000 }
47990 },
47991/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
47992 {
47993 { 0, 0, 0, 0 },
47994 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47995 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7300000 }
47996 },
47997/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
47998 {
47999 { 0, 0, 0, 0 },
48000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48001 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7300000 }
48002 },
48003/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
48004 {
48005 { 0, 0, 0, 0 },
48006 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48007 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3800000 }
48008 },
48009/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
48010 {
48011 { 0, 0, 0, 0 },
48012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48013 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a00000 }
48014 },
48015/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
48016 {
48017 { 0, 0, 0, 0 },
48018 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48019 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b00000 }
48020 },
48021/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
48022 {
48023 { 0, 0, 0, 0 },
48024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48025 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b00000 }
48026 },
48027/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
48028 {
48029 { 0, 0, 0, 0 },
48030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48031 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5800000 }
48032 },
48033/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
48034 {
48035 { 0, 0, 0, 0 },
48036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48037 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a00000 }
48038 },
48039/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
48040 {
48041 { 0, 0, 0, 0 },
48042 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48043 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b00000 }
48044 },
48045/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
48046 {
48047 { 0, 0, 0, 0 },
48048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48049 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b00000 }
48050 },
48051/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
48052 {
48053 { 0, 0, 0, 0 },
48054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48055 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c00000 }
48056 },
48057/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
48058 {
48059 { 0, 0, 0, 0 },
48060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48061 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e00000 }
48062 },
48063/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
48064 {
48065 { 0, 0, 0, 0 },
48066 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48067 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f00000 }
48068 },
48069/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
48070 {
48071 { 0, 0, 0, 0 },
48072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48073 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f00000 }
48074 },
48075/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
48076 {
48077 { 0, 0, 0, 0 },
48078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48079 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c00000 }
48080 },
48081/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
48082 {
48083 { 0, 0, 0, 0 },
48084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48085 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e00000 }
48086 },
48087/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
48088 {
48089 { 0, 0, 0, 0 },
48090 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48091 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f00000 }
48092 },
48093/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
48094 {
48095 { 0, 0, 0, 0 },
48096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48097 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f00000 }
48098 },
48099/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
48100 {
48101 { 0, 0, 0, 0 },
48102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
48103 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c00000 }
48104 },
48105/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
48106 {
48107 { 0, 0, 0, 0 },
48108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
48109 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e00000 }
48110 },
48111/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
48112 {
48113 { 0, 0, 0, 0 },
48114 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
48115 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f00000 }
48116 },
48117/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
48118 {
48119 { 0, 0, 0, 0 },
48120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
48121 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f00000 }
48122 },
48123/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
48124 {
48125 { 0, 0, 0, 0 },
48126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
48127 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7800000 }
48128 },
48129/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
48130 {
48131 { 0, 0, 0, 0 },
48132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
48133 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a00000 }
48134 },
48135/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
48136 {
48137 { 0, 0, 0, 0 },
48138 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
48139 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b00000 }
48140 },
48141/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
48142 {
48143 { 0, 0, 0, 0 },
48144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
48145 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b00000 }
48146 },
48147/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48148 {
48149 { 0, 0, 0, 0 },
48150 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48151 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9000000 }
48152 },
48153/* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
48154 {
48155 { 0, 0, 0, 0 },
48156 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48157 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9200000 }
48158 },
48159/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48160 {
48161 { 0, 0, 0, 0 },
48162 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48163 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1800000 }
48164 },
48165/* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
48166 {
48167 { 0, 0, 0, 0 },
48168 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48169 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a00000 }
48170 },
48171/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48172 {
48173 { 0, 0, 0, 0 },
48174 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48175 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1000000 }
48176 },
48177/* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
48178 {
48179 { 0, 0, 0, 0 },
48180 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48181 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1200000 }
48182 },
48183/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
48184 {
48185 { 0, 0, 0, 0 },
48186 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48187 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3000000 }
48188 },
48189/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
48190 {
48191 { 0, 0, 0, 0 },
48192 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48193 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3200000 }
48194 },
48195/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
48196 {
48197 { 0, 0, 0, 0 },
48198 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48199 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5000000 }
48200 },
48201/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
48202 {
48203 { 0, 0, 0, 0 },
48204 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48205 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5200000 }
48206 },
48207/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
48208 {
48209 { 0, 0, 0, 0 },
48210 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48211 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7000000 }
48212 },
48213/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
48214 {
48215 { 0, 0, 0, 0 },
48216 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48217 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7200000 }
48218 },
48219/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
48220 {
48221 { 0, 0, 0, 0 },
48222 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
48223 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3800000 }
48224 },
48225/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
48226 {
48227 { 0, 0, 0, 0 },
48228 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
48229 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a00000 }
48230 },
48231/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
48232 {
48233 { 0, 0, 0, 0 },
48234 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
48235 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5800000 }
48236 },
48237/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
48238 {
48239 { 0, 0, 0, 0 },
48240 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
48241 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a00000 }
48242 },
48243/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
48244 {
48245 { 0, 0, 0, 0 },
48246 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
48247 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c00000 }
48248 },
48249/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
48250 {
48251 { 0, 0, 0, 0 },
48252 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
48253 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e00000 }
48254 },
48255/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
48256 {
48257 { 0, 0, 0, 0 },
48258 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
48259 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c00000 }
48260 },
48261/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
48262 {
48263 { 0, 0, 0, 0 },
48264 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
48265 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e00000 }
48266 },
48267/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
48268 {
48269 { 0, 0, 0, 0 },
48270 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
48271 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c00000 }
48272 },
48273/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
48274 {
48275 { 0, 0, 0, 0 },
48276 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
48277 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e00000 }
48278 },
48279/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
48280 {
48281 { 0, 0, 0, 0 },
48282 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
48283 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7800000 }
48284 },
48285/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
48286 {
48287 { 0, 0, 0, 0 },
48288 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
48289 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a00000 }
48290 },
48291/* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
48292 {
48293 { 0, 0, 0, 0 },
48294 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48295 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc900 }
48296 },
48297/* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
48298 {
48299 { 0, 0, 0, 0 },
48300 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48301 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8920 }
48302 },
48303/* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48304 {
48305 { 0, 0, 0, 0 },
48306 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48307 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8900 }
48308 },
48309/* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
48310 {
48311 { 0, 0, 0, 0 },
48312 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48313 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc180 }
48314 },
48315/* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
48316 {
48317 { 0, 0, 0, 0 },
48318 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48319 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a0 }
48320 },
48321/* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48322 {
48323 { 0, 0, 0, 0 },
48324 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48325 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8180 }
48326 },
48327/* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
48328 {
48329 { 0, 0, 0, 0 },
48330 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48331 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc100 }
48332 },
48333/* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
48334 {
48335 { 0, 0, 0, 0 },
48336 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48337 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8120 }
48338 },
48339/* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48340 {
48341 { 0, 0, 0, 0 },
48342 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48343 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8100 }
48344 },
48345/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48346 {
48347 { 0, 0, 0, 0 },
48348 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48349 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30000 }
48350 },
48351/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48352 {
48353 { 0, 0, 0, 0 },
48354 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48355 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832000 }
48356 },
48357/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
48358 {
48359 { 0, 0, 0, 0 },
48360 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48361 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830000 }
48362 },
48363/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48364 {
48365 { 0, 0, 0, 0 },
48366 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48367 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5000000 }
48368 },
48369/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48370 {
48371 { 0, 0, 0, 0 },
48372 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48373 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85200000 }
48374 },
48375/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
48376 {
48377 { 0, 0, 0, 0 },
48378 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48379 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85000000 }
48380 },
48381/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
48382 {
48383 { 0, 0, 0, 0 },
48384 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48385 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7000000 }
48386 },
48387/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
48388 {
48389 { 0, 0, 0, 0 },
48390 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48391 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87200000 }
48392 },
48393/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
48394 {
48395 { 0, 0, 0, 0 },
48396 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48397 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87000000 }
48398 },
48399/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
48400 {
48401 { 0, 0, 0, 0 },
48402 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48403 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38000 }
48404 },
48405/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
48406 {
48407 { 0, 0, 0, 0 },
48408 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48409 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a000 }
48410 },
48411/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
48412 {
48413 { 0, 0, 0, 0 },
48414 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48415 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838000 }
48416 },
48417/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
48418 {
48419 { 0, 0, 0, 0 },
48420 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48421 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5800000 }
48422 },
48423/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
48424 {
48425 { 0, 0, 0, 0 },
48426 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48427 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a00000 }
48428 },
48429/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
48430 {
48431 { 0, 0, 0, 0 },
48432 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48433 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85800000 }
48434 },
48435/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
48436 {
48437 { 0, 0, 0, 0 },
48438 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48439 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c000 }
48440 },
48441/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
48442 {
48443 { 0, 0, 0, 0 },
48444 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48445 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e000 }
48446 },
48447/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
48448 {
48449 { 0, 0, 0, 0 },
48450 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48451 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c000 }
48452 },
48453/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
48454 {
48455 { 0, 0, 0, 0 },
48456 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48457 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c00000 }
48458 },
48459/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
48460 {
48461 { 0, 0, 0, 0 },
48462 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48463 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e00000 }
48464 },
48465/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
48466 {
48467 { 0, 0, 0, 0 },
48468 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48469 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c00000 }
48470 },
48471/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
48472 {
48473 { 0, 0, 0, 0 },
48474 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
48475 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c00000 }
48476 },
48477/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
48478 {
48479 { 0, 0, 0, 0 },
48480 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
48481 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e00000 }
48482 },
48483/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
48484 {
48485 { 0, 0, 0, 0 },
48486 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
48487 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c00000 }
48488 },
48489/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
48490 {
48491 { 0, 0, 0, 0 },
48492 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
48493 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7800000 }
48494 },
48495/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
48496 {
48497 { 0, 0, 0, 0 },
48498 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
48499 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a00000 }
48500 },
48501/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
48502 {
48503 { 0, 0, 0, 0 },
48504 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
48505 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87800000 }
48506 },
48507/* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48508 {
48509 { 0, 0, 0, 0 },
48510 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
48511 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2f000000 }
48512 },
48513/* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48514 {
48515 { 0, 0, 0, 0 },
48516 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
48517 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3f000000 }
48518 },
48519/* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48520 {
48521 { 0, 0, 0, 0 },
48522 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
48523 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1f000000 }
48524 },
48525/* sub.w${S} #${Imm-8-HI},r0 */
48526 {
48527 { 0, 0, 0, 0 },
48528 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
48529 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xf0000 }
48530 },
48531/* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48532 {
48533 { 0, 0, 0, 0 },
48534 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
48535 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2e0000 }
48536 },
48537/* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48538 {
48539 { 0, 0, 0, 0 },
48540 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
48541 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3e0000 }
48542 },
48543/* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48544 {
48545 { 0, 0, 0, 0 },
48546 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
48547 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1e000000 }
48548 },
48549/* sub.b${S} #${Imm-8-QI},r0l */
48550 {
48551 { 0, 0, 0, 0 },
48552 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
48553 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xe00 }
48554 },
48555/* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
48556 {
48557 { 0, 0, 0, 0 },
48558 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48559 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x98310000 }
48560 },
48561/* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
48562 {
48563 { 0, 0, 0, 0 },
48564 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48565 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90b10000 }
48566 },
48567/* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
48568 {
48569 { 0, 0, 0, 0 },
48570 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48571 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x90310000 }
48572 },
48573/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
48574 {
48575 { 0, 0, 0, 0 },
48576 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48577 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92310000 }
48578 },
48579/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
48580 {
48581 { 0, 0, 0, 0 },
48582 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48583 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92b10000 }
48584 },
48585/* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
48586 {
48587 { 0, 0, 0, 0 },
48588 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48589 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92f10000 }
48590 },
48591/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
48592 {
48593 { 0, 0, 0, 0 },
48594 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48595 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94310000 }
48596 },
48597/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
48598 {
48599 { 0, 0, 0, 0 },
48600 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48601 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94b10000 }
48602 },
48603/* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
48604 {
48605 { 0, 0, 0, 0 },
48606 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48607 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94f10000 }
48608 },
48609/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
48610 {
48611 { 0, 0, 0, 0 },
48612 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
48613 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96f10000 }
48614 },
48615/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
48616 {
48617 { 0, 0, 0, 0 },
48618 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48619 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96310000 }
48620 },
48621/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
48622 {
48623 { 0, 0, 0, 0 },
48624 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
48625 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96b10000 }
48626 },
48627/* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
48628 {
48629 { 0, 0, 0, 0 },
48630 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
48631 & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x28 }
48632 },
48633/* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
48634 {
48635 { 0, 0, 0, 0 },
48636 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
48637 & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2900 }
48638 },
48639/* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
48640 {
48641 { 0, 0, 0, 0 },
48642 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
48643 & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2a00 }
48644 },
48645/* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
48646 {
48647 { 0, 0, 0, 0 },
48648 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
48649 & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x2b0000 }
48650 },
48651/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48652 {
48653 { 0, 0, 0, 0 },
48654 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
48655 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990a00 }
48656 },
48657/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
48658 {
48659 { 0, 0, 0, 0 },
48660 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
48661 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992a00 }
48662 },
48663/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
48664 {
48665 { 0, 0, 0, 0 },
48666 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
48667 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993a00 }
48668 },
48669/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48670 {
48671 { 0, 0, 0, 0 },
48672 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
48673 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918a00 }
48674 },
48675/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
48676 {
48677 { 0, 0, 0, 0 },
48678 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
48679 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91aa00 }
48680 },
48681/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
48682 {
48683 { 0, 0, 0, 0 },
48684 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
48685 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ba00 }
48686 },
48687/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48688 {
48689 { 0, 0, 0, 0 },
48690 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48691 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910a00 }
48692 },
48693/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48694 {
48695 { 0, 0, 0, 0 },
48696 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48697 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912a00 }
48698 },
48699/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48700 {
48701 { 0, 0, 0, 0 },
48702 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48703 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913a00 }
48704 },
48705/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48706 {
48707 { 0, 0, 0, 0 },
48708 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48709 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930a0000 }
48710 },
48711/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48712 {
48713 { 0, 0, 0, 0 },
48714 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48715 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932a0000 }
48716 },
48717/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48718 {
48719 { 0, 0, 0, 0 },
48720 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48721 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933a0000 }
48722 },
48723/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48724 {
48725 { 0, 0, 0, 0 },
48726 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48727 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950a0000 }
48728 },
48729/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48730 {
48731 { 0, 0, 0, 0 },
48732 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48733 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952a0000 }
48734 },
48735/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48736 {
48737 { 0, 0, 0, 0 },
48738 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48739 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953a0000 }
48740 },
48741/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48742 {
48743 { 0, 0, 0, 0 },
48744 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48745 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970a0000 }
48746 },
48747/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48748 {
48749 { 0, 0, 0, 0 },
48750 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48751 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972a0000 }
48752 },
48753/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48754 {
48755 { 0, 0, 0, 0 },
48756 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48757 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973a0000 }
48758 },
48759/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48760 {
48761 { 0, 0, 0, 0 },
48762 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48763 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938a0000 }
48764 },
48765/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48766 {
48767 { 0, 0, 0, 0 },
48768 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48769 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93aa0000 }
48770 },
48771/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48772 {
48773 { 0, 0, 0, 0 },
48774 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48775 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ba0000 }
48776 },
48777/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48778 {
48779 { 0, 0, 0, 0 },
48780 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48781 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958a0000 }
48782 },
48783/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48784 {
48785 { 0, 0, 0, 0 },
48786 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48787 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95aa0000 }
48788 },
48789/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48790 {
48791 { 0, 0, 0, 0 },
48792 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48793 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ba0000 }
48794 },
48795/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48796 {
48797 { 0, 0, 0, 0 },
48798 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48799 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ca0000 }
48800 },
48801/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48802 {
48803 { 0, 0, 0, 0 },
48804 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48805 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ea0000 }
48806 },
48807/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48808 {
48809 { 0, 0, 0, 0 },
48810 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48811 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fa0000 }
48812 },
48813/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48814 {
48815 { 0, 0, 0, 0 },
48816 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48817 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ca0000 }
48818 },
48819/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48820 {
48821 { 0, 0, 0, 0 },
48822 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48823 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ea0000 }
48824 },
48825/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48826 {
48827 { 0, 0, 0, 0 },
48828 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48829 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fa0000 }
48830 },
48831/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48832 {
48833 { 0, 0, 0, 0 },
48834 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
48835 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ca0000 }
48836 },
48837/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48838 {
48839 { 0, 0, 0, 0 },
48840 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
48841 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ea0000 }
48842 },
48843/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48844 {
48845 { 0, 0, 0, 0 },
48846 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
48847 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fa0000 }
48848 },
48849/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48850 {
48851 { 0, 0, 0, 0 },
48852 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
48853 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978a0000 }
48854 },
48855/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48856 {
48857 { 0, 0, 0, 0 },
48858 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
48859 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97aa0000 }
48860 },
48861/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48862 {
48863 { 0, 0, 0, 0 },
48864 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
48865 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ba0000 }
48866 },
48867/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48868 {
48869 { 0, 0, 0, 0 },
48870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
48871 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90a0000 }
48872 },
48873/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
48874 {
48875 { 0, 0, 0, 0 },
48876 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
48877 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92a0000 }
48878 },
48879/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
48880 {
48881 { 0, 0, 0, 0 },
48882 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
48883 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93a0000 }
48884 },
48885/* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
48886 {
48887 { 0, 0, 0, 0 },
48888 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
48889 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93a0000 }
48890 },
48891/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48892 {
48893 { 0, 0, 0, 0 },
48894 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
48895 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18a0000 }
48896 },
48897/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
48898 {
48899 { 0, 0, 0, 0 },
48900 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
48901 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1aa0000 }
48902 },
48903/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
48904 {
48905 { 0, 0, 0, 0 },
48906 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
48907 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ba0000 }
48908 },
48909/* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
48910 {
48911 { 0, 0, 0, 0 },
48912 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
48913 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ba0000 }
48914 },
48915/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48916 {
48917 { 0, 0, 0, 0 },
48918 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48919 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10a0000 }
48920 },
48921/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
48922 {
48923 { 0, 0, 0, 0 },
48924 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48925 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12a0000 }
48926 },
48927/* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
48928 {
48929 { 0, 0, 0, 0 },
48930 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48931 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13a0000 }
48932 },
48933/* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
48934 {
48935 { 0, 0, 0, 0 },
48936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48937 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13a0000 }
48938 },
48939/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48940 {
48941 { 0, 0, 0, 0 },
48942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48943 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30a0000 }
48944 },
48945/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48946 {
48947 { 0, 0, 0, 0 },
48948 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48949 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32a0000 }
48950 },
48951/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48952 {
48953 { 0, 0, 0, 0 },
48954 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48955 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33a0000 }
48956 },
48957/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
48958 {
48959 { 0, 0, 0, 0 },
48960 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48961 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33a0000 }
48962 },
48963/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48964 {
48965 { 0, 0, 0, 0 },
48966 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48967 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50a0000 }
48968 },
48969/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48970 {
48971 { 0, 0, 0, 0 },
48972 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48973 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52a0000 }
48974 },
48975/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48976 {
48977 { 0, 0, 0, 0 },
48978 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48979 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53a0000 }
48980 },
48981/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
48982 {
48983 { 0, 0, 0, 0 },
48984 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48985 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53a0000 }
48986 },
48987/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48988 {
48989 { 0, 0, 0, 0 },
48990 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48991 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70a0000 }
48992 },
48993/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48994 {
48995 { 0, 0, 0, 0 },
48996 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48997 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72a0000 }
48998 },
48999/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49000 {
49001 { 0, 0, 0, 0 },
49002 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49003 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73a0000 }
49004 },
49005/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49006 {
49007 { 0, 0, 0, 0 },
49008 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49009 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73a0000 }
49010 },
49011/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49012 {
49013 { 0, 0, 0, 0 },
49014 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49015 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38a0000 }
49016 },
49017/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49018 {
49019 { 0, 0, 0, 0 },
49020 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49021 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3aa0000 }
49022 },
49023/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49024 {
49025 { 0, 0, 0, 0 },
49026 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49027 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ba0000 }
49028 },
49029/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49030 {
49031 { 0, 0, 0, 0 },
49032 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49033 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3ba0000 }
49034 },
49035/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49036 {
49037 { 0, 0, 0, 0 },
49038 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49039 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58a0000 }
49040 },
49041/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49042 {
49043 { 0, 0, 0, 0 },
49044 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49045 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5aa0000 }
49046 },
49047/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49048 {
49049 { 0, 0, 0, 0 },
49050 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49051 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ba0000 }
49052 },
49053/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49054 {
49055 { 0, 0, 0, 0 },
49056 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49057 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5ba0000 }
49058 },
49059/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49060 {
49061 { 0, 0, 0, 0 },
49062 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49063 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ca0000 }
49064 },
49065/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49066 {
49067 { 0, 0, 0, 0 },
49068 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49069 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ea0000 }
49070 },
49071/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49072 {
49073 { 0, 0, 0, 0 },
49074 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49075 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fa0000 }
49076 },
49077/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49078 {
49079 { 0, 0, 0, 0 },
49080 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49081 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fa0000 }
49082 },
49083/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49084 {
49085 { 0, 0, 0, 0 },
49086 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49087 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ca0000 }
49088 },
49089/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49090 {
49091 { 0, 0, 0, 0 },
49092 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49093 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ea0000 }
49094 },
49095/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49096 {
49097 { 0, 0, 0, 0 },
49098 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49099 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fa0000 }
49100 },
49101/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49102 {
49103 { 0, 0, 0, 0 },
49104 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49105 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fa0000 }
49106 },
49107/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49108 {
49109 { 0, 0, 0, 0 },
49110 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49111 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ca0000 }
49112 },
49113/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49114 {
49115 { 0, 0, 0, 0 },
49116 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49117 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ea0000 }
49118 },
49119/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49120 {
49121 { 0, 0, 0, 0 },
49122 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49123 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fa0000 }
49124 },
49125/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
49126 {
49127 { 0, 0, 0, 0 },
49128 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
49129 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fa0000 }
49130 },
49131/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49132 {
49133 { 0, 0, 0, 0 },
49134 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49135 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78a0000 }
49136 },
49137/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49138 {
49139 { 0, 0, 0, 0 },
49140 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49141 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7aa0000 }
49142 },
49143/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49144 {
49145 { 0, 0, 0, 0 },
49146 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49147 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ba0000 }
49148 },
49149/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
49150 {
49151 { 0, 0, 0, 0 },
49152 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
49153 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7ba0000 }
49154 },
49155/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49156 {
49157 { 0, 0, 0, 0 },
49158 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49159 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90a0000 }
49160 },
49161/* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
49162 {
49163 { 0, 0, 0, 0 },
49164 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49165 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92a0000 }
49166 },
49167/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49168 {
49169 { 0, 0, 0, 0 },
49170 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49171 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18a0000 }
49172 },
49173/* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
49174 {
49175 { 0, 0, 0, 0 },
49176 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49177 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1aa0000 }
49178 },
49179/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49180 {
49181 { 0, 0, 0, 0 },
49182 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49183 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10a0000 }
49184 },
49185/* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49186 {
49187 { 0, 0, 0, 0 },
49188 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49189 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12a0000 }
49190 },
49191/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49192 {
49193 { 0, 0, 0, 0 },
49194 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49195 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30a0000 }
49196 },
49197/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49198 {
49199 { 0, 0, 0, 0 },
49200 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49201 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32a0000 }
49202 },
49203/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49204 {
49205 { 0, 0, 0, 0 },
49206 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49207 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50a0000 }
49208 },
49209/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49210 {
49211 { 0, 0, 0, 0 },
49212 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49213 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52a0000 }
49214 },
49215/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49216 {
49217 { 0, 0, 0, 0 },
49218 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49219 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70a0000 }
49220 },
49221/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49222 {
49223 { 0, 0, 0, 0 },
49224 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49225 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72a0000 }
49226 },
49227/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49228 {
49229 { 0, 0, 0, 0 },
49230 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49231 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38a0000 }
49232 },
49233/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49234 {
49235 { 0, 0, 0, 0 },
49236 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49237 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3aa0000 }
49238 },
49239/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49240 {
49241 { 0, 0, 0, 0 },
49242 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49243 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58a0000 }
49244 },
49245/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49246 {
49247 { 0, 0, 0, 0 },
49248 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49249 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5aa0000 }
49250 },
49251/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49252 {
49253 { 0, 0, 0, 0 },
49254 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49255 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ca0000 }
49256 },
49257/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49258 {
49259 { 0, 0, 0, 0 },
49260 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49261 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ea0000 }
49262 },
49263/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49264 {
49265 { 0, 0, 0, 0 },
49266 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49267 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ca0000 }
49268 },
49269/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49270 {
49271 { 0, 0, 0, 0 },
49272 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49273 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ea0000 }
49274 },
49275/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49276 {
49277 { 0, 0, 0, 0 },
49278 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
49279 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ca0000 }
49280 },
49281/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
49282 {
49283 { 0, 0, 0, 0 },
49284 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
49285 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ea0000 }
49286 },
49287/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49288 {
49289 { 0, 0, 0, 0 },
49290 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
49291 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78a0000 }
49292 },
49293/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
49294 {
49295 { 0, 0, 0, 0 },
49296 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
49297 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7aa0000 }
49298 },
49299/* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
49300 {
49301 { 0, 0, 0, 0 },
49302 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49303 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90a }
49304 },
49305/* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
49306 {
49307 { 0, 0, 0, 0 },
49308 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49309 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892a }
49310 },
49311/* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49312 {
49313 { 0, 0, 0, 0 },
49314 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49315 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890a }
49316 },
49317/* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
49318 {
49319 { 0, 0, 0, 0 },
49320 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49321 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18a }
49322 },
49323/* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
49324 {
49325 { 0, 0, 0, 0 },
49326 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49327 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81aa }
49328 },
49329/* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49330 {
49331 { 0, 0, 0, 0 },
49332 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49333 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818a }
49334 },
49335/* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
49336 {
49337 { 0, 0, 0, 0 },
49338 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49339 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10a }
49340 },
49341/* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
49342 {
49343 { 0, 0, 0, 0 },
49344 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49345 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812a }
49346 },
49347/* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49348 {
49349 { 0, 0, 0, 0 },
49350 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49351 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810a }
49352 },
49353/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49354 {
49355 { 0, 0, 0, 0 },
49356 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49357 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30a00 }
49358 },
49359/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49360 {
49361 { 0, 0, 0, 0 },
49362 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49363 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832a00 }
49364 },
49365/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49366 {
49367 { 0, 0, 0, 0 },
49368 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49369 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830a00 }
49370 },
49371/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49372 {
49373 { 0, 0, 0, 0 },
49374 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49375 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50a0000 }
49376 },
49377/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49378 {
49379 { 0, 0, 0, 0 },
49380 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49381 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852a0000 }
49382 },
49383/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49384 {
49385 { 0, 0, 0, 0 },
49386 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49387 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850a0000 }
49388 },
49389/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49390 {
49391 { 0, 0, 0, 0 },
49392 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49393 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70a0000 }
49394 },
49395/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49396 {
49397 { 0, 0, 0, 0 },
49398 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49399 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872a0000 }
49400 },
49401/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49402 {
49403 { 0, 0, 0, 0 },
49404 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49405 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870a0000 }
49406 },
49407/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49408 {
49409 { 0, 0, 0, 0 },
49410 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49411 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38a00 }
49412 },
49413/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49414 {
49415 { 0, 0, 0, 0 },
49416 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49417 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83aa00 }
49418 },
49419/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49420 {
49421 { 0, 0, 0, 0 },
49422 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49423 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838a00 }
49424 },
49425/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49426 {
49427 { 0, 0, 0, 0 },
49428 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49429 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58a0000 }
49430 },
49431/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49432 {
49433 { 0, 0, 0, 0 },
49434 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49435 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85aa0000 }
49436 },
49437/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49438 {
49439 { 0, 0, 0, 0 },
49440 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49441 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858a0000 }
49442 },
49443/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49444 {
49445 { 0, 0, 0, 0 },
49446 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49447 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ca00 }
49448 },
49449/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49450 {
49451 { 0, 0, 0, 0 },
49452 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49453 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ea00 }
49454 },
49455/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49456 {
49457 { 0, 0, 0, 0 },
49458 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49459 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ca00 }
49460 },
49461/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49462 {
49463 { 0, 0, 0, 0 },
49464 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49465 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ca0000 }
49466 },
49467/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49468 {
49469 { 0, 0, 0, 0 },
49470 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49471 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ea0000 }
49472 },
49473/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49474 {
49475 { 0, 0, 0, 0 },
49476 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49477 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ca0000 }
49478 },
49479/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49480 {
49481 { 0, 0, 0, 0 },
49482 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
49483 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ca0000 }
49484 },
49485/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49486 {
49487 { 0, 0, 0, 0 },
49488 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
49489 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ea0000 }
49490 },
49491/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49492 {
49493 { 0, 0, 0, 0 },
49494 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
49495 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ca0000 }
49496 },
49497/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49498 {
49499 { 0, 0, 0, 0 },
49500 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
49501 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78a0000 }
49502 },
49503/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49504 {
49505 { 0, 0, 0, 0 },
49506 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
49507 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87aa0000 }
49508 },
49509/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49510 {
49511 { 0, 0, 0, 0 },
49512 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
49513 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878a0000 }
49514 },
49515/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49516 {
49517 { 0, 0, 0, 0 },
49518 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49519 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980a00 }
49520 },
49521/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49522 {
49523 { 0, 0, 0, 0 },
49524 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49525 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982a00 }
49526 },
49527/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49528 {
49529 { 0, 0, 0, 0 },
49530 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49531 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983a00 }
49532 },
49533/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49534 {
49535 { 0, 0, 0, 0 },
49536 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49537 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908a00 }
49538 },
49539/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49540 {
49541 { 0, 0, 0, 0 },
49542 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49543 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90aa00 }
49544 },
49545/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49546 {
49547 { 0, 0, 0, 0 },
49548 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49549 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ba00 }
49550 },
49551/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49552 {
49553 { 0, 0, 0, 0 },
49554 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49555 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900a00 }
49556 },
49557/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49558 {
49559 { 0, 0, 0, 0 },
49560 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49561 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902a00 }
49562 },
49563/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49564 {
49565 { 0, 0, 0, 0 },
49566 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49567 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903a00 }
49568 },
49569/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49570 {
49571 { 0, 0, 0, 0 },
49572 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49573 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920a0000 }
49574 },
49575/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49576 {
49577 { 0, 0, 0, 0 },
49578 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49579 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922a0000 }
49580 },
49581/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49582 {
49583 { 0, 0, 0, 0 },
49584 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49585 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923a0000 }
49586 },
49587/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49588 {
49589 { 0, 0, 0, 0 },
49590 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49591 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940a0000 }
49592 },
49593/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49594 {
49595 { 0, 0, 0, 0 },
49596 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49597 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942a0000 }
49598 },
49599/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49600 {
49601 { 0, 0, 0, 0 },
49602 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49603 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943a0000 }
49604 },
49605/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49606 {
49607 { 0, 0, 0, 0 },
49608 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49609 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960a0000 }
49610 },
49611/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49612 {
49613 { 0, 0, 0, 0 },
49614 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49615 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962a0000 }
49616 },
49617/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49618 {
49619 { 0, 0, 0, 0 },
49620 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49621 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963a0000 }
49622 },
49623/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49624 {
49625 { 0, 0, 0, 0 },
49626 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49627 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928a0000 }
49628 },
49629/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49630 {
49631 { 0, 0, 0, 0 },
49632 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49633 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92aa0000 }
49634 },
49635/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49636 {
49637 { 0, 0, 0, 0 },
49638 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49639 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ba0000 }
49640 },
49641/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49642 {
49643 { 0, 0, 0, 0 },
49644 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49645 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948a0000 }
49646 },
49647/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49648 {
49649 { 0, 0, 0, 0 },
49650 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49651 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94aa0000 }
49652 },
49653/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49654 {
49655 { 0, 0, 0, 0 },
49656 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49657 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ba0000 }
49658 },
49659/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49660 {
49661 { 0, 0, 0, 0 },
49662 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49663 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ca0000 }
49664 },
49665/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49666 {
49667 { 0, 0, 0, 0 },
49668 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49669 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ea0000 }
49670 },
49671/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49672 {
49673 { 0, 0, 0, 0 },
49674 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49675 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fa0000 }
49676 },
49677/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49678 {
49679 { 0, 0, 0, 0 },
49680 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49681 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ca0000 }
49682 },
49683/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49684 {
49685 { 0, 0, 0, 0 },
49686 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49687 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ea0000 }
49688 },
49689/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49690 {
49691 { 0, 0, 0, 0 },
49692 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49693 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fa0000 }
49694 },
49695/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49696 {
49697 { 0, 0, 0, 0 },
49698 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
49699 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ca0000 }
49700 },
49701/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49702 {
49703 { 0, 0, 0, 0 },
49704 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
49705 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ea0000 }
49706 },
49707/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49708 {
49709 { 0, 0, 0, 0 },
49710 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
49711 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fa0000 }
49712 },
49713/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49714 {
49715 { 0, 0, 0, 0 },
49716 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
49717 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968a0000 }
49718 },
49719/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49720 {
49721 { 0, 0, 0, 0 },
49722 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
49723 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96aa0000 }
49724 },
49725/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49726 {
49727 { 0, 0, 0, 0 },
49728 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
49729 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ba0000 }
49730 },
49731/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49732 {
49733 { 0, 0, 0, 0 },
49734 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49735 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80a0000 }
49736 },
49737/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
49738 {
49739 { 0, 0, 0, 0 },
49740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49741 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82a0000 }
49742 },
49743/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
49744 {
49745 { 0, 0, 0, 0 },
49746 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49747 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83a0000 }
49748 },
49749/* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
49750 {
49751 { 0, 0, 0, 0 },
49752 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49753 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83a0000 }
49754 },
49755/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49756 {
49757 { 0, 0, 0, 0 },
49758 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49759 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08a0000 }
49760 },
49761/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
49762 {
49763 { 0, 0, 0, 0 },
49764 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49765 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0aa0000 }
49766 },
49767/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
49768 {
49769 { 0, 0, 0, 0 },
49770 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49771 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ba0000 }
49772 },
49773/* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
49774 {
49775 { 0, 0, 0, 0 },
49776 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49777 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ba0000 }
49778 },
49779/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49780 {
49781 { 0, 0, 0, 0 },
49782 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49783 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00a0000 }
49784 },
49785/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49786 {
49787 { 0, 0, 0, 0 },
49788 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49789 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02a0000 }
49790 },
49791/* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49792 {
49793 { 0, 0, 0, 0 },
49794 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49795 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03a0000 }
49796 },
49797/* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49798 {
49799 { 0, 0, 0, 0 },
49800 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49801 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03a0000 }
49802 },
49803/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49804 {
49805 { 0, 0, 0, 0 },
49806 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49807 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20a0000 }
49808 },
49809/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49810 {
49811 { 0, 0, 0, 0 },
49812 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49813 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22a0000 }
49814 },
49815/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49816 {
49817 { 0, 0, 0, 0 },
49818 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49819 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23a0000 }
49820 },
49821/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49822 {
49823 { 0, 0, 0, 0 },
49824 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49825 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23a0000 }
49826 },
49827/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49828 {
49829 { 0, 0, 0, 0 },
49830 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49831 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40a0000 }
49832 },
49833/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49834 {
49835 { 0, 0, 0, 0 },
49836 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49837 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42a0000 }
49838 },
49839/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49840 {
49841 { 0, 0, 0, 0 },
49842 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49843 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43a0000 }
49844 },
49845/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49846 {
49847 { 0, 0, 0, 0 },
49848 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49849 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43a0000 }
49850 },
49851/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49852 {
49853 { 0, 0, 0, 0 },
49854 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49855 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60a0000 }
49856 },
49857/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49858 {
49859 { 0, 0, 0, 0 },
49860 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49861 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62a0000 }
49862 },
49863/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49864 {
49865 { 0, 0, 0, 0 },
49866 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49867 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63a0000 }
49868 },
49869/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49870 {
49871 { 0, 0, 0, 0 },
49872 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49873 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63a0000 }
49874 },
49875/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49876 {
49877 { 0, 0, 0, 0 },
49878 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49879 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28a0000 }
49880 },
49881/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49882 {
49883 { 0, 0, 0, 0 },
49884 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49885 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2aa0000 }
49886 },
49887/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49888 {
49889 { 0, 0, 0, 0 },
49890 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49891 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ba0000 }
49892 },
49893/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49894 {
49895 { 0, 0, 0, 0 },
49896 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49897 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2ba0000 }
49898 },
49899/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49900 {
49901 { 0, 0, 0, 0 },
49902 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49903 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48a0000 }
49904 },
49905/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49906 {
49907 { 0, 0, 0, 0 },
49908 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49909 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4aa0000 }
49910 },
49911/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49912 {
49913 { 0, 0, 0, 0 },
49914 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49915 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ba0000 }
49916 },
49917/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49918 {
49919 { 0, 0, 0, 0 },
49920 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49921 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4ba0000 }
49922 },
49923/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49924 {
49925 { 0, 0, 0, 0 },
49926 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49927 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ca0000 }
49928 },
49929/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49930 {
49931 { 0, 0, 0, 0 },
49932 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49933 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ea0000 }
49934 },
49935/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49936 {
49937 { 0, 0, 0, 0 },
49938 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49939 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fa0000 }
49940 },
49941/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49942 {
49943 { 0, 0, 0, 0 },
49944 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49945 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fa0000 }
49946 },
49947/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49948 {
49949 { 0, 0, 0, 0 },
49950 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49951 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ca0000 }
49952 },
49953/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49954 {
49955 { 0, 0, 0, 0 },
49956 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49957 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ea0000 }
49958 },
49959/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49960 {
49961 { 0, 0, 0, 0 },
49962 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49963 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fa0000 }
49964 },
49965/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49966 {
49967 { 0, 0, 0, 0 },
49968 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49969 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fa0000 }
49970 },
49971/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49972 {
49973 { 0, 0, 0, 0 },
49974 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49975 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ca0000 }
49976 },
49977/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49978 {
49979 { 0, 0, 0, 0 },
49980 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49981 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ea0000 }
49982 },
49983/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49984 {
49985 { 0, 0, 0, 0 },
49986 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49987 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fa0000 }
49988 },
49989/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
49990 {
49991 { 0, 0, 0, 0 },
49992 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
49993 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fa0000 }
49994 },
49995/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49996 {
49997 { 0, 0, 0, 0 },
49998 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49999 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68a0000 }
50000 },
50001/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
50002 {
50003 { 0, 0, 0, 0 },
50004 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
50005 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6aa0000 }
50006 },
50007/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
50008 {
50009 { 0, 0, 0, 0 },
50010 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
50011 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ba0000 }
50012 },
50013/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
50014 {
50015 { 0, 0, 0, 0 },
50016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
50017 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6ba0000 }
50018 },
50019/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50020 {
50021 { 0, 0, 0, 0 },
50022 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50023 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80a0000 }
50024 },
50025/* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
50026 {
50027 { 0, 0, 0, 0 },
50028 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50029 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82a0000 }
50030 },
50031/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50032 {
50033 { 0, 0, 0, 0 },
50034 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50035 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08a0000 }
50036 },
50037/* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
50038 {
50039 { 0, 0, 0, 0 },
50040 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50041 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0aa0000 }
50042 },
50043/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50044 {
50045 { 0, 0, 0, 0 },
50046 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50047 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00a0000 }
50048 },
50049/* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
50050 {
50051 { 0, 0, 0, 0 },
50052 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50053 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02a0000 }
50054 },
50055/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
50056 {
50057 { 0, 0, 0, 0 },
50058 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50059 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20a0000 }
50060 },
50061/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
50062 {
50063 { 0, 0, 0, 0 },
50064 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50065 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22a0000 }
50066 },
50067/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
50068 {
50069 { 0, 0, 0, 0 },
50070 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50071 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40a0000 }
50072 },
50073/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
50074 {
50075 { 0, 0, 0, 0 },
50076 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50077 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42a0000 }
50078 },
50079/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
50080 {
50081 { 0, 0, 0, 0 },
50082 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50083 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60a0000 }
50084 },
50085/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
50086 {
50087 { 0, 0, 0, 0 },
50088 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50089 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62a0000 }
50090 },
50091/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
50092 {
50093 { 0, 0, 0, 0 },
50094 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
50095 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28a0000 }
50096 },
50097/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
50098 {
50099 { 0, 0, 0, 0 },
50100 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
50101 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2aa0000 }
50102 },
50103/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
50104 {
50105 { 0, 0, 0, 0 },
50106 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
50107 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48a0000 }
50108 },
50109/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
50110 {
50111 { 0, 0, 0, 0 },
50112 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
50113 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4aa0000 }
50114 },
50115/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
50116 {
50117 { 0, 0, 0, 0 },
50118 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
50119 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ca0000 }
50120 },
50121/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
50122 {
50123 { 0, 0, 0, 0 },
50124 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
50125 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ea0000 }
50126 },
50127/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
50128 {
50129 { 0, 0, 0, 0 },
50130 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
50131 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ca0000 }
50132 },
50133/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
50134 {
50135 { 0, 0, 0, 0 },
50136 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
50137 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ea0000 }
50138 },
50139/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
50140 {
50141 { 0, 0, 0, 0 },
50142 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
50143 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ca0000 }
50144 },
50145/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
50146 {
50147 { 0, 0, 0, 0 },
50148 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
50149 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ea0000 }
50150 },
50151/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
50152 {
50153 { 0, 0, 0, 0 },
50154 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
50155 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68a0000 }
50156 },
50157/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
50158 {
50159 { 0, 0, 0, 0 },
50160 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
50161 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6aa0000 }
50162 },
50163/* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
50164 {
50165 { 0, 0, 0, 0 },
50166 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50167 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80a }
50168 },
50169/* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
50170 {
50171 { 0, 0, 0, 0 },
50172 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50173 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882a }
50174 },
50175/* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50176 {
50177 { 0, 0, 0, 0 },
50178 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50179 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880a }
50180 },
50181/* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
50182 {
50183 { 0, 0, 0, 0 },
50184 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50185 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08a }
50186 },
50187/* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
50188 {
50189 { 0, 0, 0, 0 },
50190 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50191 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80aa }
50192 },
50193/* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50194 {
50195 { 0, 0, 0, 0 },
50196 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50197 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808a }
50198 },
50199/* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
50200 {
50201 { 0, 0, 0, 0 },
50202 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50203 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00a }
50204 },
50205/* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
50206 {
50207 { 0, 0, 0, 0 },
50208 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50209 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802a }
50210 },
50211/* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50212 {
50213 { 0, 0, 0, 0 },
50214 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50215 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800a }
50216 },
50217/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50218 {
50219 { 0, 0, 0, 0 },
50220 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50221 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20a00 }
50222 },
50223/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50224 {
50225 { 0, 0, 0, 0 },
50226 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50227 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822a00 }
50228 },
50229/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
50230 {
50231 { 0, 0, 0, 0 },
50232 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50233 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820a00 }
50234 },
50235/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50236 {
50237 { 0, 0, 0, 0 },
50238 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50239 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40a0000 }
50240 },
50241/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50242 {
50243 { 0, 0, 0, 0 },
50244 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50245 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842a0000 }
50246 },
50247/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
50248 {
50249 { 0, 0, 0, 0 },
50250 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50251 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840a0000 }
50252 },
50253/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50254 {
50255 { 0, 0, 0, 0 },
50256 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50257 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60a0000 }
50258 },
50259/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50260 {
50261 { 0, 0, 0, 0 },
50262 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50263 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862a0000 }
50264 },
50265/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
50266 {
50267 { 0, 0, 0, 0 },
50268 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50269 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860a0000 }
50270 },
50271/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
50272 {
50273 { 0, 0, 0, 0 },
50274 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50275 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28a00 }
50276 },
50277/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
50278 {
50279 { 0, 0, 0, 0 },
50280 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50281 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82aa00 }
50282 },
50283/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
50284 {
50285 { 0, 0, 0, 0 },
50286 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50287 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828a00 }
50288 },
50289/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
50290 {
50291 { 0, 0, 0, 0 },
50292 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50293 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48a0000 }
50294 },
50295/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
50296 {
50297 { 0, 0, 0, 0 },
50298 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50299 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84aa0000 }
50300 },
50301/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
50302 {
50303 { 0, 0, 0, 0 },
50304 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50305 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848a0000 }
50306 },
50307/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
50308 {
50309 { 0, 0, 0, 0 },
50310 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50311 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ca00 }
50312 },
50313/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
50314 {
50315 { 0, 0, 0, 0 },
50316 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50317 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ea00 }
50318 },
50319/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
50320 {
50321 { 0, 0, 0, 0 },
50322 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50323 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ca00 }
50324 },
50325/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
50326 {
50327 { 0, 0, 0, 0 },
50328 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50329 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ca0000 }
50330 },
50331/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
50332 {
50333 { 0, 0, 0, 0 },
50334 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50335 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ea0000 }
50336 },
50337/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
50338 {
50339 { 0, 0, 0, 0 },
50340 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50341 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ca0000 }
50342 },
50343/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
50344 {
50345 { 0, 0, 0, 0 },
50346 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
50347 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ca0000 }
50348 },
50349/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
50350 {
50351 { 0, 0, 0, 0 },
50352 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
50353 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ea0000 }
50354 },
50355/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
50356 {
50357 { 0, 0, 0, 0 },
50358 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
50359 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ca0000 }
50360 },
50361/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
50362 {
50363 { 0, 0, 0, 0 },
50364 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
50365 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68a0000 }
50366 },
50367/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
50368 {
50369 { 0, 0, 0, 0 },
50370 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
50371 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86aa0000 }
50372 },
50373/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
50374 {
50375 { 0, 0, 0, 0 },
50376 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
50377 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868a0000 }
50378 },
50379/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
50380 {
50381 { 0, 0, 0, 0 },
50382 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
50383 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa98000 }
50384 },
50385/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
50386 {
50387 { 0, 0, 0, 0 },
50388 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
50389 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9a000 }
50390 },
50391/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
50392 {
50393 { 0, 0, 0, 0 },
50394 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
50395 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa9b000 }
50396 },
50397/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
50398 {
50399 { 0, 0, 0, 0 },
50400 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
50401 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa98400 }
50402 },
50403/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
50404 {
50405 { 0, 0, 0, 0 },
50406 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
50407 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa9a400 }
50408 },
50409/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
50410 {
50411 { 0, 0, 0, 0 },
50412 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
50413 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa9b400 }
50414 },
50415/* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50416 {
50417 { 0, 0, 0, 0 },
50418 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50419 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa98600 }
50420 },
50421/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50422 {
50423 { 0, 0, 0, 0 },
50424 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50425 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa9a600 }
50426 },
50427/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50428 {
50429 { 0, 0, 0, 0 },
50430 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50431 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa9b600 }
50432 },
50433/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50434 {
50435 { 0, 0, 0, 0 },
50436 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50437 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa9880000 }
50438 },
50439/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50440 {
50441 { 0, 0, 0, 0 },
50442 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50443 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9a80000 }
50444 },
50445/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50446 {
50447 { 0, 0, 0, 0 },
50448 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50449 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9b80000 }
50450 },
50451/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50452 {
50453 { 0, 0, 0, 0 },
50454 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50455 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa98c0000 }
50456 },
50457/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50458 {
50459 { 0, 0, 0, 0 },
50460 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50461 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9ac0000 }
50462 },
50463/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50464 {
50465 { 0, 0, 0, 0 },
50466 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50467 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9bc0000 }
50468 },
50469/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50470 {
50471 { 0, 0, 0, 0 },
50472 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50473 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa98a0000 }
50474 },
50475/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50476 {
50477 { 0, 0, 0, 0 },
50478 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50479 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9aa0000 }
50480 },
50481/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50482 {
50483 { 0, 0, 0, 0 },
50484 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50485 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9ba0000 }
50486 },
50487/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50488 {
50489 { 0, 0, 0, 0 },
50490 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50491 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa98e0000 }
50492 },
50493/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50494 {
50495 { 0, 0, 0, 0 },
50496 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50497 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9ae0000 }
50498 },
50499/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50500 {
50501 { 0, 0, 0, 0 },
50502 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50503 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9be0000 }
50504 },
50505/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50506 {
50507 { 0, 0, 0, 0 },
50508 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50509 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa98b0000 }
50510 },
50511/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50512 {
50513 { 0, 0, 0, 0 },
50514 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50515 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9ab0000 }
50516 },
50517/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50518 {
50519 { 0, 0, 0, 0 },
50520 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50521 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9bb0000 }
50522 },
50523/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50524 {
50525 { 0, 0, 0, 0 },
50526 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
50527 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa98f0000 }
50528 },
50529/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50530 {
50531 { 0, 0, 0, 0 },
50532 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50533 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa9af0000 }
50534 },
50535/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50536 {
50537 { 0, 0, 0, 0 },
50538 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50539 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa9bf0000 }
50540 },
50541/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
50542 {
50543 { 0, 0, 0, 0 },
50544 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
50545 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa9c00000 }
50546 },
50547/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
50548 {
50549 { 0, 0, 0, 0 },
50550 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
50551 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9e00000 }
50552 },
50553/* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
50554 {
50555 { 0, 0, 0, 0 },
50556 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
50557 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa9f00000 }
50558 },
50559/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
50560 {
50561 { 0, 0, 0, 0 },
50562 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
50563 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa9c40000 }
50564 },
50565/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
50566 {
50567 { 0, 0, 0, 0 },
50568 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
50569 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa9e40000 }
50570 },
50571/* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
50572 {
50573 { 0, 0, 0, 0 },
50574 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
50575 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa9f40000 }
50576 },
50577/* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50578 {
50579 { 0, 0, 0, 0 },
50580 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50581 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa9c60000 }
50582 },
50583/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50584 {
50585 { 0, 0, 0, 0 },
50586 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50587 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa9e60000 }
50588 },
50589/* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
50590 {
50591 { 0, 0, 0, 0 },
50592 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
50593 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa9f60000 }
50594 },
50595/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50596 {
50597 { 0, 0, 0, 0 },
50598 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50599 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa9c80000 }
50600 },
50601/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50602 {
50603 { 0, 0, 0, 0 },
50604 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50605 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa9e80000 }
50606 },
50607/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50608 {
50609 { 0, 0, 0, 0 },
50610 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50611 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa9f80000 }
50612 },
50613/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50614 {
50615 { 0, 0, 0, 0 },
50616 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
50617 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa9cc0000 }
50618 },
50619/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50620 {
50621 { 0, 0, 0, 0 },
50622 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
50623 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa9ec0000 }
50624 },
50625/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50626 {
50627 { 0, 0, 0, 0 },
50628 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
50629 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa9fc0000 }
50630 },
50631/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50632 {
50633 { 0, 0, 0, 0 },
50634 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50635 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ca0000 }
50636 },
50637/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50638 {
50639 { 0, 0, 0, 0 },
50640 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50641 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ea0000 }
50642 },
50643/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50644 {
50645 { 0, 0, 0, 0 },
50646 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50647 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa9fa0000 }
50648 },
50649/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50650 {
50651 { 0, 0, 0, 0 },
50652 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50653 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ce0000 }
50654 },
50655/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50656 {
50657 { 0, 0, 0, 0 },
50658 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50659 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ee0000 }
50660 },
50661/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50662 {
50663 { 0, 0, 0, 0 },
50664 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50665 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa9fe0000 }
50666 },
50667/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50668 {
50669 { 0, 0, 0, 0 },
50670 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50671 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9cb0000 }
50672 },
50673/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50674 {
50675 { 0, 0, 0, 0 },
50676 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50677 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9eb0000 }
50678 },
50679/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50680 {
50681 { 0, 0, 0, 0 },
50682 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50683 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa9fb0000 }
50684 },
50685/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50686 {
50687 { 0, 0, 0, 0 },
50688 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
50689 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa9cf0000 }
50690 },
50691/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50692 {
50693 { 0, 0, 0, 0 },
50694 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
50695 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa9ef0000 }
50696 },
50697/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
50698 {
50699 { 0, 0, 0, 0 },
50700 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
50701 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa9ff0000 }
50702 },
50703/* sub.w${G} $Src16RnHI,$Dst16RnHI */
50704 {
50705 { 0, 0, 0, 0 },
50706 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
50707 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa900 }
50708 },
50709/* sub.w${G} $Src16AnHI,$Dst16RnHI */
50710 {
50711 { 0, 0, 0, 0 },
50712 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
50713 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa940 }
50714 },
50715/* sub.w${G} [$Src16An],$Dst16RnHI */
50716 {
50717 { 0, 0, 0, 0 },
50718 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
50719 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa960 }
50720 },
50721/* sub.w${G} $Src16RnHI,$Dst16AnHI */
50722 {
50723 { 0, 0, 0, 0 },
50724 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
50725 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa904 }
50726 },
50727/* sub.w${G} $Src16AnHI,$Dst16AnHI */
50728 {
50729 { 0, 0, 0, 0 },
50730 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
50731 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa944 }
50732 },
50733/* sub.w${G} [$Src16An],$Dst16AnHI */
50734 {
50735 { 0, 0, 0, 0 },
50736 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
50737 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa964 }
50738 },
50739/* sub.w${G} $Src16RnHI,[$Dst16An] */
50740 {
50741 { 0, 0, 0, 0 },
50742 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
50743 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa906 }
50744 },
50745/* sub.w${G} $Src16AnHI,[$Dst16An] */
50746 {
50747 { 0, 0, 0, 0 },
50748 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
50749 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa946 }
50750 },
50751/* sub.w${G} [$Src16An],[$Dst16An] */
50752 {
50753 { 0, 0, 0, 0 },
50754 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50755 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa966 }
50756 },
50757/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
50758 {
50759 { 0, 0, 0, 0 },
50760 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
50761 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa90800 }
50762 },
50763/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
50764 {
50765 { 0, 0, 0, 0 },
50766 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
50767 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa94800 }
50768 },
50769/* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50770 {
50771 { 0, 0, 0, 0 },
50772 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
50773 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa96800 }
50774 },
50775/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
50776 {
50777 { 0, 0, 0, 0 },
50778 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
50779 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa90c0000 }
50780 },
50781/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
50782 {
50783 { 0, 0, 0, 0 },
50784 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
50785 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa94c0000 }
50786 },
50787/* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50788 {
50789 { 0, 0, 0, 0 },
50790 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
50791 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa96c0000 }
50792 },
50793/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
50794 {
50795 { 0, 0, 0, 0 },
50796 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50797 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa90a00 }
50798 },
50799/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
50800 {
50801 { 0, 0, 0, 0 },
50802 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50803 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa94a00 }
50804 },
50805/* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
50806 {
50807 { 0, 0, 0, 0 },
50808 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50809 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa96a00 }
50810 },
50811/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
50812 {
50813 { 0, 0, 0, 0 },
50814 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50815 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa90e0000 }
50816 },
50817/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
50818 {
50819 { 0, 0, 0, 0 },
50820 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50821 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa94e0000 }
50822 },
50823/* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
50824 {
50825 { 0, 0, 0, 0 },
50826 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50827 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa96e0000 }
50828 },
50829/* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
50830 {
50831 { 0, 0, 0, 0 },
50832 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50833 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa90b00 }
50834 },
50835/* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
50836 {
50837 { 0, 0, 0, 0 },
50838 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50839 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa94b00 }
50840 },
50841/* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
50842 {
50843 { 0, 0, 0, 0 },
50844 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50845 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa96b00 }
50846 },
50847/* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
50848 {
50849 { 0, 0, 0, 0 },
50850 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
50851 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa90f0000 }
50852 },
50853/* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
50854 {
50855 { 0, 0, 0, 0 },
50856 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
50857 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa94f0000 }
50858 },
50859/* sub.w${G} [$Src16An],${Dsp-16-u16} */
50860 {
50861 { 0, 0, 0, 0 },
50862 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
50863 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa96f0000 }
50864 },
50865/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
50866 {
50867 { 0, 0, 0, 0 },
50868 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
50869 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa88000 }
50870 },
50871/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
50872 {
50873 { 0, 0, 0, 0 },
50874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
50875 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8a000 }
50876 },
50877/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
50878 {
50879 { 0, 0, 0, 0 },
50880 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
50881 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa8b000 }
50882 },
50883/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
50884 {
50885 { 0, 0, 0, 0 },
50886 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
50887 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa88400 }
50888 },
50889/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
50890 {
50891 { 0, 0, 0, 0 },
50892 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
50893 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa8a400 }
50894 },
50895/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
50896 {
50897 { 0, 0, 0, 0 },
50898 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
50899 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa8b400 }
50900 },
50901/* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50902 {
50903 { 0, 0, 0, 0 },
50904 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50905 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa88600 }
50906 },
50907/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50908 {
50909 { 0, 0, 0, 0 },
50910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50911 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa8a600 }
50912 },
50913/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50914 {
50915 { 0, 0, 0, 0 },
50916 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50917 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa8b600 }
50918 },
50919/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50920 {
50921 { 0, 0, 0, 0 },
50922 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50923 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa8880000 }
50924 },
50925/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50926 {
50927 { 0, 0, 0, 0 },
50928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50929 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8a80000 }
50930 },
50931/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50932 {
50933 { 0, 0, 0, 0 },
50934 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50935 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8b80000 }
50936 },
50937/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50938 {
50939 { 0, 0, 0, 0 },
50940 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50941 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa88c0000 }
50942 },
50943/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50944 {
50945 { 0, 0, 0, 0 },
50946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50947 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8ac0000 }
50948 },
50949/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50950 {
50951 { 0, 0, 0, 0 },
50952 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50953 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8bc0000 }
50954 },
50955/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50956 {
50957 { 0, 0, 0, 0 },
50958 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50959 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa88a0000 }
50960 },
50961/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50962 {
50963 { 0, 0, 0, 0 },
50964 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50965 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8aa0000 }
50966 },
50967/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50968 {
50969 { 0, 0, 0, 0 },
50970 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50971 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8ba0000 }
50972 },
50973/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50974 {
50975 { 0, 0, 0, 0 },
50976 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50977 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa88e0000 }
50978 },
50979/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50980 {
50981 { 0, 0, 0, 0 },
50982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50983 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8ae0000 }
50984 },
50985/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50986 {
50987 { 0, 0, 0, 0 },
50988 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50989 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8be0000 }
50990 },
50991/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50992 {
50993 { 0, 0, 0, 0 },
50994 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50995 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa88b0000 }
50996 },
50997/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50998 {
50999 { 0, 0, 0, 0 },
51000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51001 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8ab0000 }
51002 },
51003/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51004 {
51005 { 0, 0, 0, 0 },
51006 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51007 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8bb0000 }
51008 },
51009/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
51010 {
51011 { 0, 0, 0, 0 },
51012 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
51013 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa88f0000 }
51014 },
51015/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51016 {
51017 { 0, 0, 0, 0 },
51018 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
51019 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa8af0000 }
51020 },
51021/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51022 {
51023 { 0, 0, 0, 0 },
51024 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
51025 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa8bf0000 }
51026 },
51027/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
51028 {
51029 { 0, 0, 0, 0 },
51030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51031 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa8c00000 }
51032 },
51033/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
51034 {
51035 { 0, 0, 0, 0 },
51036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
51037 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8e00000 }
51038 },
51039/* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
51040 {
51041 { 0, 0, 0, 0 },
51042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
51043 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa8f00000 }
51044 },
51045/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
51046 {
51047 { 0, 0, 0, 0 },
51048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51049 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa8c40000 }
51050 },
51051/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
51052 {
51053 { 0, 0, 0, 0 },
51054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
51055 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa8e40000 }
51056 },
51057/* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
51058 {
51059 { 0, 0, 0, 0 },
51060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
51061 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa8f40000 }
51062 },
51063/* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
51064 {
51065 { 0, 0, 0, 0 },
51066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51067 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa8c60000 }
51068 },
51069/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
51070 {
51071 { 0, 0, 0, 0 },
51072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
51073 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa8e60000 }
51074 },
51075/* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
51076 {
51077 { 0, 0, 0, 0 },
51078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
51079 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa8f60000 }
51080 },
51081/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
51082 {
51083 { 0, 0, 0, 0 },
51084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51085 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa8c80000 }
51086 },
51087/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
51088 {
51089 { 0, 0, 0, 0 },
51090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51091 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa8e80000 }
51092 },
51093/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
51094 {
51095 { 0, 0, 0, 0 },
51096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51097 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa8f80000 }
51098 },
51099/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
51100 {
51101 { 0, 0, 0, 0 },
51102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51103 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa8cc0000 }
51104 },
51105/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
51106 {
51107 { 0, 0, 0, 0 },
51108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51109 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa8ec0000 }
51110 },
51111/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
51112 {
51113 { 0, 0, 0, 0 },
51114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51115 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa8fc0000 }
51116 },
51117/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
51118 {
51119 { 0, 0, 0, 0 },
51120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51121 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ca0000 }
51122 },
51123/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51124 {
51125 { 0, 0, 0, 0 },
51126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51127 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ea0000 }
51128 },
51129/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51130 {
51131 { 0, 0, 0, 0 },
51132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51133 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa8fa0000 }
51134 },
51135/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
51136 {
51137 { 0, 0, 0, 0 },
51138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51139 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ce0000 }
51140 },
51141/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51142 {
51143 { 0, 0, 0, 0 },
51144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51145 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ee0000 }
51146 },
51147/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51148 {
51149 { 0, 0, 0, 0 },
51150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51151 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa8fe0000 }
51152 },
51153/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
51154 {
51155 { 0, 0, 0, 0 },
51156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51157 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8cb0000 }
51158 },
51159/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51160 {
51161 { 0, 0, 0, 0 },
51162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51163 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8eb0000 }
51164 },
51165/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51166 {
51167 { 0, 0, 0, 0 },
51168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51169 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa8fb0000 }
51170 },
51171/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
51172 {
51173 { 0, 0, 0, 0 },
51174 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
51175 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa8cf0000 }
51176 },
51177/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51178 {
51179 { 0, 0, 0, 0 },
51180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
51181 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa8ef0000 }
51182 },
51183/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
51184 {
51185 { 0, 0, 0, 0 },
51186 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
51187 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa8ff0000 }
51188 },
51189/* sub.b${G} $Src16RnQI,$Dst16RnQI */
51190 {
51191 { 0, 0, 0, 0 },
51192 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
51193 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa800 }
51194 },
51195/* sub.b${G} $Src16AnQI,$Dst16RnQI */
51196 {
51197 { 0, 0, 0, 0 },
51198 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
51199 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa840 }
51200 },
51201/* sub.b${G} [$Src16An],$Dst16RnQI */
51202 {
51203 { 0, 0, 0, 0 },
51204 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51205 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa860 }
51206 },
51207/* sub.b${G} $Src16RnQI,$Dst16AnQI */
51208 {
51209 { 0, 0, 0, 0 },
51210 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
51211 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa804 }
51212 },
51213/* sub.b${G} $Src16AnQI,$Dst16AnQI */
51214 {
51215 { 0, 0, 0, 0 },
51216 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
51217 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa844 }
51218 },
51219/* sub.b${G} [$Src16An],$Dst16AnQI */
51220 {
51221 { 0, 0, 0, 0 },
51222 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51223 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa864 }
51224 },
51225/* sub.b${G} $Src16RnQI,[$Dst16An] */
51226 {
51227 { 0, 0, 0, 0 },
51228 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
51229 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa806 }
51230 },
51231/* sub.b${G} $Src16AnQI,[$Dst16An] */
51232 {
51233 { 0, 0, 0, 0 },
51234 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
51235 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa846 }
51236 },
51237/* sub.b${G} [$Src16An],[$Dst16An] */
51238 {
51239 { 0, 0, 0, 0 },
51240 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51241 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa866 }
51242 },
51243/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
51244 {
51245 { 0, 0, 0, 0 },
51246 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51247 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa80800 }
51248 },
51249/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
51250 {
51251 { 0, 0, 0, 0 },
51252 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51253 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa84800 }
51254 },
51255/* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
51256 {
51257 { 0, 0, 0, 0 },
51258 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51259 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa86800 }
51260 },
51261/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
51262 {
51263 { 0, 0, 0, 0 },
51264 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51265 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa80c0000 }
51266 },
51267/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
51268 {
51269 { 0, 0, 0, 0 },
51270 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51271 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa84c0000 }
51272 },
51273/* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
51274 {
51275 { 0, 0, 0, 0 },
51276 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51277 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa86c0000 }
51278 },
51279/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
51280 {
51281 { 0, 0, 0, 0 },
51282 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51283 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa80a00 }
51284 },
51285/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
51286 {
51287 { 0, 0, 0, 0 },
51288 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51289 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa84a00 }
51290 },
51291/* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
51292 {
51293 { 0, 0, 0, 0 },
51294 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51295 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa86a00 }
51296 },
51297/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
51298 {
51299 { 0, 0, 0, 0 },
51300 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51301 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa80e0000 }
51302 },
51303/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
51304 {
51305 { 0, 0, 0, 0 },
51306 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51307 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa84e0000 }
51308 },
51309/* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
51310 {
51311 { 0, 0, 0, 0 },
51312 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51313 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa86e0000 }
51314 },
51315/* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
51316 {
51317 { 0, 0, 0, 0 },
51318 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51319 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa80b00 }
51320 },
51321/* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
51322 {
51323 { 0, 0, 0, 0 },
51324 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51325 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa84b00 }
51326 },
51327/* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
51328 {
51329 { 0, 0, 0, 0 },
51330 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51331 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa86b00 }
51332 },
51333/* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
51334 {
51335 { 0, 0, 0, 0 },
51336 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
51337 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa80f0000 }
51338 },
51339/* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
51340 {
51341 { 0, 0, 0, 0 },
51342 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
51343 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa84f0000 }
51344 },
51345/* sub.b${G} [$Src16An],${Dsp-16-u16} */
51346 {
51347 { 0, 0, 0, 0 },
51348 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
51349 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa86f0000 }
51350 },
51351/* sub.b${S} #${Imm-8-QI},r0l */
51352 {
51353 { 0, 0, 0, 0 },
51354 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
51355 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8c00 }
51356 },
51357/* sub.b${S} #${Imm-8-QI},r0h */
51358 {
51359 { 0, 0, 0, 0 },
51360 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
51361 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8b00 }
51362 },
51363/* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
51364 {
51365 { 0, 0, 0, 0 },
51366 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51367 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x8d0000 }
51368 },
51369/* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
51370 {
51371 { 0, 0, 0, 0 },
51372 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51373 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x8e0000 }
51374 },
51375/* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
51376 {
51377 { 0, 0, 0, 0 },
51378 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
51379 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x8f000000 }
51380 },
51381/* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
51382 {
51383 { 0, 0, 0, 0 },
51384 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
51385 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893e0000 }
51386 },
51387/* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
51388 {
51389 { 0, 0, 0, 0 },
51390 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
51391 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81be0000 }
51392 },
51393/* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
51394 {
51395 { 0, 0, 0, 0 },
51396 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51397 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813e0000 }
51398 },
51399/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51400 {
51401 { 0, 0, 0, 0 },
51402 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51403 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833e0000 }
51404 },
51405/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51406 {
51407 { 0, 0, 0, 0 },
51408 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51409 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83be0000 }
51410 },
51411/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51412 {
51413 { 0, 0, 0, 0 },
51414 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51415 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83fe0000 }
51416 },
51417/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51418 {
51419 { 0, 0, 0, 0 },
51420 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51421 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853e0000 }
51422 },
51423/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51424 {
51425 { 0, 0, 0, 0 },
51426 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51427 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85be0000 }
51428 },
51429/* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
51430 {
51431 { 0, 0, 0, 0 },
51432 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
51433 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85fe0000 }
51434 },
51435/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51436 {
51437 { 0, 0, 0, 0 },
51438 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
51439 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87fe0000 }
51440 },
51441/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51442 {
51443 { 0, 0, 0, 0 },
51444 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51445 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873e0000 }
51446 },
51447/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
51448 {
51449 { 0, 0, 0, 0 },
51450 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
51451 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87be0000 }
51452 },
51453/* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
51454 {
51455 { 0, 0, 0, 0 },
51456 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
51457 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883e00 }
51458 },
51459/* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
51460 {
51461 { 0, 0, 0, 0 },
51462 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
51463 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80be00 }
51464 },
51465/* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51466 {
51467 { 0, 0, 0, 0 },
51468 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51469 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803e00 }
51470 },
51471/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51472 {
51473 { 0, 0, 0, 0 },
51474 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51475 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823e0000 }
51476 },
51477/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51478 {
51479 { 0, 0, 0, 0 },
51480 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51481 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82be0000 }
51482 },
51483/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51484 {
51485 { 0, 0, 0, 0 },
51486 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51487 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82fe0000 }
51488 },
51489/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51490 {
51491 { 0, 0, 0, 0 },
51492 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51493 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843e0000 }
51494 },
51495/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51496 {
51497 { 0, 0, 0, 0 },
51498 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51499 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84be0000 }
51500 },
51501/* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51502 {
51503 { 0, 0, 0, 0 },
51504 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
51505 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84fe0000 }
51506 },
51507/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51508 {
51509 { 0, 0, 0, 0 },
51510 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
51511 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86fe0000 }
51512 },
51513/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51514 {
51515 { 0, 0, 0, 0 },
51516 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51517 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863e0000 }
51518 },
51519/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
51520 {
51521 { 0, 0, 0, 0 },
51522 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
51523 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86be0000 }
51524 },
51525/* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
51526 {
51527 { 0, 0, 0, 0 },
51528 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
51529 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77500000 }
51530 },
51531/* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
51532 {
51533 { 0, 0, 0, 0 },
51534 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
51535 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77540000 }
51536 },
51537/* sub.w${G} #${Imm-16-HI},[$Dst16An] */
51538 {
51539 { 0, 0, 0, 0 },
51540 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
51541 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77560000 }
51542 },
51543/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
51544 {
51545 { 0, 0, 0, 0 },
51546 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51547 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77580000 }
51548 },
51549/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51550 {
51551 { 0, 0, 0, 0 },
51552 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51553 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x775a0000 }
51554 },
51555/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51556 {
51557 { 0, 0, 0, 0 },
51558 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51559 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x775b0000 }
51560 },
51561/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
51562 {
51563 { 0, 0, 0, 0 },
51564 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51565 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x775c0000 }
51566 },
51567/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51568 {
51569 { 0, 0, 0, 0 },
51570 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51571 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x775e0000 }
51572 },
51573/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51574 {
51575 { 0, 0, 0, 0 },
51576 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
51577 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x775f0000 }
51578 },
51579/* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
51580 {
51581 { 0, 0, 0, 0 },
51582 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
51583 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x765000 }
51584 },
51585/* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
51586 {
51587 { 0, 0, 0, 0 },
51588 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
51589 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x765400 }
51590 },
51591/* sub.b${G} #${Imm-16-QI},[$Dst16An] */
51592 {
51593 { 0, 0, 0, 0 },
51594 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
51595 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x765600 }
51596 },
51597/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
51598 {
51599 { 0, 0, 0, 0 },
51600 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51601 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76580000 }
51602 },
51603/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51604 {
51605 { 0, 0, 0, 0 },
51606 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51607 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x765a0000 }
51608 },
51609/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51610 {
51611 { 0, 0, 0, 0 },
51612 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51613 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x765b0000 }
51614 },
51615/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
51616 {
51617 { 0, 0, 0, 0 },
51618 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51619 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x765c0000 }
51620 },
51621/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51622 {
51623 { 0, 0, 0, 0 },
51624 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51625 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x765e0000 }
51626 },
51627/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51628 {
51629 { 0, 0, 0, 0 },
51630 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
51631 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x765f0000 }
51632 },
51633/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
51634 {
51635 { 0, 0, 0, 0 },
51636 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
51637 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990200 }
51638 },
51639/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
51640 {
51641 { 0, 0, 0, 0 },
51642 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
51643 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992200 }
51644 },
51645/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
51646 {
51647 { 0, 0, 0, 0 },
51648 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
51649 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993200 }
51650 },
51651/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
51652 {
51653 { 0, 0, 0, 0 },
51654 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
51655 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918200 }
51656 },
51657/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
51658 {
51659 { 0, 0, 0, 0 },
51660 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
51661 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a200 }
51662 },
51663/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
51664 {
51665 { 0, 0, 0, 0 },
51666 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
51667 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b200 }
51668 },
51669/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
51670 {
51671 { 0, 0, 0, 0 },
51672 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
51673 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910200 }
51674 },
51675/* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
51676 {
51677 { 0, 0, 0, 0 },
51678 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
51679 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912200 }
51680 },
51681/* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
51682 {
51683 { 0, 0, 0, 0 },
51684 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
51685 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913200 }
51686 },
51687/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
51688 {
51689 { 0, 0, 0, 0 },
51690 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
51691 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930200 }
51692 },
51693/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
51694 {
51695 { 0, 0, 0, 0 },
51696 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
51697 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932200 }
51698 },
51699/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
51700 {
51701 { 0, 0, 0, 0 },
51702 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
51703 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933200 }
51704 },
51705/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
51706 {
51707 { 0, 0, 0, 0 },
51708 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
51709 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950200 }
51710 },
51711/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
51712 {
51713 { 0, 0, 0, 0 },
51714 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
51715 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952200 }
51716 },
51717/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
51718 {
51719 { 0, 0, 0, 0 },
51720 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
51721 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953200 }
51722 },
51723/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
51724 {
51725 { 0, 0, 0, 0 },
51726 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
51727 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970200 }
51728 },
51729/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
51730 {
51731 { 0, 0, 0, 0 },
51732 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
51733 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972200 }
51734 },
51735/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
51736 {
51737 { 0, 0, 0, 0 },
51738 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
51739 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973200 }
51740 },
51741/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
51742 {
51743 { 0, 0, 0, 0 },
51744 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51745 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938200 }
51746 },
51747/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
51748 {
51749 { 0, 0, 0, 0 },
51750 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51751 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a200 }
51752 },
51753/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
51754 {
51755 { 0, 0, 0, 0 },
51756 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51757 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b200 }
51758 },
51759/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
51760 {
51761 { 0, 0, 0, 0 },
51762 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51763 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958200 }
51764 },
51765/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
51766 {
51767 { 0, 0, 0, 0 },
51768 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51769 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a200 }
51770 },
51771/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
51772 {
51773 { 0, 0, 0, 0 },
51774 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51775 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b200 }
51776 },
51777/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
51778 {
51779 { 0, 0, 0, 0 },
51780 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51781 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c200 }
51782 },
51783/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
51784 {
51785 { 0, 0, 0, 0 },
51786 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51787 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e200 }
51788 },
51789/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
51790 {
51791 { 0, 0, 0, 0 },
51792 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51793 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f200 }
51794 },
51795/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
51796 {
51797 { 0, 0, 0, 0 },
51798 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
51799 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c200 }
51800 },
51801/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
51802 {
51803 { 0, 0, 0, 0 },
51804 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
51805 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e200 }
51806 },
51807/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
51808 {
51809 { 0, 0, 0, 0 },
51810 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
51811 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f200 }
51812 },
51813/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
51814 {
51815 { 0, 0, 0, 0 },
51816 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
51817 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c200 }
51818 },
51819/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
51820 {
51821 { 0, 0, 0, 0 },
51822 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
51823 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e200 }
51824 },
51825/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
51826 {
51827 { 0, 0, 0, 0 },
51828 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
51829 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f200 }
51830 },
51831/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
51832 {
51833 { 0, 0, 0, 0 },
51834 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
51835 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978200 }
51836 },
51837/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
51838 {
51839 { 0, 0, 0, 0 },
51840 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
51841 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a200 }
51842 },
51843/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
51844 {
51845 { 0, 0, 0, 0 },
51846 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
51847 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b200 }
51848 },
51849/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
51850 {
51851 { 0, 0, 0, 0 },
51852 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
51853 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90200 }
51854 },
51855/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
51856 {
51857 { 0, 0, 0, 0 },
51858 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
51859 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92200 }
51860 },
51861/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
51862 {
51863 { 0, 0, 0, 0 },
51864 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
51865 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93200 }
51866 },
51867/* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
51868 {
51869 { 0, 0, 0, 0 },
51870 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
51871 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93200 }
51872 },
51873/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
51874 {
51875 { 0, 0, 0, 0 },
51876 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
51877 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18200 }
51878 },
51879/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
51880 {
51881 { 0, 0, 0, 0 },
51882 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
51883 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a200 }
51884 },
51885/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
51886 {
51887 { 0, 0, 0, 0 },
51888 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
51889 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b200 }
51890 },
51891/* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
51892 {
51893 { 0, 0, 0, 0 },
51894 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
51895 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b200 }
51896 },
51897/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
51898 {
51899 { 0, 0, 0, 0 },
51900 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
51901 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10200 }
51902 },
51903/* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
51904 {
51905 { 0, 0, 0, 0 },
51906 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
51907 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12200 }
51908 },
51909/* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
51910 {
51911 { 0, 0, 0, 0 },
51912 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
51913 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13200 }
51914 },
51915/* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
51916 {
51917 { 0, 0, 0, 0 },
51918 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
51919 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13200 }
51920 },
51921/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
51922 {
51923 { 0, 0, 0, 0 },
51924 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
51925 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30200 }
51926 },
51927/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
51928 {
51929 { 0, 0, 0, 0 },
51930 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
51931 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32200 }
51932 },
51933/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
51934 {
51935 { 0, 0, 0, 0 },
51936 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
51937 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33200 }
51938 },
51939/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
51940 {
51941 { 0, 0, 0, 0 },
51942 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
51943 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33200 }
51944 },
51945/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
51946 {
51947 { 0, 0, 0, 0 },
51948 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
51949 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50200 }
51950 },
51951/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
51952 {
51953 { 0, 0, 0, 0 },
51954 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
51955 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52200 }
51956 },
51957/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
51958 {
51959 { 0, 0, 0, 0 },
51960 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
51961 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53200 }
51962 },
51963/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
51964 {
51965 { 0, 0, 0, 0 },
51966 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
51967 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53200 }
51968 },
51969/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
51970 {
51971 { 0, 0, 0, 0 },
51972 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
51973 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70200 }
51974 },
51975/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
51976 {
51977 { 0, 0, 0, 0 },
51978 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
51979 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72200 }
51980 },
51981/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
51982 {
51983 { 0, 0, 0, 0 },
51984 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
51985 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73200 }
51986 },
51987/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
51988 {
51989 { 0, 0, 0, 0 },
51990 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
51991 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73200 }
51992 },
51993/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
51994 {
51995 { 0, 0, 0, 0 },
51996 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
51997 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38200 }
51998 },
51999/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52000 {
52001 { 0, 0, 0, 0 },
52002 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52003 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a200 }
52004 },
52005/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52006 {
52007 { 0, 0, 0, 0 },
52008 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52009 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b200 }
52010 },
52011/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52012 {
52013 { 0, 0, 0, 0 },
52014 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52015 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b200 }
52016 },
52017/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52018 {
52019 { 0, 0, 0, 0 },
52020 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52021 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58200 }
52022 },
52023/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52024 {
52025 { 0, 0, 0, 0 },
52026 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52027 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a200 }
52028 },
52029/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52030 {
52031 { 0, 0, 0, 0 },
52032 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52033 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b200 }
52034 },
52035/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52036 {
52037 { 0, 0, 0, 0 },
52038 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52039 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b200 }
52040 },
52041/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52042 {
52043 { 0, 0, 0, 0 },
52044 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52045 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c200 }
52046 },
52047/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52048 {
52049 { 0, 0, 0, 0 },
52050 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52051 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e200 }
52052 },
52053/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52054 {
52055 { 0, 0, 0, 0 },
52056 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52057 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f200 }
52058 },
52059/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52060 {
52061 { 0, 0, 0, 0 },
52062 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52063 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f200 }
52064 },
52065/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52066 {
52067 { 0, 0, 0, 0 },
52068 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52069 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c200 }
52070 },
52071/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52072 {
52073 { 0, 0, 0, 0 },
52074 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52075 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e200 }
52076 },
52077/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52078 {
52079 { 0, 0, 0, 0 },
52080 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52081 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f200 }
52082 },
52083/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52084 {
52085 { 0, 0, 0, 0 },
52086 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52087 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f200 }
52088 },
52089/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52090 {
52091 { 0, 0, 0, 0 },
52092 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
52093 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c200 }
52094 },
52095/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52096 {
52097 { 0, 0, 0, 0 },
52098 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52099 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e200 }
52100 },
52101/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52102 {
52103 { 0, 0, 0, 0 },
52104 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52105 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f200 }
52106 },
52107/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52108 {
52109 { 0, 0, 0, 0 },
52110 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
52111 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f200 }
52112 },
52113/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52114 {
52115 { 0, 0, 0, 0 },
52116 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
52117 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78200 }
52118 },
52119/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52120 {
52121 { 0, 0, 0, 0 },
52122 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52123 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a200 }
52124 },
52125/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52126 {
52127 { 0, 0, 0, 0 },
52128 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52129 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b200 }
52130 },
52131/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52132 {
52133 { 0, 0, 0, 0 },
52134 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
52135 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b200 }
52136 },
52137/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52138 {
52139 { 0, 0, 0, 0 },
52140 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52141 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90200 }
52142 },
52143/* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52144 {
52145 { 0, 0, 0, 0 },
52146 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
52147 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92200 }
52148 },
52149/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52150 {
52151 { 0, 0, 0, 0 },
52152 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52153 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18200 }
52154 },
52155/* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52156 {
52157 { 0, 0, 0, 0 },
52158 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
52159 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a200 }
52160 },
52161/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52162 {
52163 { 0, 0, 0, 0 },
52164 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52165 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10200 }
52166 },
52167/* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52168 {
52169 { 0, 0, 0, 0 },
52170 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52171 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12200 }
52172 },
52173/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52174 {
52175 { 0, 0, 0, 0 },
52176 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52177 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30200 }
52178 },
52179/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52180 {
52181 { 0, 0, 0, 0 },
52182 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52183 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32200 }
52184 },
52185/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52186 {
52187 { 0, 0, 0, 0 },
52188 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52189 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50200 }
52190 },
52191/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52192 {
52193 { 0, 0, 0, 0 },
52194 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52195 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52200 }
52196 },
52197/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52198 {
52199 { 0, 0, 0, 0 },
52200 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52201 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70200 }
52202 },
52203/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52204 {
52205 { 0, 0, 0, 0 },
52206 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52207 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72200 }
52208 },
52209/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52210 {
52211 { 0, 0, 0, 0 },
52212 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
52213 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38200 }
52214 },
52215/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52216 {
52217 { 0, 0, 0, 0 },
52218 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
52219 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a200 }
52220 },
52221/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52222 {
52223 { 0, 0, 0, 0 },
52224 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
52225 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58200 }
52226 },
52227/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52228 {
52229 { 0, 0, 0, 0 },
52230 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
52231 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a200 }
52232 },
52233/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52234 {
52235 { 0, 0, 0, 0 },
52236 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
52237 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c200 }
52238 },
52239/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52240 {
52241 { 0, 0, 0, 0 },
52242 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
52243 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e200 }
52244 },
52245/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52246 {
52247 { 0, 0, 0, 0 },
52248 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
52249 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c200 }
52250 },
52251/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52252 {
52253 { 0, 0, 0, 0 },
52254 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
52255 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e200 }
52256 },
52257/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52258 {
52259 { 0, 0, 0, 0 },
52260 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
52261 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c200 }
52262 },
52263/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52264 {
52265 { 0, 0, 0, 0 },
52266 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
52267 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e200 }
52268 },
52269/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52270 {
52271 { 0, 0, 0, 0 },
52272 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
52273 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78200 }
52274 },
52275/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52276 {
52277 { 0, 0, 0, 0 },
52278 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
52279 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a200 }
52280 },
52281/* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52282 {
52283 { 0, 0, 0, 0 },
52284 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
52285 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c902 }
52286 },
52287/* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52288 {
52289 { 0, 0, 0, 0 },
52290 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
52291 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18922 }
52292 },
52293/* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52294 {
52295 { 0, 0, 0, 0 },
52296 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52297 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18902 }
52298 },
52299/* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52300 {
52301 { 0, 0, 0, 0 },
52302 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
52303 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c182 }
52304 },
52305/* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52306 {
52307 { 0, 0, 0, 0 },
52308 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
52309 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a2 }
52310 },
52311/* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52312 {
52313 { 0, 0, 0, 0 },
52314 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52315 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18182 }
52316 },
52317/* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52318 {
52319 { 0, 0, 0, 0 },
52320 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52321 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c102 }
52322 },
52323/* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52324 {
52325 { 0, 0, 0, 0 },
52326 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52327 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18122 }
52328 },
52329/* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52330 {
52331 { 0, 0, 0, 0 },
52332 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52333 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18102 }
52334 },
52335/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52336 {
52337 { 0, 0, 0, 0 },
52338 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52339 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30200 }
52340 },
52341/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52342 {
52343 { 0, 0, 0, 0 },
52344 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52345 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832200 }
52346 },
52347/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52348 {
52349 { 0, 0, 0, 0 },
52350 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52351 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830200 }
52352 },
52353/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52354 {
52355 { 0, 0, 0, 0 },
52356 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52357 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50200 }
52358 },
52359/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52360 {
52361 { 0, 0, 0, 0 },
52362 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52363 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852200 }
52364 },
52365/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52366 {
52367 { 0, 0, 0, 0 },
52368 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52369 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850200 }
52370 },
52371/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52372 {
52373 { 0, 0, 0, 0 },
52374 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52375 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70200 }
52376 },
52377/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52378 {
52379 { 0, 0, 0, 0 },
52380 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52381 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872200 }
52382 },
52383/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52384 {
52385 { 0, 0, 0, 0 },
52386 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52387 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870200 }
52388 },
52389/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52390 {
52391 { 0, 0, 0, 0 },
52392 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52393 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38200 }
52394 },
52395/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52396 {
52397 { 0, 0, 0, 0 },
52398 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52399 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a200 }
52400 },
52401/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52402 {
52403 { 0, 0, 0, 0 },
52404 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52405 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838200 }
52406 },
52407/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52408 {
52409 { 0, 0, 0, 0 },
52410 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52411 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58200 }
52412 },
52413/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52414 {
52415 { 0, 0, 0, 0 },
52416 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52417 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a200 }
52418 },
52419/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52420 {
52421 { 0, 0, 0, 0 },
52422 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52423 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858200 }
52424 },
52425/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52426 {
52427 { 0, 0, 0, 0 },
52428 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52429 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c200 }
52430 },
52431/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52432 {
52433 { 0, 0, 0, 0 },
52434 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52435 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e200 }
52436 },
52437/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52438 {
52439 { 0, 0, 0, 0 },
52440 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52441 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c200 }
52442 },
52443/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52444 {
52445 { 0, 0, 0, 0 },
52446 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52447 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c200 }
52448 },
52449/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52450 {
52451 { 0, 0, 0, 0 },
52452 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52453 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e200 }
52454 },
52455/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52456 {
52457 { 0, 0, 0, 0 },
52458 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52459 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c200 }
52460 },
52461/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52462 {
52463 { 0, 0, 0, 0 },
52464 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
52465 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c200 }
52466 },
52467/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52468 {
52469 { 0, 0, 0, 0 },
52470 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
52471 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e200 }
52472 },
52473/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52474 {
52475 { 0, 0, 0, 0 },
52476 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
52477 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c200 }
52478 },
52479/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52480 {
52481 { 0, 0, 0, 0 },
52482 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
52483 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78200 }
52484 },
52485/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52486 {
52487 { 0, 0, 0, 0 },
52488 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
52489 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a200 }
52490 },
52491/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52492 {
52493 { 0, 0, 0, 0 },
52494 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
52495 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878200 }
52496 },
52497/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52498 {
52499 { 0, 0, 0, 0 },
52500 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52501 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980200 }
52502 },
52503/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
52504 {
52505 { 0, 0, 0, 0 },
52506 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52507 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982200 }
52508 },
52509/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
52510 {
52511 { 0, 0, 0, 0 },
52512 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52513 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983200 }
52514 },
52515/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52516 {
52517 { 0, 0, 0, 0 },
52518 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52519 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908200 }
52520 },
52521/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
52522 {
52523 { 0, 0, 0, 0 },
52524 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52525 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a200 }
52526 },
52527/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
52528 {
52529 { 0, 0, 0, 0 },
52530 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52531 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b200 }
52532 },
52533/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52534 {
52535 { 0, 0, 0, 0 },
52536 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52537 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900200 }
52538 },
52539/* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52540 {
52541 { 0, 0, 0, 0 },
52542 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52543 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902200 }
52544 },
52545/* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52546 {
52547 { 0, 0, 0, 0 },
52548 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52549 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903200 }
52550 },
52551/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52552 {
52553 { 0, 0, 0, 0 },
52554 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52555 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920200 }
52556 },
52557/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52558 {
52559 { 0, 0, 0, 0 },
52560 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52561 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922200 }
52562 },
52563/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52564 {
52565 { 0, 0, 0, 0 },
52566 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52567 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923200 }
52568 },
52569/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52570 {
52571 { 0, 0, 0, 0 },
52572 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52573 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940200 }
52574 },
52575/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52576 {
52577 { 0, 0, 0, 0 },
52578 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52579 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942200 }
52580 },
52581/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52582 {
52583 { 0, 0, 0, 0 },
52584 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52585 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943200 }
52586 },
52587/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52588 {
52589 { 0, 0, 0, 0 },
52590 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52591 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960200 }
52592 },
52593/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52594 {
52595 { 0, 0, 0, 0 },
52596 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52597 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962200 }
52598 },
52599/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52600 {
52601 { 0, 0, 0, 0 },
52602 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52603 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963200 }
52604 },
52605/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52606 {
52607 { 0, 0, 0, 0 },
52608 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52609 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928200 }
52610 },
52611/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52612 {
52613 { 0, 0, 0, 0 },
52614 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52615 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a200 }
52616 },
52617/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52618 {
52619 { 0, 0, 0, 0 },
52620 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52621 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b200 }
52622 },
52623/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52624 {
52625 { 0, 0, 0, 0 },
52626 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52627 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948200 }
52628 },
52629/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52630 {
52631 { 0, 0, 0, 0 },
52632 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52633 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a200 }
52634 },
52635/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52636 {
52637 { 0, 0, 0, 0 },
52638 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52639 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b200 }
52640 },
52641/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52642 {
52643 { 0, 0, 0, 0 },
52644 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52645 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c200 }
52646 },
52647/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52648 {
52649 { 0, 0, 0, 0 },
52650 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52651 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e200 }
52652 },
52653/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52654 {
52655 { 0, 0, 0, 0 },
52656 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52657 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f200 }
52658 },
52659/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52660 {
52661 { 0, 0, 0, 0 },
52662 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52663 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c200 }
52664 },
52665/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52666 {
52667 { 0, 0, 0, 0 },
52668 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52669 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e200 }
52670 },
52671/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52672 {
52673 { 0, 0, 0, 0 },
52674 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52675 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f200 }
52676 },
52677/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52678 {
52679 { 0, 0, 0, 0 },
52680 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
52681 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c200 }
52682 },
52683/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52684 {
52685 { 0, 0, 0, 0 },
52686 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
52687 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e200 }
52688 },
52689/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52690 {
52691 { 0, 0, 0, 0 },
52692 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
52693 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f200 }
52694 },
52695/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52696 {
52697 { 0, 0, 0, 0 },
52698 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
52699 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968200 }
52700 },
52701/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52702 {
52703 { 0, 0, 0, 0 },
52704 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
52705 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a200 }
52706 },
52707/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52708 {
52709 { 0, 0, 0, 0 },
52710 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
52711 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b200 }
52712 },
52713/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52714 {
52715 { 0, 0, 0, 0 },
52716 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52717 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80200 }
52718 },
52719/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
52720 {
52721 { 0, 0, 0, 0 },
52722 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52723 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82200 }
52724 },
52725/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
52726 {
52727 { 0, 0, 0, 0 },
52728 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52729 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83200 }
52730 },
52731/* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
52732 {
52733 { 0, 0, 0, 0 },
52734 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
52735 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83200 }
52736 },
52737/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52738 {
52739 { 0, 0, 0, 0 },
52740 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52741 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08200 }
52742 },
52743/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
52744 {
52745 { 0, 0, 0, 0 },
52746 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52747 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a200 }
52748 },
52749/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
52750 {
52751 { 0, 0, 0, 0 },
52752 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52753 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b200 }
52754 },
52755/* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
52756 {
52757 { 0, 0, 0, 0 },
52758 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
52759 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b200 }
52760 },
52761/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52762 {
52763 { 0, 0, 0, 0 },
52764 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52765 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00200 }
52766 },
52767/* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52768 {
52769 { 0, 0, 0, 0 },
52770 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52771 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02200 }
52772 },
52773/* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52774 {
52775 { 0, 0, 0, 0 },
52776 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52777 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03200 }
52778 },
52779/* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52780 {
52781 { 0, 0, 0, 0 },
52782 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52783 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03200 }
52784 },
52785/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52786 {
52787 { 0, 0, 0, 0 },
52788 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52789 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20200 }
52790 },
52791/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52792 {
52793 { 0, 0, 0, 0 },
52794 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52795 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22200 }
52796 },
52797/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52798 {
52799 { 0, 0, 0, 0 },
52800 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52801 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23200 }
52802 },
52803/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52804 {
52805 { 0, 0, 0, 0 },
52806 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52807 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23200 }
52808 },
52809/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52810 {
52811 { 0, 0, 0, 0 },
52812 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52813 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40200 }
52814 },
52815/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52816 {
52817 { 0, 0, 0, 0 },
52818 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52819 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42200 }
52820 },
52821/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52822 {
52823 { 0, 0, 0, 0 },
52824 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52825 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43200 }
52826 },
52827/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52828 {
52829 { 0, 0, 0, 0 },
52830 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52831 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43200 }
52832 },
52833/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52834 {
52835 { 0, 0, 0, 0 },
52836 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52837 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60200 }
52838 },
52839/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52840 {
52841 { 0, 0, 0, 0 },
52842 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52843 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62200 }
52844 },
52845/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52846 {
52847 { 0, 0, 0, 0 },
52848 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52849 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63200 }
52850 },
52851/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52852 {
52853 { 0, 0, 0, 0 },
52854 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52855 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63200 }
52856 },
52857/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52858 {
52859 { 0, 0, 0, 0 },
52860 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52861 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28200 }
52862 },
52863/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52864 {
52865 { 0, 0, 0, 0 },
52866 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52867 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a200 }
52868 },
52869/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52870 {
52871 { 0, 0, 0, 0 },
52872 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52873 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b200 }
52874 },
52875/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52876 {
52877 { 0, 0, 0, 0 },
52878 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52879 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b200 }
52880 },
52881/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52882 {
52883 { 0, 0, 0, 0 },
52884 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52885 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48200 }
52886 },
52887/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52888 {
52889 { 0, 0, 0, 0 },
52890 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52891 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a200 }
52892 },
52893/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52894 {
52895 { 0, 0, 0, 0 },
52896 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52897 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b200 }
52898 },
52899/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52900 {
52901 { 0, 0, 0, 0 },
52902 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52903 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b200 }
52904 },
52905/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52906 {
52907 { 0, 0, 0, 0 },
52908 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52909 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c200 }
52910 },
52911/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52912 {
52913 { 0, 0, 0, 0 },
52914 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52915 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e200 }
52916 },
52917/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52918 {
52919 { 0, 0, 0, 0 },
52920 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52921 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f200 }
52922 },
52923/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52924 {
52925 { 0, 0, 0, 0 },
52926 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52927 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f200 }
52928 },
52929/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52930 {
52931 { 0, 0, 0, 0 },
52932 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52933 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c200 }
52934 },
52935/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52936 {
52937 { 0, 0, 0, 0 },
52938 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52939 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e200 }
52940 },
52941/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52942 {
52943 { 0, 0, 0, 0 },
52944 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52945 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f200 }
52946 },
52947/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52948 {
52949 { 0, 0, 0, 0 },
52950 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52951 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f200 }
52952 },
52953/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52954 {
52955 { 0, 0, 0, 0 },
52956 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
52957 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c200 }
52958 },
52959/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52960 {
52961 { 0, 0, 0, 0 },
52962 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52963 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e200 }
52964 },
52965/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52966 {
52967 { 0, 0, 0, 0 },
52968 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52969 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f200 }
52970 },
52971/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
52972 {
52973 { 0, 0, 0, 0 },
52974 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
52975 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f200 }
52976 },
52977/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52978 {
52979 { 0, 0, 0, 0 },
52980 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
52981 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68200 }
52982 },
52983/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52984 {
52985 { 0, 0, 0, 0 },
52986 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52987 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a200 }
52988 },
52989/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52990 {
52991 { 0, 0, 0, 0 },
52992 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52993 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b200 }
52994 },
52995/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
52996 {
52997 { 0, 0, 0, 0 },
52998 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
52999 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b200 }
53000 },
53001/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53002 {
53003 { 0, 0, 0, 0 },
53004 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53005 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80200 }
53006 },
53007/* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53008 {
53009 { 0, 0, 0, 0 },
53010 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
53011 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82200 }
53012 },
53013/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53014 {
53015 { 0, 0, 0, 0 },
53016 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53017 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08200 }
53018 },
53019/* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53020 {
53021 { 0, 0, 0, 0 },
53022 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
53023 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a200 }
53024 },
53025/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53026 {
53027 { 0, 0, 0, 0 },
53028 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53029 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00200 }
53030 },
53031/* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53032 {
53033 { 0, 0, 0, 0 },
53034 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53035 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02200 }
53036 },
53037/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53038 {
53039 { 0, 0, 0, 0 },
53040 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53041 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20200 }
53042 },
53043/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53044 {
53045 { 0, 0, 0, 0 },
53046 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53047 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22200 }
53048 },
53049/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53050 {
53051 { 0, 0, 0, 0 },
53052 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53053 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40200 }
53054 },
53055/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53056 {
53057 { 0, 0, 0, 0 },
53058 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53059 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42200 }
53060 },
53061/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53062 {
53063 { 0, 0, 0, 0 },
53064 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53065 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60200 }
53066 },
53067/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53068 {
53069 { 0, 0, 0, 0 },
53070 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53071 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62200 }
53072 },
53073/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53074 {
53075 { 0, 0, 0, 0 },
53076 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
53077 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28200 }
53078 },
53079/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53080 {
53081 { 0, 0, 0, 0 },
53082 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
53083 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a200 }
53084 },
53085/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53086 {
53087 { 0, 0, 0, 0 },
53088 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
53089 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48200 }
53090 },
53091/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53092 {
53093 { 0, 0, 0, 0 },
53094 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
53095 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a200 }
53096 },
53097/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53098 {
53099 { 0, 0, 0, 0 },
53100 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
53101 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c200 }
53102 },
53103/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53104 {
53105 { 0, 0, 0, 0 },
53106 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
53107 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e200 }
53108 },
53109/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53110 {
53111 { 0, 0, 0, 0 },
53112 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
53113 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c200 }
53114 },
53115/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53116 {
53117 { 0, 0, 0, 0 },
53118 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
53119 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e200 }
53120 },
53121/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53122 {
53123 { 0, 0, 0, 0 },
53124 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
53125 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c200 }
53126 },
53127/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53128 {
53129 { 0, 0, 0, 0 },
53130 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
53131 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e200 }
53132 },
53133/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53134 {
53135 { 0, 0, 0, 0 },
53136 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
53137 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68200 }
53138 },
53139/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53140 {
53141 { 0, 0, 0, 0 },
53142 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
53143 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a200 }
53144 },
53145/* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53146 {
53147 { 0, 0, 0, 0 },
53148 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53149 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c802 }
53150 },
53151/* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53152 {
53153 { 0, 0, 0, 0 },
53154 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53155 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18822 }
53156 },
53157/* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53158 {
53159 { 0, 0, 0, 0 },
53160 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53161 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18802 }
53162 },
53163/* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53164 {
53165 { 0, 0, 0, 0 },
53166 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53167 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c082 }
53168 },
53169/* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53170 {
53171 { 0, 0, 0, 0 },
53172 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53173 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a2 }
53174 },
53175/* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53176 {
53177 { 0, 0, 0, 0 },
53178 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53179 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18082 }
53180 },
53181/* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53182 {
53183 { 0, 0, 0, 0 },
53184 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53185 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c002 }
53186 },
53187/* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53188 {
53189 { 0, 0, 0, 0 },
53190 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53191 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18022 }
53192 },
53193/* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53194 {
53195 { 0, 0, 0, 0 },
53196 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53197 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18002 }
53198 },
53199/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53200 {
53201 { 0, 0, 0, 0 },
53202 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53203 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20200 }
53204 },
53205/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53206 {
53207 { 0, 0, 0, 0 },
53208 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53209 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822200 }
53210 },
53211/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53212 {
53213 { 0, 0, 0, 0 },
53214 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53215 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820200 }
53216 },
53217/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53218 {
53219 { 0, 0, 0, 0 },
53220 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53221 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40200 }
53222 },
53223/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53224 {
53225 { 0, 0, 0, 0 },
53226 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53227 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842200 }
53228 },
53229/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53230 {
53231 { 0, 0, 0, 0 },
53232 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53233 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840200 }
53234 },
53235/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53236 {
53237 { 0, 0, 0, 0 },
53238 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53239 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60200 }
53240 },
53241/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53242 {
53243 { 0, 0, 0, 0 },
53244 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53245 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862200 }
53246 },
53247/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53248 {
53249 { 0, 0, 0, 0 },
53250 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53251 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860200 }
53252 },
53253/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53254 {
53255 { 0, 0, 0, 0 },
53256 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53257 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28200 }
53258 },
53259/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53260 {
53261 { 0, 0, 0, 0 },
53262 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53263 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a200 }
53264 },
53265/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53266 {
53267 { 0, 0, 0, 0 },
53268 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53269 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828200 }
53270 },
53271/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53272 {
53273 { 0, 0, 0, 0 },
53274 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53275 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48200 }
53276 },
53277/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53278 {
53279 { 0, 0, 0, 0 },
53280 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53281 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a200 }
53282 },
53283/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53284 {
53285 { 0, 0, 0, 0 },
53286 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53287 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848200 }
53288 },
53289/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53290 {
53291 { 0, 0, 0, 0 },
53292 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53293 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c200 }
53294 },
53295/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53296 {
53297 { 0, 0, 0, 0 },
53298 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53299 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e200 }
53300 },
53301/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53302 {
53303 { 0, 0, 0, 0 },
53304 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53305 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c200 }
53306 },
53307/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53308 {
53309 { 0, 0, 0, 0 },
53310 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53311 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c200 }
53312 },
53313/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53314 {
53315 { 0, 0, 0, 0 },
53316 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53317 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e200 }
53318 },
53319/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53320 {
53321 { 0, 0, 0, 0 },
53322 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53323 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c200 }
53324 },
53325/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53326 {
53327 { 0, 0, 0, 0 },
53328 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
53329 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c200 }
53330 },
53331/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53332 {
53333 { 0, 0, 0, 0 },
53334 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
53335 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e200 }
53336 },
53337/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53338 {
53339 { 0, 0, 0, 0 },
53340 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
53341 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c200 }
53342 },
53343/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53344 {
53345 { 0, 0, 0, 0 },
53346 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
53347 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68200 }
53348 },
53349/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53350 {
53351 { 0, 0, 0, 0 },
53352 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
53353 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a200 }
53354 },
53355/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53356 {
53357 { 0, 0, 0, 0 },
53358 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
53359 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868200 }
53360 },
53361/* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53362 {
53363 { 0, 0, 0, 0 },
53364 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
53365 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1991e00 }
53366 },
53367/* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53368 {
53369 { 0, 0, 0, 0 },
53370 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
53371 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1919e00 }
53372 },
53373/* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53374 {
53375 { 0, 0, 0, 0 },
53376 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53377 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1911e00 }
53378 },
53379/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53380 {
53381 { 0, 0, 0, 0 },
53382 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53383 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1931e00 }
53384 },
53385/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53386 {
53387 { 0, 0, 0, 0 },
53388 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53389 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1939e00 }
53390 },
53391/* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53392 {
53393 { 0, 0, 0, 0 },
53394 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53395 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193de00 }
53396 },
53397/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53398 {
53399 { 0, 0, 0, 0 },
53400 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53401 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1951e00 }
53402 },
53403/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53404 {
53405 { 0, 0, 0, 0 },
53406 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53407 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1959e00 }
53408 },
53409/* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53410 {
53411 { 0, 0, 0, 0 },
53412 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53413 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195de00 }
53414 },
53415/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53416 {
53417 { 0, 0, 0, 0 },
53418 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
53419 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197de00 }
53420 },
53421/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53422 {
53423 { 0, 0, 0, 0 },
53424 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53425 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1971e00 }
53426 },
53427/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53428 {
53429 { 0, 0, 0, 0 },
53430 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
53431 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1979e00 }
53432 },
53433/* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53434 {
53435 { 0, 0, 0, 0 },
53436 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53437 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1981e00 }
53438 },
53439/* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53440 {
53441 { 0, 0, 0, 0 },
53442 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53443 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1909e00 }
53444 },
53445/* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53446 {
53447 { 0, 0, 0, 0 },
53448 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53449 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1901e00 }
53450 },
53451/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53452 {
53453 { 0, 0, 0, 0 },
53454 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53455 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1921e00 }
53456 },
53457/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53458 {
53459 { 0, 0, 0, 0 },
53460 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53461 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1929e00 }
53462 },
53463/* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53464 {
53465 { 0, 0, 0, 0 },
53466 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53467 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192de00 }
53468 },
53469/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53470 {
53471 { 0, 0, 0, 0 },
53472 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53473 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1941e00 }
53474 },
53475/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53476 {
53477 { 0, 0, 0, 0 },
53478 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53479 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1949e00 }
53480 },
53481/* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53482 {
53483 { 0, 0, 0, 0 },
53484 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53485 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194de00 }
53486 },
53487/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53488 {
53489 { 0, 0, 0, 0 },
53490 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
53491 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196de00 }
53492 },
53493/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53494 {
53495 { 0, 0, 0, 0 },
53496 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53497 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1961e00 }
53498 },
53499/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53500 {
53501 { 0, 0, 0, 0 },
53502 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
53503 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1969e00 }
53504 },
53505/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53506 {
53507 { 0, 0, 0, 0 },
53508 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53509 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990a00 }
53510 },
53511/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53512 {
53513 { 0, 0, 0, 0 },
53514 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53515 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992a00 }
53516 },
53517/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53518 {
53519 { 0, 0, 0, 0 },
53520 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53521 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993a00 }
53522 },
53523/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53524 {
53525 { 0, 0, 0, 0 },
53526 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53527 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918a00 }
53528 },
53529/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53530 {
53531 { 0, 0, 0, 0 },
53532 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53533 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191aa00 }
53534 },
53535/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53536 {
53537 { 0, 0, 0, 0 },
53538 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53539 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ba00 }
53540 },
53541/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53542 {
53543 { 0, 0, 0, 0 },
53544 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53545 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910a00 }
53546 },
53547/* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53548 {
53549 { 0, 0, 0, 0 },
53550 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53551 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912a00 }
53552 },
53553/* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53554 {
53555 { 0, 0, 0, 0 },
53556 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53557 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913a00 }
53558 },
53559/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53560 {
53561 { 0, 0, 0, 0 },
53562 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53563 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930a00 }
53564 },
53565/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53566 {
53567 { 0, 0, 0, 0 },
53568 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53569 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932a00 }
53570 },
53571/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53572 {
53573 { 0, 0, 0, 0 },
53574 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53575 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933a00 }
53576 },
53577/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53578 {
53579 { 0, 0, 0, 0 },
53580 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53581 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950a00 }
53582 },
53583/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53584 {
53585 { 0, 0, 0, 0 },
53586 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53587 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952a00 }
53588 },
53589/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53590 {
53591 { 0, 0, 0, 0 },
53592 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53593 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953a00 }
53594 },
53595/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53596 {
53597 { 0, 0, 0, 0 },
53598 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53599 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970a00 }
53600 },
53601/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53602 {
53603 { 0, 0, 0, 0 },
53604 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53605 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972a00 }
53606 },
53607/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53608 {
53609 { 0, 0, 0, 0 },
53610 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53611 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973a00 }
53612 },
53613/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53614 {
53615 { 0, 0, 0, 0 },
53616 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
53617 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938a00 }
53618 },
53619/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53620 {
53621 { 0, 0, 0, 0 },
53622 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
53623 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193aa00 }
53624 },
53625/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53626 {
53627 { 0, 0, 0, 0 },
53628 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
53629 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ba00 }
53630 },
53631/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53632 {
53633 { 0, 0, 0, 0 },
53634 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53635 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958a00 }
53636 },
53637/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53638 {
53639 { 0, 0, 0, 0 },
53640 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53641 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195aa00 }
53642 },
53643/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53644 {
53645 { 0, 0, 0, 0 },
53646 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53647 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ba00 }
53648 },
53649/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53650 {
53651 { 0, 0, 0, 0 },
53652 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53653 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ca00 }
53654 },
53655/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53656 {
53657 { 0, 0, 0, 0 },
53658 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53659 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ea00 }
53660 },
53661/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53662 {
53663 { 0, 0, 0, 0 },
53664 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53665 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fa00 }
53666 },
53667/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53668 {
53669 { 0, 0, 0, 0 },
53670 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53671 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ca00 }
53672 },
53673/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53674 {
53675 { 0, 0, 0, 0 },
53676 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53677 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ea00 }
53678 },
53679/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53680 {
53681 { 0, 0, 0, 0 },
53682 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53683 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fa00 }
53684 },
53685/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53686 {
53687 { 0, 0, 0, 0 },
53688 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
53689 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ca00 }
53690 },
53691/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53692 {
53693 { 0, 0, 0, 0 },
53694 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
53695 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ea00 }
53696 },
53697/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53698 {
53699 { 0, 0, 0, 0 },
53700 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
53701 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fa00 }
53702 },
53703/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53704 {
53705 { 0, 0, 0, 0 },
53706 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
53707 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978a00 }
53708 },
53709/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53710 {
53711 { 0, 0, 0, 0 },
53712 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
53713 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197aa00 }
53714 },
53715/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53716 {
53717 { 0, 0, 0, 0 },
53718 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
53719 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ba00 }
53720 },
53721/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53722 {
53723 { 0, 0, 0, 0 },
53724 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53725 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90a00 }
53726 },
53727/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
53728 {
53729 { 0, 0, 0, 0 },
53730 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53731 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92a00 }
53732 },
53733/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
53734 {
53735 { 0, 0, 0, 0 },
53736 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53737 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93a00 }
53738 },
53739/* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
53740 {
53741 { 0, 0, 0, 0 },
53742 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
53743 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93a00 }
53744 },
53745/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53746 {
53747 { 0, 0, 0, 0 },
53748 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53749 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18a00 }
53750 },
53751/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
53752 {
53753 { 0, 0, 0, 0 },
53754 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53755 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1aa00 }
53756 },
53757/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
53758 {
53759 { 0, 0, 0, 0 },
53760 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53761 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ba00 }
53762 },
53763/* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
53764 {
53765 { 0, 0, 0, 0 },
53766 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
53767 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ba00 }
53768 },
53769/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53770 {
53771 { 0, 0, 0, 0 },
53772 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53773 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10a00 }
53774 },
53775/* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53776 {
53777 { 0, 0, 0, 0 },
53778 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53779 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12a00 }
53780 },
53781/* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53782 {
53783 { 0, 0, 0, 0 },
53784 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53785 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13a00 }
53786 },
53787/* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53788 {
53789 { 0, 0, 0, 0 },
53790 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53791 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13a00 }
53792 },
53793/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53794 {
53795 { 0, 0, 0, 0 },
53796 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53797 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30a00 }
53798 },
53799/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53800 {
53801 { 0, 0, 0, 0 },
53802 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53803 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32a00 }
53804 },
53805/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53806 {
53807 { 0, 0, 0, 0 },
53808 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53809 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33a00 }
53810 },
53811/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53812 {
53813 { 0, 0, 0, 0 },
53814 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53815 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33a00 }
53816 },
53817/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53818 {
53819 { 0, 0, 0, 0 },
53820 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53821 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50a00 }
53822 },
53823/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53824 {
53825 { 0, 0, 0, 0 },
53826 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53827 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52a00 }
53828 },
53829/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53830 {
53831 { 0, 0, 0, 0 },
53832 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53833 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53a00 }
53834 },
53835/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53836 {
53837 { 0, 0, 0, 0 },
53838 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53839 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53a00 }
53840 },
53841/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53842 {
53843 { 0, 0, 0, 0 },
53844 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53845 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70a00 }
53846 },
53847/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53848 {
53849 { 0, 0, 0, 0 },
53850 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53851 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72a00 }
53852 },
53853/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53854 {
53855 { 0, 0, 0, 0 },
53856 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53857 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73a00 }
53858 },
53859/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53860 {
53861 { 0, 0, 0, 0 },
53862 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53863 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73a00 }
53864 },
53865/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53866 {
53867 { 0, 0, 0, 0 },
53868 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53869 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38a00 }
53870 },
53871/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53872 {
53873 { 0, 0, 0, 0 },
53874 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53875 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3aa00 }
53876 },
53877/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53878 {
53879 { 0, 0, 0, 0 },
53880 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53881 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ba00 }
53882 },
53883/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53884 {
53885 { 0, 0, 0, 0 },
53886 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53887 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3ba00 }
53888 },
53889/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53890 {
53891 { 0, 0, 0, 0 },
53892 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53893 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58a00 }
53894 },
53895/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53896 {
53897 { 0, 0, 0, 0 },
53898 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53899 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5aa00 }
53900 },
53901/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53902 {
53903 { 0, 0, 0, 0 },
53904 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53905 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ba00 }
53906 },
53907/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53908 {
53909 { 0, 0, 0, 0 },
53910 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53911 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5ba00 }
53912 },
53913/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53914 {
53915 { 0, 0, 0, 0 },
53916 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53917 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ca00 }
53918 },
53919/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53920 {
53921 { 0, 0, 0, 0 },
53922 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53923 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ea00 }
53924 },
53925/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53926 {
53927 { 0, 0, 0, 0 },
53928 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53929 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fa00 }
53930 },
53931/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53932 {
53933 { 0, 0, 0, 0 },
53934 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53935 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fa00 }
53936 },
53937/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53938 {
53939 { 0, 0, 0, 0 },
53940 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53941 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ca00 }
53942 },
53943/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53944 {
53945 { 0, 0, 0, 0 },
53946 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53947 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ea00 }
53948 },
53949/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53950 {
53951 { 0, 0, 0, 0 },
53952 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53953 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fa00 }
53954 },
53955/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53956 {
53957 { 0, 0, 0, 0 },
53958 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53959 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fa00 }
53960 },
53961/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53962 {
53963 { 0, 0, 0, 0 },
53964 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
53965 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ca00 }
53966 },
53967/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53968 {
53969 { 0, 0, 0, 0 },
53970 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
53971 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ea00 }
53972 },
53973/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53974 {
53975 { 0, 0, 0, 0 },
53976 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
53977 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fa00 }
53978 },
53979/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
53980 {
53981 { 0, 0, 0, 0 },
53982 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
53983 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fa00 }
53984 },
53985/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53986 {
53987 { 0, 0, 0, 0 },
53988 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
53989 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78a00 }
53990 },
53991/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53992 {
53993 { 0, 0, 0, 0 },
53994 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
53995 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7aa00 }
53996 },
53997/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53998 {
53999 { 0, 0, 0, 0 },
54000 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
54001 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ba00 }
54002 },
54003/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
54004 {
54005 { 0, 0, 0, 0 },
54006 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
54007 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7ba00 }
54008 },
54009/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54010 {
54011 { 0, 0, 0, 0 },
54012 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54013 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90a00 }
54014 },
54015/* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
54016 {
54017 { 0, 0, 0, 0 },
54018 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
54019 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92a00 }
54020 },
54021/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54022 {
54023 { 0, 0, 0, 0 },
54024 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54025 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18a00 }
54026 },
54027/* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
54028 {
54029 { 0, 0, 0, 0 },
54030 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
54031 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1aa00 }
54032 },
54033/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54034 {
54035 { 0, 0, 0, 0 },
54036 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54037 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10a00 }
54038 },
54039/* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54040 {
54041 { 0, 0, 0, 0 },
54042 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54043 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12a00 }
54044 },
54045/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54046 {
54047 { 0, 0, 0, 0 },
54048 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54049 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30a00 }
54050 },
54051/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54052 {
54053 { 0, 0, 0, 0 },
54054 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54055 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32a00 }
54056 },
54057/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54058 {
54059 { 0, 0, 0, 0 },
54060 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54061 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50a00 }
54062 },
54063/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54064 {
54065 { 0, 0, 0, 0 },
54066 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54067 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52a00 }
54068 },
54069/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54070 {
54071 { 0, 0, 0, 0 },
54072 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54073 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70a00 }
54074 },
54075/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54076 {
54077 { 0, 0, 0, 0 },
54078 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54079 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72a00 }
54080 },
54081/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54082 {
54083 { 0, 0, 0, 0 },
54084 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54085 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38a00 }
54086 },
54087/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54088 {
54089 { 0, 0, 0, 0 },
54090 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54091 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3aa00 }
54092 },
54093/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54094 {
54095 { 0, 0, 0, 0 },
54096 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54097 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58a00 }
54098 },
54099/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54100 {
54101 { 0, 0, 0, 0 },
54102 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54103 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5aa00 }
54104 },
54105/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54106 {
54107 { 0, 0, 0, 0 },
54108 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54109 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ca00 }
54110 },
54111/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54112 {
54113 { 0, 0, 0, 0 },
54114 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54115 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ea00 }
54116 },
54117/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54118 {
54119 { 0, 0, 0, 0 },
54120 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54121 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ca00 }
54122 },
54123/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54124 {
54125 { 0, 0, 0, 0 },
54126 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54127 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ea00 }
54128 },
54129/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54130 {
54131 { 0, 0, 0, 0 },
54132 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
54133 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ca00 }
54134 },
54135/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
54136 {
54137 { 0, 0, 0, 0 },
54138 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
54139 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ea00 }
54140 },
54141/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54142 {
54143 { 0, 0, 0, 0 },
54144 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
54145 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78a00 }
54146 },
54147/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
54148 {
54149 { 0, 0, 0, 0 },
54150 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
54151 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7aa00 }
54152 },
54153/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
54154 {
54155 { 0, 0, 0, 0 },
54156 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
54157 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90a }
54158 },
54159/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
54160 {
54161 { 0, 0, 0, 0 },
54162 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
54163 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892a }
54164 },
54165/* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
54166 {
54167 { 0, 0, 0, 0 },
54168 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54169 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890a }
54170 },
54171/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
54172 {
54173 { 0, 0, 0, 0 },
54174 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
54175 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18a }
54176 },
54177/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
54178 {
54179 { 0, 0, 0, 0 },
54180 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
54181 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181aa }
54182 },
54183/* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
54184 {
54185 { 0, 0, 0, 0 },
54186 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54187 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818a }
54188 },
54189/* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
54190 {
54191 { 0, 0, 0, 0 },
54192 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54193 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10a }
54194 },
54195/* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
54196 {
54197 { 0, 0, 0, 0 },
54198 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54199 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812a }
54200 },
54201/* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54202 {
54203 { 0, 0, 0, 0 },
54204 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54205 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810a }
54206 },
54207/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54208 {
54209 { 0, 0, 0, 0 },
54210 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54211 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30a00 }
54212 },
54213/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54214 {
54215 { 0, 0, 0, 0 },
54216 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54217 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832a00 }
54218 },
54219/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54220 {
54221 { 0, 0, 0, 0 },
54222 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54223 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830a00 }
54224 },
54225/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54226 {
54227 { 0, 0, 0, 0 },
54228 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54229 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50a00 }
54230 },
54231/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54232 {
54233 { 0, 0, 0, 0 },
54234 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54235 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852a00 }
54236 },
54237/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54238 {
54239 { 0, 0, 0, 0 },
54240 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54241 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850a00 }
54242 },
54243/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54244 {
54245 { 0, 0, 0, 0 },
54246 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54247 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70a00 }
54248 },
54249/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54250 {
54251 { 0, 0, 0, 0 },
54252 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54253 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872a00 }
54254 },
54255/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54256 {
54257 { 0, 0, 0, 0 },
54258 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54259 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870a00 }
54260 },
54261/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54262 {
54263 { 0, 0, 0, 0 },
54264 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54265 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38a00 }
54266 },
54267/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54268 {
54269 { 0, 0, 0, 0 },
54270 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54271 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183aa00 }
54272 },
54273/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54274 {
54275 { 0, 0, 0, 0 },
54276 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54277 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838a00 }
54278 },
54279/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54280 {
54281 { 0, 0, 0, 0 },
54282 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54283 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58a00 }
54284 },
54285/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54286 {
54287 { 0, 0, 0, 0 },
54288 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54289 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185aa00 }
54290 },
54291/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54292 {
54293 { 0, 0, 0, 0 },
54294 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54295 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858a00 }
54296 },
54297/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54298 {
54299 { 0, 0, 0, 0 },
54300 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54301 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3ca00 }
54302 },
54303/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54304 {
54305 { 0, 0, 0, 0 },
54306 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54307 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ea00 }
54308 },
54309/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54310 {
54311 { 0, 0, 0, 0 },
54312 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54313 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ca00 }
54314 },
54315/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54316 {
54317 { 0, 0, 0, 0 },
54318 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54319 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5ca00 }
54320 },
54321/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54322 {
54323 { 0, 0, 0, 0 },
54324 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54325 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ea00 }
54326 },
54327/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54328 {
54329 { 0, 0, 0, 0 },
54330 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54331 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ca00 }
54332 },
54333/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54334 {
54335 { 0, 0, 0, 0 },
54336 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
54337 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7ca00 }
54338 },
54339/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54340 {
54341 { 0, 0, 0, 0 },
54342 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
54343 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ea00 }
54344 },
54345/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54346 {
54347 { 0, 0, 0, 0 },
54348 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
54349 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ca00 }
54350 },
54351/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54352 {
54353 { 0, 0, 0, 0 },
54354 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
54355 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78a00 }
54356 },
54357/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54358 {
54359 { 0, 0, 0, 0 },
54360 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
54361 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187aa00 }
54362 },
54363/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54364 {
54365 { 0, 0, 0, 0 },
54366 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
54367 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878a00 }
54368 },
54369/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54370 {
54371 { 0, 0, 0, 0 },
54372 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54373 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980a00 }
54374 },
54375/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54376 {
54377 { 0, 0, 0, 0 },
54378 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54379 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982a00 }
54380 },
54381/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54382 {
54383 { 0, 0, 0, 0 },
54384 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54385 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983a00 }
54386 },
54387/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54388 {
54389 { 0, 0, 0, 0 },
54390 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54391 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908a00 }
54392 },
54393/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54394 {
54395 { 0, 0, 0, 0 },
54396 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54397 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190aa00 }
54398 },
54399/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54400 {
54401 { 0, 0, 0, 0 },
54402 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54403 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ba00 }
54404 },
54405/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54406 {
54407 { 0, 0, 0, 0 },
54408 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54409 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900a00 }
54410 },
54411/* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54412 {
54413 { 0, 0, 0, 0 },
54414 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54415 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902a00 }
54416 },
54417/* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54418 {
54419 { 0, 0, 0, 0 },
54420 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54421 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903a00 }
54422 },
54423/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54424 {
54425 { 0, 0, 0, 0 },
54426 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54427 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920a00 }
54428 },
54429/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54430 {
54431 { 0, 0, 0, 0 },
54432 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54433 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922a00 }
54434 },
54435/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54436 {
54437 { 0, 0, 0, 0 },
54438 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54439 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923a00 }
54440 },
54441/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54442 {
54443 { 0, 0, 0, 0 },
54444 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54445 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940a00 }
54446 },
54447/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54448 {
54449 { 0, 0, 0, 0 },
54450 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54451 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942a00 }
54452 },
54453/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54454 {
54455 { 0, 0, 0, 0 },
54456 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54457 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943a00 }
54458 },
54459/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54460 {
54461 { 0, 0, 0, 0 },
54462 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54463 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960a00 }
54464 },
54465/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54466 {
54467 { 0, 0, 0, 0 },
54468 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54469 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962a00 }
54470 },
54471/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54472 {
54473 { 0, 0, 0, 0 },
54474 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54475 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963a00 }
54476 },
54477/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54478 {
54479 { 0, 0, 0, 0 },
54480 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54481 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928a00 }
54482 },
54483/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54484 {
54485 { 0, 0, 0, 0 },
54486 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54487 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192aa00 }
54488 },
54489/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54490 {
54491 { 0, 0, 0, 0 },
54492 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54493 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ba00 }
54494 },
54495/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54496 {
54497 { 0, 0, 0, 0 },
54498 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54499 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948a00 }
54500 },
54501/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54502 {
54503 { 0, 0, 0, 0 },
54504 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54505 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194aa00 }
54506 },
54507/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54508 {
54509 { 0, 0, 0, 0 },
54510 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54511 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ba00 }
54512 },
54513/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54514 {
54515 { 0, 0, 0, 0 },
54516 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54517 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ca00 }
54518 },
54519/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54520 {
54521 { 0, 0, 0, 0 },
54522 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54523 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ea00 }
54524 },
54525/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54526 {
54527 { 0, 0, 0, 0 },
54528 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54529 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fa00 }
54530 },
54531/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54532 {
54533 { 0, 0, 0, 0 },
54534 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54535 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ca00 }
54536 },
54537/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54538 {
54539 { 0, 0, 0, 0 },
54540 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54541 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ea00 }
54542 },
54543/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54544 {
54545 { 0, 0, 0, 0 },
54546 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54547 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fa00 }
54548 },
54549/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54550 {
54551 { 0, 0, 0, 0 },
54552 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
54553 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ca00 }
54554 },
54555/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54556 {
54557 { 0, 0, 0, 0 },
54558 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54559 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ea00 }
54560 },
54561/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54562 {
54563 { 0, 0, 0, 0 },
54564 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54565 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fa00 }
54566 },
54567/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54568 {
54569 { 0, 0, 0, 0 },
54570 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
54571 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968a00 }
54572 },
54573/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54574 {
54575 { 0, 0, 0, 0 },
54576 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54577 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196aa00 }
54578 },
54579/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54580 {
54581 { 0, 0, 0, 0 },
54582 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54583 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ba00 }
54584 },
54585/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54586 {
54587 { 0, 0, 0, 0 },
54588 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54589 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80a00 }
54590 },
54591/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54592 {
54593 { 0, 0, 0, 0 },
54594 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54595 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82a00 }
54596 },
54597/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54598 {
54599 { 0, 0, 0, 0 },
54600 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54601 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83a00 }
54602 },
54603/* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54604 {
54605 { 0, 0, 0, 0 },
54606 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
54607 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83a00 }
54608 },
54609/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54610 {
54611 { 0, 0, 0, 0 },
54612 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54613 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08a00 }
54614 },
54615/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
54616 {
54617 { 0, 0, 0, 0 },
54618 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54619 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0aa00 }
54620 },
54621/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
54622 {
54623 { 0, 0, 0, 0 },
54624 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54625 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ba00 }
54626 },
54627/* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
54628 {
54629 { 0, 0, 0, 0 },
54630 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
54631 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ba00 }
54632 },
54633/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54634 {
54635 { 0, 0, 0, 0 },
54636 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54637 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00a00 }
54638 },
54639/* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54640 {
54641 { 0, 0, 0, 0 },
54642 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54643 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02a00 }
54644 },
54645/* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54646 {
54647 { 0, 0, 0, 0 },
54648 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54649 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03a00 }
54650 },
54651/* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54652 {
54653 { 0, 0, 0, 0 },
54654 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54655 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03a00 }
54656 },
54657/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54658 {
54659 { 0, 0, 0, 0 },
54660 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54661 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20a00 }
54662 },
54663/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54664 {
54665 { 0, 0, 0, 0 },
54666 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54667 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22a00 }
54668 },
54669/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54670 {
54671 { 0, 0, 0, 0 },
54672 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54673 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23a00 }
54674 },
54675/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54676 {
54677 { 0, 0, 0, 0 },
54678 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54679 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23a00 }
54680 },
54681/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54682 {
54683 { 0, 0, 0, 0 },
54684 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54685 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40a00 }
54686 },
54687/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54688 {
54689 { 0, 0, 0, 0 },
54690 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54691 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42a00 }
54692 },
54693/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54694 {
54695 { 0, 0, 0, 0 },
54696 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54697 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43a00 }
54698 },
54699/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54700 {
54701 { 0, 0, 0, 0 },
54702 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54703 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43a00 }
54704 },
54705/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54706 {
54707 { 0, 0, 0, 0 },
54708 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54709 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60a00 }
54710 },
54711/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54712 {
54713 { 0, 0, 0, 0 },
54714 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54715 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62a00 }
54716 },
54717/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54718 {
54719 { 0, 0, 0, 0 },
54720 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54721 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63a00 }
54722 },
54723/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54724 {
54725 { 0, 0, 0, 0 },
54726 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54727 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63a00 }
54728 },
54729/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54730 {
54731 { 0, 0, 0, 0 },
54732 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54733 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28a00 }
54734 },
54735/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54736 {
54737 { 0, 0, 0, 0 },
54738 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54739 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2aa00 }
54740 },
54741/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54742 {
54743 { 0, 0, 0, 0 },
54744 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54745 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ba00 }
54746 },
54747/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54748 {
54749 { 0, 0, 0, 0 },
54750 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54751 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2ba00 }
54752 },
54753/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54754 {
54755 { 0, 0, 0, 0 },
54756 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54757 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48a00 }
54758 },
54759/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54760 {
54761 { 0, 0, 0, 0 },
54762 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54763 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4aa00 }
54764 },
54765/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54766 {
54767 { 0, 0, 0, 0 },
54768 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54769 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ba00 }
54770 },
54771/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54772 {
54773 { 0, 0, 0, 0 },
54774 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54775 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4ba00 }
54776 },
54777/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54778 {
54779 { 0, 0, 0, 0 },
54780 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54781 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ca00 }
54782 },
54783/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54784 {
54785 { 0, 0, 0, 0 },
54786 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54787 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ea00 }
54788 },
54789/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54790 {
54791 { 0, 0, 0, 0 },
54792 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54793 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fa00 }
54794 },
54795/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54796 {
54797 { 0, 0, 0, 0 },
54798 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54799 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fa00 }
54800 },
54801/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54802 {
54803 { 0, 0, 0, 0 },
54804 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54805 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ca00 }
54806 },
54807/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54808 {
54809 { 0, 0, 0, 0 },
54810 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54811 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ea00 }
54812 },
54813/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54814 {
54815 { 0, 0, 0, 0 },
54816 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54817 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fa00 }
54818 },
54819/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54820 {
54821 { 0, 0, 0, 0 },
54822 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54823 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fa00 }
54824 },
54825/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54826 {
54827 { 0, 0, 0, 0 },
54828 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
54829 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ca00 }
54830 },
54831/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54832 {
54833 { 0, 0, 0, 0 },
54834 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
54835 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ea00 }
54836 },
54837/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54838 {
54839 { 0, 0, 0, 0 },
54840 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
54841 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fa00 }
54842 },
54843/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
54844 {
54845 { 0, 0, 0, 0 },
54846 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
54847 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fa00 }
54848 },
54849/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54850 {
54851 { 0, 0, 0, 0 },
54852 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
54853 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68a00 }
54854 },
54855/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54856 {
54857 { 0, 0, 0, 0 },
54858 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
54859 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6aa00 }
54860 },
54861/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54862 {
54863 { 0, 0, 0, 0 },
54864 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
54865 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ba00 }
54866 },
54867/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
54868 {
54869 { 0, 0, 0, 0 },
54870 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
54871 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6ba00 }
54872 },
54873/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54874 {
54875 { 0, 0, 0, 0 },
54876 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54877 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80a00 }
54878 },
54879/* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
54880 {
54881 { 0, 0, 0, 0 },
54882 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
54883 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82a00 }
54884 },
54885/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54886 {
54887 { 0, 0, 0, 0 },
54888 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54889 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08a00 }
54890 },
54891/* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
54892 {
54893 { 0, 0, 0, 0 },
54894 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
54895 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0aa00 }
54896 },
54897/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54898 {
54899 { 0, 0, 0, 0 },
54900 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54901 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00a00 }
54902 },
54903/* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54904 {
54905 { 0, 0, 0, 0 },
54906 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54907 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02a00 }
54908 },
54909/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54910 {
54911 { 0, 0, 0, 0 },
54912 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54913 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20a00 }
54914 },
54915/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54916 {
54917 { 0, 0, 0, 0 },
54918 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54919 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22a00 }
54920 },
54921/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54922 {
54923 { 0, 0, 0, 0 },
54924 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54925 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40a00 }
54926 },
54927/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54928 {
54929 { 0, 0, 0, 0 },
54930 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54931 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42a00 }
54932 },
54933/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54934 {
54935 { 0, 0, 0, 0 },
54936 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54937 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60a00 }
54938 },
54939/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54940 {
54941 { 0, 0, 0, 0 },
54942 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54943 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62a00 }
54944 },
54945/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54946 {
54947 { 0, 0, 0, 0 },
54948 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54949 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28a00 }
54950 },
54951/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54952 {
54953 { 0, 0, 0, 0 },
54954 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54955 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2aa00 }
54956 },
54957/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54958 {
54959 { 0, 0, 0, 0 },
54960 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54961 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48a00 }
54962 },
54963/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54964 {
54965 { 0, 0, 0, 0 },
54966 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54967 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4aa00 }
54968 },
54969/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54970 {
54971 { 0, 0, 0, 0 },
54972 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54973 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ca00 }
54974 },
54975/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54976 {
54977 { 0, 0, 0, 0 },
54978 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54979 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ea00 }
54980 },
54981/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54982 {
54983 { 0, 0, 0, 0 },
54984 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54985 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ca00 }
54986 },
54987/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54988 {
54989 { 0, 0, 0, 0 },
54990 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54991 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ea00 }
54992 },
54993/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54994 {
54995 { 0, 0, 0, 0 },
54996 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
54997 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ca00 }
54998 },
54999/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
55000 {
55001 { 0, 0, 0, 0 },
55002 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
55003 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ea00 }
55004 },
55005/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55006 {
55007 { 0, 0, 0, 0 },
55008 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
55009 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68a00 }
55010 },
55011/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
55012 {
55013 { 0, 0, 0, 0 },
55014 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
55015 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6aa00 }
55016 },
55017/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
55018 {
55019 { 0, 0, 0, 0 },
55020 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55021 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80a }
55022 },
55023/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
55024 {
55025 { 0, 0, 0, 0 },
55026 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55027 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882a }
55028 },
55029/* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
55030 {
55031 { 0, 0, 0, 0 },
55032 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
55033 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880a }
55034 },
55035/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
55036 {
55037 { 0, 0, 0, 0 },
55038 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55039 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08a }
55040 },
55041/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
55042 {
55043 { 0, 0, 0, 0 },
55044 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55045 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180aa }
55046 },
55047/* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
55048 {
55049 { 0, 0, 0, 0 },
55050 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55051 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808a }
55052 },
55053/* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
55054 {
55055 { 0, 0, 0, 0 },
55056 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55057 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00a }
55058 },
55059/* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
55060 {
55061 { 0, 0, 0, 0 },
55062 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55063 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802a }
55064 },
55065/* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55066 {
55067 { 0, 0, 0, 0 },
55068 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55069 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800a }
55070 },
55071/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55072 {
55073 { 0, 0, 0, 0 },
55074 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55075 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20a00 }
55076 },
55077/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55078 {
55079 { 0, 0, 0, 0 },
55080 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55081 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822a00 }
55082 },
55083/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55084 {
55085 { 0, 0, 0, 0 },
55086 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55087 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820a00 }
55088 },
55089/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55090 {
55091 { 0, 0, 0, 0 },
55092 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55093 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40a00 }
55094 },
55095/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55096 {
55097 { 0, 0, 0, 0 },
55098 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55099 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842a00 }
55100 },
55101/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55102 {
55103 { 0, 0, 0, 0 },
55104 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55105 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840a00 }
55106 },
55107/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55108 {
55109 { 0, 0, 0, 0 },
55110 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55111 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60a00 }
55112 },
55113/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55114 {
55115 { 0, 0, 0, 0 },
55116 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55117 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862a00 }
55118 },
55119/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55120 {
55121 { 0, 0, 0, 0 },
55122 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55123 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860a00 }
55124 },
55125/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
55126 {
55127 { 0, 0, 0, 0 },
55128 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55129 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28a00 }
55130 },
55131/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
55132 {
55133 { 0, 0, 0, 0 },
55134 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55135 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182aa00 }
55136 },
55137/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55138 {
55139 { 0, 0, 0, 0 },
55140 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55141 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828a00 }
55142 },
55143/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
55144 {
55145 { 0, 0, 0, 0 },
55146 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55147 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48a00 }
55148 },
55149/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
55150 {
55151 { 0, 0, 0, 0 },
55152 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55153 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184aa00 }
55154 },
55155/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55156 {
55157 { 0, 0, 0, 0 },
55158 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55159 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848a00 }
55160 },
55161/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
55162 {
55163 { 0, 0, 0, 0 },
55164 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55165 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2ca00 }
55166 },
55167/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
55168 {
55169 { 0, 0, 0, 0 },
55170 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55171 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ea00 }
55172 },
55173/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55174 {
55175 { 0, 0, 0, 0 },
55176 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55177 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ca00 }
55178 },
55179/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
55180 {
55181 { 0, 0, 0, 0 },
55182 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55183 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4ca00 }
55184 },
55185/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
55186 {
55187 { 0, 0, 0, 0 },
55188 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55189 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ea00 }
55190 },
55191/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55192 {
55193 { 0, 0, 0, 0 },
55194 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55195 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ca00 }
55196 },
55197/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
55198 {
55199 { 0, 0, 0, 0 },
55200 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
55201 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6ca00 }
55202 },
55203/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
55204 {
55205 { 0, 0, 0, 0 },
55206 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
55207 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ea00 }
55208 },
55209/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55210 {
55211 { 0, 0, 0, 0 },
55212 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
55213 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ca00 }
55214 },
55215/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
55216 {
55217 { 0, 0, 0, 0 },
55218 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
55219 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68a00 }
55220 },
55221/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
55222 {
55223 { 0, 0, 0, 0 },
55224 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
55225 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186aa00 }
55226 },
55227/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55228 {
55229 { 0, 0, 0, 0 },
55230 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
55231 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868a00 }
55232 },
55233/* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
55234 {
55235 { 0, 0, 0, 0 },
55236 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
55237 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1990e00 }
55238 },
55239/* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
55240 {
55241 { 0, 0, 0, 0 },
55242 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
55243 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1918e00 }
55244 },
55245/* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
55246 {
55247 { 0, 0, 0, 0 },
55248 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55249 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1910e00 }
55250 },
55251/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55252 {
55253 { 0, 0, 0, 0 },
55254 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55255 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1930e00 }
55256 },
55257/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
55258 {
55259 { 0, 0, 0, 0 },
55260 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55261 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1938e00 }
55262 },
55263/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
55264 {
55265 { 0, 0, 0, 0 },
55266 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55267 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ce00 }
55268 },
55269/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55270 {
55271 { 0, 0, 0, 0 },
55272 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55273 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1950e00 }
55274 },
55275/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
55276 {
55277 { 0, 0, 0, 0 },
55278 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55279 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1958e00 }
55280 },
55281/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
55282 {
55283 { 0, 0, 0, 0 },
55284 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55285 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ce00 }
55286 },
55287/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
55288 {
55289 { 0, 0, 0, 0 },
55290 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
55291 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ce00 }
55292 },
55293/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55294 {
55295 { 0, 0, 0, 0 },
55296 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55297 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1970e00 }
55298 },
55299/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
55300 {
55301 { 0, 0, 0, 0 },
55302 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
55303 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1978e00 }
55304 },
55305/* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
55306 {
55307 { 0, 0, 0, 0 },
55308 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55309 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1980e00 }
55310 },
55311/* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
55312 {
55313 { 0, 0, 0, 0 },
55314 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55315 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1908e00 }
55316 },
55317/* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
55318 {
55319 { 0, 0, 0, 0 },
55320 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55321 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1900e00 }
55322 },
55323/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55324 {
55325 { 0, 0, 0, 0 },
55326 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55327 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1920e00 }
55328 },
55329/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
55330 {
55331 { 0, 0, 0, 0 },
55332 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55333 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1928e00 }
55334 },
55335/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
55336 {
55337 { 0, 0, 0, 0 },
55338 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55339 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ce00 }
55340 },
55341/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55342 {
55343 { 0, 0, 0, 0 },
55344 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55345 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1940e00 }
55346 },
55347/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
55348 {
55349 { 0, 0, 0, 0 },
55350 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55351 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1948e00 }
55352 },
55353/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
55354 {
55355 { 0, 0, 0, 0 },
55356 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55357 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ce00 }
55358 },
55359/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
55360 {
55361 { 0, 0, 0, 0 },
55362 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
55363 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ce00 }
55364 },
55365/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55366 {
55367 { 0, 0, 0, 0 },
55368 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55369 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1960e00 }
55370 },
55371/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
55372 {
55373 { 0, 0, 0, 0 },
55374 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
55375 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1968e00 }
55376 },
55377/* divx.l $Dst32RnPrefixedSI */
55378 {
55379 { 0, 0, 0, 0 },
55380 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
55381 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI, { 0x1a92f }
55382 },
55383/* divx.l $Dst32AnPrefixedSI */
55384 {
55385 { 0, 0, 0, 0 },
55386 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
55387 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI, { 0x1a1af }
55388 },
55389/* divx.l [$Dst32AnPrefixed] */
55390 {
55391 { 0, 0, 0, 0 },
55392 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
55393 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI, { 0x1a12f }
55394 },
55395/* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55396 {
55397 { 0, 0, 0, 0 },
55398 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55399 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI, { 0x1a32f00 }
55400 },
55401/* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55402 {
55403 { 0, 0, 0, 0 },
55404 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55405 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI, { 0x1a52f00 }
55406 },
55407/* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55408 {
55409 { 0, 0, 0, 0 },
55410 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55411 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI, { 0x1a72f00 }
55412 },
55413/* divx.l ${Dsp-24-u8}[sb] */
55414 {
55415 { 0, 0, 0, 0 },
55416 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55417 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a3af00 }
55418 },
55419/* divx.l ${Dsp-24-u16}[sb] */
55420 {
55421 { 0, 0, 0, 0 },
55422 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55423 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a5af00 }
55424 },
55425/* divx.l ${Dsp-24-s8}[fb] */
55426 {
55427 { 0, 0, 0, 0 },
55428 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55429 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3ef00 }
55430 },
55431/* divx.l ${Dsp-24-s16}[fb] */
55432 {
55433 { 0, 0, 0, 0 },
55434 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55435 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5ef00 }
55436 },
55437/* divx.l ${Dsp-24-u16} */
55438 {
55439 { 0, 0, 0, 0 },
55440 { { MNEM, ' ', OP (DSP_24_U16), 0 } },
55441 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI, { 0x1a7ef00 }
55442 },
55443/* divx.l ${Dsp-24-u24} */
55444 {
55445 { 0, 0, 0, 0 },
55446 { { MNEM, ' ', OP (DSP_24_U24), 0 } },
55447 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI, { 0x1a7af00 }
55448 },
55449/* divu.l $Dst32RnPrefixedSI */
55450 {
55451 { 0, 0, 0, 0 },
55452 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
55453 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI, { 0x1a90f }
55454 },
55455/* divu.l $Dst32AnPrefixedSI */
55456 {
55457 { 0, 0, 0, 0 },
55458 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
55459 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI, { 0x1a18f }
55460 },
55461/* divu.l [$Dst32AnPrefixed] */
55462 {
55463 { 0, 0, 0, 0 },
55464 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
55465 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI, { 0x1a10f }
55466 },
55467/* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55468 {
55469 { 0, 0, 0, 0 },
55470 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55471 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI, { 0x1a30f00 }
55472 },
55473/* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55474 {
55475 { 0, 0, 0, 0 },
55476 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55477 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI, { 0x1a50f00 }
55478 },
55479/* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55480 {
55481 { 0, 0, 0, 0 },
55482 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55483 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI, { 0x1a70f00 }
55484 },
55485/* divu.l ${Dsp-24-u8}[sb] */
55486 {
55487 { 0, 0, 0, 0 },
55488 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55489 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a38f00 }
55490 },
55491/* divu.l ${Dsp-24-u16}[sb] */
55492 {
55493 { 0, 0, 0, 0 },
55494 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55495 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a58f00 }
55496 },
55497/* divu.l ${Dsp-24-s8}[fb] */
55498 {
55499 { 0, 0, 0, 0 },
55500 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55501 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3cf00 }
55502 },
55503/* divu.l ${Dsp-24-s16}[fb] */
55504 {
55505 { 0, 0, 0, 0 },
55506 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55507 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5cf00 }
55508 },
55509/* divu.l ${Dsp-24-u16} */
55510 {
55511 { 0, 0, 0, 0 },
55512 { { MNEM, ' ', OP (DSP_24_U16), 0 } },
55513 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI, { 0x1a7cf00 }
55514 },
55515/* divu.l ${Dsp-24-u24} */
55516 {
55517 { 0, 0, 0, 0 },
55518 { { MNEM, ' ', OP (DSP_24_U24), 0 } },
55519 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI, { 0x1a78f00 }
55520 },
55521/* div.l $Dst32RnPrefixedSI */
55522 {
55523 { 0, 0, 0, 0 },
55524 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
55525 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI, { 0x1a91f }
55526 },
55527/* div.l $Dst32AnPrefixedSI */
55528 {
55529 { 0, 0, 0, 0 },
55530 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
55531 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI, { 0x1a19f }
55532 },
55533/* div.l [$Dst32AnPrefixed] */
55534 {
55535 { 0, 0, 0, 0 },
55536 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
55537 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI, { 0x1a11f }
55538 },
55539/* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55540 {
55541 { 0, 0, 0, 0 },
55542 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55543 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI, { 0x1a31f00 }
55544 },
55545/* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55546 {
55547 { 0, 0, 0, 0 },
55548 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55549 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI, { 0x1a51f00 }
55550 },
55551/* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55552 {
55553 { 0, 0, 0, 0 },
55554 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55555 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI, { 0x1a71f00 }
55556 },
55557/* div.l ${Dsp-24-u8}[sb] */
55558 {
55559 { 0, 0, 0, 0 },
55560 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55561 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a39f00 }
55562 },
55563/* div.l ${Dsp-24-u16}[sb] */
55564 {
55565 { 0, 0, 0, 0 },
55566 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55567 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a59f00 }
55568 },
55569/* div.l ${Dsp-24-s8}[fb] */
55570 {
55571 { 0, 0, 0, 0 },
55572 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55573 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3df00 }
55574 },
55575/* div.l ${Dsp-24-s16}[fb] */
55576 {
55577 { 0, 0, 0, 0 },
55578 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55579 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5df00 }
55580 },
55581/* div.l ${Dsp-24-u16} */
55582 {
55583 { 0, 0, 0, 0 },
55584 { { MNEM, ' ', OP (DSP_24_U16), 0 } },
55585 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI, { 0x1a7df00 }
55586 },
55587/* div.l ${Dsp-24-u24} */
55588 {
55589 { 0, 0, 0, 0 },
55590 { { MNEM, ' ', OP (DSP_24_U24), 0 } },
55591 & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI, { 0x1a79f00 }
55592 },
55593/* divx.w $Dst32RnUnprefixedHI */
55594 {
55595 { 0, 0, 0, 0 },
55596 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
55597 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x991e }
55598 },
55599/* divx.w $Dst32AnUnprefixedHI */
55600 {
55601 { 0, 0, 0, 0 },
55602 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
55603 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x919e }
55604 },
55605/* divx.w [$Dst32AnUnprefixed] */
55606 {
55607 { 0, 0, 0, 0 },
55608 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55609 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x911e }
55610 },
55611/* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
55612 {
55613 { 0, 0, 0, 0 },
55614 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55615 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931e00 }
55616 },
55617/* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
55618 {
55619 { 0, 0, 0, 0 },
55620 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55621 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x951e0000 }
55622 },
55623/* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
55624 {
55625 { 0, 0, 0, 0 },
55626 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55627 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x971e0000 }
55628 },
55629/* divx.w ${Dsp-16-u8}[sb] */
55630 {
55631 { 0, 0, 0, 0 },
55632 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
55633 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939e00 }
55634 },
55635/* divx.w ${Dsp-16-u16}[sb] */
55636 {
55637 { 0, 0, 0, 0 },
55638 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
55639 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959e0000 }
55640 },
55641/* divx.w ${Dsp-16-s8}[fb] */
55642 {
55643 { 0, 0, 0, 0 },
55644 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
55645 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93de00 }
55646 },
55647/* divx.w ${Dsp-16-s16}[fb] */
55648 {
55649 { 0, 0, 0, 0 },
55650 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
55651 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95de0000 }
55652 },
55653/* divx.w ${Dsp-16-u16} */
55654 {
55655 { 0, 0, 0, 0 },
55656 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
55657 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97de0000 }
55658 },
55659/* divx.w ${Dsp-16-u24} */
55660 {
55661 { 0, 0, 0, 0 },
55662 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
55663 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x979e0000 }
55664 },
55665/* divx.b $Dst32RnUnprefixedQI */
55666 {
55667 { 0, 0, 0, 0 },
55668 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
55669 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x981e }
55670 },
55671/* divx.b $Dst32AnUnprefixedQI */
55672 {
55673 { 0, 0, 0, 0 },
55674 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
55675 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x909e }
55676 },
55677/* divx.b [$Dst32AnUnprefixed] */
55678 {
55679 { 0, 0, 0, 0 },
55680 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55681 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x901e }
55682 },
55683/* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
55684 {
55685 { 0, 0, 0, 0 },
55686 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55687 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x921e00 }
55688 },
55689/* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
55690 {
55691 { 0, 0, 0, 0 },
55692 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55693 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x941e0000 }
55694 },
55695/* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
55696 {
55697 { 0, 0, 0, 0 },
55698 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55699 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x961e0000 }
55700 },
55701/* divx.b ${Dsp-16-u8}[sb] */
55702 {
55703 { 0, 0, 0, 0 },
55704 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
55705 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929e00 }
55706 },
55707/* divx.b ${Dsp-16-u16}[sb] */
55708 {
55709 { 0, 0, 0, 0 },
55710 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
55711 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949e0000 }
55712 },
55713/* divx.b ${Dsp-16-s8}[fb] */
55714 {
55715 { 0, 0, 0, 0 },
55716 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
55717 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92de00 }
55718 },
55719/* divx.b ${Dsp-16-s16}[fb] */
55720 {
55721 { 0, 0, 0, 0 },
55722 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
55723 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94de0000 }
55724 },
55725/* divx.b ${Dsp-16-u16} */
55726 {
55727 { 0, 0, 0, 0 },
55728 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
55729 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96de0000 }
55730 },
55731/* divx.b ${Dsp-16-u24} */
55732 {
55733 { 0, 0, 0, 0 },
55734 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
55735 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x969e0000 }
55736 },
55737/* divx.w $Dst16RnHI */
55738 {
55739 { 0, 0, 0, 0 },
55740 { { MNEM, ' ', OP (DST16RNHI), 0 } },
55741 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7790 }
55742 },
55743/* divx.w $Dst16AnHI */
55744 {
55745 { 0, 0, 0, 0 },
55746 { { MNEM, ' ', OP (DST16ANHI), 0 } },
55747 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7794 }
55748 },
55749/* divx.w [$Dst16An] */
55750 {
55751 { 0, 0, 0, 0 },
55752 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
55753 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7796 }
55754 },
55755/* divx.w ${Dsp-16-u8}[$Dst16An] */
55756 {
55757 { 0, 0, 0, 0 },
55758 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
55759 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x779800 }
55760 },
55761/* divx.w ${Dsp-16-u16}[$Dst16An] */
55762 {
55763 { 0, 0, 0, 0 },
55764 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
55765 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x779c0000 }
55766 },
55767/* divx.w ${Dsp-16-u8}[sb] */
55768 {
55769 { 0, 0, 0, 0 },
55770 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
55771 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x779a00 }
55772 },
55773/* divx.w ${Dsp-16-u16}[sb] */
55774 {
55775 { 0, 0, 0, 0 },
55776 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
55777 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x779e0000 }
55778 },
55779/* divx.w ${Dsp-16-s8}[fb] */
55780 {
55781 { 0, 0, 0, 0 },
55782 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
55783 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x779b00 }
55784 },
55785/* divx.w ${Dsp-16-u16} */
55786 {
55787 { 0, 0, 0, 0 },
55788 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
55789 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x779f0000 }
55790 },
55791/* divx.b $Dst16RnQI */
55792 {
55793 { 0, 0, 0, 0 },
55794 { { MNEM, ' ', OP (DST16RNQI), 0 } },
55795 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7690 }
55796 },
55797/* divx.b $Dst16AnQI */
55798 {
55799 { 0, 0, 0, 0 },
55800 { { MNEM, ' ', OP (DST16ANQI), 0 } },
55801 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7694 }
55802 },
55803/* divx.b [$Dst16An] */
55804 {
55805 { 0, 0, 0, 0 },
55806 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
55807 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7696 }
55808 },
55809/* divx.b ${Dsp-16-u8}[$Dst16An] */
55810 {
55811 { 0, 0, 0, 0 },
55812 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
55813 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x769800 }
55814 },
55815/* divx.b ${Dsp-16-u16}[$Dst16An] */
55816 {
55817 { 0, 0, 0, 0 },
55818 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
55819 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x769c0000 }
55820 },
55821/* divx.b ${Dsp-16-u8}[sb] */
55822 {
55823 { 0, 0, 0, 0 },
55824 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
55825 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x769a00 }
55826 },
55827/* divx.b ${Dsp-16-u16}[sb] */
55828 {
55829 { 0, 0, 0, 0 },
55830 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
55831 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x769e0000 }
55832 },
55833/* divx.b ${Dsp-16-s8}[fb] */
55834 {
55835 { 0, 0, 0, 0 },
55836 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
55837 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x769b00 }
55838 },
55839/* divx.b ${Dsp-16-u16} */
55840 {
55841 { 0, 0, 0, 0 },
55842 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
55843 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x769f0000 }
55844 },
55845/* divu.w $Dst32RnUnprefixedHI */
55846 {
55847 { 0, 0, 0, 0 },
55848 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
55849 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x890e }
55850 },
55851/* divu.w $Dst32AnUnprefixedHI */
55852 {
55853 { 0, 0, 0, 0 },
55854 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
55855 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x818e }
55856 },
55857/* divu.w [$Dst32AnUnprefixed] */
55858 {
55859 { 0, 0, 0, 0 },
55860 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55861 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x810e }
55862 },
55863/* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
55864 {
55865 { 0, 0, 0, 0 },
55866 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55867 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x830e00 }
55868 },
55869/* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
55870 {
55871 { 0, 0, 0, 0 },
55872 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55873 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x850e0000 }
55874 },
55875/* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
55876 {
55877 { 0, 0, 0, 0 },
55878 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55879 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x870e0000 }
55880 },
55881/* divu.w ${Dsp-16-u8}[sb] */
55882 {
55883 { 0, 0, 0, 0 },
55884 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
55885 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838e00 }
55886 },
55887/* divu.w ${Dsp-16-u16}[sb] */
55888 {
55889 { 0, 0, 0, 0 },
55890 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
55891 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858e0000 }
55892 },
55893/* divu.w ${Dsp-16-s8}[fb] */
55894 {
55895 { 0, 0, 0, 0 },
55896 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
55897 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ce00 }
55898 },
55899/* divu.w ${Dsp-16-s16}[fb] */
55900 {
55901 { 0, 0, 0, 0 },
55902 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
55903 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ce0000 }
55904 },
55905/* divu.w ${Dsp-16-u16} */
55906 {
55907 { 0, 0, 0, 0 },
55908 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
55909 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87ce0000 }
55910 },
55911/* divu.w ${Dsp-16-u24} */
55912 {
55913 { 0, 0, 0, 0 },
55914 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
55915 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x878e0000 }
55916 },
55917/* divu.b $Dst32RnUnprefixedQI */
55918 {
55919 { 0, 0, 0, 0 },
55920 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
55921 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x880e }
55922 },
55923/* divu.b $Dst32AnUnprefixedQI */
55924 {
55925 { 0, 0, 0, 0 },
55926 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
55927 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x808e }
55928 },
55929/* divu.b [$Dst32AnUnprefixed] */
55930 {
55931 { 0, 0, 0, 0 },
55932 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55933 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x800e }
55934 },
55935/* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
55936 {
55937 { 0, 0, 0, 0 },
55938 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55939 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820e00 }
55940 },
55941/* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
55942 {
55943 { 0, 0, 0, 0 },
55944 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55945 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x840e0000 }
55946 },
55947/* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
55948 {
55949 { 0, 0, 0, 0 },
55950 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55951 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x860e0000 }
55952 },
55953/* divu.b ${Dsp-16-u8}[sb] */
55954 {
55955 { 0, 0, 0, 0 },
55956 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
55957 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828e00 }
55958 },
55959/* divu.b ${Dsp-16-u16}[sb] */
55960 {
55961 { 0, 0, 0, 0 },
55962 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
55963 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848e0000 }
55964 },
55965/* divu.b ${Dsp-16-s8}[fb] */
55966 {
55967 { 0, 0, 0, 0 },
55968 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
55969 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ce00 }
55970 },
55971/* divu.b ${Dsp-16-s16}[fb] */
55972 {
55973 { 0, 0, 0, 0 },
55974 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
55975 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ce0000 }
55976 },
55977/* divu.b ${Dsp-16-u16} */
55978 {
55979 { 0, 0, 0, 0 },
55980 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
55981 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86ce0000 }
55982 },
55983/* divu.b ${Dsp-16-u24} */
55984 {
55985 { 0, 0, 0, 0 },
55986 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
55987 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x868e0000 }
55988 },
55989/* divu.w $Dst16RnHI */
55990 {
55991 { 0, 0, 0, 0 },
55992 { { MNEM, ' ', OP (DST16RNHI), 0 } },
55993 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77c0 }
55994 },
55995/* divu.w $Dst16AnHI */
55996 {
55997 { 0, 0, 0, 0 },
55998 { { MNEM, ' ', OP (DST16ANHI), 0 } },
55999 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77c4 }
56000 },
56001/* divu.w [$Dst16An] */
56002 {
56003 { 0, 0, 0, 0 },
56004 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56005 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77c6 }
56006 },
56007/* divu.w ${Dsp-16-u8}[$Dst16An] */
56008 {
56009 { 0, 0, 0, 0 },
56010 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56011 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77c800 }
56012 },
56013/* divu.w ${Dsp-16-u16}[$Dst16An] */
56014 {
56015 { 0, 0, 0, 0 },
56016 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56017 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77cc0000 }
56018 },
56019/* divu.w ${Dsp-16-u8}[sb] */
56020 {
56021 { 0, 0, 0, 0 },
56022 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56023 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ca00 }
56024 },
56025/* divu.w ${Dsp-16-u16}[sb] */
56026 {
56027 { 0, 0, 0, 0 },
56028 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56029 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ce0000 }
56030 },
56031/* divu.w ${Dsp-16-s8}[fb] */
56032 {
56033 { 0, 0, 0, 0 },
56034 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56035 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77cb00 }
56036 },
56037/* divu.w ${Dsp-16-u16} */
56038 {
56039 { 0, 0, 0, 0 },
56040 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56041 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77cf0000 }
56042 },
56043/* divu.b $Dst16RnQI */
56044 {
56045 { 0, 0, 0, 0 },
56046 { { MNEM, ' ', OP (DST16RNQI), 0 } },
56047 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76c0 }
56048 },
56049/* divu.b $Dst16AnQI */
56050 {
56051 { 0, 0, 0, 0 },
56052 { { MNEM, ' ', OP (DST16ANQI), 0 } },
56053 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76c4 }
56054 },
56055/* divu.b [$Dst16An] */
56056 {
56057 { 0, 0, 0, 0 },
56058 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56059 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76c6 }
56060 },
56061/* divu.b ${Dsp-16-u8}[$Dst16An] */
56062 {
56063 { 0, 0, 0, 0 },
56064 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56065 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76c800 }
56066 },
56067/* divu.b ${Dsp-16-u16}[$Dst16An] */
56068 {
56069 { 0, 0, 0, 0 },
56070 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56071 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76cc0000 }
56072 },
56073/* divu.b ${Dsp-16-u8}[sb] */
56074 {
56075 { 0, 0, 0, 0 },
56076 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56077 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ca00 }
56078 },
56079/* divu.b ${Dsp-16-u16}[sb] */
56080 {
56081 { 0, 0, 0, 0 },
56082 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56083 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ce0000 }
56084 },
56085/* divu.b ${Dsp-16-s8}[fb] */
56086 {
56087 { 0, 0, 0, 0 },
56088 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56089 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76cb00 }
56090 },
56091/* divu.b ${Dsp-16-u16} */
56092 {
56093 { 0, 0, 0, 0 },
56094 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56095 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76cf0000 }
56096 },
56097/* div.w $Dst32RnUnprefixedHI */
56098 {
56099 { 0, 0, 0, 0 },
56100 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56101 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x891e }
56102 },
56103/* div.w $Dst32AnUnprefixedHI */
56104 {
56105 { 0, 0, 0, 0 },
56106 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56107 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x819e }
56108 },
56109/* div.w [$Dst32AnUnprefixed] */
56110 {
56111 { 0, 0, 0, 0 },
56112 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56113 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x811e }
56114 },
56115/* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56116 {
56117 { 0, 0, 0, 0 },
56118 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56119 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831e00 }
56120 },
56121/* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56122 {
56123 { 0, 0, 0, 0 },
56124 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56125 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x851e0000 }
56126 },
56127/* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56128 {
56129 { 0, 0, 0, 0 },
56130 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56131 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x871e0000 }
56132 },
56133/* div.w ${Dsp-16-u8}[sb] */
56134 {
56135 { 0, 0, 0, 0 },
56136 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56137 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839e00 }
56138 },
56139/* div.w ${Dsp-16-u16}[sb] */
56140 {
56141 { 0, 0, 0, 0 },
56142 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56143 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859e0000 }
56144 },
56145/* div.w ${Dsp-16-s8}[fb] */
56146 {
56147 { 0, 0, 0, 0 },
56148 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56149 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83de00 }
56150 },
56151/* div.w ${Dsp-16-s16}[fb] */
56152 {
56153 { 0, 0, 0, 0 },
56154 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56155 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85de0000 }
56156 },
56157/* div.w ${Dsp-16-u16} */
56158 {
56159 { 0, 0, 0, 0 },
56160 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56161 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87de0000 }
56162 },
56163/* div.w ${Dsp-16-u24} */
56164 {
56165 { 0, 0, 0, 0 },
56166 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56167 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x879e0000 }
56168 },
56169/* div.b $Dst32RnUnprefixedQI */
56170 {
56171 { 0, 0, 0, 0 },
56172 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56173 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x881e }
56174 },
56175/* div.b $Dst32AnUnprefixedQI */
56176 {
56177 { 0, 0, 0, 0 },
56178 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56179 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x809e }
56180 },
56181/* div.b [$Dst32AnUnprefixed] */
56182 {
56183 { 0, 0, 0, 0 },
56184 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56185 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x801e }
56186 },
56187/* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56188 {
56189 { 0, 0, 0, 0 },
56190 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56191 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x821e00 }
56192 },
56193/* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56194 {
56195 { 0, 0, 0, 0 },
56196 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56197 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x841e0000 }
56198 },
56199/* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56200 {
56201 { 0, 0, 0, 0 },
56202 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56203 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x861e0000 }
56204 },
56205/* div.b ${Dsp-16-u8}[sb] */
56206 {
56207 { 0, 0, 0, 0 },
56208 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56209 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829e00 }
56210 },
56211/* div.b ${Dsp-16-u16}[sb] */
56212 {
56213 { 0, 0, 0, 0 },
56214 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56215 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849e0000 }
56216 },
56217/* div.b ${Dsp-16-s8}[fb] */
56218 {
56219 { 0, 0, 0, 0 },
56220 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56221 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82de00 }
56222 },
56223/* div.b ${Dsp-16-s16}[fb] */
56224 {
56225 { 0, 0, 0, 0 },
56226 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56227 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84de0000 }
56228 },
56229/* div.b ${Dsp-16-u16} */
56230 {
56231 { 0, 0, 0, 0 },
56232 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56233 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86de0000 }
56234 },
56235/* div.b ${Dsp-16-u24} */
56236 {
56237 { 0, 0, 0, 0 },
56238 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56239 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x869e0000 }
56240 },
56241/* div.w $Dst16RnHI */
56242 {
56243 { 0, 0, 0, 0 },
56244 { { MNEM, ' ', OP (DST16RNHI), 0 } },
56245 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77d0 }
56246 },
56247/* div.w $Dst16AnHI */
56248 {
56249 { 0, 0, 0, 0 },
56250 { { MNEM, ' ', OP (DST16ANHI), 0 } },
56251 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77d4 }
56252 },
56253/* div.w [$Dst16An] */
56254 {
56255 { 0, 0, 0, 0 },
56256 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56257 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77d6 }
56258 },
56259/* div.w ${Dsp-16-u8}[$Dst16An] */
56260 {
56261 { 0, 0, 0, 0 },
56262 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56263 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77d800 }
56264 },
56265/* div.w ${Dsp-16-u16}[$Dst16An] */
56266 {
56267 { 0, 0, 0, 0 },
56268 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56269 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77dc0000 }
56270 },
56271/* div.w ${Dsp-16-u8}[sb] */
56272 {
56273 { 0, 0, 0, 0 },
56274 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56275 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77da00 }
56276 },
56277/* div.w ${Dsp-16-u16}[sb] */
56278 {
56279 { 0, 0, 0, 0 },
56280 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56281 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77de0000 }
56282 },
56283/* div.w ${Dsp-16-s8}[fb] */
56284 {
56285 { 0, 0, 0, 0 },
56286 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56287 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77db00 }
56288 },
56289/* div.w ${Dsp-16-u16} */
56290 {
56291 { 0, 0, 0, 0 },
56292 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56293 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77df0000 }
56294 },
56295/* div.b $Dst16RnQI */
56296 {
56297 { 0, 0, 0, 0 },
56298 { { MNEM, ' ', OP (DST16RNQI), 0 } },
56299 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76d0 }
56300 },
56301/* div.b $Dst16AnQI */
56302 {
56303 { 0, 0, 0, 0 },
56304 { { MNEM, ' ', OP (DST16ANQI), 0 } },
56305 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76d4 }
56306 },
56307/* div.b [$Dst16An] */
56308 {
56309 { 0, 0, 0, 0 },
56310 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56311 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76d6 }
56312 },
56313/* div.b ${Dsp-16-u8}[$Dst16An] */
56314 {
56315 { 0, 0, 0, 0 },
56316 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56317 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76d800 }
56318 },
56319/* div.b ${Dsp-16-u16}[$Dst16An] */
56320 {
56321 { 0, 0, 0, 0 },
56322 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56323 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76dc0000 }
56324 },
56325/* div.b ${Dsp-16-u8}[sb] */
56326 {
56327 { 0, 0, 0, 0 },
56328 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56329 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76da00 }
56330 },
56331/* div.b ${Dsp-16-u16}[sb] */
56332 {
56333 { 0, 0, 0, 0 },
56334 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56335 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76de0000 }
56336 },
56337/* div.b ${Dsp-16-s8}[fb] */
56338 {
56339 { 0, 0, 0, 0 },
56340 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56341 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76db00 }
56342 },
56343/* div.b ${Dsp-16-u16} */
56344 {
56345 { 0, 0, 0, 0 },
56346 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56347 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76df0000 }
56348 },
56349/* dec.w $Dst32RnUnprefixedHI */
56350 {
56351 { 0, 0, 0, 0 },
56352 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56353 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb90e }
56354 },
56355/* dec.w $Dst32AnUnprefixedHI */
56356 {
56357 { 0, 0, 0, 0 },
56358 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56359 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18e }
56360 },
56361/* dec.w [$Dst32AnUnprefixed] */
56362 {
56363 { 0, 0, 0, 0 },
56364 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56365 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb10e }
56366 },
56367/* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56368 {
56369 { 0, 0, 0, 0 },
56370 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56371 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30e00 }
56372 },
56373/* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56374 {
56375 { 0, 0, 0, 0 },
56376 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56377 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50e0000 }
56378 },
56379/* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56380 {
56381 { 0, 0, 0, 0 },
56382 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56383 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70e0000 }
56384 },
56385/* dec.w ${Dsp-16-u8}[sb] */
56386 {
56387 { 0, 0, 0, 0 },
56388 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56389 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38e00 }
56390 },
56391/* dec.w ${Dsp-16-u16}[sb] */
56392 {
56393 { 0, 0, 0, 0 },
56394 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56395 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58e0000 }
56396 },
56397/* dec.w ${Dsp-16-s8}[fb] */
56398 {
56399 { 0, 0, 0, 0 },
56400 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56401 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ce00 }
56402 },
56403/* dec.w ${Dsp-16-s16}[fb] */
56404 {
56405 { 0, 0, 0, 0 },
56406 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56407 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ce0000 }
56408 },
56409/* dec.w ${Dsp-16-u16} */
56410 {
56411 { 0, 0, 0, 0 },
56412 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56413 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ce0000 }
56414 },
56415/* dec.w ${Dsp-16-u24} */
56416 {
56417 { 0, 0, 0, 0 },
56418 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56419 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb78e0000 }
56420 },
56421/* dec.b $Dst32RnUnprefixedQI */
56422 {
56423 { 0, 0, 0, 0 },
56424 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56425 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb80e }
56426 },
56427/* dec.b $Dst32AnUnprefixedQI */
56428 {
56429 { 0, 0, 0, 0 },
56430 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56431 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb08e }
56432 },
56433/* dec.b [$Dst32AnUnprefixed] */
56434 {
56435 { 0, 0, 0, 0 },
56436 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56437 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb00e }
56438 },
56439/* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56440 {
56441 { 0, 0, 0, 0 },
56442 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56443 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20e00 }
56444 },
56445/* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56446 {
56447 { 0, 0, 0, 0 },
56448 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56449 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40e0000 }
56450 },
56451/* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56452 {
56453 { 0, 0, 0, 0 },
56454 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56455 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60e0000 }
56456 },
56457/* dec.b ${Dsp-16-u8}[sb] */
56458 {
56459 { 0, 0, 0, 0 },
56460 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56461 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28e00 }
56462 },
56463/* dec.b ${Dsp-16-u16}[sb] */
56464 {
56465 { 0, 0, 0, 0 },
56466 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56467 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48e0000 }
56468 },
56469/* dec.b ${Dsp-16-s8}[fb] */
56470 {
56471 { 0, 0, 0, 0 },
56472 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56473 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ce00 }
56474 },
56475/* dec.b ${Dsp-16-s16}[fb] */
56476 {
56477 { 0, 0, 0, 0 },
56478 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56479 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ce0000 }
56480 },
56481/* dec.b ${Dsp-16-u16} */
56482 {
56483 { 0, 0, 0, 0 },
56484 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56485 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ce0000 }
56486 },
56487/* dec.b ${Dsp-16-u24} */
56488 {
56489 { 0, 0, 0, 0 },
56490 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56491 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb68e0000 }
56492 },
56493/* dec.b r0l */
56494 {
56495 { 0, 0, 0, 0 },
56496 { { MNEM, ' ', 'r', '0', 'l', 0 } },
56497 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xac }
56498 },
56499/* dec.b r0h */
56500 {
56501 { 0, 0, 0, 0 },
56502 { { MNEM, ' ', 'r', '0', 'h', 0 } },
56503 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xab }
56504 },
56505/* dec.b ${Dsp-8-u8}[sb] */
56506 {
56507 { 0, 0, 0, 0 },
56508 { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
56509 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xad00 }
56510 },
56511/* dec.b ${Dsp-8-s8}[fb] */
56512 {
56513 { 0, 0, 0, 0 },
56514 { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
56515 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xae00 }
56516 },
56517/* dec.b ${Dsp-8-u16} */
56518 {
56519 { 0, 0, 0, 0 },
56520 { { MNEM, ' ', OP (DSP_8_U16), 0 } },
56521 & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xaf0000 }
56522 },
56523/* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
56524 {
56525 { 0, 0, 0, 0 },
56526 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56527 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa81100 }
56528 },
56529/* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
56530 {
56531 { 0, 0, 0, 0 },
56532 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56533 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa09100 }
56534 },
56535/* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
56536 {
56537 { 0, 0, 0, 0 },
56538 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56539 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa01100 }
56540 },
56541/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
56542 {
56543 { 0, 0, 0, 0 },
56544 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56545 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2110000 }
56546 },
56547/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
56548 {
56549 { 0, 0, 0, 0 },
56550 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56551 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2910000 }
56552 },
56553/* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
56554 {
56555 { 0, 0, 0, 0 },
56556 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56557 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2d10000 }
56558 },
56559/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
56560 {
56561 { 0, 0, 0, 0 },
56562 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56563 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4110000 }
56564 },
56565/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
56566 {
56567 { 0, 0, 0, 0 },
56568 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56569 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4910000 }
56570 },
56571/* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
56572 {
56573 { 0, 0, 0, 0 },
56574 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56575 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4d10000 }
56576 },
56577/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
56578 {
56579 { 0, 0, 0, 0 },
56580 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
56581 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6d10000 }
56582 },
56583/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
56584 {
56585 { 0, 0, 0, 0 },
56586 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56587 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6110000 }
56588 },
56589/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
56590 {
56591 { 0, 0, 0, 0 },
56592 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
56593 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6910000 }
56594 },
56595/* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
56596 {
56597 { 0, 0, 0, 0 },
56598 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0HI_S), 0 } },
56599 & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI, { 0x6100 }
56600 },
56601/* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
56602 {
56603 { 0, 0, 0, 0 },
56604 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0HI_S), 0 } },
56605 & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI, { 0x7100 }
56606 },
56607/* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
56608 {
56609 { 0, 0, 0, 0 },
56610 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0HI_S), 0 } },
56611 & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI, { 0x510000 }
56612 },
56613/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
56614 {
56615 { 0, 0, 0, 0 },
56616 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0QI_S), 0 } },
56617 & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI, { 0x6000 }
56618 },
56619/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
56620 {
56621 { 0, 0, 0, 0 },
56622 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0QI_S), 0 } },
56623 & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI, { 0x7000 }
56624 },
56625/* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
56626 {
56627 { 0, 0, 0, 0 },
56628 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0QI_S), 0 } },
56629 & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI, { 0x500000 }
56630 },
56631/* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
56632 {
56633 { 0, 0, 0, 0 },
56634 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
56635 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x67000000 }
56636 },
56637/* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
56638 {
56639 { 0, 0, 0, 0 },
56640 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
56641 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x77000000 }
56642 },
56643/* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
56644 {
56645 { 0, 0, 0, 0 },
56646 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
56647 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x57000000 }
56648 },
56649/* cmp.w${S} #${Imm-8-HI},r0 */
56650 {
56651 { 0, 0, 0, 0 },
56652 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
56653 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x470000 }
56654 },
56655/* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
56656 {
56657 { 0, 0, 0, 0 },
56658 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
56659 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x660000 }
56660 },
56661/* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
56662 {
56663 { 0, 0, 0, 0 },
56664 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
56665 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x760000 }
56666 },
56667/* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
56668 {
56669 { 0, 0, 0, 0 },
56670 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
56671 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x56000000 }
56672 },
56673/* cmp.b${S} #${Imm-8-QI},r0l */
56674 {
56675 { 0, 0, 0, 0 },
56676 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
56677 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4600 }
56678 },
56679/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
56680 {
56681 { 0, 0, 0, 0 },
56682 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56683 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990100 }
56684 },
56685/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
56686 {
56687 { 0, 0, 0, 0 },
56688 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56689 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992100 }
56690 },
56691/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
56692 {
56693 { 0, 0, 0, 0 },
56694 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56695 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993100 }
56696 },
56697/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
56698 {
56699 { 0, 0, 0, 0 },
56700 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56701 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918100 }
56702 },
56703/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
56704 {
56705 { 0, 0, 0, 0 },
56706 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56707 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a100 }
56708 },
56709/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
56710 {
56711 { 0, 0, 0, 0 },
56712 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56713 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b100 }
56714 },
56715/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
56716 {
56717 { 0, 0, 0, 0 },
56718 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56719 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910100 }
56720 },
56721/* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
56722 {
56723 { 0, 0, 0, 0 },
56724 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56725 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912100 }
56726 },
56727/* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
56728 {
56729 { 0, 0, 0, 0 },
56730 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56731 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913100 }
56732 },
56733/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
56734 {
56735 { 0, 0, 0, 0 },
56736 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56737 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93010000 }
56738 },
56739/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
56740 {
56741 { 0, 0, 0, 0 },
56742 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56743 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93210000 }
56744 },
56745/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
56746 {
56747 { 0, 0, 0, 0 },
56748 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56749 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93310000 }
56750 },
56751/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
56752 {
56753 { 0, 0, 0, 0 },
56754 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56755 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95010000 }
56756 },
56757/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
56758 {
56759 { 0, 0, 0, 0 },
56760 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56761 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95210000 }
56762 },
56763/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
56764 {
56765 { 0, 0, 0, 0 },
56766 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56767 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95310000 }
56768 },
56769/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
56770 {
56771 { 0, 0, 0, 0 },
56772 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56773 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97010000 }
56774 },
56775/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
56776 {
56777 { 0, 0, 0, 0 },
56778 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56779 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97210000 }
56780 },
56781/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
56782 {
56783 { 0, 0, 0, 0 },
56784 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56785 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97310000 }
56786 },
56787/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
56788 {
56789 { 0, 0, 0, 0 },
56790 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
56791 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93810000 }
56792 },
56793/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
56794 {
56795 { 0, 0, 0, 0 },
56796 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
56797 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a10000 }
56798 },
56799/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
56800 {
56801 { 0, 0, 0, 0 },
56802 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
56803 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b10000 }
56804 },
56805/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
56806 {
56807 { 0, 0, 0, 0 },
56808 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
56809 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95810000 }
56810 },
56811/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
56812 {
56813 { 0, 0, 0, 0 },
56814 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
56815 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a10000 }
56816 },
56817/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
56818 {
56819 { 0, 0, 0, 0 },
56820 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
56821 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b10000 }
56822 },
56823/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
56824 {
56825 { 0, 0, 0, 0 },
56826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
56827 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c10000 }
56828 },
56829/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
56830 {
56831 { 0, 0, 0, 0 },
56832 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
56833 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e10000 }
56834 },
56835/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
56836 {
56837 { 0, 0, 0, 0 },
56838 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
56839 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f10000 }
56840 },
56841/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
56842 {
56843 { 0, 0, 0, 0 },
56844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
56845 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c10000 }
56846 },
56847/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
56848 {
56849 { 0, 0, 0, 0 },
56850 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
56851 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e10000 }
56852 },
56853/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
56854 {
56855 { 0, 0, 0, 0 },
56856 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
56857 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f10000 }
56858 },
56859/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
56860 {
56861 { 0, 0, 0, 0 },
56862 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
56863 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c10000 }
56864 },
56865/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
56866 {
56867 { 0, 0, 0, 0 },
56868 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
56869 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e10000 }
56870 },
56871/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
56872 {
56873 { 0, 0, 0, 0 },
56874 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
56875 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f10000 }
56876 },
56877/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
56878 {
56879 { 0, 0, 0, 0 },
56880 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
56881 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97810000 }
56882 },
56883/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
56884 {
56885 { 0, 0, 0, 0 },
56886 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
56887 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a10000 }
56888 },
56889/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
56890 {
56891 { 0, 0, 0, 0 },
56892 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
56893 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b10000 }
56894 },
56895/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
56896 {
56897 { 0, 0, 0, 0 },
56898 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56899 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9010000 }
56900 },
56901/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
56902 {
56903 { 0, 0, 0, 0 },
56904 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56905 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9210000 }
56906 },
56907/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
56908 {
56909 { 0, 0, 0, 0 },
56910 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56911 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9310000 }
56912 },
56913/* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
56914 {
56915 { 0, 0, 0, 0 },
56916 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56917 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9310000 }
56918 },
56919/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
56920 {
56921 { 0, 0, 0, 0 },
56922 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56923 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1810000 }
56924 },
56925/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
56926 {
56927 { 0, 0, 0, 0 },
56928 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56929 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a10000 }
56930 },
56931/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
56932 {
56933 { 0, 0, 0, 0 },
56934 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56935 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b10000 }
56936 },
56937/* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
56938 {
56939 { 0, 0, 0, 0 },
56940 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56941 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b10000 }
56942 },
56943/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
56944 {
56945 { 0, 0, 0, 0 },
56946 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56947 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1010000 }
56948 },
56949/* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
56950 {
56951 { 0, 0, 0, 0 },
56952 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56953 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1210000 }
56954 },
56955/* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
56956 {
56957 { 0, 0, 0, 0 },
56958 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56959 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1310000 }
56960 },
56961/* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
56962 {
56963 { 0, 0, 0, 0 },
56964 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56965 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1310000 }
56966 },
56967/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
56968 {
56969 { 0, 0, 0, 0 },
56970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56971 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3010000 }
56972 },
56973/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
56974 {
56975 { 0, 0, 0, 0 },
56976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56977 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3210000 }
56978 },
56979/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
56980 {
56981 { 0, 0, 0, 0 },
56982 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56983 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3310000 }
56984 },
56985/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
56986 {
56987 { 0, 0, 0, 0 },
56988 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56989 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3310000 }
56990 },
56991/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
56992 {
56993 { 0, 0, 0, 0 },
56994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56995 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5010000 }
56996 },
56997/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
56998 {
56999 { 0, 0, 0, 0 },
57000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57001 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5210000 }
57002 },
57003/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57004 {
57005 { 0, 0, 0, 0 },
57006 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57007 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5310000 }
57008 },
57009/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
57010 {
57011 { 0, 0, 0, 0 },
57012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57013 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5310000 }
57014 },
57015/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57016 {
57017 { 0, 0, 0, 0 },
57018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57019 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7010000 }
57020 },
57021/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57022 {
57023 { 0, 0, 0, 0 },
57024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57025 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7210000 }
57026 },
57027/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57028 {
57029 { 0, 0, 0, 0 },
57030 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57031 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7310000 }
57032 },
57033/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
57034 {
57035 { 0, 0, 0, 0 },
57036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57037 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7310000 }
57038 },
57039/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
57040 {
57041 { 0, 0, 0, 0 },
57042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57043 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3810000 }
57044 },
57045/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57046 {
57047 { 0, 0, 0, 0 },
57048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57049 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a10000 }
57050 },
57051/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
57052 {
57053 { 0, 0, 0, 0 },
57054 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57055 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b10000 }
57056 },
57057/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57058 {
57059 { 0, 0, 0, 0 },
57060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57061 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b10000 }
57062 },
57063/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
57064 {
57065 { 0, 0, 0, 0 },
57066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57067 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5810000 }
57068 },
57069/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57070 {
57071 { 0, 0, 0, 0 },
57072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57073 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a10000 }
57074 },
57075/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
57076 {
57077 { 0, 0, 0, 0 },
57078 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57079 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b10000 }
57080 },
57081/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57082 {
57083 { 0, 0, 0, 0 },
57084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57085 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b10000 }
57086 },
57087/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
57088 {
57089 { 0, 0, 0, 0 },
57090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57091 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c10000 }
57092 },
57093/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57094 {
57095 { 0, 0, 0, 0 },
57096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57097 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e10000 }
57098 },
57099/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
57100 {
57101 { 0, 0, 0, 0 },
57102 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57103 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f10000 }
57104 },
57105/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57106 {
57107 { 0, 0, 0, 0 },
57108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57109 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f10000 }
57110 },
57111/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
57112 {
57113 { 0, 0, 0, 0 },
57114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57115 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c10000 }
57116 },
57117/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
57118 {
57119 { 0, 0, 0, 0 },
57120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57121 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e10000 }
57122 },
57123/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
57124 {
57125 { 0, 0, 0, 0 },
57126 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57127 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f10000 }
57128 },
57129/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
57130 {
57131 { 0, 0, 0, 0 },
57132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57133 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f10000 }
57134 },
57135/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
57136 {
57137 { 0, 0, 0, 0 },
57138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
57139 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c10000 }
57140 },
57141/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57142 {
57143 { 0, 0, 0, 0 },
57144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
57145 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e10000 }
57146 },
57147/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
57148 {
57149 { 0, 0, 0, 0 },
57150 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
57151 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f10000 }
57152 },
57153/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
57154 {
57155 { 0, 0, 0, 0 },
57156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
57157 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f10000 }
57158 },
57159/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
57160 {
57161 { 0, 0, 0, 0 },
57162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
57163 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7810000 }
57164 },
57165/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
57166 {
57167 { 0, 0, 0, 0 },
57168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
57169 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a10000 }
57170 },
57171/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
57172 {
57173 { 0, 0, 0, 0 },
57174 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
57175 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b10000 }
57176 },
57177/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
57178 {
57179 { 0, 0, 0, 0 },
57180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
57181 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b10000 }
57182 },
57183/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57184 {
57185 { 0, 0, 0, 0 },
57186 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57187 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9010000 }
57188 },
57189/* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
57190 {
57191 { 0, 0, 0, 0 },
57192 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57193 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9210000 }
57194 },
57195/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57196 {
57197 { 0, 0, 0, 0 },
57198 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57199 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1810000 }
57200 },
57201/* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
57202 {
57203 { 0, 0, 0, 0 },
57204 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57205 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a10000 }
57206 },
57207/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57208 {
57209 { 0, 0, 0, 0 },
57210 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57211 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1010000 }
57212 },
57213/* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
57214 {
57215 { 0, 0, 0, 0 },
57216 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57217 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1210000 }
57218 },
57219/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
57220 {
57221 { 0, 0, 0, 0 },
57222 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57223 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3010000 }
57224 },
57225/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
57226 {
57227 { 0, 0, 0, 0 },
57228 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57229 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3210000 }
57230 },
57231/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
57232 {
57233 { 0, 0, 0, 0 },
57234 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57235 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5010000 }
57236 },
57237/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
57238 {
57239 { 0, 0, 0, 0 },
57240 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57241 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5210000 }
57242 },
57243/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
57244 {
57245 { 0, 0, 0, 0 },
57246 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57247 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7010000 }
57248 },
57249/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
57250 {
57251 { 0, 0, 0, 0 },
57252 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57253 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7210000 }
57254 },
57255/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
57256 {
57257 { 0, 0, 0, 0 },
57258 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
57259 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3810000 }
57260 },
57261/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
57262 {
57263 { 0, 0, 0, 0 },
57264 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
57265 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a10000 }
57266 },
57267/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
57268 {
57269 { 0, 0, 0, 0 },
57270 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
57271 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5810000 }
57272 },
57273/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
57274 {
57275 { 0, 0, 0, 0 },
57276 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
57277 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a10000 }
57278 },
57279/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
57280 {
57281 { 0, 0, 0, 0 },
57282 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
57283 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c10000 }
57284 },
57285/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
57286 {
57287 { 0, 0, 0, 0 },
57288 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
57289 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e10000 }
57290 },
57291/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
57292 {
57293 { 0, 0, 0, 0 },
57294 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
57295 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c10000 }
57296 },
57297/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
57298 {
57299 { 0, 0, 0, 0 },
57300 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
57301 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e10000 }
57302 },
57303/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
57304 {
57305 { 0, 0, 0, 0 },
57306 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
57307 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c10000 }
57308 },
57309/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
57310 {
57311 { 0, 0, 0, 0 },
57312 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
57313 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e10000 }
57314 },
57315/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
57316 {
57317 { 0, 0, 0, 0 },
57318 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
57319 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7810000 }
57320 },
57321/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
57322 {
57323 { 0, 0, 0, 0 },
57324 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
57325 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a10000 }
57326 },
57327/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
57328 {
57329 { 0, 0, 0, 0 },
57330 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57331 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc901 }
57332 },
57333/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
57334 {
57335 { 0, 0, 0, 0 },
57336 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57337 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8921 }
57338 },
57339/* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57340 {
57341 { 0, 0, 0, 0 },
57342 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57343 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8901 }
57344 },
57345/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
57346 {
57347 { 0, 0, 0, 0 },
57348 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57349 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc181 }
57350 },
57351/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
57352 {
57353 { 0, 0, 0, 0 },
57354 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57355 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a1 }
57356 },
57357/* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57358 {
57359 { 0, 0, 0, 0 },
57360 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57361 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8181 }
57362 },
57363/* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
57364 {
57365 { 0, 0, 0, 0 },
57366 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57367 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc101 }
57368 },
57369/* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
57370 {
57371 { 0, 0, 0, 0 },
57372 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57373 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8121 }
57374 },
57375/* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57376 {
57377 { 0, 0, 0, 0 },
57378 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57379 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8101 }
57380 },
57381/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
57382 {
57383 { 0, 0, 0, 0 },
57384 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57385 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30100 }
57386 },
57387/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
57388 {
57389 { 0, 0, 0, 0 },
57390 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57391 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832100 }
57392 },
57393/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
57394 {
57395 { 0, 0, 0, 0 },
57396 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57397 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830100 }
57398 },
57399/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
57400 {
57401 { 0, 0, 0, 0 },
57402 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57403 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5010000 }
57404 },
57405/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
57406 {
57407 { 0, 0, 0, 0 },
57408 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57409 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85210000 }
57410 },
57411/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
57412 {
57413 { 0, 0, 0, 0 },
57414 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57415 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85010000 }
57416 },
57417/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
57418 {
57419 { 0, 0, 0, 0 },
57420 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57421 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7010000 }
57422 },
57423/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
57424 {
57425 { 0, 0, 0, 0 },
57426 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57427 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87210000 }
57428 },
57429/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
57430 {
57431 { 0, 0, 0, 0 },
57432 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57433 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87010000 }
57434 },
57435/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
57436 {
57437 { 0, 0, 0, 0 },
57438 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57439 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38100 }
57440 },
57441/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
57442 {
57443 { 0, 0, 0, 0 },
57444 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57445 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a100 }
57446 },
57447/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
57448 {
57449 { 0, 0, 0, 0 },
57450 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57451 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838100 }
57452 },
57453/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
57454 {
57455 { 0, 0, 0, 0 },
57456 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57457 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5810000 }
57458 },
57459/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
57460 {
57461 { 0, 0, 0, 0 },
57462 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57463 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a10000 }
57464 },
57465/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
57466 {
57467 { 0, 0, 0, 0 },
57468 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57469 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85810000 }
57470 },
57471/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
57472 {
57473 { 0, 0, 0, 0 },
57474 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57475 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c100 }
57476 },
57477/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
57478 {
57479 { 0, 0, 0, 0 },
57480 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57481 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e100 }
57482 },
57483/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
57484 {
57485 { 0, 0, 0, 0 },
57486 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57487 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c100 }
57488 },
57489/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
57490 {
57491 { 0, 0, 0, 0 },
57492 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57493 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c10000 }
57494 },
57495/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
57496 {
57497 { 0, 0, 0, 0 },
57498 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57499 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e10000 }
57500 },
57501/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
57502 {
57503 { 0, 0, 0, 0 },
57504 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57505 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c10000 }
57506 },
57507/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
57508 {
57509 { 0, 0, 0, 0 },
57510 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
57511 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c10000 }
57512 },
57513/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
57514 {
57515 { 0, 0, 0, 0 },
57516 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
57517 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e10000 }
57518 },
57519/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
57520 {
57521 { 0, 0, 0, 0 },
57522 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
57523 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c10000 }
57524 },
57525/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
57526 {
57527 { 0, 0, 0, 0 },
57528 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
57529 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7810000 }
57530 },
57531/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
57532 {
57533 { 0, 0, 0, 0 },
57534 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
57535 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a10000 }
57536 },
57537/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
57538 {
57539 { 0, 0, 0, 0 },
57540 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
57541 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87810000 }
57542 },
57543/* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
57544 {
57545 { 0, 0, 0, 0 },
57546 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
57547 & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x38 }
57548 },
57549/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
57550 {
57551 { 0, 0, 0, 0 },
57552 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
57553 & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x3900 }
57554 },
57555/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
57556 {
57557 { 0, 0, 0, 0 },
57558 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
57559 & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x3a00 }
57560 },
57561/* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
57562 {
57563 { 0, 0, 0, 0 },
57564 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
57565 & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x3b0000 }
57566 },
57567/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
57568 {
57569 { 0, 0, 0, 0 },
57570 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57571 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990600 }
57572 },
57573/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
57574 {
57575 { 0, 0, 0, 0 },
57576 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57577 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992600 }
57578 },
57579/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
57580 {
57581 { 0, 0, 0, 0 },
57582 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57583 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993600 }
57584 },
57585/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
57586 {
57587 { 0, 0, 0, 0 },
57588 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57589 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918600 }
57590 },
57591/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
57592 {
57593 { 0, 0, 0, 0 },
57594 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57595 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a600 }
57596 },
57597/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
57598 {
57599 { 0, 0, 0, 0 },
57600 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57601 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b600 }
57602 },
57603/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57604 {
57605 { 0, 0, 0, 0 },
57606 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57607 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910600 }
57608 },
57609/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57610 {
57611 { 0, 0, 0, 0 },
57612 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57613 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912600 }
57614 },
57615/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57616 {
57617 { 0, 0, 0, 0 },
57618 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57619 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913600 }
57620 },
57621/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57622 {
57623 { 0, 0, 0, 0 },
57624 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57625 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93060000 }
57626 },
57627/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57628 {
57629 { 0, 0, 0, 0 },
57630 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57631 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93260000 }
57632 },
57633/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57634 {
57635 { 0, 0, 0, 0 },
57636 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57637 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93360000 }
57638 },
57639/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57640 {
57641 { 0, 0, 0, 0 },
57642 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57643 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95060000 }
57644 },
57645/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57646 {
57647 { 0, 0, 0, 0 },
57648 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57649 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95260000 }
57650 },
57651/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57652 {
57653 { 0, 0, 0, 0 },
57654 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57655 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95360000 }
57656 },
57657/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57658 {
57659 { 0, 0, 0, 0 },
57660 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57661 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97060000 }
57662 },
57663/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57664 {
57665 { 0, 0, 0, 0 },
57666 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57667 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97260000 }
57668 },
57669/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57670 {
57671 { 0, 0, 0, 0 },
57672 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57673 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97360000 }
57674 },
57675/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
57676 {
57677 { 0, 0, 0, 0 },
57678 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57679 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93860000 }
57680 },
57681/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57682 {
57683 { 0, 0, 0, 0 },
57684 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57685 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a60000 }
57686 },
57687/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57688 {
57689 { 0, 0, 0, 0 },
57690 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57691 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b60000 }
57692 },
57693/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
57694 {
57695 { 0, 0, 0, 0 },
57696 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57697 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95860000 }
57698 },
57699/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57700 {
57701 { 0, 0, 0, 0 },
57702 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57703 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a60000 }
57704 },
57705/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57706 {
57707 { 0, 0, 0, 0 },
57708 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57709 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b60000 }
57710 },
57711/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
57712 {
57713 { 0, 0, 0, 0 },
57714 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57715 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c60000 }
57716 },
57717/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57718 {
57719 { 0, 0, 0, 0 },
57720 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57721 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e60000 }
57722 },
57723/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57724 {
57725 { 0, 0, 0, 0 },
57726 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57727 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f60000 }
57728 },
57729/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
57730 {
57731 { 0, 0, 0, 0 },
57732 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57733 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c60000 }
57734 },
57735/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
57736 {
57737 { 0, 0, 0, 0 },
57738 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57739 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e60000 }
57740 },
57741/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
57742 {
57743 { 0, 0, 0, 0 },
57744 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57745 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f60000 }
57746 },
57747/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
57748 {
57749 { 0, 0, 0, 0 },
57750 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
57751 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c60000 }
57752 },
57753/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57754 {
57755 { 0, 0, 0, 0 },
57756 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
57757 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e60000 }
57758 },
57759/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57760 {
57761 { 0, 0, 0, 0 },
57762 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
57763 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f60000 }
57764 },
57765/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
57766 {
57767 { 0, 0, 0, 0 },
57768 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
57769 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97860000 }
57770 },
57771/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
57772 {
57773 { 0, 0, 0, 0 },
57774 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
57775 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a60000 }
57776 },
57777/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
57778 {
57779 { 0, 0, 0, 0 },
57780 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
57781 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b60000 }
57782 },
57783/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
57784 {
57785 { 0, 0, 0, 0 },
57786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57787 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9060000 }
57788 },
57789/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
57790 {
57791 { 0, 0, 0, 0 },
57792 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57793 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9260000 }
57794 },
57795/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
57796 {
57797 { 0, 0, 0, 0 },
57798 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57799 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9360000 }
57800 },
57801/* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
57802 {
57803 { 0, 0, 0, 0 },
57804 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57805 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9360000 }
57806 },
57807/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
57808 {
57809 { 0, 0, 0, 0 },
57810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57811 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1860000 }
57812 },
57813/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
57814 {
57815 { 0, 0, 0, 0 },
57816 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57817 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a60000 }
57818 },
57819/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
57820 {
57821 { 0, 0, 0, 0 },
57822 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57823 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b60000 }
57824 },
57825/* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
57826 {
57827 { 0, 0, 0, 0 },
57828 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57829 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b60000 }
57830 },
57831/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57832 {
57833 { 0, 0, 0, 0 },
57834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57835 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1060000 }
57836 },
57837/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
57838 {
57839 { 0, 0, 0, 0 },
57840 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57841 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1260000 }
57842 },
57843/* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
57844 {
57845 { 0, 0, 0, 0 },
57846 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57847 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1360000 }
57848 },
57849/* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
57850 {
57851 { 0, 0, 0, 0 },
57852 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57853 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1360000 }
57854 },
57855/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57856 {
57857 { 0, 0, 0, 0 },
57858 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57859 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3060000 }
57860 },
57861/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57862 {
57863 { 0, 0, 0, 0 },
57864 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57865 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3260000 }
57866 },
57867/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57868 {
57869 { 0, 0, 0, 0 },
57870 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57871 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3360000 }
57872 },
57873/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
57874 {
57875 { 0, 0, 0, 0 },
57876 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57877 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3360000 }
57878 },
57879/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57880 {
57881 { 0, 0, 0, 0 },
57882 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57883 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5060000 }
57884 },
57885/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57886 {
57887 { 0, 0, 0, 0 },
57888 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57889 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5260000 }
57890 },
57891/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57892 {
57893 { 0, 0, 0, 0 },
57894 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57895 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5360000 }
57896 },
57897/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
57898 {
57899 { 0, 0, 0, 0 },
57900 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57901 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5360000 }
57902 },
57903/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57904 {
57905 { 0, 0, 0, 0 },
57906 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57907 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7060000 }
57908 },
57909/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57910 {
57911 { 0, 0, 0, 0 },
57912 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57913 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7260000 }
57914 },
57915/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57916 {
57917 { 0, 0, 0, 0 },
57918 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57919 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7360000 }
57920 },
57921/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
57922 {
57923 { 0, 0, 0, 0 },
57924 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57925 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7360000 }
57926 },
57927/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
57928 {
57929 { 0, 0, 0, 0 },
57930 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57931 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3860000 }
57932 },
57933/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57934 {
57935 { 0, 0, 0, 0 },
57936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57937 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a60000 }
57938 },
57939/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
57940 {
57941 { 0, 0, 0, 0 },
57942 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57943 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b60000 }
57944 },
57945/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57946 {
57947 { 0, 0, 0, 0 },
57948 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57949 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b60000 }
57950 },
57951/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
57952 {
57953 { 0, 0, 0, 0 },
57954 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57955 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5860000 }
57956 },
57957/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57958 {
57959 { 0, 0, 0, 0 },
57960 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57961 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a60000 }
57962 },
57963/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
57964 {
57965 { 0, 0, 0, 0 },
57966 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57967 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b60000 }
57968 },
57969/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57970 {
57971 { 0, 0, 0, 0 },
57972 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57973 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b60000 }
57974 },
57975/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
57976 {
57977 { 0, 0, 0, 0 },
57978 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57979 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c60000 }
57980 },
57981/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57982 {
57983 { 0, 0, 0, 0 },
57984 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57985 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e60000 }
57986 },
57987/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
57988 {
57989 { 0, 0, 0, 0 },
57990 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57991 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f60000 }
57992 },
57993/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57994 {
57995 { 0, 0, 0, 0 },
57996 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57997 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f60000 }
57998 },
57999/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58000 {
58001 { 0, 0, 0, 0 },
58002 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58003 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c60000 }
58004 },
58005/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58006 {
58007 { 0, 0, 0, 0 },
58008 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58009 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e60000 }
58010 },
58011/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58012 {
58013 { 0, 0, 0, 0 },
58014 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58015 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f60000 }
58016 },
58017/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58018 {
58019 { 0, 0, 0, 0 },
58020 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58021 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f60000 }
58022 },
58023/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58024 {
58025 { 0, 0, 0, 0 },
58026 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
58027 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c60000 }
58028 },
58029/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58030 {
58031 { 0, 0, 0, 0 },
58032 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58033 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e60000 }
58034 },
58035/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58036 {
58037 { 0, 0, 0, 0 },
58038 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58039 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f60000 }
58040 },
58041/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
58042 {
58043 { 0, 0, 0, 0 },
58044 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
58045 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f60000 }
58046 },
58047/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58048 {
58049 { 0, 0, 0, 0 },
58050 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
58051 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7860000 }
58052 },
58053/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58054 {
58055 { 0, 0, 0, 0 },
58056 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58057 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a60000 }
58058 },
58059/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58060 {
58061 { 0, 0, 0, 0 },
58062 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58063 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b60000 }
58064 },
58065/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
58066 {
58067 { 0, 0, 0, 0 },
58068 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
58069 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b60000 }
58070 },
58071/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58072 {
58073 { 0, 0, 0, 0 },
58074 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58075 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9060000 }
58076 },
58077/* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
58078 {
58079 { 0, 0, 0, 0 },
58080 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58081 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9260000 }
58082 },
58083/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58084 {
58085 { 0, 0, 0, 0 },
58086 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58087 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1860000 }
58088 },
58089/* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
58090 {
58091 { 0, 0, 0, 0 },
58092 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58093 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a60000 }
58094 },
58095/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58096 {
58097 { 0, 0, 0, 0 },
58098 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58099 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1060000 }
58100 },
58101/* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58102 {
58103 { 0, 0, 0, 0 },
58104 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58105 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1260000 }
58106 },
58107/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58108 {
58109 { 0, 0, 0, 0 },
58110 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58111 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3060000 }
58112 },
58113/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58114 {
58115 { 0, 0, 0, 0 },
58116 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58117 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3260000 }
58118 },
58119/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58120 {
58121 { 0, 0, 0, 0 },
58122 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58123 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5060000 }
58124 },
58125/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58126 {
58127 { 0, 0, 0, 0 },
58128 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58129 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5260000 }
58130 },
58131/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58132 {
58133 { 0, 0, 0, 0 },
58134 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58135 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7060000 }
58136 },
58137/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58138 {
58139 { 0, 0, 0, 0 },
58140 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58141 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7260000 }
58142 },
58143/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58144 {
58145 { 0, 0, 0, 0 },
58146 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
58147 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3860000 }
58148 },
58149/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58150 {
58151 { 0, 0, 0, 0 },
58152 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
58153 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a60000 }
58154 },
58155/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58156 {
58157 { 0, 0, 0, 0 },
58158 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
58159 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5860000 }
58160 },
58161/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58162 {
58163 { 0, 0, 0, 0 },
58164 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
58165 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a60000 }
58166 },
58167/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58168 {
58169 { 0, 0, 0, 0 },
58170 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
58171 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c60000 }
58172 },
58173/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58174 {
58175 { 0, 0, 0, 0 },
58176 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
58177 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e60000 }
58178 },
58179/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58180 {
58181 { 0, 0, 0, 0 },
58182 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
58183 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c60000 }
58184 },
58185/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58186 {
58187 { 0, 0, 0, 0 },
58188 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
58189 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e60000 }
58190 },
58191/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58192 {
58193 { 0, 0, 0, 0 },
58194 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
58195 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c60000 }
58196 },
58197/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
58198 {
58199 { 0, 0, 0, 0 },
58200 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
58201 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e60000 }
58202 },
58203/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58204 {
58205 { 0, 0, 0, 0 },
58206 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
58207 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7860000 }
58208 },
58209/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
58210 {
58211 { 0, 0, 0, 0 },
58212 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
58213 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a60000 }
58214 },
58215/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
58216 {
58217 { 0, 0, 0, 0 },
58218 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58219 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc906 }
58220 },
58221/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
58222 {
58223 { 0, 0, 0, 0 },
58224 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58225 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8926 }
58226 },
58227/* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58228 {
58229 { 0, 0, 0, 0 },
58230 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58231 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8906 }
58232 },
58233/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
58234 {
58235 { 0, 0, 0, 0 },
58236 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58237 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc186 }
58238 },
58239/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
58240 {
58241 { 0, 0, 0, 0 },
58242 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58243 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a6 }
58244 },
58245/* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58246 {
58247 { 0, 0, 0, 0 },
58248 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58249 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8186 }
58250 },
58251/* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
58252 {
58253 { 0, 0, 0, 0 },
58254 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58255 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc106 }
58256 },
58257/* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
58258 {
58259 { 0, 0, 0, 0 },
58260 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58261 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8126 }
58262 },
58263/* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58264 {
58265 { 0, 0, 0, 0 },
58266 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58267 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8106 }
58268 },
58269/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58270 {
58271 { 0, 0, 0, 0 },
58272 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58273 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30600 }
58274 },
58275/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58276 {
58277 { 0, 0, 0, 0 },
58278 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58279 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832600 }
58280 },
58281/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58282 {
58283 { 0, 0, 0, 0 },
58284 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58285 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830600 }
58286 },
58287/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58288 {
58289 { 0, 0, 0, 0 },
58290 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58291 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5060000 }
58292 },
58293/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58294 {
58295 { 0, 0, 0, 0 },
58296 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58297 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85260000 }
58298 },
58299/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58300 {
58301 { 0, 0, 0, 0 },
58302 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58303 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85060000 }
58304 },
58305/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58306 {
58307 { 0, 0, 0, 0 },
58308 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58309 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7060000 }
58310 },
58311/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58312 {
58313 { 0, 0, 0, 0 },
58314 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58315 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87260000 }
58316 },
58317/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58318 {
58319 { 0, 0, 0, 0 },
58320 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58321 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87060000 }
58322 },
58323/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
58324 {
58325 { 0, 0, 0, 0 },
58326 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58327 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38600 }
58328 },
58329/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
58330 {
58331 { 0, 0, 0, 0 },
58332 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58333 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a600 }
58334 },
58335/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58336 {
58337 { 0, 0, 0, 0 },
58338 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58339 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838600 }
58340 },
58341/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
58342 {
58343 { 0, 0, 0, 0 },
58344 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58345 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5860000 }
58346 },
58347/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
58348 {
58349 { 0, 0, 0, 0 },
58350 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58351 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a60000 }
58352 },
58353/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58354 {
58355 { 0, 0, 0, 0 },
58356 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58357 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85860000 }
58358 },
58359/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
58360 {
58361 { 0, 0, 0, 0 },
58362 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58363 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c600 }
58364 },
58365/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
58366 {
58367 { 0, 0, 0, 0 },
58368 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58369 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e600 }
58370 },
58371/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58372 {
58373 { 0, 0, 0, 0 },
58374 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58375 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c600 }
58376 },
58377/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
58378 {
58379 { 0, 0, 0, 0 },
58380 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58381 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c60000 }
58382 },
58383/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
58384 {
58385 { 0, 0, 0, 0 },
58386 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58387 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e60000 }
58388 },
58389/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58390 {
58391 { 0, 0, 0, 0 },
58392 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58393 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c60000 }
58394 },
58395/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
58396 {
58397 { 0, 0, 0, 0 },
58398 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
58399 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c60000 }
58400 },
58401/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
58402 {
58403 { 0, 0, 0, 0 },
58404 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
58405 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e60000 }
58406 },
58407/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58408 {
58409 { 0, 0, 0, 0 },
58410 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
58411 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c60000 }
58412 },
58413/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
58414 {
58415 { 0, 0, 0, 0 },
58416 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
58417 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7860000 }
58418 },
58419/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
58420 {
58421 { 0, 0, 0, 0 },
58422 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
58423 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a60000 }
58424 },
58425/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58426 {
58427 { 0, 0, 0, 0 },
58428 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
58429 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87860000 }
58430 },
58431/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
58432 {
58433 { 0, 0, 0, 0 },
58434 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58435 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980600 }
58436 },
58437/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
58438 {
58439 { 0, 0, 0, 0 },
58440 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58441 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982600 }
58442 },
58443/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
58444 {
58445 { 0, 0, 0, 0 },
58446 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58447 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983600 }
58448 },
58449/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
58450 {
58451 { 0, 0, 0, 0 },
58452 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58453 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908600 }
58454 },
58455/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
58456 {
58457 { 0, 0, 0, 0 },
58458 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58459 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a600 }
58460 },
58461/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
58462 {
58463 { 0, 0, 0, 0 },
58464 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58465 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b600 }
58466 },
58467/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58468 {
58469 { 0, 0, 0, 0 },
58470 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58471 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900600 }
58472 },
58473/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58474 {
58475 { 0, 0, 0, 0 },
58476 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58477 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902600 }
58478 },
58479/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58480 {
58481 { 0, 0, 0, 0 },
58482 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58483 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903600 }
58484 },
58485/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58486 {
58487 { 0, 0, 0, 0 },
58488 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58489 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92060000 }
58490 },
58491/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58492 {
58493 { 0, 0, 0, 0 },
58494 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58495 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92260000 }
58496 },
58497/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58498 {
58499 { 0, 0, 0, 0 },
58500 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58501 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92360000 }
58502 },
58503/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58504 {
58505 { 0, 0, 0, 0 },
58506 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58507 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94060000 }
58508 },
58509/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58510 {
58511 { 0, 0, 0, 0 },
58512 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58513 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94260000 }
58514 },
58515/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58516 {
58517 { 0, 0, 0, 0 },
58518 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58519 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94360000 }
58520 },
58521/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58522 {
58523 { 0, 0, 0, 0 },
58524 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58525 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96060000 }
58526 },
58527/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58528 {
58529 { 0, 0, 0, 0 },
58530 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58531 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96260000 }
58532 },
58533/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58534 {
58535 { 0, 0, 0, 0 },
58536 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58537 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96360000 }
58538 },
58539/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58540 {
58541 { 0, 0, 0, 0 },
58542 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58543 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92860000 }
58544 },
58545/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58546 {
58547 { 0, 0, 0, 0 },
58548 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58549 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a60000 }
58550 },
58551/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58552 {
58553 { 0, 0, 0, 0 },
58554 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58555 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b60000 }
58556 },
58557/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58558 {
58559 { 0, 0, 0, 0 },
58560 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58561 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94860000 }
58562 },
58563/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58564 {
58565 { 0, 0, 0, 0 },
58566 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58567 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a60000 }
58568 },
58569/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58570 {
58571 { 0, 0, 0, 0 },
58572 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58573 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b60000 }
58574 },
58575/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58576 {
58577 { 0, 0, 0, 0 },
58578 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58579 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c60000 }
58580 },
58581/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58582 {
58583 { 0, 0, 0, 0 },
58584 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58585 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e60000 }
58586 },
58587/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58588 {
58589 { 0, 0, 0, 0 },
58590 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58591 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f60000 }
58592 },
58593/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58594 {
58595 { 0, 0, 0, 0 },
58596 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58597 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c60000 }
58598 },
58599/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58600 {
58601 { 0, 0, 0, 0 },
58602 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58603 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e60000 }
58604 },
58605/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58606 {
58607 { 0, 0, 0, 0 },
58608 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58609 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f60000 }
58610 },
58611/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58612 {
58613 { 0, 0, 0, 0 },
58614 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
58615 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c60000 }
58616 },
58617/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58618 {
58619 { 0, 0, 0, 0 },
58620 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
58621 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e60000 }
58622 },
58623/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58624 {
58625 { 0, 0, 0, 0 },
58626 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
58627 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f60000 }
58628 },
58629/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58630 {
58631 { 0, 0, 0, 0 },
58632 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
58633 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96860000 }
58634 },
58635/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58636 {
58637 { 0, 0, 0, 0 },
58638 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
58639 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a60000 }
58640 },
58641/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58642 {
58643 { 0, 0, 0, 0 },
58644 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
58645 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b60000 }
58646 },
58647/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
58648 {
58649 { 0, 0, 0, 0 },
58650 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58651 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8060000 }
58652 },
58653/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
58654 {
58655 { 0, 0, 0, 0 },
58656 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58657 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8260000 }
58658 },
58659/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
58660 {
58661 { 0, 0, 0, 0 },
58662 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58663 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8360000 }
58664 },
58665/* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
58666 {
58667 { 0, 0, 0, 0 },
58668 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58669 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8360000 }
58670 },
58671/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
58672 {
58673 { 0, 0, 0, 0 },
58674 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58675 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0860000 }
58676 },
58677/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
58678 {
58679 { 0, 0, 0, 0 },
58680 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58681 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a60000 }
58682 },
58683/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
58684 {
58685 { 0, 0, 0, 0 },
58686 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58687 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b60000 }
58688 },
58689/* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
58690 {
58691 { 0, 0, 0, 0 },
58692 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58693 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b60000 }
58694 },
58695/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58696 {
58697 { 0, 0, 0, 0 },
58698 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58699 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0060000 }
58700 },
58701/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58702 {
58703 { 0, 0, 0, 0 },
58704 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58705 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0260000 }
58706 },
58707/* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58708 {
58709 { 0, 0, 0, 0 },
58710 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58711 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0360000 }
58712 },
58713/* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58714 {
58715 { 0, 0, 0, 0 },
58716 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58717 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0360000 }
58718 },
58719/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58720 {
58721 { 0, 0, 0, 0 },
58722 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58723 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2060000 }
58724 },
58725/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58726 {
58727 { 0, 0, 0, 0 },
58728 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58729 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2260000 }
58730 },
58731/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58732 {
58733 { 0, 0, 0, 0 },
58734 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58735 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2360000 }
58736 },
58737/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58738 {
58739 { 0, 0, 0, 0 },
58740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58741 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2360000 }
58742 },
58743/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58744 {
58745 { 0, 0, 0, 0 },
58746 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58747 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4060000 }
58748 },
58749/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58750 {
58751 { 0, 0, 0, 0 },
58752 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58753 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4260000 }
58754 },
58755/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58756 {
58757 { 0, 0, 0, 0 },
58758 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58759 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4360000 }
58760 },
58761/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58762 {
58763 { 0, 0, 0, 0 },
58764 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58765 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4360000 }
58766 },
58767/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58768 {
58769 { 0, 0, 0, 0 },
58770 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58771 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6060000 }
58772 },
58773/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58774 {
58775 { 0, 0, 0, 0 },
58776 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58777 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6260000 }
58778 },
58779/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58780 {
58781 { 0, 0, 0, 0 },
58782 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58783 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6360000 }
58784 },
58785/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58786 {
58787 { 0, 0, 0, 0 },
58788 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58789 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6360000 }
58790 },
58791/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58792 {
58793 { 0, 0, 0, 0 },
58794 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58795 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2860000 }
58796 },
58797/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58798 {
58799 { 0, 0, 0, 0 },
58800 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58801 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a60000 }
58802 },
58803/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58804 {
58805 { 0, 0, 0, 0 },
58806 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58807 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b60000 }
58808 },
58809/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58810 {
58811 { 0, 0, 0, 0 },
58812 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58813 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b60000 }
58814 },
58815/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58816 {
58817 { 0, 0, 0, 0 },
58818 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58819 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4860000 }
58820 },
58821/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58822 {
58823 { 0, 0, 0, 0 },
58824 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58825 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a60000 }
58826 },
58827/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58828 {
58829 { 0, 0, 0, 0 },
58830 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58831 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b60000 }
58832 },
58833/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58834 {
58835 { 0, 0, 0, 0 },
58836 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58837 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b60000 }
58838 },
58839/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58840 {
58841 { 0, 0, 0, 0 },
58842 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58843 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c60000 }
58844 },
58845/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58846 {
58847 { 0, 0, 0, 0 },
58848 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58849 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e60000 }
58850 },
58851/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58852 {
58853 { 0, 0, 0, 0 },
58854 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58855 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f60000 }
58856 },
58857/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58858 {
58859 { 0, 0, 0, 0 },
58860 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58861 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f60000 }
58862 },
58863/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58864 {
58865 { 0, 0, 0, 0 },
58866 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58867 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c60000 }
58868 },
58869/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58870 {
58871 { 0, 0, 0, 0 },
58872 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58873 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e60000 }
58874 },
58875/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58876 {
58877 { 0, 0, 0, 0 },
58878 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58879 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f60000 }
58880 },
58881/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58882 {
58883 { 0, 0, 0, 0 },
58884 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58885 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f60000 }
58886 },
58887/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58888 {
58889 { 0, 0, 0, 0 },
58890 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
58891 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c60000 }
58892 },
58893/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58894 {
58895 { 0, 0, 0, 0 },
58896 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58897 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e60000 }
58898 },
58899/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58900 {
58901 { 0, 0, 0, 0 },
58902 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58903 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f60000 }
58904 },
58905/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
58906 {
58907 { 0, 0, 0, 0 },
58908 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
58909 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f60000 }
58910 },
58911/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58912 {
58913 { 0, 0, 0, 0 },
58914 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
58915 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6860000 }
58916 },
58917/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58918 {
58919 { 0, 0, 0, 0 },
58920 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58921 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a60000 }
58922 },
58923/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58924 {
58925 { 0, 0, 0, 0 },
58926 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58927 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b60000 }
58928 },
58929/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
58930 {
58931 { 0, 0, 0, 0 },
58932 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
58933 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b60000 }
58934 },
58935/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
58936 {
58937 { 0, 0, 0, 0 },
58938 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58939 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8060000 }
58940 },
58941/* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
58942 {
58943 { 0, 0, 0, 0 },
58944 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58945 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8260000 }
58946 },
58947/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
58948 {
58949 { 0, 0, 0, 0 },
58950 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58951 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0860000 }
58952 },
58953/* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
58954 {
58955 { 0, 0, 0, 0 },
58956 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58957 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a60000 }
58958 },
58959/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58960 {
58961 { 0, 0, 0, 0 },
58962 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58963 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0060000 }
58964 },
58965/* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58966 {
58967 { 0, 0, 0, 0 },
58968 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58969 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0260000 }
58970 },
58971/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58972 {
58973 { 0, 0, 0, 0 },
58974 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58975 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2060000 }
58976 },
58977/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58978 {
58979 { 0, 0, 0, 0 },
58980 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58981 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2260000 }
58982 },
58983/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58984 {
58985 { 0, 0, 0, 0 },
58986 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58987 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4060000 }
58988 },
58989/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58990 {
58991 { 0, 0, 0, 0 },
58992 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58993 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4260000 }
58994 },
58995/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58996 {
58997 { 0, 0, 0, 0 },
58998 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58999 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6060000 }
59000 },
59001/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59002 {
59003 { 0, 0, 0, 0 },
59004 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59005 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6260000 }
59006 },
59007/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59008 {
59009 { 0, 0, 0, 0 },
59010 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
59011 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2860000 }
59012 },
59013/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59014 {
59015 { 0, 0, 0, 0 },
59016 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
59017 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a60000 }
59018 },
59019/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59020 {
59021 { 0, 0, 0, 0 },
59022 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
59023 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4860000 }
59024 },
59025/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59026 {
59027 { 0, 0, 0, 0 },
59028 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
59029 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a60000 }
59030 },
59031/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59032 {
59033 { 0, 0, 0, 0 },
59034 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
59035 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c60000 }
59036 },
59037/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59038 {
59039 { 0, 0, 0, 0 },
59040 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
59041 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e60000 }
59042 },
59043/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59044 {
59045 { 0, 0, 0, 0 },
59046 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
59047 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c60000 }
59048 },
59049/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59050 {
59051 { 0, 0, 0, 0 },
59052 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
59053 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e60000 }
59054 },
59055/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59056 {
59057 { 0, 0, 0, 0 },
59058 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
59059 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c60000 }
59060 },
59061/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59062 {
59063 { 0, 0, 0, 0 },
59064 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
59065 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e60000 }
59066 },
59067/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59068 {
59069 { 0, 0, 0, 0 },
59070 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
59071 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6860000 }
59072 },
59073/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59074 {
59075 { 0, 0, 0, 0 },
59076 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
59077 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a60000 }
59078 },
59079/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59080 {
59081 { 0, 0, 0, 0 },
59082 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59083 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc806 }
59084 },
59085/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59086 {
59087 { 0, 0, 0, 0 },
59088 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59089 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8826 }
59090 },
59091/* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59092 {
59093 { 0, 0, 0, 0 },
59094 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59095 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8806 }
59096 },
59097/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59098 {
59099 { 0, 0, 0, 0 },
59100 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59101 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc086 }
59102 },
59103/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59104 {
59105 { 0, 0, 0, 0 },
59106 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59107 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a6 }
59108 },
59109/* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59110 {
59111 { 0, 0, 0, 0 },
59112 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59113 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8086 }
59114 },
59115/* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59116 {
59117 { 0, 0, 0, 0 },
59118 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59119 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc006 }
59120 },
59121/* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59122 {
59123 { 0, 0, 0, 0 },
59124 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59125 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8026 }
59126 },
59127/* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59128 {
59129 { 0, 0, 0, 0 },
59130 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59131 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8006 }
59132 },
59133/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59134 {
59135 { 0, 0, 0, 0 },
59136 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59137 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20600 }
59138 },
59139/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59140 {
59141 { 0, 0, 0, 0 },
59142 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59143 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822600 }
59144 },
59145/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59146 {
59147 { 0, 0, 0, 0 },
59148 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59149 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820600 }
59150 },
59151/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59152 {
59153 { 0, 0, 0, 0 },
59154 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59155 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4060000 }
59156 },
59157/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59158 {
59159 { 0, 0, 0, 0 },
59160 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59161 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84260000 }
59162 },
59163/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59164 {
59165 { 0, 0, 0, 0 },
59166 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59167 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84060000 }
59168 },
59169/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59170 {
59171 { 0, 0, 0, 0 },
59172 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59173 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6060000 }
59174 },
59175/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59176 {
59177 { 0, 0, 0, 0 },
59178 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59179 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86260000 }
59180 },
59181/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59182 {
59183 { 0, 0, 0, 0 },
59184 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59185 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86060000 }
59186 },
59187/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
59188 {
59189 { 0, 0, 0, 0 },
59190 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59191 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28600 }
59192 },
59193/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
59194 {
59195 { 0, 0, 0, 0 },
59196 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59197 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a600 }
59198 },
59199/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59200 {
59201 { 0, 0, 0, 0 },
59202 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59203 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828600 }
59204 },
59205/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
59206 {
59207 { 0, 0, 0, 0 },
59208 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59209 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4860000 }
59210 },
59211/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
59212 {
59213 { 0, 0, 0, 0 },
59214 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59215 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a60000 }
59216 },
59217/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59218 {
59219 { 0, 0, 0, 0 },
59220 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59221 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84860000 }
59222 },
59223/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
59224 {
59225 { 0, 0, 0, 0 },
59226 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59227 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c600 }
59228 },
59229/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
59230 {
59231 { 0, 0, 0, 0 },
59232 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59233 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e600 }
59234 },
59235/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59236 {
59237 { 0, 0, 0, 0 },
59238 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59239 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c600 }
59240 },
59241/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
59242 {
59243 { 0, 0, 0, 0 },
59244 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59245 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c60000 }
59246 },
59247/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
59248 {
59249 { 0, 0, 0, 0 },
59250 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59251 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e60000 }
59252 },
59253/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59254 {
59255 { 0, 0, 0, 0 },
59256 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59257 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c60000 }
59258 },
59259/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
59260 {
59261 { 0, 0, 0, 0 },
59262 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
59263 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c60000 }
59264 },
59265/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
59266 {
59267 { 0, 0, 0, 0 },
59268 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
59269 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e60000 }
59270 },
59271/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59272 {
59273 { 0, 0, 0, 0 },
59274 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
59275 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c60000 }
59276 },
59277/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
59278 {
59279 { 0, 0, 0, 0 },
59280 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
59281 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6860000 }
59282 },
59283/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
59284 {
59285 { 0, 0, 0, 0 },
59286 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
59287 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a60000 }
59288 },
59289/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59290 {
59291 { 0, 0, 0, 0 },
59292 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
59293 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86860000 }
59294 },
59295/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
59296 {
59297 { 0, 0, 0, 0 },
59298 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
59299 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xc18000 }
59300 },
59301/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
59302 {
59303 { 0, 0, 0, 0 },
59304 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
59305 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1a000 }
59306 },
59307/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
59308 {
59309 { 0, 0, 0, 0 },
59310 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
59311 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xc1b000 }
59312 },
59313/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
59314 {
59315 { 0, 0, 0, 0 },
59316 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
59317 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xc18400 }
59318 },
59319/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
59320 {
59321 { 0, 0, 0, 0 },
59322 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
59323 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xc1a400 }
59324 },
59325/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
59326 {
59327 { 0, 0, 0, 0 },
59328 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
59329 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xc1b400 }
59330 },
59331/* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
59332 {
59333 { 0, 0, 0, 0 },
59334 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59335 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xc18600 }
59336 },
59337/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
59338 {
59339 { 0, 0, 0, 0 },
59340 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59341 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xc1a600 }
59342 },
59343/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
59344 {
59345 { 0, 0, 0, 0 },
59346 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59347 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xc1b600 }
59348 },
59349/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
59350 {
59351 { 0, 0, 0, 0 },
59352 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59353 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xc1880000 }
59354 },
59355/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
59356 {
59357 { 0, 0, 0, 0 },
59358 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59359 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1a80000 }
59360 },
59361/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
59362 {
59363 { 0, 0, 0, 0 },
59364 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59365 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1b80000 }
59366 },
59367/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
59368 {
59369 { 0, 0, 0, 0 },
59370 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59371 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xc18c0000 }
59372 },
59373/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
59374 {
59375 { 0, 0, 0, 0 },
59376 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59377 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1ac0000 }
59378 },
59379/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
59380 {
59381 { 0, 0, 0, 0 },
59382 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59383 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1bc0000 }
59384 },
59385/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
59386 {
59387 { 0, 0, 0, 0 },
59388 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59389 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xc18a0000 }
59390 },
59391/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59392 {
59393 { 0, 0, 0, 0 },
59394 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59395 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1aa0000 }
59396 },
59397/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59398 {
59399 { 0, 0, 0, 0 },
59400 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59401 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1ba0000 }
59402 },
59403/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
59404 {
59405 { 0, 0, 0, 0 },
59406 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59407 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xc18e0000 }
59408 },
59409/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59410 {
59411 { 0, 0, 0, 0 },
59412 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59413 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1ae0000 }
59414 },
59415/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59416 {
59417 { 0, 0, 0, 0 },
59418 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59419 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1be0000 }
59420 },
59421/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
59422 {
59423 { 0, 0, 0, 0 },
59424 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59425 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xc18b0000 }
59426 },
59427/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59428 {
59429 { 0, 0, 0, 0 },
59430 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59431 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1ab0000 }
59432 },
59433/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59434 {
59435 { 0, 0, 0, 0 },
59436 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59437 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1bb0000 }
59438 },
59439/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
59440 {
59441 { 0, 0, 0, 0 },
59442 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
59443 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xc18f0000 }
59444 },
59445/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59446 {
59447 { 0, 0, 0, 0 },
59448 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59449 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xc1af0000 }
59450 },
59451/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59452 {
59453 { 0, 0, 0, 0 },
59454 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59455 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xc1bf0000 }
59456 },
59457/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
59458 {
59459 { 0, 0, 0, 0 },
59460 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
59461 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xc1c00000 }
59462 },
59463/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
59464 {
59465 { 0, 0, 0, 0 },
59466 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
59467 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1e00000 }
59468 },
59469/* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
59470 {
59471 { 0, 0, 0, 0 },
59472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
59473 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xc1f00000 }
59474 },
59475/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
59476 {
59477 { 0, 0, 0, 0 },
59478 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
59479 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xc1c40000 }
59480 },
59481/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
59482 {
59483 { 0, 0, 0, 0 },
59484 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
59485 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xc1e40000 }
59486 },
59487/* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
59488 {
59489 { 0, 0, 0, 0 },
59490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
59491 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xc1f40000 }
59492 },
59493/* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
59494 {
59495 { 0, 0, 0, 0 },
59496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59497 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xc1c60000 }
59498 },
59499/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
59500 {
59501 { 0, 0, 0, 0 },
59502 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59503 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xc1e60000 }
59504 },
59505/* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
59506 {
59507 { 0, 0, 0, 0 },
59508 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
59509 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xc1f60000 }
59510 },
59511/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
59512 {
59513 { 0, 0, 0, 0 },
59514 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59515 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xc1c80000 }
59516 },
59517/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
59518 {
59519 { 0, 0, 0, 0 },
59520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59521 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xc1e80000 }
59522 },
59523/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
59524 {
59525 { 0, 0, 0, 0 },
59526 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59527 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xc1f80000 }
59528 },
59529/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
59530 {
59531 { 0, 0, 0, 0 },
59532 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59533 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xc1cc0000 }
59534 },
59535/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
59536 {
59537 { 0, 0, 0, 0 },
59538 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59539 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xc1ec0000 }
59540 },
59541/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
59542 {
59543 { 0, 0, 0, 0 },
59544 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59545 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xc1fc0000 }
59546 },
59547/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
59548 {
59549 { 0, 0, 0, 0 },
59550 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59551 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ca0000 }
59552 },
59553/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59554 {
59555 { 0, 0, 0, 0 },
59556 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59557 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ea0000 }
59558 },
59559/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59560 {
59561 { 0, 0, 0, 0 },
59562 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59563 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xc1fa0000 }
59564 },
59565/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
59566 {
59567 { 0, 0, 0, 0 },
59568 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59569 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ce0000 }
59570 },
59571/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59572 {
59573 { 0, 0, 0, 0 },
59574 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59575 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ee0000 }
59576 },
59577/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59578 {
59579 { 0, 0, 0, 0 },
59580 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59581 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xc1fe0000 }
59582 },
59583/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
59584 {
59585 { 0, 0, 0, 0 },
59586 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59587 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1cb0000 }
59588 },
59589/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59590 {
59591 { 0, 0, 0, 0 },
59592 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59593 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1eb0000 }
59594 },
59595/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59596 {
59597 { 0, 0, 0, 0 },
59598 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59599 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xc1fb0000 }
59600 },
59601/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
59602 {
59603 { 0, 0, 0, 0 },
59604 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
59605 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xc1cf0000 }
59606 },
59607/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59608 {
59609 { 0, 0, 0, 0 },
59610 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
59611 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xc1ef0000 }
59612 },
59613/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
59614 {
59615 { 0, 0, 0, 0 },
59616 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
59617 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xc1ff0000 }
59618 },
59619/* cmp.w${G} $Src16RnHI,$Dst16RnHI */
59620 {
59621 { 0, 0, 0, 0 },
59622 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
59623 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xc100 }
59624 },
59625/* cmp.w${G} $Src16AnHI,$Dst16RnHI */
59626 {
59627 { 0, 0, 0, 0 },
59628 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
59629 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xc140 }
59630 },
59631/* cmp.w${G} [$Src16An],$Dst16RnHI */
59632 {
59633 { 0, 0, 0, 0 },
59634 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
59635 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xc160 }
59636 },
59637/* cmp.w${G} $Src16RnHI,$Dst16AnHI */
59638 {
59639 { 0, 0, 0, 0 },
59640 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
59641 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xc104 }
59642 },
59643/* cmp.w${G} $Src16AnHI,$Dst16AnHI */
59644 {
59645 { 0, 0, 0, 0 },
59646 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
59647 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xc144 }
59648 },
59649/* cmp.w${G} [$Src16An],$Dst16AnHI */
59650 {
59651 { 0, 0, 0, 0 },
59652 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
59653 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xc164 }
59654 },
59655/* cmp.w${G} $Src16RnHI,[$Dst16An] */
59656 {
59657 { 0, 0, 0, 0 },
59658 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
59659 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xc106 }
59660 },
59661/* cmp.w${G} $Src16AnHI,[$Dst16An] */
59662 {
59663 { 0, 0, 0, 0 },
59664 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
59665 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xc146 }
59666 },
59667/* cmp.w${G} [$Src16An],[$Dst16An] */
59668 {
59669 { 0, 0, 0, 0 },
59670 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59671 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xc166 }
59672 },
59673/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
59674 {
59675 { 0, 0, 0, 0 },
59676 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
59677 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xc10800 }
59678 },
59679/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
59680 {
59681 { 0, 0, 0, 0 },
59682 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
59683 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xc14800 }
59684 },
59685/* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
59686 {
59687 { 0, 0, 0, 0 },
59688 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
59689 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xc16800 }
59690 },
59691/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
59692 {
59693 { 0, 0, 0, 0 },
59694 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
59695 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xc10c0000 }
59696 },
59697/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
59698 {
59699 { 0, 0, 0, 0 },
59700 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
59701 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xc14c0000 }
59702 },
59703/* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
59704 {
59705 { 0, 0, 0, 0 },
59706 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
59707 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xc16c0000 }
59708 },
59709/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
59710 {
59711 { 0, 0, 0, 0 },
59712 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59713 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xc10a00 }
59714 },
59715/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
59716 {
59717 { 0, 0, 0, 0 },
59718 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59719 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xc14a00 }
59720 },
59721/* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
59722 {
59723 { 0, 0, 0, 0 },
59724 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59725 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xc16a00 }
59726 },
59727/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
59728 {
59729 { 0, 0, 0, 0 },
59730 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59731 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xc10e0000 }
59732 },
59733/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
59734 {
59735 { 0, 0, 0, 0 },
59736 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59737 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xc14e0000 }
59738 },
59739/* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
59740 {
59741 { 0, 0, 0, 0 },
59742 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59743 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xc16e0000 }
59744 },
59745/* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
59746 {
59747 { 0, 0, 0, 0 },
59748 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59749 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xc10b00 }
59750 },
59751/* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
59752 {
59753 { 0, 0, 0, 0 },
59754 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59755 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xc14b00 }
59756 },
59757/* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
59758 {
59759 { 0, 0, 0, 0 },
59760 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59761 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xc16b00 }
59762 },
59763/* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
59764 {
59765 { 0, 0, 0, 0 },
59766 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
59767 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xc10f0000 }
59768 },
59769/* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
59770 {
59771 { 0, 0, 0, 0 },
59772 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
59773 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xc14f0000 }
59774 },
59775/* cmp.w${G} [$Src16An],${Dsp-16-u16} */
59776 {
59777 { 0, 0, 0, 0 },
59778 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
59779 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xc16f0000 }
59780 },
59781/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
59782 {
59783 { 0, 0, 0, 0 },
59784 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
59785 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xc08000 }
59786 },
59787/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
59788 {
59789 { 0, 0, 0, 0 },
59790 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
59791 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0a000 }
59792 },
59793/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
59794 {
59795 { 0, 0, 0, 0 },
59796 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
59797 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xc0b000 }
59798 },
59799/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
59800 {
59801 { 0, 0, 0, 0 },
59802 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
59803 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xc08400 }
59804 },
59805/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
59806 {
59807 { 0, 0, 0, 0 },
59808 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
59809 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xc0a400 }
59810 },
59811/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
59812 {
59813 { 0, 0, 0, 0 },
59814 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
59815 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xc0b400 }
59816 },
59817/* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
59818 {
59819 { 0, 0, 0, 0 },
59820 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59821 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xc08600 }
59822 },
59823/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
59824 {
59825 { 0, 0, 0, 0 },
59826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59827 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xc0a600 }
59828 },
59829/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
59830 {
59831 { 0, 0, 0, 0 },
59832 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59833 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xc0b600 }
59834 },
59835/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
59836 {
59837 { 0, 0, 0, 0 },
59838 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59839 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xc0880000 }
59840 },
59841/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
59842 {
59843 { 0, 0, 0, 0 },
59844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59845 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0a80000 }
59846 },
59847/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
59848 {
59849 { 0, 0, 0, 0 },
59850 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59851 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0b80000 }
59852 },
59853/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
59854 {
59855 { 0, 0, 0, 0 },
59856 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59857 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xc08c0000 }
59858 },
59859/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
59860 {
59861 { 0, 0, 0, 0 },
59862 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59863 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0ac0000 }
59864 },
59865/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
59866 {
59867 { 0, 0, 0, 0 },
59868 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59869 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0bc0000 }
59870 },
59871/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
59872 {
59873 { 0, 0, 0, 0 },
59874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59875 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xc08a0000 }
59876 },
59877/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59878 {
59879 { 0, 0, 0, 0 },
59880 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59881 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0aa0000 }
59882 },
59883/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59884 {
59885 { 0, 0, 0, 0 },
59886 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59887 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0ba0000 }
59888 },
59889/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
59890 {
59891 { 0, 0, 0, 0 },
59892 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59893 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xc08e0000 }
59894 },
59895/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59896 {
59897 { 0, 0, 0, 0 },
59898 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59899 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0ae0000 }
59900 },
59901/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59902 {
59903 { 0, 0, 0, 0 },
59904 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59905 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0be0000 }
59906 },
59907/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
59908 {
59909 { 0, 0, 0, 0 },
59910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59911 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xc08b0000 }
59912 },
59913/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59914 {
59915 { 0, 0, 0, 0 },
59916 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59917 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0ab0000 }
59918 },
59919/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59920 {
59921 { 0, 0, 0, 0 },
59922 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59923 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0bb0000 }
59924 },
59925/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
59926 {
59927 { 0, 0, 0, 0 },
59928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
59929 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xc08f0000 }
59930 },
59931/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59932 {
59933 { 0, 0, 0, 0 },
59934 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59935 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xc0af0000 }
59936 },
59937/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59938 {
59939 { 0, 0, 0, 0 },
59940 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59941 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xc0bf0000 }
59942 },
59943/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
59944 {
59945 { 0, 0, 0, 0 },
59946 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
59947 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xc0c00000 }
59948 },
59949/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
59950 {
59951 { 0, 0, 0, 0 },
59952 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
59953 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0e00000 }
59954 },
59955/* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
59956 {
59957 { 0, 0, 0, 0 },
59958 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
59959 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xc0f00000 }
59960 },
59961/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
59962 {
59963 { 0, 0, 0, 0 },
59964 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
59965 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xc0c40000 }
59966 },
59967/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
59968 {
59969 { 0, 0, 0, 0 },
59970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
59971 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xc0e40000 }
59972 },
59973/* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
59974 {
59975 { 0, 0, 0, 0 },
59976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
59977 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xc0f40000 }
59978 },
59979/* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
59980 {
59981 { 0, 0, 0, 0 },
59982 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59983 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xc0c60000 }
59984 },
59985/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
59986 {
59987 { 0, 0, 0, 0 },
59988 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59989 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xc0e60000 }
59990 },
59991/* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
59992 {
59993 { 0, 0, 0, 0 },
59994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
59995 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xc0f60000 }
59996 },
59997/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
59998 {
59999 { 0, 0, 0, 0 },
60000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60001 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xc0c80000 }
60002 },
60003/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60004 {
60005 { 0, 0, 0, 0 },
60006 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60007 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xc0e80000 }
60008 },
60009/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60010 {
60011 { 0, 0, 0, 0 },
60012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60013 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xc0f80000 }
60014 },
60015/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60016 {
60017 { 0, 0, 0, 0 },
60018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60019 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xc0cc0000 }
60020 },
60021/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60022 {
60023 { 0, 0, 0, 0 },
60024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60025 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xc0ec0000 }
60026 },
60027/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60028 {
60029 { 0, 0, 0, 0 },
60030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60031 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xc0fc0000 }
60032 },
60033/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60034 {
60035 { 0, 0, 0, 0 },
60036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60037 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ca0000 }
60038 },
60039/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60040 {
60041 { 0, 0, 0, 0 },
60042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60043 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ea0000 }
60044 },
60045/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60046 {
60047 { 0, 0, 0, 0 },
60048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60049 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xc0fa0000 }
60050 },
60051/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60052 {
60053 { 0, 0, 0, 0 },
60054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60055 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ce0000 }
60056 },
60057/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60058 {
60059 { 0, 0, 0, 0 },
60060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60061 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ee0000 }
60062 },
60063/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60064 {
60065 { 0, 0, 0, 0 },
60066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60067 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xc0fe0000 }
60068 },
60069/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60070 {
60071 { 0, 0, 0, 0 },
60072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60073 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0cb0000 }
60074 },
60075/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60076 {
60077 { 0, 0, 0, 0 },
60078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60079 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0eb0000 }
60080 },
60081/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60082 {
60083 { 0, 0, 0, 0 },
60084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60085 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xc0fb0000 }
60086 },
60087/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60088 {
60089 { 0, 0, 0, 0 },
60090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
60091 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xc0cf0000 }
60092 },
60093/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60094 {
60095 { 0, 0, 0, 0 },
60096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
60097 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xc0ef0000 }
60098 },
60099/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60100 {
60101 { 0, 0, 0, 0 },
60102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
60103 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xc0ff0000 }
60104 },
60105/* cmp.b${G} $Src16RnQI,$Dst16RnQI */
60106 {
60107 { 0, 0, 0, 0 },
60108 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
60109 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xc000 }
60110 },
60111/* cmp.b${G} $Src16AnQI,$Dst16RnQI */
60112 {
60113 { 0, 0, 0, 0 },
60114 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
60115 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xc040 }
60116 },
60117/* cmp.b${G} [$Src16An],$Dst16RnQI */
60118 {
60119 { 0, 0, 0, 0 },
60120 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
60121 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xc060 }
60122 },
60123/* cmp.b${G} $Src16RnQI,$Dst16AnQI */
60124 {
60125 { 0, 0, 0, 0 },
60126 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
60127 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xc004 }
60128 },
60129/* cmp.b${G} $Src16AnQI,$Dst16AnQI */
60130 {
60131 { 0, 0, 0, 0 },
60132 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
60133 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xc044 }
60134 },
60135/* cmp.b${G} [$Src16An],$Dst16AnQI */
60136 {
60137 { 0, 0, 0, 0 },
60138 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
60139 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xc064 }
60140 },
60141/* cmp.b${G} $Src16RnQI,[$Dst16An] */
60142 {
60143 { 0, 0, 0, 0 },
60144 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
60145 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xc006 }
60146 },
60147/* cmp.b${G} $Src16AnQI,[$Dst16An] */
60148 {
60149 { 0, 0, 0, 0 },
60150 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
60151 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xc046 }
60152 },
60153/* cmp.b${G} [$Src16An],[$Dst16An] */
60154 {
60155 { 0, 0, 0, 0 },
60156 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60157 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xc066 }
60158 },
60159/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60160 {
60161 { 0, 0, 0, 0 },
60162 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60163 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xc00800 }
60164 },
60165/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60166 {
60167 { 0, 0, 0, 0 },
60168 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60169 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xc04800 }
60170 },
60171/* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60172 {
60173 { 0, 0, 0, 0 },
60174 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60175 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xc06800 }
60176 },
60177/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60178 {
60179 { 0, 0, 0, 0 },
60180 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60181 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xc00c0000 }
60182 },
60183/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60184 {
60185 { 0, 0, 0, 0 },
60186 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60187 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xc04c0000 }
60188 },
60189/* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60190 {
60191 { 0, 0, 0, 0 },
60192 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60193 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xc06c0000 }
60194 },
60195/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60196 {
60197 { 0, 0, 0, 0 },
60198 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60199 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xc00a00 }
60200 },
60201/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60202 {
60203 { 0, 0, 0, 0 },
60204 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60205 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xc04a00 }
60206 },
60207/* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60208 {
60209 { 0, 0, 0, 0 },
60210 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60211 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xc06a00 }
60212 },
60213/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60214 {
60215 { 0, 0, 0, 0 },
60216 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60217 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xc00e0000 }
60218 },
60219/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60220 {
60221 { 0, 0, 0, 0 },
60222 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60223 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xc04e0000 }
60224 },
60225/* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60226 {
60227 { 0, 0, 0, 0 },
60228 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60229 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xc06e0000 }
60230 },
60231/* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60232 {
60233 { 0, 0, 0, 0 },
60234 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60235 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xc00b00 }
60236 },
60237/* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60238 {
60239 { 0, 0, 0, 0 },
60240 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60241 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xc04b00 }
60242 },
60243/* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60244 {
60245 { 0, 0, 0, 0 },
60246 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60247 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xc06b00 }
60248 },
60249/* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
60250 {
60251 { 0, 0, 0, 0 },
60252 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
60253 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xc00f0000 }
60254 },
60255/* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
60256 {
60257 { 0, 0, 0, 0 },
60258 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
60259 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xc04f0000 }
60260 },
60261/* cmp.b${G} [$Src16An],${Dsp-16-u16} */
60262 {
60263 { 0, 0, 0, 0 },
60264 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
60265 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xc06f0000 }
60266 },
60267/* cmp.b${S} #${Imm-8-QI},r0l */
60268 {
60269 { 0, 0, 0, 0 },
60270 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
60271 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xe400 }
60272 },
60273/* cmp.b${S} #${Imm-8-QI},r0h */
60274 {
60275 { 0, 0, 0, 0 },
60276 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
60277 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xe300 }
60278 },
60279/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60280 {
60281 { 0, 0, 0, 0 },
60282 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60283 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xe50000 }
60284 },
60285/* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60286 {
60287 { 0, 0, 0, 0 },
60288 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60289 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xe60000 }
60290 },
60291/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60292 {
60293 { 0, 0, 0, 0 },
60294 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
60295 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xe7000000 }
60296 },
60297/* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60298 {
60299 { 0, 0, 0, 0 },
60300 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
60301 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe910 }
60302 },
60303/* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60304 {
60305 { 0, 0, 0, 0 },
60306 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
60307 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe190 }
60308 },
60309/* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60310 {
60311 { 0, 0, 0, 0 },
60312 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60313 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe110 }
60314 },
60315/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60316 {
60317 { 0, 0, 0, 0 },
60318 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60319 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe31000 }
60320 },
60321/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60322 {
60323 { 0, 0, 0, 0 },
60324 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60325 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5100000 }
60326 },
60327/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60328 {
60329 { 0, 0, 0, 0 },
60330 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60331 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7100000 }
60332 },
60333/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60334 {
60335 { 0, 0, 0, 0 },
60336 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60337 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe39000 }
60338 },
60339/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60340 {
60341 { 0, 0, 0, 0 },
60342 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60343 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5900000 }
60344 },
60345/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60346 {
60347 { 0, 0, 0, 0 },
60348 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60349 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3d000 }
60350 },
60351/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60352 {
60353 { 0, 0, 0, 0 },
60354 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60355 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5d00000 }
60356 },
60357/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
60358 {
60359 { 0, 0, 0, 0 },
60360 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
60361 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7d00000 }
60362 },
60363/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
60364 {
60365 { 0, 0, 0, 0 },
60366 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
60367 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7900000 }
60368 },
60369/* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
60370 {
60371 { 0, 0, 0, 0 },
60372 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
60373 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe810 }
60374 },
60375/* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
60376 {
60377 { 0, 0, 0, 0 },
60378 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
60379 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe090 }
60380 },
60381/* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60382 {
60383 { 0, 0, 0, 0 },
60384 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60385 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe010 }
60386 },
60387/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60388 {
60389 { 0, 0, 0, 0 },
60390 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60391 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe21000 }
60392 },
60393/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60394 {
60395 { 0, 0, 0, 0 },
60396 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60397 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4100000 }
60398 },
60399/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60400 {
60401 { 0, 0, 0, 0 },
60402 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60403 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6100000 }
60404 },
60405/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60406 {
60407 { 0, 0, 0, 0 },
60408 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60409 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe29000 }
60410 },
60411/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60412 {
60413 { 0, 0, 0, 0 },
60414 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60415 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4900000 }
60416 },
60417/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60418 {
60419 { 0, 0, 0, 0 },
60420 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60421 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2d000 }
60422 },
60423/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60424 {
60425 { 0, 0, 0, 0 },
60426 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60427 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4d00000 }
60428 },
60429/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
60430 {
60431 { 0, 0, 0, 0 },
60432 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
60433 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6d00000 }
60434 },
60435/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
60436 {
60437 { 0, 0, 0, 0 },
60438 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
60439 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6900000 }
60440 },
60441/* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
60442 {
60443 { 0, 0, 0, 0 },
60444 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
60445 & ifmt_cmp16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd100 }
60446 },
60447/* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
60448 {
60449 { 0, 0, 0, 0 },
60450 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
60451 & ifmt_cmp16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd104 }
60452 },
60453/* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
60454 {
60455 { 0, 0, 0, 0 },
60456 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
60457 & ifmt_cmp16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd106 }
60458 },
60459/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60460 {
60461 { 0, 0, 0, 0 },
60462 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60463 & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd10800 }
60464 },
60465/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60466 {
60467 { 0, 0, 0, 0 },
60468 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60469 & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd10c0000 }
60470 },
60471/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60472 {
60473 { 0, 0, 0, 0 },
60474 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60475 & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd10a00 }
60476 },
60477/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60478 {
60479 { 0, 0, 0, 0 },
60480 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60481 & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd10e0000 }
60482 },
60483/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60484 {
60485 { 0, 0, 0, 0 },
60486 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60487 & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd10b00 }
60488 },
60489/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
60490 {
60491 { 0, 0, 0, 0 },
60492 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
60493 & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd10f0000 }
60494 },
60495/* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
60496 {
60497 { 0, 0, 0, 0 },
60498 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
60499 & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xd000 }
60500 },
60501/* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
60502 {
60503 { 0, 0, 0, 0 },
60504 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
60505 & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xd004 }
60506 },
60507/* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
60508 {
60509 { 0, 0, 0, 0 },
60510 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
60511 & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xd006 }
60512 },
60513/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60514 {
60515 { 0, 0, 0, 0 },
60516 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60517 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd00800 }
60518 },
60519/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60520 {
60521 { 0, 0, 0, 0 },
60522 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60523 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd00c0000 }
60524 },
60525/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60526 {
60527 { 0, 0, 0, 0 },
60528 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60529 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd00a00 }
60530 },
60531/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60532 {
60533 { 0, 0, 0, 0 },
60534 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60535 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd00e0000 }
60536 },
60537/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60538 {
60539 { 0, 0, 0, 0 },
60540 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60541 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd00b00 }
60542 },
60543/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
60544 {
60545 { 0, 0, 0, 0 },
60546 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
60547 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd00f0000 }
60548 },
60549/* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
60550 {
60551 { 0, 0, 0, 0 },
60552 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
60553 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992e0000 }
60554 },
60555/* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
60556 {
60557 { 0, 0, 0, 0 },
60558 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
60559 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91ae0000 }
60560 },
60561/* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
60562 {
60563 { 0, 0, 0, 0 },
60564 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60565 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912e0000 }
60566 },
60567/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60568 {
60569 { 0, 0, 0, 0 },
60570 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60571 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932e0000 }
60572 },
60573/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
60574 {
60575 { 0, 0, 0, 0 },
60576 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60577 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93ae0000 }
60578 },
60579/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
60580 {
60581 { 0, 0, 0, 0 },
60582 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60583 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ee0000 }
60584 },
60585/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60586 {
60587 { 0, 0, 0, 0 },
60588 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60589 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952e0000 }
60590 },
60591/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
60592 {
60593 { 0, 0, 0, 0 },
60594 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60595 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95ae0000 }
60596 },
60597/* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
60598 {
60599 { 0, 0, 0, 0 },
60600 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60601 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ee0000 }
60602 },
60603/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
60604 {
60605 { 0, 0, 0, 0 },
60606 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
60607 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ee0000 }
60608 },
60609/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60610 {
60611 { 0, 0, 0, 0 },
60612 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60613 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972e0000 }
60614 },
60615/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
60616 {
60617 { 0, 0, 0, 0 },
60618 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
60619 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97ae0000 }
60620 },
60621/* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
60622 {
60623 { 0, 0, 0, 0 },
60624 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
60625 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982e00 }
60626 },
60627/* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
60628 {
60629 { 0, 0, 0, 0 },
60630 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
60631 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90ae00 }
60632 },
60633/* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
60634 {
60635 { 0, 0, 0, 0 },
60636 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60637 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902e00 }
60638 },
60639/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60640 {
60641 { 0, 0, 0, 0 },
60642 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60643 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922e0000 }
60644 },
60645/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
60646 {
60647 { 0, 0, 0, 0 },
60648 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60649 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92ae0000 }
60650 },
60651/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
60652 {
60653 { 0, 0, 0, 0 },
60654 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60655 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ee0000 }
60656 },
60657/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60658 {
60659 { 0, 0, 0, 0 },
60660 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60661 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942e0000 }
60662 },
60663/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
60664 {
60665 { 0, 0, 0, 0 },
60666 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60667 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94ae0000 }
60668 },
60669/* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
60670 {
60671 { 0, 0, 0, 0 },
60672 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60673 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ee0000 }
60674 },
60675/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
60676 {
60677 { 0, 0, 0, 0 },
60678 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
60679 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ee0000 }
60680 },
60681/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60682 {
60683 { 0, 0, 0, 0 },
60684 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60685 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962e0000 }
60686 },
60687/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
60688 {
60689 { 0, 0, 0, 0 },
60690 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
60691 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96ae0000 }
60692 },
60693/* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
60694 {
60695 { 0, 0, 0, 0 },
60696 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
60697 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77800000 }
60698 },
60699/* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
60700 {
60701 { 0, 0, 0, 0 },
60702 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
60703 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77840000 }
60704 },
60705/* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
60706 {
60707 { 0, 0, 0, 0 },
60708 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
60709 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77860000 }
60710 },
60711/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
60712 {
60713 { 0, 0, 0, 0 },
60714 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60715 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77880000 }
60716 },
60717/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
60718 {
60719 { 0, 0, 0, 0 },
60720 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60721 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x778a0000 }
60722 },
60723/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
60724 {
60725 { 0, 0, 0, 0 },
60726 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60727 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x778b0000 }
60728 },
60729/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
60730 {
60731 { 0, 0, 0, 0 },
60732 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60733 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x778c0000 }
60734 },
60735/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
60736 {
60737 { 0, 0, 0, 0 },
60738 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60739 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x778e0000 }
60740 },
60741/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
60742 {
60743 { 0, 0, 0, 0 },
60744 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
60745 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x778f0000 }
60746 },
60747/* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
60748 {
60749 { 0, 0, 0, 0 },
60750 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
60751 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x768000 }
60752 },
60753/* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
60754 {
60755 { 0, 0, 0, 0 },
60756 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
60757 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x768400 }
60758 },
60759/* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
60760 {
60761 { 0, 0, 0, 0 },
60762 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
60763 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x768600 }
60764 },
60765/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
60766 {
60767 { 0, 0, 0, 0 },
60768 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60769 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76880000 }
60770 },
60771/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
60772 {
60773 { 0, 0, 0, 0 },
60774 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60775 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x768a0000 }
60776 },
60777/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
60778 {
60779 { 0, 0, 0, 0 },
60780 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60781 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x768b0000 }
60782 },
60783/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
60784 {
60785 { 0, 0, 0, 0 },
60786 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60787 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x768c0000 }
60788 },
60789/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
60790 {
60791 { 0, 0, 0, 0 },
60792 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60793 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x768e0000 }
60794 },
60795/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
60796 {
60797 { 0, 0, 0, 0 },
60798 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
60799 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x768f0000 }
60800 },
60801/* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
60802 {
60803 { 0, 0, 0, 0 },
60804 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
60805 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa8310000 }
60806 },
60807/* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
60808 {
60809 { 0, 0, 0, 0 },
60810 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
60811 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0b10000 }
60812 },
60813/* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
60814 {
60815 { 0, 0, 0, 0 },
60816 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60817 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa0310000 }
60818 },
60819/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60820 {
60821 { 0, 0, 0, 0 },
60822 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60823 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2310000 }
60824 },
60825/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
60826 {
60827 { 0, 0, 0, 0 },
60828 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60829 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2b10000 }
60830 },
60831/* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
60832 {
60833 { 0, 0, 0, 0 },
60834 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60835 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2f10000 }
60836 },
60837/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60838 {
60839 { 0, 0, 0, 0 },
60840 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60841 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4310000 }
60842 },
60843/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
60844 {
60845 { 0, 0, 0, 0 },
60846 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60847 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4b10000 }
60848 },
60849/* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
60850 {
60851 { 0, 0, 0, 0 },
60852 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60853 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4f10000 }
60854 },
60855/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
60856 {
60857 { 0, 0, 0, 0 },
60858 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
60859 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6f10000 }
60860 },
60861/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60862 {
60863 { 0, 0, 0, 0 },
60864 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60865 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6310000 }
60866 },
60867/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
60868 {
60869 { 0, 0, 0, 0 },
60870 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
60871 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6b10000 }
60872 },
60873/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
60874 {
60875 { 0, 0, 0, 0 },
60876 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
60877 & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893e00 }
60878 },
60879/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
60880 {
60881 { 0, 0, 0, 0 },
60882 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
60883 & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181be00 }
60884 },
60885/* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
60886 {
60887 { 0, 0, 0, 0 },
60888 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
60889 & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813e00 }
60890 },
60891/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
60892 {
60893 { 0, 0, 0, 0 },
60894 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
60895 & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833e00 }
60896 },
60897/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
60898 {
60899 { 0, 0, 0, 0 },
60900 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60901 & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183be00 }
60902 },
60903/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
60904 {
60905 { 0, 0, 0, 0 },
60906 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60907 & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183fe00 }
60908 },
60909/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
60910 {
60911 { 0, 0, 0, 0 },
60912 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
60913 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853e00 }
60914 },
60915/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
60916 {
60917 { 0, 0, 0, 0 },
60918 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60919 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185be00 }
60920 },
60921/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
60922 {
60923 { 0, 0, 0, 0 },
60924 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
60925 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185fe00 }
60926 },
60927/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
60928 {
60929 { 0, 0, 0, 0 },
60930 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), 0 } },
60931 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187fe00 }
60932 },
60933/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
60934 {
60935 { 0, 0, 0, 0 },
60936 { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
60937 & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873e00 }
60938 },
60939/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
60940 {
60941 { 0, 0, 0, 0 },
60942 { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), 0 } },
60943 & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187be00 }
60944 },
60945/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
60946 {
60947 { 0, 0, 0, 0 },
60948 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
60949 & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883e00 }
60950 },
60951/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
60952 {
60953 { 0, 0, 0, 0 },
60954 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
60955 & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180be00 }
60956 },
60957/* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
60958 {
60959 { 0, 0, 0, 0 },
60960 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
60961 & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803e00 }
60962 },
60963/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
60964 {
60965 { 0, 0, 0, 0 },
60966 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
60967 & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823e00 }
60968 },
60969/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
60970 {
60971 { 0, 0, 0, 0 },
60972 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60973 & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182be00 }
60974 },
60975/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
60976 {
60977 { 0, 0, 0, 0 },
60978 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60979 & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182fe00 }
60980 },
60981/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
60982 {
60983 { 0, 0, 0, 0 },
60984 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
60985 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843e00 }
60986 },
60987/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
60988 {
60989 { 0, 0, 0, 0 },
60990 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60991 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184be00 }
60992 },
60993/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
60994 {
60995 { 0, 0, 0, 0 },
60996 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
60997 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184fe00 }
60998 },
60999/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
61000 {
61001 { 0, 0, 0, 0 },
61002 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), 0 } },
61003 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186fe00 }
61004 },
61005/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
61006 {
61007 { 0, 0, 0, 0 },
61008 { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
61009 & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863e00 }
61010 },
61011/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
61012 {
61013 { 0, 0, 0, 0 },
61014 { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), 0 } },
61015 & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186be00 }
61016 },
61017/* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
61018 {
61019 { 0, 0, 0, 0 },
61020 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
61021 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d828 }
61022 },
61023/* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
61024 {
61025 { 0, 0, 0, 0 },
61026 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
61027 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a8 }
61028 },
61029/* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
61030 {
61031 { 0, 0, 0, 0 },
61032 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
61033 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d028 }
61034 },
61035/* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
61036 {
61037 { 0, 0, 0, 0 },
61038 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61039 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22800 }
61040 },
61041/* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
61042 {
61043 { 0, 0, 0, 0 },
61044 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61045 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42800 }
61046 },
61047/* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
61048 {
61049 { 0, 0, 0, 0 },
61050 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61051 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62800 }
61052 },
61053/* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
61054 {
61055 { 0, 0, 0, 0 },
61056 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
61057 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a800 }
61058 },
61059/* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
61060 {
61061 { 0, 0, 0, 0 },
61062 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
61063 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a800 }
61064 },
61065/* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
61066 {
61067 { 0, 0, 0, 0 },
61068 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
61069 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e800 }
61070 },
61071/* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
61072 {
61073 { 0, 0, 0, 0 },
61074 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
61075 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e800 }
61076 },
61077/* bxor${X} ${BitBase32-24-u19-Prefixed} */
61078 {
61079 { 0, 0, 0, 0 },
61080 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
61081 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e800 }
61082 },
61083/* bxor${X} ${BitBase32-24-u27-Prefixed} */
61084 {
61085 { 0, 0, 0, 0 },
61086 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
61087 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a800 }
61088 },
61089/* bxor${X} $Bitno16R,$Bit16Rn */
61090 {
61091 { 0, 0, 0, 0 },
61092 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61093 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ec000 }
61094 },
61095/* bxor${X} $Bitno16R,$Bit16An */
61096 {
61097 { 0, 0, 0, 0 },
61098 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61099 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ec400 }
61100 },
61101/* bxor${X} [$Bit16An] */
61102 {
61103 { 0, 0, 0, 0 },
61104 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61105 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ec6 }
61106 },
61107/* bxor${X} ${Dsp-16-u8}[$Bit16An] */
61108 {
61109 { 0, 0, 0, 0 },
61110 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61111 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ec800 }
61112 },
61113/* bxor${X} ${Dsp-16-u16}[$Bit16An] */
61114 {
61115 { 0, 0, 0, 0 },
61116 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61117 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ecc0000 }
61118 },
61119/* bxor${X} ${BitBase16-16-u8}[sb] */
61120 {
61121 { 0, 0, 0, 0 },
61122 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61123 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eca00 }
61124 },
61125/* bxor${X} ${BitBase16-16-u16}[sb] */
61126 {
61127 { 0, 0, 0, 0 },
61128 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61129 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ece0000 }
61130 },
61131/* bxor${X} ${BitBase16-16-s8}[fb] */
61132 {
61133 { 0, 0, 0, 0 },
61134 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61135 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ecb00 }
61136 },
61137/* bxor${X} ${BitBase16-16-u16} */
61138 {
61139 { 0, 0, 0, 0 },
61140 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61141 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ecf0000 }
61142 },
61143/* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61144 {
61145 { 0, 0, 0, 0 },
61146 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61147 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd828 }
61148 },
61149/* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61150 {
61151 { 0, 0, 0, 0 },
61152 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61153 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a8 }
61154 },
61155/* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61156 {
61157 { 0, 0, 0, 0 },
61158 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61159 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd028 }
61160 },
61161/* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61162 {
61163 { 0, 0, 0, 0 },
61164 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61165 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22800 }
61166 },
61167/* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61168 {
61169 { 0, 0, 0, 0 },
61170 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61171 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4280000 }
61172 },
61173/* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61174 {
61175 { 0, 0, 0, 0 },
61176 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61177 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6280000 }
61178 },
61179/* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61180 {
61181 { 0, 0, 0, 0 },
61182 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61183 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a800 }
61184 },
61185/* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61186 {
61187 { 0, 0, 0, 0 },
61188 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61189 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a80000 }
61190 },
61191/* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61192 {
61193 { 0, 0, 0, 0 },
61194 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61195 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e800 }
61196 },
61197/* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61198 {
61199 { 0, 0, 0, 0 },
61200 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61201 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e80000 }
61202 },
61203/* btsts${X} ${BitBase32-16-u19-Unprefixed} */
61204 {
61205 { 0, 0, 0, 0 },
61206 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61207 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e80000 }
61208 },
61209/* btsts${X} ${BitBase32-16-u27-Unprefixed} */
61210 {
61211 { 0, 0, 0, 0 },
61212 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61213 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a80000 }
61214 },
61215/* btsts${X} $Bitno16R,$Bit16Rn */
61216 {
61217 { 0, 0, 0, 0 },
61218 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61219 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e1000 }
61220 },
61221/* btsts${X} $Bitno16R,$Bit16An */
61222 {
61223 { 0, 0, 0, 0 },
61224 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61225 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e1400 }
61226 },
61227/* btsts${X} [$Bit16An] */
61228 {
61229 { 0, 0, 0, 0 },
61230 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61231 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e16 }
61232 },
61233/* btsts${X} ${Dsp-16-u8}[$Bit16An] */
61234 {
61235 { 0, 0, 0, 0 },
61236 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61237 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e1800 }
61238 },
61239/* btsts${X} ${Dsp-16-u16}[$Bit16An] */
61240 {
61241 { 0, 0, 0, 0 },
61242 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61243 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e1c0000 }
61244 },
61245/* btsts${X} ${BitBase16-16-u8}[sb] */
61246 {
61247 { 0, 0, 0, 0 },
61248 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61249 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e1a00 }
61250 },
61251/* btsts${X} ${BitBase16-16-u16}[sb] */
61252 {
61253 { 0, 0, 0, 0 },
61254 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61255 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e1e0000 }
61256 },
61257/* btsts${X} ${BitBase16-16-s8}[fb] */
61258 {
61259 { 0, 0, 0, 0 },
61260 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61261 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e1b00 }
61262 },
61263/* btsts${X} ${BitBase16-16-u16} */
61264 {
61265 { 0, 0, 0, 0 },
61266 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61267 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e1f0000 }
61268 },
61269/* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61270 {
61271 { 0, 0, 0, 0 },
61272 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61273 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd820 }
61274 },
61275/* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61276 {
61277 { 0, 0, 0, 0 },
61278 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61279 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a0 }
61280 },
61281/* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61282 {
61283 { 0, 0, 0, 0 },
61284 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61285 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd020 }
61286 },
61287/* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61288 {
61289 { 0, 0, 0, 0 },
61290 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61291 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22000 }
61292 },
61293/* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61294 {
61295 { 0, 0, 0, 0 },
61296 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61297 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4200000 }
61298 },
61299/* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61300 {
61301 { 0, 0, 0, 0 },
61302 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61303 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6200000 }
61304 },
61305/* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61306 {
61307 { 0, 0, 0, 0 },
61308 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61309 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a000 }
61310 },
61311/* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61312 {
61313 { 0, 0, 0, 0 },
61314 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61315 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a00000 }
61316 },
61317/* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61318 {
61319 { 0, 0, 0, 0 },
61320 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61321 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e000 }
61322 },
61323/* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61324 {
61325 { 0, 0, 0, 0 },
61326 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61327 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e00000 }
61328 },
61329/* btstc${X} ${BitBase32-16-u19-Unprefixed} */
61330 {
61331 { 0, 0, 0, 0 },
61332 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61333 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e00000 }
61334 },
61335/* btstc${X} ${BitBase32-16-u27-Unprefixed} */
61336 {
61337 { 0, 0, 0, 0 },
61338 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61339 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a00000 }
61340 },
61341/* btstc${X} $Bitno16R,$Bit16Rn */
61342 {
61343 { 0, 0, 0, 0 },
61344 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61345 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e0000 }
61346 },
61347/* btstc${X} $Bitno16R,$Bit16An */
61348 {
61349 { 0, 0, 0, 0 },
61350 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61351 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e0400 }
61352 },
61353/* btstc${X} [$Bit16An] */
61354 {
61355 { 0, 0, 0, 0 },
61356 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61357 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e06 }
61358 },
61359/* btstc${X} ${Dsp-16-u8}[$Bit16An] */
61360 {
61361 { 0, 0, 0, 0 },
61362 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61363 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e0800 }
61364 },
61365/* btstc${X} ${Dsp-16-u16}[$Bit16An] */
61366 {
61367 { 0, 0, 0, 0 },
61368 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61369 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e0c0000 }
61370 },
61371/* btstc${X} ${BitBase16-16-u8}[sb] */
61372 {
61373 { 0, 0, 0, 0 },
61374 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61375 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e0a00 }
61376 },
61377/* btstc${X} ${BitBase16-16-u16}[sb] */
61378 {
61379 { 0, 0, 0, 0 },
61380 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61381 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e0e0000 }
61382 },
61383/* btstc${X} ${BitBase16-16-s8}[fb] */
61384 {
61385 { 0, 0, 0, 0 },
61386 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61387 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e0b00 }
61388 },
61389/* btstc${X} ${BitBase16-16-u16} */
61390 {
61391 { 0, 0, 0, 0 },
61392 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61393 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e0f0000 }
61394 },
61395/* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61396 {
61397 { 0, 0, 0, 0 },
61398 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61399 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd800 }
61400 },
61401/* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61402 {
61403 { 0, 0, 0, 0 },
61404 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61405 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd080 }
61406 },
61407/* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61408 {
61409 { 0, 0, 0, 0 },
61410 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61411 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd000 }
61412 },
61413/* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61414 {
61415 { 0, 0, 0, 0 },
61416 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61417 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd20000 }
61418 },
61419/* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61420 {
61421 { 0, 0, 0, 0 },
61422 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61423 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4000000 }
61424 },
61425/* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61426 {
61427 { 0, 0, 0, 0 },
61428 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61429 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6000000 }
61430 },
61431/* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61432 {
61433 { 0, 0, 0, 0 },
61434 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61435 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd28000 }
61436 },
61437/* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61438 {
61439 { 0, 0, 0, 0 },
61440 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61441 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4800000 }
61442 },
61443/* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61444 {
61445 { 0, 0, 0, 0 },
61446 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61447 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2c000 }
61448 },
61449/* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61450 {
61451 { 0, 0, 0, 0 },
61452 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61453 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4c00000 }
61454 },
61455/* btst${X} ${BitBase32-16-u19-Unprefixed} */
61456 {
61457 { 0, 0, 0, 0 },
61458 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61459 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6c00000 }
61460 },
61461/* btst${X} ${BitBase32-16-u27-Unprefixed} */
61462 {
61463 { 0, 0, 0, 0 },
61464 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61465 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6800000 }
61466 },
61467/* btst${G} $Bitno16R,$Bit16Rn */
61468 {
61469 { 0, 0, 0, 0 },
61470 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61471 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7eb000 }
61472 },
61473/* btst${G} $Bitno16R,$Bit16An */
61474 {
61475 { 0, 0, 0, 0 },
61476 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61477 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7eb400 }
61478 },
61479/* btst${G} ${Dsp-16-u8}[$Bit16An] */
61480 {
61481 { 0, 0, 0, 0 },
61482 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61483 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7eb800 }
61484 },
61485/* btst${G} ${BitBase16-16-u8}[sb] */
61486 {
61487 { 0, 0, 0, 0 },
61488 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61489 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eba00 }
61490 },
61491/* btst${G} ${BitBase16-16-s8}[fb] */
61492 {
61493 { 0, 0, 0, 0 },
61494 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61495 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ebb00 }
61496 },
61497/* btst${S} ${BitBase16-8-u11-S}[sb] */
61498 {
61499 { 0, 0, 0, 0 },
61500 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
61501 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5800 }
61502 },
61503/* btst${G} ${Dsp-16-u16}[$Bit16An] */
61504 {
61505 { 0, 0, 0, 0 },
61506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61507 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ebc0000 }
61508 },
61509/* btst${G} ${BitBase16-16-u16}[sb] */
61510 {
61511 { 0, 0, 0, 0 },
61512 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61513 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ebe0000 }
61514 },
61515/* btst${G} ${BitBase16-16-u16} */
61516 {
61517 { 0, 0, 0, 0 },
61518 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
61519 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ebf0000 }
61520 },
61521/* btst${G} [$Bit16An] */
61522 {
61523 { 0, 0, 0, 0 },
61524 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
61525 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7eb6 }
61526 },
61527/* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61528 {
61529 { 0, 0, 0, 0 },
61530 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61531 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd838 }
61532 },
61533/* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61534 {
61535 { 0, 0, 0, 0 },
61536 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61537 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b8 }
61538 },
61539/* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61540 {
61541 { 0, 0, 0, 0 },
61542 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61543 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd038 }
61544 },
61545/* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61546 {
61547 { 0, 0, 0, 0 },
61548 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61549 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23800 }
61550 },
61551/* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61552 {
61553 { 0, 0, 0, 0 },
61554 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61555 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4380000 }
61556 },
61557/* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61558 {
61559 { 0, 0, 0, 0 },
61560 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61561 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6380000 }
61562 },
61563/* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61564 {
61565 { 0, 0, 0, 0 },
61566 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61567 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b800 }
61568 },
61569/* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61570 {
61571 { 0, 0, 0, 0 },
61572 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61573 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b80000 }
61574 },
61575/* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61576 {
61577 { 0, 0, 0, 0 },
61578 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61579 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f800 }
61580 },
61581/* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61582 {
61583 { 0, 0, 0, 0 },
61584 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61585 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f80000 }
61586 },
61587/* bset${X} ${BitBase32-16-u19-Unprefixed} */
61588 {
61589 { 0, 0, 0, 0 },
61590 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61591 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f80000 }
61592 },
61593/* bset${X} ${BitBase32-16-u27-Unprefixed} */
61594 {
61595 { 0, 0, 0, 0 },
61596 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61597 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b80000 }
61598 },
61599/* bset${G} $Bitno16R,$Bit16Rn */
61600 {
61601 { 0, 0, 0, 0 },
61602 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61603 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e9000 }
61604 },
61605/* bset${G} $Bitno16R,$Bit16An */
61606 {
61607 { 0, 0, 0, 0 },
61608 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61609 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e9400 }
61610 },
61611/* bset${G} ${Dsp-16-u8}[$Bit16An] */
61612 {
61613 { 0, 0, 0, 0 },
61614 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61615 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e9800 }
61616 },
61617/* bset${G} ${BitBase16-16-u8}[sb] */
61618 {
61619 { 0, 0, 0, 0 },
61620 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61621 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e9a00 }
61622 },
61623/* bset${G} ${BitBase16-16-s8}[fb] */
61624 {
61625 { 0, 0, 0, 0 },
61626 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61627 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e9b00 }
61628 },
61629/* bset${S} ${BitBase16-8-u11-S}[sb] */
61630 {
61631 { 0, 0, 0, 0 },
61632 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
61633 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4800 }
61634 },
61635/* bset${G} ${Dsp-16-u16}[$Bit16An] */
61636 {
61637 { 0, 0, 0, 0 },
61638 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61639 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e9c0000 }
61640 },
61641/* bset${G} ${BitBase16-16-u16}[sb] */
61642 {
61643 { 0, 0, 0, 0 },
61644 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61645 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e9e0000 }
61646 },
61647/* bset${G} ${BitBase16-16-u16} */
61648 {
61649 { 0, 0, 0, 0 },
61650 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
61651 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e9f0000 }
61652 },
61653/* bset${G} [$Bit16An] */
61654 {
61655 { 0, 0, 0, 0 },
61656 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
61657 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e96 }
61658 },
61659/* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
61660 {
61661 { 0, 0, 0, 0 },
61662 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
61663 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d820 }
61664 },
61665/* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
61666 {
61667 { 0, 0, 0, 0 },
61668 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
61669 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a0 }
61670 },
61671/* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
61672 {
61673 { 0, 0, 0, 0 },
61674 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
61675 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d020 }
61676 },
61677/* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
61678 {
61679 { 0, 0, 0, 0 },
61680 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61681 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22000 }
61682 },
61683/* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
61684 {
61685 { 0, 0, 0, 0 },
61686 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61687 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42000 }
61688 },
61689/* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
61690 {
61691 { 0, 0, 0, 0 },
61692 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61693 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62000 }
61694 },
61695/* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
61696 {
61697 { 0, 0, 0, 0 },
61698 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
61699 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a000 }
61700 },
61701/* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
61702 {
61703 { 0, 0, 0, 0 },
61704 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
61705 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a000 }
61706 },
61707/* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
61708 {
61709 { 0, 0, 0, 0 },
61710 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
61711 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e000 }
61712 },
61713/* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
61714 {
61715 { 0, 0, 0, 0 },
61716 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
61717 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e000 }
61718 },
61719/* bor${X} ${BitBase32-24-u19-Prefixed} */
61720 {
61721 { 0, 0, 0, 0 },
61722 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
61723 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e000 }
61724 },
61725/* bor${X} ${BitBase32-24-u27-Prefixed} */
61726 {
61727 { 0, 0, 0, 0 },
61728 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
61729 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a000 }
61730 },
61731/* bor${X} $Bitno16R,$Bit16Rn */
61732 {
61733 { 0, 0, 0, 0 },
61734 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61735 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e6000 }
61736 },
61737/* bor${X} $Bitno16R,$Bit16An */
61738 {
61739 { 0, 0, 0, 0 },
61740 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61741 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e6400 }
61742 },
61743/* bor${X} [$Bit16An] */
61744 {
61745 { 0, 0, 0, 0 },
61746 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61747 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e66 }
61748 },
61749/* bor${X} ${Dsp-16-u8}[$Bit16An] */
61750 {
61751 { 0, 0, 0, 0 },
61752 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61753 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e6800 }
61754 },
61755/* bor${X} ${Dsp-16-u16}[$Bit16An] */
61756 {
61757 { 0, 0, 0, 0 },
61758 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61759 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e6c0000 }
61760 },
61761/* bor${X} ${BitBase16-16-u8}[sb] */
61762 {
61763 { 0, 0, 0, 0 },
61764 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61765 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e6a00 }
61766 },
61767/* bor${X} ${BitBase16-16-u16}[sb] */
61768 {
61769 { 0, 0, 0, 0 },
61770 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61771 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e6e0000 }
61772 },
61773/* bor${X} ${BitBase16-16-s8}[fb] */
61774 {
61775 { 0, 0, 0, 0 },
61776 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61777 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e6b00 }
61778 },
61779/* bor${X} ${BitBase16-16-u16} */
61780 {
61781 { 0, 0, 0, 0 },
61782 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61783 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e6f0000 }
61784 },
61785/* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
61786 {
61787 { 0, 0, 0, 0 },
61788 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
61789 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d838 }
61790 },
61791/* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
61792 {
61793 { 0, 0, 0, 0 },
61794 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
61795 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b8 }
61796 },
61797/* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
61798 {
61799 { 0, 0, 0, 0 },
61800 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
61801 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d038 }
61802 },
61803/* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
61804 {
61805 { 0, 0, 0, 0 },
61806 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61807 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23800 }
61808 },
61809/* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
61810 {
61811 { 0, 0, 0, 0 },
61812 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61813 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43800 }
61814 },
61815/* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
61816 {
61817 { 0, 0, 0, 0 },
61818 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61819 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63800 }
61820 },
61821/* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
61822 {
61823 { 0, 0, 0, 0 },
61824 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
61825 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b800 }
61826 },
61827/* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
61828 {
61829 { 0, 0, 0, 0 },
61830 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
61831 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b800 }
61832 },
61833/* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
61834 {
61835 { 0, 0, 0, 0 },
61836 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
61837 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f800 }
61838 },
61839/* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
61840 {
61841 { 0, 0, 0, 0 },
61842 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
61843 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f800 }
61844 },
61845/* bnxor${X} ${BitBase32-24-u19-Prefixed} */
61846 {
61847 { 0, 0, 0, 0 },
61848 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
61849 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f800 }
61850 },
61851/* bnxor${X} ${BitBase32-24-u27-Prefixed} */
61852 {
61853 { 0, 0, 0, 0 },
61854 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
61855 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b800 }
61856 },
61857/* bnxor${X} $Bitno16R,$Bit16Rn */
61858 {
61859 { 0, 0, 0, 0 },
61860 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61861 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ed000 }
61862 },
61863/* bnxor${X} $Bitno16R,$Bit16An */
61864 {
61865 { 0, 0, 0, 0 },
61866 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61867 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ed400 }
61868 },
61869/* bnxor${X} [$Bit16An] */
61870 {
61871 { 0, 0, 0, 0 },
61872 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61873 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ed6 }
61874 },
61875/* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
61876 {
61877 { 0, 0, 0, 0 },
61878 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61879 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ed800 }
61880 },
61881/* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
61882 {
61883 { 0, 0, 0, 0 },
61884 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61885 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7edc0000 }
61886 },
61887/* bnxor${X} ${BitBase16-16-u8}[sb] */
61888 {
61889 { 0, 0, 0, 0 },
61890 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61891 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eda00 }
61892 },
61893/* bnxor${X} ${BitBase16-16-u16}[sb] */
61894 {
61895 { 0, 0, 0, 0 },
61896 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61897 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ede0000 }
61898 },
61899/* bnxor${X} ${BitBase16-16-s8}[fb] */
61900 {
61901 { 0, 0, 0, 0 },
61902 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61903 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7edb00 }
61904 },
61905/* bnxor${X} ${BitBase16-16-u16} */
61906 {
61907 { 0, 0, 0, 0 },
61908 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61909 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7edf0000 }
61910 },
61911/* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
61912 {
61913 { 0, 0, 0, 0 },
61914 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
61915 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d800 }
61916 },
61917/* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
61918 {
61919 { 0, 0, 0, 0 },
61920 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
61921 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d080 }
61922 },
61923/* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
61924 {
61925 { 0, 0, 0, 0 },
61926 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
61927 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d000 }
61928 },
61929/* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
61930 {
61931 { 0, 0, 0, 0 },
61932 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61933 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20000 }
61934 },
61935/* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
61936 {
61937 { 0, 0, 0, 0 },
61938 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61939 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40000 }
61940 },
61941/* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
61942 {
61943 { 0, 0, 0, 0 },
61944 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61945 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60000 }
61946 },
61947/* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
61948 {
61949 { 0, 0, 0, 0 },
61950 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
61951 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28000 }
61952 },
61953/* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
61954 {
61955 { 0, 0, 0, 0 },
61956 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
61957 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48000 }
61958 },
61959/* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
61960 {
61961 { 0, 0, 0, 0 },
61962 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
61963 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c000 }
61964 },
61965/* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
61966 {
61967 { 0, 0, 0, 0 },
61968 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
61969 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c000 }
61970 },
61971/* bntst${X} ${BitBase32-24-u19-Prefixed} */
61972 {
61973 { 0, 0, 0, 0 },
61974 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
61975 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c000 }
61976 },
61977/* bntst${X} ${BitBase32-24-u27-Prefixed} */
61978 {
61979 { 0, 0, 0, 0 },
61980 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
61981 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68000 }
61982 },
61983/* bntst${X} $Bitno16R,$Bit16Rn */
61984 {
61985 { 0, 0, 0, 0 },
61986 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61987 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e3000 }
61988 },
61989/* bntst${X} $Bitno16R,$Bit16An */
61990 {
61991 { 0, 0, 0, 0 },
61992 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61993 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e3400 }
61994 },
61995/* bntst${X} [$Bit16An] */
61996 {
61997 { 0, 0, 0, 0 },
61998 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61999 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e36 }
62000 },
62001/* bntst${X} ${Dsp-16-u8}[$Bit16An] */
62002 {
62003 { 0, 0, 0, 0 },
62004 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62005 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e3800 }
62006 },
62007/* bntst${X} ${Dsp-16-u16}[$Bit16An] */
62008 {
62009 { 0, 0, 0, 0 },
62010 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62011 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e3c0000 }
62012 },
62013/* bntst${X} ${BitBase16-16-u8}[sb] */
62014 {
62015 { 0, 0, 0, 0 },
62016 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62017 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e3a00 }
62018 },
62019/* bntst${X} ${BitBase16-16-u16}[sb] */
62020 {
62021 { 0, 0, 0, 0 },
62022 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62023 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e3e0000 }
62024 },
62025/* bntst${X} ${BitBase16-16-s8}[fb] */
62026 {
62027 { 0, 0, 0, 0 },
62028 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62029 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e3b00 }
62030 },
62031/* bntst${X} ${BitBase16-16-u16} */
62032 {
62033 { 0, 0, 0, 0 },
62034 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62035 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e3f0000 }
62036 },
62037/* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
62038 {
62039 { 0, 0, 0, 0 },
62040 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
62041 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd818 }
62042 },
62043/* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
62044 {
62045 { 0, 0, 0, 0 },
62046 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
62047 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd098 }
62048 },
62049/* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
62050 {
62051 { 0, 0, 0, 0 },
62052 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62053 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd018 }
62054 },
62055/* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
62056 {
62057 { 0, 0, 0, 0 },
62058 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62059 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd21800 }
62060 },
62061/* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
62062 {
62063 { 0, 0, 0, 0 },
62064 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62065 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4180000 }
62066 },
62067/* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
62068 {
62069 { 0, 0, 0, 0 },
62070 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62071 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6180000 }
62072 },
62073/* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
62074 {
62075 { 0, 0, 0, 0 },
62076 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62077 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd29800 }
62078 },
62079/* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
62080 {
62081 { 0, 0, 0, 0 },
62082 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62083 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4980000 }
62084 },
62085/* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
62086 {
62087 { 0, 0, 0, 0 },
62088 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62089 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2d800 }
62090 },
62091/* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
62092 {
62093 { 0, 0, 0, 0 },
62094 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62095 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4d80000 }
62096 },
62097/* bnot${X} ${BitBase32-16-u19-Unprefixed} */
62098 {
62099 { 0, 0, 0, 0 },
62100 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
62101 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6d80000 }
62102 },
62103/* bnot${X} ${BitBase32-16-u27-Unprefixed} */
62104 {
62105 { 0, 0, 0, 0 },
62106 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
62107 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6980000 }
62108 },
62109/* bnot${G} $Bitno16R,$Bit16Rn */
62110 {
62111 { 0, 0, 0, 0 },
62112 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62113 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ea000 }
62114 },
62115/* bnot${G} $Bitno16R,$Bit16An */
62116 {
62117 { 0, 0, 0, 0 },
62118 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62119 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ea400 }
62120 },
62121/* bnot${G} ${Dsp-16-u8}[$Bit16An] */
62122 {
62123 { 0, 0, 0, 0 },
62124 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62125 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ea800 }
62126 },
62127/* bnot${G} ${BitBase16-16-u8}[sb] */
62128 {
62129 { 0, 0, 0, 0 },
62130 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62131 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eaa00 }
62132 },
62133/* bnot${G} ${BitBase16-16-s8}[fb] */
62134 {
62135 { 0, 0, 0, 0 },
62136 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62137 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7eab00 }
62138 },
62139/* bnot${S} ${BitBase16-8-u11-S}[sb] */
62140 {
62141 { 0, 0, 0, 0 },
62142 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
62143 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5000 }
62144 },
62145/* bnot${G} ${Dsp-16-u16}[$Bit16An] */
62146 {
62147 { 0, 0, 0, 0 },
62148 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62149 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7eac0000 }
62150 },
62151/* bnot${G} ${BitBase16-16-u16}[sb] */
62152 {
62153 { 0, 0, 0, 0 },
62154 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62155 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7eae0000 }
62156 },
62157/* bnot${G} ${BitBase16-16-u16} */
62158 {
62159 { 0, 0, 0, 0 },
62160 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
62161 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7eaf0000 }
62162 },
62163/* bnot${G} [$Bit16An] */
62164 {
62165 { 0, 0, 0, 0 },
62166 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
62167 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ea6 }
62168 },
62169/* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62170 {
62171 { 0, 0, 0, 0 },
62172 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62173 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d830 }
62174 },
62175/* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62176 {
62177 { 0, 0, 0, 0 },
62178 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62179 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b0 }
62180 },
62181/* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62182 {
62183 { 0, 0, 0, 0 },
62184 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62185 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d030 }
62186 },
62187/* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62188 {
62189 { 0, 0, 0, 0 },
62190 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62191 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23000 }
62192 },
62193/* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62194 {
62195 { 0, 0, 0, 0 },
62196 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62197 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43000 }
62198 },
62199/* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62200 {
62201 { 0, 0, 0, 0 },
62202 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62203 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63000 }
62204 },
62205/* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
62206 {
62207 { 0, 0, 0, 0 },
62208 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62209 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b000 }
62210 },
62211/* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
62212 {
62213 { 0, 0, 0, 0 },
62214 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62215 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b000 }
62216 },
62217/* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
62218 {
62219 { 0, 0, 0, 0 },
62220 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62221 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f000 }
62222 },
62223/* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
62224 {
62225 { 0, 0, 0, 0 },
62226 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62227 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f000 }
62228 },
62229/* bnor${X} ${BitBase32-24-u19-Prefixed} */
62230 {
62231 { 0, 0, 0, 0 },
62232 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62233 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f000 }
62234 },
62235/* bnor${X} ${BitBase32-24-u27-Prefixed} */
62236 {
62237 { 0, 0, 0, 0 },
62238 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62239 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b000 }
62240 },
62241/* bnor${X} $Bitno16R,$Bit16Rn */
62242 {
62243 { 0, 0, 0, 0 },
62244 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62245 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e7000 }
62246 },
62247/* bnor${X} $Bitno16R,$Bit16An */
62248 {
62249 { 0, 0, 0, 0 },
62250 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62251 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e7400 }
62252 },
62253/* bnor${X} [$Bit16An] */
62254 {
62255 { 0, 0, 0, 0 },
62256 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62257 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e76 }
62258 },
62259/* bnor${X} ${Dsp-16-u8}[$Bit16An] */
62260 {
62261 { 0, 0, 0, 0 },
62262 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62263 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e7800 }
62264 },
62265/* bnor${X} ${Dsp-16-u16}[$Bit16An] */
62266 {
62267 { 0, 0, 0, 0 },
62268 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62269 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e7c0000 }
62270 },
62271/* bnor${X} ${BitBase16-16-u8}[sb] */
62272 {
62273 { 0, 0, 0, 0 },
62274 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62275 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e7a00 }
62276 },
62277/* bnor${X} ${BitBase16-16-u16}[sb] */
62278 {
62279 { 0, 0, 0, 0 },
62280 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62281 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e7e0000 }
62282 },
62283/* bnor${X} ${BitBase16-16-s8}[fb] */
62284 {
62285 { 0, 0, 0, 0 },
62286 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62287 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e7b00 }
62288 },
62289/* bnor${X} ${BitBase16-16-u16} */
62290 {
62291 { 0, 0, 0, 0 },
62292 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62293 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e7f0000 }
62294 },
62295/* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62296 {
62297 { 0, 0, 0, 0 },
62298 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62299 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d818 }
62300 },
62301/* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62302 {
62303 { 0, 0, 0, 0 },
62304 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62305 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d098 }
62306 },
62307/* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62308 {
62309 { 0, 0, 0, 0 },
62310 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62311 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d018 }
62312 },
62313/* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62314 {
62315 { 0, 0, 0, 0 },
62316 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62317 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d21800 }
62318 },
62319/* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62320 {
62321 { 0, 0, 0, 0 },
62322 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62323 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d41800 }
62324 },
62325/* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62326 {
62327 { 0, 0, 0, 0 },
62328 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62329 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d61800 }
62330 },
62331/* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
62332 {
62333 { 0, 0, 0, 0 },
62334 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62335 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d29800 }
62336 },
62337/* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
62338 {
62339 { 0, 0, 0, 0 },
62340 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62341 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d49800 }
62342 },
62343/* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
62344 {
62345 { 0, 0, 0, 0 },
62346 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62347 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2d800 }
62348 },
62349/* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
62350 {
62351 { 0, 0, 0, 0 },
62352 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62353 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4d800 }
62354 },
62355/* bnand${X} ${BitBase32-24-u19-Prefixed} */
62356 {
62357 { 0, 0, 0, 0 },
62358 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62359 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6d800 }
62360 },
62361/* bnand${X} ${BitBase32-24-u27-Prefixed} */
62362 {
62363 { 0, 0, 0, 0 },
62364 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62365 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d69800 }
62366 },
62367/* bnand${X} $Bitno16R,$Bit16Rn */
62368 {
62369 { 0, 0, 0, 0 },
62370 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62371 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e5000 }
62372 },
62373/* bnand${X} $Bitno16R,$Bit16An */
62374 {
62375 { 0, 0, 0, 0 },
62376 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62377 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e5400 }
62378 },
62379/* bnand${X} [$Bit16An] */
62380 {
62381 { 0, 0, 0, 0 },
62382 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62383 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e56 }
62384 },
62385/* bnand${X} ${Dsp-16-u8}[$Bit16An] */
62386 {
62387 { 0, 0, 0, 0 },
62388 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62389 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e5800 }
62390 },
62391/* bnand${X} ${Dsp-16-u16}[$Bit16An] */
62392 {
62393 { 0, 0, 0, 0 },
62394 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62395 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e5c0000 }
62396 },
62397/* bnand${X} ${BitBase16-16-u8}[sb] */
62398 {
62399 { 0, 0, 0, 0 },
62400 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62401 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e5a00 }
62402 },
62403/* bnand${X} ${BitBase16-16-u16}[sb] */
62404 {
62405 { 0, 0, 0, 0 },
62406 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62407 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e5e0000 }
62408 },
62409/* bnand${X} ${BitBase16-16-s8}[fb] */
62410 {
62411 { 0, 0, 0, 0 },
62412 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62413 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e5b00 }
62414 },
62415/* bnand${X} ${BitBase16-16-u16} */
62416 {
62417 { 0, 0, 0, 0 },
62418 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62419 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e5f0000 }
62420 },
62421/* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
62422 {
62423 { 0, 0, 0, 0 },
62424 { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
62425 & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed, { 0xd81000 }
62426 },
62427/* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
62428 {
62429 { 0, 0, 0, 0 },
62430 { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
62431 & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed, { 0xd09000 }
62432 },
62433/* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
62434 {
62435 { 0, 0, 0, 0 },
62436 { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62437 & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed, { 0xd01000 }
62438 },
62439/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
62440 {
62441 { 0, 0, 0, 0 },
62442 { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62443 & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed, { 0xd2100000 }
62444 },
62445/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
62446 {
62447 { 0, 0, 0, 0 },
62448 { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62449 & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed, { 0xd2900000 }
62450 },
62451/* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
62452 {
62453 { 0, 0, 0, 0 },
62454 { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62455 & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed, { 0xd2d00000 }
62456 },
62457/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
62458 {
62459 { 0, 0, 0, 0 },
62460 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62461 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed, { 0xd4100000 }
62462 },
62463/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
62464 {
62465 { 0, 0, 0, 0 },
62466 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62467 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed, { 0xd4900000 }
62468 },
62469/* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
62470 {
62471 { 0, 0, 0, 0 },
62472 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62473 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed, { 0xd4d00000 }
62474 },
62475/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
62476 {
62477 { 0, 0, 0, 0 },
62478 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
62479 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed, { 0xd6d00000 }
62480 },
62481/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
62482 {
62483 { 0, 0, 0, 0 },
62484 { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62485 & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed, { 0xd6100000 }
62486 },
62487/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
62488 {
62489 { 0, 0, 0, 0 },
62490 { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
62491 & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed, { 0xd6900000 }
62492 },
62493/* bm${cond16-24} $Bitno16R,$Bit16Rn */
62494 {
62495 { 0, 0, 0, 0 },
62496 { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62497 & ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct, { 0x7e200000 }
62498 },
62499/* bm${cond16-24} $Bitno16R,$Bit16An */
62500 {
62501 { 0, 0, 0, 0 },
62502 { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62503 & ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct, { 0x7e240000 }
62504 },
62505/* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
62506 {
62507 { 0, 0, 0, 0 },
62508 { { MNEM, OP (COND16_24), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62509 & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative, { 0x7e280000 }
62510 },
62511/* bm${cond16-24} ${BitBase16-16-u8}[sb] */
62512 {
62513 { 0, 0, 0, 0 },
62514 { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62515 & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative, { 0x7e2a0000 }
62516 },
62517/* bm${cond16-24} ${BitBase16-16-s8}[fb] */
62518 {
62519 { 0, 0, 0, 0 },
62520 { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62521 & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative, { 0x7e2b0000 }
62522 },
62523/* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
62524 {
62525 { 0, 0, 0, 0 },
62526 { { MNEM, OP (COND16_32), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62527 & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative, { 0x7e2c0000 }
62528 },
62529/* bm${cond16-32} ${BitBase16-16-u16}[sb] */
62530 {
62531 { 0, 0, 0, 0 },
62532 { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62533 & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative, { 0x7e2e0000 }
62534 },
62535/* bm${cond16-32} ${BitBase16-16-u16} */
62536 {
62537 { 0, 0, 0, 0 },
62538 { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), 0 } },
62539 & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute, { 0x7e2f0000 }
62540 },
62541/* bm${cond16-16} [$Bit16An] */
62542 {
62543 { 0, 0, 0, 0 },
62544 { { MNEM, OP (COND16_16), ' ', '[', OP (BIT16AN), ']', 0 } },
62545 & ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect, { 0x7e2600 }
62546 },
62547/* bitindex.w $Dst32RnUnprefixedHI */
62548 {
62549 { 0, 0, 0, 0 },
62550 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
62551 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc92e }
62552 },
62553/* bitindex.w $Dst32AnUnprefixedHI */
62554 {
62555 { 0, 0, 0, 0 },
62556 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
62557 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1ae }
62558 },
62559/* bitindex.w [$Dst32AnUnprefixed] */
62560 {
62561 { 0, 0, 0, 0 },
62562 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62563 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc12e }
62564 },
62565/* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
62566 {
62567 { 0, 0, 0, 0 },
62568 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62569 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc32e00 }
62570 },
62571/* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
62572 {
62573 { 0, 0, 0, 0 },
62574 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62575 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc52e0000 }
62576 },
62577/* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
62578 {
62579 { 0, 0, 0, 0 },
62580 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62581 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc72e0000 }
62582 },
62583/* bitindex.w ${Dsp-16-u8}[sb] */
62584 {
62585 { 0, 0, 0, 0 },
62586 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
62587 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3ae00 }
62588 },
62589/* bitindex.w ${Dsp-16-u16}[sb] */
62590 {
62591 { 0, 0, 0, 0 },
62592 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
62593 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5ae0000 }
62594 },
62595/* bitindex.w ${Dsp-16-s8}[fb] */
62596 {
62597 { 0, 0, 0, 0 },
62598 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
62599 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ee00 }
62600 },
62601/* bitindex.w ${Dsp-16-s16}[fb] */
62602 {
62603 { 0, 0, 0, 0 },
62604 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
62605 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ee0000 }
62606 },
62607/* bitindex.w ${Dsp-16-u16} */
62608 {
62609 { 0, 0, 0, 0 },
62610 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
62611 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ee0000 }
62612 },
62613/* bitindex.w ${Dsp-16-u24} */
62614 {
62615 { 0, 0, 0, 0 },
62616 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
62617 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7ae0000 }
62618 },
62619/* bitindex.b $Dst32RnUnprefixedQI */
62620 {
62621 { 0, 0, 0, 0 },
62622 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
62623 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc82e }
62624 },
62625/* bitindex.b $Dst32AnUnprefixedQI */
62626 {
62627 { 0, 0, 0, 0 },
62628 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
62629 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0ae }
62630 },
62631/* bitindex.b [$Dst32AnUnprefixed] */
62632 {
62633 { 0, 0, 0, 0 },
62634 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62635 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc02e }
62636 },
62637/* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
62638 {
62639 { 0, 0, 0, 0 },
62640 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62641 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22e00 }
62642 },
62643/* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
62644 {
62645 { 0, 0, 0, 0 },
62646 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62647 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc42e0000 }
62648 },
62649/* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
62650 {
62651 { 0, 0, 0, 0 },
62652 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62653 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc62e0000 }
62654 },
62655/* bitindex.b ${Dsp-16-u8}[sb] */
62656 {
62657 { 0, 0, 0, 0 },
62658 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
62659 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2ae00 }
62660 },
62661/* bitindex.b ${Dsp-16-u16}[sb] */
62662 {
62663 { 0, 0, 0, 0 },
62664 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
62665 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4ae0000 }
62666 },
62667/* bitindex.b ${Dsp-16-s8}[fb] */
62668 {
62669 { 0, 0, 0, 0 },
62670 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
62671 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ee00 }
62672 },
62673/* bitindex.b ${Dsp-16-s16}[fb] */
62674 {
62675 { 0, 0, 0, 0 },
62676 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
62677 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ee0000 }
62678 },
62679/* bitindex.b ${Dsp-16-u16} */
62680 {
62681 { 0, 0, 0, 0 },
62682 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
62683 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ee0000 }
62684 },
62685/* bitindex.b ${Dsp-16-u24} */
62686 {
62687 { 0, 0, 0, 0 },
62688 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
62689 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6ae0000 }
62690 },
62691/* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
62692 {
62693 { 0, 0, 0, 0 },
62694 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
62695 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd830 }
62696 },
62697/* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
62698 {
62699 { 0, 0, 0, 0 },
62700 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
62701 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b0 }
62702 },
62703/* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
62704 {
62705 { 0, 0, 0, 0 },
62706 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62707 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd030 }
62708 },
62709/* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
62710 {
62711 { 0, 0, 0, 0 },
62712 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62713 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23000 }
62714 },
62715/* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
62716 {
62717 { 0, 0, 0, 0 },
62718 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62719 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4300000 }
62720 },
62721/* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
62722 {
62723 { 0, 0, 0, 0 },
62724 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62725 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6300000 }
62726 },
62727/* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
62728 {
62729 { 0, 0, 0, 0 },
62730 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62731 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b000 }
62732 },
62733/* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
62734 {
62735 { 0, 0, 0, 0 },
62736 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62737 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b00000 }
62738 },
62739/* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
62740 {
62741 { 0, 0, 0, 0 },
62742 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62743 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f000 }
62744 },
62745/* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
62746 {
62747 { 0, 0, 0, 0 },
62748 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62749 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f00000 }
62750 },
62751/* bclr${X} ${BitBase32-16-u19-Unprefixed} */
62752 {
62753 { 0, 0, 0, 0 },
62754 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
62755 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f00000 }
62756 },
62757/* bclr${X} ${BitBase32-16-u27-Unprefixed} */
62758 {
62759 { 0, 0, 0, 0 },
62760 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
62761 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b00000 }
62762 },
62763/* bclr${G} $Bitno16R,$Bit16Rn */
62764 {
62765 { 0, 0, 0, 0 },
62766 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62767 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e8000 }
62768 },
62769/* bclr${G} $Bitno16R,$Bit16An */
62770 {
62771 { 0, 0, 0, 0 },
62772 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62773 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e8400 }
62774 },
62775/* bclr${G} ${Dsp-16-u8}[$Bit16An] */
62776 {
62777 { 0, 0, 0, 0 },
62778 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62779 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e8800 }
62780 },
62781/* bclr${G} ${BitBase16-16-u8}[sb] */
62782 {
62783 { 0, 0, 0, 0 },
62784 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62785 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e8a00 }
62786 },
62787/* bclr${G} ${BitBase16-16-s8}[fb] */
62788 {
62789 { 0, 0, 0, 0 },
62790 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62791 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e8b00 }
62792 },
62793/* bclr${S} ${BitBase16-8-u11-S}[sb] */
62794 {
62795 { 0, 0, 0, 0 },
62796 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
62797 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4000 }
62798 },
62799/* bclr${G} ${Dsp-16-u16}[$Bit16An] */
62800 {
62801 { 0, 0, 0, 0 },
62802 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62803 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e8c0000 }
62804 },
62805/* bclr${G} ${BitBase16-16-u16}[sb] */
62806 {
62807 { 0, 0, 0, 0 },
62808 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62809 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e8e0000 }
62810 },
62811/* bclr${G} ${BitBase16-16-u16} */
62812 {
62813 { 0, 0, 0, 0 },
62814 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
62815 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e8f0000 }
62816 },
62817/* bclr${G} [$Bit16An] */
62818 {
62819 { 0, 0, 0, 0 },
62820 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
62821 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e86 }
62822 },
62823/* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62824 {
62825 { 0, 0, 0, 0 },
62826 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62827 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d808 }
62828 },
62829/* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62830 {
62831 { 0, 0, 0, 0 },
62832 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62833 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d088 }
62834 },
62835/* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62836 {
62837 { 0, 0, 0, 0 },
62838 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62839 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d008 }
62840 },
62841/* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62842 {
62843 { 0, 0, 0, 0 },
62844 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62845 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20800 }
62846 },
62847/* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62848 {
62849 { 0, 0, 0, 0 },
62850 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62851 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40800 }
62852 },
62853/* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62854 {
62855 { 0, 0, 0, 0 },
62856 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62857 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60800 }
62858 },
62859/* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
62860 {
62861 { 0, 0, 0, 0 },
62862 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62863 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28800 }
62864 },
62865/* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
62866 {
62867 { 0, 0, 0, 0 },
62868 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62869 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48800 }
62870 },
62871/* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
62872 {
62873 { 0, 0, 0, 0 },
62874 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62875 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c800 }
62876 },
62877/* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
62878 {
62879 { 0, 0, 0, 0 },
62880 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62881 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c800 }
62882 },
62883/* band${X} ${BitBase32-24-u19-Prefixed} */
62884 {
62885 { 0, 0, 0, 0 },
62886 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62887 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c800 }
62888 },
62889/* band${X} ${BitBase32-24-u27-Prefixed} */
62890 {
62891 { 0, 0, 0, 0 },
62892 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62893 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68800 }
62894 },
62895/* band${X} $Bitno16R,$Bit16Rn */
62896 {
62897 { 0, 0, 0, 0 },
62898 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62899 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e4000 }
62900 },
62901/* band${X} $Bitno16R,$Bit16An */
62902 {
62903 { 0, 0, 0, 0 },
62904 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62905 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e4400 }
62906 },
62907/* band${X} [$Bit16An] */
62908 {
62909 { 0, 0, 0, 0 },
62910 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62911 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e46 }
62912 },
62913/* band${X} ${Dsp-16-u8}[$Bit16An] */
62914 {
62915 { 0, 0, 0, 0 },
62916 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62917 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e4800 }
62918 },
62919/* band${X} ${Dsp-16-u16}[$Bit16An] */
62920 {
62921 { 0, 0, 0, 0 },
62922 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62923 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e4c0000 }
62924 },
62925/* band${X} ${BitBase16-16-u8}[sb] */
62926 {
62927 { 0, 0, 0, 0 },
62928 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62929 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e4a00 }
62930 },
62931/* band${X} ${BitBase16-16-u16}[sb] */
62932 {
62933 { 0, 0, 0, 0 },
62934 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62935 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e4e0000 }
62936 },
62937/* band${X} ${BitBase16-16-s8}[fb] */
62938 {
62939 { 0, 0, 0, 0 },
62940 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62941 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e4b00 }
62942 },
62943/* band${X} ${BitBase16-16-u16} */
62944 {
62945 { 0, 0, 0, 0 },
62946 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62947 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e4f0000 }
62948 },
62949/* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
62950 {
62951 { 0, 0, 0, 0 },
62952 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
62953 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6d000000 }
62954 },
62955/* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
62956 {
62957 { 0, 0, 0, 0 },
62958 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
62959 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7d000000 }
62960 },
62961/* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
62962 {
62963 { 0, 0, 0, 0 },
62964 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
62965 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x5d000000 }
62966 },
62967/* and.w${S} #${Imm-8-HI},r0 */
62968 {
62969 { 0, 0, 0, 0 },
62970 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
62971 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x4d0000 }
62972 },
62973/* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
62974 {
62975 { 0, 0, 0, 0 },
62976 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
62977 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6c0000 }
62978 },
62979/* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
62980 {
62981 { 0, 0, 0, 0 },
62982 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
62983 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7c0000 }
62984 },
62985/* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
62986 {
62987 { 0, 0, 0, 0 },
62988 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
62989 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x5c000000 }
62990 },
62991/* and.b${S} #${Imm-8-QI},r0l */
62992 {
62993 { 0, 0, 0, 0 },
62994 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
62995 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4c00 }
62996 },
62997/* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
62998 {
62999 { 0, 0, 0, 0 },
63000 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
63001 & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x10 }
63002 },
63003/* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
63004 {
63005 { 0, 0, 0, 0 },
63006 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
63007 & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1100 }
63008 },
63009/* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
63010 {
63011 { 0, 0, 0, 0 },
63012 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
63013 & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1200 }
63014 },
63015/* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
63016 {
63017 { 0, 0, 0, 0 },
63018 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
63019 & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x130000 }
63020 },
63021/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63022 {
63023 { 0, 0, 0, 0 },
63024 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63025 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990d00 }
63026 },
63027/* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
63028 {
63029 { 0, 0, 0, 0 },
63030 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63031 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992d00 }
63032 },
63033/* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
63034 {
63035 { 0, 0, 0, 0 },
63036 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63037 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993d00 }
63038 },
63039/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63040 {
63041 { 0, 0, 0, 0 },
63042 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63043 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918d00 }
63044 },
63045/* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
63046 {
63047 { 0, 0, 0, 0 },
63048 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63049 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ad00 }
63050 },
63051/* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
63052 {
63053 { 0, 0, 0, 0 },
63054 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63055 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bd00 }
63056 },
63057/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63058 {
63059 { 0, 0, 0, 0 },
63060 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63061 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910d00 }
63062 },
63063/* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
63064 {
63065 { 0, 0, 0, 0 },
63066 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63067 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912d00 }
63068 },
63069/* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
63070 {
63071 { 0, 0, 0, 0 },
63072 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63073 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913d00 }
63074 },
63075/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63076 {
63077 { 0, 0, 0, 0 },
63078 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63079 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930d0000 }
63080 },
63081/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63082 {
63083 { 0, 0, 0, 0 },
63084 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63085 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932d0000 }
63086 },
63087/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63088 {
63089 { 0, 0, 0, 0 },
63090 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63091 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933d0000 }
63092 },
63093/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63094 {
63095 { 0, 0, 0, 0 },
63096 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63097 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950d0000 }
63098 },
63099/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63100 {
63101 { 0, 0, 0, 0 },
63102 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63103 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952d0000 }
63104 },
63105/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63106 {
63107 { 0, 0, 0, 0 },
63108 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63109 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953d0000 }
63110 },
63111/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63112 {
63113 { 0, 0, 0, 0 },
63114 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63115 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970d0000 }
63116 },
63117/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63118 {
63119 { 0, 0, 0, 0 },
63120 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63121 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972d0000 }
63122 },
63123/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63124 {
63125 { 0, 0, 0, 0 },
63126 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63127 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973d0000 }
63128 },
63129/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
63130 {
63131 { 0, 0, 0, 0 },
63132 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63133 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938d0000 }
63134 },
63135/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
63136 {
63137 { 0, 0, 0, 0 },
63138 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63139 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ad0000 }
63140 },
63141/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
63142 {
63143 { 0, 0, 0, 0 },
63144 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63145 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bd0000 }
63146 },
63147/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
63148 {
63149 { 0, 0, 0, 0 },
63150 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63151 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958d0000 }
63152 },
63153/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
63154 {
63155 { 0, 0, 0, 0 },
63156 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63157 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ad0000 }
63158 },
63159/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
63160 {
63161 { 0, 0, 0, 0 },
63162 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63163 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bd0000 }
63164 },
63165/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
63166 {
63167 { 0, 0, 0, 0 },
63168 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63169 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cd0000 }
63170 },
63171/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
63172 {
63173 { 0, 0, 0, 0 },
63174 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63175 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ed0000 }
63176 },
63177/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
63178 {
63179 { 0, 0, 0, 0 },
63180 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63181 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fd0000 }
63182 },
63183/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
63184 {
63185 { 0, 0, 0, 0 },
63186 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63187 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cd0000 }
63188 },
63189/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
63190 {
63191 { 0, 0, 0, 0 },
63192 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63193 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ed0000 }
63194 },
63195/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
63196 {
63197 { 0, 0, 0, 0 },
63198 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63199 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fd0000 }
63200 },
63201/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
63202 {
63203 { 0, 0, 0, 0 },
63204 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
63205 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cd0000 }
63206 },
63207/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
63208 {
63209 { 0, 0, 0, 0 },
63210 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
63211 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ed0000 }
63212 },
63213/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
63214 {
63215 { 0, 0, 0, 0 },
63216 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
63217 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fd0000 }
63218 },
63219/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
63220 {
63221 { 0, 0, 0, 0 },
63222 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
63223 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978d0000 }
63224 },
63225/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
63226 {
63227 { 0, 0, 0, 0 },
63228 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
63229 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ad0000 }
63230 },
63231/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
63232 {
63233 { 0, 0, 0, 0 },
63234 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
63235 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bd0000 }
63236 },
63237/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63238 {
63239 { 0, 0, 0, 0 },
63240 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63241 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90d0000 }
63242 },
63243/* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
63244 {
63245 { 0, 0, 0, 0 },
63246 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63247 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92d0000 }
63248 },
63249/* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
63250 {
63251 { 0, 0, 0, 0 },
63252 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63253 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93d0000 }
63254 },
63255/* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
63256 {
63257 { 0, 0, 0, 0 },
63258 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63259 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93d0000 }
63260 },
63261/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63262 {
63263 { 0, 0, 0, 0 },
63264 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63265 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18d0000 }
63266 },
63267/* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
63268 {
63269 { 0, 0, 0, 0 },
63270 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63271 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ad0000 }
63272 },
63273/* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
63274 {
63275 { 0, 0, 0, 0 },
63276 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63277 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bd0000 }
63278 },
63279/* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
63280 {
63281 { 0, 0, 0, 0 },
63282 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63283 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bd0000 }
63284 },
63285/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63286 {
63287 { 0, 0, 0, 0 },
63288 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63289 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10d0000 }
63290 },
63291/* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
63292 {
63293 { 0, 0, 0, 0 },
63294 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63295 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12d0000 }
63296 },
63297/* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
63298 {
63299 { 0, 0, 0, 0 },
63300 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63301 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13d0000 }
63302 },
63303/* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
63304 {
63305 { 0, 0, 0, 0 },
63306 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63307 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13d0000 }
63308 },
63309/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63310 {
63311 { 0, 0, 0, 0 },
63312 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63313 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30d0000 }
63314 },
63315/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63316 {
63317 { 0, 0, 0, 0 },
63318 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63319 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32d0000 }
63320 },
63321/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63322 {
63323 { 0, 0, 0, 0 },
63324 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63325 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33d0000 }
63326 },
63327/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
63328 {
63329 { 0, 0, 0, 0 },
63330 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63331 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33d0000 }
63332 },
63333/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63334 {
63335 { 0, 0, 0, 0 },
63336 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63337 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50d0000 }
63338 },
63339/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63340 {
63341 { 0, 0, 0, 0 },
63342 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63343 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52d0000 }
63344 },
63345/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63346 {
63347 { 0, 0, 0, 0 },
63348 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63349 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53d0000 }
63350 },
63351/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
63352 {
63353 { 0, 0, 0, 0 },
63354 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63355 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53d0000 }
63356 },
63357/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63358 {
63359 { 0, 0, 0, 0 },
63360 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63361 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70d0000 }
63362 },
63363/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63364 {
63365 { 0, 0, 0, 0 },
63366 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63367 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72d0000 }
63368 },
63369/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63370 {
63371 { 0, 0, 0, 0 },
63372 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63373 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73d0000 }
63374 },
63375/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
63376 {
63377 { 0, 0, 0, 0 },
63378 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63379 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73d0000 }
63380 },
63381/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
63382 {
63383 { 0, 0, 0, 0 },
63384 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63385 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38d0000 }
63386 },
63387/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
63388 {
63389 { 0, 0, 0, 0 },
63390 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63391 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ad0000 }
63392 },
63393/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
63394 {
63395 { 0, 0, 0, 0 },
63396 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63397 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bd0000 }
63398 },
63399/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
63400 {
63401 { 0, 0, 0, 0 },
63402 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63403 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bd0000 }
63404 },
63405/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
63406 {
63407 { 0, 0, 0, 0 },
63408 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63409 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58d0000 }
63410 },
63411/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
63412 {
63413 { 0, 0, 0, 0 },
63414 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63415 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ad0000 }
63416 },
63417/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
63418 {
63419 { 0, 0, 0, 0 },
63420 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63421 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bd0000 }
63422 },
63423/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
63424 {
63425 { 0, 0, 0, 0 },
63426 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63427 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bd0000 }
63428 },
63429/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
63430 {
63431 { 0, 0, 0, 0 },
63432 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63433 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cd0000 }
63434 },
63435/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
63436 {
63437 { 0, 0, 0, 0 },
63438 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63439 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ed0000 }
63440 },
63441/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
63442 {
63443 { 0, 0, 0, 0 },
63444 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63445 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fd0000 }
63446 },
63447/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
63448 {
63449 { 0, 0, 0, 0 },
63450 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63451 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fd0000 }
63452 },
63453/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
63454 {
63455 { 0, 0, 0, 0 },
63456 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63457 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cd0000 }
63458 },
63459/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
63460 {
63461 { 0, 0, 0, 0 },
63462 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63463 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ed0000 }
63464 },
63465/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
63466 {
63467 { 0, 0, 0, 0 },
63468 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63469 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fd0000 }
63470 },
63471/* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
63472 {
63473 { 0, 0, 0, 0 },
63474 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63475 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fd0000 }
63476 },
63477/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
63478 {
63479 { 0, 0, 0, 0 },
63480 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
63481 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cd0000 }
63482 },
63483/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
63484 {
63485 { 0, 0, 0, 0 },
63486 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
63487 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ed0000 }
63488 },
63489/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
63490 {
63491 { 0, 0, 0, 0 },
63492 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
63493 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fd0000 }
63494 },
63495/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
63496 {
63497 { 0, 0, 0, 0 },
63498 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
63499 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fd0000 }
63500 },
63501/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
63502 {
63503 { 0, 0, 0, 0 },
63504 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
63505 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78d0000 }
63506 },
63507/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
63508 {
63509 { 0, 0, 0, 0 },
63510 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
63511 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ad0000 }
63512 },
63513/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
63514 {
63515 { 0, 0, 0, 0 },
63516 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
63517 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bd0000 }
63518 },
63519/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
63520 {
63521 { 0, 0, 0, 0 },
63522 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
63523 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bd0000 }
63524 },
63525/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63526 {
63527 { 0, 0, 0, 0 },
63528 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63529 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90d0000 }
63530 },
63531/* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
63532 {
63533 { 0, 0, 0, 0 },
63534 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63535 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92d0000 }
63536 },
63537/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63538 {
63539 { 0, 0, 0, 0 },
63540 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63541 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18d0000 }
63542 },
63543/* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
63544 {
63545 { 0, 0, 0, 0 },
63546 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63547 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ad0000 }
63548 },
63549/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63550 {
63551 { 0, 0, 0, 0 },
63552 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63553 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10d0000 }
63554 },
63555/* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
63556 {
63557 { 0, 0, 0, 0 },
63558 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63559 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12d0000 }
63560 },
63561/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
63562 {
63563 { 0, 0, 0, 0 },
63564 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63565 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30d0000 }
63566 },
63567/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
63568 {
63569 { 0, 0, 0, 0 },
63570 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63571 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32d0000 }
63572 },
63573/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
63574 {
63575 { 0, 0, 0, 0 },
63576 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63577 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50d0000 }
63578 },
63579/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
63580 {
63581 { 0, 0, 0, 0 },
63582 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63583 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52d0000 }
63584 },
63585/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
63586 {
63587 { 0, 0, 0, 0 },
63588 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63589 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70d0000 }
63590 },
63591/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
63592 {
63593 { 0, 0, 0, 0 },
63594 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63595 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72d0000 }
63596 },
63597/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
63598 {
63599 { 0, 0, 0, 0 },
63600 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
63601 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38d0000 }
63602 },
63603/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
63604 {
63605 { 0, 0, 0, 0 },
63606 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
63607 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ad0000 }
63608 },
63609/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
63610 {
63611 { 0, 0, 0, 0 },
63612 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
63613 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58d0000 }
63614 },
63615/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
63616 {
63617 { 0, 0, 0, 0 },
63618 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
63619 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ad0000 }
63620 },
63621/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
63622 {
63623 { 0, 0, 0, 0 },
63624 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
63625 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cd0000 }
63626 },
63627/* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
63628 {
63629 { 0, 0, 0, 0 },
63630 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
63631 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ed0000 }
63632 },
63633/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
63634 {
63635 { 0, 0, 0, 0 },
63636 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
63637 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cd0000 }
63638 },
63639/* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
63640 {
63641 { 0, 0, 0, 0 },
63642 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
63643 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ed0000 }
63644 },
63645/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
63646 {
63647 { 0, 0, 0, 0 },
63648 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
63649 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cd0000 }
63650 },
63651/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
63652 {
63653 { 0, 0, 0, 0 },
63654 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
63655 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ed0000 }
63656 },
63657/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
63658 {
63659 { 0, 0, 0, 0 },
63660 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
63661 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78d0000 }
63662 },
63663/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
63664 {
63665 { 0, 0, 0, 0 },
63666 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
63667 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ad0000 }
63668 },
63669/* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
63670 {
63671 { 0, 0, 0, 0 },
63672 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63673 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90d }
63674 },
63675/* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
63676 {
63677 { 0, 0, 0, 0 },
63678 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63679 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892d }
63680 },
63681/* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63682 {
63683 { 0, 0, 0, 0 },
63684 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63685 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890d }
63686 },
63687/* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
63688 {
63689 { 0, 0, 0, 0 },
63690 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63691 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18d }
63692 },
63693/* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
63694 {
63695 { 0, 0, 0, 0 },
63696 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63697 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ad }
63698 },
63699/* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63700 {
63701 { 0, 0, 0, 0 },
63702 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63703 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818d }
63704 },
63705/* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
63706 {
63707 { 0, 0, 0, 0 },
63708 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63709 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10d }
63710 },
63711/* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
63712 {
63713 { 0, 0, 0, 0 },
63714 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63715 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812d }
63716 },
63717/* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63718 {
63719 { 0, 0, 0, 0 },
63720 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63721 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810d }
63722 },
63723/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
63724 {
63725 { 0, 0, 0, 0 },
63726 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63727 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30d00 }
63728 },
63729/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
63730 {
63731 { 0, 0, 0, 0 },
63732 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63733 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832d00 }
63734 },
63735/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
63736 {
63737 { 0, 0, 0, 0 },
63738 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63739 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830d00 }
63740 },
63741/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
63742 {
63743 { 0, 0, 0, 0 },
63744 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63745 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50d0000 }
63746 },
63747/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
63748 {
63749 { 0, 0, 0, 0 },
63750 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63751 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852d0000 }
63752 },
63753/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
63754 {
63755 { 0, 0, 0, 0 },
63756 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63757 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850d0000 }
63758 },
63759/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
63760 {
63761 { 0, 0, 0, 0 },
63762 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63763 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70d0000 }
63764 },
63765/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
63766 {
63767 { 0, 0, 0, 0 },
63768 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63769 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872d0000 }
63770 },
63771/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
63772 {
63773 { 0, 0, 0, 0 },
63774 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63775 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870d0000 }
63776 },
63777/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
63778 {
63779 { 0, 0, 0, 0 },
63780 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
63781 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38d00 }
63782 },
63783/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
63784 {
63785 { 0, 0, 0, 0 },
63786 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
63787 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ad00 }
63788 },
63789/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
63790 {
63791 { 0, 0, 0, 0 },
63792 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
63793 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838d00 }
63794 },
63795/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
63796 {
63797 { 0, 0, 0, 0 },
63798 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
63799 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58d0000 }
63800 },
63801/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
63802 {
63803 { 0, 0, 0, 0 },
63804 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
63805 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ad0000 }
63806 },
63807/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
63808 {
63809 { 0, 0, 0, 0 },
63810 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
63811 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858d0000 }
63812 },
63813/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
63814 {
63815 { 0, 0, 0, 0 },
63816 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
63817 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cd00 }
63818 },
63819/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
63820 {
63821 { 0, 0, 0, 0 },
63822 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
63823 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ed00 }
63824 },
63825/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
63826 {
63827 { 0, 0, 0, 0 },
63828 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
63829 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cd00 }
63830 },
63831/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
63832 {
63833 { 0, 0, 0, 0 },
63834 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
63835 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cd0000 }
63836 },
63837/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
63838 {
63839 { 0, 0, 0, 0 },
63840 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
63841 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ed0000 }
63842 },
63843/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
63844 {
63845 { 0, 0, 0, 0 },
63846 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
63847 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cd0000 }
63848 },
63849/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
63850 {
63851 { 0, 0, 0, 0 },
63852 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
63853 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cd0000 }
63854 },
63855/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
63856 {
63857 { 0, 0, 0, 0 },
63858 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
63859 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ed0000 }
63860 },
63861/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
63862 {
63863 { 0, 0, 0, 0 },
63864 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
63865 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cd0000 }
63866 },
63867/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
63868 {
63869 { 0, 0, 0, 0 },
63870 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
63871 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78d0000 }
63872 },
63873/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
63874 {
63875 { 0, 0, 0, 0 },
63876 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
63877 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ad0000 }
63878 },
63879/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
63880 {
63881 { 0, 0, 0, 0 },
63882 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
63883 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878d0000 }
63884 },
63885/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
63886 {
63887 { 0, 0, 0, 0 },
63888 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
63889 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980d00 }
63890 },
63891/* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
63892 {
63893 { 0, 0, 0, 0 },
63894 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
63895 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982d00 }
63896 },
63897/* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
63898 {
63899 { 0, 0, 0, 0 },
63900 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
63901 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983d00 }
63902 },
63903/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
63904 {
63905 { 0, 0, 0, 0 },
63906 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
63907 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908d00 }
63908 },
63909/* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
63910 {
63911 { 0, 0, 0, 0 },
63912 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
63913 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ad00 }
63914 },
63915/* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
63916 {
63917 { 0, 0, 0, 0 },
63918 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
63919 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bd00 }
63920 },
63921/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63922 {
63923 { 0, 0, 0, 0 },
63924 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63925 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900d00 }
63926 },
63927/* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
63928 {
63929 { 0, 0, 0, 0 },
63930 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63931 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902d00 }
63932 },
63933/* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
63934 {
63935 { 0, 0, 0, 0 },
63936 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63937 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903d00 }
63938 },
63939/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63940 {
63941 { 0, 0, 0, 0 },
63942 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63943 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920d0000 }
63944 },
63945/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63946 {
63947 { 0, 0, 0, 0 },
63948 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63949 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922d0000 }
63950 },
63951/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63952 {
63953 { 0, 0, 0, 0 },
63954 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63955 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923d0000 }
63956 },
63957/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63958 {
63959 { 0, 0, 0, 0 },
63960 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63961 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940d0000 }
63962 },
63963/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63964 {
63965 { 0, 0, 0, 0 },
63966 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63967 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942d0000 }
63968 },
63969/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63970 {
63971 { 0, 0, 0, 0 },
63972 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63973 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943d0000 }
63974 },
63975/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63976 {
63977 { 0, 0, 0, 0 },
63978 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63979 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960d0000 }
63980 },
63981/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63982 {
63983 { 0, 0, 0, 0 },
63984 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63985 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962d0000 }
63986 },
63987/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63988 {
63989 { 0, 0, 0, 0 },
63990 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63991 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963d0000 }
63992 },
63993/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
63994 {
63995 { 0, 0, 0, 0 },
63996 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63997 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928d0000 }
63998 },
63999/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
64000 {
64001 { 0, 0, 0, 0 },
64002 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64003 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ad0000 }
64004 },
64005/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
64006 {
64007 { 0, 0, 0, 0 },
64008 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64009 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bd0000 }
64010 },
64011/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
64012 {
64013 { 0, 0, 0, 0 },
64014 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64015 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948d0000 }
64016 },
64017/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
64018 {
64019 { 0, 0, 0, 0 },
64020 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64021 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ad0000 }
64022 },
64023/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
64024 {
64025 { 0, 0, 0, 0 },
64026 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64027 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bd0000 }
64028 },
64029/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
64030 {
64031 { 0, 0, 0, 0 },
64032 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64033 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cd0000 }
64034 },
64035/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
64036 {
64037 { 0, 0, 0, 0 },
64038 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64039 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ed0000 }
64040 },
64041/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
64042 {
64043 { 0, 0, 0, 0 },
64044 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64045 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fd0000 }
64046 },
64047/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
64048 {
64049 { 0, 0, 0, 0 },
64050 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64051 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cd0000 }
64052 },
64053/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
64054 {
64055 { 0, 0, 0, 0 },
64056 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64057 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ed0000 }
64058 },
64059/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
64060 {
64061 { 0, 0, 0, 0 },
64062 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64063 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fd0000 }
64064 },
64065/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
64066 {
64067 { 0, 0, 0, 0 },
64068 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
64069 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cd0000 }
64070 },
64071/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
64072 {
64073 { 0, 0, 0, 0 },
64074 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64075 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ed0000 }
64076 },
64077/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
64078 {
64079 { 0, 0, 0, 0 },
64080 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64081 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fd0000 }
64082 },
64083/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
64084 {
64085 { 0, 0, 0, 0 },
64086 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
64087 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968d0000 }
64088 },
64089/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
64090 {
64091 { 0, 0, 0, 0 },
64092 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
64093 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ad0000 }
64094 },
64095/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
64096 {
64097 { 0, 0, 0, 0 },
64098 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
64099 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bd0000 }
64100 },
64101/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64102 {
64103 { 0, 0, 0, 0 },
64104 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64105 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80d0000 }
64106 },
64107/* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
64108 {
64109 { 0, 0, 0, 0 },
64110 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64111 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82d0000 }
64112 },
64113/* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
64114 {
64115 { 0, 0, 0, 0 },
64116 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64117 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83d0000 }
64118 },
64119/* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
64120 {
64121 { 0, 0, 0, 0 },
64122 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64123 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83d0000 }
64124 },
64125/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64126 {
64127 { 0, 0, 0, 0 },
64128 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64129 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08d0000 }
64130 },
64131/* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
64132 {
64133 { 0, 0, 0, 0 },
64134 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64135 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ad0000 }
64136 },
64137/* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
64138 {
64139 { 0, 0, 0, 0 },
64140 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64141 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bd0000 }
64142 },
64143/* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
64144 {
64145 { 0, 0, 0, 0 },
64146 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64147 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bd0000 }
64148 },
64149/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64150 {
64151 { 0, 0, 0, 0 },
64152 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64153 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00d0000 }
64154 },
64155/* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
64156 {
64157 { 0, 0, 0, 0 },
64158 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64159 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02d0000 }
64160 },
64161/* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
64162 {
64163 { 0, 0, 0, 0 },
64164 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64165 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03d0000 }
64166 },
64167/* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
64168 {
64169 { 0, 0, 0, 0 },
64170 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64171 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03d0000 }
64172 },
64173/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64174 {
64175 { 0, 0, 0, 0 },
64176 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64177 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20d0000 }
64178 },
64179/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64180 {
64181 { 0, 0, 0, 0 },
64182 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64183 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22d0000 }
64184 },
64185/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64186 {
64187 { 0, 0, 0, 0 },
64188 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64189 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23d0000 }
64190 },
64191/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
64192 {
64193 { 0, 0, 0, 0 },
64194 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64195 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23d0000 }
64196 },
64197/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64198 {
64199 { 0, 0, 0, 0 },
64200 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64201 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40d0000 }
64202 },
64203/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64204 {
64205 { 0, 0, 0, 0 },
64206 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64207 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42d0000 }
64208 },
64209/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64210 {
64211 { 0, 0, 0, 0 },
64212 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64213 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43d0000 }
64214 },
64215/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
64216 {
64217 { 0, 0, 0, 0 },
64218 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64219 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43d0000 }
64220 },
64221/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64222 {
64223 { 0, 0, 0, 0 },
64224 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64225 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60d0000 }
64226 },
64227/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64228 {
64229 { 0, 0, 0, 0 },
64230 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64231 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62d0000 }
64232 },
64233/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64234 {
64235 { 0, 0, 0, 0 },
64236 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64237 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63d0000 }
64238 },
64239/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
64240 {
64241 { 0, 0, 0, 0 },
64242 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64243 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63d0000 }
64244 },
64245/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
64246 {
64247 { 0, 0, 0, 0 },
64248 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64249 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28d0000 }
64250 },
64251/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
64252 {
64253 { 0, 0, 0, 0 },
64254 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64255 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ad0000 }
64256 },
64257/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
64258 {
64259 { 0, 0, 0, 0 },
64260 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64261 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bd0000 }
64262 },
64263/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
64264 {
64265 { 0, 0, 0, 0 },
64266 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64267 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bd0000 }
64268 },
64269/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
64270 {
64271 { 0, 0, 0, 0 },
64272 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64273 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48d0000 }
64274 },
64275/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
64276 {
64277 { 0, 0, 0, 0 },
64278 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64279 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ad0000 }
64280 },
64281/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
64282 {
64283 { 0, 0, 0, 0 },
64284 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64285 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bd0000 }
64286 },
64287/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
64288 {
64289 { 0, 0, 0, 0 },
64290 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64291 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bd0000 }
64292 },
64293/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
64294 {
64295 { 0, 0, 0, 0 },
64296 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64297 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cd0000 }
64298 },
64299/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
64300 {
64301 { 0, 0, 0, 0 },
64302 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64303 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ed0000 }
64304 },
64305/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
64306 {
64307 { 0, 0, 0, 0 },
64308 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64309 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fd0000 }
64310 },
64311/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
64312 {
64313 { 0, 0, 0, 0 },
64314 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64315 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fd0000 }
64316 },
64317/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
64318 {
64319 { 0, 0, 0, 0 },
64320 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64321 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cd0000 }
64322 },
64323/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
64324 {
64325 { 0, 0, 0, 0 },
64326 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64327 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ed0000 }
64328 },
64329/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
64330 {
64331 { 0, 0, 0, 0 },
64332 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64333 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fd0000 }
64334 },
64335/* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
64336 {
64337 { 0, 0, 0, 0 },
64338 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64339 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fd0000 }
64340 },
64341/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
64342 {
64343 { 0, 0, 0, 0 },
64344 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
64345 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cd0000 }
64346 },
64347/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
64348 {
64349 { 0, 0, 0, 0 },
64350 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
64351 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ed0000 }
64352 },
64353/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
64354 {
64355 { 0, 0, 0, 0 },
64356 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
64357 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fd0000 }
64358 },
64359/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
64360 {
64361 { 0, 0, 0, 0 },
64362 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
64363 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fd0000 }
64364 },
64365/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
64366 {
64367 { 0, 0, 0, 0 },
64368 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
64369 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68d0000 }
64370 },
64371/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
64372 {
64373 { 0, 0, 0, 0 },
64374 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
64375 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ad0000 }
64376 },
64377/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
64378 {
64379 { 0, 0, 0, 0 },
64380 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
64381 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bd0000 }
64382 },
64383/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
64384 {
64385 { 0, 0, 0, 0 },
64386 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
64387 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bd0000 }
64388 },
64389/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64390 {
64391 { 0, 0, 0, 0 },
64392 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64393 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80d0000 }
64394 },
64395/* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
64396 {
64397 { 0, 0, 0, 0 },
64398 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64399 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82d0000 }
64400 },
64401/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64402 {
64403 { 0, 0, 0, 0 },
64404 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64405 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08d0000 }
64406 },
64407/* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
64408 {
64409 { 0, 0, 0, 0 },
64410 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64411 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ad0000 }
64412 },
64413/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64414 {
64415 { 0, 0, 0, 0 },
64416 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64417 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00d0000 }
64418 },
64419/* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
64420 {
64421 { 0, 0, 0, 0 },
64422 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64423 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02d0000 }
64424 },
64425/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
64426 {
64427 { 0, 0, 0, 0 },
64428 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64429 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20d0000 }
64430 },
64431/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
64432 {
64433 { 0, 0, 0, 0 },
64434 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64435 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22d0000 }
64436 },
64437/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
64438 {
64439 { 0, 0, 0, 0 },
64440 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64441 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40d0000 }
64442 },
64443/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
64444 {
64445 { 0, 0, 0, 0 },
64446 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64447 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42d0000 }
64448 },
64449/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
64450 {
64451 { 0, 0, 0, 0 },
64452 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64453 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60d0000 }
64454 },
64455/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
64456 {
64457 { 0, 0, 0, 0 },
64458 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64459 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62d0000 }
64460 },
64461/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
64462 {
64463 { 0, 0, 0, 0 },
64464 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
64465 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28d0000 }
64466 },
64467/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
64468 {
64469 { 0, 0, 0, 0 },
64470 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
64471 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ad0000 }
64472 },
64473/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
64474 {
64475 { 0, 0, 0, 0 },
64476 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
64477 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48d0000 }
64478 },
64479/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
64480 {
64481 { 0, 0, 0, 0 },
64482 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
64483 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ad0000 }
64484 },
64485/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
64486 {
64487 { 0, 0, 0, 0 },
64488 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64489 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cd0000 }
64490 },
64491/* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
64492 {
64493 { 0, 0, 0, 0 },
64494 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64495 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ed0000 }
64496 },
64497/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
64498 {
64499 { 0, 0, 0, 0 },
64500 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64501 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cd0000 }
64502 },
64503/* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
64504 {
64505 { 0, 0, 0, 0 },
64506 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64507 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ed0000 }
64508 },
64509/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
64510 {
64511 { 0, 0, 0, 0 },
64512 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
64513 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cd0000 }
64514 },
64515/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
64516 {
64517 { 0, 0, 0, 0 },
64518 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
64519 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ed0000 }
64520 },
64521/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
64522 {
64523 { 0, 0, 0, 0 },
64524 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
64525 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68d0000 }
64526 },
64527/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
64528 {
64529 { 0, 0, 0, 0 },
64530 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
64531 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ad0000 }
64532 },
64533/* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
64534 {
64535 { 0, 0, 0, 0 },
64536 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64537 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80d }
64538 },
64539/* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
64540 {
64541 { 0, 0, 0, 0 },
64542 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64543 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882d }
64544 },
64545/* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64546 {
64547 { 0, 0, 0, 0 },
64548 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64549 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880d }
64550 },
64551/* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
64552 {
64553 { 0, 0, 0, 0 },
64554 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64555 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08d }
64556 },
64557/* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
64558 {
64559 { 0, 0, 0, 0 },
64560 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64561 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ad }
64562 },
64563/* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64564 {
64565 { 0, 0, 0, 0 },
64566 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64567 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808d }
64568 },
64569/* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
64570 {
64571 { 0, 0, 0, 0 },
64572 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64573 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00d }
64574 },
64575/* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
64576 {
64577 { 0, 0, 0, 0 },
64578 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64579 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802d }
64580 },
64581/* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64582 {
64583 { 0, 0, 0, 0 },
64584 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64585 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800d }
64586 },
64587/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64588 {
64589 { 0, 0, 0, 0 },
64590 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64591 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20d00 }
64592 },
64593/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64594 {
64595 { 0, 0, 0, 0 },
64596 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64597 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822d00 }
64598 },
64599/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
64600 {
64601 { 0, 0, 0, 0 },
64602 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64603 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820d00 }
64604 },
64605/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64606 {
64607 { 0, 0, 0, 0 },
64608 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64609 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40d0000 }
64610 },
64611/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64612 {
64613 { 0, 0, 0, 0 },
64614 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64615 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842d0000 }
64616 },
64617/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
64618 {
64619 { 0, 0, 0, 0 },
64620 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64621 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840d0000 }
64622 },
64623/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
64624 {
64625 { 0, 0, 0, 0 },
64626 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64627 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60d0000 }
64628 },
64629/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
64630 {
64631 { 0, 0, 0, 0 },
64632 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64633 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862d0000 }
64634 },
64635/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
64636 {
64637 { 0, 0, 0, 0 },
64638 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64639 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860d0000 }
64640 },
64641/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
64642 {
64643 { 0, 0, 0, 0 },
64644 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64645 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28d00 }
64646 },
64647/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
64648 {
64649 { 0, 0, 0, 0 },
64650 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64651 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ad00 }
64652 },
64653/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
64654 {
64655 { 0, 0, 0, 0 },
64656 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64657 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828d00 }
64658 },
64659/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
64660 {
64661 { 0, 0, 0, 0 },
64662 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64663 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48d0000 }
64664 },
64665/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
64666 {
64667 { 0, 0, 0, 0 },
64668 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64669 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ad0000 }
64670 },
64671/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
64672 {
64673 { 0, 0, 0, 0 },
64674 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64675 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848d0000 }
64676 },
64677/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
64678 {
64679 { 0, 0, 0, 0 },
64680 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64681 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cd00 }
64682 },
64683/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
64684 {
64685 { 0, 0, 0, 0 },
64686 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64687 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ed00 }
64688 },
64689/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
64690 {
64691 { 0, 0, 0, 0 },
64692 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64693 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cd00 }
64694 },
64695/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
64696 {
64697 { 0, 0, 0, 0 },
64698 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64699 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cd0000 }
64700 },
64701/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
64702 {
64703 { 0, 0, 0, 0 },
64704 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64705 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ed0000 }
64706 },
64707/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
64708 {
64709 { 0, 0, 0, 0 },
64710 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64711 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cd0000 }
64712 },
64713/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
64714 {
64715 { 0, 0, 0, 0 },
64716 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
64717 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cd0000 }
64718 },
64719/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
64720 {
64721 { 0, 0, 0, 0 },
64722 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
64723 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ed0000 }
64724 },
64725/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
64726 {
64727 { 0, 0, 0, 0 },
64728 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
64729 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cd0000 }
64730 },
64731/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
64732 {
64733 { 0, 0, 0, 0 },
64734 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
64735 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68d0000 }
64736 },
64737/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
64738 {
64739 { 0, 0, 0, 0 },
64740 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
64741 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ad0000 }
64742 },
64743/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
64744 {
64745 { 0, 0, 0, 0 },
64746 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
64747 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868d0000 }
64748 },
64749/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
64750 {
64751 { 0, 0, 0, 0 },
64752 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
64753 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x918000 }
64754 },
64755/* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
64756 {
64757 { 0, 0, 0, 0 },
64758 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
64759 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x91a000 }
64760 },
64761/* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
64762 {
64763 { 0, 0, 0, 0 },
64764 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
64765 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x91b000 }
64766 },
64767/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
64768 {
64769 { 0, 0, 0, 0 },
64770 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
64771 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x918400 }
64772 },
64773/* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
64774 {
64775 { 0, 0, 0, 0 },
64776 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
64777 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x91a400 }
64778 },
64779/* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
64780 {
64781 { 0, 0, 0, 0 },
64782 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
64783 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x91b400 }
64784 },
64785/* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
64786 {
64787 { 0, 0, 0, 0 },
64788 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
64789 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x918600 }
64790 },
64791/* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
64792 {
64793 { 0, 0, 0, 0 },
64794 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
64795 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x91a600 }
64796 },
64797/* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
64798 {
64799 { 0, 0, 0, 0 },
64800 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
64801 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x91b600 }
64802 },
64803/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
64804 {
64805 { 0, 0, 0, 0 },
64806 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
64807 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x91880000 }
64808 },
64809/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
64810 {
64811 { 0, 0, 0, 0 },
64812 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
64813 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x91a80000 }
64814 },
64815/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
64816 {
64817 { 0, 0, 0, 0 },
64818 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
64819 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x91b80000 }
64820 },
64821/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
64822 {
64823 { 0, 0, 0, 0 },
64824 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
64825 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x918c0000 }
64826 },
64827/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
64828 {
64829 { 0, 0, 0, 0 },
64830 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
64831 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x91ac0000 }
64832 },
64833/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
64834 {
64835 { 0, 0, 0, 0 },
64836 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
64837 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x91bc0000 }
64838 },
64839/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
64840 {
64841 { 0, 0, 0, 0 },
64842 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64843 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x918a0000 }
64844 },
64845/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
64846 {
64847 { 0, 0, 0, 0 },
64848 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64849 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91aa0000 }
64850 },
64851/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
64852 {
64853 { 0, 0, 0, 0 },
64854 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64855 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91ba0000 }
64856 },
64857/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
64858 {
64859 { 0, 0, 0, 0 },
64860 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64861 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x918e0000 }
64862 },
64863/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
64864 {
64865 { 0, 0, 0, 0 },
64866 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64867 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91ae0000 }
64868 },
64869/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
64870 {
64871 { 0, 0, 0, 0 },
64872 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64873 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91be0000 }
64874 },
64875/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
64876 {
64877 { 0, 0, 0, 0 },
64878 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64879 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x918b0000 }
64880 },
64881/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
64882 {
64883 { 0, 0, 0, 0 },
64884 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64885 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91ab0000 }
64886 },
64887/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
64888 {
64889 { 0, 0, 0, 0 },
64890 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64891 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91bb0000 }
64892 },
64893/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
64894 {
64895 { 0, 0, 0, 0 },
64896 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
64897 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x918f0000 }
64898 },
64899/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
64900 {
64901 { 0, 0, 0, 0 },
64902 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64903 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x91af0000 }
64904 },
64905/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
64906 {
64907 { 0, 0, 0, 0 },
64908 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64909 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x91bf0000 }
64910 },
64911/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
64912 {
64913 { 0, 0, 0, 0 },
64914 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
64915 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x91c00000 }
64916 },
64917/* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
64918 {
64919 { 0, 0, 0, 0 },
64920 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
64921 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x91e00000 }
64922 },
64923/* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
64924 {
64925 { 0, 0, 0, 0 },
64926 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
64927 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x91f00000 }
64928 },
64929/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
64930 {
64931 { 0, 0, 0, 0 },
64932 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
64933 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x91c40000 }
64934 },
64935/* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
64936 {
64937 { 0, 0, 0, 0 },
64938 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
64939 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x91e40000 }
64940 },
64941/* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
64942 {
64943 { 0, 0, 0, 0 },
64944 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
64945 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x91f40000 }
64946 },
64947/* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
64948 {
64949 { 0, 0, 0, 0 },
64950 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
64951 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x91c60000 }
64952 },
64953/* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
64954 {
64955 { 0, 0, 0, 0 },
64956 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
64957 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x91e60000 }
64958 },
64959/* and.w${G} ${Dsp-16-u16},[$Dst16An] */
64960 {
64961 { 0, 0, 0, 0 },
64962 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
64963 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x91f60000 }
64964 },
64965/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
64966 {
64967 { 0, 0, 0, 0 },
64968 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
64969 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x91c80000 }
64970 },
64971/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
64972 {
64973 { 0, 0, 0, 0 },
64974 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
64975 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x91e80000 }
64976 },
64977/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
64978 {
64979 { 0, 0, 0, 0 },
64980 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
64981 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x91f80000 }
64982 },
64983/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
64984 {
64985 { 0, 0, 0, 0 },
64986 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
64987 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x91cc0000 }
64988 },
64989/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
64990 {
64991 { 0, 0, 0, 0 },
64992 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
64993 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x91ec0000 }
64994 },
64995/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
64996 {
64997 { 0, 0, 0, 0 },
64998 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
64999 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x91fc0000 }
65000 },
65001/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
65002 {
65003 { 0, 0, 0, 0 },
65004 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65005 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ca0000 }
65006 },
65007/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
65008 {
65009 { 0, 0, 0, 0 },
65010 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65011 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ea0000 }
65012 },
65013/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
65014 {
65015 { 0, 0, 0, 0 },
65016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65017 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x91fa0000 }
65018 },
65019/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
65020 {
65021 { 0, 0, 0, 0 },
65022 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65023 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ce0000 }
65024 },
65025/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
65026 {
65027 { 0, 0, 0, 0 },
65028 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65029 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ee0000 }
65030 },
65031/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
65032 {
65033 { 0, 0, 0, 0 },
65034 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65035 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x91fe0000 }
65036 },
65037/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
65038 {
65039 { 0, 0, 0, 0 },
65040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65041 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x91cb0000 }
65042 },
65043/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
65044 {
65045 { 0, 0, 0, 0 },
65046 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65047 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x91eb0000 }
65048 },
65049/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
65050 {
65051 { 0, 0, 0, 0 },
65052 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65053 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x91fb0000 }
65054 },
65055/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
65056 {
65057 { 0, 0, 0, 0 },
65058 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
65059 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x91cf0000 }
65060 },
65061/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
65062 {
65063 { 0, 0, 0, 0 },
65064 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
65065 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x91ef0000 }
65066 },
65067/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
65068 {
65069 { 0, 0, 0, 0 },
65070 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
65071 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x91ff0000 }
65072 },
65073/* and.w${G} $Src16RnHI,$Dst16RnHI */
65074 {
65075 { 0, 0, 0, 0 },
65076 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
65077 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9100 }
65078 },
65079/* and.w${G} $Src16AnHI,$Dst16RnHI */
65080 {
65081 { 0, 0, 0, 0 },
65082 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
65083 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9140 }
65084 },
65085/* and.w${G} [$Src16An],$Dst16RnHI */
65086 {
65087 { 0, 0, 0, 0 },
65088 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
65089 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9160 }
65090 },
65091/* and.w${G} $Src16RnHI,$Dst16AnHI */
65092 {
65093 { 0, 0, 0, 0 },
65094 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
65095 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9104 }
65096 },
65097/* and.w${G} $Src16AnHI,$Dst16AnHI */
65098 {
65099 { 0, 0, 0, 0 },
65100 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
65101 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9144 }
65102 },
65103/* and.w${G} [$Src16An],$Dst16AnHI */
65104 {
65105 { 0, 0, 0, 0 },
65106 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
65107 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9164 }
65108 },
65109/* and.w${G} $Src16RnHI,[$Dst16An] */
65110 {
65111 { 0, 0, 0, 0 },
65112 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
65113 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9106 }
65114 },
65115/* and.w${G} $Src16AnHI,[$Dst16An] */
65116 {
65117 { 0, 0, 0, 0 },
65118 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
65119 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9146 }
65120 },
65121/* and.w${G} [$Src16An],[$Dst16An] */
65122 {
65123 { 0, 0, 0, 0 },
65124 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65125 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9166 }
65126 },
65127/* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
65128 {
65129 { 0, 0, 0, 0 },
65130 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65131 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x910800 }
65132 },
65133/* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
65134 {
65135 { 0, 0, 0, 0 },
65136 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65137 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x914800 }
65138 },
65139/* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
65140 {
65141 { 0, 0, 0, 0 },
65142 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65143 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x916800 }
65144 },
65145/* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
65146 {
65147 { 0, 0, 0, 0 },
65148 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65149 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x910c0000 }
65150 },
65151/* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
65152 {
65153 { 0, 0, 0, 0 },
65154 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65155 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x914c0000 }
65156 },
65157/* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
65158 {
65159 { 0, 0, 0, 0 },
65160 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65161 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x916c0000 }
65162 },
65163/* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
65164 {
65165 { 0, 0, 0, 0 },
65166 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65167 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x910a00 }
65168 },
65169/* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
65170 {
65171 { 0, 0, 0, 0 },
65172 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65173 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x914a00 }
65174 },
65175/* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
65176 {
65177 { 0, 0, 0, 0 },
65178 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65179 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x916a00 }
65180 },
65181/* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
65182 {
65183 { 0, 0, 0, 0 },
65184 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65185 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x910e0000 }
65186 },
65187/* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
65188 {
65189 { 0, 0, 0, 0 },
65190 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65191 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x914e0000 }
65192 },
65193/* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
65194 {
65195 { 0, 0, 0, 0 },
65196 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65197 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x916e0000 }
65198 },
65199/* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
65200 {
65201 { 0, 0, 0, 0 },
65202 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65203 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x910b00 }
65204 },
65205/* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
65206 {
65207 { 0, 0, 0, 0 },
65208 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65209 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x914b00 }
65210 },
65211/* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
65212 {
65213 { 0, 0, 0, 0 },
65214 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65215 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x916b00 }
65216 },
65217/* and.w${G} $Src16RnHI,${Dsp-16-u16} */
65218 {
65219 { 0, 0, 0, 0 },
65220 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
65221 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x910f0000 }
65222 },
65223/* and.w${G} $Src16AnHI,${Dsp-16-u16} */
65224 {
65225 { 0, 0, 0, 0 },
65226 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
65227 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x914f0000 }
65228 },
65229/* and.w${G} [$Src16An],${Dsp-16-u16} */
65230 {
65231 { 0, 0, 0, 0 },
65232 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
65233 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x916f0000 }
65234 },
65235/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
65236 {
65237 { 0, 0, 0, 0 },
65238 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65239 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x908000 }
65240 },
65241/* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
65242 {
65243 { 0, 0, 0, 0 },
65244 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
65245 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x90a000 }
65246 },
65247/* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
65248 {
65249 { 0, 0, 0, 0 },
65250 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
65251 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x90b000 }
65252 },
65253/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
65254 {
65255 { 0, 0, 0, 0 },
65256 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65257 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x908400 }
65258 },
65259/* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
65260 {
65261 { 0, 0, 0, 0 },
65262 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
65263 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x90a400 }
65264 },
65265/* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
65266 {
65267 { 0, 0, 0, 0 },
65268 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
65269 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x90b400 }
65270 },
65271/* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
65272 {
65273 { 0, 0, 0, 0 },
65274 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65275 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x908600 }
65276 },
65277/* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
65278 {
65279 { 0, 0, 0, 0 },
65280 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65281 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x90a600 }
65282 },
65283/* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
65284 {
65285 { 0, 0, 0, 0 },
65286 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65287 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x90b600 }
65288 },
65289/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
65290 {
65291 { 0, 0, 0, 0 },
65292 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65293 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x90880000 }
65294 },
65295/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
65296 {
65297 { 0, 0, 0, 0 },
65298 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65299 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x90a80000 }
65300 },
65301/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
65302 {
65303 { 0, 0, 0, 0 },
65304 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65305 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x90b80000 }
65306 },
65307/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
65308 {
65309 { 0, 0, 0, 0 },
65310 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65311 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x908c0000 }
65312 },
65313/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
65314 {
65315 { 0, 0, 0, 0 },
65316 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65317 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x90ac0000 }
65318 },
65319/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
65320 {
65321 { 0, 0, 0, 0 },
65322 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65323 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x90bc0000 }
65324 },
65325/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
65326 {
65327 { 0, 0, 0, 0 },
65328 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65329 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x908a0000 }
65330 },
65331/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
65332 {
65333 { 0, 0, 0, 0 },
65334 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65335 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90aa0000 }
65336 },
65337/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
65338 {
65339 { 0, 0, 0, 0 },
65340 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65341 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90ba0000 }
65342 },
65343/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
65344 {
65345 { 0, 0, 0, 0 },
65346 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65347 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x908e0000 }
65348 },
65349/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
65350 {
65351 { 0, 0, 0, 0 },
65352 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65353 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90ae0000 }
65354 },
65355/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
65356 {
65357 { 0, 0, 0, 0 },
65358 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65359 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90be0000 }
65360 },
65361/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
65362 {
65363 { 0, 0, 0, 0 },
65364 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65365 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x908b0000 }
65366 },
65367/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
65368 {
65369 { 0, 0, 0, 0 },
65370 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65371 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90ab0000 }
65372 },
65373/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
65374 {
65375 { 0, 0, 0, 0 },
65376 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65377 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90bb0000 }
65378 },
65379/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
65380 {
65381 { 0, 0, 0, 0 },
65382 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
65383 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x908f0000 }
65384 },
65385/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
65386 {
65387 { 0, 0, 0, 0 },
65388 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65389 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x90af0000 }
65390 },
65391/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
65392 {
65393 { 0, 0, 0, 0 },
65394 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65395 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x90bf0000 }
65396 },
65397/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
65398 {
65399 { 0, 0, 0, 0 },
65400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65401 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x90c00000 }
65402 },
65403/* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
65404 {
65405 { 0, 0, 0, 0 },
65406 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
65407 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x90e00000 }
65408 },
65409/* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
65410 {
65411 { 0, 0, 0, 0 },
65412 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
65413 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x90f00000 }
65414 },
65415/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
65416 {
65417 { 0, 0, 0, 0 },
65418 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65419 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x90c40000 }
65420 },
65421/* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
65422 {
65423 { 0, 0, 0, 0 },
65424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
65425 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x90e40000 }
65426 },
65427/* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
65428 {
65429 { 0, 0, 0, 0 },
65430 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
65431 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x90f40000 }
65432 },
65433/* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
65434 {
65435 { 0, 0, 0, 0 },
65436 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65437 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x90c60000 }
65438 },
65439/* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
65440 {
65441 { 0, 0, 0, 0 },
65442 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65443 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x90e60000 }
65444 },
65445/* and.b${G} ${Dsp-16-u16},[$Dst16An] */
65446 {
65447 { 0, 0, 0, 0 },
65448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
65449 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x90f60000 }
65450 },
65451/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
65452 {
65453 { 0, 0, 0, 0 },
65454 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65455 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x90c80000 }
65456 },
65457/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
65458 {
65459 { 0, 0, 0, 0 },
65460 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65461 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x90e80000 }
65462 },
65463/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
65464 {
65465 { 0, 0, 0, 0 },
65466 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65467 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x90f80000 }
65468 },
65469/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
65470 {
65471 { 0, 0, 0, 0 },
65472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65473 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x90cc0000 }
65474 },
65475/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
65476 {
65477 { 0, 0, 0, 0 },
65478 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65479 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x90ec0000 }
65480 },
65481/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
65482 {
65483 { 0, 0, 0, 0 },
65484 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65485 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x90fc0000 }
65486 },
65487/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
65488 {
65489 { 0, 0, 0, 0 },
65490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65491 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ca0000 }
65492 },
65493/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
65494 {
65495 { 0, 0, 0, 0 },
65496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65497 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ea0000 }
65498 },
65499/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
65500 {
65501 { 0, 0, 0, 0 },
65502 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65503 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x90fa0000 }
65504 },
65505/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
65506 {
65507 { 0, 0, 0, 0 },
65508 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65509 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ce0000 }
65510 },
65511/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
65512 {
65513 { 0, 0, 0, 0 },
65514 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65515 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ee0000 }
65516 },
65517/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
65518 {
65519 { 0, 0, 0, 0 },
65520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65521 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x90fe0000 }
65522 },
65523/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
65524 {
65525 { 0, 0, 0, 0 },
65526 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65527 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x90cb0000 }
65528 },
65529/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
65530 {
65531 { 0, 0, 0, 0 },
65532 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65533 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x90eb0000 }
65534 },
65535/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
65536 {
65537 { 0, 0, 0, 0 },
65538 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65539 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x90fb0000 }
65540 },
65541/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
65542 {
65543 { 0, 0, 0, 0 },
65544 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
65545 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x90cf0000 }
65546 },
65547/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
65548 {
65549 { 0, 0, 0, 0 },
65550 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
65551 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x90ef0000 }
65552 },
65553/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
65554 {
65555 { 0, 0, 0, 0 },
65556 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
65557 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x90ff0000 }
65558 },
65559/* and.b${G} $Src16RnQI,$Dst16RnQI */
65560 {
65561 { 0, 0, 0, 0 },
65562 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
65563 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9000 }
65564 },
65565/* and.b${G} $Src16AnQI,$Dst16RnQI */
65566 {
65567 { 0, 0, 0, 0 },
65568 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
65569 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9040 }
65570 },
65571/* and.b${G} [$Src16An],$Dst16RnQI */
65572 {
65573 { 0, 0, 0, 0 },
65574 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65575 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9060 }
65576 },
65577/* and.b${G} $Src16RnQI,$Dst16AnQI */
65578 {
65579 { 0, 0, 0, 0 },
65580 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
65581 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9004 }
65582 },
65583/* and.b${G} $Src16AnQI,$Dst16AnQI */
65584 {
65585 { 0, 0, 0, 0 },
65586 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
65587 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9044 }
65588 },
65589/* and.b${G} [$Src16An],$Dst16AnQI */
65590 {
65591 { 0, 0, 0, 0 },
65592 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65593 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9064 }
65594 },
65595/* and.b${G} $Src16RnQI,[$Dst16An] */
65596 {
65597 { 0, 0, 0, 0 },
65598 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
65599 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9006 }
65600 },
65601/* and.b${G} $Src16AnQI,[$Dst16An] */
65602 {
65603 { 0, 0, 0, 0 },
65604 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
65605 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9046 }
65606 },
65607/* and.b${G} [$Src16An],[$Dst16An] */
65608 {
65609 { 0, 0, 0, 0 },
65610 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65611 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9066 }
65612 },
65613/* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
65614 {
65615 { 0, 0, 0, 0 },
65616 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65617 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x900800 }
65618 },
65619/* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
65620 {
65621 { 0, 0, 0, 0 },
65622 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65623 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x904800 }
65624 },
65625/* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
65626 {
65627 { 0, 0, 0, 0 },
65628 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65629 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x906800 }
65630 },
65631/* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
65632 {
65633 { 0, 0, 0, 0 },
65634 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65635 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x900c0000 }
65636 },
65637/* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
65638 {
65639 { 0, 0, 0, 0 },
65640 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65641 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x904c0000 }
65642 },
65643/* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
65644 {
65645 { 0, 0, 0, 0 },
65646 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65647 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x906c0000 }
65648 },
65649/* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
65650 {
65651 { 0, 0, 0, 0 },
65652 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65653 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x900a00 }
65654 },
65655/* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
65656 {
65657 { 0, 0, 0, 0 },
65658 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65659 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x904a00 }
65660 },
65661/* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
65662 {
65663 { 0, 0, 0, 0 },
65664 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65665 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x906a00 }
65666 },
65667/* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
65668 {
65669 { 0, 0, 0, 0 },
65670 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65671 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x900e0000 }
65672 },
65673/* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
65674 {
65675 { 0, 0, 0, 0 },
65676 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65677 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x904e0000 }
65678 },
65679/* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
65680 {
65681 { 0, 0, 0, 0 },
65682 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65683 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x906e0000 }
65684 },
65685/* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
65686 {
65687 { 0, 0, 0, 0 },
65688 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65689 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x900b00 }
65690 },
65691/* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
65692 {
65693 { 0, 0, 0, 0 },
65694 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65695 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x904b00 }
65696 },
65697/* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
65698 {
65699 { 0, 0, 0, 0 },
65700 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65701 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x906b00 }
65702 },
65703/* and.b${G} $Src16RnQI,${Dsp-16-u16} */
65704 {
65705 { 0, 0, 0, 0 },
65706 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
65707 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x900f0000 }
65708 },
65709/* and.b${G} $Src16AnQI,${Dsp-16-u16} */
65710 {
65711 { 0, 0, 0, 0 },
65712 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
65713 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x904f0000 }
65714 },
65715/* and.b${G} [$Src16An],${Dsp-16-u16} */
65716 {
65717 { 0, 0, 0, 0 },
65718 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
65719 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x906f0000 }
65720 },
65721/* and.b${S} #${Imm-8-QI},r0l */
65722 {
65723 { 0, 0, 0, 0 },
65724 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
65725 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9400 }
65726 },
65727/* and.b${S} #${Imm-8-QI},r0h */
65728 {
65729 { 0, 0, 0, 0 },
65730 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
65731 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9300 }
65732 },
65733/* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
65734 {
65735 { 0, 0, 0, 0 },
65736 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65737 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x950000 }
65738 },
65739/* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
65740 {
65741 { 0, 0, 0, 0 },
65742 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65743 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x960000 }
65744 },
65745/* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
65746 {
65747 { 0, 0, 0, 0 },
65748 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
65749 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x97000000 }
65750 },
65751/* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
65752 {
65753 { 0, 0, 0, 0 },
65754 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
65755 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893f0000 }
65756 },
65757/* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
65758 {
65759 { 0, 0, 0, 0 },
65760 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
65761 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81bf0000 }
65762 },
65763/* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
65764 {
65765 { 0, 0, 0, 0 },
65766 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65767 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813f0000 }
65768 },
65769/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
65770 {
65771 { 0, 0, 0, 0 },
65772 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65773 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833f0000 }
65774 },
65775/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
65776 {
65777 { 0, 0, 0, 0 },
65778 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65779 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83bf0000 }
65780 },
65781/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
65782 {
65783 { 0, 0, 0, 0 },
65784 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65785 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ff0000 }
65786 },
65787/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
65788 {
65789 { 0, 0, 0, 0 },
65790 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65791 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853f0000 }
65792 },
65793/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
65794 {
65795 { 0, 0, 0, 0 },
65796 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65797 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85bf0000 }
65798 },
65799/* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
65800 {
65801 { 0, 0, 0, 0 },
65802 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65803 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ff0000 }
65804 },
65805/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
65806 {
65807 { 0, 0, 0, 0 },
65808 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
65809 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ff0000 }
65810 },
65811/* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
65812 {
65813 { 0, 0, 0, 0 },
65814 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65815 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873f0000 }
65816 },
65817/* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
65818 {
65819 { 0, 0, 0, 0 },
65820 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
65821 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87bf0000 }
65822 },
65823/* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
65824 {
65825 { 0, 0, 0, 0 },
65826 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
65827 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883f00 }
65828 },
65829/* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
65830 {
65831 { 0, 0, 0, 0 },
65832 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
65833 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80bf00 }
65834 },
65835/* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
65836 {
65837 { 0, 0, 0, 0 },
65838 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65839 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803f00 }
65840 },
65841/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
65842 {
65843 { 0, 0, 0, 0 },
65844 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65845 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823f0000 }
65846 },
65847/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
65848 {
65849 { 0, 0, 0, 0 },
65850 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65851 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82bf0000 }
65852 },
65853/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
65854 {
65855 { 0, 0, 0, 0 },
65856 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65857 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ff0000 }
65858 },
65859/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
65860 {
65861 { 0, 0, 0, 0 },
65862 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65863 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843f0000 }
65864 },
65865/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
65866 {
65867 { 0, 0, 0, 0 },
65868 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65869 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84bf0000 }
65870 },
65871/* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
65872 {
65873 { 0, 0, 0, 0 },
65874 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65875 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ff0000 }
65876 },
65877/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
65878 {
65879 { 0, 0, 0, 0 },
65880 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
65881 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ff0000 }
65882 },
65883/* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
65884 {
65885 { 0, 0, 0, 0 },
65886 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65887 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863f0000 }
65888 },
65889/* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
65890 {
65891 { 0, 0, 0, 0 },
65892 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
65893 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86bf0000 }
65894 },
65895/* and.w${G} #${Imm-16-HI},$Dst16RnHI */
65896 {
65897 { 0, 0, 0, 0 },
65898 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
65899 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77200000 }
65900 },
65901/* and.w${G} #${Imm-16-HI},$Dst16AnHI */
65902 {
65903 { 0, 0, 0, 0 },
65904 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
65905 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77240000 }
65906 },
65907/* and.w${G} #${Imm-16-HI},[$Dst16An] */
65908 {
65909 { 0, 0, 0, 0 },
65910 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
65911 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77260000 }
65912 },
65913/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
65914 {
65915 { 0, 0, 0, 0 },
65916 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65917 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77280000 }
65918 },
65919/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
65920 {
65921 { 0, 0, 0, 0 },
65922 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65923 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x772a0000 }
65924 },
65925/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
65926 {
65927 { 0, 0, 0, 0 },
65928 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65929 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x772b0000 }
65930 },
65931/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
65932 {
65933 { 0, 0, 0, 0 },
65934 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65935 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x772c0000 }
65936 },
65937/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
65938 {
65939 { 0, 0, 0, 0 },
65940 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65941 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x772e0000 }
65942 },
65943/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
65944 {
65945 { 0, 0, 0, 0 },
65946 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
65947 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x772f0000 }
65948 },
65949/* and.b${G} #${Imm-16-QI},$Dst16RnQI */
65950 {
65951 { 0, 0, 0, 0 },
65952 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
65953 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x762000 }
65954 },
65955/* and.b${G} #${Imm-16-QI},$Dst16AnQI */
65956 {
65957 { 0, 0, 0, 0 },
65958 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
65959 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x762400 }
65960 },
65961/* and.b${G} #${Imm-16-QI},[$Dst16An] */
65962 {
65963 { 0, 0, 0, 0 },
65964 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
65965 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x762600 }
65966 },
65967/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
65968 {
65969 { 0, 0, 0, 0 },
65970 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65971 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76280000 }
65972 },
65973/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
65974 {
65975 { 0, 0, 0, 0 },
65976 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65977 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x762a0000 }
65978 },
65979/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
65980 {
65981 { 0, 0, 0, 0 },
65982 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65983 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x762b0000 }
65984 },
65985/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
65986 {
65987 { 0, 0, 0, 0 },
65988 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65989 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x762c0000 }
65990 },
65991/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
65992 {
65993 { 0, 0, 0, 0 },
65994 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65995 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x762e0000 }
65996 },
65997/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
65998 {
65999 { 0, 0, 0, 0 },
66000 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
66001 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x762f0000 }
66002 },
66003/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
66004 {
66005 { 0, 0, 0, 0 },
66006 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
66007 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
66008 },
66009/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66010 {
66011 { 0, 0, 0, 0 },
66012 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66013 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
66014 },
66015/* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66016 {
66017 { 0, 0, 0, 0 },
66018 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66019 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
66020 },
66021/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
66022 {
66023 { 0, 0, 0, 0 },
66024 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
66025 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
66026 },
66027/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66028 {
66029 { 0, 0, 0, 0 },
66030 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66031 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
66032 },
66033/* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
66034 {
66035 { 0, 0, 0, 0 },
66036 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
66037 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
66038 },
66039/* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
66040 {
66041 { 0, 0, 0, 0 },
66042 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66043 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
66044 },
66045/* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
66046 {
66047 { 0, 0, 0, 0 },
66048 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
66049 & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
66050 },
66051/* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
66052 {
66053 { 0, 0, 0, 0 },
66054 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
66055 & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
66056 },
66057/* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
66058 {
66059 { 0, 0, 0, 0 },
66060 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
66061 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
66062 },
66063/* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
66064 {
66065 { 0, 0, 0, 0 },
66066 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
66067 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
66068 },
66069/* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
66070 {
66071 { 0, 0, 0, 0 },
66072 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
66073 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
66074 },
66075/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
66076 {
66077 { 0, 0, 0, 0 },
66078 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
66079 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
66080 },
66081/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66082 {
66083 { 0, 0, 0, 0 },
66084 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66085 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
66086 },
66087/* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66088 {
66089 { 0, 0, 0, 0 },
66090 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66091 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
66092 },
66093/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
66094 {
66095 { 0, 0, 0, 0 },
66096 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
66097 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
66098 },
66099/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66100 {
66101 { 0, 0, 0, 0 },
66102 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66103 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
66104 },
66105/* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
66106 {
66107 { 0, 0, 0, 0 },
66108 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
66109 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
66110 },
66111/* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
66112 {
66113 { 0, 0, 0, 0 },
66114 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66115 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
66116 },
66117/* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
66118 {
66119 { 0, 0, 0, 0 },
66120 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
66121 & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
66122 },
66123/* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
66124 {
66125 { 0, 0, 0, 0 },
66126 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
66127 & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
66128 },
66129/* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
66130 {
66131 { 0, 0, 0, 0 },
66132 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
66133 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
66134 },
66135/* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
66136 {
66137 { 0, 0, 0, 0 },
66138 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
66139 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
66140 },
66141/* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
66142 {
66143 { 0, 0, 0, 0 },
66144 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
66145 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
66146 },
66147/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
66148 {
66149 { 0, 0, 0, 0 },
66150 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
66151 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
66152 },
66153/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66154 {
66155 { 0, 0, 0, 0 },
66156 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66157 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
66158 },
66159/* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66160 {
66161 { 0, 0, 0, 0 },
66162 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66163 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
66164 },
66165/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
66166 {
66167 { 0, 0, 0, 0 },
66168 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
66169 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
66170 },
66171/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66172 {
66173 { 0, 0, 0, 0 },
66174 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66175 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
66176 },
66177/* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
66178 {
66179 { 0, 0, 0, 0 },
66180 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66181 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
66182 },
66183/* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
66184 {
66185 { 0, 0, 0, 0 },
66186 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
66187 & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
66188 },
66189/* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
66190 {
66191 { 0, 0, 0, 0 },
66192 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
66193 & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
66194 },
66195/* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
66196 {
66197 { 0, 0, 0, 0 },
66198 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
66199 & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
66200 },
66201/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
66202 {
66203 { 0, 0, 0, 0 },
66204 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
66205 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
66206 },
66207/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66208 {
66209 { 0, 0, 0, 0 },
66210 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66211 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
66212 },
66213/* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66214 {
66215 { 0, 0, 0, 0 },
66216 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66217 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
66218 },
66219/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
66220 {
66221 { 0, 0, 0, 0 },
66222 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
66223 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
66224 },
66225/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66226 {
66227 { 0, 0, 0, 0 },
66228 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66229 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
66230 },
66231/* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
66232 {
66233 { 0, 0, 0, 0 },
66234 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66235 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
66236 },
66237/* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
66238 {
66239 { 0, 0, 0, 0 },
66240 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
66241 & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
66242 },
66243/* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
66244 {
66245 { 0, 0, 0, 0 },
66246 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
66247 & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
66248 },
66249/* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
66250 {
66251 { 0, 0, 0, 0 },
66252 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
66253 & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
66254 },
66255/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66256 {
66257 { 0, 0, 0, 0 },
66258 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66259 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980200 }
66260 },
66261/* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
66262 {
66263 { 0, 0, 0, 0 },
66264 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66265 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982200 }
66266 },
66267/* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
66268 {
66269 { 0, 0, 0, 0 },
66270 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66271 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983200 }
66272 },
66273/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66274 {
66275 { 0, 0, 0, 0 },
66276 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66277 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908200 }
66278 },
66279/* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
66280 {
66281 { 0, 0, 0, 0 },
66282 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66283 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a200 }
66284 },
66285/* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
66286 {
66287 { 0, 0, 0, 0 },
66288 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66289 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b200 }
66290 },
66291/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66292 {
66293 { 0, 0, 0, 0 },
66294 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66295 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900200 }
66296 },
66297/* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
66298 {
66299 { 0, 0, 0, 0 },
66300 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66301 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902200 }
66302 },
66303/* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
66304 {
66305 { 0, 0, 0, 0 },
66306 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66307 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903200 }
66308 },
66309/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66310 {
66311 { 0, 0, 0, 0 },
66312 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66313 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92020000 }
66314 },
66315/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66316 {
66317 { 0, 0, 0, 0 },
66318 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66319 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92220000 }
66320 },
66321/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66322 {
66323 { 0, 0, 0, 0 },
66324 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66325 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92320000 }
66326 },
66327/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66328 {
66329 { 0, 0, 0, 0 },
66330 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66331 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94020000 }
66332 },
66333/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66334 {
66335 { 0, 0, 0, 0 },
66336 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66337 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94220000 }
66338 },
66339/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66340 {
66341 { 0, 0, 0, 0 },
66342 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66343 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94320000 }
66344 },
66345/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66346 {
66347 { 0, 0, 0, 0 },
66348 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66349 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96020000 }
66350 },
66351/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66352 {
66353 { 0, 0, 0, 0 },
66354 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66355 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96220000 }
66356 },
66357/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66358 {
66359 { 0, 0, 0, 0 },
66360 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66361 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96320000 }
66362 },
66363/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
66364 {
66365 { 0, 0, 0, 0 },
66366 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66367 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92820000 }
66368 },
66369/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
66370 {
66371 { 0, 0, 0, 0 },
66372 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66373 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a20000 }
66374 },
66375/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
66376 {
66377 { 0, 0, 0, 0 },
66378 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66379 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b20000 }
66380 },
66381/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
66382 {
66383 { 0, 0, 0, 0 },
66384 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66385 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94820000 }
66386 },
66387/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
66388 {
66389 { 0, 0, 0, 0 },
66390 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66391 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a20000 }
66392 },
66393/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
66394 {
66395 { 0, 0, 0, 0 },
66396 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66397 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b20000 }
66398 },
66399/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
66400 {
66401 { 0, 0, 0, 0 },
66402 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66403 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c20000 }
66404 },
66405/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
66406 {
66407 { 0, 0, 0, 0 },
66408 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66409 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e20000 }
66410 },
66411/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
66412 {
66413 { 0, 0, 0, 0 },
66414 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66415 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f20000 }
66416 },
66417/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
66418 {
66419 { 0, 0, 0, 0 },
66420 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66421 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c20000 }
66422 },
66423/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
66424 {
66425 { 0, 0, 0, 0 },
66426 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66427 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e20000 }
66428 },
66429/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
66430 {
66431 { 0, 0, 0, 0 },
66432 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66433 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f20000 }
66434 },
66435/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
66436 {
66437 { 0, 0, 0, 0 },
66438 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
66439 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c20000 }
66440 },
66441/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
66442 {
66443 { 0, 0, 0, 0 },
66444 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
66445 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e20000 }
66446 },
66447/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
66448 {
66449 { 0, 0, 0, 0 },
66450 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
66451 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f20000 }
66452 },
66453/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
66454 {
66455 { 0, 0, 0, 0 },
66456 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
66457 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96820000 }
66458 },
66459/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
66460 {
66461 { 0, 0, 0, 0 },
66462 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
66463 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a20000 }
66464 },
66465/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
66466 {
66467 { 0, 0, 0, 0 },
66468 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
66469 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b20000 }
66470 },
66471/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66472 {
66473 { 0, 0, 0, 0 },
66474 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66475 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8020000 }
66476 },
66477/* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
66478 {
66479 { 0, 0, 0, 0 },
66480 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66481 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8220000 }
66482 },
66483/* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
66484 {
66485 { 0, 0, 0, 0 },
66486 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66487 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8320000 }
66488 },
66489/* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
66490 {
66491 { 0, 0, 0, 0 },
66492 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66493 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8320000 }
66494 },
66495/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66496 {
66497 { 0, 0, 0, 0 },
66498 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66499 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0820000 }
66500 },
66501/* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
66502 {
66503 { 0, 0, 0, 0 },
66504 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66505 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a20000 }
66506 },
66507/* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
66508 {
66509 { 0, 0, 0, 0 },
66510 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66511 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b20000 }
66512 },
66513/* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
66514 {
66515 { 0, 0, 0, 0 },
66516 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66517 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b20000 }
66518 },
66519/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66520 {
66521 { 0, 0, 0, 0 },
66522 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66523 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0020000 }
66524 },
66525/* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
66526 {
66527 { 0, 0, 0, 0 },
66528 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66529 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0220000 }
66530 },
66531/* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
66532 {
66533 { 0, 0, 0, 0 },
66534 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66535 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0320000 }
66536 },
66537/* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
66538 {
66539 { 0, 0, 0, 0 },
66540 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66541 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0320000 }
66542 },
66543/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66544 {
66545 { 0, 0, 0, 0 },
66546 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66547 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2020000 }
66548 },
66549/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66550 {
66551 { 0, 0, 0, 0 },
66552 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66553 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2220000 }
66554 },
66555/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66556 {
66557 { 0, 0, 0, 0 },
66558 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66559 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2320000 }
66560 },
66561/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
66562 {
66563 { 0, 0, 0, 0 },
66564 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66565 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2320000 }
66566 },
66567/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66568 {
66569 { 0, 0, 0, 0 },
66570 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66571 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4020000 }
66572 },
66573/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66574 {
66575 { 0, 0, 0, 0 },
66576 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66577 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4220000 }
66578 },
66579/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66580 {
66581 { 0, 0, 0, 0 },
66582 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66583 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4320000 }
66584 },
66585/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
66586 {
66587 { 0, 0, 0, 0 },
66588 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66589 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4320000 }
66590 },
66591/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66592 {
66593 { 0, 0, 0, 0 },
66594 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66595 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6020000 }
66596 },
66597/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66598 {
66599 { 0, 0, 0, 0 },
66600 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66601 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6220000 }
66602 },
66603/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66604 {
66605 { 0, 0, 0, 0 },
66606 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66607 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6320000 }
66608 },
66609/* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
66610 {
66611 { 0, 0, 0, 0 },
66612 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66613 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6320000 }
66614 },
66615/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
66616 {
66617 { 0, 0, 0, 0 },
66618 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
66619 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2820000 }
66620 },
66621/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
66622 {
66623 { 0, 0, 0, 0 },
66624 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
66625 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a20000 }
66626 },
66627/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
66628 {
66629 { 0, 0, 0, 0 },
66630 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
66631 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b20000 }
66632 },
66633/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
66634 {
66635 { 0, 0, 0, 0 },
66636 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
66637 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b20000 }
66638 },
66639/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
66640 {
66641 { 0, 0, 0, 0 },
66642 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
66643 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4820000 }
66644 },
66645/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
66646 {
66647 { 0, 0, 0, 0 },
66648 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
66649 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a20000 }
66650 },
66651/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
66652 {
66653 { 0, 0, 0, 0 },
66654 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
66655 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b20000 }
66656 },
66657/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
66658 {
66659 { 0, 0, 0, 0 },
66660 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
66661 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b20000 }
66662 },
66663/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
66664 {
66665 { 0, 0, 0, 0 },
66666 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
66667 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c20000 }
66668 },
66669/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
66670 {
66671 { 0, 0, 0, 0 },
66672 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
66673 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e20000 }
66674 },
66675/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
66676 {
66677 { 0, 0, 0, 0 },
66678 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
66679 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f20000 }
66680 },
66681/* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
66682 {
66683 { 0, 0, 0, 0 },
66684 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
66685 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f20000 }
66686 },
66687/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
66688 {
66689 { 0, 0, 0, 0 },
66690 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
66691 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c20000 }
66692 },
66693/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
66694 {
66695 { 0, 0, 0, 0 },
66696 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
66697 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e20000 }
66698 },
66699/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
66700 {
66701 { 0, 0, 0, 0 },
66702 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
66703 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f20000 }
66704 },
66705/* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
66706 {
66707 { 0, 0, 0, 0 },
66708 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
66709 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f20000 }
66710 },
66711/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
66712 {
66713 { 0, 0, 0, 0 },
66714 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
66715 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c20000 }
66716 },
66717/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
66718 {
66719 { 0, 0, 0, 0 },
66720 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
66721 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e20000 }
66722 },
66723/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
66724 {
66725 { 0, 0, 0, 0 },
66726 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
66727 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f20000 }
66728 },
66729/* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
66730 {
66731 { 0, 0, 0, 0 },
66732 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
66733 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f20000 }
66734 },
66735/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
66736 {
66737 { 0, 0, 0, 0 },
66738 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
66739 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6820000 }
66740 },
66741/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
66742 {
66743 { 0, 0, 0, 0 },
66744 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
66745 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a20000 }
66746 },
66747/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
66748 {
66749 { 0, 0, 0, 0 },
66750 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
66751 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b20000 }
66752 },
66753/* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
66754 {
66755 { 0, 0, 0, 0 },
66756 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
66757 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b20000 }
66758 },
66759/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66760 {
66761 { 0, 0, 0, 0 },
66762 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66763 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8020000 }
66764 },
66765/* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
66766 {
66767 { 0, 0, 0, 0 },
66768 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66769 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8220000 }
66770 },
66771/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66772 {
66773 { 0, 0, 0, 0 },
66774 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66775 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0820000 }
66776 },
66777/* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
66778 {
66779 { 0, 0, 0, 0 },
66780 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66781 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a20000 }
66782 },
66783/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66784 {
66785 { 0, 0, 0, 0 },
66786 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66787 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0020000 }
66788 },
66789/* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
66790 {
66791 { 0, 0, 0, 0 },
66792 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66793 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0220000 }
66794 },
66795/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
66796 {
66797 { 0, 0, 0, 0 },
66798 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66799 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2020000 }
66800 },
66801/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
66802 {
66803 { 0, 0, 0, 0 },
66804 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66805 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2220000 }
66806 },
66807/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
66808 {
66809 { 0, 0, 0, 0 },
66810 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66811 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4020000 }
66812 },
66813/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
66814 {
66815 { 0, 0, 0, 0 },
66816 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66817 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4220000 }
66818 },
66819/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
66820 {
66821 { 0, 0, 0, 0 },
66822 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66823 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6020000 }
66824 },
66825/* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
66826 {
66827 { 0, 0, 0, 0 },
66828 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66829 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6220000 }
66830 },
66831/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
66832 {
66833 { 0, 0, 0, 0 },
66834 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
66835 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2820000 }
66836 },
66837/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
66838 {
66839 { 0, 0, 0, 0 },
66840 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
66841 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a20000 }
66842 },
66843/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
66844 {
66845 { 0, 0, 0, 0 },
66846 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
66847 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4820000 }
66848 },
66849/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
66850 {
66851 { 0, 0, 0, 0 },
66852 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
66853 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a20000 }
66854 },
66855/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
66856 {
66857 { 0, 0, 0, 0 },
66858 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
66859 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c20000 }
66860 },
66861/* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
66862 {
66863 { 0, 0, 0, 0 },
66864 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
66865 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e20000 }
66866 },
66867/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
66868 {
66869 { 0, 0, 0, 0 },
66870 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
66871 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c20000 }
66872 },
66873/* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
66874 {
66875 { 0, 0, 0, 0 },
66876 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
66877 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e20000 }
66878 },
66879/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
66880 {
66881 { 0, 0, 0, 0 },
66882 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
66883 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c20000 }
66884 },
66885/* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
66886 {
66887 { 0, 0, 0, 0 },
66888 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
66889 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e20000 }
66890 },
66891/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
66892 {
66893 { 0, 0, 0, 0 },
66894 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
66895 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6820000 }
66896 },
66897/* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
66898 {
66899 { 0, 0, 0, 0 },
66900 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
66901 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a20000 }
66902 },
66903/* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
66904 {
66905 { 0, 0, 0, 0 },
66906 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66907 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc802 }
66908 },
66909/* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
66910 {
66911 { 0, 0, 0, 0 },
66912 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66913 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8822 }
66914 },
66915/* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66916 {
66917 { 0, 0, 0, 0 },
66918 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66919 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8802 }
66920 },
66921/* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
66922 {
66923 { 0, 0, 0, 0 },
66924 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66925 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc082 }
66926 },
66927/* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
66928 {
66929 { 0, 0, 0, 0 },
66930 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66931 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a2 }
66932 },
66933/* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66934 {
66935 { 0, 0, 0, 0 },
66936 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66937 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8082 }
66938 },
66939/* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
66940 {
66941 { 0, 0, 0, 0 },
66942 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66943 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc002 }
66944 },
66945/* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
66946 {
66947 { 0, 0, 0, 0 },
66948 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66949 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8022 }
66950 },
66951/* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66952 {
66953 { 0, 0, 0, 0 },
66954 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66955 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8002 }
66956 },
66957/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
66958 {
66959 { 0, 0, 0, 0 },
66960 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66961 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20200 }
66962 },
66963/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
66964 {
66965 { 0, 0, 0, 0 },
66966 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66967 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822200 }
66968 },
66969/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
66970 {
66971 { 0, 0, 0, 0 },
66972 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66973 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820200 }
66974 },
66975/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
66976 {
66977 { 0, 0, 0, 0 },
66978 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66979 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4020000 }
66980 },
66981/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
66982 {
66983 { 0, 0, 0, 0 },
66984 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66985 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84220000 }
66986 },
66987/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
66988 {
66989 { 0, 0, 0, 0 },
66990 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66991 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84020000 }
66992 },
66993/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
66994 {
66995 { 0, 0, 0, 0 },
66996 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66997 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6020000 }
66998 },
66999/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
67000 {
67001 { 0, 0, 0, 0 },
67002 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67003 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86220000 }
67004 },
67005/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
67006 {
67007 { 0, 0, 0, 0 },
67008 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67009 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86020000 }
67010 },
67011/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
67012 {
67013 { 0, 0, 0, 0 },
67014 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67015 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28200 }
67016 },
67017/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
67018 {
67019 { 0, 0, 0, 0 },
67020 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67021 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a200 }
67022 },
67023/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
67024 {
67025 { 0, 0, 0, 0 },
67026 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67027 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828200 }
67028 },
67029/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
67030 {
67031 { 0, 0, 0, 0 },
67032 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67033 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4820000 }
67034 },
67035/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
67036 {
67037 { 0, 0, 0, 0 },
67038 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67039 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a20000 }
67040 },
67041/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
67042 {
67043 { 0, 0, 0, 0 },
67044 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67045 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84820000 }
67046 },
67047/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
67048 {
67049 { 0, 0, 0, 0 },
67050 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67051 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c200 }
67052 },
67053/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
67054 {
67055 { 0, 0, 0, 0 },
67056 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67057 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e200 }
67058 },
67059/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
67060 {
67061 { 0, 0, 0, 0 },
67062 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67063 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c200 }
67064 },
67065/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
67066 {
67067 { 0, 0, 0, 0 },
67068 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67069 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c20000 }
67070 },
67071/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
67072 {
67073 { 0, 0, 0, 0 },
67074 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67075 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e20000 }
67076 },
67077/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
67078 {
67079 { 0, 0, 0, 0 },
67080 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67081 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c20000 }
67082 },
67083/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
67084 {
67085 { 0, 0, 0, 0 },
67086 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
67087 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c20000 }
67088 },
67089/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
67090 {
67091 { 0, 0, 0, 0 },
67092 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
67093 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e20000 }
67094 },
67095/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
67096 {
67097 { 0, 0, 0, 0 },
67098 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
67099 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c20000 }
67100 },
67101/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
67102 {
67103 { 0, 0, 0, 0 },
67104 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
67105 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6820000 }
67106 },
67107/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
67108 {
67109 { 0, 0, 0, 0 },
67110 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
67111 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a20000 }
67112 },
67113/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
67114 {
67115 { 0, 0, 0, 0 },
67116 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
67117 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86820000 }
67118 },
67119/* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
67120 {
67121 { 0, 0, 0, 0 },
67122 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67123 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x881100 }
67124 },
67125/* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
67126 {
67127 { 0, 0, 0, 0 },
67128 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67129 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x809100 }
67130 },
67131/* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
67132 {
67133 { 0, 0, 0, 0 },
67134 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67135 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x801100 }
67136 },
67137/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
67138 {
67139 { 0, 0, 0, 0 },
67140 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67141 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82110000 }
67142 },
67143/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
67144 {
67145 { 0, 0, 0, 0 },
67146 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67147 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82910000 }
67148 },
67149/* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
67150 {
67151 { 0, 0, 0, 0 },
67152 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67153 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82d10000 }
67154 },
67155/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
67156 {
67157 { 0, 0, 0, 0 },
67158 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67159 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84110000 }
67160 },
67161/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
67162 {
67163 { 0, 0, 0, 0 },
67164 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67165 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84910000 }
67166 },
67167/* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
67168 {
67169 { 0, 0, 0, 0 },
67170 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67171 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84d10000 }
67172 },
67173/* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
67174 {
67175 { 0, 0, 0, 0 },
67176 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
67177 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86d10000 }
67178 },
67179/* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
67180 {
67181 { 0, 0, 0, 0 },
67182 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67183 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86110000 }
67184 },
67185/* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
67186 {
67187 { 0, 0, 0, 0 },
67188 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
67189 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86910000 }
67190 },
67191/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
67192 {
67193 { 0, 0, 0, 0 },
67194 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67195 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990000 }
67196 },
67197/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
67198 {
67199 { 0, 0, 0, 0 },
67200 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67201 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992000 }
67202 },
67203/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
67204 {
67205 { 0, 0, 0, 0 },
67206 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67207 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993000 }
67208 },
67209/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
67210 {
67211 { 0, 0, 0, 0 },
67212 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67213 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918000 }
67214 },
67215/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
67216 {
67217 { 0, 0, 0, 0 },
67218 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67219 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a000 }
67220 },
67221/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
67222 {
67223 { 0, 0, 0, 0 },
67224 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67225 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b000 }
67226 },
67227/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
67228 {
67229 { 0, 0, 0, 0 },
67230 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67231 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910000 }
67232 },
67233/* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
67234 {
67235 { 0, 0, 0, 0 },
67236 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67237 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912000 }
67238 },
67239/* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
67240 {
67241 { 0, 0, 0, 0 },
67242 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67243 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913000 }
67244 },
67245/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
67246 {
67247 { 0, 0, 0, 0 },
67248 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67249 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930000 }
67250 },
67251/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
67252 {
67253 { 0, 0, 0, 0 },
67254 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67255 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932000 }
67256 },
67257/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
67258 {
67259 { 0, 0, 0, 0 },
67260 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67261 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933000 }
67262 },
67263/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
67264 {
67265 { 0, 0, 0, 0 },
67266 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67267 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950000 }
67268 },
67269/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
67270 {
67271 { 0, 0, 0, 0 },
67272 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67273 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952000 }
67274 },
67275/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
67276 {
67277 { 0, 0, 0, 0 },
67278 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67279 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953000 }
67280 },
67281/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
67282 {
67283 { 0, 0, 0, 0 },
67284 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67285 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970000 }
67286 },
67287/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
67288 {
67289 { 0, 0, 0, 0 },
67290 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67291 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972000 }
67292 },
67293/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
67294 {
67295 { 0, 0, 0, 0 },
67296 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67297 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973000 }
67298 },
67299/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
67300 {
67301 { 0, 0, 0, 0 },
67302 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67303 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938000 }
67304 },
67305/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
67306 {
67307 { 0, 0, 0, 0 },
67308 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67309 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a000 }
67310 },
67311/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
67312 {
67313 { 0, 0, 0, 0 },
67314 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67315 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b000 }
67316 },
67317/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
67318 {
67319 { 0, 0, 0, 0 },
67320 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67321 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958000 }
67322 },
67323/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
67324 {
67325 { 0, 0, 0, 0 },
67326 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67327 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a000 }
67328 },
67329/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
67330 {
67331 { 0, 0, 0, 0 },
67332 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67333 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b000 }
67334 },
67335/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
67336 {
67337 { 0, 0, 0, 0 },
67338 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67339 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c000 }
67340 },
67341/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
67342 {
67343 { 0, 0, 0, 0 },
67344 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67345 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e000 }
67346 },
67347/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
67348 {
67349 { 0, 0, 0, 0 },
67350 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67351 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f000 }
67352 },
67353/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
67354 {
67355 { 0, 0, 0, 0 },
67356 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67357 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c000 }
67358 },
67359/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
67360 {
67361 { 0, 0, 0, 0 },
67362 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67363 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e000 }
67364 },
67365/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
67366 {
67367 { 0, 0, 0, 0 },
67368 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67369 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f000 }
67370 },
67371/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
67372 {
67373 { 0, 0, 0, 0 },
67374 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
67375 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c000 }
67376 },
67377/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
67378 {
67379 { 0, 0, 0, 0 },
67380 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67381 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e000 }
67382 },
67383/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
67384 {
67385 { 0, 0, 0, 0 },
67386 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67387 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f000 }
67388 },
67389/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
67390 {
67391 { 0, 0, 0, 0 },
67392 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
67393 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978000 }
67394 },
67395/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
67396 {
67397 { 0, 0, 0, 0 },
67398 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67399 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a000 }
67400 },
67401/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
67402 {
67403 { 0, 0, 0, 0 },
67404 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67405 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b000 }
67406 },
67407/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
67408 {
67409 { 0, 0, 0, 0 },
67410 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67411 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90000 }
67412 },
67413/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
67414 {
67415 { 0, 0, 0, 0 },
67416 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67417 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92000 }
67418 },
67419/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
67420 {
67421 { 0, 0, 0, 0 },
67422 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67423 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93000 }
67424 },
67425/* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
67426 {
67427 { 0, 0, 0, 0 },
67428 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
67429 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93000 }
67430 },
67431/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
67432 {
67433 { 0, 0, 0, 0 },
67434 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67435 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18000 }
67436 },
67437/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
67438 {
67439 { 0, 0, 0, 0 },
67440 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67441 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a000 }
67442 },
67443/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
67444 {
67445 { 0, 0, 0, 0 },
67446 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67447 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b000 }
67448 },
67449/* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
67450 {
67451 { 0, 0, 0, 0 },
67452 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
67453 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b000 }
67454 },
67455/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
67456 {
67457 { 0, 0, 0, 0 },
67458 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67459 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10000 }
67460 },
67461/* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
67462 {
67463 { 0, 0, 0, 0 },
67464 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67465 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12000 }
67466 },
67467/* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
67468 {
67469 { 0, 0, 0, 0 },
67470 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67471 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13000 }
67472 },
67473/* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
67474 {
67475 { 0, 0, 0, 0 },
67476 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67477 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13000 }
67478 },
67479/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
67480 {
67481 { 0, 0, 0, 0 },
67482 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67483 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30000 }
67484 },
67485/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
67486 {
67487 { 0, 0, 0, 0 },
67488 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67489 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32000 }
67490 },
67491/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
67492 {
67493 { 0, 0, 0, 0 },
67494 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67495 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33000 }
67496 },
67497/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
67498 {
67499 { 0, 0, 0, 0 },
67500 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67501 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33000 }
67502 },
67503/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
67504 {
67505 { 0, 0, 0, 0 },
67506 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67507 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50000 }
67508 },
67509/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
67510 {
67511 { 0, 0, 0, 0 },
67512 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67513 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52000 }
67514 },
67515/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
67516 {
67517 { 0, 0, 0, 0 },
67518 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67519 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53000 }
67520 },
67521/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
67522 {
67523 { 0, 0, 0, 0 },
67524 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67525 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53000 }
67526 },
67527/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
67528 {
67529 { 0, 0, 0, 0 },
67530 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67531 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70000 }
67532 },
67533/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
67534 {
67535 { 0, 0, 0, 0 },
67536 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67537 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72000 }
67538 },
67539/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
67540 {
67541 { 0, 0, 0, 0 },
67542 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67543 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73000 }
67544 },
67545/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
67546 {
67547 { 0, 0, 0, 0 },
67548 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67549 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73000 }
67550 },
67551/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
67552 {
67553 { 0, 0, 0, 0 },
67554 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67555 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38000 }
67556 },
67557/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
67558 {
67559 { 0, 0, 0, 0 },
67560 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67561 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a000 }
67562 },
67563/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
67564 {
67565 { 0, 0, 0, 0 },
67566 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67567 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b000 }
67568 },
67569/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
67570 {
67571 { 0, 0, 0, 0 },
67572 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67573 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b000 }
67574 },
67575/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
67576 {
67577 { 0, 0, 0, 0 },
67578 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67579 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58000 }
67580 },
67581/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
67582 {
67583 { 0, 0, 0, 0 },
67584 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67585 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a000 }
67586 },
67587/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
67588 {
67589 { 0, 0, 0, 0 },
67590 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67591 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b000 }
67592 },
67593/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
67594 {
67595 { 0, 0, 0, 0 },
67596 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67597 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b000 }
67598 },
67599/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
67600 {
67601 { 0, 0, 0, 0 },
67602 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67603 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c000 }
67604 },
67605/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
67606 {
67607 { 0, 0, 0, 0 },
67608 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67609 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e000 }
67610 },
67611/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
67612 {
67613 { 0, 0, 0, 0 },
67614 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67615 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f000 }
67616 },
67617/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
67618 {
67619 { 0, 0, 0, 0 },
67620 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67621 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f000 }
67622 },
67623/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
67624 {
67625 { 0, 0, 0, 0 },
67626 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67627 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c000 }
67628 },
67629/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
67630 {
67631 { 0, 0, 0, 0 },
67632 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67633 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e000 }
67634 },
67635/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
67636 {
67637 { 0, 0, 0, 0 },
67638 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67639 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f000 }
67640 },
67641/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
67642 {
67643 { 0, 0, 0, 0 },
67644 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67645 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f000 }
67646 },
67647/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
67648 {
67649 { 0, 0, 0, 0 },
67650 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
67651 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c000 }
67652 },
67653/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
67654 {
67655 { 0, 0, 0, 0 },
67656 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
67657 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e000 }
67658 },
67659/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
67660 {
67661 { 0, 0, 0, 0 },
67662 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
67663 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f000 }
67664 },
67665/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
67666 {
67667 { 0, 0, 0, 0 },
67668 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
67669 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f000 }
67670 },
67671/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
67672 {
67673 { 0, 0, 0, 0 },
67674 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
67675 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78000 }
67676 },
67677/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
67678 {
67679 { 0, 0, 0, 0 },
67680 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
67681 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a000 }
67682 },
67683/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
67684 {
67685 { 0, 0, 0, 0 },
67686 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
67687 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b000 }
67688 },
67689/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
67690 {
67691 { 0, 0, 0, 0 },
67692 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
67693 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b000 }
67694 },
67695/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
67696 {
67697 { 0, 0, 0, 0 },
67698 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67699 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90000 }
67700 },
67701/* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
67702 {
67703 { 0, 0, 0, 0 },
67704 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
67705 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92000 }
67706 },
67707/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
67708 {
67709 { 0, 0, 0, 0 },
67710 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67711 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18000 }
67712 },
67713/* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
67714 {
67715 { 0, 0, 0, 0 },
67716 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
67717 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a000 }
67718 },
67719/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
67720 {
67721 { 0, 0, 0, 0 },
67722 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67723 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10000 }
67724 },
67725/* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
67726 {
67727 { 0, 0, 0, 0 },
67728 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67729 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12000 }
67730 },
67731/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
67732 {
67733 { 0, 0, 0, 0 },
67734 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67735 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30000 }
67736 },
67737/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
67738 {
67739 { 0, 0, 0, 0 },
67740 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67741 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32000 }
67742 },
67743/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
67744 {
67745 { 0, 0, 0, 0 },
67746 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67747 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50000 }
67748 },
67749/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
67750 {
67751 { 0, 0, 0, 0 },
67752 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67753 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52000 }
67754 },
67755/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
67756 {
67757 { 0, 0, 0, 0 },
67758 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67759 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70000 }
67760 },
67761/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
67762 {
67763 { 0, 0, 0, 0 },
67764 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67765 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72000 }
67766 },
67767/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
67768 {
67769 { 0, 0, 0, 0 },
67770 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
67771 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38000 }
67772 },
67773/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
67774 {
67775 { 0, 0, 0, 0 },
67776 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
67777 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a000 }
67778 },
67779/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
67780 {
67781 { 0, 0, 0, 0 },
67782 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
67783 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58000 }
67784 },
67785/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
67786 {
67787 { 0, 0, 0, 0 },
67788 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
67789 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a000 }
67790 },
67791/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
67792 {
67793 { 0, 0, 0, 0 },
67794 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
67795 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c000 }
67796 },
67797/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
67798 {
67799 { 0, 0, 0, 0 },
67800 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
67801 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e000 }
67802 },
67803/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
67804 {
67805 { 0, 0, 0, 0 },
67806 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
67807 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c000 }
67808 },
67809/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
67810 {
67811 { 0, 0, 0, 0 },
67812 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
67813 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e000 }
67814 },
67815/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
67816 {
67817 { 0, 0, 0, 0 },
67818 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
67819 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c000 }
67820 },
67821/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
67822 {
67823 { 0, 0, 0, 0 },
67824 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
67825 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e000 }
67826 },
67827/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
67828 {
67829 { 0, 0, 0, 0 },
67830 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
67831 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78000 }
67832 },
67833/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
67834 {
67835 { 0, 0, 0, 0 },
67836 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
67837 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a000 }
67838 },
67839/* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
67840 {
67841 { 0, 0, 0, 0 },
67842 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
67843 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c900 }
67844 },
67845/* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
67846 {
67847 { 0, 0, 0, 0 },
67848 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
67849 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18920 }
67850 },
67851/* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
67852 {
67853 { 0, 0, 0, 0 },
67854 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67855 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18900 }
67856 },
67857/* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
67858 {
67859 { 0, 0, 0, 0 },
67860 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
67861 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c180 }
67862 },
67863/* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
67864 {
67865 { 0, 0, 0, 0 },
67866 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
67867 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a0 }
67868 },
67869/* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
67870 {
67871 { 0, 0, 0, 0 },
67872 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67873 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18180 }
67874 },
67875/* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
67876 {
67877 { 0, 0, 0, 0 },
67878 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67879 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c100 }
67880 },
67881/* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
67882 {
67883 { 0, 0, 0, 0 },
67884 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67885 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18120 }
67886 },
67887/* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
67888 {
67889 { 0, 0, 0, 0 },
67890 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67891 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18100 }
67892 },
67893/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
67894 {
67895 { 0, 0, 0, 0 },
67896 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67897 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30000 }
67898 },
67899/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
67900 {
67901 { 0, 0, 0, 0 },
67902 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67903 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832000 }
67904 },
67905/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
67906 {
67907 { 0, 0, 0, 0 },
67908 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67909 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830000 }
67910 },
67911/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
67912 {
67913 { 0, 0, 0, 0 },
67914 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67915 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50000 }
67916 },
67917/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
67918 {
67919 { 0, 0, 0, 0 },
67920 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67921 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852000 }
67922 },
67923/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
67924 {
67925 { 0, 0, 0, 0 },
67926 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67927 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850000 }
67928 },
67929/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
67930 {
67931 { 0, 0, 0, 0 },
67932 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67933 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70000 }
67934 },
67935/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
67936 {
67937 { 0, 0, 0, 0 },
67938 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67939 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872000 }
67940 },
67941/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
67942 {
67943 { 0, 0, 0, 0 },
67944 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67945 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870000 }
67946 },
67947/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
67948 {
67949 { 0, 0, 0, 0 },
67950 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
67951 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38000 }
67952 },
67953/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
67954 {
67955 { 0, 0, 0, 0 },
67956 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
67957 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a000 }
67958 },
67959/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
67960 {
67961 { 0, 0, 0, 0 },
67962 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
67963 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838000 }
67964 },
67965/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
67966 {
67967 { 0, 0, 0, 0 },
67968 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
67969 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58000 }
67970 },
67971/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
67972 {
67973 { 0, 0, 0, 0 },
67974 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
67975 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a000 }
67976 },
67977/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
67978 {
67979 { 0, 0, 0, 0 },
67980 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
67981 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858000 }
67982 },
67983/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
67984 {
67985 { 0, 0, 0, 0 },
67986 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
67987 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c000 }
67988 },
67989/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
67990 {
67991 { 0, 0, 0, 0 },
67992 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
67993 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e000 }
67994 },
67995/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
67996 {
67997 { 0, 0, 0, 0 },
67998 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
67999 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c000 }
68000 },
68001/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
68002 {
68003 { 0, 0, 0, 0 },
68004 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68005 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c000 }
68006 },
68007/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
68008 {
68009 { 0, 0, 0, 0 },
68010 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68011 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e000 }
68012 },
68013/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
68014 {
68015 { 0, 0, 0, 0 },
68016 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68017 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c000 }
68018 },
68019/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
68020 {
68021 { 0, 0, 0, 0 },
68022 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
68023 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c000 }
68024 },
68025/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
68026 {
68027 { 0, 0, 0, 0 },
68028 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
68029 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e000 }
68030 },
68031/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
68032 {
68033 { 0, 0, 0, 0 },
68034 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
68035 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c000 }
68036 },
68037/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
68038 {
68039 { 0, 0, 0, 0 },
68040 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
68041 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78000 }
68042 },
68043/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
68044 {
68045 { 0, 0, 0, 0 },
68046 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
68047 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a000 }
68048 },
68049/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
68050 {
68051 { 0, 0, 0, 0 },
68052 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
68053 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878000 }
68054 },
68055/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68056 {
68057 { 0, 0, 0, 0 },
68058 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68059 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980000 }
68060 },
68061/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
68062 {
68063 { 0, 0, 0, 0 },
68064 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68065 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982000 }
68066 },
68067/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
68068 {
68069 { 0, 0, 0, 0 },
68070 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68071 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983000 }
68072 },
68073/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68074 {
68075 { 0, 0, 0, 0 },
68076 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68077 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908000 }
68078 },
68079/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
68080 {
68081 { 0, 0, 0, 0 },
68082 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68083 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a000 }
68084 },
68085/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
68086 {
68087 { 0, 0, 0, 0 },
68088 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68089 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b000 }
68090 },
68091/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68092 {
68093 { 0, 0, 0, 0 },
68094 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68095 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900000 }
68096 },
68097/* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
68098 {
68099 { 0, 0, 0, 0 },
68100 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68101 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902000 }
68102 },
68103/* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
68104 {
68105 { 0, 0, 0, 0 },
68106 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68107 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903000 }
68108 },
68109/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
68110 {
68111 { 0, 0, 0, 0 },
68112 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68113 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920000 }
68114 },
68115/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
68116 {
68117 { 0, 0, 0, 0 },
68118 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68119 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922000 }
68120 },
68121/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
68122 {
68123 { 0, 0, 0, 0 },
68124 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68125 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923000 }
68126 },
68127/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
68128 {
68129 { 0, 0, 0, 0 },
68130 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68131 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940000 }
68132 },
68133/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
68134 {
68135 { 0, 0, 0, 0 },
68136 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68137 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942000 }
68138 },
68139/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
68140 {
68141 { 0, 0, 0, 0 },
68142 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68143 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943000 }
68144 },
68145/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
68146 {
68147 { 0, 0, 0, 0 },
68148 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68149 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960000 }
68150 },
68151/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
68152 {
68153 { 0, 0, 0, 0 },
68154 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68155 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962000 }
68156 },
68157/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
68158 {
68159 { 0, 0, 0, 0 },
68160 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68161 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963000 }
68162 },
68163/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
68164 {
68165 { 0, 0, 0, 0 },
68166 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68167 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928000 }
68168 },
68169/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
68170 {
68171 { 0, 0, 0, 0 },
68172 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68173 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a000 }
68174 },
68175/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
68176 {
68177 { 0, 0, 0, 0 },
68178 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68179 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b000 }
68180 },
68181/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
68182 {
68183 { 0, 0, 0, 0 },
68184 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68185 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948000 }
68186 },
68187/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
68188 {
68189 { 0, 0, 0, 0 },
68190 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68191 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a000 }
68192 },
68193/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
68194 {
68195 { 0, 0, 0, 0 },
68196 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68197 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b000 }
68198 },
68199/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
68200 {
68201 { 0, 0, 0, 0 },
68202 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68203 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c000 }
68204 },
68205/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
68206 {
68207 { 0, 0, 0, 0 },
68208 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68209 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e000 }
68210 },
68211/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
68212 {
68213 { 0, 0, 0, 0 },
68214 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68215 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f000 }
68216 },
68217/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
68218 {
68219 { 0, 0, 0, 0 },
68220 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68221 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c000 }
68222 },
68223/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
68224 {
68225 { 0, 0, 0, 0 },
68226 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68227 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e000 }
68228 },
68229/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
68230 {
68231 { 0, 0, 0, 0 },
68232 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68233 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f000 }
68234 },
68235/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
68236 {
68237 { 0, 0, 0, 0 },
68238 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
68239 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c000 }
68240 },
68241/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
68242 {
68243 { 0, 0, 0, 0 },
68244 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
68245 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e000 }
68246 },
68247/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
68248 {
68249 { 0, 0, 0, 0 },
68250 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
68251 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f000 }
68252 },
68253/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
68254 {
68255 { 0, 0, 0, 0 },
68256 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
68257 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968000 }
68258 },
68259/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
68260 {
68261 { 0, 0, 0, 0 },
68262 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
68263 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a000 }
68264 },
68265/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
68266 {
68267 { 0, 0, 0, 0 },
68268 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
68269 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b000 }
68270 },
68271/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68272 {
68273 { 0, 0, 0, 0 },
68274 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68275 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80000 }
68276 },
68277/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
68278 {
68279 { 0, 0, 0, 0 },
68280 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68281 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82000 }
68282 },
68283/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
68284 {
68285 { 0, 0, 0, 0 },
68286 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68287 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83000 }
68288 },
68289/* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
68290 {
68291 { 0, 0, 0, 0 },
68292 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
68293 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83000 }
68294 },
68295/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68296 {
68297 { 0, 0, 0, 0 },
68298 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68299 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08000 }
68300 },
68301/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
68302 {
68303 { 0, 0, 0, 0 },
68304 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68305 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a000 }
68306 },
68307/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
68308 {
68309 { 0, 0, 0, 0 },
68310 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68311 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b000 }
68312 },
68313/* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
68314 {
68315 { 0, 0, 0, 0 },
68316 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
68317 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b000 }
68318 },
68319/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68320 {
68321 { 0, 0, 0, 0 },
68322 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68323 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00000 }
68324 },
68325/* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
68326 {
68327 { 0, 0, 0, 0 },
68328 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68329 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02000 }
68330 },
68331/* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
68332 {
68333 { 0, 0, 0, 0 },
68334 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68335 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03000 }
68336 },
68337/* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
68338 {
68339 { 0, 0, 0, 0 },
68340 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68341 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03000 }
68342 },
68343/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
68344 {
68345 { 0, 0, 0, 0 },
68346 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68347 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20000 }
68348 },
68349/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
68350 {
68351 { 0, 0, 0, 0 },
68352 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68353 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22000 }
68354 },
68355/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
68356 {
68357 { 0, 0, 0, 0 },
68358 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68359 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23000 }
68360 },
68361/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
68362 {
68363 { 0, 0, 0, 0 },
68364 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68365 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23000 }
68366 },
68367/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
68368 {
68369 { 0, 0, 0, 0 },
68370 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68371 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40000 }
68372 },
68373/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
68374 {
68375 { 0, 0, 0, 0 },
68376 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68377 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42000 }
68378 },
68379/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
68380 {
68381 { 0, 0, 0, 0 },
68382 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68383 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43000 }
68384 },
68385/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
68386 {
68387 { 0, 0, 0, 0 },
68388 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68389 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43000 }
68390 },
68391/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
68392 {
68393 { 0, 0, 0, 0 },
68394 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68395 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60000 }
68396 },
68397/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
68398 {
68399 { 0, 0, 0, 0 },
68400 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68401 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62000 }
68402 },
68403/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
68404 {
68405 { 0, 0, 0, 0 },
68406 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68407 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63000 }
68408 },
68409/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
68410 {
68411 { 0, 0, 0, 0 },
68412 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68413 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63000 }
68414 },
68415/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
68416 {
68417 { 0, 0, 0, 0 },
68418 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68419 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28000 }
68420 },
68421/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
68422 {
68423 { 0, 0, 0, 0 },
68424 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68425 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a000 }
68426 },
68427/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
68428 {
68429 { 0, 0, 0, 0 },
68430 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68431 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b000 }
68432 },
68433/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
68434 {
68435 { 0, 0, 0, 0 },
68436 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68437 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b000 }
68438 },
68439/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
68440 {
68441 { 0, 0, 0, 0 },
68442 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68443 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48000 }
68444 },
68445/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
68446 {
68447 { 0, 0, 0, 0 },
68448 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68449 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a000 }
68450 },
68451/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
68452 {
68453 { 0, 0, 0, 0 },
68454 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68455 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b000 }
68456 },
68457/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
68458 {
68459 { 0, 0, 0, 0 },
68460 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68461 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b000 }
68462 },
68463/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
68464 {
68465 { 0, 0, 0, 0 },
68466 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68467 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c000 }
68468 },
68469/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
68470 {
68471 { 0, 0, 0, 0 },
68472 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68473 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e000 }
68474 },
68475/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
68476 {
68477 { 0, 0, 0, 0 },
68478 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68479 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f000 }
68480 },
68481/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
68482 {
68483 { 0, 0, 0, 0 },
68484 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68485 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f000 }
68486 },
68487/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
68488 {
68489 { 0, 0, 0, 0 },
68490 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68491 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c000 }
68492 },
68493/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
68494 {
68495 { 0, 0, 0, 0 },
68496 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68497 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e000 }
68498 },
68499/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
68500 {
68501 { 0, 0, 0, 0 },
68502 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68503 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f000 }
68504 },
68505/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
68506 {
68507 { 0, 0, 0, 0 },
68508 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68509 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f000 }
68510 },
68511/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
68512 {
68513 { 0, 0, 0, 0 },
68514 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
68515 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c000 }
68516 },
68517/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
68518 {
68519 { 0, 0, 0, 0 },
68520 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68521 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e000 }
68522 },
68523/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
68524 {
68525 { 0, 0, 0, 0 },
68526 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68527 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f000 }
68528 },
68529/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
68530 {
68531 { 0, 0, 0, 0 },
68532 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
68533 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f000 }
68534 },
68535/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
68536 {
68537 { 0, 0, 0, 0 },
68538 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
68539 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68000 }
68540 },
68541/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
68542 {
68543 { 0, 0, 0, 0 },
68544 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68545 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a000 }
68546 },
68547/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
68548 {
68549 { 0, 0, 0, 0 },
68550 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68551 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b000 }
68552 },
68553/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
68554 {
68555 { 0, 0, 0, 0 },
68556 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
68557 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b000 }
68558 },
68559/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68560 {
68561 { 0, 0, 0, 0 },
68562 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68563 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80000 }
68564 },
68565/* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
68566 {
68567 { 0, 0, 0, 0 },
68568 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
68569 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82000 }
68570 },
68571/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68572 {
68573 { 0, 0, 0, 0 },
68574 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68575 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08000 }
68576 },
68577/* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
68578 {
68579 { 0, 0, 0, 0 },
68580 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
68581 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a000 }
68582 },
68583/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68584 {
68585 { 0, 0, 0, 0 },
68586 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68587 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00000 }
68588 },
68589/* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
68590 {
68591 { 0, 0, 0, 0 },
68592 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68593 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02000 }
68594 },
68595/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
68596 {
68597 { 0, 0, 0, 0 },
68598 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68599 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20000 }
68600 },
68601/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
68602 {
68603 { 0, 0, 0, 0 },
68604 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68605 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22000 }
68606 },
68607/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
68608 {
68609 { 0, 0, 0, 0 },
68610 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68611 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40000 }
68612 },
68613/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
68614 {
68615 { 0, 0, 0, 0 },
68616 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68617 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42000 }
68618 },
68619/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
68620 {
68621 { 0, 0, 0, 0 },
68622 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68623 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60000 }
68624 },
68625/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
68626 {
68627 { 0, 0, 0, 0 },
68628 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68629 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62000 }
68630 },
68631/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
68632 {
68633 { 0, 0, 0, 0 },
68634 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
68635 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28000 }
68636 },
68637/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
68638 {
68639 { 0, 0, 0, 0 },
68640 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
68641 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a000 }
68642 },
68643/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
68644 {
68645 { 0, 0, 0, 0 },
68646 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
68647 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48000 }
68648 },
68649/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
68650 {
68651 { 0, 0, 0, 0 },
68652 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
68653 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a000 }
68654 },
68655/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
68656 {
68657 { 0, 0, 0, 0 },
68658 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
68659 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c000 }
68660 },
68661/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
68662 {
68663 { 0, 0, 0, 0 },
68664 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
68665 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e000 }
68666 },
68667/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
68668 {
68669 { 0, 0, 0, 0 },
68670 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
68671 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c000 }
68672 },
68673/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
68674 {
68675 { 0, 0, 0, 0 },
68676 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
68677 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e000 }
68678 },
68679/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
68680 {
68681 { 0, 0, 0, 0 },
68682 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
68683 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c000 }
68684 },
68685/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
68686 {
68687 { 0, 0, 0, 0 },
68688 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
68689 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e000 }
68690 },
68691/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
68692 {
68693 { 0, 0, 0, 0 },
68694 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
68695 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68000 }
68696 },
68697/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
68698 {
68699 { 0, 0, 0, 0 },
68700 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
68701 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a000 }
68702 },
68703/* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
68704 {
68705 { 0, 0, 0, 0 },
68706 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
68707 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c800 }
68708 },
68709/* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
68710 {
68711 { 0, 0, 0, 0 },
68712 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
68713 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18820 }
68714 },
68715/* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
68716 {
68717 { 0, 0, 0, 0 },
68718 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68719 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18800 }
68720 },
68721/* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
68722 {
68723 { 0, 0, 0, 0 },
68724 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
68725 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c080 }
68726 },
68727/* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
68728 {
68729 { 0, 0, 0, 0 },
68730 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
68731 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a0 }
68732 },
68733/* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
68734 {
68735 { 0, 0, 0, 0 },
68736 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68737 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18080 }
68738 },
68739/* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
68740 {
68741 { 0, 0, 0, 0 },
68742 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68743 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c000 }
68744 },
68745/* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
68746 {
68747 { 0, 0, 0, 0 },
68748 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68749 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18020 }
68750 },
68751/* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
68752 {
68753 { 0, 0, 0, 0 },
68754 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68755 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18000 }
68756 },
68757/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
68758 {
68759 { 0, 0, 0, 0 },
68760 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68761 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20000 }
68762 },
68763/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
68764 {
68765 { 0, 0, 0, 0 },
68766 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68767 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822000 }
68768 },
68769/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
68770 {
68771 { 0, 0, 0, 0 },
68772 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68773 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820000 }
68774 },
68775/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
68776 {
68777 { 0, 0, 0, 0 },
68778 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68779 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40000 }
68780 },
68781/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
68782 {
68783 { 0, 0, 0, 0 },
68784 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68785 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842000 }
68786 },
68787/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
68788 {
68789 { 0, 0, 0, 0 },
68790 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68791 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840000 }
68792 },
68793/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
68794 {
68795 { 0, 0, 0, 0 },
68796 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68797 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60000 }
68798 },
68799/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
68800 {
68801 { 0, 0, 0, 0 },
68802 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68803 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862000 }
68804 },
68805/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
68806 {
68807 { 0, 0, 0, 0 },
68808 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68809 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860000 }
68810 },
68811/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
68812 {
68813 { 0, 0, 0, 0 },
68814 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68815 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28000 }
68816 },
68817/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
68818 {
68819 { 0, 0, 0, 0 },
68820 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68821 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a000 }
68822 },
68823/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
68824 {
68825 { 0, 0, 0, 0 },
68826 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68827 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828000 }
68828 },
68829/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
68830 {
68831 { 0, 0, 0, 0 },
68832 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68833 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48000 }
68834 },
68835/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
68836 {
68837 { 0, 0, 0, 0 },
68838 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68839 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a000 }
68840 },
68841/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
68842 {
68843 { 0, 0, 0, 0 },
68844 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68845 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848000 }
68846 },
68847/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
68848 {
68849 { 0, 0, 0, 0 },
68850 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68851 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c000 }
68852 },
68853/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
68854 {
68855 { 0, 0, 0, 0 },
68856 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68857 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e000 }
68858 },
68859/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
68860 {
68861 { 0, 0, 0, 0 },
68862 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68863 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c000 }
68864 },
68865/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
68866 {
68867 { 0, 0, 0, 0 },
68868 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68869 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c000 }
68870 },
68871/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
68872 {
68873 { 0, 0, 0, 0 },
68874 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68875 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e000 }
68876 },
68877/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
68878 {
68879 { 0, 0, 0, 0 },
68880 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68881 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c000 }
68882 },
68883/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
68884 {
68885 { 0, 0, 0, 0 },
68886 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
68887 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c000 }
68888 },
68889/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
68890 {
68891 { 0, 0, 0, 0 },
68892 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
68893 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e000 }
68894 },
68895/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
68896 {
68897 { 0, 0, 0, 0 },
68898 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
68899 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c000 }
68900 },
68901/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
68902 {
68903 { 0, 0, 0, 0 },
68904 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
68905 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68000 }
68906 },
68907/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
68908 {
68909 { 0, 0, 0, 0 },
68910 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
68911 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a000 }
68912 },
68913/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
68914 {
68915 { 0, 0, 0, 0 },
68916 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
68917 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868000 }
68918 },
68919/* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
68920 {
68921 { 0, 0, 0, 0 },
68922 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
68923 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1891e00 }
68924 },
68925/* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
68926 {
68927 { 0, 0, 0, 0 },
68928 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
68929 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1819e00 }
68930 },
68931/* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
68932 {
68933 { 0, 0, 0, 0 },
68934 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68935 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1811e00 }
68936 },
68937/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
68938 {
68939 { 0, 0, 0, 0 },
68940 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68941 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1831e00 }
68942 },
68943/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
68944 {
68945 { 0, 0, 0, 0 },
68946 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68947 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1839e00 }
68948 },
68949/* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
68950 {
68951 { 0, 0, 0, 0 },
68952 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68953 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183de00 }
68954 },
68955/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
68956 {
68957 { 0, 0, 0, 0 },
68958 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68959 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1851e00 }
68960 },
68961/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
68962 {
68963 { 0, 0, 0, 0 },
68964 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68965 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1859e00 }
68966 },
68967/* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
68968 {
68969 { 0, 0, 0, 0 },
68970 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68971 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185de00 }
68972 },
68973/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
68974 {
68975 { 0, 0, 0, 0 },
68976 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
68977 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187de00 }
68978 },
68979/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
68980 {
68981 { 0, 0, 0, 0 },
68982 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68983 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1871e00 }
68984 },
68985/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
68986 {
68987 { 0, 0, 0, 0 },
68988 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
68989 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1879e00 }
68990 },
68991/* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
68992 {
68993 { 0, 0, 0, 0 },
68994 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
68995 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1881e00 }
68996 },
68997/* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
68998 {
68999 { 0, 0, 0, 0 },
69000 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
69001 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1809e00 }
69002 },
69003/* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
69004 {
69005 { 0, 0, 0, 0 },
69006 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69007 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1801e00 }
69008 },
69009/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
69010 {
69011 { 0, 0, 0, 0 },
69012 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69013 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1821e00 }
69014 },
69015/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
69016 {
69017 { 0, 0, 0, 0 },
69018 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69019 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1829e00 }
69020 },
69021/* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
69022 {
69023 { 0, 0, 0, 0 },
69024 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69025 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182de00 }
69026 },
69027/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
69028 {
69029 { 0, 0, 0, 0 },
69030 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69031 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1841e00 }
69032 },
69033/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
69034 {
69035 { 0, 0, 0, 0 },
69036 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69037 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1849e00 }
69038 },
69039/* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
69040 {
69041 { 0, 0, 0, 0 },
69042 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69043 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184de00 }
69044 },
69045/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
69046 {
69047 { 0, 0, 0, 0 },
69048 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
69049 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186de00 }
69050 },
69051/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
69052 {
69053 { 0, 0, 0, 0 },
69054 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69055 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1861e00 }
69056 },
69057/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
69058 {
69059 { 0, 0, 0, 0 },
69060 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
69061 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1869e00 }
69062 },
69063/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69064 {
69065 { 0, 0, 0, 0 },
69066 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69067 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990800 }
69068 },
69069/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
69070 {
69071 { 0, 0, 0, 0 },
69072 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69073 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992800 }
69074 },
69075/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
69076 {
69077 { 0, 0, 0, 0 },
69078 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69079 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993800 }
69080 },
69081/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69082 {
69083 { 0, 0, 0, 0 },
69084 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69085 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918800 }
69086 },
69087/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
69088 {
69089 { 0, 0, 0, 0 },
69090 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69091 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a800 }
69092 },
69093/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
69094 {
69095 { 0, 0, 0, 0 },
69096 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69097 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b800 }
69098 },
69099/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69100 {
69101 { 0, 0, 0, 0 },
69102 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69103 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910800 }
69104 },
69105/* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
69106 {
69107 { 0, 0, 0, 0 },
69108 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69109 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912800 }
69110 },
69111/* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
69112 {
69113 { 0, 0, 0, 0 },
69114 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69115 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913800 }
69116 },
69117/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
69118 {
69119 { 0, 0, 0, 0 },
69120 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69121 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930800 }
69122 },
69123/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69124 {
69125 { 0, 0, 0, 0 },
69126 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69127 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932800 }
69128 },
69129/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69130 {
69131 { 0, 0, 0, 0 },
69132 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69133 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933800 }
69134 },
69135/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
69136 {
69137 { 0, 0, 0, 0 },
69138 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69139 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950800 }
69140 },
69141/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
69142 {
69143 { 0, 0, 0, 0 },
69144 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69145 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952800 }
69146 },
69147/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
69148 {
69149 { 0, 0, 0, 0 },
69150 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69151 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953800 }
69152 },
69153/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
69154 {
69155 { 0, 0, 0, 0 },
69156 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69157 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970800 }
69158 },
69159/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
69160 {
69161 { 0, 0, 0, 0 },
69162 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69163 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972800 }
69164 },
69165/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
69166 {
69167 { 0, 0, 0, 0 },
69168 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69169 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973800 }
69170 },
69171/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
69172 {
69173 { 0, 0, 0, 0 },
69174 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69175 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938800 }
69176 },
69177/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
69178 {
69179 { 0, 0, 0, 0 },
69180 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69181 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a800 }
69182 },
69183/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
69184 {
69185 { 0, 0, 0, 0 },
69186 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69187 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b800 }
69188 },
69189/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
69190 {
69191 { 0, 0, 0, 0 },
69192 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69193 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958800 }
69194 },
69195/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
69196 {
69197 { 0, 0, 0, 0 },
69198 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69199 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a800 }
69200 },
69201/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
69202 {
69203 { 0, 0, 0, 0 },
69204 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69205 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b800 }
69206 },
69207/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
69208 {
69209 { 0, 0, 0, 0 },
69210 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69211 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c800 }
69212 },
69213/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
69214 {
69215 { 0, 0, 0, 0 },
69216 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69217 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e800 }
69218 },
69219/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
69220 {
69221 { 0, 0, 0, 0 },
69222 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69223 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f800 }
69224 },
69225/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
69226 {
69227 { 0, 0, 0, 0 },
69228 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69229 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c800 }
69230 },
69231/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
69232 {
69233 { 0, 0, 0, 0 },
69234 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69235 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e800 }
69236 },
69237/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
69238 {
69239 { 0, 0, 0, 0 },
69240 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69241 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f800 }
69242 },
69243/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
69244 {
69245 { 0, 0, 0, 0 },
69246 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
69247 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c800 }
69248 },
69249/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
69250 {
69251 { 0, 0, 0, 0 },
69252 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
69253 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e800 }
69254 },
69255/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
69256 {
69257 { 0, 0, 0, 0 },
69258 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
69259 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f800 }
69260 },
69261/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
69262 {
69263 { 0, 0, 0, 0 },
69264 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
69265 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978800 }
69266 },
69267/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
69268 {
69269 { 0, 0, 0, 0 },
69270 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
69271 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a800 }
69272 },
69273/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
69274 {
69275 { 0, 0, 0, 0 },
69276 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
69277 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b800 }
69278 },
69279/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69280 {
69281 { 0, 0, 0, 0 },
69282 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69283 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90800 }
69284 },
69285/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
69286 {
69287 { 0, 0, 0, 0 },
69288 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69289 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92800 }
69290 },
69291/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
69292 {
69293 { 0, 0, 0, 0 },
69294 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69295 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93800 }
69296 },
69297/* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
69298 {
69299 { 0, 0, 0, 0 },
69300 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
69301 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93800 }
69302 },
69303/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69304 {
69305 { 0, 0, 0, 0 },
69306 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69307 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18800 }
69308 },
69309/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
69310 {
69311 { 0, 0, 0, 0 },
69312 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69313 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a800 }
69314 },
69315/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
69316 {
69317 { 0, 0, 0, 0 },
69318 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69319 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b800 }
69320 },
69321/* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
69322 {
69323 { 0, 0, 0, 0 },
69324 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
69325 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b800 }
69326 },
69327/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69328 {
69329 { 0, 0, 0, 0 },
69330 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69331 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10800 }
69332 },
69333/* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
69334 {
69335 { 0, 0, 0, 0 },
69336 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69337 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12800 }
69338 },
69339/* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
69340 {
69341 { 0, 0, 0, 0 },
69342 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69343 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13800 }
69344 },
69345/* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
69346 {
69347 { 0, 0, 0, 0 },
69348 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69349 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13800 }
69350 },
69351/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
69352 {
69353 { 0, 0, 0, 0 },
69354 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69355 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30800 }
69356 },
69357/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
69358 {
69359 { 0, 0, 0, 0 },
69360 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69361 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32800 }
69362 },
69363/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
69364 {
69365 { 0, 0, 0, 0 },
69366 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69367 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33800 }
69368 },
69369/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
69370 {
69371 { 0, 0, 0, 0 },
69372 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69373 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33800 }
69374 },
69375/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
69376 {
69377 { 0, 0, 0, 0 },
69378 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69379 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50800 }
69380 },
69381/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
69382 {
69383 { 0, 0, 0, 0 },
69384 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69385 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52800 }
69386 },
69387/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
69388 {
69389 { 0, 0, 0, 0 },
69390 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69391 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53800 }
69392 },
69393/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
69394 {
69395 { 0, 0, 0, 0 },
69396 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69397 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53800 }
69398 },
69399/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
69400 {
69401 { 0, 0, 0, 0 },
69402 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69403 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70800 }
69404 },
69405/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
69406 {
69407 { 0, 0, 0, 0 },
69408 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69409 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72800 }
69410 },
69411/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
69412 {
69413 { 0, 0, 0, 0 },
69414 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69415 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73800 }
69416 },
69417/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
69418 {
69419 { 0, 0, 0, 0 },
69420 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69421 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73800 }
69422 },
69423/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
69424 {
69425 { 0, 0, 0, 0 },
69426 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69427 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38800 }
69428 },
69429/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
69430 {
69431 { 0, 0, 0, 0 },
69432 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69433 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a800 }
69434 },
69435/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
69436 {
69437 { 0, 0, 0, 0 },
69438 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69439 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b800 }
69440 },
69441/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
69442 {
69443 { 0, 0, 0, 0 },
69444 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69445 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b800 }
69446 },
69447/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
69448 {
69449 { 0, 0, 0, 0 },
69450 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69451 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58800 }
69452 },
69453/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
69454 {
69455 { 0, 0, 0, 0 },
69456 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69457 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a800 }
69458 },
69459/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
69460 {
69461 { 0, 0, 0, 0 },
69462 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69463 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b800 }
69464 },
69465/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
69466 {
69467 { 0, 0, 0, 0 },
69468 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69469 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b800 }
69470 },
69471/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
69472 {
69473 { 0, 0, 0, 0 },
69474 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69475 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c800 }
69476 },
69477/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
69478 {
69479 { 0, 0, 0, 0 },
69480 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69481 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e800 }
69482 },
69483/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
69484 {
69485 { 0, 0, 0, 0 },
69486 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69487 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f800 }
69488 },
69489/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
69490 {
69491 { 0, 0, 0, 0 },
69492 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69493 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f800 }
69494 },
69495/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
69496 {
69497 { 0, 0, 0, 0 },
69498 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69499 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c800 }
69500 },
69501/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
69502 {
69503 { 0, 0, 0, 0 },
69504 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69505 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e800 }
69506 },
69507/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
69508 {
69509 { 0, 0, 0, 0 },
69510 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69511 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f800 }
69512 },
69513/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
69514 {
69515 { 0, 0, 0, 0 },
69516 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69517 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f800 }
69518 },
69519/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
69520 {
69521 { 0, 0, 0, 0 },
69522 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
69523 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c800 }
69524 },
69525/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
69526 {
69527 { 0, 0, 0, 0 },
69528 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
69529 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e800 }
69530 },
69531/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
69532 {
69533 { 0, 0, 0, 0 },
69534 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
69535 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f800 }
69536 },
69537/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
69538 {
69539 { 0, 0, 0, 0 },
69540 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
69541 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f800 }
69542 },
69543/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
69544 {
69545 { 0, 0, 0, 0 },
69546 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
69547 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78800 }
69548 },
69549/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
69550 {
69551 { 0, 0, 0, 0 },
69552 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
69553 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a800 }
69554 },
69555/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
69556 {
69557 { 0, 0, 0, 0 },
69558 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
69559 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b800 }
69560 },
69561/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
69562 {
69563 { 0, 0, 0, 0 },
69564 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
69565 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b800 }
69566 },
69567/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69568 {
69569 { 0, 0, 0, 0 },
69570 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69571 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90800 }
69572 },
69573/* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
69574 {
69575 { 0, 0, 0, 0 },
69576 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
69577 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92800 }
69578 },
69579/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69580 {
69581 { 0, 0, 0, 0 },
69582 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69583 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18800 }
69584 },
69585/* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
69586 {
69587 { 0, 0, 0, 0 },
69588 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
69589 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a800 }
69590 },
69591/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69592 {
69593 { 0, 0, 0, 0 },
69594 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69595 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10800 }
69596 },
69597/* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
69598 {
69599 { 0, 0, 0, 0 },
69600 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69601 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12800 }
69602 },
69603/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
69604 {
69605 { 0, 0, 0, 0 },
69606 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69607 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30800 }
69608 },
69609/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
69610 {
69611 { 0, 0, 0, 0 },
69612 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69613 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32800 }
69614 },
69615/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
69616 {
69617 { 0, 0, 0, 0 },
69618 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69619 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50800 }
69620 },
69621/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
69622 {
69623 { 0, 0, 0, 0 },
69624 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69625 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52800 }
69626 },
69627/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
69628 {
69629 { 0, 0, 0, 0 },
69630 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69631 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70800 }
69632 },
69633/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
69634 {
69635 { 0, 0, 0, 0 },
69636 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69637 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72800 }
69638 },
69639/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
69640 {
69641 { 0, 0, 0, 0 },
69642 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
69643 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38800 }
69644 },
69645/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
69646 {
69647 { 0, 0, 0, 0 },
69648 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
69649 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a800 }
69650 },
69651/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
69652 {
69653 { 0, 0, 0, 0 },
69654 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
69655 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58800 }
69656 },
69657/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
69658 {
69659 { 0, 0, 0, 0 },
69660 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
69661 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a800 }
69662 },
69663/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
69664 {
69665 { 0, 0, 0, 0 },
69666 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
69667 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c800 }
69668 },
69669/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
69670 {
69671 { 0, 0, 0, 0 },
69672 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
69673 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e800 }
69674 },
69675/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
69676 {
69677 { 0, 0, 0, 0 },
69678 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
69679 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c800 }
69680 },
69681/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
69682 {
69683 { 0, 0, 0, 0 },
69684 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
69685 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e800 }
69686 },
69687/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
69688 {
69689 { 0, 0, 0, 0 },
69690 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
69691 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c800 }
69692 },
69693/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
69694 {
69695 { 0, 0, 0, 0 },
69696 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
69697 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e800 }
69698 },
69699/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
69700 {
69701 { 0, 0, 0, 0 },
69702 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
69703 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78800 }
69704 },
69705/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
69706 {
69707 { 0, 0, 0, 0 },
69708 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
69709 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a800 }
69710 },
69711/* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
69712 {
69713 { 0, 0, 0, 0 },
69714 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
69715 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c908 }
69716 },
69717/* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
69718 {
69719 { 0, 0, 0, 0 },
69720 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
69721 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18928 }
69722 },
69723/* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
69724 {
69725 { 0, 0, 0, 0 },
69726 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69727 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18908 }
69728 },
69729/* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
69730 {
69731 { 0, 0, 0, 0 },
69732 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
69733 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c188 }
69734 },
69735/* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
69736 {
69737 { 0, 0, 0, 0 },
69738 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
69739 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a8 }
69740 },
69741/* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
69742 {
69743 { 0, 0, 0, 0 },
69744 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69745 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18188 }
69746 },
69747/* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
69748 {
69749 { 0, 0, 0, 0 },
69750 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69751 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c108 }
69752 },
69753/* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
69754 {
69755 { 0, 0, 0, 0 },
69756 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69757 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18128 }
69758 },
69759/* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
69760 {
69761 { 0, 0, 0, 0 },
69762 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69763 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18108 }
69764 },
69765/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
69766 {
69767 { 0, 0, 0, 0 },
69768 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69769 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30800 }
69770 },
69771/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
69772 {
69773 { 0, 0, 0, 0 },
69774 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69775 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832800 }
69776 },
69777/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
69778 {
69779 { 0, 0, 0, 0 },
69780 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69781 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830800 }
69782 },
69783/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
69784 {
69785 { 0, 0, 0, 0 },
69786 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69787 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50800 }
69788 },
69789/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
69790 {
69791 { 0, 0, 0, 0 },
69792 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69793 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852800 }
69794 },
69795/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
69796 {
69797 { 0, 0, 0, 0 },
69798 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69799 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850800 }
69800 },
69801/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
69802 {
69803 { 0, 0, 0, 0 },
69804 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69805 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70800 }
69806 },
69807/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
69808 {
69809 { 0, 0, 0, 0 },
69810 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69811 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872800 }
69812 },
69813/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
69814 {
69815 { 0, 0, 0, 0 },
69816 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69817 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870800 }
69818 },
69819/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
69820 {
69821 { 0, 0, 0, 0 },
69822 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69823 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38800 }
69824 },
69825/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
69826 {
69827 { 0, 0, 0, 0 },
69828 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69829 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a800 }
69830 },
69831/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
69832 {
69833 { 0, 0, 0, 0 },
69834 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69835 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838800 }
69836 },
69837/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
69838 {
69839 { 0, 0, 0, 0 },
69840 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69841 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58800 }
69842 },
69843/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
69844 {
69845 { 0, 0, 0, 0 },
69846 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69847 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a800 }
69848 },
69849/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
69850 {
69851 { 0, 0, 0, 0 },
69852 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69853 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858800 }
69854 },
69855/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
69856 {
69857 { 0, 0, 0, 0 },
69858 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69859 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c800 }
69860 },
69861/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
69862 {
69863 { 0, 0, 0, 0 },
69864 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69865 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e800 }
69866 },
69867/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
69868 {
69869 { 0, 0, 0, 0 },
69870 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69871 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c800 }
69872 },
69873/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
69874 {
69875 { 0, 0, 0, 0 },
69876 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69877 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c800 }
69878 },
69879/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
69880 {
69881 { 0, 0, 0, 0 },
69882 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69883 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e800 }
69884 },
69885/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
69886 {
69887 { 0, 0, 0, 0 },
69888 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69889 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c800 }
69890 },
69891/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
69892 {
69893 { 0, 0, 0, 0 },
69894 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
69895 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c800 }
69896 },
69897/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
69898 {
69899 { 0, 0, 0, 0 },
69900 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
69901 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e800 }
69902 },
69903/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
69904 {
69905 { 0, 0, 0, 0 },
69906 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
69907 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c800 }
69908 },
69909/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
69910 {
69911 { 0, 0, 0, 0 },
69912 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
69913 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78800 }
69914 },
69915/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
69916 {
69917 { 0, 0, 0, 0 },
69918 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
69919 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a800 }
69920 },
69921/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
69922 {
69923 { 0, 0, 0, 0 },
69924 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
69925 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878800 }
69926 },
69927/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
69928 {
69929 { 0, 0, 0, 0 },
69930 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
69931 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980800 }
69932 },
69933/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
69934 {
69935 { 0, 0, 0, 0 },
69936 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
69937 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982800 }
69938 },
69939/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
69940 {
69941 { 0, 0, 0, 0 },
69942 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
69943 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983800 }
69944 },
69945/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
69946 {
69947 { 0, 0, 0, 0 },
69948 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
69949 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908800 }
69950 },
69951/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
69952 {
69953 { 0, 0, 0, 0 },
69954 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
69955 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a800 }
69956 },
69957/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
69958 {
69959 { 0, 0, 0, 0 },
69960 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
69961 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b800 }
69962 },
69963/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69964 {
69965 { 0, 0, 0, 0 },
69966 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69967 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900800 }
69968 },
69969/* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
69970 {
69971 { 0, 0, 0, 0 },
69972 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69973 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902800 }
69974 },
69975/* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
69976 {
69977 { 0, 0, 0, 0 },
69978 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69979 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903800 }
69980 },
69981/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
69982 {
69983 { 0, 0, 0, 0 },
69984 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69985 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920800 }
69986 },
69987/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69988 {
69989 { 0, 0, 0, 0 },
69990 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69991 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922800 }
69992 },
69993/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69994 {
69995 { 0, 0, 0, 0 },
69996 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69997 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923800 }
69998 },
69999/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
70000 {
70001 { 0, 0, 0, 0 },
70002 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70003 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940800 }
70004 },
70005/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
70006 {
70007 { 0, 0, 0, 0 },
70008 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70009 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942800 }
70010 },
70011/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
70012 {
70013 { 0, 0, 0, 0 },
70014 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70015 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943800 }
70016 },
70017/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
70018 {
70019 { 0, 0, 0, 0 },
70020 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70021 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960800 }
70022 },
70023/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
70024 {
70025 { 0, 0, 0, 0 },
70026 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70027 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962800 }
70028 },
70029/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
70030 {
70031 { 0, 0, 0, 0 },
70032 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70033 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963800 }
70034 },
70035/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
70036 {
70037 { 0, 0, 0, 0 },
70038 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70039 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928800 }
70040 },
70041/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
70042 {
70043 { 0, 0, 0, 0 },
70044 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70045 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a800 }
70046 },
70047/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
70048 {
70049 { 0, 0, 0, 0 },
70050 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70051 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b800 }
70052 },
70053/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
70054 {
70055 { 0, 0, 0, 0 },
70056 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70057 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948800 }
70058 },
70059/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
70060 {
70061 { 0, 0, 0, 0 },
70062 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70063 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a800 }
70064 },
70065/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
70066 {
70067 { 0, 0, 0, 0 },
70068 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70069 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b800 }
70070 },
70071/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
70072 {
70073 { 0, 0, 0, 0 },
70074 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70075 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c800 }
70076 },
70077/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
70078 {
70079 { 0, 0, 0, 0 },
70080 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70081 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e800 }
70082 },
70083/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
70084 {
70085 { 0, 0, 0, 0 },
70086 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70087 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f800 }
70088 },
70089/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
70090 {
70091 { 0, 0, 0, 0 },
70092 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70093 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c800 }
70094 },
70095/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
70096 {
70097 { 0, 0, 0, 0 },
70098 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70099 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e800 }
70100 },
70101/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
70102 {
70103 { 0, 0, 0, 0 },
70104 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70105 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f800 }
70106 },
70107/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
70108 {
70109 { 0, 0, 0, 0 },
70110 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
70111 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c800 }
70112 },
70113/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
70114 {
70115 { 0, 0, 0, 0 },
70116 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
70117 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e800 }
70118 },
70119/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
70120 {
70121 { 0, 0, 0, 0 },
70122 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
70123 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f800 }
70124 },
70125/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
70126 {
70127 { 0, 0, 0, 0 },
70128 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
70129 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968800 }
70130 },
70131/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
70132 {
70133 { 0, 0, 0, 0 },
70134 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
70135 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a800 }
70136 },
70137/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
70138 {
70139 { 0, 0, 0, 0 },
70140 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
70141 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b800 }
70142 },
70143/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70144 {
70145 { 0, 0, 0, 0 },
70146 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70147 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80800 }
70148 },
70149/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
70150 {
70151 { 0, 0, 0, 0 },
70152 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70153 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82800 }
70154 },
70155/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
70156 {
70157 { 0, 0, 0, 0 },
70158 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70159 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83800 }
70160 },
70161/* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
70162 {
70163 { 0, 0, 0, 0 },
70164 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
70165 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83800 }
70166 },
70167/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70168 {
70169 { 0, 0, 0, 0 },
70170 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70171 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08800 }
70172 },
70173/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
70174 {
70175 { 0, 0, 0, 0 },
70176 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70177 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a800 }
70178 },
70179/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
70180 {
70181 { 0, 0, 0, 0 },
70182 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70183 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b800 }
70184 },
70185/* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
70186 {
70187 { 0, 0, 0, 0 },
70188 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
70189 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b800 }
70190 },
70191/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70192 {
70193 { 0, 0, 0, 0 },
70194 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70195 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00800 }
70196 },
70197/* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
70198 {
70199 { 0, 0, 0, 0 },
70200 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70201 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02800 }
70202 },
70203/* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
70204 {
70205 { 0, 0, 0, 0 },
70206 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70207 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03800 }
70208 },
70209/* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
70210 {
70211 { 0, 0, 0, 0 },
70212 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70213 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03800 }
70214 },
70215/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
70216 {
70217 { 0, 0, 0, 0 },
70218 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70219 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20800 }
70220 },
70221/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
70222 {
70223 { 0, 0, 0, 0 },
70224 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70225 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22800 }
70226 },
70227/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
70228 {
70229 { 0, 0, 0, 0 },
70230 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70231 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23800 }
70232 },
70233/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
70234 {
70235 { 0, 0, 0, 0 },
70236 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70237 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23800 }
70238 },
70239/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
70240 {
70241 { 0, 0, 0, 0 },
70242 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70243 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40800 }
70244 },
70245/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
70246 {
70247 { 0, 0, 0, 0 },
70248 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70249 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42800 }
70250 },
70251/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
70252 {
70253 { 0, 0, 0, 0 },
70254 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70255 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43800 }
70256 },
70257/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
70258 {
70259 { 0, 0, 0, 0 },
70260 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70261 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43800 }
70262 },
70263/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
70264 {
70265 { 0, 0, 0, 0 },
70266 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70267 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60800 }
70268 },
70269/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
70270 {
70271 { 0, 0, 0, 0 },
70272 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70273 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62800 }
70274 },
70275/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
70276 {
70277 { 0, 0, 0, 0 },
70278 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70279 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63800 }
70280 },
70281/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
70282 {
70283 { 0, 0, 0, 0 },
70284 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70285 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63800 }
70286 },
70287/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
70288 {
70289 { 0, 0, 0, 0 },
70290 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70291 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28800 }
70292 },
70293/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
70294 {
70295 { 0, 0, 0, 0 },
70296 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70297 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a800 }
70298 },
70299/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
70300 {
70301 { 0, 0, 0, 0 },
70302 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70303 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b800 }
70304 },
70305/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
70306 {
70307 { 0, 0, 0, 0 },
70308 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70309 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b800 }
70310 },
70311/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
70312 {
70313 { 0, 0, 0, 0 },
70314 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70315 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48800 }
70316 },
70317/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
70318 {
70319 { 0, 0, 0, 0 },
70320 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70321 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a800 }
70322 },
70323/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
70324 {
70325 { 0, 0, 0, 0 },
70326 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70327 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b800 }
70328 },
70329/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
70330 {
70331 { 0, 0, 0, 0 },
70332 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70333 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b800 }
70334 },
70335/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
70336 {
70337 { 0, 0, 0, 0 },
70338 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70339 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c800 }
70340 },
70341/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
70342 {
70343 { 0, 0, 0, 0 },
70344 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70345 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e800 }
70346 },
70347/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
70348 {
70349 { 0, 0, 0, 0 },
70350 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70351 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f800 }
70352 },
70353/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
70354 {
70355 { 0, 0, 0, 0 },
70356 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70357 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f800 }
70358 },
70359/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
70360 {
70361 { 0, 0, 0, 0 },
70362 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70363 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c800 }
70364 },
70365/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
70366 {
70367 { 0, 0, 0, 0 },
70368 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70369 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e800 }
70370 },
70371/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
70372 {
70373 { 0, 0, 0, 0 },
70374 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70375 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f800 }
70376 },
70377/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
70378 {
70379 { 0, 0, 0, 0 },
70380 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70381 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f800 }
70382 },
70383/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
70384 {
70385 { 0, 0, 0, 0 },
70386 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
70387 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c800 }
70388 },
70389/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
70390 {
70391 { 0, 0, 0, 0 },
70392 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
70393 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e800 }
70394 },
70395/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
70396 {
70397 { 0, 0, 0, 0 },
70398 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
70399 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f800 }
70400 },
70401/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
70402 {
70403 { 0, 0, 0, 0 },
70404 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
70405 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f800 }
70406 },
70407/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
70408 {
70409 { 0, 0, 0, 0 },
70410 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
70411 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68800 }
70412 },
70413/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
70414 {
70415 { 0, 0, 0, 0 },
70416 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
70417 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a800 }
70418 },
70419/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
70420 {
70421 { 0, 0, 0, 0 },
70422 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
70423 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b800 }
70424 },
70425/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
70426 {
70427 { 0, 0, 0, 0 },
70428 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
70429 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b800 }
70430 },
70431/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70432 {
70433 { 0, 0, 0, 0 },
70434 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70435 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80800 }
70436 },
70437/* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
70438 {
70439 { 0, 0, 0, 0 },
70440 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
70441 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82800 }
70442 },
70443/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70444 {
70445 { 0, 0, 0, 0 },
70446 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70447 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08800 }
70448 },
70449/* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
70450 {
70451 { 0, 0, 0, 0 },
70452 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
70453 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a800 }
70454 },
70455/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70456 {
70457 { 0, 0, 0, 0 },
70458 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70459 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00800 }
70460 },
70461/* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
70462 {
70463 { 0, 0, 0, 0 },
70464 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70465 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02800 }
70466 },
70467/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
70468 {
70469 { 0, 0, 0, 0 },
70470 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70471 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20800 }
70472 },
70473/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
70474 {
70475 { 0, 0, 0, 0 },
70476 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70477 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22800 }
70478 },
70479/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
70480 {
70481 { 0, 0, 0, 0 },
70482 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70483 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40800 }
70484 },
70485/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
70486 {
70487 { 0, 0, 0, 0 },
70488 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70489 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42800 }
70490 },
70491/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
70492 {
70493 { 0, 0, 0, 0 },
70494 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70495 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60800 }
70496 },
70497/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
70498 {
70499 { 0, 0, 0, 0 },
70500 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70501 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62800 }
70502 },
70503/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
70504 {
70505 { 0, 0, 0, 0 },
70506 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70507 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28800 }
70508 },
70509/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
70510 {
70511 { 0, 0, 0, 0 },
70512 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70513 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a800 }
70514 },
70515/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
70516 {
70517 { 0, 0, 0, 0 },
70518 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70519 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48800 }
70520 },
70521/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
70522 {
70523 { 0, 0, 0, 0 },
70524 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70525 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a800 }
70526 },
70527/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
70528 {
70529 { 0, 0, 0, 0 },
70530 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70531 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c800 }
70532 },
70533/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
70534 {
70535 { 0, 0, 0, 0 },
70536 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70537 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e800 }
70538 },
70539/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
70540 {
70541 { 0, 0, 0, 0 },
70542 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70543 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c800 }
70544 },
70545/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
70546 {
70547 { 0, 0, 0, 0 },
70548 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70549 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e800 }
70550 },
70551/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
70552 {
70553 { 0, 0, 0, 0 },
70554 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
70555 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c800 }
70556 },
70557/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
70558 {
70559 { 0, 0, 0, 0 },
70560 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
70561 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e800 }
70562 },
70563/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
70564 {
70565 { 0, 0, 0, 0 },
70566 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
70567 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68800 }
70568 },
70569/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
70570 {
70571 { 0, 0, 0, 0 },
70572 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
70573 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a800 }
70574 },
70575/* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
70576 {
70577 { 0, 0, 0, 0 },
70578 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
70579 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c808 }
70580 },
70581/* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
70582 {
70583 { 0, 0, 0, 0 },
70584 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
70585 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18828 }
70586 },
70587/* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
70588 {
70589 { 0, 0, 0, 0 },
70590 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70591 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18808 }
70592 },
70593/* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
70594 {
70595 { 0, 0, 0, 0 },
70596 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
70597 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c088 }
70598 },
70599/* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
70600 {
70601 { 0, 0, 0, 0 },
70602 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
70603 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a8 }
70604 },
70605/* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
70606 {
70607 { 0, 0, 0, 0 },
70608 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70609 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18088 }
70610 },
70611/* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
70612 {
70613 { 0, 0, 0, 0 },
70614 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70615 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c008 }
70616 },
70617/* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
70618 {
70619 { 0, 0, 0, 0 },
70620 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70621 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18028 }
70622 },
70623/* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
70624 {
70625 { 0, 0, 0, 0 },
70626 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70627 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18008 }
70628 },
70629/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
70630 {
70631 { 0, 0, 0, 0 },
70632 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70633 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20800 }
70634 },
70635/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
70636 {
70637 { 0, 0, 0, 0 },
70638 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70639 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822800 }
70640 },
70641/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
70642 {
70643 { 0, 0, 0, 0 },
70644 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70645 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820800 }
70646 },
70647/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
70648 {
70649 { 0, 0, 0, 0 },
70650 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70651 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40800 }
70652 },
70653/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
70654 {
70655 { 0, 0, 0, 0 },
70656 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70657 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842800 }
70658 },
70659/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
70660 {
70661 { 0, 0, 0, 0 },
70662 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70663 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840800 }
70664 },
70665/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
70666 {
70667 { 0, 0, 0, 0 },
70668 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70669 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60800 }
70670 },
70671/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
70672 {
70673 { 0, 0, 0, 0 },
70674 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70675 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862800 }
70676 },
70677/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
70678 {
70679 { 0, 0, 0, 0 },
70680 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70681 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860800 }
70682 },
70683/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
70684 {
70685 { 0, 0, 0, 0 },
70686 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70687 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28800 }
70688 },
70689/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
70690 {
70691 { 0, 0, 0, 0 },
70692 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70693 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a800 }
70694 },
70695/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
70696 {
70697 { 0, 0, 0, 0 },
70698 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70699 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828800 }
70700 },
70701/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
70702 {
70703 { 0, 0, 0, 0 },
70704 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70705 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48800 }
70706 },
70707/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
70708 {
70709 { 0, 0, 0, 0 },
70710 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70711 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a800 }
70712 },
70713/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
70714 {
70715 { 0, 0, 0, 0 },
70716 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70717 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848800 }
70718 },
70719/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
70720 {
70721 { 0, 0, 0, 0 },
70722 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70723 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c800 }
70724 },
70725/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
70726 {
70727 { 0, 0, 0, 0 },
70728 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70729 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e800 }
70730 },
70731/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
70732 {
70733 { 0, 0, 0, 0 },
70734 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70735 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c800 }
70736 },
70737/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
70738 {
70739 { 0, 0, 0, 0 },
70740 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70741 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c800 }
70742 },
70743/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
70744 {
70745 { 0, 0, 0, 0 },
70746 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70747 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e800 }
70748 },
70749/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
70750 {
70751 { 0, 0, 0, 0 },
70752 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70753 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c800 }
70754 },
70755/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
70756 {
70757 { 0, 0, 0, 0 },
70758 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
70759 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c800 }
70760 },
70761/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
70762 {
70763 { 0, 0, 0, 0 },
70764 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
70765 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e800 }
70766 },
70767/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
70768 {
70769 { 0, 0, 0, 0 },
70770 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
70771 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c800 }
70772 },
70773/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
70774 {
70775 { 0, 0, 0, 0 },
70776 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
70777 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68800 }
70778 },
70779/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
70780 {
70781 { 0, 0, 0, 0 },
70782 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
70783 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a800 }
70784 },
70785/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
70786 {
70787 { 0, 0, 0, 0 },
70788 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
70789 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868800 }
70790 },
70791/* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
70792 {
70793 { 0, 0, 0, 0 },
70794 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
70795 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1890e00 }
70796 },
70797/* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
70798 {
70799 { 0, 0, 0, 0 },
70800 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
70801 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1818e00 }
70802 },
70803/* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
70804 {
70805 { 0, 0, 0, 0 },
70806 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70807 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1810e00 }
70808 },
70809/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
70810 {
70811 { 0, 0, 0, 0 },
70812 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70813 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1830e00 }
70814 },
70815/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
70816 {
70817 { 0, 0, 0, 0 },
70818 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70819 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838e00 }
70820 },
70821/* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
70822 {
70823 { 0, 0, 0, 0 },
70824 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70825 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ce00 }
70826 },
70827/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
70828 {
70829 { 0, 0, 0, 0 },
70830 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70831 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1850e00 }
70832 },
70833/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
70834 {
70835 { 0, 0, 0, 0 },
70836 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70837 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858e00 }
70838 },
70839/* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
70840 {
70841 { 0, 0, 0, 0 },
70842 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70843 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ce00 }
70844 },
70845/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
70846 {
70847 { 0, 0, 0, 0 },
70848 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
70849 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ce00 }
70850 },
70851/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
70852 {
70853 { 0, 0, 0, 0 },
70854 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70855 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1870e00 }
70856 },
70857/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
70858 {
70859 { 0, 0, 0, 0 },
70860 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
70861 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1878e00 }
70862 },
70863/* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
70864 {
70865 { 0, 0, 0, 0 },
70866 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
70867 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1880e00 }
70868 },
70869/* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
70870 {
70871 { 0, 0, 0, 0 },
70872 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
70873 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1808e00 }
70874 },
70875/* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
70876 {
70877 { 0, 0, 0, 0 },
70878 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70879 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1800e00 }
70880 },
70881/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
70882 {
70883 { 0, 0, 0, 0 },
70884 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70885 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1820e00 }
70886 },
70887/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
70888 {
70889 { 0, 0, 0, 0 },
70890 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70891 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828e00 }
70892 },
70893/* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
70894 {
70895 { 0, 0, 0, 0 },
70896 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70897 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ce00 }
70898 },
70899/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
70900 {
70901 { 0, 0, 0, 0 },
70902 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70903 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1840e00 }
70904 },
70905/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
70906 {
70907 { 0, 0, 0, 0 },
70908 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70909 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848e00 }
70910 },
70911/* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
70912 {
70913 { 0, 0, 0, 0 },
70914 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70915 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ce00 }
70916 },
70917/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
70918 {
70919 { 0, 0, 0, 0 },
70920 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
70921 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ce00 }
70922 },
70923/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
70924 {
70925 { 0, 0, 0, 0 },
70926 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70927 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1860e00 }
70928 },
70929/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
70930 {
70931 { 0, 0, 0, 0 },
70932 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
70933 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1868e00 }
70934 },
70935/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
70936 {
70937 { 0, 0, 0, 0 },
70938 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
70939 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990400 }
70940 },
70941/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
70942 {
70943 { 0, 0, 0, 0 },
70944 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
70945 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992400 }
70946 },
70947/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
70948 {
70949 { 0, 0, 0, 0 },
70950 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
70951 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993400 }
70952 },
70953/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
70954 {
70955 { 0, 0, 0, 0 },
70956 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
70957 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918400 }
70958 },
70959/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
70960 {
70961 { 0, 0, 0, 0 },
70962 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
70963 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a400 }
70964 },
70965/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
70966 {
70967 { 0, 0, 0, 0 },
70968 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
70969 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b400 }
70970 },
70971/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70972 {
70973 { 0, 0, 0, 0 },
70974 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70975 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910400 }
70976 },
70977/* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
70978 {
70979 { 0, 0, 0, 0 },
70980 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70981 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912400 }
70982 },
70983/* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
70984 {
70985 { 0, 0, 0, 0 },
70986 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70987 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913400 }
70988 },
70989/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
70990 {
70991 { 0, 0, 0, 0 },
70992 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70993 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930400 }
70994 },
70995/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
70996 {
70997 { 0, 0, 0, 0 },
70998 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70999 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932400 }
71000 },
71001/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
71002 {
71003 { 0, 0, 0, 0 },
71004 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71005 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933400 }
71006 },
71007/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
71008 {
71009 { 0, 0, 0, 0 },
71010 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71011 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950400 }
71012 },
71013/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71014 {
71015 { 0, 0, 0, 0 },
71016 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71017 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952400 }
71018 },
71019/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71020 {
71021 { 0, 0, 0, 0 },
71022 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71023 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953400 }
71024 },
71025/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
71026 {
71027 { 0, 0, 0, 0 },
71028 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71029 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970400 }
71030 },
71031/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71032 {
71033 { 0, 0, 0, 0 },
71034 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71035 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972400 }
71036 },
71037/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71038 {
71039 { 0, 0, 0, 0 },
71040 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71041 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973400 }
71042 },
71043/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
71044 {
71045 { 0, 0, 0, 0 },
71046 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71047 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938400 }
71048 },
71049/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
71050 {
71051 { 0, 0, 0, 0 },
71052 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71053 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a400 }
71054 },
71055/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
71056 {
71057 { 0, 0, 0, 0 },
71058 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71059 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b400 }
71060 },
71061/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
71062 {
71063 { 0, 0, 0, 0 },
71064 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71065 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958400 }
71066 },
71067/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
71068 {
71069 { 0, 0, 0, 0 },
71070 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71071 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a400 }
71072 },
71073/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
71074 {
71075 { 0, 0, 0, 0 },
71076 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71077 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b400 }
71078 },
71079/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
71080 {
71081 { 0, 0, 0, 0 },
71082 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71083 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c400 }
71084 },
71085/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
71086 {
71087 { 0, 0, 0, 0 },
71088 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71089 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e400 }
71090 },
71091/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
71092 {
71093 { 0, 0, 0, 0 },
71094 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71095 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f400 }
71096 },
71097/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
71098 {
71099 { 0, 0, 0, 0 },
71100 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71101 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c400 }
71102 },
71103/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
71104 {
71105 { 0, 0, 0, 0 },
71106 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71107 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e400 }
71108 },
71109/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
71110 {
71111 { 0, 0, 0, 0 },
71112 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71113 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f400 }
71114 },
71115/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
71116 {
71117 { 0, 0, 0, 0 },
71118 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
71119 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c400 }
71120 },
71121/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
71122 {
71123 { 0, 0, 0, 0 },
71124 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71125 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e400 }
71126 },
71127/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
71128 {
71129 { 0, 0, 0, 0 },
71130 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71131 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f400 }
71132 },
71133/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
71134 {
71135 { 0, 0, 0, 0 },
71136 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
71137 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978400 }
71138 },
71139/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
71140 {
71141 { 0, 0, 0, 0 },
71142 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
71143 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a400 }
71144 },
71145/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
71146 {
71147 { 0, 0, 0, 0 },
71148 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
71149 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b400 }
71150 },
71151/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71152 {
71153 { 0, 0, 0, 0 },
71154 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71155 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90400 }
71156 },
71157/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
71158 {
71159 { 0, 0, 0, 0 },
71160 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71161 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92400 }
71162 },
71163/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
71164 {
71165 { 0, 0, 0, 0 },
71166 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71167 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93400 }
71168 },
71169/* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
71170 {
71171 { 0, 0, 0, 0 },
71172 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
71173 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93400 }
71174 },
71175/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71176 {
71177 { 0, 0, 0, 0 },
71178 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71179 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18400 }
71180 },
71181/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
71182 {
71183 { 0, 0, 0, 0 },
71184 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71185 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a400 }
71186 },
71187/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
71188 {
71189 { 0, 0, 0, 0 },
71190 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71191 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b400 }
71192 },
71193/* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
71194 {
71195 { 0, 0, 0, 0 },
71196 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
71197 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b400 }
71198 },
71199/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71200 {
71201 { 0, 0, 0, 0 },
71202 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71203 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10400 }
71204 },
71205/* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
71206 {
71207 { 0, 0, 0, 0 },
71208 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71209 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12400 }
71210 },
71211/* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
71212 {
71213 { 0, 0, 0, 0 },
71214 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71215 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13400 }
71216 },
71217/* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
71218 {
71219 { 0, 0, 0, 0 },
71220 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71221 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13400 }
71222 },
71223/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
71224 {
71225 { 0, 0, 0, 0 },
71226 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71227 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30400 }
71228 },
71229/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
71230 {
71231 { 0, 0, 0, 0 },
71232 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71233 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32400 }
71234 },
71235/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
71236 {
71237 { 0, 0, 0, 0 },
71238 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71239 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33400 }
71240 },
71241/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
71242 {
71243 { 0, 0, 0, 0 },
71244 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71245 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33400 }
71246 },
71247/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
71248 {
71249 { 0, 0, 0, 0 },
71250 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71251 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50400 }
71252 },
71253/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
71254 {
71255 { 0, 0, 0, 0 },
71256 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71257 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52400 }
71258 },
71259/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
71260 {
71261 { 0, 0, 0, 0 },
71262 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71263 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53400 }
71264 },
71265/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
71266 {
71267 { 0, 0, 0, 0 },
71268 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71269 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53400 }
71270 },
71271/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
71272 {
71273 { 0, 0, 0, 0 },
71274 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71275 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70400 }
71276 },
71277/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
71278 {
71279 { 0, 0, 0, 0 },
71280 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71281 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72400 }
71282 },
71283/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
71284 {
71285 { 0, 0, 0, 0 },
71286 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71287 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73400 }
71288 },
71289/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
71290 {
71291 { 0, 0, 0, 0 },
71292 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71293 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73400 }
71294 },
71295/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
71296 {
71297 { 0, 0, 0, 0 },
71298 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71299 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38400 }
71300 },
71301/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
71302 {
71303 { 0, 0, 0, 0 },
71304 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71305 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a400 }
71306 },
71307/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
71308 {
71309 { 0, 0, 0, 0 },
71310 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71311 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b400 }
71312 },
71313/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
71314 {
71315 { 0, 0, 0, 0 },
71316 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71317 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b400 }
71318 },
71319/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
71320 {
71321 { 0, 0, 0, 0 },
71322 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71323 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58400 }
71324 },
71325/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
71326 {
71327 { 0, 0, 0, 0 },
71328 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71329 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a400 }
71330 },
71331/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
71332 {
71333 { 0, 0, 0, 0 },
71334 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71335 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b400 }
71336 },
71337/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
71338 {
71339 { 0, 0, 0, 0 },
71340 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71341 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b400 }
71342 },
71343/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
71344 {
71345 { 0, 0, 0, 0 },
71346 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71347 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c400 }
71348 },
71349/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
71350 {
71351 { 0, 0, 0, 0 },
71352 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71353 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e400 }
71354 },
71355/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
71356 {
71357 { 0, 0, 0, 0 },
71358 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71359 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f400 }
71360 },
71361/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
71362 {
71363 { 0, 0, 0, 0 },
71364 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71365 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f400 }
71366 },
71367/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
71368 {
71369 { 0, 0, 0, 0 },
71370 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71371 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c400 }
71372 },
71373/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
71374 {
71375 { 0, 0, 0, 0 },
71376 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71377 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e400 }
71378 },
71379/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
71380 {
71381 { 0, 0, 0, 0 },
71382 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71383 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f400 }
71384 },
71385/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
71386 {
71387 { 0, 0, 0, 0 },
71388 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71389 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f400 }
71390 },
71391/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
71392 {
71393 { 0, 0, 0, 0 },
71394 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
71395 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c400 }
71396 },
71397/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
71398 {
71399 { 0, 0, 0, 0 },
71400 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
71401 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e400 }
71402 },
71403/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
71404 {
71405 { 0, 0, 0, 0 },
71406 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
71407 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f400 }
71408 },
71409/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
71410 {
71411 { 0, 0, 0, 0 },
71412 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
71413 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f400 }
71414 },
71415/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
71416 {
71417 { 0, 0, 0, 0 },
71418 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
71419 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78400 }
71420 },
71421/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
71422 {
71423 { 0, 0, 0, 0 },
71424 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
71425 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a400 }
71426 },
71427/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
71428 {
71429 { 0, 0, 0, 0 },
71430 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
71431 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b400 }
71432 },
71433/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
71434 {
71435 { 0, 0, 0, 0 },
71436 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
71437 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b400 }
71438 },
71439/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71440 {
71441 { 0, 0, 0, 0 },
71442 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71443 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90400 }
71444 },
71445/* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
71446 {
71447 { 0, 0, 0, 0 },
71448 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
71449 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92400 }
71450 },
71451/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71452 {
71453 { 0, 0, 0, 0 },
71454 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71455 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18400 }
71456 },
71457/* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
71458 {
71459 { 0, 0, 0, 0 },
71460 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
71461 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a400 }
71462 },
71463/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71464 {
71465 { 0, 0, 0, 0 },
71466 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71467 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10400 }
71468 },
71469/* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
71470 {
71471 { 0, 0, 0, 0 },
71472 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71473 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12400 }
71474 },
71475/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
71476 {
71477 { 0, 0, 0, 0 },
71478 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71479 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30400 }
71480 },
71481/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
71482 {
71483 { 0, 0, 0, 0 },
71484 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71485 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32400 }
71486 },
71487/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
71488 {
71489 { 0, 0, 0, 0 },
71490 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71491 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50400 }
71492 },
71493/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
71494 {
71495 { 0, 0, 0, 0 },
71496 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71497 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52400 }
71498 },
71499/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
71500 {
71501 { 0, 0, 0, 0 },
71502 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71503 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70400 }
71504 },
71505/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
71506 {
71507 { 0, 0, 0, 0 },
71508 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71509 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72400 }
71510 },
71511/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
71512 {
71513 { 0, 0, 0, 0 },
71514 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
71515 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38400 }
71516 },
71517/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
71518 {
71519 { 0, 0, 0, 0 },
71520 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
71521 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a400 }
71522 },
71523/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
71524 {
71525 { 0, 0, 0, 0 },
71526 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
71527 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58400 }
71528 },
71529/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
71530 {
71531 { 0, 0, 0, 0 },
71532 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
71533 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a400 }
71534 },
71535/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
71536 {
71537 { 0, 0, 0, 0 },
71538 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
71539 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c400 }
71540 },
71541/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
71542 {
71543 { 0, 0, 0, 0 },
71544 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
71545 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e400 }
71546 },
71547/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
71548 {
71549 { 0, 0, 0, 0 },
71550 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
71551 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c400 }
71552 },
71553/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
71554 {
71555 { 0, 0, 0, 0 },
71556 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
71557 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e400 }
71558 },
71559/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
71560 {
71561 { 0, 0, 0, 0 },
71562 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
71563 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c400 }
71564 },
71565/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
71566 {
71567 { 0, 0, 0, 0 },
71568 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
71569 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e400 }
71570 },
71571/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
71572 {
71573 { 0, 0, 0, 0 },
71574 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
71575 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78400 }
71576 },
71577/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
71578 {
71579 { 0, 0, 0, 0 },
71580 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
71581 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a400 }
71582 },
71583/* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
71584 {
71585 { 0, 0, 0, 0 },
71586 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71587 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c904 }
71588 },
71589/* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
71590 {
71591 { 0, 0, 0, 0 },
71592 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71593 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18924 }
71594 },
71595/* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
71596 {
71597 { 0, 0, 0, 0 },
71598 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71599 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18904 }
71600 },
71601/* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
71602 {
71603 { 0, 0, 0, 0 },
71604 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71605 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c184 }
71606 },
71607/* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
71608 {
71609 { 0, 0, 0, 0 },
71610 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71611 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a4 }
71612 },
71613/* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
71614 {
71615 { 0, 0, 0, 0 },
71616 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71617 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18184 }
71618 },
71619/* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
71620 {
71621 { 0, 0, 0, 0 },
71622 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71623 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c104 }
71624 },
71625/* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
71626 {
71627 { 0, 0, 0, 0 },
71628 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71629 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18124 }
71630 },
71631/* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
71632 {
71633 { 0, 0, 0, 0 },
71634 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71635 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18104 }
71636 },
71637/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
71638 {
71639 { 0, 0, 0, 0 },
71640 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71641 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30400 }
71642 },
71643/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
71644 {
71645 { 0, 0, 0, 0 },
71646 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71647 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832400 }
71648 },
71649/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
71650 {
71651 { 0, 0, 0, 0 },
71652 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71653 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830400 }
71654 },
71655/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
71656 {
71657 { 0, 0, 0, 0 },
71658 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71659 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50400 }
71660 },
71661/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
71662 {
71663 { 0, 0, 0, 0 },
71664 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71665 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852400 }
71666 },
71667/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
71668 {
71669 { 0, 0, 0, 0 },
71670 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71671 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850400 }
71672 },
71673/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
71674 {
71675 { 0, 0, 0, 0 },
71676 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71677 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70400 }
71678 },
71679/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
71680 {
71681 { 0, 0, 0, 0 },
71682 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71683 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872400 }
71684 },
71685/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
71686 {
71687 { 0, 0, 0, 0 },
71688 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71689 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870400 }
71690 },
71691/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
71692 {
71693 { 0, 0, 0, 0 },
71694 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71695 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38400 }
71696 },
71697/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
71698 {
71699 { 0, 0, 0, 0 },
71700 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71701 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a400 }
71702 },
71703/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
71704 {
71705 { 0, 0, 0, 0 },
71706 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71707 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838400 }
71708 },
71709/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
71710 {
71711 { 0, 0, 0, 0 },
71712 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71713 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58400 }
71714 },
71715/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
71716 {
71717 { 0, 0, 0, 0 },
71718 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71719 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a400 }
71720 },
71721/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
71722 {
71723 { 0, 0, 0, 0 },
71724 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71725 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858400 }
71726 },
71727/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
71728 {
71729 { 0, 0, 0, 0 },
71730 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71731 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c400 }
71732 },
71733/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
71734 {
71735 { 0, 0, 0, 0 },
71736 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71737 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e400 }
71738 },
71739/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
71740 {
71741 { 0, 0, 0, 0 },
71742 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71743 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c400 }
71744 },
71745/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
71746 {
71747 { 0, 0, 0, 0 },
71748 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71749 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c400 }
71750 },
71751/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
71752 {
71753 { 0, 0, 0, 0 },
71754 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71755 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e400 }
71756 },
71757/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
71758 {
71759 { 0, 0, 0, 0 },
71760 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71761 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c400 }
71762 },
71763/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
71764 {
71765 { 0, 0, 0, 0 },
71766 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
71767 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c400 }
71768 },
71769/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
71770 {
71771 { 0, 0, 0, 0 },
71772 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
71773 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e400 }
71774 },
71775/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
71776 {
71777 { 0, 0, 0, 0 },
71778 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
71779 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c400 }
71780 },
71781/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
71782 {
71783 { 0, 0, 0, 0 },
71784 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
71785 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78400 }
71786 },
71787/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
71788 {
71789 { 0, 0, 0, 0 },
71790 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
71791 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a400 }
71792 },
71793/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
71794 {
71795 { 0, 0, 0, 0 },
71796 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
71797 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878400 }
71798 },
71799/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
71800 {
71801 { 0, 0, 0, 0 },
71802 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
71803 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980400 }
71804 },
71805/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
71806 {
71807 { 0, 0, 0, 0 },
71808 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
71809 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982400 }
71810 },
71811/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
71812 {
71813 { 0, 0, 0, 0 },
71814 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
71815 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983400 }
71816 },
71817/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
71818 {
71819 { 0, 0, 0, 0 },
71820 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
71821 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908400 }
71822 },
71823/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
71824 {
71825 { 0, 0, 0, 0 },
71826 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
71827 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a400 }
71828 },
71829/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
71830 {
71831 { 0, 0, 0, 0 },
71832 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
71833 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b400 }
71834 },
71835/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71836 {
71837 { 0, 0, 0, 0 },
71838 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71839 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900400 }
71840 },
71841/* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
71842 {
71843 { 0, 0, 0, 0 },
71844 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71845 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902400 }
71846 },
71847/* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
71848 {
71849 { 0, 0, 0, 0 },
71850 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71851 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903400 }
71852 },
71853/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
71854 {
71855 { 0, 0, 0, 0 },
71856 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71857 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920400 }
71858 },
71859/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
71860 {
71861 { 0, 0, 0, 0 },
71862 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71863 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922400 }
71864 },
71865/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
71866 {
71867 { 0, 0, 0, 0 },
71868 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71869 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923400 }
71870 },
71871/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
71872 {
71873 { 0, 0, 0, 0 },
71874 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71875 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940400 }
71876 },
71877/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71878 {
71879 { 0, 0, 0, 0 },
71880 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71881 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942400 }
71882 },
71883/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71884 {
71885 { 0, 0, 0, 0 },
71886 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71887 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943400 }
71888 },
71889/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
71890 {
71891 { 0, 0, 0, 0 },
71892 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71893 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960400 }
71894 },
71895/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71896 {
71897 { 0, 0, 0, 0 },
71898 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71899 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962400 }
71900 },
71901/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71902 {
71903 { 0, 0, 0, 0 },
71904 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71905 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963400 }
71906 },
71907/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
71908 {
71909 { 0, 0, 0, 0 },
71910 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71911 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928400 }
71912 },
71913/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
71914 {
71915 { 0, 0, 0, 0 },
71916 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71917 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a400 }
71918 },
71919/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
71920 {
71921 { 0, 0, 0, 0 },
71922 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71923 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b400 }
71924 },
71925/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
71926 {
71927 { 0, 0, 0, 0 },
71928 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71929 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948400 }
71930 },
71931/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
71932 {
71933 { 0, 0, 0, 0 },
71934 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71935 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a400 }
71936 },
71937/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
71938 {
71939 { 0, 0, 0, 0 },
71940 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71941 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b400 }
71942 },
71943/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
71944 {
71945 { 0, 0, 0, 0 },
71946 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71947 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c400 }
71948 },
71949/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
71950 {
71951 { 0, 0, 0, 0 },
71952 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71953 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e400 }
71954 },
71955/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
71956 {
71957 { 0, 0, 0, 0 },
71958 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71959 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f400 }
71960 },
71961/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
71962 {
71963 { 0, 0, 0, 0 },
71964 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71965 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c400 }
71966 },
71967/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
71968 {
71969 { 0, 0, 0, 0 },
71970 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71971 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e400 }
71972 },
71973/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
71974 {
71975 { 0, 0, 0, 0 },
71976 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71977 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f400 }
71978 },
71979/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
71980 {
71981 { 0, 0, 0, 0 },
71982 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
71983 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c400 }
71984 },
71985/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
71986 {
71987 { 0, 0, 0, 0 },
71988 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71989 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e400 }
71990 },
71991/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
71992 {
71993 { 0, 0, 0, 0 },
71994 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71995 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f400 }
71996 },
71997/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
71998 {
71999 { 0, 0, 0, 0 },
72000 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
72001 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968400 }
72002 },
72003/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
72004 {
72005 { 0, 0, 0, 0 },
72006 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
72007 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a400 }
72008 },
72009/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
72010 {
72011 { 0, 0, 0, 0 },
72012 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
72013 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b400 }
72014 },
72015/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72016 {
72017 { 0, 0, 0, 0 },
72018 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72019 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80400 }
72020 },
72021/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
72022 {
72023 { 0, 0, 0, 0 },
72024 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72025 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82400 }
72026 },
72027/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
72028 {
72029 { 0, 0, 0, 0 },
72030 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72031 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83400 }
72032 },
72033/* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
72034 {
72035 { 0, 0, 0, 0 },
72036 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
72037 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83400 }
72038 },
72039/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72040 {
72041 { 0, 0, 0, 0 },
72042 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72043 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08400 }
72044 },
72045/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
72046 {
72047 { 0, 0, 0, 0 },
72048 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72049 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a400 }
72050 },
72051/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
72052 {
72053 { 0, 0, 0, 0 },
72054 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72055 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b400 }
72056 },
72057/* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
72058 {
72059 { 0, 0, 0, 0 },
72060 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
72061 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b400 }
72062 },
72063/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72064 {
72065 { 0, 0, 0, 0 },
72066 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72067 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00400 }
72068 },
72069/* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
72070 {
72071 { 0, 0, 0, 0 },
72072 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72073 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02400 }
72074 },
72075/* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
72076 {
72077 { 0, 0, 0, 0 },
72078 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72079 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03400 }
72080 },
72081/* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
72082 {
72083 { 0, 0, 0, 0 },
72084 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72085 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03400 }
72086 },
72087/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
72088 {
72089 { 0, 0, 0, 0 },
72090 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72091 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20400 }
72092 },
72093/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
72094 {
72095 { 0, 0, 0, 0 },
72096 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72097 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22400 }
72098 },
72099/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
72100 {
72101 { 0, 0, 0, 0 },
72102 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72103 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23400 }
72104 },
72105/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
72106 {
72107 { 0, 0, 0, 0 },
72108 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72109 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23400 }
72110 },
72111/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
72112 {
72113 { 0, 0, 0, 0 },
72114 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72115 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40400 }
72116 },
72117/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
72118 {
72119 { 0, 0, 0, 0 },
72120 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72121 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42400 }
72122 },
72123/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
72124 {
72125 { 0, 0, 0, 0 },
72126 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72127 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43400 }
72128 },
72129/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
72130 {
72131 { 0, 0, 0, 0 },
72132 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72133 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43400 }
72134 },
72135/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
72136 {
72137 { 0, 0, 0, 0 },
72138 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72139 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60400 }
72140 },
72141/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
72142 {
72143 { 0, 0, 0, 0 },
72144 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72145 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62400 }
72146 },
72147/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
72148 {
72149 { 0, 0, 0, 0 },
72150 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72151 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63400 }
72152 },
72153/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
72154 {
72155 { 0, 0, 0, 0 },
72156 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72157 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63400 }
72158 },
72159/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
72160 {
72161 { 0, 0, 0, 0 },
72162 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72163 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28400 }
72164 },
72165/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
72166 {
72167 { 0, 0, 0, 0 },
72168 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72169 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a400 }
72170 },
72171/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
72172 {
72173 { 0, 0, 0, 0 },
72174 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72175 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b400 }
72176 },
72177/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
72178 {
72179 { 0, 0, 0, 0 },
72180 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72181 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b400 }
72182 },
72183/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
72184 {
72185 { 0, 0, 0, 0 },
72186 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72187 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48400 }
72188 },
72189/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
72190 {
72191 { 0, 0, 0, 0 },
72192 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72193 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a400 }
72194 },
72195/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
72196 {
72197 { 0, 0, 0, 0 },
72198 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72199 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b400 }
72200 },
72201/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
72202 {
72203 { 0, 0, 0, 0 },
72204 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72205 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b400 }
72206 },
72207/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
72208 {
72209 { 0, 0, 0, 0 },
72210 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72211 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c400 }
72212 },
72213/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
72214 {
72215 { 0, 0, 0, 0 },
72216 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72217 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e400 }
72218 },
72219/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
72220 {
72221 { 0, 0, 0, 0 },
72222 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72223 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f400 }
72224 },
72225/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
72226 {
72227 { 0, 0, 0, 0 },
72228 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72229 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f400 }
72230 },
72231/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
72232 {
72233 { 0, 0, 0, 0 },
72234 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72235 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c400 }
72236 },
72237/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
72238 {
72239 { 0, 0, 0, 0 },
72240 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72241 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e400 }
72242 },
72243/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
72244 {
72245 { 0, 0, 0, 0 },
72246 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72247 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f400 }
72248 },
72249/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
72250 {
72251 { 0, 0, 0, 0 },
72252 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72253 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f400 }
72254 },
72255/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
72256 {
72257 { 0, 0, 0, 0 },
72258 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
72259 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c400 }
72260 },
72261/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
72262 {
72263 { 0, 0, 0, 0 },
72264 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
72265 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e400 }
72266 },
72267/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
72268 {
72269 { 0, 0, 0, 0 },
72270 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
72271 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f400 }
72272 },
72273/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
72274 {
72275 { 0, 0, 0, 0 },
72276 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
72277 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f400 }
72278 },
72279/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
72280 {
72281 { 0, 0, 0, 0 },
72282 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
72283 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68400 }
72284 },
72285/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
72286 {
72287 { 0, 0, 0, 0 },
72288 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
72289 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a400 }
72290 },
72291/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
72292 {
72293 { 0, 0, 0, 0 },
72294 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
72295 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b400 }
72296 },
72297/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
72298 {
72299 { 0, 0, 0, 0 },
72300 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
72301 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b400 }
72302 },
72303/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72304 {
72305 { 0, 0, 0, 0 },
72306 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72307 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80400 }
72308 },
72309/* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
72310 {
72311 { 0, 0, 0, 0 },
72312 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
72313 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82400 }
72314 },
72315/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72316 {
72317 { 0, 0, 0, 0 },
72318 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72319 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08400 }
72320 },
72321/* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
72322 {
72323 { 0, 0, 0, 0 },
72324 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
72325 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a400 }
72326 },
72327/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72328 {
72329 { 0, 0, 0, 0 },
72330 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72331 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00400 }
72332 },
72333/* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
72334 {
72335 { 0, 0, 0, 0 },
72336 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72337 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02400 }
72338 },
72339/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
72340 {
72341 { 0, 0, 0, 0 },
72342 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72343 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20400 }
72344 },
72345/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
72346 {
72347 { 0, 0, 0, 0 },
72348 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72349 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22400 }
72350 },
72351/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
72352 {
72353 { 0, 0, 0, 0 },
72354 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72355 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40400 }
72356 },
72357/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
72358 {
72359 { 0, 0, 0, 0 },
72360 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72361 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42400 }
72362 },
72363/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
72364 {
72365 { 0, 0, 0, 0 },
72366 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72367 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60400 }
72368 },
72369/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
72370 {
72371 { 0, 0, 0, 0 },
72372 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72373 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62400 }
72374 },
72375/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
72376 {
72377 { 0, 0, 0, 0 },
72378 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
72379 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28400 }
72380 },
72381/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
72382 {
72383 { 0, 0, 0, 0 },
72384 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
72385 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a400 }
72386 },
72387/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
72388 {
72389 { 0, 0, 0, 0 },
72390 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
72391 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48400 }
72392 },
72393/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
72394 {
72395 { 0, 0, 0, 0 },
72396 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
72397 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a400 }
72398 },
72399/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
72400 {
72401 { 0, 0, 0, 0 },
72402 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
72403 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c400 }
72404 },
72405/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
72406 {
72407 { 0, 0, 0, 0 },
72408 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
72409 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e400 }
72410 },
72411/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
72412 {
72413 { 0, 0, 0, 0 },
72414 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
72415 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c400 }
72416 },
72417/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
72418 {
72419 { 0, 0, 0, 0 },
72420 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
72421 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e400 }
72422 },
72423/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
72424 {
72425 { 0, 0, 0, 0 },
72426 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
72427 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c400 }
72428 },
72429/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
72430 {
72431 { 0, 0, 0, 0 },
72432 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
72433 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e400 }
72434 },
72435/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
72436 {
72437 { 0, 0, 0, 0 },
72438 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
72439 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68400 }
72440 },
72441/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
72442 {
72443 { 0, 0, 0, 0 },
72444 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
72445 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a400 }
72446 },
72447/* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
72448 {
72449 { 0, 0, 0, 0 },
72450 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
72451 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c804 }
72452 },
72453/* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
72454 {
72455 { 0, 0, 0, 0 },
72456 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
72457 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18824 }
72458 },
72459/* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
72460 {
72461 { 0, 0, 0, 0 },
72462 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72463 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18804 }
72464 },
72465/* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
72466 {
72467 { 0, 0, 0, 0 },
72468 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
72469 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c084 }
72470 },
72471/* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
72472 {
72473 { 0, 0, 0, 0 },
72474 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
72475 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a4 }
72476 },
72477/* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
72478 {
72479 { 0, 0, 0, 0 },
72480 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72481 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18084 }
72482 },
72483/* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
72484 {
72485 { 0, 0, 0, 0 },
72486 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72487 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c004 }
72488 },
72489/* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
72490 {
72491 { 0, 0, 0, 0 },
72492 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72493 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18024 }
72494 },
72495/* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
72496 {
72497 { 0, 0, 0, 0 },
72498 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72499 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18004 }
72500 },
72501/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72502 {
72503 { 0, 0, 0, 0 },
72504 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72505 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20400 }
72506 },
72507/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72508 {
72509 { 0, 0, 0, 0 },
72510 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72511 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822400 }
72512 },
72513/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
72514 {
72515 { 0, 0, 0, 0 },
72516 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72517 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820400 }
72518 },
72519/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72520 {
72521 { 0, 0, 0, 0 },
72522 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72523 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40400 }
72524 },
72525/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72526 {
72527 { 0, 0, 0, 0 },
72528 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72529 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842400 }
72530 },
72531/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
72532 {
72533 { 0, 0, 0, 0 },
72534 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72535 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840400 }
72536 },
72537/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72538 {
72539 { 0, 0, 0, 0 },
72540 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72541 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60400 }
72542 },
72543/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72544 {
72545 { 0, 0, 0, 0 },
72546 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72547 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862400 }
72548 },
72549/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
72550 {
72551 { 0, 0, 0, 0 },
72552 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72553 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860400 }
72554 },
72555/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
72556 {
72557 { 0, 0, 0, 0 },
72558 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72559 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28400 }
72560 },
72561/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
72562 {
72563 { 0, 0, 0, 0 },
72564 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72565 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a400 }
72566 },
72567/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
72568 {
72569 { 0, 0, 0, 0 },
72570 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72571 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828400 }
72572 },
72573/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
72574 {
72575 { 0, 0, 0, 0 },
72576 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72577 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48400 }
72578 },
72579/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
72580 {
72581 { 0, 0, 0, 0 },
72582 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72583 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a400 }
72584 },
72585/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
72586 {
72587 { 0, 0, 0, 0 },
72588 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72589 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848400 }
72590 },
72591/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
72592 {
72593 { 0, 0, 0, 0 },
72594 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72595 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c400 }
72596 },
72597/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
72598 {
72599 { 0, 0, 0, 0 },
72600 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72601 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e400 }
72602 },
72603/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
72604 {
72605 { 0, 0, 0, 0 },
72606 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72607 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c400 }
72608 },
72609/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
72610 {
72611 { 0, 0, 0, 0 },
72612 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72613 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c400 }
72614 },
72615/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
72616 {
72617 { 0, 0, 0, 0 },
72618 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72619 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e400 }
72620 },
72621/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
72622 {
72623 { 0, 0, 0, 0 },
72624 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72625 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c400 }
72626 },
72627/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
72628 {
72629 { 0, 0, 0, 0 },
72630 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
72631 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c400 }
72632 },
72633/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
72634 {
72635 { 0, 0, 0, 0 },
72636 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
72637 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e400 }
72638 },
72639/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
72640 {
72641 { 0, 0, 0, 0 },
72642 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
72643 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c400 }
72644 },
72645/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
72646 {
72647 { 0, 0, 0, 0 },
72648 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
72649 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68400 }
72650 },
72651/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
72652 {
72653 { 0, 0, 0, 0 },
72654 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
72655 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a400 }
72656 },
72657/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
72658 {
72659 { 0, 0, 0, 0 },
72660 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
72661 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868400 }
72662 },
72663/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
72664 {
72665 { 0, 0, 0, 0 },
72666 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
72667 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb18000 }
72668 },
72669/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
72670 {
72671 { 0, 0, 0, 0 },
72672 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
72673 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1a000 }
72674 },
72675/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
72676 {
72677 { 0, 0, 0, 0 },
72678 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
72679 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb1b000 }
72680 },
72681/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
72682 {
72683 { 0, 0, 0, 0 },
72684 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
72685 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb18400 }
72686 },
72687/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
72688 {
72689 { 0, 0, 0, 0 },
72690 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
72691 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb1a400 }
72692 },
72693/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
72694 {
72695 { 0, 0, 0, 0 },
72696 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
72697 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb1b400 }
72698 },
72699/* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
72700 {
72701 { 0, 0, 0, 0 },
72702 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
72703 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb18600 }
72704 },
72705/* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
72706 {
72707 { 0, 0, 0, 0 },
72708 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
72709 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb1a600 }
72710 },
72711/* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
72712 {
72713 { 0, 0, 0, 0 },
72714 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
72715 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb1b600 }
72716 },
72717/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
72718 {
72719 { 0, 0, 0, 0 },
72720 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
72721 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb1880000 }
72722 },
72723/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
72724 {
72725 { 0, 0, 0, 0 },
72726 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
72727 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1a80000 }
72728 },
72729/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
72730 {
72731 { 0, 0, 0, 0 },
72732 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
72733 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1b80000 }
72734 },
72735/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
72736 {
72737 { 0, 0, 0, 0 },
72738 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
72739 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb18c0000 }
72740 },
72741/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
72742 {
72743 { 0, 0, 0, 0 },
72744 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
72745 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1ac0000 }
72746 },
72747/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
72748 {
72749 { 0, 0, 0, 0 },
72750 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
72751 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1bc0000 }
72752 },
72753/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
72754 {
72755 { 0, 0, 0, 0 },
72756 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72757 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb18a0000 }
72758 },
72759/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
72760 {
72761 { 0, 0, 0, 0 },
72762 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72763 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1aa0000 }
72764 },
72765/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
72766 {
72767 { 0, 0, 0, 0 },
72768 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72769 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1ba0000 }
72770 },
72771/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
72772 {
72773 { 0, 0, 0, 0 },
72774 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72775 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb18e0000 }
72776 },
72777/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
72778 {
72779 { 0, 0, 0, 0 },
72780 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72781 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1ae0000 }
72782 },
72783/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
72784 {
72785 { 0, 0, 0, 0 },
72786 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72787 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1be0000 }
72788 },
72789/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
72790 {
72791 { 0, 0, 0, 0 },
72792 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72793 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb18b0000 }
72794 },
72795/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
72796 {
72797 { 0, 0, 0, 0 },
72798 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72799 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1ab0000 }
72800 },
72801/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
72802 {
72803 { 0, 0, 0, 0 },
72804 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72805 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1bb0000 }
72806 },
72807/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
72808 {
72809 { 0, 0, 0, 0 },
72810 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
72811 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb18f0000 }
72812 },
72813/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
72814 {
72815 { 0, 0, 0, 0 },
72816 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
72817 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb1af0000 }
72818 },
72819/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
72820 {
72821 { 0, 0, 0, 0 },
72822 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
72823 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb1bf0000 }
72824 },
72825/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
72826 {
72827 { 0, 0, 0, 0 },
72828 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
72829 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb1c00000 }
72830 },
72831/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
72832 {
72833 { 0, 0, 0, 0 },
72834 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
72835 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1e00000 }
72836 },
72837/* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
72838 {
72839 { 0, 0, 0, 0 },
72840 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
72841 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb1f00000 }
72842 },
72843/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
72844 {
72845 { 0, 0, 0, 0 },
72846 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
72847 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb1c40000 }
72848 },
72849/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
72850 {
72851 { 0, 0, 0, 0 },
72852 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
72853 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb1e40000 }
72854 },
72855/* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
72856 {
72857 { 0, 0, 0, 0 },
72858 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
72859 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb1f40000 }
72860 },
72861/* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
72862 {
72863 { 0, 0, 0, 0 },
72864 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
72865 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb1c60000 }
72866 },
72867/* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
72868 {
72869 { 0, 0, 0, 0 },
72870 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
72871 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb1e60000 }
72872 },
72873/* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
72874 {
72875 { 0, 0, 0, 0 },
72876 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
72877 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb1f60000 }
72878 },
72879/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
72880 {
72881 { 0, 0, 0, 0 },
72882 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
72883 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb1c80000 }
72884 },
72885/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
72886 {
72887 { 0, 0, 0, 0 },
72888 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
72889 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb1e80000 }
72890 },
72891/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
72892 {
72893 { 0, 0, 0, 0 },
72894 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
72895 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb1f80000 }
72896 },
72897/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
72898 {
72899 { 0, 0, 0, 0 },
72900 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
72901 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb1cc0000 }
72902 },
72903/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
72904 {
72905 { 0, 0, 0, 0 },
72906 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
72907 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb1ec0000 }
72908 },
72909/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
72910 {
72911 { 0, 0, 0, 0 },
72912 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
72913 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb1fc0000 }
72914 },
72915/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
72916 {
72917 { 0, 0, 0, 0 },
72918 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72919 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ca0000 }
72920 },
72921/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
72922 {
72923 { 0, 0, 0, 0 },
72924 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72925 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ea0000 }
72926 },
72927/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
72928 {
72929 { 0, 0, 0, 0 },
72930 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72931 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb1fa0000 }
72932 },
72933/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
72934 {
72935 { 0, 0, 0, 0 },
72936 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72937 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ce0000 }
72938 },
72939/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
72940 {
72941 { 0, 0, 0, 0 },
72942 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72943 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ee0000 }
72944 },
72945/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
72946 {
72947 { 0, 0, 0, 0 },
72948 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72949 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb1fe0000 }
72950 },
72951/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
72952 {
72953 { 0, 0, 0, 0 },
72954 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72955 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1cb0000 }
72956 },
72957/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
72958 {
72959 { 0, 0, 0, 0 },
72960 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72961 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1eb0000 }
72962 },
72963/* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
72964 {
72965 { 0, 0, 0, 0 },
72966 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72967 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb1fb0000 }
72968 },
72969/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
72970 {
72971 { 0, 0, 0, 0 },
72972 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
72973 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb1cf0000 }
72974 },
72975/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
72976 {
72977 { 0, 0, 0, 0 },
72978 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
72979 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb1ef0000 }
72980 },
72981/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
72982 {
72983 { 0, 0, 0, 0 },
72984 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
72985 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb1ff0000 }
72986 },
72987/* adc.w${X} $Src16RnHI,$Dst16RnHI */
72988 {
72989 { 0, 0, 0, 0 },
72990 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
72991 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb100 }
72992 },
72993/* adc.w${X} $Src16AnHI,$Dst16RnHI */
72994 {
72995 { 0, 0, 0, 0 },
72996 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
72997 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb140 }
72998 },
72999/* adc.w${X} [$Src16An],$Dst16RnHI */
73000 {
73001 { 0, 0, 0, 0 },
73002 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
73003 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb160 }
73004 },
73005/* adc.w${X} $Src16RnHI,$Dst16AnHI */
73006 {
73007 { 0, 0, 0, 0 },
73008 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
73009 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb104 }
73010 },
73011/* adc.w${X} $Src16AnHI,$Dst16AnHI */
73012 {
73013 { 0, 0, 0, 0 },
73014 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
73015 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb144 }
73016 },
73017/* adc.w${X} [$Src16An],$Dst16AnHI */
73018 {
73019 { 0, 0, 0, 0 },
73020 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
73021 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb164 }
73022 },
73023/* adc.w${X} $Src16RnHI,[$Dst16An] */
73024 {
73025 { 0, 0, 0, 0 },
73026 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
73027 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb106 }
73028 },
73029/* adc.w${X} $Src16AnHI,[$Dst16An] */
73030 {
73031 { 0, 0, 0, 0 },
73032 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
73033 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb146 }
73034 },
73035/* adc.w${X} [$Src16An],[$Dst16An] */
73036 {
73037 { 0, 0, 0, 0 },
73038 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73039 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb166 }
73040 },
73041/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
73042 {
73043 { 0, 0, 0, 0 },
73044 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73045 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb10800 }
73046 },
73047/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
73048 {
73049 { 0, 0, 0, 0 },
73050 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73051 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb14800 }
73052 },
73053/* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
73054 {
73055 { 0, 0, 0, 0 },
73056 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73057 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb16800 }
73058 },
73059/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
73060 {
73061 { 0, 0, 0, 0 },
73062 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73063 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb10c0000 }
73064 },
73065/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
73066 {
73067 { 0, 0, 0, 0 },
73068 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73069 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb14c0000 }
73070 },
73071/* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
73072 {
73073 { 0, 0, 0, 0 },
73074 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73075 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb16c0000 }
73076 },
73077/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
73078 {
73079 { 0, 0, 0, 0 },
73080 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73081 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb10a00 }
73082 },
73083/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
73084 {
73085 { 0, 0, 0, 0 },
73086 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73087 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb14a00 }
73088 },
73089/* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
73090 {
73091 { 0, 0, 0, 0 },
73092 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73093 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb16a00 }
73094 },
73095/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
73096 {
73097 { 0, 0, 0, 0 },
73098 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73099 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb10e0000 }
73100 },
73101/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
73102 {
73103 { 0, 0, 0, 0 },
73104 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73105 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb14e0000 }
73106 },
73107/* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
73108 {
73109 { 0, 0, 0, 0 },
73110 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73111 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb16e0000 }
73112 },
73113/* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
73114 {
73115 { 0, 0, 0, 0 },
73116 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73117 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb10b00 }
73118 },
73119/* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
73120 {
73121 { 0, 0, 0, 0 },
73122 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73123 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb14b00 }
73124 },
73125/* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
73126 {
73127 { 0, 0, 0, 0 },
73128 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73129 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb16b00 }
73130 },
73131/* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
73132 {
73133 { 0, 0, 0, 0 },
73134 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
73135 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb10f0000 }
73136 },
73137/* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
73138 {
73139 { 0, 0, 0, 0 },
73140 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
73141 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb14f0000 }
73142 },
73143/* adc.w${X} [$Src16An],${Dsp-16-u16} */
73144 {
73145 { 0, 0, 0, 0 },
73146 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
73147 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb16f0000 }
73148 },
73149/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
73150 {
73151 { 0, 0, 0, 0 },
73152 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73153 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb08000 }
73154 },
73155/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
73156 {
73157 { 0, 0, 0, 0 },
73158 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
73159 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0a000 }
73160 },
73161/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
73162 {
73163 { 0, 0, 0, 0 },
73164 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
73165 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb0b000 }
73166 },
73167/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
73168 {
73169 { 0, 0, 0, 0 },
73170 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73171 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb08400 }
73172 },
73173/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
73174 {
73175 { 0, 0, 0, 0 },
73176 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
73177 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb0a400 }
73178 },
73179/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
73180 {
73181 { 0, 0, 0, 0 },
73182 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
73183 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb0b400 }
73184 },
73185/* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
73186 {
73187 { 0, 0, 0, 0 },
73188 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73189 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb08600 }
73190 },
73191/* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
73192 {
73193 { 0, 0, 0, 0 },
73194 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73195 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb0a600 }
73196 },
73197/* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
73198 {
73199 { 0, 0, 0, 0 },
73200 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73201 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb0b600 }
73202 },
73203/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
73204 {
73205 { 0, 0, 0, 0 },
73206 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73207 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb0880000 }
73208 },
73209/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
73210 {
73211 { 0, 0, 0, 0 },
73212 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73213 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0a80000 }
73214 },
73215/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
73216 {
73217 { 0, 0, 0, 0 },
73218 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73219 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0b80000 }
73220 },
73221/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
73222 {
73223 { 0, 0, 0, 0 },
73224 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73225 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb08c0000 }
73226 },
73227/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
73228 {
73229 { 0, 0, 0, 0 },
73230 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73231 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0ac0000 }
73232 },
73233/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
73234 {
73235 { 0, 0, 0, 0 },
73236 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73237 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0bc0000 }
73238 },
73239/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
73240 {
73241 { 0, 0, 0, 0 },
73242 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73243 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb08a0000 }
73244 },
73245/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
73246 {
73247 { 0, 0, 0, 0 },
73248 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73249 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0aa0000 }
73250 },
73251/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
73252 {
73253 { 0, 0, 0, 0 },
73254 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73255 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0ba0000 }
73256 },
73257/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
73258 {
73259 { 0, 0, 0, 0 },
73260 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73261 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb08e0000 }
73262 },
73263/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
73264 {
73265 { 0, 0, 0, 0 },
73266 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73267 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0ae0000 }
73268 },
73269/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
73270 {
73271 { 0, 0, 0, 0 },
73272 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73273 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0be0000 }
73274 },
73275/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
73276 {
73277 { 0, 0, 0, 0 },
73278 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73279 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb08b0000 }
73280 },
73281/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
73282 {
73283 { 0, 0, 0, 0 },
73284 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73285 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0ab0000 }
73286 },
73287/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
73288 {
73289 { 0, 0, 0, 0 },
73290 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73291 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0bb0000 }
73292 },
73293/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
73294 {
73295 { 0, 0, 0, 0 },
73296 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
73297 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb08f0000 }
73298 },
73299/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
73300 {
73301 { 0, 0, 0, 0 },
73302 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73303 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb0af0000 }
73304 },
73305/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
73306 {
73307 { 0, 0, 0, 0 },
73308 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73309 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb0bf0000 }
73310 },
73311/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
73312 {
73313 { 0, 0, 0, 0 },
73314 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73315 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb0c00000 }
73316 },
73317/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
73318 {
73319 { 0, 0, 0, 0 },
73320 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
73321 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0e00000 }
73322 },
73323/* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
73324 {
73325 { 0, 0, 0, 0 },
73326 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
73327 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb0f00000 }
73328 },
73329/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
73330 {
73331 { 0, 0, 0, 0 },
73332 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73333 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb0c40000 }
73334 },
73335/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
73336 {
73337 { 0, 0, 0, 0 },
73338 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
73339 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb0e40000 }
73340 },
73341/* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
73342 {
73343 { 0, 0, 0, 0 },
73344 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
73345 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb0f40000 }
73346 },
73347/* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
73348 {
73349 { 0, 0, 0, 0 },
73350 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73351 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb0c60000 }
73352 },
73353/* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
73354 {
73355 { 0, 0, 0, 0 },
73356 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73357 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb0e60000 }
73358 },
73359/* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
73360 {
73361 { 0, 0, 0, 0 },
73362 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
73363 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb0f60000 }
73364 },
73365/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
73366 {
73367 { 0, 0, 0, 0 },
73368 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73369 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb0c80000 }
73370 },
73371/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
73372 {
73373 { 0, 0, 0, 0 },
73374 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73375 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb0e80000 }
73376 },
73377/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
73378 {
73379 { 0, 0, 0, 0 },
73380 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73381 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb0f80000 }
73382 },
73383/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
73384 {
73385 { 0, 0, 0, 0 },
73386 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73387 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb0cc0000 }
73388 },
73389/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
73390 {
73391 { 0, 0, 0, 0 },
73392 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73393 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb0ec0000 }
73394 },
73395/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
73396 {
73397 { 0, 0, 0, 0 },
73398 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73399 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb0fc0000 }
73400 },
73401/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
73402 {
73403 { 0, 0, 0, 0 },
73404 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73405 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ca0000 }
73406 },
73407/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
73408 {
73409 { 0, 0, 0, 0 },
73410 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73411 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ea0000 }
73412 },
73413/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
73414 {
73415 { 0, 0, 0, 0 },
73416 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73417 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb0fa0000 }
73418 },
73419/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
73420 {
73421 { 0, 0, 0, 0 },
73422 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73423 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ce0000 }
73424 },
73425/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
73426 {
73427 { 0, 0, 0, 0 },
73428 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73429 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ee0000 }
73430 },
73431/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
73432 {
73433 { 0, 0, 0, 0 },
73434 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73435 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb0fe0000 }
73436 },
73437/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
73438 {
73439 { 0, 0, 0, 0 },
73440 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73441 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0cb0000 }
73442 },
73443/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
73444 {
73445 { 0, 0, 0, 0 },
73446 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73447 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0eb0000 }
73448 },
73449/* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
73450 {
73451 { 0, 0, 0, 0 },
73452 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73453 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb0fb0000 }
73454 },
73455/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
73456 {
73457 { 0, 0, 0, 0 },
73458 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
73459 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb0cf0000 }
73460 },
73461/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
73462 {
73463 { 0, 0, 0, 0 },
73464 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
73465 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb0ef0000 }
73466 },
73467/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
73468 {
73469 { 0, 0, 0, 0 },
73470 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
73471 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb0ff0000 }
73472 },
73473/* adc.b${X} $Src16RnQI,$Dst16RnQI */
73474 {
73475 { 0, 0, 0, 0 },
73476 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
73477 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb000 }
73478 },
73479/* adc.b${X} $Src16AnQI,$Dst16RnQI */
73480 {
73481 { 0, 0, 0, 0 },
73482 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
73483 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb040 }
73484 },
73485/* adc.b${X} [$Src16An],$Dst16RnQI */
73486 {
73487 { 0, 0, 0, 0 },
73488 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73489 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb060 }
73490 },
73491/* adc.b${X} $Src16RnQI,$Dst16AnQI */
73492 {
73493 { 0, 0, 0, 0 },
73494 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
73495 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb004 }
73496 },
73497/* adc.b${X} $Src16AnQI,$Dst16AnQI */
73498 {
73499 { 0, 0, 0, 0 },
73500 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
73501 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb044 }
73502 },
73503/* adc.b${X} [$Src16An],$Dst16AnQI */
73504 {
73505 { 0, 0, 0, 0 },
73506 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73507 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb064 }
73508 },
73509/* adc.b${X} $Src16RnQI,[$Dst16An] */
73510 {
73511 { 0, 0, 0, 0 },
73512 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
73513 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb006 }
73514 },
73515/* adc.b${X} $Src16AnQI,[$Dst16An] */
73516 {
73517 { 0, 0, 0, 0 },
73518 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
73519 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb046 }
73520 },
73521/* adc.b${X} [$Src16An],[$Dst16An] */
73522 {
73523 { 0, 0, 0, 0 },
73524 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73525 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb066 }
73526 },
73527/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
73528 {
73529 { 0, 0, 0, 0 },
73530 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73531 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb00800 }
73532 },
73533/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
73534 {
73535 { 0, 0, 0, 0 },
73536 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73537 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb04800 }
73538 },
73539/* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
73540 {
73541 { 0, 0, 0, 0 },
73542 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73543 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb06800 }
73544 },
73545/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
73546 {
73547 { 0, 0, 0, 0 },
73548 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73549 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb00c0000 }
73550 },
73551/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
73552 {
73553 { 0, 0, 0, 0 },
73554 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73555 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb04c0000 }
73556 },
73557/* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
73558 {
73559 { 0, 0, 0, 0 },
73560 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73561 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb06c0000 }
73562 },
73563/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
73564 {
73565 { 0, 0, 0, 0 },
73566 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73567 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb00a00 }
73568 },
73569/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
73570 {
73571 { 0, 0, 0, 0 },
73572 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73573 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb04a00 }
73574 },
73575/* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
73576 {
73577 { 0, 0, 0, 0 },
73578 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73579 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb06a00 }
73580 },
73581/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
73582 {
73583 { 0, 0, 0, 0 },
73584 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73585 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb00e0000 }
73586 },
73587/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
73588 {
73589 { 0, 0, 0, 0 },
73590 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73591 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb04e0000 }
73592 },
73593/* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
73594 {
73595 { 0, 0, 0, 0 },
73596 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73597 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb06e0000 }
73598 },
73599/* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
73600 {
73601 { 0, 0, 0, 0 },
73602 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73603 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb00b00 }
73604 },
73605/* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
73606 {
73607 { 0, 0, 0, 0 },
73608 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73609 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb04b00 }
73610 },
73611/* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
73612 {
73613 { 0, 0, 0, 0 },
73614 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73615 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb06b00 }
73616 },
73617/* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
73618 {
73619 { 0, 0, 0, 0 },
73620 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
73621 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb00f0000 }
73622 },
73623/* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
73624 {
73625 { 0, 0, 0, 0 },
73626 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
73627 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb04f0000 }
73628 },
73629/* adc.b${X} [$Src16An],${Dsp-16-u16} */
73630 {
73631 { 0, 0, 0, 0 },
73632 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
73633 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb06f0000 }
73634 },
73635/* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
73636 {
73637 { 0, 0, 0, 0 },
73638 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
73639 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892e00 }
73640 },
73641/* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
73642 {
73643 { 0, 0, 0, 0 },
73644 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
73645 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181ae00 }
73646 },
73647/* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
73648 {
73649 { 0, 0, 0, 0 },
73650 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
73651 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812e00 }
73652 },
73653/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
73654 {
73655 { 0, 0, 0, 0 },
73656 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
73657 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832e00 }
73658 },
73659/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
73660 {
73661 { 0, 0, 0, 0 },
73662 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73663 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ae00 }
73664 },
73665/* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
73666 {
73667 { 0, 0, 0, 0 },
73668 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73669 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ee00 }
73670 },
73671/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
73672 {
73673 { 0, 0, 0, 0 },
73674 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
73675 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852e00 }
73676 },
73677/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
73678 {
73679 { 0, 0, 0, 0 },
73680 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73681 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ae00 }
73682 },
73683/* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
73684 {
73685 { 0, 0, 0, 0 },
73686 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
73687 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ee00 }
73688 },
73689/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
73690 {
73691 { 0, 0, 0, 0 },
73692 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
73693 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ee00 }
73694 },
73695/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
73696 {
73697 { 0, 0, 0, 0 },
73698 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
73699 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872e00 }
73700 },
73701/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
73702 {
73703 { 0, 0, 0, 0 },
73704 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
73705 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187ae00 }
73706 },
73707/* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
73708 {
73709 { 0, 0, 0, 0 },
73710 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
73711 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882e00 }
73712 },
73713/* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
73714 {
73715 { 0, 0, 0, 0 },
73716 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
73717 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180ae00 }
73718 },
73719/* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
73720 {
73721 { 0, 0, 0, 0 },
73722 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
73723 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802e00 }
73724 },
73725/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
73726 {
73727 { 0, 0, 0, 0 },
73728 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
73729 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822e00 }
73730 },
73731/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
73732 {
73733 { 0, 0, 0, 0 },
73734 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73735 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ae00 }
73736 },
73737/* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
73738 {
73739 { 0, 0, 0, 0 },
73740 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73741 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ee00 }
73742 },
73743/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
73744 {
73745 { 0, 0, 0, 0 },
73746 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
73747 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842e00 }
73748 },
73749/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
73750 {
73751 { 0, 0, 0, 0 },
73752 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73753 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ae00 }
73754 },
73755/* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
73756 {
73757 { 0, 0, 0, 0 },
73758 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
73759 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ee00 }
73760 },
73761/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
73762 {
73763 { 0, 0, 0, 0 },
73764 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
73765 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ee00 }
73766 },
73767/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
73768 {
73769 { 0, 0, 0, 0 },
73770 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
73771 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862e00 }
73772 },
73773/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
73774 {
73775 { 0, 0, 0, 0 },
73776 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
73777 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186ae00 }
73778 },
73779/* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
73780 {
73781 { 0, 0, 0, 0 },
73782 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
73783 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77600000 }
73784 },
73785/* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
73786 {
73787 { 0, 0, 0, 0 },
73788 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
73789 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77640000 }
73790 },
73791/* adc.w${X} #${Imm-16-HI},[$Dst16An] */
73792 {
73793 { 0, 0, 0, 0 },
73794 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
73795 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77660000 }
73796 },
73797/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
73798 {
73799 { 0, 0, 0, 0 },
73800 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73801 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77680000 }
73802 },
73803/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
73804 {
73805 { 0, 0, 0, 0 },
73806 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73807 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x776a0000 }
73808 },
73809/* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
73810 {
73811 { 0, 0, 0, 0 },
73812 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73813 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x776b0000 }
73814 },
73815/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
73816 {
73817 { 0, 0, 0, 0 },
73818 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73819 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x776c0000 }
73820 },
73821/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
73822 {
73823 { 0, 0, 0, 0 },
73824 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73825 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x776e0000 }
73826 },
73827/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
73828 {
73829 { 0, 0, 0, 0 },
73830 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
73831 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x776f0000 }
73832 },
73833/* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
73834 {
73835 { 0, 0, 0, 0 },
73836 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
73837 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x766000 }
73838 },
73839/* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
73840 {
73841 { 0, 0, 0, 0 },
73842 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
73843 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x766400 }
73844 },
73845/* adc.b${X} #${Imm-16-QI},[$Dst16An] */
73846 {
73847 { 0, 0, 0, 0 },
73848 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
73849 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x766600 }
73850 },
73851/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
73852 {
73853 { 0, 0, 0, 0 },
73854 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73855 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76680000 }
73856 },
73857/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
73858 {
73859 { 0, 0, 0, 0 },
73860 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73861 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x766a0000 }
73862 },
73863/* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
73864 {
73865 { 0, 0, 0, 0 },
73866 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73867 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x766b0000 }
73868 },
73869/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
73870 {
73871 { 0, 0, 0, 0 },
73872 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73873 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x766c0000 }
73874 },
73875/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
73876 {
73877 { 0, 0, 0, 0 },
73878 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73879 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x766e0000 }
73880 },
73881/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
73882 {
73883 { 0, 0, 0, 0 },
73884 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
73885 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x766f0000 }
73886 },
73887/* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
73888 {
73889 { 0, 0, 0, 0 },
73890 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
73891 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x27000000 }
73892 },
73893/* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
73894 {
73895 { 0, 0, 0, 0 },
73896 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
73897 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x37000000 }
73898 },
73899/* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
73900 {
73901 { 0, 0, 0, 0 },
73902 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
73903 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x17000000 }
73904 },
73905/* add.w${S} #${Imm-8-HI},r0 */
73906 {
73907 { 0, 0, 0, 0 },
73908 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
73909 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x70000 }
73910 },
73911/* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
73912 {
73913 { 0, 0, 0, 0 },
73914 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
73915 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x260000 }
73916 },
73917/* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
73918 {
73919 { 0, 0, 0, 0 },
73920 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
73921 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x360000 }
73922 },
73923/* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
73924 {
73925 { 0, 0, 0, 0 },
73926 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
73927 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x16000000 }
73928 },
73929/* add.b${S} #${Imm-8-QI},r0l */
73930 {
73931 { 0, 0, 0, 0 },
73932 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
73933 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x600 }
73934 },
73935/* add.l${S} #${Imm1-S},a0 */
73936 {
73937 { 0, 0, 0, 0 },
73938 { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '0', 0 } },
73939 & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI, { 0x8c }
73940 },
73941/* add.l${S} #${Imm1-S},a1 */
73942 {
73943 { 0, 0, 0, 0 },
73944 { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '1', 0 } },
73945 & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI, { 0x8d }
73946 },
73947/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
73948 {
73949 { 0, 0, 0, 0 },
73950 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
73951 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990200 }
73952 },
73953/* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
73954 {
73955 { 0, 0, 0, 0 },
73956 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
73957 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992200 }
73958 },
73959/* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
73960 {
73961 { 0, 0, 0, 0 },
73962 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
73963 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993200 }
73964 },
73965/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
73966 {
73967 { 0, 0, 0, 0 },
73968 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
73969 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918200 }
73970 },
73971/* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
73972 {
73973 { 0, 0, 0, 0 },
73974 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
73975 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a200 }
73976 },
73977/* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
73978 {
73979 { 0, 0, 0, 0 },
73980 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
73981 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b200 }
73982 },
73983/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
73984 {
73985 { 0, 0, 0, 0 },
73986 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
73987 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910200 }
73988 },
73989/* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
73990 {
73991 { 0, 0, 0, 0 },
73992 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
73993 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912200 }
73994 },
73995/* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
73996 {
73997 { 0, 0, 0, 0 },
73998 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
73999 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913200 }
74000 },
74001/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74002 {
74003 { 0, 0, 0, 0 },
74004 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74005 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93020000 }
74006 },
74007/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74008 {
74009 { 0, 0, 0, 0 },
74010 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74011 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93220000 }
74012 },
74013/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74014 {
74015 { 0, 0, 0, 0 },
74016 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74017 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93320000 }
74018 },
74019/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74020 {
74021 { 0, 0, 0, 0 },
74022 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74023 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95020000 }
74024 },
74025/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74026 {
74027 { 0, 0, 0, 0 },
74028 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74029 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95220000 }
74030 },
74031/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74032 {
74033 { 0, 0, 0, 0 },
74034 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74035 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95320000 }
74036 },
74037/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74038 {
74039 { 0, 0, 0, 0 },
74040 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74041 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97020000 }
74042 },
74043/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74044 {
74045 { 0, 0, 0, 0 },
74046 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74047 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97220000 }
74048 },
74049/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74050 {
74051 { 0, 0, 0, 0 },
74052 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74053 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97320000 }
74054 },
74055/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
74056 {
74057 { 0, 0, 0, 0 },
74058 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74059 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93820000 }
74060 },
74061/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
74062 {
74063 { 0, 0, 0, 0 },
74064 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74065 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a20000 }
74066 },
74067/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
74068 {
74069 { 0, 0, 0, 0 },
74070 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74071 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b20000 }
74072 },
74073/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
74074 {
74075 { 0, 0, 0, 0 },
74076 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74077 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95820000 }
74078 },
74079/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
74080 {
74081 { 0, 0, 0, 0 },
74082 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74083 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a20000 }
74084 },
74085/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
74086 {
74087 { 0, 0, 0, 0 },
74088 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74089 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b20000 }
74090 },
74091/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
74092 {
74093 { 0, 0, 0, 0 },
74094 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74095 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c20000 }
74096 },
74097/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
74098 {
74099 { 0, 0, 0, 0 },
74100 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74101 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e20000 }
74102 },
74103/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
74104 {
74105 { 0, 0, 0, 0 },
74106 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74107 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f20000 }
74108 },
74109/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
74110 {
74111 { 0, 0, 0, 0 },
74112 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74113 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c20000 }
74114 },
74115/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
74116 {
74117 { 0, 0, 0, 0 },
74118 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74119 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e20000 }
74120 },
74121/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
74122 {
74123 { 0, 0, 0, 0 },
74124 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74125 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f20000 }
74126 },
74127/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
74128 {
74129 { 0, 0, 0, 0 },
74130 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
74131 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c20000 }
74132 },
74133/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
74134 {
74135 { 0, 0, 0, 0 },
74136 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
74137 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e20000 }
74138 },
74139/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
74140 {
74141 { 0, 0, 0, 0 },
74142 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
74143 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f20000 }
74144 },
74145/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
74146 {
74147 { 0, 0, 0, 0 },
74148 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
74149 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97820000 }
74150 },
74151/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
74152 {
74153 { 0, 0, 0, 0 },
74154 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
74155 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a20000 }
74156 },
74157/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
74158 {
74159 { 0, 0, 0, 0 },
74160 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
74161 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b20000 }
74162 },
74163/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74164 {
74165 { 0, 0, 0, 0 },
74166 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74167 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9020000 }
74168 },
74169/* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
74170 {
74171 { 0, 0, 0, 0 },
74172 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74173 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9220000 }
74174 },
74175/* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
74176 {
74177 { 0, 0, 0, 0 },
74178 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74179 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9320000 }
74180 },
74181/* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
74182 {
74183 { 0, 0, 0, 0 },
74184 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74185 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9320000 }
74186 },
74187/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74188 {
74189 { 0, 0, 0, 0 },
74190 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74191 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1820000 }
74192 },
74193/* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
74194 {
74195 { 0, 0, 0, 0 },
74196 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74197 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a20000 }
74198 },
74199/* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
74200 {
74201 { 0, 0, 0, 0 },
74202 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74203 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b20000 }
74204 },
74205/* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
74206 {
74207 { 0, 0, 0, 0 },
74208 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74209 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b20000 }
74210 },
74211/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74212 {
74213 { 0, 0, 0, 0 },
74214 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74215 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1020000 }
74216 },
74217/* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
74218 {
74219 { 0, 0, 0, 0 },
74220 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74221 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1220000 }
74222 },
74223/* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
74224 {
74225 { 0, 0, 0, 0 },
74226 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74227 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1320000 }
74228 },
74229/* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
74230 {
74231 { 0, 0, 0, 0 },
74232 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74233 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1320000 }
74234 },
74235/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74236 {
74237 { 0, 0, 0, 0 },
74238 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74239 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3020000 }
74240 },
74241/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74242 {
74243 { 0, 0, 0, 0 },
74244 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74245 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3220000 }
74246 },
74247/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74248 {
74249 { 0, 0, 0, 0 },
74250 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74251 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3320000 }
74252 },
74253/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
74254 {
74255 { 0, 0, 0, 0 },
74256 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74257 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3320000 }
74258 },
74259/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74260 {
74261 { 0, 0, 0, 0 },
74262 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74263 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5020000 }
74264 },
74265/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74266 {
74267 { 0, 0, 0, 0 },
74268 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74269 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5220000 }
74270 },
74271/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74272 {
74273 { 0, 0, 0, 0 },
74274 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74275 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5320000 }
74276 },
74277/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
74278 {
74279 { 0, 0, 0, 0 },
74280 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74281 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5320000 }
74282 },
74283/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74284 {
74285 { 0, 0, 0, 0 },
74286 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74287 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7020000 }
74288 },
74289/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74290 {
74291 { 0, 0, 0, 0 },
74292 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74293 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7220000 }
74294 },
74295/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74296 {
74297 { 0, 0, 0, 0 },
74298 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74299 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7320000 }
74300 },
74301/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
74302 {
74303 { 0, 0, 0, 0 },
74304 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74305 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7320000 }
74306 },
74307/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
74308 {
74309 { 0, 0, 0, 0 },
74310 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74311 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3820000 }
74312 },
74313/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
74314 {
74315 { 0, 0, 0, 0 },
74316 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74317 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a20000 }
74318 },
74319/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
74320 {
74321 { 0, 0, 0, 0 },
74322 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74323 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b20000 }
74324 },
74325/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
74326 {
74327 { 0, 0, 0, 0 },
74328 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74329 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b20000 }
74330 },
74331/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
74332 {
74333 { 0, 0, 0, 0 },
74334 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74335 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5820000 }
74336 },
74337/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
74338 {
74339 { 0, 0, 0, 0 },
74340 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74341 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a20000 }
74342 },
74343/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
74344 {
74345 { 0, 0, 0, 0 },
74346 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74347 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b20000 }
74348 },
74349/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
74350 {
74351 { 0, 0, 0, 0 },
74352 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74353 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b20000 }
74354 },
74355/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
74356 {
74357 { 0, 0, 0, 0 },
74358 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74359 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c20000 }
74360 },
74361/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
74362 {
74363 { 0, 0, 0, 0 },
74364 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74365 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e20000 }
74366 },
74367/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
74368 {
74369 { 0, 0, 0, 0 },
74370 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74371 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f20000 }
74372 },
74373/* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
74374 {
74375 { 0, 0, 0, 0 },
74376 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74377 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f20000 }
74378 },
74379/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
74380 {
74381 { 0, 0, 0, 0 },
74382 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74383 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c20000 }
74384 },
74385/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
74386 {
74387 { 0, 0, 0, 0 },
74388 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74389 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e20000 }
74390 },
74391/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
74392 {
74393 { 0, 0, 0, 0 },
74394 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74395 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f20000 }
74396 },
74397/* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
74398 {
74399 { 0, 0, 0, 0 },
74400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74401 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f20000 }
74402 },
74403/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
74404 {
74405 { 0, 0, 0, 0 },
74406 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
74407 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c20000 }
74408 },
74409/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
74410 {
74411 { 0, 0, 0, 0 },
74412 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
74413 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e20000 }
74414 },
74415/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
74416 {
74417 { 0, 0, 0, 0 },
74418 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
74419 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f20000 }
74420 },
74421/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
74422 {
74423 { 0, 0, 0, 0 },
74424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
74425 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f20000 }
74426 },
74427/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
74428 {
74429 { 0, 0, 0, 0 },
74430 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
74431 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7820000 }
74432 },
74433/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
74434 {
74435 { 0, 0, 0, 0 },
74436 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
74437 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a20000 }
74438 },
74439/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
74440 {
74441 { 0, 0, 0, 0 },
74442 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
74443 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b20000 }
74444 },
74445/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
74446 {
74447 { 0, 0, 0, 0 },
74448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
74449 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b20000 }
74450 },
74451/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74452 {
74453 { 0, 0, 0, 0 },
74454 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74455 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9020000 }
74456 },
74457/* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
74458 {
74459 { 0, 0, 0, 0 },
74460 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74461 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9220000 }
74462 },
74463/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74464 {
74465 { 0, 0, 0, 0 },
74466 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74467 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1820000 }
74468 },
74469/* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
74470 {
74471 { 0, 0, 0, 0 },
74472 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74473 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a20000 }
74474 },
74475/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74476 {
74477 { 0, 0, 0, 0 },
74478 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74479 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1020000 }
74480 },
74481/* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
74482 {
74483 { 0, 0, 0, 0 },
74484 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74485 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1220000 }
74486 },
74487/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
74488 {
74489 { 0, 0, 0, 0 },
74490 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74491 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3020000 }
74492 },
74493/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
74494 {
74495 { 0, 0, 0, 0 },
74496 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74497 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3220000 }
74498 },
74499/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
74500 {
74501 { 0, 0, 0, 0 },
74502 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74503 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5020000 }
74504 },
74505/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
74506 {
74507 { 0, 0, 0, 0 },
74508 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74509 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5220000 }
74510 },
74511/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
74512 {
74513 { 0, 0, 0, 0 },
74514 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74515 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7020000 }
74516 },
74517/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
74518 {
74519 { 0, 0, 0, 0 },
74520 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74521 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7220000 }
74522 },
74523/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
74524 {
74525 { 0, 0, 0, 0 },
74526 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
74527 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3820000 }
74528 },
74529/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
74530 {
74531 { 0, 0, 0, 0 },
74532 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
74533 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a20000 }
74534 },
74535/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
74536 {
74537 { 0, 0, 0, 0 },
74538 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
74539 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5820000 }
74540 },
74541/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
74542 {
74543 { 0, 0, 0, 0 },
74544 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
74545 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a20000 }
74546 },
74547/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
74548 {
74549 { 0, 0, 0, 0 },
74550 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
74551 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c20000 }
74552 },
74553/* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
74554 {
74555 { 0, 0, 0, 0 },
74556 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
74557 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e20000 }
74558 },
74559/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
74560 {
74561 { 0, 0, 0, 0 },
74562 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
74563 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c20000 }
74564 },
74565/* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
74566 {
74567 { 0, 0, 0, 0 },
74568 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
74569 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e20000 }
74570 },
74571/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
74572 {
74573 { 0, 0, 0, 0 },
74574 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
74575 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c20000 }
74576 },
74577/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
74578 {
74579 { 0, 0, 0, 0 },
74580 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
74581 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e20000 }
74582 },
74583/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
74584 {
74585 { 0, 0, 0, 0 },
74586 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
74587 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7820000 }
74588 },
74589/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
74590 {
74591 { 0, 0, 0, 0 },
74592 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
74593 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a20000 }
74594 },
74595/* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
74596 {
74597 { 0, 0, 0, 0 },
74598 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74599 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc902 }
74600 },
74601/* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
74602 {
74603 { 0, 0, 0, 0 },
74604 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74605 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8922 }
74606 },
74607/* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74608 {
74609 { 0, 0, 0, 0 },
74610 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74611 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8902 }
74612 },
74613/* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
74614 {
74615 { 0, 0, 0, 0 },
74616 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74617 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc182 }
74618 },
74619/* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
74620 {
74621 { 0, 0, 0, 0 },
74622 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74623 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a2 }
74624 },
74625/* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74626 {
74627 { 0, 0, 0, 0 },
74628 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74629 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8182 }
74630 },
74631/* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
74632 {
74633 { 0, 0, 0, 0 },
74634 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74635 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc102 }
74636 },
74637/* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
74638 {
74639 { 0, 0, 0, 0 },
74640 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74641 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8122 }
74642 },
74643/* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74644 {
74645 { 0, 0, 0, 0 },
74646 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74647 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8102 }
74648 },
74649/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
74650 {
74651 { 0, 0, 0, 0 },
74652 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74653 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30200 }
74654 },
74655/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
74656 {
74657 { 0, 0, 0, 0 },
74658 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74659 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832200 }
74660 },
74661/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
74662 {
74663 { 0, 0, 0, 0 },
74664 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74665 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830200 }
74666 },
74667/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
74668 {
74669 { 0, 0, 0, 0 },
74670 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74671 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5020000 }
74672 },
74673/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
74674 {
74675 { 0, 0, 0, 0 },
74676 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74677 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85220000 }
74678 },
74679/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
74680 {
74681 { 0, 0, 0, 0 },
74682 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74683 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85020000 }
74684 },
74685/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
74686 {
74687 { 0, 0, 0, 0 },
74688 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74689 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7020000 }
74690 },
74691/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
74692 {
74693 { 0, 0, 0, 0 },
74694 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74695 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87220000 }
74696 },
74697/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
74698 {
74699 { 0, 0, 0, 0 },
74700 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74701 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87020000 }
74702 },
74703/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
74704 {
74705 { 0, 0, 0, 0 },
74706 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
74707 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38200 }
74708 },
74709/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
74710 {
74711 { 0, 0, 0, 0 },
74712 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
74713 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a200 }
74714 },
74715/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
74716 {
74717 { 0, 0, 0, 0 },
74718 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
74719 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838200 }
74720 },
74721/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
74722 {
74723 { 0, 0, 0, 0 },
74724 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
74725 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5820000 }
74726 },
74727/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
74728 {
74729 { 0, 0, 0, 0 },
74730 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
74731 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a20000 }
74732 },
74733/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
74734 {
74735 { 0, 0, 0, 0 },
74736 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
74737 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85820000 }
74738 },
74739/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
74740 {
74741 { 0, 0, 0, 0 },
74742 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74743 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c200 }
74744 },
74745/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
74746 {
74747 { 0, 0, 0, 0 },
74748 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74749 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e200 }
74750 },
74751/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
74752 {
74753 { 0, 0, 0, 0 },
74754 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74755 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c200 }
74756 },
74757/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
74758 {
74759 { 0, 0, 0, 0 },
74760 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
74761 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c20000 }
74762 },
74763/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
74764 {
74765 { 0, 0, 0, 0 },
74766 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
74767 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e20000 }
74768 },
74769/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
74770 {
74771 { 0, 0, 0, 0 },
74772 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
74773 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c20000 }
74774 },
74775/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
74776 {
74777 { 0, 0, 0, 0 },
74778 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
74779 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c20000 }
74780 },
74781/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
74782 {
74783 { 0, 0, 0, 0 },
74784 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
74785 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e20000 }
74786 },
74787/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
74788 {
74789 { 0, 0, 0, 0 },
74790 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
74791 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c20000 }
74792 },
74793/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
74794 {
74795 { 0, 0, 0, 0 },
74796 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
74797 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7820000 }
74798 },
74799/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
74800 {
74801 { 0, 0, 0, 0 },
74802 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
74803 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a20000 }
74804 },
74805/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
74806 {
74807 { 0, 0, 0, 0 },
74808 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
74809 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87820000 }
74810 },
74811/* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
74812 {
74813 { 0, 0, 0, 0 },
74814 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
74815 & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x20 }
74816 },
74817/* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
74818 {
74819 { 0, 0, 0, 0 },
74820 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
74821 & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2100 }
74822 },
74823/* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
74824 {
74825 { 0, 0, 0, 0 },
74826 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
74827 & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2200 }
74828 },
74829/* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
74830 {
74831 { 0, 0, 0, 0 },
74832 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
74833 & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x230000 }
74834 },
74835/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
74836 {
74837 { 0, 0, 0, 0 },
74838 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
74839 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990800 }
74840 },
74841/* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
74842 {
74843 { 0, 0, 0, 0 },
74844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
74845 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992800 }
74846 },
74847/* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
74848 {
74849 { 0, 0, 0, 0 },
74850 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
74851 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993800 }
74852 },
74853/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
74854 {
74855 { 0, 0, 0, 0 },
74856 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
74857 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918800 }
74858 },
74859/* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
74860 {
74861 { 0, 0, 0, 0 },
74862 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
74863 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a800 }
74864 },
74865/* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
74866 {
74867 { 0, 0, 0, 0 },
74868 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
74869 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b800 }
74870 },
74871/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74872 {
74873 { 0, 0, 0, 0 },
74874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74875 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910800 }
74876 },
74877/* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
74878 {
74879 { 0, 0, 0, 0 },
74880 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74881 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912800 }
74882 },
74883/* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
74884 {
74885 { 0, 0, 0, 0 },
74886 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74887 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913800 }
74888 },
74889/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74890 {
74891 { 0, 0, 0, 0 },
74892 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74893 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93080000 }
74894 },
74895/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74896 {
74897 { 0, 0, 0, 0 },
74898 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74899 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93280000 }
74900 },
74901/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74902 {
74903 { 0, 0, 0, 0 },
74904 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74905 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93380000 }
74906 },
74907/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74908 {
74909 { 0, 0, 0, 0 },
74910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74911 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95080000 }
74912 },
74913/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74914 {
74915 { 0, 0, 0, 0 },
74916 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74917 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95280000 }
74918 },
74919/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74920 {
74921 { 0, 0, 0, 0 },
74922 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74923 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95380000 }
74924 },
74925/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74926 {
74927 { 0, 0, 0, 0 },
74928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74929 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97080000 }
74930 },
74931/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74932 {
74933 { 0, 0, 0, 0 },
74934 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74935 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97280000 }
74936 },
74937/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74938 {
74939 { 0, 0, 0, 0 },
74940 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74941 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97380000 }
74942 },
74943/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
74944 {
74945 { 0, 0, 0, 0 },
74946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74947 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93880000 }
74948 },
74949/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
74950 {
74951 { 0, 0, 0, 0 },
74952 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74953 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a80000 }
74954 },
74955/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
74956 {
74957 { 0, 0, 0, 0 },
74958 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74959 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b80000 }
74960 },
74961/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
74962 {
74963 { 0, 0, 0, 0 },
74964 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74965 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95880000 }
74966 },
74967/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
74968 {
74969 { 0, 0, 0, 0 },
74970 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74971 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a80000 }
74972 },
74973/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
74974 {
74975 { 0, 0, 0, 0 },
74976 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74977 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b80000 }
74978 },
74979/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
74980 {
74981 { 0, 0, 0, 0 },
74982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74983 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c80000 }
74984 },
74985/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
74986 {
74987 { 0, 0, 0, 0 },
74988 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74989 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e80000 }
74990 },
74991/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
74992 {
74993 { 0, 0, 0, 0 },
74994 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74995 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f80000 }
74996 },
74997/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
74998 {
74999 { 0, 0, 0, 0 },
75000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75001 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c80000 }
75002 },
75003/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
75004 {
75005 { 0, 0, 0, 0 },
75006 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75007 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e80000 }
75008 },
75009/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
75010 {
75011 { 0, 0, 0, 0 },
75012 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75013 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f80000 }
75014 },
75015/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
75016 {
75017 { 0, 0, 0, 0 },
75018 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
75019 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c80000 }
75020 },
75021/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
75022 {
75023 { 0, 0, 0, 0 },
75024 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75025 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e80000 }
75026 },
75027/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
75028 {
75029 { 0, 0, 0, 0 },
75030 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75031 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f80000 }
75032 },
75033/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
75034 {
75035 { 0, 0, 0, 0 },
75036 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
75037 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97880000 }
75038 },
75039/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
75040 {
75041 { 0, 0, 0, 0 },
75042 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75043 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a80000 }
75044 },
75045/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
75046 {
75047 { 0, 0, 0, 0 },
75048 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75049 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b80000 }
75050 },
75051/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75052 {
75053 { 0, 0, 0, 0 },
75054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75055 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9080000 }
75056 },
75057/* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
75058 {
75059 { 0, 0, 0, 0 },
75060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75061 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9280000 }
75062 },
75063/* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
75064 {
75065 { 0, 0, 0, 0 },
75066 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75067 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9380000 }
75068 },
75069/* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
75070 {
75071 { 0, 0, 0, 0 },
75072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75073 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9380000 }
75074 },
75075/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75076 {
75077 { 0, 0, 0, 0 },
75078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75079 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1880000 }
75080 },
75081/* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
75082 {
75083 { 0, 0, 0, 0 },
75084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75085 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a80000 }
75086 },
75087/* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
75088 {
75089 { 0, 0, 0, 0 },
75090 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75091 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b80000 }
75092 },
75093/* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
75094 {
75095 { 0, 0, 0, 0 },
75096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75097 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b80000 }
75098 },
75099/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75100 {
75101 { 0, 0, 0, 0 },
75102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75103 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1080000 }
75104 },
75105/* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
75106 {
75107 { 0, 0, 0, 0 },
75108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75109 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1280000 }
75110 },
75111/* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
75112 {
75113 { 0, 0, 0, 0 },
75114 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75115 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1380000 }
75116 },
75117/* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
75118 {
75119 { 0, 0, 0, 0 },
75120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75121 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1380000 }
75122 },
75123/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75124 {
75125 { 0, 0, 0, 0 },
75126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75127 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3080000 }
75128 },
75129/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75130 {
75131 { 0, 0, 0, 0 },
75132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75133 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3280000 }
75134 },
75135/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75136 {
75137 { 0, 0, 0, 0 },
75138 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75139 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3380000 }
75140 },
75141/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
75142 {
75143 { 0, 0, 0, 0 },
75144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75145 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3380000 }
75146 },
75147/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75148 {
75149 { 0, 0, 0, 0 },
75150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75151 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5080000 }
75152 },
75153/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75154 {
75155 { 0, 0, 0, 0 },
75156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75157 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5280000 }
75158 },
75159/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75160 {
75161 { 0, 0, 0, 0 },
75162 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75163 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5380000 }
75164 },
75165/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
75166 {
75167 { 0, 0, 0, 0 },
75168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75169 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5380000 }
75170 },
75171/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75172 {
75173 { 0, 0, 0, 0 },
75174 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75175 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7080000 }
75176 },
75177/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75178 {
75179 { 0, 0, 0, 0 },
75180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75181 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7280000 }
75182 },
75183/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75184 {
75185 { 0, 0, 0, 0 },
75186 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75187 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7380000 }
75188 },
75189/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
75190 {
75191 { 0, 0, 0, 0 },
75192 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75193 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7380000 }
75194 },
75195/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
75196 {
75197 { 0, 0, 0, 0 },
75198 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75199 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3880000 }
75200 },
75201/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
75202 {
75203 { 0, 0, 0, 0 },
75204 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75205 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a80000 }
75206 },
75207/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
75208 {
75209 { 0, 0, 0, 0 },
75210 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75211 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b80000 }
75212 },
75213/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
75214 {
75215 { 0, 0, 0, 0 },
75216 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75217 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b80000 }
75218 },
75219/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
75220 {
75221 { 0, 0, 0, 0 },
75222 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75223 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5880000 }
75224 },
75225/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
75226 {
75227 { 0, 0, 0, 0 },
75228 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75229 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a80000 }
75230 },
75231/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
75232 {
75233 { 0, 0, 0, 0 },
75234 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75235 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b80000 }
75236 },
75237/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
75238 {
75239 { 0, 0, 0, 0 },
75240 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75241 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b80000 }
75242 },
75243/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
75244 {
75245 { 0, 0, 0, 0 },
75246 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75247 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c80000 }
75248 },
75249/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
75250 {
75251 { 0, 0, 0, 0 },
75252 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75253 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e80000 }
75254 },
75255/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
75256 {
75257 { 0, 0, 0, 0 },
75258 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75259 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f80000 }
75260 },
75261/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
75262 {
75263 { 0, 0, 0, 0 },
75264 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75265 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f80000 }
75266 },
75267/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
75268 {
75269 { 0, 0, 0, 0 },
75270 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75271 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c80000 }
75272 },
75273/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
75274 {
75275 { 0, 0, 0, 0 },
75276 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75277 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e80000 }
75278 },
75279/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
75280 {
75281 { 0, 0, 0, 0 },
75282 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75283 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f80000 }
75284 },
75285/* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
75286 {
75287 { 0, 0, 0, 0 },
75288 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75289 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f80000 }
75290 },
75291/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
75292 {
75293 { 0, 0, 0, 0 },
75294 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
75295 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c80000 }
75296 },
75297/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
75298 {
75299 { 0, 0, 0, 0 },
75300 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
75301 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e80000 }
75302 },
75303/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
75304 {
75305 { 0, 0, 0, 0 },
75306 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
75307 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f80000 }
75308 },
75309/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
75310 {
75311 { 0, 0, 0, 0 },
75312 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
75313 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f80000 }
75314 },
75315/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
75316 {
75317 { 0, 0, 0, 0 },
75318 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
75319 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7880000 }
75320 },
75321/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
75322 {
75323 { 0, 0, 0, 0 },
75324 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
75325 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a80000 }
75326 },
75327/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
75328 {
75329 { 0, 0, 0, 0 },
75330 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
75331 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b80000 }
75332 },
75333/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
75334 {
75335 { 0, 0, 0, 0 },
75336 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
75337 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b80000 }
75338 },
75339/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75340 {
75341 { 0, 0, 0, 0 },
75342 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75343 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9080000 }
75344 },
75345/* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
75346 {
75347 { 0, 0, 0, 0 },
75348 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75349 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9280000 }
75350 },
75351/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75352 {
75353 { 0, 0, 0, 0 },
75354 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75355 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1880000 }
75356 },
75357/* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
75358 {
75359 { 0, 0, 0, 0 },
75360 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75361 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a80000 }
75362 },
75363/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75364 {
75365 { 0, 0, 0, 0 },
75366 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75367 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1080000 }
75368 },
75369/* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
75370 {
75371 { 0, 0, 0, 0 },
75372 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75373 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1280000 }
75374 },
75375/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
75376 {
75377 { 0, 0, 0, 0 },
75378 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75379 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3080000 }
75380 },
75381/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
75382 {
75383 { 0, 0, 0, 0 },
75384 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75385 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3280000 }
75386 },
75387/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
75388 {
75389 { 0, 0, 0, 0 },
75390 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75391 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5080000 }
75392 },
75393/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
75394 {
75395 { 0, 0, 0, 0 },
75396 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75397 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5280000 }
75398 },
75399/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
75400 {
75401 { 0, 0, 0, 0 },
75402 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75403 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7080000 }
75404 },
75405/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
75406 {
75407 { 0, 0, 0, 0 },
75408 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75409 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7280000 }
75410 },
75411/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
75412 {
75413 { 0, 0, 0, 0 },
75414 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
75415 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3880000 }
75416 },
75417/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
75418 {
75419 { 0, 0, 0, 0 },
75420 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
75421 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a80000 }
75422 },
75423/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
75424 {
75425 { 0, 0, 0, 0 },
75426 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
75427 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5880000 }
75428 },
75429/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
75430 {
75431 { 0, 0, 0, 0 },
75432 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
75433 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a80000 }
75434 },
75435/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
75436 {
75437 { 0, 0, 0, 0 },
75438 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
75439 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c80000 }
75440 },
75441/* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
75442 {
75443 { 0, 0, 0, 0 },
75444 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
75445 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e80000 }
75446 },
75447/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
75448 {
75449 { 0, 0, 0, 0 },
75450 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
75451 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c80000 }
75452 },
75453/* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
75454 {
75455 { 0, 0, 0, 0 },
75456 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
75457 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e80000 }
75458 },
75459/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
75460 {
75461 { 0, 0, 0, 0 },
75462 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
75463 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c80000 }
75464 },
75465/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
75466 {
75467 { 0, 0, 0, 0 },
75468 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
75469 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e80000 }
75470 },
75471/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
75472 {
75473 { 0, 0, 0, 0 },
75474 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
75475 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7880000 }
75476 },
75477/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
75478 {
75479 { 0, 0, 0, 0 },
75480 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
75481 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a80000 }
75482 },
75483/* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
75484 {
75485 { 0, 0, 0, 0 },
75486 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75487 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc908 }
75488 },
75489/* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
75490 {
75491 { 0, 0, 0, 0 },
75492 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75493 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8928 }
75494 },
75495/* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75496 {
75497 { 0, 0, 0, 0 },
75498 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75499 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8908 }
75500 },
75501/* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
75502 {
75503 { 0, 0, 0, 0 },
75504 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75505 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc188 }
75506 },
75507/* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
75508 {
75509 { 0, 0, 0, 0 },
75510 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75511 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a8 }
75512 },
75513/* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75514 {
75515 { 0, 0, 0, 0 },
75516 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75517 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8188 }
75518 },
75519/* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
75520 {
75521 { 0, 0, 0, 0 },
75522 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75523 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc108 }
75524 },
75525/* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
75526 {
75527 { 0, 0, 0, 0 },
75528 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75529 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8128 }
75530 },
75531/* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75532 {
75533 { 0, 0, 0, 0 },
75534 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75535 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8108 }
75536 },
75537/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75538 {
75539 { 0, 0, 0, 0 },
75540 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75541 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30800 }
75542 },
75543/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75544 {
75545 { 0, 0, 0, 0 },
75546 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75547 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832800 }
75548 },
75549/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
75550 {
75551 { 0, 0, 0, 0 },
75552 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75553 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830800 }
75554 },
75555/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75556 {
75557 { 0, 0, 0, 0 },
75558 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75559 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5080000 }
75560 },
75561/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75562 {
75563 { 0, 0, 0, 0 },
75564 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75565 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85280000 }
75566 },
75567/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
75568 {
75569 { 0, 0, 0, 0 },
75570 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75571 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85080000 }
75572 },
75573/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75574 {
75575 { 0, 0, 0, 0 },
75576 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75577 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7080000 }
75578 },
75579/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75580 {
75581 { 0, 0, 0, 0 },
75582 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75583 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87280000 }
75584 },
75585/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
75586 {
75587 { 0, 0, 0, 0 },
75588 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75589 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87080000 }
75590 },
75591/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
75592 {
75593 { 0, 0, 0, 0 },
75594 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75595 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38800 }
75596 },
75597/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
75598 {
75599 { 0, 0, 0, 0 },
75600 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75601 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a800 }
75602 },
75603/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
75604 {
75605 { 0, 0, 0, 0 },
75606 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75607 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838800 }
75608 },
75609/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
75610 {
75611 { 0, 0, 0, 0 },
75612 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75613 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5880000 }
75614 },
75615/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
75616 {
75617 { 0, 0, 0, 0 },
75618 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75619 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a80000 }
75620 },
75621/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
75622 {
75623 { 0, 0, 0, 0 },
75624 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75625 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85880000 }
75626 },
75627/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
75628 {
75629 { 0, 0, 0, 0 },
75630 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75631 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c800 }
75632 },
75633/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
75634 {
75635 { 0, 0, 0, 0 },
75636 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75637 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e800 }
75638 },
75639/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
75640 {
75641 { 0, 0, 0, 0 },
75642 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75643 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c800 }
75644 },
75645/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
75646 {
75647 { 0, 0, 0, 0 },
75648 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75649 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c80000 }
75650 },
75651/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
75652 {
75653 { 0, 0, 0, 0 },
75654 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75655 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e80000 }
75656 },
75657/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
75658 {
75659 { 0, 0, 0, 0 },
75660 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75661 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c80000 }
75662 },
75663/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
75664 {
75665 { 0, 0, 0, 0 },
75666 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
75667 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c80000 }
75668 },
75669/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
75670 {
75671 { 0, 0, 0, 0 },
75672 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
75673 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e80000 }
75674 },
75675/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
75676 {
75677 { 0, 0, 0, 0 },
75678 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
75679 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c80000 }
75680 },
75681/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
75682 {
75683 { 0, 0, 0, 0 },
75684 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
75685 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7880000 }
75686 },
75687/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
75688 {
75689 { 0, 0, 0, 0 },
75690 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
75691 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a80000 }
75692 },
75693/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
75694 {
75695 { 0, 0, 0, 0 },
75696 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
75697 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87880000 }
75698 },
75699/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
75700 {
75701 { 0, 0, 0, 0 },
75702 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
75703 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980800 }
75704 },
75705/* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
75706 {
75707 { 0, 0, 0, 0 },
75708 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
75709 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982800 }
75710 },
75711/* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
75712 {
75713 { 0, 0, 0, 0 },
75714 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
75715 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983800 }
75716 },
75717/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
75718 {
75719 { 0, 0, 0, 0 },
75720 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
75721 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908800 }
75722 },
75723/* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
75724 {
75725 { 0, 0, 0, 0 },
75726 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
75727 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a800 }
75728 },
75729/* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
75730 {
75731 { 0, 0, 0, 0 },
75732 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
75733 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b800 }
75734 },
75735/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75736 {
75737 { 0, 0, 0, 0 },
75738 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75739 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900800 }
75740 },
75741/* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
75742 {
75743 { 0, 0, 0, 0 },
75744 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75745 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902800 }
75746 },
75747/* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
75748 {
75749 { 0, 0, 0, 0 },
75750 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75751 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903800 }
75752 },
75753/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75754 {
75755 { 0, 0, 0, 0 },
75756 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75757 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92080000 }
75758 },
75759/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75760 {
75761 { 0, 0, 0, 0 },
75762 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75763 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92280000 }
75764 },
75765/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75766 {
75767 { 0, 0, 0, 0 },
75768 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75769 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92380000 }
75770 },
75771/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75772 {
75773 { 0, 0, 0, 0 },
75774 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75775 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94080000 }
75776 },
75777/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75778 {
75779 { 0, 0, 0, 0 },
75780 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75781 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94280000 }
75782 },
75783/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75784 {
75785 { 0, 0, 0, 0 },
75786 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75787 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94380000 }
75788 },
75789/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75790 {
75791 { 0, 0, 0, 0 },
75792 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75793 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96080000 }
75794 },
75795/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75796 {
75797 { 0, 0, 0, 0 },
75798 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75799 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96280000 }
75800 },
75801/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75802 {
75803 { 0, 0, 0, 0 },
75804 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75805 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96380000 }
75806 },
75807/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
75808 {
75809 { 0, 0, 0, 0 },
75810 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75811 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92880000 }
75812 },
75813/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
75814 {
75815 { 0, 0, 0, 0 },
75816 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75817 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a80000 }
75818 },
75819/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
75820 {
75821 { 0, 0, 0, 0 },
75822 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75823 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b80000 }
75824 },
75825/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
75826 {
75827 { 0, 0, 0, 0 },
75828 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75829 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94880000 }
75830 },
75831/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
75832 {
75833 { 0, 0, 0, 0 },
75834 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75835 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a80000 }
75836 },
75837/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
75838 {
75839 { 0, 0, 0, 0 },
75840 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75841 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b80000 }
75842 },
75843/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
75844 {
75845 { 0, 0, 0, 0 },
75846 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75847 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c80000 }
75848 },
75849/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
75850 {
75851 { 0, 0, 0, 0 },
75852 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75853 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e80000 }
75854 },
75855/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
75856 {
75857 { 0, 0, 0, 0 },
75858 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75859 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f80000 }
75860 },
75861/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
75862 {
75863 { 0, 0, 0, 0 },
75864 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75865 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c80000 }
75866 },
75867/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
75868 {
75869 { 0, 0, 0, 0 },
75870 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75871 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e80000 }
75872 },
75873/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
75874 {
75875 { 0, 0, 0, 0 },
75876 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75877 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f80000 }
75878 },
75879/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
75880 {
75881 { 0, 0, 0, 0 },
75882 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
75883 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c80000 }
75884 },
75885/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
75886 {
75887 { 0, 0, 0, 0 },
75888 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75889 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e80000 }
75890 },
75891/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
75892 {
75893 { 0, 0, 0, 0 },
75894 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75895 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f80000 }
75896 },
75897/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
75898 {
75899 { 0, 0, 0, 0 },
75900 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
75901 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96880000 }
75902 },
75903/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
75904 {
75905 { 0, 0, 0, 0 },
75906 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75907 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a80000 }
75908 },
75909/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
75910 {
75911 { 0, 0, 0, 0 },
75912 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75913 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b80000 }
75914 },
75915/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
75916 {
75917 { 0, 0, 0, 0 },
75918 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
75919 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8080000 }
75920 },
75921/* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
75922 {
75923 { 0, 0, 0, 0 },
75924 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
75925 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8280000 }
75926 },
75927/* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
75928 {
75929 { 0, 0, 0, 0 },
75930 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
75931 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8380000 }
75932 },
75933/* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
75934 {
75935 { 0, 0, 0, 0 },
75936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
75937 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8380000 }
75938 },
75939/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
75940 {
75941 { 0, 0, 0, 0 },
75942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
75943 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0880000 }
75944 },
75945/* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
75946 {
75947 { 0, 0, 0, 0 },
75948 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
75949 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a80000 }
75950 },
75951/* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
75952 {
75953 { 0, 0, 0, 0 },
75954 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
75955 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b80000 }
75956 },
75957/* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
75958 {
75959 { 0, 0, 0, 0 },
75960 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
75961 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b80000 }
75962 },
75963/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75964 {
75965 { 0, 0, 0, 0 },
75966 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75967 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0080000 }
75968 },
75969/* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
75970 {
75971 { 0, 0, 0, 0 },
75972 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75973 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0280000 }
75974 },
75975/* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
75976 {
75977 { 0, 0, 0, 0 },
75978 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75979 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0380000 }
75980 },
75981/* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
75982 {
75983 { 0, 0, 0, 0 },
75984 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75985 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0380000 }
75986 },
75987/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75988 {
75989 { 0, 0, 0, 0 },
75990 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75991 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2080000 }
75992 },
75993/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75994 {
75995 { 0, 0, 0, 0 },
75996 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75997 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2280000 }
75998 },
75999/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
76000 {
76001 { 0, 0, 0, 0 },
76002 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76003 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2380000 }
76004 },
76005/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
76006 {
76007 { 0, 0, 0, 0 },
76008 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76009 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2380000 }
76010 },
76011/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76012 {
76013 { 0, 0, 0, 0 },
76014 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76015 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4080000 }
76016 },
76017/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76018 {
76019 { 0, 0, 0, 0 },
76020 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76021 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4280000 }
76022 },
76023/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76024 {
76025 { 0, 0, 0, 0 },
76026 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76027 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4380000 }
76028 },
76029/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
76030 {
76031 { 0, 0, 0, 0 },
76032 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76033 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4380000 }
76034 },
76035/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76036 {
76037 { 0, 0, 0, 0 },
76038 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76039 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6080000 }
76040 },
76041/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76042 {
76043 { 0, 0, 0, 0 },
76044 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76045 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6280000 }
76046 },
76047/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76048 {
76049 { 0, 0, 0, 0 },
76050 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76051 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6380000 }
76052 },
76053/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
76054 {
76055 { 0, 0, 0, 0 },
76056 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76057 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6380000 }
76058 },
76059/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
76060 {
76061 { 0, 0, 0, 0 },
76062 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76063 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2880000 }
76064 },
76065/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
76066 {
76067 { 0, 0, 0, 0 },
76068 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76069 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a80000 }
76070 },
76071/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
76072 {
76073 { 0, 0, 0, 0 },
76074 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76075 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b80000 }
76076 },
76077/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
76078 {
76079 { 0, 0, 0, 0 },
76080 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76081 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b80000 }
76082 },
76083/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
76084 {
76085 { 0, 0, 0, 0 },
76086 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76087 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4880000 }
76088 },
76089/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
76090 {
76091 { 0, 0, 0, 0 },
76092 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76093 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a80000 }
76094 },
76095/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
76096 {
76097 { 0, 0, 0, 0 },
76098 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76099 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b80000 }
76100 },
76101/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
76102 {
76103 { 0, 0, 0, 0 },
76104 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76105 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b80000 }
76106 },
76107/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
76108 {
76109 { 0, 0, 0, 0 },
76110 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76111 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c80000 }
76112 },
76113/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
76114 {
76115 { 0, 0, 0, 0 },
76116 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76117 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e80000 }
76118 },
76119/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
76120 {
76121 { 0, 0, 0, 0 },
76122 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76123 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f80000 }
76124 },
76125/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
76126 {
76127 { 0, 0, 0, 0 },
76128 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76129 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f80000 }
76130 },
76131/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
76132 {
76133 { 0, 0, 0, 0 },
76134 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76135 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c80000 }
76136 },
76137/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
76138 {
76139 { 0, 0, 0, 0 },
76140 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76141 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e80000 }
76142 },
76143/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
76144 {
76145 { 0, 0, 0, 0 },
76146 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76147 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f80000 }
76148 },
76149/* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
76150 {
76151 { 0, 0, 0, 0 },
76152 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76153 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f80000 }
76154 },
76155/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
76156 {
76157 { 0, 0, 0, 0 },
76158 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
76159 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c80000 }
76160 },
76161/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
76162 {
76163 { 0, 0, 0, 0 },
76164 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
76165 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e80000 }
76166 },
76167/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
76168 {
76169 { 0, 0, 0, 0 },
76170 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
76171 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f80000 }
76172 },
76173/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
76174 {
76175 { 0, 0, 0, 0 },
76176 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
76177 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f80000 }
76178 },
76179/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
76180 {
76181 { 0, 0, 0, 0 },
76182 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
76183 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6880000 }
76184 },
76185/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
76186 {
76187 { 0, 0, 0, 0 },
76188 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
76189 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a80000 }
76190 },
76191/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
76192 {
76193 { 0, 0, 0, 0 },
76194 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
76195 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b80000 }
76196 },
76197/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
76198 {
76199 { 0, 0, 0, 0 },
76200 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
76201 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b80000 }
76202 },
76203/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76204 {
76205 { 0, 0, 0, 0 },
76206 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76207 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8080000 }
76208 },
76209/* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
76210 {
76211 { 0, 0, 0, 0 },
76212 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76213 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8280000 }
76214 },
76215/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76216 {
76217 { 0, 0, 0, 0 },
76218 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76219 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0880000 }
76220 },
76221/* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
76222 {
76223 { 0, 0, 0, 0 },
76224 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76225 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a80000 }
76226 },
76227/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76228 {
76229 { 0, 0, 0, 0 },
76230 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76231 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0080000 }
76232 },
76233/* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
76234 {
76235 { 0, 0, 0, 0 },
76236 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76237 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0280000 }
76238 },
76239/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
76240 {
76241 { 0, 0, 0, 0 },
76242 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76243 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2080000 }
76244 },
76245/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
76246 {
76247 { 0, 0, 0, 0 },
76248 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76249 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2280000 }
76250 },
76251/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
76252 {
76253 { 0, 0, 0, 0 },
76254 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76255 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4080000 }
76256 },
76257/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
76258 {
76259 { 0, 0, 0, 0 },
76260 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76261 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4280000 }
76262 },
76263/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
76264 {
76265 { 0, 0, 0, 0 },
76266 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76267 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6080000 }
76268 },
76269/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
76270 {
76271 { 0, 0, 0, 0 },
76272 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76273 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6280000 }
76274 },
76275/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
76276 {
76277 { 0, 0, 0, 0 },
76278 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
76279 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2880000 }
76280 },
76281/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
76282 {
76283 { 0, 0, 0, 0 },
76284 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
76285 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a80000 }
76286 },
76287/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
76288 {
76289 { 0, 0, 0, 0 },
76290 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
76291 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4880000 }
76292 },
76293/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
76294 {
76295 { 0, 0, 0, 0 },
76296 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
76297 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a80000 }
76298 },
76299/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
76300 {
76301 { 0, 0, 0, 0 },
76302 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
76303 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c80000 }
76304 },
76305/* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
76306 {
76307 { 0, 0, 0, 0 },
76308 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
76309 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e80000 }
76310 },
76311/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
76312 {
76313 { 0, 0, 0, 0 },
76314 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
76315 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c80000 }
76316 },
76317/* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
76318 {
76319 { 0, 0, 0, 0 },
76320 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
76321 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e80000 }
76322 },
76323/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
76324 {
76325 { 0, 0, 0, 0 },
76326 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
76327 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c80000 }
76328 },
76329/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
76330 {
76331 { 0, 0, 0, 0 },
76332 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
76333 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e80000 }
76334 },
76335/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
76336 {
76337 { 0, 0, 0, 0 },
76338 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
76339 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6880000 }
76340 },
76341/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
76342 {
76343 { 0, 0, 0, 0 },
76344 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
76345 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a80000 }
76346 },
76347/* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
76348 {
76349 { 0, 0, 0, 0 },
76350 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76351 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc808 }
76352 },
76353/* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
76354 {
76355 { 0, 0, 0, 0 },
76356 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76357 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8828 }
76358 },
76359/* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76360 {
76361 { 0, 0, 0, 0 },
76362 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76363 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8808 }
76364 },
76365/* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
76366 {
76367 { 0, 0, 0, 0 },
76368 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76369 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc088 }
76370 },
76371/* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
76372 {
76373 { 0, 0, 0, 0 },
76374 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76375 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a8 }
76376 },
76377/* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76378 {
76379 { 0, 0, 0, 0 },
76380 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76381 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8088 }
76382 },
76383/* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
76384 {
76385 { 0, 0, 0, 0 },
76386 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76387 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc008 }
76388 },
76389/* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
76390 {
76391 { 0, 0, 0, 0 },
76392 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76393 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8028 }
76394 },
76395/* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76396 {
76397 { 0, 0, 0, 0 },
76398 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76399 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8008 }
76400 },
76401/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
76402 {
76403 { 0, 0, 0, 0 },
76404 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76405 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20800 }
76406 },
76407/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
76408 {
76409 { 0, 0, 0, 0 },
76410 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76411 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822800 }
76412 },
76413/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
76414 {
76415 { 0, 0, 0, 0 },
76416 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76417 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820800 }
76418 },
76419/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
76420 {
76421 { 0, 0, 0, 0 },
76422 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76423 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4080000 }
76424 },
76425/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
76426 {
76427 { 0, 0, 0, 0 },
76428 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76429 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84280000 }
76430 },
76431/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
76432 {
76433 { 0, 0, 0, 0 },
76434 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76435 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84080000 }
76436 },
76437/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
76438 {
76439 { 0, 0, 0, 0 },
76440 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76441 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6080000 }
76442 },
76443/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
76444 {
76445 { 0, 0, 0, 0 },
76446 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76447 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86280000 }
76448 },
76449/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
76450 {
76451 { 0, 0, 0, 0 },
76452 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76453 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86080000 }
76454 },
76455/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
76456 {
76457 { 0, 0, 0, 0 },
76458 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76459 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28800 }
76460 },
76461/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
76462 {
76463 { 0, 0, 0, 0 },
76464 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76465 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a800 }
76466 },
76467/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
76468 {
76469 { 0, 0, 0, 0 },
76470 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76471 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828800 }
76472 },
76473/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
76474 {
76475 { 0, 0, 0, 0 },
76476 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76477 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4880000 }
76478 },
76479/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
76480 {
76481 { 0, 0, 0, 0 },
76482 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76483 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a80000 }
76484 },
76485/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
76486 {
76487 { 0, 0, 0, 0 },
76488 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76489 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84880000 }
76490 },
76491/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
76492 {
76493 { 0, 0, 0, 0 },
76494 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76495 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c800 }
76496 },
76497/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
76498 {
76499 { 0, 0, 0, 0 },
76500 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76501 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e800 }
76502 },
76503/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
76504 {
76505 { 0, 0, 0, 0 },
76506 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76507 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c800 }
76508 },
76509/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
76510 {
76511 { 0, 0, 0, 0 },
76512 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76513 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c80000 }
76514 },
76515/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
76516 {
76517 { 0, 0, 0, 0 },
76518 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76519 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e80000 }
76520 },
76521/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
76522 {
76523 { 0, 0, 0, 0 },
76524 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76525 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c80000 }
76526 },
76527/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
76528 {
76529 { 0, 0, 0, 0 },
76530 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
76531 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c80000 }
76532 },
76533/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
76534 {
76535 { 0, 0, 0, 0 },
76536 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
76537 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e80000 }
76538 },
76539/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
76540 {
76541 { 0, 0, 0, 0 },
76542 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
76543 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c80000 }
76544 },
76545/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
76546 {
76547 { 0, 0, 0, 0 },
76548 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
76549 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6880000 }
76550 },
76551/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
76552 {
76553 { 0, 0, 0, 0 },
76554 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
76555 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a80000 }
76556 },
76557/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
76558 {
76559 { 0, 0, 0, 0 },
76560 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
76561 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86880000 }
76562 },
76563/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
76564 {
76565 { 0, 0, 0, 0 },
76566 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
76567 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa18000 }
76568 },
76569/* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
76570 {
76571 { 0, 0, 0, 0 },
76572 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
76573 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1a000 }
76574 },
76575/* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
76576 {
76577 { 0, 0, 0, 0 },
76578 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
76579 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa1b000 }
76580 },
76581/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
76582 {
76583 { 0, 0, 0, 0 },
76584 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
76585 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa18400 }
76586 },
76587/* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
76588 {
76589 { 0, 0, 0, 0 },
76590 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
76591 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa1a400 }
76592 },
76593/* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
76594 {
76595 { 0, 0, 0, 0 },
76596 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
76597 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa1b400 }
76598 },
76599/* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
76600 {
76601 { 0, 0, 0, 0 },
76602 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
76603 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa18600 }
76604 },
76605/* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
76606 {
76607 { 0, 0, 0, 0 },
76608 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
76609 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa1a600 }
76610 },
76611/* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
76612 {
76613 { 0, 0, 0, 0 },
76614 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
76615 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa1b600 }
76616 },
76617/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
76618 {
76619 { 0, 0, 0, 0 },
76620 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
76621 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa1880000 }
76622 },
76623/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
76624 {
76625 { 0, 0, 0, 0 },
76626 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
76627 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1a80000 }
76628 },
76629/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
76630 {
76631 { 0, 0, 0, 0 },
76632 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
76633 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1b80000 }
76634 },
76635/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
76636 {
76637 { 0, 0, 0, 0 },
76638 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
76639 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa18c0000 }
76640 },
76641/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
76642 {
76643 { 0, 0, 0, 0 },
76644 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
76645 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1ac0000 }
76646 },
76647/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
76648 {
76649 { 0, 0, 0, 0 },
76650 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
76651 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1bc0000 }
76652 },
76653/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
76654 {
76655 { 0, 0, 0, 0 },
76656 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76657 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa18a0000 }
76658 },
76659/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
76660 {
76661 { 0, 0, 0, 0 },
76662 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76663 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1aa0000 }
76664 },
76665/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
76666 {
76667 { 0, 0, 0, 0 },
76668 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76669 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1ba0000 }
76670 },
76671/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
76672 {
76673 { 0, 0, 0, 0 },
76674 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76675 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa18e0000 }
76676 },
76677/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
76678 {
76679 { 0, 0, 0, 0 },
76680 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76681 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1ae0000 }
76682 },
76683/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
76684 {
76685 { 0, 0, 0, 0 },
76686 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76687 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1be0000 }
76688 },
76689/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
76690 {
76691 { 0, 0, 0, 0 },
76692 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76693 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa18b0000 }
76694 },
76695/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
76696 {
76697 { 0, 0, 0, 0 },
76698 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76699 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1ab0000 }
76700 },
76701/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
76702 {
76703 { 0, 0, 0, 0 },
76704 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76705 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1bb0000 }
76706 },
76707/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
76708 {
76709 { 0, 0, 0, 0 },
76710 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
76711 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa18f0000 }
76712 },
76713/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
76714 {
76715 { 0, 0, 0, 0 },
76716 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
76717 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa1af0000 }
76718 },
76719/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
76720 {
76721 { 0, 0, 0, 0 },
76722 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
76723 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa1bf0000 }
76724 },
76725/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
76726 {
76727 { 0, 0, 0, 0 },
76728 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
76729 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa1c00000 }
76730 },
76731/* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
76732 {
76733 { 0, 0, 0, 0 },
76734 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
76735 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1e00000 }
76736 },
76737/* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
76738 {
76739 { 0, 0, 0, 0 },
76740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
76741 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa1f00000 }
76742 },
76743/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
76744 {
76745 { 0, 0, 0, 0 },
76746 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
76747 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa1c40000 }
76748 },
76749/* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
76750 {
76751 { 0, 0, 0, 0 },
76752 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
76753 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa1e40000 }
76754 },
76755/* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
76756 {
76757 { 0, 0, 0, 0 },
76758 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
76759 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa1f40000 }
76760 },
76761/* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
76762 {
76763 { 0, 0, 0, 0 },
76764 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
76765 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa1c60000 }
76766 },
76767/* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
76768 {
76769 { 0, 0, 0, 0 },
76770 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
76771 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa1e60000 }
76772 },
76773/* add.w${G} ${Dsp-16-u16},[$Dst16An] */
76774 {
76775 { 0, 0, 0, 0 },
76776 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
76777 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa1f60000 }
76778 },
76779/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
76780 {
76781 { 0, 0, 0, 0 },
76782 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
76783 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa1c80000 }
76784 },
76785/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
76786 {
76787 { 0, 0, 0, 0 },
76788 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
76789 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa1e80000 }
76790 },
76791/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
76792 {
76793 { 0, 0, 0, 0 },
76794 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
76795 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa1f80000 }
76796 },
76797/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
76798 {
76799 { 0, 0, 0, 0 },
76800 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
76801 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa1cc0000 }
76802 },
76803/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
76804 {
76805 { 0, 0, 0, 0 },
76806 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
76807 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa1ec0000 }
76808 },
76809/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
76810 {
76811 { 0, 0, 0, 0 },
76812 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
76813 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa1fc0000 }
76814 },
76815/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
76816 {
76817 { 0, 0, 0, 0 },
76818 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76819 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ca0000 }
76820 },
76821/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
76822 {
76823 { 0, 0, 0, 0 },
76824 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76825 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ea0000 }
76826 },
76827/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
76828 {
76829 { 0, 0, 0, 0 },
76830 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76831 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa1fa0000 }
76832 },
76833/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
76834 {
76835 { 0, 0, 0, 0 },
76836 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76837 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ce0000 }
76838 },
76839/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
76840 {
76841 { 0, 0, 0, 0 },
76842 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76843 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ee0000 }
76844 },
76845/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
76846 {
76847 { 0, 0, 0, 0 },
76848 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76849 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa1fe0000 }
76850 },
76851/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
76852 {
76853 { 0, 0, 0, 0 },
76854 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76855 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1cb0000 }
76856 },
76857/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
76858 {
76859 { 0, 0, 0, 0 },
76860 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76861 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1eb0000 }
76862 },
76863/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
76864 {
76865 { 0, 0, 0, 0 },
76866 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76867 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa1fb0000 }
76868 },
76869/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
76870 {
76871 { 0, 0, 0, 0 },
76872 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
76873 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa1cf0000 }
76874 },
76875/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
76876 {
76877 { 0, 0, 0, 0 },
76878 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
76879 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa1ef0000 }
76880 },
76881/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
76882 {
76883 { 0, 0, 0, 0 },
76884 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
76885 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa1ff0000 }
76886 },
76887/* add.w${G} $Src16RnHI,$Dst16RnHI */
76888 {
76889 { 0, 0, 0, 0 },
76890 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
76891 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa100 }
76892 },
76893/* add.w${G} $Src16AnHI,$Dst16RnHI */
76894 {
76895 { 0, 0, 0, 0 },
76896 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
76897 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa140 }
76898 },
76899/* add.w${G} [$Src16An],$Dst16RnHI */
76900 {
76901 { 0, 0, 0, 0 },
76902 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
76903 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa160 }
76904 },
76905/* add.w${G} $Src16RnHI,$Dst16AnHI */
76906 {
76907 { 0, 0, 0, 0 },
76908 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
76909 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa104 }
76910 },
76911/* add.w${G} $Src16AnHI,$Dst16AnHI */
76912 {
76913 { 0, 0, 0, 0 },
76914 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
76915 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa144 }
76916 },
76917/* add.w${G} [$Src16An],$Dst16AnHI */
76918 {
76919 { 0, 0, 0, 0 },
76920 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
76921 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa164 }
76922 },
76923/* add.w${G} $Src16RnHI,[$Dst16An] */
76924 {
76925 { 0, 0, 0, 0 },
76926 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
76927 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa106 }
76928 },
76929/* add.w${G} $Src16AnHI,[$Dst16An] */
76930 {
76931 { 0, 0, 0, 0 },
76932 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
76933 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa146 }
76934 },
76935/* add.w${G} [$Src16An],[$Dst16An] */
76936 {
76937 { 0, 0, 0, 0 },
76938 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
76939 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa166 }
76940 },
76941/* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
76942 {
76943 { 0, 0, 0, 0 },
76944 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
76945 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa10800 }
76946 },
76947/* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
76948 {
76949 { 0, 0, 0, 0 },
76950 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
76951 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa14800 }
76952 },
76953/* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
76954 {
76955 { 0, 0, 0, 0 },
76956 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
76957 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa16800 }
76958 },
76959/* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
76960 {
76961 { 0, 0, 0, 0 },
76962 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
76963 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa10c0000 }
76964 },
76965/* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
76966 {
76967 { 0, 0, 0, 0 },
76968 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
76969 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa14c0000 }
76970 },
76971/* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
76972 {
76973 { 0, 0, 0, 0 },
76974 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
76975 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa16c0000 }
76976 },
76977/* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
76978 {
76979 { 0, 0, 0, 0 },
76980 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76981 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa10a00 }
76982 },
76983/* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
76984 {
76985 { 0, 0, 0, 0 },
76986 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76987 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa14a00 }
76988 },
76989/* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
76990 {
76991 { 0, 0, 0, 0 },
76992 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76993 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa16a00 }
76994 },
76995/* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
76996 {
76997 { 0, 0, 0, 0 },
76998 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76999 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa10e0000 }
77000 },
77001/* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
77002 {
77003 { 0, 0, 0, 0 },
77004 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77005 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa14e0000 }
77006 },
77007/* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
77008 {
77009 { 0, 0, 0, 0 },
77010 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77011 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa16e0000 }
77012 },
77013/* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
77014 {
77015 { 0, 0, 0, 0 },
77016 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77017 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa10b00 }
77018 },
77019/* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
77020 {
77021 { 0, 0, 0, 0 },
77022 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77023 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa14b00 }
77024 },
77025/* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
77026 {
77027 { 0, 0, 0, 0 },
77028 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77029 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa16b00 }
77030 },
77031/* add.w${G} $Src16RnHI,${Dsp-16-u16} */
77032 {
77033 { 0, 0, 0, 0 },
77034 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
77035 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa10f0000 }
77036 },
77037/* add.w${G} $Src16AnHI,${Dsp-16-u16} */
77038 {
77039 { 0, 0, 0, 0 },
77040 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
77041 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa14f0000 }
77042 },
77043/* add.w${G} [$Src16An],${Dsp-16-u16} */
77044 {
77045 { 0, 0, 0, 0 },
77046 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
77047 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa16f0000 }
77048 },
77049/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
77050 {
77051 { 0, 0, 0, 0 },
77052 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77053 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa08000 }
77054 },
77055/* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
77056 {
77057 { 0, 0, 0, 0 },
77058 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
77059 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0a000 }
77060 },
77061/* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
77062 {
77063 { 0, 0, 0, 0 },
77064 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
77065 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa0b000 }
77066 },
77067/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
77068 {
77069 { 0, 0, 0, 0 },
77070 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77071 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa08400 }
77072 },
77073/* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
77074 {
77075 { 0, 0, 0, 0 },
77076 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
77077 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa0a400 }
77078 },
77079/* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
77080 {
77081 { 0, 0, 0, 0 },
77082 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
77083 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa0b400 }
77084 },
77085/* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
77086 {
77087 { 0, 0, 0, 0 },
77088 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77089 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa08600 }
77090 },
77091/* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
77092 {
77093 { 0, 0, 0, 0 },
77094 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77095 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa0a600 }
77096 },
77097/* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
77098 {
77099 { 0, 0, 0, 0 },
77100 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77101 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa0b600 }
77102 },
77103/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
77104 {
77105 { 0, 0, 0, 0 },
77106 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77107 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa0880000 }
77108 },
77109/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
77110 {
77111 { 0, 0, 0, 0 },
77112 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77113 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0a80000 }
77114 },
77115/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
77116 {
77117 { 0, 0, 0, 0 },
77118 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77119 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0b80000 }
77120 },
77121/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
77122 {
77123 { 0, 0, 0, 0 },
77124 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77125 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa08c0000 }
77126 },
77127/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
77128 {
77129 { 0, 0, 0, 0 },
77130 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77131 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0ac0000 }
77132 },
77133/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
77134 {
77135 { 0, 0, 0, 0 },
77136 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77137 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0bc0000 }
77138 },
77139/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
77140 {
77141 { 0, 0, 0, 0 },
77142 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77143 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa08a0000 }
77144 },
77145/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
77146 {
77147 { 0, 0, 0, 0 },
77148 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77149 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0aa0000 }
77150 },
77151/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
77152 {
77153 { 0, 0, 0, 0 },
77154 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77155 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0ba0000 }
77156 },
77157/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
77158 {
77159 { 0, 0, 0, 0 },
77160 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77161 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa08e0000 }
77162 },
77163/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
77164 {
77165 { 0, 0, 0, 0 },
77166 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77167 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0ae0000 }
77168 },
77169/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
77170 {
77171 { 0, 0, 0, 0 },
77172 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77173 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0be0000 }
77174 },
77175/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
77176 {
77177 { 0, 0, 0, 0 },
77178 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77179 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa08b0000 }
77180 },
77181/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
77182 {
77183 { 0, 0, 0, 0 },
77184 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77185 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0ab0000 }
77186 },
77187/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
77188 {
77189 { 0, 0, 0, 0 },
77190 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77191 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0bb0000 }
77192 },
77193/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
77194 {
77195 { 0, 0, 0, 0 },
77196 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
77197 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa08f0000 }
77198 },
77199/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
77200 {
77201 { 0, 0, 0, 0 },
77202 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77203 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa0af0000 }
77204 },
77205/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
77206 {
77207 { 0, 0, 0, 0 },
77208 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77209 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa0bf0000 }
77210 },
77211/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
77212 {
77213 { 0, 0, 0, 0 },
77214 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77215 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa0c00000 }
77216 },
77217/* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
77218 {
77219 { 0, 0, 0, 0 },
77220 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
77221 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0e00000 }
77222 },
77223/* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
77224 {
77225 { 0, 0, 0, 0 },
77226 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
77227 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa0f00000 }
77228 },
77229/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
77230 {
77231 { 0, 0, 0, 0 },
77232 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77233 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa0c40000 }
77234 },
77235/* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
77236 {
77237 { 0, 0, 0, 0 },
77238 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
77239 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa0e40000 }
77240 },
77241/* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
77242 {
77243 { 0, 0, 0, 0 },
77244 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
77245 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa0f40000 }
77246 },
77247/* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
77248 {
77249 { 0, 0, 0, 0 },
77250 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77251 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa0c60000 }
77252 },
77253/* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
77254 {
77255 { 0, 0, 0, 0 },
77256 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77257 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa0e60000 }
77258 },
77259/* add.b${G} ${Dsp-16-u16},[$Dst16An] */
77260 {
77261 { 0, 0, 0, 0 },
77262 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
77263 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa0f60000 }
77264 },
77265/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
77266 {
77267 { 0, 0, 0, 0 },
77268 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77269 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa0c80000 }
77270 },
77271/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
77272 {
77273 { 0, 0, 0, 0 },
77274 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77275 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa0e80000 }
77276 },
77277/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
77278 {
77279 { 0, 0, 0, 0 },
77280 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77281 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa0f80000 }
77282 },
77283/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
77284 {
77285 { 0, 0, 0, 0 },
77286 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77287 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa0cc0000 }
77288 },
77289/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
77290 {
77291 { 0, 0, 0, 0 },
77292 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77293 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa0ec0000 }
77294 },
77295/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
77296 {
77297 { 0, 0, 0, 0 },
77298 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77299 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa0fc0000 }
77300 },
77301/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
77302 {
77303 { 0, 0, 0, 0 },
77304 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77305 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ca0000 }
77306 },
77307/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
77308 {
77309 { 0, 0, 0, 0 },
77310 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77311 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ea0000 }
77312 },
77313/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
77314 {
77315 { 0, 0, 0, 0 },
77316 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77317 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa0fa0000 }
77318 },
77319/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
77320 {
77321 { 0, 0, 0, 0 },
77322 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77323 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ce0000 }
77324 },
77325/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
77326 {
77327 { 0, 0, 0, 0 },
77328 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77329 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ee0000 }
77330 },
77331/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
77332 {
77333 { 0, 0, 0, 0 },
77334 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77335 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa0fe0000 }
77336 },
77337/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
77338 {
77339 { 0, 0, 0, 0 },
77340 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77341 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0cb0000 }
77342 },
77343/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
77344 {
77345 { 0, 0, 0, 0 },
77346 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77347 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0eb0000 }
77348 },
77349/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
77350 {
77351 { 0, 0, 0, 0 },
77352 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77353 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa0fb0000 }
77354 },
77355/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
77356 {
77357 { 0, 0, 0, 0 },
77358 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
77359 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa0cf0000 }
77360 },
77361/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
77362 {
77363 { 0, 0, 0, 0 },
77364 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
77365 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa0ef0000 }
77366 },
77367/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
77368 {
77369 { 0, 0, 0, 0 },
77370 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
77371 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa0ff0000 }
77372 },
77373/* add.b${G} $Src16RnQI,$Dst16RnQI */
77374 {
77375 { 0, 0, 0, 0 },
77376 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
77377 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa000 }
77378 },
77379/* add.b${G} $Src16AnQI,$Dst16RnQI */
77380 {
77381 { 0, 0, 0, 0 },
77382 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
77383 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa040 }
77384 },
77385/* add.b${G} [$Src16An],$Dst16RnQI */
77386 {
77387 { 0, 0, 0, 0 },
77388 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77389 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa060 }
77390 },
77391/* add.b${G} $Src16RnQI,$Dst16AnQI */
77392 {
77393 { 0, 0, 0, 0 },
77394 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
77395 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa004 }
77396 },
77397/* add.b${G} $Src16AnQI,$Dst16AnQI */
77398 {
77399 { 0, 0, 0, 0 },
77400 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
77401 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa044 }
77402 },
77403/* add.b${G} [$Src16An],$Dst16AnQI */
77404 {
77405 { 0, 0, 0, 0 },
77406 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77407 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa064 }
77408 },
77409/* add.b${G} $Src16RnQI,[$Dst16An] */
77410 {
77411 { 0, 0, 0, 0 },
77412 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
77413 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa006 }
77414 },
77415/* add.b${G} $Src16AnQI,[$Dst16An] */
77416 {
77417 { 0, 0, 0, 0 },
77418 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
77419 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa046 }
77420 },
77421/* add.b${G} [$Src16An],[$Dst16An] */
77422 {
77423 { 0, 0, 0, 0 },
77424 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77425 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa066 }
77426 },
77427/* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
77428 {
77429 { 0, 0, 0, 0 },
77430 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77431 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa00800 }
77432 },
77433/* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
77434 {
77435 { 0, 0, 0, 0 },
77436 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77437 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa04800 }
77438 },
77439/* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
77440 {
77441 { 0, 0, 0, 0 },
77442 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77443 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa06800 }
77444 },
77445/* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
77446 {
77447 { 0, 0, 0, 0 },
77448 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77449 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa00c0000 }
77450 },
77451/* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
77452 {
77453 { 0, 0, 0, 0 },
77454 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77455 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa04c0000 }
77456 },
77457/* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
77458 {
77459 { 0, 0, 0, 0 },
77460 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77461 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa06c0000 }
77462 },
77463/* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
77464 {
77465 { 0, 0, 0, 0 },
77466 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77467 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa00a00 }
77468 },
77469/* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
77470 {
77471 { 0, 0, 0, 0 },
77472 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77473 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa04a00 }
77474 },
77475/* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
77476 {
77477 { 0, 0, 0, 0 },
77478 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77479 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa06a00 }
77480 },
77481/* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
77482 {
77483 { 0, 0, 0, 0 },
77484 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77485 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa00e0000 }
77486 },
77487/* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
77488 {
77489 { 0, 0, 0, 0 },
77490 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77491 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa04e0000 }
77492 },
77493/* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
77494 {
77495 { 0, 0, 0, 0 },
77496 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77497 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa06e0000 }
77498 },
77499/* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
77500 {
77501 { 0, 0, 0, 0 },
77502 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77503 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa00b00 }
77504 },
77505/* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
77506 {
77507 { 0, 0, 0, 0 },
77508 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77509 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa04b00 }
77510 },
77511/* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
77512 {
77513 { 0, 0, 0, 0 },
77514 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77515 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa06b00 }
77516 },
77517/* add.b${G} $Src16RnQI,${Dsp-16-u16} */
77518 {
77519 { 0, 0, 0, 0 },
77520 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
77521 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa00f0000 }
77522 },
77523/* add.b${G} $Src16AnQI,${Dsp-16-u16} */
77524 {
77525 { 0, 0, 0, 0 },
77526 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
77527 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa04f0000 }
77528 },
77529/* add.b${G} [$Src16An],${Dsp-16-u16} */
77530 {
77531 { 0, 0, 0, 0 },
77532 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
77533 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa06f0000 }
77534 },
77535/* add.b${S} #${Imm-8-QI},r0l */
77536 {
77537 { 0, 0, 0, 0 },
77538 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
77539 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8400 }
77540 },
77541/* add.b${S} #${Imm-8-QI},r0h */
77542 {
77543 { 0, 0, 0, 0 },
77544 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
77545 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8300 }
77546 },
77547/* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
77548 {
77549 { 0, 0, 0, 0 },
77550 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77551 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x850000 }
77552 },
77553/* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
77554 {
77555 { 0, 0, 0, 0 },
77556 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77557 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x860000 }
77558 },
77559/* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
77560 {
77561 { 0, 0, 0, 0 },
77562 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
77563 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x87000000 }
77564 },
77565/* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
77566 {
77567 { 0, 0, 0, 0 },
77568 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
77569 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xf830 }
77570 },
77571/* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
77572 {
77573 { 0, 0, 0, 0 },
77574 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
77575 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xf0b0 }
77576 },
77577/* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
77578 {
77579 { 0, 0, 0, 0 },
77580 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77581 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xf030 }
77582 },
77583/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
77584 {
77585 { 0, 0, 0, 0 },
77586 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77587 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xf23000 }
77588 },
77589/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
77590 {
77591 { 0, 0, 0, 0 },
77592 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77593 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xf4300000 }
77594 },
77595/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
77596 {
77597 { 0, 0, 0, 0 },
77598 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77599 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xf6300000 }
77600 },
77601/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
77602 {
77603 { 0, 0, 0, 0 },
77604 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77605 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xf2b000 }
77606 },
77607/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
77608 {
77609 { 0, 0, 0, 0 },
77610 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77611 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xf4b00000 }
77612 },
77613/* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
77614 {
77615 { 0, 0, 0, 0 },
77616 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77617 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xf2f000 }
77618 },
77619/* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
77620 {
77621 { 0, 0, 0, 0 },
77622 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
77623 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xf4f00000 }
77624 },
77625/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
77626 {
77627 { 0, 0, 0, 0 },
77628 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
77629 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xf6f00000 }
77630 },
77631/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
77632 {
77633 { 0, 0, 0, 0 },
77634 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
77635 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xf6b00000 }
77636 },
77637/* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
77638 {
77639 { 0, 0, 0, 0 },
77640 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
77641 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe930 }
77642 },
77643/* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
77644 {
77645 { 0, 0, 0, 0 },
77646 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
77647 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1b0 }
77648 },
77649/* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
77650 {
77651 { 0, 0, 0, 0 },
77652 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77653 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe130 }
77654 },
77655/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
77656 {
77657 { 0, 0, 0, 0 },
77658 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77659 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe33000 }
77660 },
77661/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
77662 {
77663 { 0, 0, 0, 0 },
77664 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77665 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5300000 }
77666 },
77667/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
77668 {
77669 { 0, 0, 0, 0 },
77670 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77671 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7300000 }
77672 },
77673/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
77674 {
77675 { 0, 0, 0, 0 },
77676 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77677 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3b000 }
77678 },
77679/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
77680 {
77681 { 0, 0, 0, 0 },
77682 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77683 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5b00000 }
77684 },
77685/* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
77686 {
77687 { 0, 0, 0, 0 },
77688 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77689 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3f000 }
77690 },
77691/* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
77692 {
77693 { 0, 0, 0, 0 },
77694 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
77695 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5f00000 }
77696 },
77697/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
77698 {
77699 { 0, 0, 0, 0 },
77700 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
77701 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7f00000 }
77702 },
77703/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
77704 {
77705 { 0, 0, 0, 0 },
77706 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
77707 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7b00000 }
77708 },
77709/* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
77710 {
77711 { 0, 0, 0, 0 },
77712 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
77713 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe830 }
77714 },
77715/* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
77716 {
77717 { 0, 0, 0, 0 },
77718 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
77719 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0b0 }
77720 },
77721/* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
77722 {
77723 { 0, 0, 0, 0 },
77724 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77725 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe030 }
77726 },
77727/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
77728 {
77729 { 0, 0, 0, 0 },
77730 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77731 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe23000 }
77732 },
77733/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
77734 {
77735 { 0, 0, 0, 0 },
77736 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77737 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4300000 }
77738 },
77739/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
77740 {
77741 { 0, 0, 0, 0 },
77742 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77743 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6300000 }
77744 },
77745/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
77746 {
77747 { 0, 0, 0, 0 },
77748 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77749 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2b000 }
77750 },
77751/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
77752 {
77753 { 0, 0, 0, 0 },
77754 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77755 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4b00000 }
77756 },
77757/* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
77758 {
77759 { 0, 0, 0, 0 },
77760 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77761 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2f000 }
77762 },
77763/* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
77764 {
77765 { 0, 0, 0, 0 },
77766 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
77767 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4f00000 }
77768 },
77769/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
77770 {
77771 { 0, 0, 0, 0 },
77772 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
77773 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6f00000 }
77774 },
77775/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
77776 {
77777 { 0, 0, 0, 0 },
77778 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
77779 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6b00000 }
77780 },
77781/* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
77782 {
77783 { 0, 0, 0, 0 },
77784 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
77785 & ifmt_cmp16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xc900 }
77786 },
77787/* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
77788 {
77789 { 0, 0, 0, 0 },
77790 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
77791 & ifmt_cmp16_w_imm4_Q_16_dst16_An_direct_HI, { 0xc904 }
77792 },
77793/* add.w${Q} #${Imm-8-s4},[$Dst16An] */
77794 {
77795 { 0, 0, 0, 0 },
77796 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
77797 & ifmt_cmp16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xc906 }
77798 },
77799/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
77800 {
77801 { 0, 0, 0, 0 },
77802 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77803 & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xc90800 }
77804 },
77805/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
77806 {
77807 { 0, 0, 0, 0 },
77808 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77809 & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xc90c0000 }
77810 },
77811/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
77812 {
77813 { 0, 0, 0, 0 },
77814 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77815 & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xc90a00 }
77816 },
77817/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
77818 {
77819 { 0, 0, 0, 0 },
77820 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77821 & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xc90e0000 }
77822 },
77823/* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
77824 {
77825 { 0, 0, 0, 0 },
77826 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77827 & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xc90b00 }
77828 },
77829/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
77830 {
77831 { 0, 0, 0, 0 },
77832 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
77833 & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xc90f0000 }
77834 },
77835/* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
77836 {
77837 { 0, 0, 0, 0 },
77838 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
77839 & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xc800 }
77840 },
77841/* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
77842 {
77843 { 0, 0, 0, 0 },
77844 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
77845 & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xc804 }
77846 },
77847/* add.b${Q} #${Imm-8-s4},[$Dst16An] */
77848 {
77849 { 0, 0, 0, 0 },
77850 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
77851 & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xc806 }
77852 },
77853/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
77854 {
77855 { 0, 0, 0, 0 },
77856 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77857 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xc80800 }
77858 },
77859/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
77860 {
77861 { 0, 0, 0, 0 },
77862 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77863 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xc80c0000 }
77864 },
77865/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
77866 {
77867 { 0, 0, 0, 0 },
77868 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77869 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xc80a00 }
77870 },
77871/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
77872 {
77873 { 0, 0, 0, 0 },
77874 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77875 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xc80e0000 }
77876 },
77877/* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
77878 {
77879 { 0, 0, 0, 0 },
77880 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77881 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xc80b00 }
77882 },
77883/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
77884 {
77885 { 0, 0, 0, 0 },
77886 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
77887 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xc80f0000 }
77888 },
77889/* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
77890 {
77891 { 0, 0, 0, 0 },
77892 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
77893 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892e0000 }
77894 },
77895/* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
77896 {
77897 { 0, 0, 0, 0 },
77898 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
77899 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81ae0000 }
77900 },
77901/* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
77902 {
77903 { 0, 0, 0, 0 },
77904 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77905 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812e0000 }
77906 },
77907/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
77908 {
77909 { 0, 0, 0, 0 },
77910 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77911 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832e0000 }
77912 },
77913/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
77914 {
77915 { 0, 0, 0, 0 },
77916 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77917 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ae0000 }
77918 },
77919/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
77920 {
77921 { 0, 0, 0, 0 },
77922 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77923 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ee0000 }
77924 },
77925/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
77926 {
77927 { 0, 0, 0, 0 },
77928 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77929 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852e0000 }
77930 },
77931/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
77932 {
77933 { 0, 0, 0, 0 },
77934 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77935 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ae0000 }
77936 },
77937/* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
77938 {
77939 { 0, 0, 0, 0 },
77940 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
77941 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ee0000 }
77942 },
77943/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
77944 {
77945 { 0, 0, 0, 0 },
77946 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
77947 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ee0000 }
77948 },
77949/* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
77950 {
77951 { 0, 0, 0, 0 },
77952 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77953 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872e0000 }
77954 },
77955/* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
77956 {
77957 { 0, 0, 0, 0 },
77958 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
77959 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87ae0000 }
77960 },
77961/* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
77962 {
77963 { 0, 0, 0, 0 },
77964 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
77965 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882e00 }
77966 },
77967/* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
77968 {
77969 { 0, 0, 0, 0 },
77970 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
77971 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80ae00 }
77972 },
77973/* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
77974 {
77975 { 0, 0, 0, 0 },
77976 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77977 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802e00 }
77978 },
77979/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
77980 {
77981 { 0, 0, 0, 0 },
77982 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77983 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822e0000 }
77984 },
77985/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
77986 {
77987 { 0, 0, 0, 0 },
77988 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77989 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ae0000 }
77990 },
77991/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
77992 {
77993 { 0, 0, 0, 0 },
77994 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77995 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ee0000 }
77996 },
77997/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
77998 {
77999 { 0, 0, 0, 0 },
78000 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78001 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842e0000 }
78002 },
78003/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
78004 {
78005 { 0, 0, 0, 0 },
78006 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78007 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ae0000 }
78008 },
78009/* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
78010 {
78011 { 0, 0, 0, 0 },
78012 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78013 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ee0000 }
78014 },
78015/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
78016 {
78017 { 0, 0, 0, 0 },
78018 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
78019 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ee0000 }
78020 },
78021/* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78022 {
78023 { 0, 0, 0, 0 },
78024 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78025 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862e0000 }
78026 },
78027/* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
78028 {
78029 { 0, 0, 0, 0 },
78030 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
78031 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86ae0000 }
78032 },
78033/* add.w${G} #${Imm-16-HI},$Dst16RnHI */
78034 {
78035 { 0, 0, 0, 0 },
78036 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
78037 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77400000 }
78038 },
78039/* add.w${G} #${Imm-16-HI},$Dst16AnHI */
78040 {
78041 { 0, 0, 0, 0 },
78042 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
78043 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77440000 }
78044 },
78045/* add.w${G} #${Imm-16-HI},[$Dst16An] */
78046 {
78047 { 0, 0, 0, 0 },
78048 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
78049 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77460000 }
78050 },
78051/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
78052 {
78053 { 0, 0, 0, 0 },
78054 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78055 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77480000 }
78056 },
78057/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
78058 {
78059 { 0, 0, 0, 0 },
78060 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78061 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x774a0000 }
78062 },
78063/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
78064 {
78065 { 0, 0, 0, 0 },
78066 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78067 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x774b0000 }
78068 },
78069/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
78070 {
78071 { 0, 0, 0, 0 },
78072 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78073 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x774c0000 }
78074 },
78075/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
78076 {
78077 { 0, 0, 0, 0 },
78078 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78079 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x774e0000 }
78080 },
78081/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
78082 {
78083 { 0, 0, 0, 0 },
78084 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
78085 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x774f0000 }
78086 },
78087/* add.b${G} #${Imm-16-QI},$Dst16RnQI */
78088 {
78089 { 0, 0, 0, 0 },
78090 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
78091 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x764000 }
78092 },
78093/* add.b${G} #${Imm-16-QI},$Dst16AnQI */
78094 {
78095 { 0, 0, 0, 0 },
78096 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
78097 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x764400 }
78098 },
78099/* add.b${G} #${Imm-16-QI},[$Dst16An] */
78100 {
78101 { 0, 0, 0, 0 },
78102 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
78103 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x764600 }
78104 },
78105/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
78106 {
78107 { 0, 0, 0, 0 },
78108 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78109 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76480000 }
78110 },
78111/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
78112 {
78113 { 0, 0, 0, 0 },
78114 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78115 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x764a0000 }
78116 },
78117/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
78118 {
78119 { 0, 0, 0, 0 },
78120 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78121 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x764b0000 }
78122 },
78123/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
78124 {
78125 { 0, 0, 0, 0 },
78126 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78127 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x764c0000 }
78128 },
78129/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
78130 {
78131 { 0, 0, 0, 0 },
78132 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78133 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x764e0000 }
78134 },
78135/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
78136 {
78137 { 0, 0, 0, 0 },
78138 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
78139 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x764f0000 }
78140 },
78141/* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
78142 {
78143 { 0, 0, 0, 0 },
78144 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
78145 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x88310000 }
78146 },
78147/* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
78148 {
78149 { 0, 0, 0, 0 },
78150 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
78151 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80b10000 }
78152 },
78153/* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
78154 {
78155 { 0, 0, 0, 0 },
78156 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78157 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x80310000 }
78158 },
78159/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78160 {
78161 { 0, 0, 0, 0 },
78162 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78163 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82310000 }
78164 },
78165/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
78166 {
78167 { 0, 0, 0, 0 },
78168 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78169 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82b10000 }
78170 },
78171/* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
78172 {
78173 { 0, 0, 0, 0 },
78174 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78175 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82f10000 }
78176 },
78177/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78178 {
78179 { 0, 0, 0, 0 },
78180 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78181 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84310000 }
78182 },
78183/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
78184 {
78185 { 0, 0, 0, 0 },
78186 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78187 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84b10000 }
78188 },
78189/* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
78190 {
78191 { 0, 0, 0, 0 },
78192 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78193 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84f10000 }
78194 },
78195/* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
78196 {
78197 { 0, 0, 0, 0 },
78198 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
78199 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86f10000 }
78200 },
78201/* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78202 {
78203 { 0, 0, 0, 0 },
78204 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78205 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86310000 }
78206 },
78207/* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
78208 {
78209 { 0, 0, 0, 0 },
78210 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
78211 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86b10000 }
78212 },
78213/* adcf.w $Dst32RnUnprefixedHI */
78214 {
78215 { 0, 0, 0, 0 },
78216 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
78217 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb91e }
78218 },
78219/* adcf.w $Dst32AnUnprefixedHI */
78220 {
78221 { 0, 0, 0, 0 },
78222 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
78223 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb19e }
78224 },
78225/* adcf.w [$Dst32AnUnprefixed] */
78226 {
78227 { 0, 0, 0, 0 },
78228 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78229 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb11e }
78230 },
78231/* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78232 {
78233 { 0, 0, 0, 0 },
78234 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78235 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb31e00 }
78236 },
78237/* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78238 {
78239 { 0, 0, 0, 0 },
78240 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78241 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb51e0000 }
78242 },
78243/* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78244 {
78245 { 0, 0, 0, 0 },
78246 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78247 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb71e0000 }
78248 },
78249/* adcf.w ${Dsp-16-u8}[sb] */
78250 {
78251 { 0, 0, 0, 0 },
78252 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78253 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb39e00 }
78254 },
78255/* adcf.w ${Dsp-16-u16}[sb] */
78256 {
78257 { 0, 0, 0, 0 },
78258 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78259 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb59e0000 }
78260 },
78261/* adcf.w ${Dsp-16-s8}[fb] */
78262 {
78263 { 0, 0, 0, 0 },
78264 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78265 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3de00 }
78266 },
78267/* adcf.w ${Dsp-16-s16}[fb] */
78268 {
78269 { 0, 0, 0, 0 },
78270 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78271 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5de0000 }
78272 },
78273/* adcf.w ${Dsp-16-u16} */
78274 {
78275 { 0, 0, 0, 0 },
78276 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78277 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7de0000 }
78278 },
78279/* adcf.w ${Dsp-16-u24} */
78280 {
78281 { 0, 0, 0, 0 },
78282 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78283 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb79e0000 }
78284 },
78285/* adcf.b $Dst32RnUnprefixedQI */
78286 {
78287 { 0, 0, 0, 0 },
78288 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
78289 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb81e }
78290 },
78291/* adcf.b $Dst32AnUnprefixedQI */
78292 {
78293 { 0, 0, 0, 0 },
78294 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
78295 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb09e }
78296 },
78297/* adcf.b [$Dst32AnUnprefixed] */
78298 {
78299 { 0, 0, 0, 0 },
78300 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78301 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb01e }
78302 },
78303/* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78304 {
78305 { 0, 0, 0, 0 },
78306 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78307 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb21e00 }
78308 },
78309/* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78310 {
78311 { 0, 0, 0, 0 },
78312 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78313 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb41e0000 }
78314 },
78315/* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78316 {
78317 { 0, 0, 0, 0 },
78318 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78319 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb61e0000 }
78320 },
78321/* adcf.b ${Dsp-16-u8}[sb] */
78322 {
78323 { 0, 0, 0, 0 },
78324 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78325 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb29e00 }
78326 },
78327/* adcf.b ${Dsp-16-u16}[sb] */
78328 {
78329 { 0, 0, 0, 0 },
78330 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78331 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb49e0000 }
78332 },
78333/* adcf.b ${Dsp-16-s8}[fb] */
78334 {
78335 { 0, 0, 0, 0 },
78336 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78337 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2de00 }
78338 },
78339/* adcf.b ${Dsp-16-s16}[fb] */
78340 {
78341 { 0, 0, 0, 0 },
78342 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78343 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4de0000 }
78344 },
78345/* adcf.b ${Dsp-16-u16} */
78346 {
78347 { 0, 0, 0, 0 },
78348 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78349 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6de0000 }
78350 },
78351/* adcf.b ${Dsp-16-u24} */
78352 {
78353 { 0, 0, 0, 0 },
78354 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78355 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb69e0000 }
78356 },
78357/* adcf.w $Dst16RnHI */
78358 {
78359 { 0, 0, 0, 0 },
78360 { { MNEM, ' ', OP (DST16RNHI), 0 } },
78361 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77e0 }
78362 },
78363/* adcf.w $Dst16AnHI */
78364 {
78365 { 0, 0, 0, 0 },
78366 { { MNEM, ' ', OP (DST16ANHI), 0 } },
78367 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77e4 }
78368 },
78369/* adcf.w [$Dst16An] */
78370 {
78371 { 0, 0, 0, 0 },
78372 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78373 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77e6 }
78374 },
78375/* adcf.w ${Dsp-16-u8}[$Dst16An] */
78376 {
78377 { 0, 0, 0, 0 },
78378 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78379 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77e800 }
78380 },
78381/* adcf.w ${Dsp-16-u16}[$Dst16An] */
78382 {
78383 { 0, 0, 0, 0 },
78384 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78385 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ec0000 }
78386 },
78387/* adcf.w ${Dsp-16-u8}[sb] */
78388 {
78389 { 0, 0, 0, 0 },
78390 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78391 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ea00 }
78392 },
78393/* adcf.w ${Dsp-16-u16}[sb] */
78394 {
78395 { 0, 0, 0, 0 },
78396 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78397 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ee0000 }
78398 },
78399/* adcf.w ${Dsp-16-s8}[fb] */
78400 {
78401 { 0, 0, 0, 0 },
78402 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78403 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77eb00 }
78404 },
78405/* adcf.w ${Dsp-16-u16} */
78406 {
78407 { 0, 0, 0, 0 },
78408 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78409 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ef0000 }
78410 },
78411/* adcf.b $Dst16RnQI */
78412 {
78413 { 0, 0, 0, 0 },
78414 { { MNEM, ' ', OP (DST16RNQI), 0 } },
78415 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76e0 }
78416 },
78417/* adcf.b $Dst16AnQI */
78418 {
78419 { 0, 0, 0, 0 },
78420 { { MNEM, ' ', OP (DST16ANQI), 0 } },
78421 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76e4 }
78422 },
78423/* adcf.b [$Dst16An] */
78424 {
78425 { 0, 0, 0, 0 },
78426 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78427 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76e6 }
78428 },
78429/* adcf.b ${Dsp-16-u8}[$Dst16An] */
78430 {
78431 { 0, 0, 0, 0 },
78432 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78433 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76e800 }
78434 },
78435/* adcf.b ${Dsp-16-u16}[$Dst16An] */
78436 {
78437 { 0, 0, 0, 0 },
78438 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78439 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ec0000 }
78440 },
78441/* adcf.b ${Dsp-16-u8}[sb] */
78442 {
78443 { 0, 0, 0, 0 },
78444 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78445 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ea00 }
78446 },
78447/* adcf.b ${Dsp-16-u16}[sb] */
78448 {
78449 { 0, 0, 0, 0 },
78450 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78451 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ee0000 }
78452 },
78453/* adcf.b ${Dsp-16-s8}[fb] */
78454 {
78455 { 0, 0, 0, 0 },
78456 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78457 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76eb00 }
78458 },
78459/* adcf.b ${Dsp-16-u16} */
78460 {
78461 { 0, 0, 0, 0 },
78462 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78463 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ef0000 }
78464 },
78465/* abs.w $Dst32RnUnprefixedHI */
78466 {
78467 { 0, 0, 0, 0 },
78468 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
78469 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91f }
78470 },
78471/* abs.w $Dst32AnUnprefixedHI */
78472 {
78473 { 0, 0, 0, 0 },
78474 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
78475 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19f }
78476 },
78477/* abs.w [$Dst32AnUnprefixed] */
78478 {
78479 { 0, 0, 0, 0 },
78480 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78481 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11f }
78482 },
78483/* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78484 {
78485 { 0, 0, 0, 0 },
78486 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78487 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31f00 }
78488 },
78489/* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78490 {
78491 { 0, 0, 0, 0 },
78492 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78493 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51f0000 }
78494 },
78495/* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78496 {
78497 { 0, 0, 0, 0 },
78498 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78499 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71f0000 }
78500 },
78501/* abs.w ${Dsp-16-u8}[sb] */
78502 {
78503 { 0, 0, 0, 0 },
78504 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78505 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39f00 }
78506 },
78507/* abs.w ${Dsp-16-u16}[sb] */
78508 {
78509 { 0, 0, 0, 0 },
78510 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78511 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59f0000 }
78512 },
78513/* abs.w ${Dsp-16-s8}[fb] */
78514 {
78515 { 0, 0, 0, 0 },
78516 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78517 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3df00 }
78518 },
78519/* abs.w ${Dsp-16-s16}[fb] */
78520 {
78521 { 0, 0, 0, 0 },
78522 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78523 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5df0000 }
78524 },
78525/* abs.w ${Dsp-16-u16} */
78526 {
78527 { 0, 0, 0, 0 },
78528 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78529 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7df0000 }
78530 },
78531/* abs.w ${Dsp-16-u24} */
78532 {
78533 { 0, 0, 0, 0 },
78534 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78535 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79f0000 }
78536 },
78537/* abs.b $Dst32RnUnprefixedQI */
78538 {
78539 { 0, 0, 0, 0 },
78540 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
78541 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81f }
78542 },
78543/* abs.b $Dst32AnUnprefixedQI */
78544 {
78545 { 0, 0, 0, 0 },
78546 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
78547 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09f }
78548 },
78549/* abs.b [$Dst32AnUnprefixed] */
78550 {
78551 { 0, 0, 0, 0 },
78552 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78553 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01f }
78554 },
78555/* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78556 {
78557 { 0, 0, 0, 0 },
78558 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78559 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21f00 }
78560 },
78561/* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78562 {
78563 { 0, 0, 0, 0 },
78564 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78565 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41f0000 }
78566 },
78567/* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78568 {
78569 { 0, 0, 0, 0 },
78570 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78571 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61f0000 }
78572 },
78573/* abs.b ${Dsp-16-u8}[sb] */
78574 {
78575 { 0, 0, 0, 0 },
78576 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78577 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29f00 }
78578 },
78579/* abs.b ${Dsp-16-u16}[sb] */
78580 {
78581 { 0, 0, 0, 0 },
78582 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78583 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49f0000 }
78584 },
78585/* abs.b ${Dsp-16-s8}[fb] */
78586 {
78587 { 0, 0, 0, 0 },
78588 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78589 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2df00 }
78590 },
78591/* abs.b ${Dsp-16-s16}[fb] */
78592 {
78593 { 0, 0, 0, 0 },
78594 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78595 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4df0000 }
78596 },
78597/* abs.b ${Dsp-16-u16} */
78598 {
78599 { 0, 0, 0, 0 },
78600 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78601 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6df0000 }
78602 },
78603/* abs.b ${Dsp-16-u24} */
78604 {
78605 { 0, 0, 0, 0 },
78606 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78607 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69f0000 }
78608 },
78609/* abs.w $Dst16RnHI */
78610 {
78611 { 0, 0, 0, 0 },
78612 { { MNEM, ' ', OP (DST16RNHI), 0 } },
78613 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77f0 }
78614 },
78615/* abs.w $Dst16AnHI */
78616 {
78617 { 0, 0, 0, 0 },
78618 { { MNEM, ' ', OP (DST16ANHI), 0 } },
78619 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77f4 }
78620 },
78621/* abs.w [$Dst16An] */
78622 {
78623 { 0, 0, 0, 0 },
78624 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78625 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77f6 }
78626 },
78627/* abs.w ${Dsp-16-u8}[$Dst16An] */
78628 {
78629 { 0, 0, 0, 0 },
78630 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78631 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77f800 }
78632 },
78633/* abs.w ${Dsp-16-u16}[$Dst16An] */
78634 {
78635 { 0, 0, 0, 0 },
78636 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78637 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77fc0000 }
78638 },
78639/* abs.w ${Dsp-16-u8}[sb] */
78640 {
78641 { 0, 0, 0, 0 },
78642 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78643 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77fa00 }
78644 },
78645/* abs.w ${Dsp-16-u16}[sb] */
78646 {
78647 { 0, 0, 0, 0 },
78648 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78649 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77fe0000 }
78650 },
78651/* abs.w ${Dsp-16-s8}[fb] */
78652 {
78653 { 0, 0, 0, 0 },
78654 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78655 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77fb00 }
78656 },
78657/* abs.w ${Dsp-16-u16} */
78658 {
78659 { 0, 0, 0, 0 },
78660 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78661 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ff0000 }
78662 },
78663/* abs.b $Dst16RnQI */
78664 {
78665 { 0, 0, 0, 0 },
78666 { { MNEM, ' ', OP (DST16RNQI), 0 } },
78667 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76f0 }
78668 },
78669/* abs.b $Dst16AnQI */
78670 {
78671 { 0, 0, 0, 0 },
78672 { { MNEM, ' ', OP (DST16ANQI), 0 } },
78673 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76f4 }
78674 },
78675/* abs.b [$Dst16An] */
78676 {
78677 { 0, 0, 0, 0 },
78678 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78679 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76f6 }
78680 },
78681/* abs.b ${Dsp-16-u8}[$Dst16An] */
78682 {
78683 { 0, 0, 0, 0 },
78684 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78685 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76f800 }
78686 },
78687/* abs.b ${Dsp-16-u16}[$Dst16An] */
78688 {
78689 { 0, 0, 0, 0 },
78690 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78691 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76fc0000 }
78692 },
78693/* abs.b ${Dsp-16-u8}[sb] */
78694 {
78695 { 0, 0, 0, 0 },
78696 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78697 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76fa00 }
78698 },
78699/* abs.b ${Dsp-16-u16}[sb] */
78700 {
78701 { 0, 0, 0, 0 },
78702 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78703 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76fe0000 }
78704 },
78705/* abs.b ${Dsp-16-s8}[fb] */
78706 {
78707 { 0, 0, 0, 0 },
78708 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78709 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76fb00 }
78710 },
78711/* abs.b ${Dsp-16-u16} */
78712 {
78713 { 0, 0, 0, 0 },
78714 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78715 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 }
78716 },
92e0a941 78717/* add.w$Q #${Imm-12-s4},sp */
49f58d10
JB		 78718 {
78719 { 0, 0, 0, 0 },
92e0a941
DD		 78720 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
78721 & ifmt_add16_wQ_sp, { 0x7db0 }
49f58d10
JB		 78722 },
78723/* add.b$G #${Imm-16-QI},sp */
78724 {
78725 { 0, 0, 0, 0 },
78726 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } },
78727 & ifmt_add16_b_G_sp, { 0x7ceb00 }
78728 },
78729/* add.w$G #${Imm-16-HI},sp */
78730 {
78731 { 0, 0, 0, 0 },
78732 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } },
78733 & ifmt_add16_w_G_sp, { 0x7deb0000 }
78734 },
78735/* add.l$Q #${Imm3-S},sp */
78736 {
78737 { 0, 0, 0, 0 },
78738 { { MNEM, OP (Q), ' ', '#', OP (IMM3_S), ',', 's', 'p', 0 } },
78739 & ifmt_add32_l_imm3_Q, { 0x42 }
78740 },
78741/* add.l$S #${Imm-16-QI},sp */
78742 {
78743 { 0, 0, 0, 0 },
78744 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } },
78745 & ifmt_add32_l_imm8_S, { 0xb60300 }
78746 },
78747/* add.l$G #${Imm-16-HI},sp */
78748 {
78749 { 0, 0, 0, 0 },
78750 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } },
78751 & ifmt_add32_l_imm16_G, { 0xb6130000 }
78752 },
78753/* dadc.b #${Imm-16-QI} */
78754 {
78755 { 0, 0, 0, 0 },
78756 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78757 & ifmt_add32_l_imm8_S, { 0x7cee00 }
78758 },
78759/* dadc.w #${Imm-16-HI} */
78760 {
78761 { 0, 0, 0, 0 },
78762 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78763 & ifmt_add32_l_imm16_G, { 0x7dee0000 }
78764 },
78765/* dadc.b r0h,r0l */
78766 {
78767 { 0, 0, 0, 0 },
78768 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
78769 & ifmt_dadc16_b_r0h_r0l, { 0x7ce6 }
78770 },
78771/* dadc.w r1,r0 */
78772 {
78773 { 0, 0, 0, 0 },
78774 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
78775 & ifmt_dadc16_b_r0h_r0l, { 0x7de6 }
78776 },
78777/* dadd.b #${Imm-16-QI} */
78778 {
78779 { 0, 0, 0, 0 },
78780 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78781 & ifmt_add32_l_imm8_S, { 0x7cec00 }
78782 },
78783/* dadd.w #${Imm-16-HI} */
78784 {
78785 { 0, 0, 0, 0 },
78786 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78787 & ifmt_add32_l_imm16_G, { 0x7dec0000 }
78788 },
78789/* dadd.b r0h,r0l */
78790 {
78791 { 0, 0, 0, 0 },
78792 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
78793 & ifmt_dadc16_b_r0h_r0l, { 0x7ce4 }
78794 },
78795/* dadd.w r1,r0 */
78796 {
78797 { 0, 0, 0, 0 },
78798 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
78799 & ifmt_dadc16_b_r0h_r0l, { 0x7de4 }
78800 },
78801/* bm$cond16c c */
78802 {
78803 { 0, 0, 0, 0 },
78804 { { MNEM, OP (COND16C), ' ', 'c', 0 } },
78805 & ifmt_bm16_c, { 0x7dd0 }
78806 },
78807/* bm$cond32 c */
78808 {
78809 { 0, 0, 0, 0 },
78810 { { MNEM, OP (COND32), ' ', 'c', 0 } },
78811 & ifmt_bm32_c, { 0xd928 }
78812 },
78813/* brk */
78814 {
78815 { 0, 0, 0, 0 },
78816 { { MNEM, 0 } },
78817 & ifmt_brk16, { 0x0 }
78818 },
78819/* brk */
78820 {
78821 { 0, 0, 0, 0 },
78822 { { MNEM, 0 } },
78823 & ifmt_brk16, { 0x0 }
78824 },
78825/* brk2 */
78826 {
78827 { 0, 0, 0, 0 },
78828 { { MNEM, 0 } },
78829 & ifmt_brk16, { 0x8 }
78830 },
78831/* dec.w ${Dst16An-S} */
78832 {
78833 { 0, 0, 0, 0 },
78834 { { MNEM, ' ', OP (DST16AN_S), 0 } },
78835 & ifmt_dec16_w, { 0xf2 }
78836 },
78837/* div.b #${Imm-16-QI} */
78838 {
78839 { 0, 0, 0, 0 },
78840 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78841 & ifmt_add16_b_G_sp, { 0x7ce100 }
78842 },
78843/* div.w #${Imm-16-HI} */
78844 {
78845 { 0, 0, 0, 0 },
78846 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78847 & ifmt_add16_w_G_sp, { 0x7de10000 }
78848 },
78849/* div.b #${Imm-16-QI} */
78850 {
78851 { 0, 0, 0, 0 },
78852 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78853 & ifmt_div32_b_Imm_16_QI, { 0xb04300 }
78854 },
78855/* div.w #${Imm-16-HI} */
78856 {
78857 { 0, 0, 0, 0 },
78858 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78859 & ifmt_div32_w_Imm_16_HI, { 0xb0530000 }
78860 },
78861/* divu.b #${Imm-16-QI} */
78862 {
78863 { 0, 0, 0, 0 },
78864 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78865 & ifmt_add16_b_G_sp, { 0x7ce000 }
78866 },
78867/* divu.w #${Imm-16-HI} */
78868 {
78869 { 0, 0, 0, 0 },
78870 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78871 & ifmt_add16_w_G_sp, { 0x7de00000 }
78872 },
78873/* divu.b #${Imm-16-QI} */
78874 {
78875 { 0, 0, 0, 0 },
78876 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78877 & ifmt_div32_b_Imm_16_QI, { 0xb00300 }
78878 },
78879/* divu.w #${Imm-16-HI} */
78880 {
78881 { 0, 0, 0, 0 },
78882 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78883 & ifmt_div32_w_Imm_16_HI, { 0xb0130000 }
78884 },
78885/* divx.b #${Imm-16-QI} */
78886 {
78887 { 0, 0, 0, 0 },
78888 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78889 & ifmt_add16_b_G_sp, { 0x7ce300 }
78890 },
78891/* divx.w #${Imm-16-HI} */
78892 {
78893 { 0, 0, 0, 0 },
78894 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78895 & ifmt_add16_w_G_sp, { 0x7de30000 }
78896 },
78897/* divx.b #${Imm-16-QI} */
78898 {
78899 { 0, 0, 0, 0 },
78900 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78901 & ifmt_div32_b_Imm_16_QI, { 0xb24300 }
78902 },
78903/* divx.w #${Imm-16-HI} */
78904 {
78905 { 0, 0, 0, 0 },
78906 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78907 & ifmt_div32_w_Imm_16_HI, { 0xb2530000 }
78908 },
78909/* dsbb.b #${Imm-16-QI} */
78910 {
78911 { 0, 0, 0, 0 },
78912 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78913 & ifmt_add32_l_imm8_S, { 0x7cef00 }
78914 },
78915/* dsbb.w #${Imm-16-HI} */
78916 {
78917 { 0, 0, 0, 0 },
78918 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78919 & ifmt_add32_l_imm16_G, { 0x7def0000 }
78920 },
78921/* dsbb.b r0h,r0l */
78922 {
78923 { 0, 0, 0, 0 },
78924 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
78925 & ifmt_dadc16_b_r0h_r0l, { 0x7ce7 }
78926 },
78927/* dsbb.w r1,r0 */
78928 {
78929 { 0, 0, 0, 0 },
78930 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
78931 & ifmt_dadc16_b_r0h_r0l, { 0x7de7 }
78932 },
78933/* dsub.b #${Imm-16-QI} */
78934 {
78935 { 0, 0, 0, 0 },
78936 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
78937 & ifmt_add32_l_imm8_S, { 0x7ced00 }
78938 },
78939/* dsub.w #${Imm-16-HI} */
78940 {
78941 { 0, 0, 0, 0 },
78942 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
78943 & ifmt_add32_l_imm16_G, { 0x7ded0000 }
78944 },
78945/* dsub.b r0h,r0l */
78946 {
78947 { 0, 0, 0, 0 },
78948 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
78949 & ifmt_dadc16_b_r0h_r0l, { 0x7ce5 }
78950 },
78951/* dsub.w r1,r0 */
78952 {
78953 { 0, 0, 0, 0 },
78954 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
78955 & ifmt_dadc16_b_r0h_r0l, { 0x7de5 }
78956 },
78957/* enter #${Dsp-16-u8} */
78958 {
78959 { 0, 0, 0, 0 },
78960 { { MNEM, ' ', '#', OP (DSP_16_U8), 0 } },
78961 & ifmt_enter16, { 0x7cf200 }
78962 },
78963/* exitd */
78964 {
78965 { 0, 0, 0, 0 },
78966 { { MNEM, 0 } },
78967 & ifmt_dadc16_b_r0h_r0l, { 0x7df2 }
78968 },
78969/* enter #${Dsp-8-u8} */
78970 {
78971 { 0, 0, 0, 0 },
78972 { { MNEM, ' ', '#', OP (DSP_8_U8), 0 } },
78973 & ifmt_enter32, { 0xec00 }
78974 },
78975/* exitd */
78976 {
78977 { 0, 0, 0, 0 },
78978 { { MNEM, 0 } },
78979 & ifmt_brk16, { 0xfc }
78980 },
78981/* fclr ${flags16} */
78982 {
78983 { 0, 0, 0, 0 },
78984 { { MNEM, ' ', OP (FLAGS16), 0 } },
78985 & ifmt_fclr16, { 0xeb05 }
78986 },
78987/* fset ${flags16} */
78988 {
78989 { 0, 0, 0, 0 },
78990 { { MNEM, ' ', OP (FLAGS16), 0 } },
78991 & ifmt_fclr16, { 0xeb04 }
78992 },
78993/* fclr ${flags32} */
78994 {
78995 { 0, 0, 0, 0 },
78996 { { MNEM, ' ', OP (FLAGS32), 0 } },
78997 & ifmt_fclr, { 0xd3e8 }
78998 },
78999/* fset ${flags32} */
79000 {
79001 { 0, 0, 0, 0 },
79002 { { MNEM, ' ', OP (FLAGS32), 0 } },
79003 & ifmt_fclr, { 0xd1e8 }
79004 },
79005/* inc.w ${Dst16An-S} */
79006 {
79007 { 0, 0, 0, 0 },
79008 { { MNEM, ' ', OP (DST16AN_S), 0 } },
79009 & ifmt_dec16_w, { 0xb2 }
79010 },
79011/* freit */
79012 {
79013 { 0, 0, 0, 0 },
79014 { { MNEM, 0 } },
79015 & ifmt_brk16, { 0x9f }
79016 },
79017/* int #${Dsp-10-u6} */
79018 {
79019 { 0, 0, 0, 0 },
79020 { { MNEM, ' ', '#', OP (DSP_10_U6), 0 } },
79021 & ifmt_int16, { 0xebc0 }
79022 },
79023/* into */
79024 {
79025 { 0, 0, 0, 0 },
79026 { { MNEM, 0 } },
79027 & ifmt_brk16, { 0xf6 }
79028 },
79029/* int #${Dsp-8-u6} */
79030 {
79031 { 0, 0, 0, 0 },
79032 { { MNEM, ' ', '#', OP (DSP_8_U6), 0 } },
79033 & ifmt_int32, { 0xbe00 }
79034 },
79035/* into */
79036 {
79037 { 0, 0, 0, 0 },
79038 { { MNEM, 0 } },
79039 & ifmt_brk16, { 0xbf }
79040 },
79041/* j$cond16j5 ${Lab-8-8} */
79042 {
79043 { 0, 0, 0, 0 },
79044 { { MNEM, OP (COND16J5), ' ', OP (LAB_8_8), 0 } },
79045 & ifmt_jcnd16_5, { 0x6800 }
79046 },
79047/* j$cond16j ${Lab-16-8} */
79048 {
79049 { 0, 0, 0, 0 },
79050 { { MNEM, OP (COND16J), ' ', OP (LAB_16_8), 0 } },
79051 & ifmt_jcnd16, { 0x7dc000 }
79052 },
79053/* j$cond32j ${Lab-8-8} */
79054 {
79055 { 0, 0, 0, 0 },
79056 { { MNEM, OP (COND32J), ' ', OP (LAB_8_8), 0 } },
79057 & ifmt_jcnd32, { 0x8a00 }
79058 },
79059/* jmp.s ${Lab-5-3} */
79060 {
79061 { 0, 0, 0, 0 },
79062 { { MNEM, ' ', OP (LAB_5_3), 0 } },
79063 & ifmt_jmp16_s, { 0x60 }
79064 },
79065/* jmp.b ${Lab-8-8} */
79066 {
79067 { 0, 0, 0, 0 },
79068 { { MNEM, ' ', OP (LAB_8_8), 0 } },
79069 & ifmt_jmp16_b, { 0xfe00 }
79070 },
79071/* jmp.w ${Lab-8-16} */
79072 {
79073 { 0, 0, 0, 0 },
79074 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79075 & ifmt_jmp16_w, { 0xf40000 }
79076 },
79077/* jmp.a ${Lab-8-24} */
79078 {
79079 { 0, 0, 0, 0 },
79080 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79081 & ifmt_jmp16_a, { 0xfc000000 }
79082 },
79083/* jmps #${Imm-8-QI} */
79084 {
79085 { 0, 0, 0, 0 },
79086 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79087 & ifmt_jmps16, { 0xee00 }
79088 },
79089/* jmp.s ${Lab32-jmp-s} */
79090 {
79091 { 0, 0, 0, 0 },
79092 { { MNEM, ' ', OP (LAB32_JMP_S), 0 } },
79093 & ifmt_jmp32_s, { 0x4a }
79094 },
79095/* jmp.b ${Lab-8-8} */
79096 {
79097 { 0, 0, 0, 0 },
79098 { { MNEM, ' ', OP (LAB_8_8), 0 } },
79099 & ifmt_jmp16_b, { 0xbb00 }
79100 },
79101/* jmp.w ${Lab-8-16} */
79102 {
79103 { 0, 0, 0, 0 },
79104 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79105 & ifmt_jmp16_w, { 0xce0000 }
79106 },
79107/* jmp.a ${Lab-8-24} */
79108 {
79109 { 0, 0, 0, 0 },
79110 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79111 & ifmt_jmp16_a, { 0xcc000000 }
79112 },
79113/* jmps #${Imm-8-QI} */
79114 {
79115 { 0, 0, 0, 0 },
79116 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79117 & ifmt_jmps16, { 0xdc00 }
79118 },
79119/* jsr.w ${Lab-8-16} */
79120 {
79121 { 0, 0, 0, 0 },
79122 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79123 & ifmt_jmp16_w, { 0xf50000 }
79124 },
79125/* jsr.a ${Lab-8-24} */
79126 {
79127 { 0, 0, 0, 0 },
79128 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79129 & ifmt_jmp16_a, { 0xfd000000 }
79130 },
79131/* jsr.w ${Lab-8-16} */
79132 {
79133 { 0, 0, 0, 0 },
79134 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79135 & ifmt_jmp16_w, { 0xcf0000 }
79136 },
79137/* jsr.a ${Lab-8-24} */
79138 {
79139 { 0, 0, 0, 0 },
79140 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79141 & ifmt_jmp16_a, { 0xcd000000 }
79142 },
79143/* jsrs #${Imm-8-QI} */
79144 {
79145 { 0, 0, 0, 0 },
79146 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79147 & ifmt_jmps16, { 0xef00 }
79148 },
79149/* jsrs #${Imm-8-QI} */
79150 {
79151 { 0, 0, 0, 0 },
79152 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79153 & ifmt_jmps16, { 0xdd00 }
79154 },
79155/* ldc #${Imm-16-HI},${cr16} */
79156 {
79157 { 0, 0, 0, 0 },
79158 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR16), 0 } },
79159 & ifmt_ldc16_imm16, { 0xeb000000 }
79160 },
79161/* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
79162 {
79163 { 0, 0, 0, 0 },
79164 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR1_UNPREFIXED_32), 0 } },
79165 & ifmt_ldc32_imm16_cr1, { 0xd5a80000 }
79166 },
79167/* ldc #${Dsp-16-u24},${cr2-32} */
79168 {
79169 { 0, 0, 0, 0 },
79170 { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR2_32), 0 } },
79171 & ifmt_ldc32_imm16_cr2, { 0xd5280000 }
79172 },
79173/* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
79174 {
79175 { 0, 0, 0, 0 },
79176 { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR3_UNPREFIXED_32), 0 } },
79177 & ifmt_ldc32_imm16_cr3, { 0xd5680000 }
79178 },
79179/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
79180 {
79181 { 0, 0, 0, 0 },
79182 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79183 & ifmt_ldctx16, { 0x7cf00000 }
79184 },
79185/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
79186 {
79187 { 0, 0, 0, 0 },
79188 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79189 & ifmt_ldctx16, { 0xb6c30000 }
79190 },
79191/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
79192 {
79193 { 0, 0, 0, 0 },
79194 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79195 & ifmt_ldctx16, { 0x7df00000 }
79196 },
79197/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
79198 {
79199 { 0, 0, 0, 0 },
79200 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79201 & ifmt_ldctx16, { 0xb6d30000 }
79202 },
79203/* ldipl #${Imm-13-u3} */
79204 {
79205 { 0, 0, 0, 0 },
79206 { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } },
79207 & ifmt_ldipl16_imm, { 0x7da0 }
79208 },
79209/* ldipl #${Imm-13-u3} */
79210 {
79211 { 0, 0, 0, 0 },
79212 { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } },
79213 & ifmt_ldipl16_imm, { 0xd5e8 }
79214 },
79215/* mov.b$S #${Imm-8-QI},a0 */
79216 {
79217 { 0, 0, 0, 0 },
79218 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '0', 0 } },
79219 & ifmt_jmps16, { 0xe200 }
79220 },
79221/* mov.b$S #${Imm-8-QI},a1 */
79222 {
79223 { 0, 0, 0, 0 },
79224 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '1', 0 } },
79225 & ifmt_jmps16, { 0xea00 }
79226 },
79227/* mov.w$S #${Imm-8-HI},a0 */
79228 {
79229 { 0, 0, 0, 0 },
79230 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } },
79231 & ifmt_mov16_w_S_imm_a0, { 0xa20000 }
79232 },
79233/* mov.w$S #${Imm-8-HI},a1 */
79234 {
79235 { 0, 0, 0, 0 },
79236 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
79237 & ifmt_mov16_w_S_imm_a0, { 0xaa0000 }
79238 },
79239/* mov.w$S #${Imm-8-HI},a0 */
79240 {
79241 { 0, 0, 0, 0 },
79242 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } },
79243 & ifmt_mov16_w_S_imm_a0, { 0x9c0000 }
79244 },
79245/* mov.w$S #${Imm-8-HI},a1 */
79246 {
79247 { 0, 0, 0, 0 },
79248 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
79249 & ifmt_mov16_w_S_imm_a0, { 0x9d0000 }
79250 },
f75eb1c0 79251/* mov.l$S #${Dsp-8-s24},a0 */
49f58d10
JB		 79252 {
79253 { 0, 0, 0, 0 },
f75eb1c0 79254 { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '0', 0 } },
49f58d10
JB		 79255 & ifmt_mov32_l_a0, { 0xbc000000 }
79256 },
f75eb1c0 79257/* mov.l$S #${Dsp-8-s24},a1 */
49f58d10
JB		 79258 {
79259 { 0, 0, 0, 0 },
f75eb1c0 79260 { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '1', 0 } },
49f58d10
JB		 79261 & ifmt_mov32_l_a0, { 0xbd000000 }
79262 },
79263/* mov.b$S r0l,a1 */
79264 {
79265 { 0, 0, 0, 0 },
79266 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'a', '1', 0 } },
79267 & ifmt_brk16, { 0x34 }
79268 },
79269/* mov.b$S r0h,a0 */
79270 {
79271 { 0, 0, 0, 0 },
79272 { { MNEM, OP (S), ' ', 'r', '0', 'h', ',', 'a', '0', 0 } },
79273 & ifmt_brk16, { 0x30 }
79274 },
79275/* nop */
79276 {
79277 { 0, 0, 0, 0 },
79278 { { MNEM, 0 } },
79279 & ifmt_brk16, { 0x4 }
79280 },
79281/* nop */
79282 {
79283 { 0, 0, 0, 0 },
79284 { { MNEM, 0 } },
79285 & ifmt_brk16, { 0xde }
79286 },
79287/* popc ${cr16} */
79288 {
79289 { 0, 0, 0, 0 },
79290 { { MNEM, ' ', OP (CR16), 0 } },
79291 & ifmt_popc16_imm16, { 0xeb03 }
79292 },
79293/* popc ${cr1-Unprefixed-32} */
79294 {
79295 { 0, 0, 0, 0 },
79296 { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } },
79297 & ifmt_popc32_imm16_cr1, { 0xd3a8 }
79298 },
79299/* popc ${cr2-32} */
79300 {
79301 { 0, 0, 0, 0 },
79302 { { MNEM, ' ', OP (CR2_32), 0 } },
79303 & ifmt_popc32_imm16_cr2, { 0xd328 }
79304 },
79305/* pushc ${cr16} */
79306 {
79307 { 0, 0, 0, 0 },
79308 { { MNEM, ' ', OP (CR16), 0 } },
79309 & ifmt_popc16_imm16, { 0xeb02 }
79310 },
79311/* pushc ${cr1-Unprefixed-32} */
79312 {
79313 { 0, 0, 0, 0 },
79314 { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } },
79315 & ifmt_popc32_imm16_cr1, { 0xd1a8 }
79316 },
79317/* pushc ${cr2-32} */
79318 {
79319 { 0, 0, 0, 0 },
79320 { { MNEM, ' ', OP (CR2_32), 0 } },
79321 & ifmt_popc32_imm16_cr2, { 0xd128 }
79322 },
79323/* popm ${Regsetpop} */
79324 {
79325 { 0, 0, 0, 0 },
79326 { { MNEM, ' ', OP (REGSETPOP), 0 } },
79327 & ifmt_popm16, { 0xed00 }
79328 },
79329/* pushm ${Regsetpush} */
79330 {
79331 { 0, 0, 0, 0 },
79332 { { MNEM, ' ', OP (REGSETPUSH), 0 } },
79333 & ifmt_pushm16, { 0xec00 }
79334 },
79335/* popm ${Regsetpop} */
79336 {
79337 { 0, 0, 0, 0 },
79338 { { MNEM, ' ', OP (REGSETPOP), 0 } },
79339 & ifmt_popm16, { 0x8e00 }
79340 },
79341/* pushm ${Regsetpush} */
79342 {
79343 { 0, 0, 0, 0 },
79344 { { MNEM, ' ', OP (REGSETPUSH), 0 } },
79345 & ifmt_pushm16, { 0x8f00 }
79346 },
79347/* push.b$G #${Imm-16-QI} */
79348 {
79349 { 0, 0, 0, 0 },
79350 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), 0 } },
79351 & ifmt_add32_l_imm8_S, { 0x7ce200 }
79352 },
79353/* push.w$G #${Imm-16-HI} */
79354 {
79355 { 0, 0, 0, 0 },
79356 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), 0 } },
79357 & ifmt_add32_l_imm16_G, { 0x7de20000 }
79358 },
79359/* push.b #Imm-8-QI */
79360 {
79361 { 0, 0, 0, 0 },
79362 { { MNEM, ' ', '#', 'I', 'm', 'm', '-', '8', '-', 'Q', 'I', 0 } },
79363 & ifmt_jmps16, { 0xae00 }
79364 },
79365/* push.w #${Imm-8-HI} */
79366 {
79367 { 0, 0, 0, 0 },
79368 { { MNEM, ' ', '#', OP (IMM_8_HI), 0 } },
79369 & ifmt_mov16_w_S_imm_a0, { 0xaf0000 }
79370 },
79371/* push.l #${Imm-16-SI} */
79372 {
79373 { 0, 0, 0, 0 },
79374 { { MNEM, ' ', '#', OP (IMM_16_SI), 0 } },
79375 & ifmt_push32_l_imm, { 0xb6530000 }
79376 },
79377/* reit */
79378 {
79379 { 0, 0, 0, 0 },
79380 { { MNEM, 0 } },
79381 & ifmt_brk16, { 0xfb }
79382 },
79383/* reit */
79384 {
79385 { 0, 0, 0, 0 },
79386 { { MNEM, 0 } },
79387 & ifmt_brk16, { 0x9e }
79388 },
79389/* rmpa.b */
79390 {
79391 { 0, 0, 0, 0 },
79392 { { MNEM, 0 } },
79393 & ifmt_dadc16_b_r0h_r0l, { 0x7cf1 }
79394 },
79395/* rmpa.w */
79396 {
79397 { 0, 0, 0, 0 },
79398 { { MNEM, 0 } },
79399 & ifmt_dadc16_b_r0h_r0l, { 0x7df1 }
79400 },
79401/* rmpa.b */
79402 {
79403 { 0, 0, 0, 0 },
79404 { { MNEM, 0 } },
79405 & ifmt_dadc16_b_r0h_r0l, { 0xb843 }
79406 },
79407/* rmpa.w */
79408 {
79409 { 0, 0, 0, 0 },
79410 { { MNEM, 0 } },
79411 & ifmt_dadc16_b_r0h_r0l, { 0xb853 }
79412 },
79413/* rts */
79414 {
79415 { 0, 0, 0, 0 },
79416 { { MNEM, 0 } },
79417 & ifmt_brk16, { 0xf3 }
79418 },
79419/* rts */
79420 {
79421 { 0, 0, 0, 0 },
79422 { { MNEM, 0 } },
79423 & ifmt_brk16, { 0xdf }
79424 },
79425/* scmpu.b */
79426 {
79427 { 0, 0, 0, 0 },
79428 { { MNEM, 0 } },
79429 & ifmt_dadc16_b_r0h_r0l, { 0xb8c3 }
79430 },
79431/* scmpu.w */
79432 {
79433 { 0, 0, 0, 0 },
79434 { { MNEM, 0 } },
79435 & ifmt_dadc16_b_r0h_r0l, { 0xb8d3 }
79436 },
79437/* sha.l #${Imm-sh-12-s4},r2r0 */
79438 {
79439 { 0, 0, 0, 0 },
79440 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } },
79441 & ifmt_sha16_L_imm_r2r0, { 0xeba0 }
79442 },
79443/* sha.l #${Imm-sh-12-s4},r3r1 */
79444 {
79445 { 0, 0, 0, 0 },
79446 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } },
79447 & ifmt_sha16_L_imm_r2r0, { 0xebb0 }
79448 },
79449/* sha.l r1h,r2r0 */
79450 {
79451 { 0, 0, 0, 0 },
79452 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } },
79453 & ifmt_dadc16_b_r0h_r0l, { 0xeb21 }
79454 },
79455/* sha.l r1h,r3r1 */
79456 {
79457 { 0, 0, 0, 0 },
79458 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } },
79459 & ifmt_dadc16_b_r0h_r0l, { 0xeb31 }
79460 },
79461/* shl.l #${Imm-sh-12-s4},r2r0 */
79462 {
79463 { 0, 0, 0, 0 },
79464 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } },
79465 & ifmt_sha16_L_imm_r2r0, { 0xeb80 }
79466 },
79467/* shl.l #${Imm-sh-12-s4},r3r1 */
79468 {
79469 { 0, 0, 0, 0 },
79470 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } },
79471 & ifmt_sha16_L_imm_r2r0, { 0xeb90 }
79472 },
79473/* shl.l r1h,r2r0 */
79474 {
79475 { 0, 0, 0, 0 },
79476 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } },
79477 & ifmt_dadc16_b_r0h_r0l, { 0xeb01 }
79478 },
79479/* shl.l r1h,r3r1 */
79480 {
79481 { 0, 0, 0, 0 },
79482 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } },
79483 & ifmt_dadc16_b_r0h_r0l, { 0xeb11 }
79484 },
79485/* sin.b */
79486 {
79487 { 0, 0, 0, 0 },
79488 { { MNEM, 0 } },
79489 & ifmt_dadc16_b_r0h_r0l, { 0xb283 }
79490 },
79491/* sin.w */
79492 {
79493 { 0, 0, 0, 0 },
79494 { { MNEM, 0 } },
79495 & ifmt_dadc16_b_r0h_r0l, { 0xb293 }
79496 },
79497/* smovb.b */
79498 {
79499 { 0, 0, 0, 0 },
79500 { { MNEM, 0 } },
79501 & ifmt_dadc16_b_r0h_r0l, { 0x7ce9 }
79502 },
79503/* smovb.w */
79504 {
79505 { 0, 0, 0, 0 },
79506 { { MNEM, 0 } },
79507 & ifmt_dadc16_b_r0h_r0l, { 0x7de9 }
79508 },
79509/* smovb.b */
79510 {
79511 { 0, 0, 0, 0 },
79512 { { MNEM, 0 } },
79513 & ifmt_dadc16_b_r0h_r0l, { 0xb683 }
79514 },
79515/* smovb.w */
79516 {
79517 { 0, 0, 0, 0 },
79518 { { MNEM, 0 } },
79519 & ifmt_dadc16_b_r0h_r0l, { 0xb693 }
79520 },
79521/* smovf.b */
79522 {
79523 { 0, 0, 0, 0 },
79524 { { MNEM, 0 } },
79525 & ifmt_dadc16_b_r0h_r0l, { 0x7ce8 }
79526 },
79527/* smovf.w */
79528 {
79529 { 0, 0, 0, 0 },
79530 { { MNEM, 0 } },
79531 & ifmt_dadc16_b_r0h_r0l, { 0x7de8 }
79532 },
79533/* smovf.b */
79534 {
79535 { 0, 0, 0, 0 },
79536 { { MNEM, 0 } },
79537 & ifmt_dadc16_b_r0h_r0l, { 0xb083 }
79538 },
79539/* smovf.w */
79540 {
79541 { 0, 0, 0, 0 },
79542 { { MNEM, 0 } },
79543 & ifmt_dadc16_b_r0h_r0l, { 0xb093 }
79544 },
79545/* smovu.b */
79546 {
79547 { 0, 0, 0, 0 },
79548 { { MNEM, 0 } },
79549 & ifmt_dadc16_b_r0h_r0l, { 0xb883 }
79550 },
79551/* smovu.w */
79552 {
79553 { 0, 0, 0, 0 },
79554 { { MNEM, 0 } },
79555 & ifmt_dadc16_b_r0h_r0l, { 0xb893 }
79556 },
79557/* sout.b */
79558 {
79559 { 0, 0, 0, 0 },
79560 { { MNEM, 0 } },
79561 & ifmt_dadc16_b_r0h_r0l, { 0xb483 }
79562 },
79563/* sout.w */
79564 {
79565 { 0, 0, 0, 0 },
79566 { { MNEM, 0 } },
79567 & ifmt_dadc16_b_r0h_r0l, { 0xb493 }
79568 },
79569/* sstr.b */
79570 {
79571 { 0, 0, 0, 0 },
79572 { { MNEM, 0 } },
79573 & ifmt_dadc16_b_r0h_r0l, { 0x7cea }
79574 },
79575/* sstr.w */
79576 {
79577 { 0, 0, 0, 0 },
79578 { { MNEM, 0 } },
79579 & ifmt_dadc16_b_r0h_r0l, { 0x7dea }
79580 },
79581/* sstr.b */
79582 {
79583 { 0, 0, 0, 0 },
79584 { { MNEM, 0 } },
79585 & ifmt_dadc16_b_r0h_r0l, { 0xb803 }
79586 },
79587/* sstr.w */
79588 {
79589 { 0, 0, 0, 0 },
79590 { { MNEM, 0 } },
79591 & ifmt_dadc16_b_r0h_r0l, { 0xb813 }
79592 },
79593/* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
79594 {
79595 { 0, 0, 0, 0 },
79596 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'h', 0 } },
79597 & ifmt_stzx16_imm8_imm8_r0h, { 0xdb0000 }
79598 },
79599/* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
79600 {
79601 { 0, 0, 0, 0 },
79602 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
79603 & ifmt_stzx16_imm8_imm8_r0h, { 0xdc0000 }
79604 },
79605/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */
79606 {
79607 { 0, 0, 0, 0 },
79608 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '8', '[', 's', 'b', ']', 0 } },
79609 & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xdd000000 }
79610 },
79611/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */
79612 {
79613 { 0, 0, 0, 0 },
79614 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '8', '[', 'f', 'b', ']', 0 } },
79615 & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xde000000 }
79616 },
79617/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */
79618 {
79619 { 0, 0, 0, 0 },
79620 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '1', '6', 0 } },
79621 & ifmt_stzx16_imm8_imm8_abs16, { 0xde000000 }
79622 },
79623/* und */
79624 {
79625 { 0, 0, 0, 0 },
79626 { { MNEM, 0 } },
79627 & ifmt_brk16, { 0xff }
79628 },
79629/* und */
79630 {
79631 { 0, 0, 0, 0 },
79632 { { MNEM, 0 } },
79633 & ifmt_brk16, { 0xff }
79634 },
79635/* wait */
79636 {
79637 { 0, 0, 0, 0 },
79638 { { MNEM, 0 } },
79639 & ifmt_dadc16_b_r0h_r0l, { 0x7df3 }
79640 },
79641/* wait */
79642 {
79643 { 0, 0, 0, 0 },
79644 { { MNEM, 0 } },
79645 & ifmt_dadc16_b_r0h_r0l, { 0xb203 }
79646 },
79647/* exts.w r0 */
79648 {
79649 { 0, 0, 0, 0 },
79650 { { MNEM, ' ', 'r', '0', 0 } },
79651 & ifmt_dadc16_b_r0h_r0l, { 0x7cf3 }
79652 },
79653/* src-indirect */
79654 {
79655 { 0, 0, 0, 0 },
79656 { { MNEM, 0 } },
79657 & ifmt_brk16, { 0x41 }
79658 },
79659/* dest-indirect */
79660 {
79661 { 0, 0, 0, 0 },
79662 { { MNEM, 0 } },
79663 & ifmt_brk16, { 0x9 }
79664 },
79665/* src-dest-indirect */
79666 {
79667 { 0, 0, 0, 0 },
79668 { { MNEM, 0 } },
79669 & ifmt_brk16, { 0x49 }
79670 },
79671};
79672
79673#undef A
79674#undef OPERAND
79675#undef MNEM
79676#undef OP
79677
79678/* Formats for ALIAS macro-insns. */
79679
79680#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
79681#define F(f) & m32c_cgen_ifld_table[M32C_##f]
79682#else
79683#define F(f) & m32c_cgen_ifld_table[M32C_/**/f]
79684#endif
92e0a941
DD		 79685static const CGEN_IFMT ifmt_add16_bQ_sp ATTRIBUTE_UNUSED = {
79686 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
79687};
79688
49f58d10
JB		 79689#undef F
79690
79691/* Each non-simple macro entry points to an array of expansion possibilities. */
79692
79693#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
79694#define A(a) (1 << CGEN_INSN_##a)
79695#else
79696#define A(a) (1 << CGEN_INSN_/**/a)
79697#endif
79698#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
79699#define OPERAND(op) M32C_OPERAND_##op
79700#else
79701#define OPERAND(op) M32C_OPERAND_/**/op
79702#endif
79703#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
79704#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
79705
79706/* The macro instruction table. */
79707
79708static const CGEN_IBASE m32c_cgen_macro_insn_table[] =
79709{
92e0a941
DD		 79710/* add.b:q #${Imm-12-s4},sp */
79711 {
79712 -1, "add16-bQ-sp", "add.b:q", 16,
79713 { 0|A(ALIAS), { (1<<MACH_BASE), (1<<ISA_M16C) } }
79714 },
49f58d10
JB		 79715};
79716
79717/* The macro instruction opcode table. */
79718
79719static const CGEN_OPCODE m32c_cgen_macro_insn_opcode_table[] =
79720{
92e0a941
DD		 79721/* add.b:q #${Imm-12-s4},sp */
79722 {
79723 { 0, 0, 0, 0 },
79724 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
79725 & ifmt_add16_bQ_sp, { 0x7db0 }
79726 },
49f58d10
JB		 79727};
79728
79729#undef A
79730#undef OPERAND
79731#undef MNEM
79732#undef OP
79733
79734#ifndef CGEN_ASM_HASH_P
79735#define CGEN_ASM_HASH_P(insn) 1
79736#endif
79737
79738#ifndef CGEN_DIS_HASH_P
79739#define CGEN_DIS_HASH_P(insn) 1
79740#endif
79741
79742/* Return non-zero if INSN is to be added to the hash table.
79743 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
79744
79745static int
79746asm_hash_insn_p (insn)
79747 const CGEN_INSN *insn ATTRIBUTE_UNUSED;
79748{
79749 return CGEN_ASM_HASH_P (insn);
79750}
79751
79752static int
79753dis_hash_insn_p (insn)
79754 const CGEN_INSN *insn;
79755{
79756 /* If building the hash table and the NO-DIS attribute is present,
79757 ignore. */
79758 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
79759 return 0;
79760 return CGEN_DIS_HASH_P (insn);
79761}
79762
79763#ifndef CGEN_ASM_HASH
79764#define CGEN_ASM_HASH_SIZE 127
79765#ifdef CGEN_MNEMONIC_OPERANDS
79766#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
79767#else
79768#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
79769#endif
79770#endif
79771
79772/* It doesn't make much sense to provide a default here,
79773 but while this is under development we do.
79774 BUFFER is a pointer to the bytes of the insn, target order.
79775 VALUE is the first base_insn_bitsize bits as an int in host order. */
79776
79777#ifndef CGEN_DIS_HASH
79778#define CGEN_DIS_HASH_SIZE 256
79779#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
79780#endif
79781
79782/* The result is the hash value of the insn.
79783 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
79784
79785static unsigned int
79786asm_hash_insn (mnem)
79787 const char * mnem;
79788{
79789 return CGEN_ASM_HASH (mnem);
79790}
79791
79792/* BUF is a pointer to the bytes of the insn, target order.
79793 VALUE is the first base_insn_bitsize bits as an int in host order. */
79794
79795static unsigned int
79796dis_hash_insn (buf, value)
79797 const char * buf ATTRIBUTE_UNUSED;
79798 CGEN_INSN_INT value ATTRIBUTE_UNUSED;
79799{
79800 return CGEN_DIS_HASH (buf, value);
79801}
79802
49f58d10
JB		 79803/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
79804
79805static void
e729279b 79806set_fields_bitsize (CGEN_FIELDS *fields, int size)
49f58d10
JB		 79807{
79808 CGEN_FIELDS_BITSIZE (fields) = size;
79809}
79810
79811/* Function to call before using the operand instance table.
79812 This plugs the opcode entries and macro instructions into the cpu table. */
79813
79814void
e729279b 79815m32c_cgen_init_opcode_table (CGEN_CPU_DESC cd)
49f58d10
JB		 79816{
79817 int i;
79818 int num_macros = (sizeof (m32c_cgen_macro_insn_table) /
79819 sizeof (m32c_cgen_macro_insn_table[0]));
79820 const CGEN_IBASE *ib = & m32c_cgen_macro_insn_table[0];
79821 const CGEN_OPCODE *oc = & m32c_cgen_macro_insn_opcode_table[0];
e729279b
NC		 79822 CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
79823
49f58d10
JB		 79824 memset (insns, 0, num_macros * sizeof (CGEN_INSN));
79825 for (i = 0; i < num_macros; ++i)
79826 {
79827 insns[i].base = &ib[i];
79828 insns[i].opcode = &oc[i];
79829 m32c_cgen_build_insn_regex (& insns[i]);
79830 }
79831 cd->macro_insn_table.init_entries = insns;
79832 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
79833 cd->macro_insn_table.num_init_entries = num_macros;
79834
79835 oc = & m32c_cgen_insn_opcode_table[0];
79836 insns = (CGEN_INSN *) cd->insn_table.init_entries;
79837 for (i = 0; i < MAX_INSNS; ++i)
79838 {
79839 insns[i].opcode = &oc[i];
79840 m32c_cgen_build_insn_regex (& insns[i]);
79841 }
79842
79843 cd->sizeof_fields = sizeof (CGEN_FIELDS);
79844 cd->set_fields_bitsize = set_fields_bitsize;
79845
79846 cd->asm_hash_p = asm_hash_insn_p;
79847 cd->asm_hash = asm_hash_insn;
79848 cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
79849
79850 cd->dis_hash_p = dis_hash_insn_p;
79851 cd->dis_hash = dis_hash_insn;
79852 cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
79853}
GDB Binutils - Deliverables
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