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1 | /* Assembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | - the resultant file is machine generated, cgen-asm.in isn't | |
6 | ||
7 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
8 | ||
9 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software Foundation, Inc., | |
23 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
26 | Keep that in mind. */ | |
27 | ||
28 | #include "sysdep.h" | |
29 | #include <ctype.h> | |
30 | #include <stdio.h> | |
31 | #include "ansidecl.h" | |
32 | #include "bfd.h" | |
33 | #include "symcat.h" | |
34 | #include "m32r-desc.h" | |
35 | #include "m32r-opc.h" | |
36 | #include "opintl.h" | |
37 | ||
38 | #undef min | |
39 | #define min(a,b) ((a) < (b) ? (a) : (b)) | |
40 | #undef max | |
41 | #define max(a,b) ((a) > (b) ? (a) : (b)) | |
42 | ||
43 | static const char * parse_insn_normal | |
44 | PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); | |
45 | \f | |
46 | /* -- assembler routines inserted here */ | |
47 | ||
48 | /* -- asm.c */ | |
49 | ||
50 | /* Handle '#' prefixes (i.e. skip over them). */ | |
51 | ||
52 | static const char * | |
53 | parse_hash (cd, strp, opindex, valuep) | |
54 | CGEN_CPU_DESC cd; | |
55 | const char **strp; | |
56 | int opindex; | |
57 | unsigned long *valuep; | |
58 | { | |
59 | if (**strp == '#') | |
60 | ++*strp; | |
61 | return NULL; | |
62 | } | |
63 | ||
64 | /* Handle shigh(), high(). */ | |
65 | ||
66 | static const char * | |
67 | parse_hi16 (cd, strp, opindex, valuep) | |
68 | CGEN_CPU_DESC cd; | |
69 | const char **strp; | |
70 | int opindex; | |
71 | unsigned long *valuep; | |
72 | { | |
73 | const char *errmsg; | |
74 | enum cgen_parse_operand_result result_type; | |
75 | bfd_vma value; | |
76 | ||
77 | if (**strp == '#') | |
78 | ++*strp; | |
79 | ||
80 | if (strncasecmp (*strp, "high(", 5) == 0) | |
81 | { | |
82 | *strp += 5; | |
83 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, | |
84 | &result_type, &value); | |
85 | if (**strp != ')') | |
86 | return "missing `)'"; | |
87 | ++*strp; | |
88 | if (errmsg == NULL | |
89 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
90 | value >>= 16; | |
91 | *valuep = value; | |
92 | return errmsg; | |
93 | } | |
94 | else if (strncasecmp (*strp, "shigh(", 6) == 0) | |
95 | { | |
96 | *strp += 6; | |
97 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, | |
98 | &result_type, &value); | |
99 | if (**strp != ')') | |
100 | return "missing `)'"; | |
101 | ++*strp; | |
102 | if (errmsg == NULL | |
103 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
104 | value = (value >> 16) + (value & 0x8000 ? 1 : 0); | |
105 | *valuep = value; | |
106 | return errmsg; | |
107 | } | |
108 | ||
109 | return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); | |
110 | } | |
111 | ||
112 | /* Handle low() in a signed context. Also handle sda(). | |
113 | The signedness of the value doesn't matter to low(), but this also | |
114 | handles the case where low() isn't present. */ | |
115 | ||
116 | static const char * | |
117 | parse_slo16 (cd, strp, opindex, valuep) | |
118 | CGEN_CPU_DESC cd; | |
119 | const char **strp; | |
120 | int opindex; | |
121 | long *valuep; | |
122 | { | |
123 | const char *errmsg; | |
124 | enum cgen_parse_operand_result result_type; | |
125 | bfd_vma value; | |
126 | ||
127 | if (**strp == '#') | |
128 | ++*strp; | |
129 | ||
130 | if (strncasecmp (*strp, "low(", 4) == 0) | |
131 | { | |
132 | *strp += 4; | |
133 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, | |
134 | &result_type, &value); | |
135 | if (**strp != ')') | |
136 | return "missing `)'"; | |
137 | ++*strp; | |
138 | if (errmsg == NULL | |
139 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
140 | value &= 0xffff; | |
141 | *valuep = value; | |
142 | return errmsg; | |
143 | } | |
144 | ||
145 | if (strncasecmp (*strp, "sda(", 4) == 0) | |
146 | { | |
147 | *strp += 4; | |
148 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, | |
149 | NULL, &value); | |
150 | if (**strp != ')') | |
151 | return "missing `)'"; | |
152 | ++*strp; | |
153 | *valuep = value; | |
154 | return errmsg; | |
155 | } | |
156 | ||
157 | return cgen_parse_signed_integer (cd, strp, opindex, valuep); | |
158 | } | |
159 | ||
160 | /* Handle low() in an unsigned context. | |
161 | The signedness of the value doesn't matter to low(), but this also | |
162 | handles the case where low() isn't present. */ | |
163 | ||
164 | static const char * | |
165 | parse_ulo16 (cd, strp, opindex, valuep) | |
166 | CGEN_CPU_DESC cd; | |
167 | const char **strp; | |
168 | int opindex; | |
169 | unsigned long *valuep; | |
170 | { | |
171 | const char *errmsg; | |
172 | enum cgen_parse_operand_result result_type; | |
173 | bfd_vma value; | |
174 | ||
175 | if (**strp == '#') | |
176 | ++*strp; | |
177 | ||
178 | if (strncasecmp (*strp, "low(", 4) == 0) | |
179 | { | |
180 | *strp += 4; | |
181 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, | |
182 | &result_type, &value); | |
183 | if (**strp != ')') | |
184 | return "missing `)'"; | |
185 | ++*strp; | |
186 | if (errmsg == NULL | |
187 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
188 | value &= 0xffff; | |
189 | *valuep = value; | |
190 | return errmsg; | |
191 | } | |
192 | ||
193 | return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); | |
194 | } | |
195 | ||
196 | /* -- */ | |
197 | ||
198 | /* Main entry point for operand parsing. | |
199 | ||
200 | This function is basically just a big switch statement. Earlier versions | |
201 | used tables to look up the function to use, but | |
202 | - if the table contains both assembler and disassembler functions then | |
203 | the disassembler contains much of the assembler and vice-versa, | |
204 | - there's a lot of inlining possibilities as things grow, | |
205 | - using a switch statement avoids the function call overhead. | |
206 | ||
207 | This function could be moved into `parse_insn_normal', but keeping it | |
208 | separate makes clear the interface between `parse_insn_normal' and each of | |
209 | the handlers. | |
210 | */ | |
211 | ||
212 | const char * | |
213 | m32r_cgen_parse_operand (cd, opindex, strp, fields) | |
214 | CGEN_CPU_DESC cd; | |
215 | int opindex; | |
216 | const char ** strp; | |
217 | CGEN_FIELDS * fields; | |
218 | { | |
219 | const char * errmsg; | |
220 | ||
221 | switch (opindex) | |
222 | { | |
223 | case M32R_OPERAND_DCR : | |
224 | errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r1); | |
225 | break; | |
226 | case M32R_OPERAND_DISP16 : | |
227 | { | |
228 | bfd_vma value; | |
229 | errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP16, 0, NULL, & value); | |
230 | fields->f_disp16 = value; | |
231 | } | |
232 | break; | |
233 | case M32R_OPERAND_DISP24 : | |
234 | { | |
235 | bfd_vma value; | |
236 | errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP24, 0, NULL, & value); | |
237 | fields->f_disp24 = value; | |
238 | } | |
239 | break; | |
240 | case M32R_OPERAND_DISP8 : | |
241 | { | |
242 | bfd_vma value; | |
243 | errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP8, 0, NULL, & value); | |
244 | fields->f_disp8 = value; | |
245 | } | |
246 | break; | |
247 | case M32R_OPERAND_DR : | |
248 | errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); | |
249 | break; | |
250 | case M32R_OPERAND_HASH : | |
251 | errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, &fields->f_nil); | |
252 | break; | |
253 | case M32R_OPERAND_HI16 : | |
254 | errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, &fields->f_hi16); | |
255 | break; | |
256 | case M32R_OPERAND_SCR : | |
257 | errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r2); | |
258 | break; | |
259 | case M32R_OPERAND_SIMM16 : | |
260 | errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM16, &fields->f_simm16); | |
261 | break; | |
262 | case M32R_OPERAND_SIMM8 : | |
263 | errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM8, &fields->f_simm8); | |
264 | break; | |
265 | case M32R_OPERAND_SLO16 : | |
266 | errmsg = parse_slo16 (cd, strp, M32R_OPERAND_SLO16, &fields->f_simm16); | |
267 | break; | |
268 | case M32R_OPERAND_SR : | |
269 | errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); | |
270 | break; | |
271 | case M32R_OPERAND_SRC1 : | |
272 | errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); | |
273 | break; | |
274 | case M32R_OPERAND_SRC2 : | |
275 | errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); | |
276 | break; | |
277 | case M32R_OPERAND_UIMM16 : | |
278 | errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM16, &fields->f_uimm16); | |
279 | break; | |
280 | case M32R_OPERAND_UIMM24 : | |
281 | { | |
282 | bfd_vma value; | |
283 | errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_UIMM24, 0, NULL, & value); | |
284 | fields->f_uimm24 = value; | |
285 | } | |
286 | break; | |
287 | case M32R_OPERAND_UIMM4 : | |
288 | errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4); | |
289 | break; | |
290 | case M32R_OPERAND_UIMM5 : | |
291 | errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5); | |
292 | break; | |
293 | case M32R_OPERAND_ULO16 : | |
294 | errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16); | |
295 | break; | |
296 | ||
297 | default : | |
298 | /* xgettext:c-format */ | |
299 | fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); | |
300 | abort (); | |
301 | } | |
302 | ||
303 | return errmsg; | |
304 | } | |
305 | ||
306 | cgen_parse_fn * const m32r_cgen_parse_handlers[] = | |
307 | { | |
308 | parse_insn_normal, | |
309 | }; | |
310 | ||
311 | void | |
312 | m32r_cgen_init_asm (cd) | |
313 | CGEN_CPU_DESC cd; | |
314 | { | |
315 | m32r_cgen_init_opcode_table (cd); | |
316 | m32r_cgen_init_ibld_table (cd); | |
317 | cd->parse_handlers = & m32r_cgen_parse_handlers[0]; | |
318 | cd->parse_operand = m32r_cgen_parse_operand; | |
319 | } | |
320 | ||
321 | \f | |
322 | /* Default insn parser. | |
323 | ||
324 | The syntax string is scanned and operands are parsed and stored in FIELDS. | |
325 | Relocs are queued as we go via other callbacks. | |
326 | ||
327 | ??? Note that this is currently an all-or-nothing parser. If we fail to | |
328 | parse the instruction, we return 0 and the caller will start over from | |
329 | the beginning. Backtracking will be necessary in parsing subexpressions, | |
330 | but that can be handled there. Not handling backtracking here may get | |
331 | expensive in the case of the m68k. Deal with later. | |
332 | ||
333 | Returns NULL for success, an error message for failure. | |
334 | */ | |
335 | ||
336 | static const char * | |
337 | parse_insn_normal (cd, insn, strp, fields) | |
338 | CGEN_CPU_DESC cd; | |
339 | const CGEN_INSN *insn; | |
340 | const char **strp; | |
341 | CGEN_FIELDS *fields; | |
342 | { | |
343 | /* ??? Runtime added insns not handled yet. */ | |
344 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
345 | const char *str = *strp; | |
346 | const char *errmsg; | |
347 | const char *p; | |
348 | const unsigned char * syn; | |
349 | #ifdef CGEN_MNEMONIC_OPERANDS | |
350 | /* FIXME: wip */ | |
351 | int past_opcode_p; | |
352 | #endif | |
353 | ||
354 | /* For now we assume the mnemonic is first (there are no leading operands). | |
355 | We can parse it without needing to set up operand parsing. | |
356 | GAS's input scrubber will ensure mnemonics are lowercase, but we may | |
357 | not be called from GAS. */ | |
358 | p = CGEN_INSN_MNEMONIC (insn); | |
359 | while (*p && tolower (*p) == tolower (*str)) | |
360 | ++p, ++str; | |
361 | ||
362 | if (* p || (* str && !isspace (* str))) | |
363 | return _("unrecognized instruction"); | |
364 | ||
365 | CGEN_INIT_PARSE (cd); | |
366 | cgen_init_parse_operand (cd); | |
367 | #ifdef CGEN_MNEMONIC_OPERANDS | |
368 | past_opcode_p = 0; | |
369 | #endif | |
370 | ||
371 | /* We don't check for (*str != '\0') here because we want to parse | |
372 | any trailing fake arguments in the syntax string. */ | |
373 | syn = CGEN_SYNTAX_STRING (syntax); | |
374 | ||
375 | /* Mnemonics come first for now, ensure valid string. */ | |
376 | if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) | |
377 | abort (); | |
378 | ||
379 | ++syn; | |
380 | ||
381 | while (* syn != 0) | |
382 | { | |
383 | /* Non operand chars must match exactly. */ | |
384 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
385 | { | |
386 | if (*str == CGEN_SYNTAX_CHAR (* syn)) | |
387 | { | |
388 | #ifdef CGEN_MNEMONIC_OPERANDS | |
389 | if (* syn == ' ') | |
390 | past_opcode_p = 1; | |
391 | #endif | |
392 | ++ syn; | |
393 | ++ str; | |
394 | } | |
395 | else | |
396 | { | |
397 | /* Syntax char didn't match. Can't be this insn. */ | |
398 | /* FIXME: would like to return something like | |
399 | "expected char `c'" */ | |
400 | return _("syntax error"); | |
401 | } | |
402 | continue; | |
403 | } | |
404 | ||
405 | /* We have an operand of some sort. */ | |
406 | errmsg = m32r_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), | |
407 | &str, fields); | |
408 | if (errmsg) | |
409 | return errmsg; | |
410 | ||
411 | /* Done with this operand, continue with next one. */ | |
412 | ++ syn; | |
413 | } | |
414 | ||
415 | /* If we're at the end of the syntax string, we're done. */ | |
416 | if (* syn == '\0') | |
417 | { | |
418 | /* FIXME: For the moment we assume a valid `str' can only contain | |
419 | blanks now. IE: We needn't try again with a longer version of | |
420 | the insn and it is assumed that longer versions of insns appear | |
421 | before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ | |
422 | while (isspace (* str)) | |
423 | ++ str; | |
424 | ||
425 | if (* str != '\0') | |
426 | return _("junk at end of line"); /* FIXME: would like to include `str' */ | |
427 | ||
428 | return NULL; | |
429 | } | |
430 | ||
431 | /* We couldn't parse it. */ | |
432 | return _("unrecognized instruction"); | |
433 | } | |
434 | \f | |
435 | /* Main entry point. | |
436 | This routine is called for each instruction to be assembled. | |
437 | STR points to the insn to be assembled. | |
438 | We assume all necessary tables have been initialized. | |
439 | The assembled instruction, less any fixups, is stored in BUF. | |
440 | Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value | |
441 | still needs to be converted to target byte order, otherwise BUF is an array | |
442 | of bytes in target byte order. | |
443 | The result is a pointer to the insn's entry in the opcode table, | |
444 | or NULL if an error occured (an error message will have already been | |
445 | printed). | |
446 | ||
447 | Note that when processing (non-alias) macro-insns, | |
448 | this function recurses. | |
449 | ||
450 | ??? It's possible to make this cpu-independent. | |
451 | One would have to deal with a few minor things. | |
452 | At this point in time doing so would be more of a curiosity than useful | |
453 | [for example this file isn't _that_ big], but keeping the possibility in | |
454 | mind helps keep the design clean. */ | |
455 | ||
456 | const CGEN_INSN * | |
457 | m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) | |
458 | CGEN_CPU_DESC cd; | |
459 | const char *str; | |
460 | CGEN_FIELDS *fields; | |
461 | CGEN_INSN_BYTES_PTR buf; | |
462 | char **errmsg; | |
463 | { | |
464 | const char *start; | |
465 | CGEN_INSN_LIST *ilist; | |
466 | ||
467 | /* Skip leading white space. */ | |
468 | while (isspace (* str)) | |
469 | ++ str; | |
470 | ||
471 | /* The instructions are stored in hashed lists. | |
472 | Get the first in the list. */ | |
473 | ilist = CGEN_ASM_LOOKUP_INSN (cd, str); | |
474 | ||
475 | /* Keep looking until we find a match. */ | |
476 | ||
477 | start = str; | |
478 | for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) | |
479 | { | |
480 | const CGEN_INSN *insn = ilist->insn; | |
481 | ||
482 | #if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ | |
483 | /* Is this insn supported by the selected cpu? */ | |
484 | if (! m32r_cgen_insn_supported (cd, insn)) | |
485 | continue; | |
486 | #endif | |
487 | ||
488 | /* If the RELAX attribute is set, this is an insn that shouldn't be | |
489 | chosen immediately. Instead, it is used during assembler/linker | |
490 | relaxation if possible. */ | |
491 | if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) | |
492 | continue; | |
493 | ||
494 | str = start; | |
495 | ||
496 | /* Allow parse/insert handlers to obtain length of insn. */ | |
497 | CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); | |
498 | ||
499 | if (! CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields)) | |
500 | { | |
501 | /* ??? 0 is passed for `pc' */ | |
502 | if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0) | |
503 | != NULL) | |
504 | continue; | |
505 | /* It is up to the caller to actually output the insn and any | |
506 | queued relocs. */ | |
507 | return insn; | |
508 | } | |
509 | ||
510 | /* Try the next entry. */ | |
511 | } | |
512 | ||
513 | /* FIXME: We can return a better error message than this. | |
514 | Need to track why it failed and pick the right one. */ | |
515 | { | |
516 | static char errbuf[100]; | |
517 | if (strlen (start) > 50) | |
518 | /* xgettext:c-format */ | |
519 | sprintf (errbuf, _("bad instruction `%.50s...'"), start); | |
520 | else | |
521 | /* xgettext:c-format */ | |
522 | sprintf (errbuf, _("bad instruction `%.50s'"), start); | |
523 | ||
524 | *errmsg = errbuf; | |
525 | return NULL; | |
526 | } | |
527 | } | |
528 | \f | |
529 | #if 0 /* This calls back to GAS which we can't do without care. */ | |
530 | ||
531 | /* Record each member of OPVALS in the assembler's symbol table. | |
532 | This lets GAS parse registers for us. | |
533 | ??? Interesting idea but not currently used. */ | |
534 | ||
535 | /* Record each member of OPVALS in the assembler's symbol table. | |
536 | FIXME: Not currently used. */ | |
537 | ||
538 | void | |
539 | m32r_cgen_asm_hash_keywords (cd, opvals) | |
540 | CGEN_CPU_DESC cd; | |
541 | CGEN_KEYWORD *opvals; | |
542 | { | |
543 | CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); | |
544 | const CGEN_KEYWORD_ENTRY * ke; | |
545 | ||
546 | while ((ke = cgen_keyword_search_next (& search)) != NULL) | |
547 | { | |
548 | #if 0 /* Unnecessary, should be done in the search routine. */ | |
549 | if (! m32r_cgen_opval_supported (ke)) | |
550 | continue; | |
551 | #endif | |
552 | cgen_asm_record_register (cd, ke->name, ke->value); | |
553 | } | |
554 | } | |
555 | ||
556 | #endif /* 0 */ |