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Apply H>J's patch to propogate changes made by Thomas de Lellis to arm.h
[deliverable/binutils-gdb.git] / opcodes / m32r-desc.c
CommitLineData
252b5132
RH		 1/* CPU data for m32r.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include <ctype.h>
27#include <stdio.h>
28#include <stdarg.h>
29#include "ansidecl.h"
30#include "bfd.h"
31#include "symcat.h"
32#include "m32r-desc.h"
33#include "m32r-opc.h"
34#include "opintl.h"
35
36/* Attributes. */
37
38static const CGEN_ATTR_ENTRY bool_attr[] =
39{
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
43};
44
45static const CGEN_ATTR_ENTRY MACH_attr[] =
46{
47 { "base", MACH_BASE },
48 { "m32r", MACH_M32R },
1fa60b5d 49 { "m32rx", MACH_M32RX },
252b5132
RH		 50 { "max", MACH_MAX },
51 { 0, 0 }
52};
53
54static const CGEN_ATTR_ENTRY ISA_attr[] =
55{
56 { "m32r", ISA_M32R },
57 { "max", ISA_MAX },
58 { 0, 0 }
59};
60
1fa60b5d
DE		 61static const CGEN_ATTR_ENTRY PIPE_attr[] =
62{
63 { "NONE", PIPE_NONE },
64 { "O", PIPE_O },
65 { "S", PIPE_S },
66 { "OS", PIPE_OS },
67 { 0, 0 }
68};
69
252b5132
RH		 70const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
71{
72 { "MACH", & MACH_attr[0] },
73 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
74 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
75 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
76 { "RESERVED", &bool_attr[0], &bool_attr[0] },
77 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
78 { "SIGNED", &bool_attr[0], &bool_attr[0] },
79 { "RELOC", &bool_attr[0], &bool_attr[0] },
80 { 0, 0, 0 }
81};
82
83const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
84{
85 { "MACH", & MACH_attr[0] },
86 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "PC", &bool_attr[0], &bool_attr[0] },
89 { "PROFILE", &bool_attr[0], &bool_attr[0] },
90 { 0, 0, 0 }
91};
92
93const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
94{
95 { "MACH", & MACH_attr[0] },
96 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
97 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
98 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
99 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
100 { "SIGNED", &bool_attr[0], &bool_attr[0] },
101 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
102 { "RELAX", &bool_attr[0], &bool_attr[0] },
103 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
104 { "RELOC", &bool_attr[0], &bool_attr[0] },
105 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
106 { 0, 0, 0 }
107};
108
109const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
110{
111 { "MACH", & MACH_attr[0] },
1fa60b5d 112 { "PIPE", & PIPE_attr[0] },
252b5132
RH		 113 { "ALIAS", &bool_attr[0], &bool_attr[0] },
114 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
115 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
116 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
117 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
118 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
119 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
120 { "RELAX", &bool_attr[0], &bool_attr[0] },
121 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
122 { "PBB", &bool_attr[0], &bool_attr[0] },
123 { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
1fa60b5d 124 { "SPECIAL", &bool_attr[0], &bool_attr[0] },
252b5132
RH		 125 { 0, 0, 0 }
126};
127
128/* Instruction set variants. */
129
130static const CGEN_ISA m32r_cgen_isa_table[] = {
131 { "m32r", 32, 32, 16, 32, },
132 { 0 }
133};
134
135/* Machine variants. */
136
137static const CGEN_MACH m32r_cgen_mach_table[] = {
138 { "m32r", "m32r", MACH_M32R },
1fa60b5d 139 { "m32rx", "m32rx", MACH_M32RX },
252b5132
RH		 140 { 0 }
141};
142
143static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
144{
145 { "fp", 13 },
146 { "lr", 14 },
147 { "sp", 15 },
148 { "r0", 0 },
149 { "r1", 1 },
150 { "r2", 2 },
151 { "r3", 3 },
152 { "r4", 4 },
153 { "r5", 5 },
154 { "r6", 6 },
155 { "r7", 7 },
156 { "r8", 8 },
157 { "r9", 9 },
158 { "r10", 10 },
159 { "r11", 11 },
160 { "r12", 12 },
161 { "r13", 13 },
162 { "r14", 14 },
163 { "r15", 15 }
164};
165
166CGEN_KEYWORD m32r_cgen_opval_gr_names =
167{
168 & m32r_cgen_opval_gr_names_entries[0],
169 19
170};
171
172static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
173{
174 { "psw", 0 },
175 { "cbr", 1 },
176 { "spi", 2 },
177 { "spu", 3 },
178 { "bpc", 6 },
179 { "bbpsw", 8 },
180 { "bbpc", 14 },
181 { "cr0", 0 },
182 { "cr1", 1 },
183 { "cr2", 2 },
184 { "cr3", 3 },
185 { "cr4", 4 },
186 { "cr5", 5 },
187 { "cr6", 6 },
188 { "cr7", 7 },
189 { "cr8", 8 },
190 { "cr9", 9 },
191 { "cr10", 10 },
192 { "cr11", 11 },
193 { "cr12", 12 },
194 { "cr13", 13 },
195 { "cr14", 14 },
196 { "cr15", 15 }
197};
198
199CGEN_KEYWORD m32r_cgen_opval_cr_names =
200{
201 & m32r_cgen_opval_cr_names_entries[0],
202 23
203};
204
1fa60b5d
DE		 205static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
206{
207 { "a0", 0 },
208 { "a1", 1 }
209};
210
211CGEN_KEYWORD m32r_cgen_opval_h_accums =
212{
213 & m32r_cgen_opval_h_accums_entries[0],
214 2
215};
216
252b5132
RH		 217
218
219/* The hardware table. */
220
221#define A(a) (1 << CONCAT2 (CGEN_HW_,a))
222
223const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
224{
225 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
226 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
227 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
228 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
229 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
230 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
231 { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
232 { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
233 { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
234 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
235 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
236 { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1fa60b5d 237 { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
252b5132
RH		 238 { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
239 { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
240 { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
241 { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
242 { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
243 { 0 }
244};
245
246#undef A
247
248/* The instruction field table. */
249
250#define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
251
252const CGEN_IFLD m32r_cgen_ifld_table[] =
253{
254 { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
255 { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
256 { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
257 { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
258 { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
259 { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
260 { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
261 { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
262 { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
263 { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
264 { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
265 { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
266 { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
267 { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
268 { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
269 { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
270 { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
1fa60b5d
DE		 271 { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } },
272 { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } },
273 { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } },
274 { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
275 { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
276 { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
277 { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
278 { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
252b5132
RH		 279 { 0 }
280};
281
282#undef A
283
284/* The operand table. */
285
286#define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
287#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
288
289const CGEN_OPERAND m32r_cgen_operand_table[] =
290{
291/* pc: program counter */
292 { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
293 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
294/* sr: source register */
295 { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
296 { 0, { (1<<MACH_BASE) } } },
297/* dr: destination register */
298 { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
299 { 0, { (1<<MACH_BASE) } } },
300/* src1: source register 1 */
301 { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
302 { 0, { (1<<MACH_BASE) } } },
303/* src2: source register 2 */
304 { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
305 { 0, { (1<<MACH_BASE) } } },
306/* scr: source control register */
307 { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
308 { 0, { (1<<MACH_BASE) } } },
309/* dcr: destination control register */
310 { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
311 { 0, { (1<<MACH_BASE) } } },
312/* simm8: 8 bit signed immediate */
313 { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
314 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
315/* simm16: 16 bit signed immediate */
316 { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
317 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
318/* uimm4: 4 bit trap number */
319 { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
320 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
321/* uimm5: 5 bit shift count */
322 { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
323 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
324/* uimm16: 16 bit unsigned immediate */
325 { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
326 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
1fa60b5d
DE		 327/* imm1: 1 bit immediate */
328 { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
329 { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
330/* accd: accumulator destination register */
331 { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
332 { 0, { (1<<MACH_M32RX) } } },
333/* accs: accumulator source register */
334 { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
335 { 0, { (1<<MACH_M32RX) } } },
336/* acc: accumulator reg (d) */
337 { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
338 { 0, { (1<<MACH_M32RX) } } },
252b5132
RH		 339/* hash: # prefix */
340 { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
341 { 0, { (1<<MACH_BASE) } } },
342/* hi16: high 16 bit immediate, sign optional */
343 { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
344 { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
345/* slo16: 16 bit signed immediate, for low() */
346 { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
347 { 0, { (1<<MACH_BASE) } } },
348/* ulo16: 16 bit unsigned immediate, for low() */
349 { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
350 { 0, { (1<<MACH_BASE) } } },
351/* uimm24: 24 bit address */
352 { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
353 { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
354/* disp8: 8 bit displacement */
355 { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
356 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
357/* disp16: 16 bit displacement */
358 { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
359 { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
360/* disp24: 24 bit displacement */
361 { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
362 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
363/* condbit: condition bit */
364 { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
365 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
366/* accum: accumulator */
367 { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
368 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
369 { 0 }
370};
371
372#undef A
373
374#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
375#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
376
377/* The instruction table. */
378
379static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
380{
381 /* Special null first entry.
382 A `num' value of zero is thus invalid.
383 Also, the special `invalid' insn resides here. */
384 { 0, 0, 0 },
385/* add $dr,$sr */
386 {
387 M32R_INSN_ADD, "add", "add", 16,
1fa60b5d 388 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 389 },
390/* add3 $dr,$sr,$hash$slo16 */
391 {
392 M32R_INSN_ADD3, "add3", "add3", 32,
1fa60b5d 393 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 394 },
395/* and $dr,$sr */
396 {
397 M32R_INSN_AND, "and", "and", 16,
1fa60b5d 398 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 399 },
400/* and3 $dr,$sr,$uimm16 */
401 {
402 M32R_INSN_AND3, "and3", "and3", 32,
1fa60b5d 403 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 404 },
405/* or $dr,$sr */
406 {
407 M32R_INSN_OR, "or", "or", 16,
1fa60b5d 408 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 409 },
410/* or3 $dr,$sr,$hash$ulo16 */
411 {
412 M32R_INSN_OR3, "or3", "or3", 32,
1fa60b5d 413 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 414 },
415/* xor $dr,$sr */
416 {
417 M32R_INSN_XOR, "xor", "xor", 16,
1fa60b5d 418 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 419 },
420/* xor3 $dr,$sr,$uimm16 */
421 {
422 M32R_INSN_XOR3, "xor3", "xor3", 32,
1fa60b5d 423 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 424 },
425/* addi $dr,$simm8 */
426 {
427 M32R_INSN_ADDI, "addi", "addi", 16,
1fa60b5d 428 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 429 },
430/* addv $dr,$sr */
431 {
432 M32R_INSN_ADDV, "addv", "addv", 16,
1fa60b5d 433 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 434 },
435/* addv3 $dr,$sr,$simm16 */
436 {
437 M32R_INSN_ADDV3, "addv3", "addv3", 32,
1fa60b5d 438 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 439 },
440/* addx $dr,$sr */
441 {
442 M32R_INSN_ADDX, "addx", "addx", 16,
1fa60b5d 443 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 444 },
445/* bc.s $disp8 */
446 {
447 M32R_INSN_BC8, "bc8", "bc.s", 16,
1fa60b5d 448 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 449 },
450/* bc.l $disp24 */
451 {
452 M32R_INSN_BC24, "bc24", "bc.l", 32,
1fa60b5d 453 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 454 },
455/* beq $src1,$src2,$disp16 */
456 {
457 M32R_INSN_BEQ, "beq", "beq", 32,
1fa60b5d 458 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 459 },
460/* beqz $src2,$disp16 */
461 {
462 M32R_INSN_BEQZ, "beqz", "beqz", 32,
1fa60b5d 463 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 464 },
465/* bgez $src2,$disp16 */
466 {
467 M32R_INSN_BGEZ, "bgez", "bgez", 32,
1fa60b5d 468 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 469 },
470/* bgtz $src2,$disp16 */
471 {
472 M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
1fa60b5d 473 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 474 },
475/* blez $src2,$disp16 */
476 {
477 M32R_INSN_BLEZ, "blez", "blez", 32,
1fa60b5d 478 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 479 },
480/* bltz $src2,$disp16 */
481 {
482 M32R_INSN_BLTZ, "bltz", "bltz", 32,
1fa60b5d 483 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 484 },
485/* bnez $src2,$disp16 */
486 {
487 M32R_INSN_BNEZ, "bnez", "bnez", 32,
1fa60b5d 488 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 489 },
490/* bl.s $disp8 */
491 {
492 M32R_INSN_BL8, "bl8", "bl.s", 16,
1fa60b5d 493 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 494 },
495/* bl.l $disp24 */
496 {
497 M32R_INSN_BL24, "bl24", "bl.l", 32,
1fa60b5d
DE		 498 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
499 },
500/* bcl.s $disp8 */
501 {
502 M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
503 { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
504 },
505/* bcl.l $disp24 */
506 {
507 M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
508 { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
252b5132
RH		 509 },
510/* bnc.s $disp8 */
511 {
512 M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
1fa60b5d 513 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 514 },
515/* bnc.l $disp24 */
516 {
517 M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
1fa60b5d 518 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 519 },
520/* bne $src1,$src2,$disp16 */
521 {
522 M32R_INSN_BNE, "bne", "bne", 32,
1fa60b5d 523 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 524 },
525/* bra.s $disp8 */
526 {
527 M32R_INSN_BRA8, "bra8", "bra.s", 16,
1fa60b5d 528 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 529 },
530/* bra.l $disp24 */
531 {
532 M32R_INSN_BRA24, "bra24", "bra.l", 32,
1fa60b5d
DE		 533 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
534 },
535/* bncl.s $disp8 */
536 {
537 M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
538 { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
539 },
540/* bncl.l $disp24 */
541 {
542 M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
543 { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
252b5132
RH		 544 },
545/* cmp $src1,$src2 */
546 {
547 M32R_INSN_CMP, "cmp", "cmp", 16,
1fa60b5d 548 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 549 },
550/* cmpi $src2,$simm16 */
551 {
552 M32R_INSN_CMPI, "cmpi", "cmpi", 32,
1fa60b5d 553 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 554 },
555/* cmpu $src1,$src2 */
556 {
557 M32R_INSN_CMPU, "cmpu", "cmpu", 16,
1fa60b5d 558 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 559 },
560/* cmpui $src2,$simm16 */
561 {
562 M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
1fa60b5d
DE		 563 { 0, { (1<<MACH_BASE), PIPE_NONE } }
564 },
565/* cmpeq $src1,$src2 */
566 {
567 M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
568 { 0, { (1<<MACH_M32RX), PIPE_OS } }
569 },
570/* cmpz $src2 */
571 {
572 M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
573 { 0, { (1<<MACH_M32RX), PIPE_OS } }
252b5132
RH		 574 },
575/* div $dr,$sr */
576 {
577 M32R_INSN_DIV, "div", "div", 32,
1fa60b5d 578 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 579 },
580/* divu $dr,$sr */
581 {
582 M32R_INSN_DIVU, "divu", "divu", 32,
1fa60b5d 583 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 584 },
585/* rem $dr,$sr */
586 {
587 M32R_INSN_REM, "rem", "rem", 32,
1fa60b5d 588 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 589 },
590/* remu $dr,$sr */
591 {
592 M32R_INSN_REMU, "remu", "remu", 32,
1fa60b5d
DE		 593 { 0, { (1<<MACH_BASE), PIPE_NONE } }
594 },
595/* divh $dr,$sr */
596 {
597 M32R_INSN_DIVH, "divh", "divh", 32,
598 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
599 },
600/* jc $sr */
601 {
602 M32R_INSN_JC, "jc", "jc", 16,
603 { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
604 },
605/* jnc $sr */
606 {
607 M32R_INSN_JNC, "jnc", "jnc", 16,
608 { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
252b5132
RH		 609 },
610/* jl $sr */
611 {
612 M32R_INSN_JL, "jl", "jl", 16,
1fa60b5d 613 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 614 },
615/* jmp $sr */
616 {
617 M32R_INSN_JMP, "jmp", "jmp", 16,
1fa60b5d 618 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 619 },
620/* ld $dr,@$sr */
621 {
622 M32R_INSN_LD, "ld", "ld", 16,
1fa60b5d 623 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 624 },
625/* ld $dr,@($slo16,$sr) */
626 {
627 M32R_INSN_LD_D, "ld-d", "ld", 32,
1fa60b5d 628 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 629 },
630/* ldb $dr,@$sr */
631 {
632 M32R_INSN_LDB, "ldb", "ldb", 16,
1fa60b5d 633 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 634 },
635/* ldb $dr,@($slo16,$sr) */
636 {
637 M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
1fa60b5d 638 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 639 },
640/* ldh $dr,@$sr */
641 {
642 M32R_INSN_LDH, "ldh", "ldh", 16,
1fa60b5d 643 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 644 },
645/* ldh $dr,@($slo16,$sr) */
646 {
647 M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
1fa60b5d 648 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 649 },
650/* ldub $dr,@$sr */
651 {
652 M32R_INSN_LDUB, "ldub", "ldub", 16,
1fa60b5d 653 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 654 },
655/* ldub $dr,@($slo16,$sr) */
656 {
657 M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
1fa60b5d 658 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 659 },
660/* lduh $dr,@$sr */
661 {
662 M32R_INSN_LDUH, "lduh", "lduh", 16,
1fa60b5d 663 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 664 },
665/* lduh $dr,@($slo16,$sr) */
666 {
667 M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
1fa60b5d 668 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 669 },
670/* ld $dr,@$sr+ */
671 {
672 M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
1fa60b5d 673 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 674 },
675/* ld24 $dr,$uimm24 */
676 {
677 M32R_INSN_LD24, "ld24", "ld24", 32,
1fa60b5d 678 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 679 },
680/* ldi8 $dr,$simm8 */
681 {
682 M32R_INSN_LDI8, "ldi8", "ldi8", 16,
1fa60b5d 683 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 684 },
685/* ldi16 $dr,$hash$slo16 */
686 {
687 M32R_INSN_LDI16, "ldi16", "ldi16", 32,
1fa60b5d 688 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 689 },
690/* lock $dr,@$sr */
691 {
692 M32R_INSN_LOCK, "lock", "lock", 16,
1fa60b5d 693 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 694 },
695/* machi $src1,$src2 */
696 {
697 M32R_INSN_MACHI, "machi", "machi", 16,
1fa60b5d
DE		 698 { 0, { (1<<MACH_M32R), PIPE_S } }
699 },
700/* machi $src1,$src2,$acc */
701 {
702 M32R_INSN_MACHI_A, "machi-a", "machi", 16,
703 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 704 },
705/* maclo $src1,$src2 */
706 {
707 M32R_INSN_MACLO, "maclo", "maclo", 16,
1fa60b5d
DE		 708 { 0, { (1<<MACH_M32R), PIPE_S } }
709 },
710/* maclo $src1,$src2,$acc */
711 {
712 M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
713 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 714 },
715/* macwhi $src1,$src2 */
716 {
717 M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
1fa60b5d
DE		 718 { 0, { (1<<MACH_M32R), PIPE_S } }
719 },
720/* macwhi $src1,$src2,$acc */
721 {
722 M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
723 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 724 },
725/* macwlo $src1,$src2 */
726 {
727 M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
1fa60b5d
DE		 728 { 0, { (1<<MACH_M32R), PIPE_S } }
729 },
730/* macwlo $src1,$src2,$acc */
731 {
732 M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
733 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 734 },
735/* mul $dr,$sr */
736 {
737 M32R_INSN_MUL, "mul", "mul", 16,
1fa60b5d 738 { 0, { (1<<MACH_BASE), PIPE_S } }
252b5132
RH		 739 },
740/* mulhi $src1,$src2 */
741 {
742 M32R_INSN_MULHI, "mulhi", "mulhi", 16,
1fa60b5d
DE		 743 { 0, { (1<<MACH_M32R), PIPE_S } }
744 },
745/* mulhi $src1,$src2,$acc */
746 {
747 M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
748 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 749 },
750/* mullo $src1,$src2 */
751 {
752 M32R_INSN_MULLO, "mullo", "mullo", 16,
1fa60b5d
DE		 753 { 0, { (1<<MACH_M32R), PIPE_S } }
754 },
755/* mullo $src1,$src2,$acc */
756 {
757 M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
758 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 759 },
760/* mulwhi $src1,$src2 */
761 {
762 M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
1fa60b5d
DE		 763 { 0, { (1<<MACH_M32R), PIPE_S } }
764 },
765/* mulwhi $src1,$src2,$acc */
766 {
767 M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
768 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 769 },
770/* mulwlo $src1,$src2 */
771 {
772 M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
1fa60b5d
DE		 773 { 0, { (1<<MACH_M32R), PIPE_S } }
774 },
775/* mulwlo $src1,$src2,$acc */
776 {
777 M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
778 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 779 },
780/* mv $dr,$sr */
781 {
782 M32R_INSN_MV, "mv", "mv", 16,
1fa60b5d 783 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 784 },
785/* mvfachi $dr */
786 {
787 M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
1fa60b5d
DE		 788 { 0, { (1<<MACH_M32R), PIPE_S } }
789 },
790/* mvfachi $dr,$accs */
791 {
792 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
793 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 794 },
795/* mvfaclo $dr */
796 {
797 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
1fa60b5d
DE		 798 { 0, { (1<<MACH_M32R), PIPE_S } }
799 },
800/* mvfaclo $dr,$accs */
801 {
802 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
803 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 804 },
805/* mvfacmi $dr */
806 {
807 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
1fa60b5d
DE		 808 { 0, { (1<<MACH_M32R), PIPE_S } }
809 },
810/* mvfacmi $dr,$accs */
811 {
812 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
813 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 814 },
815/* mvfc $dr,$scr */
816 {
817 M32R_INSN_MVFC, "mvfc", "mvfc", 16,
1fa60b5d 818 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 819 },
820/* mvtachi $src1 */
821 {
822 M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
1fa60b5d
DE		 823 { 0, { (1<<MACH_M32R), PIPE_S } }
824 },
825/* mvtachi $src1,$accs */
826 {
827 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
828 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 829 },
830/* mvtaclo $src1 */
831 {
832 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
1fa60b5d
DE		 833 { 0, { (1<<MACH_M32R), PIPE_S } }
834 },
835/* mvtaclo $src1,$accs */
836 {
837 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
838 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 839 },
840/* mvtc $sr,$dcr */
841 {
842 M32R_INSN_MVTC, "mvtc", "mvtc", 16,
1fa60b5d 843 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 844 },
845/* neg $dr,$sr */
846 {
847 M32R_INSN_NEG, "neg", "neg", 16,
1fa60b5d 848 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 849 },
850/* nop */
851 {
852 M32R_INSN_NOP, "nop", "nop", 16,
1fa60b5d 853 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 854 },
855/* not $dr,$sr */
856 {
857 M32R_INSN_NOT, "not", "not", 16,
1fa60b5d 858 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 859 },
860/* rac */
861 {
862 M32R_INSN_RAC, "rac", "rac", 16,
1fa60b5d
DE		 863 { 0, { (1<<MACH_M32R), PIPE_S } }
864 },
865/* rac $accd,$accs,$imm1 */
866 {
867 M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
868 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 869 },
870/* rach */
871 {
872 M32R_INSN_RACH, "rach", "rach", 16,
1fa60b5d
DE		 873 { 0, { (1<<MACH_M32R), PIPE_S } }
874 },
875/* rach $accd,$accs,$imm1 */
876 {
877 M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
878 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 879 },
880/* rte */
881 {
882 M32R_INSN_RTE, "rte", "rte", 16,
1fa60b5d 883 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 884 },
885/* seth $dr,$hash$hi16 */
886 {
887 M32R_INSN_SETH, "seth", "seth", 32,
1fa60b5d 888 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 889 },
890/* sll $dr,$sr */
891 {
892 M32R_INSN_SLL, "sll", "sll", 16,
1fa60b5d 893 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 894 },
895/* sll3 $dr,$sr,$simm16 */
896 {
897 M32R_INSN_SLL3, "sll3", "sll3", 32,
1fa60b5d 898 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 899 },
900/* slli $dr,$uimm5 */
901 {
902 M32R_INSN_SLLI, "slli", "slli", 16,
1fa60b5d 903 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 904 },
905/* sra $dr,$sr */
906 {
907 M32R_INSN_SRA, "sra", "sra", 16,
1fa60b5d 908 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 909 },
910/* sra3 $dr,$sr,$simm16 */
911 {
912 M32R_INSN_SRA3, "sra3", "sra3", 32,
1fa60b5d 913 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 914 },
915/* srai $dr,$uimm5 */
916 {
917 M32R_INSN_SRAI, "srai", "srai", 16,
1fa60b5d 918 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 919 },
920/* srl $dr,$sr */
921 {
922 M32R_INSN_SRL, "srl", "srl", 16,
1fa60b5d 923 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 924 },
925/* srl3 $dr,$sr,$simm16 */
926 {
927 M32R_INSN_SRL3, "srl3", "srl3", 32,
1fa60b5d 928 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 929 },
930/* srli $dr,$uimm5 */
931 {
932 M32R_INSN_SRLI, "srli", "srli", 16,
1fa60b5d 933 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 934 },
935/* st $src1,@$src2 */
936 {
937 M32R_INSN_ST, "st", "st", 16,
1fa60b5d 938 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 939 },
940/* st $src1,@($slo16,$src2) */
941 {
942 M32R_INSN_ST_D, "st-d", "st", 32,
1fa60b5d 943 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 944 },
945/* stb $src1,@$src2 */
946 {
947 M32R_INSN_STB, "stb", "stb", 16,
1fa60b5d 948 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 949 },
950/* stb $src1,@($slo16,$src2) */
951 {
952 M32R_INSN_STB_D, "stb-d", "stb", 32,
1fa60b5d 953 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 954 },
955/* sth $src1,@$src2 */
956 {
957 M32R_INSN_STH, "sth", "sth", 16,
1fa60b5d 958 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 959 },
960/* sth $src1,@($slo16,$src2) */
961 {
962 M32R_INSN_STH_D, "sth-d", "sth", 32,
1fa60b5d 963 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 964 },
965/* st $src1,@+$src2 */
966 {
967 M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1fa60b5d 968 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 969 },
970/* st $src1,@-$src2 */
971 {
972 M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1fa60b5d 973 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 974 },
975/* sub $dr,$sr */
976 {
977 M32R_INSN_SUB, "sub", "sub", 16,
1fa60b5d 978 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 979 },
980/* subv $dr,$sr */
981 {
982 M32R_INSN_SUBV, "subv", "subv", 16,
1fa60b5d 983 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 984 },
985/* subx $dr,$sr */
986 {
987 M32R_INSN_SUBX, "subx", "subx", 16,
1fa60b5d 988 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 989 },
990/* trap $uimm4 */
991 {
992 M32R_INSN_TRAP, "trap", "trap", 16,
1fa60b5d 993 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 994 },
995/* unlock $src1,@$src2 */
996 {
997 M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1fa60b5d
DE		 998 { 0, { (1<<MACH_BASE), PIPE_O } }
999 },
1000/* satb $dr,$sr */
1001 {
1002 M32R_INSN_SATB, "satb", "satb", 32,
1003 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1004 },
1005/* sath $dr,$sr */
1006 {
1007 M32R_INSN_SATH, "sath", "sath", 32,
1008 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1009 },
1010/* sat $dr,$sr */
1011 {
1012 M32R_INSN_SAT, "sat", "sat", 32,
1013 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1014 },
1015/* pcmpbz $src2 */
1016 {
1017 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1018 { 0, { (1<<MACH_M32RX), PIPE_OS } }
1019 },
1020/* sadd */
1021 {
1022 M32R_INSN_SADD, "sadd", "sadd", 16,
1023 { 0, { (1<<MACH_M32RX), PIPE_S } }
1024 },
1025/* macwu1 $src1,$src2 */
1026 {
1027 M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1028 { 0, { (1<<MACH_M32RX), PIPE_S } }
1029 },
1030/* msblo $src1,$src2 */
1031 {
1032 M32R_INSN_MSBLO, "msblo", "msblo", 16,
1033 { 0, { (1<<MACH_M32RX), PIPE_S } }
1034 },
1035/* mulwu1 $src1,$src2 */
1036 {
1037 M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1038 { 0, { (1<<MACH_M32RX), PIPE_S } }
1039 },
1040/* maclh1 $src1,$src2 */
1041 {
1042 M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1043 { 0, { (1<<MACH_M32RX), PIPE_S } }
1044 },
1045/* sc */
1046 {
1047 M32R_INSN_SC, "sc", "sc", 16,
1048 { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1049 },
1050/* snc */
1051 {
1052 M32R_INSN_SNC, "snc", "snc", 16,
1053 { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
252b5132
RH		 1054 },
1055};
1056
1057#undef A
1058#undef MNEM
1059#undef OP
1060
1061/* Initialize anything needed to be done once, before any cpu_open call. */
1062
1063static void
1064init_tables ()
1065{
1066}
1067
1068/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */
1069
1070static const CGEN_MACH *
1071lookup_mach_via_bfd_name (table, name)
1072 const CGEN_MACH *table;
1073 const char *name;
1074{
1075 while (table->name)
1076 {
1077 if (strcmp (name, table->bfd_name) == 0)
1078 return table;
1079 ++table;
1080 }
1081 abort ();
1082}
1083
1084/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1085
1086static void
1087build_hw_table (cd)
1088 CGEN_CPU_TABLE *cd;
1089{
1090 int i;
1091 int machs = cd->machs;
1092 const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1093 /* MAX_HW is only an upper bound on the number of selected entries.
1094 However each entry is indexed by it's enum so there can be holes in
1095 the table. */
1096 const CGEN_HW_ENTRY **selected =
1097 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1098
1099 cd->hw_table.init_entries = init;
1100 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1101 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1102 /* ??? For now we just use machs to determine which ones we want. */
1103 for (i = 0; init[i].name != NULL; ++i)
1104 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1105 & machs)
1106 selected[init[i].type] = &init[i];
1107 cd->hw_table.entries = selected;
1108 cd->hw_table.num_entries = MAX_HW;
1109}
1110
1111/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1112
1113static void
1114build_ifield_table (cd)
1115 CGEN_CPU_TABLE *cd;
1116{
1117 cd->ifld_table = & m32r_cgen_ifld_table[0];
1118}
1119
1120/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1121
1122static void
1123build_operand_table (cd)
1124 CGEN_CPU_TABLE *cd;
1125{
1126 int i;
1127 int machs = cd->machs;
1128 const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1129 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1130 However each entry is indexed by it's enum so there can be holes in
1131 the table. */
1132 const CGEN_OPERAND **selected =
1133 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1134
1135 cd->operand_table.init_entries = init;
1136 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1137 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1138 /* ??? For now we just use mach to determine which ones we want. */
1139 for (i = 0; init[i].name != NULL; ++i)
1140 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1141 & machs)
1142 selected[init[i].type] = &init[i];
1143 cd->operand_table.entries = selected;
1144 cd->operand_table.num_entries = MAX_OPERANDS;
1145}
1146
1147/* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1148 ??? This could leave out insns not supported by the specified mach/isa,
1149 but that would cause errors like "foo only supported by bar" to become
1150 "unknown insn", so for now we include all insns and require the app to
1151 do the checking later.
1152 ??? On the other hand, parsing of such insns may require their hardware or
1153 operand elements to be in the table [which they mightn't be]. */
1154
1155static void
1156build_insn_table (cd)
1157 CGEN_CPU_TABLE *cd;
1158{
1159 int i;
1160 const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1161 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1162
1163 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1164 for (i = 0; i < MAX_INSNS; ++i)
1165 insns[i].base = &ib[i];
1166 cd->insn_table.init_entries = insns;
1167 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1168 cd->insn_table.num_init_entries = MAX_INSNS;
1169}
1170
1171/* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */
1172
1173static void
1174m32r_cgen_rebuild_tables (cd)
1175 CGEN_CPU_TABLE *cd;
1176{
1177 int i,n_isas,n_machs;
1178 unsigned int isas = cd->isas;
1179 unsigned int machs = cd->machs;
1180
1181 cd->int_insn_p = CGEN_INT_INSN_P;
1182
1183 /* Data derived from the isa spec. */
1184#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1185 cd->default_insn_bitsize = UNSET;
1186 cd->base_insn_bitsize = UNSET;
1187 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1188 cd->max_insn_bitsize = 0;
1189 for (i = 0; i < MAX_ISAS; ++i)
1190 if (((1 << i) & isas) != 0)
1191 {
1192 const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1193
1194 /* Default insn sizes of all selected isas must be equal or we set
1195 the result to 0, meaning "unknown". */
1196 if (cd->default_insn_bitsize == UNSET)
1197 cd->default_insn_bitsize = isa->default_insn_bitsize;
1198 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1199 ; /* this is ok */
1200 else
1201 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1202
1203 /* Base insn sizes of all selected isas must be equal or we set
1204 the result to 0, meaning "unknown". */
1205 if (cd->base_insn_bitsize == UNSET)
1206 cd->base_insn_bitsize = isa->base_insn_bitsize;
1207 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1208 ; /* this is ok */
1209 else
1210 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1211
1212 /* Set min,max insn sizes. */
1213 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1214 cd->min_insn_bitsize = isa->min_insn_bitsize;
1215 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1216 cd->max_insn_bitsize = isa->max_insn_bitsize;
1217
1218 ++n_isas;
1219 }
1220
1221 /* Data derived from the mach spec. */
1222 for (i = 0; i < MAX_MACHS; ++i)
1223 if (((1 << i) & machs) != 0)
1224 {
1225 const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1226
1227 ++n_machs;
1228 }
1229
1230 /* Determine which hw elements are used by MACH. */
1231 build_hw_table (cd);
1232
1233 /* Build the ifield table. */
1234 build_ifield_table (cd);
1235
1236 /* Determine which operands are used by MACH/ISA. */
1237 build_operand_table (cd);
1238
1239 /* Build the instruction table. */
1240 build_insn_table (cd);
1241}
1242
1243/* Initialize a cpu table and return a descriptor.
1244 It's much like opening a file, and must be the first function called.
1245 The arguments are a set of (type/value) pairs, terminated with
1246 CGEN_CPU_OPEN_END.
1247
1248 Currently supported values:
1249 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1250 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1251 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1252 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1253 CGEN_CPU_OPEN_END: terminates arguments
1254
1255 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1256 precluded.
1257
1258 ??? We only support ISO C stdargs here, not K&R.
1259 Laziness, plus experiment to see if anything requires K&R - eventually
1260 K&R will no longer be supported - e.g. GDB is currently trying this. */
1261
1262CGEN_CPU_DESC
1263m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1264{
1265 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1266 static int init_p;
1267 unsigned int isas = 0; /* 0 = "unspecified" */
1268 unsigned int machs = 0; /* 0 = "unspecified" */
1269 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1270 va_list ap;
1271
1272 if (! init_p)
1273 {
1274 init_tables ();
1275 init_p = 1;
1276 }
1277
1278 memset (cd, 0, sizeof (*cd));
1279
1280 va_start (ap, arg_type);
1281 while (arg_type != CGEN_CPU_OPEN_END)
1282 {
1283 switch (arg_type)
1284 {
1285 case CGEN_CPU_OPEN_ISAS :
1286 isas = va_arg (ap, unsigned int);
1287 break;
1288 case CGEN_CPU_OPEN_MACHS :
1289 machs = va_arg (ap, unsigned int);
1290 break;
1291 case CGEN_CPU_OPEN_BFDMACH :
1292 {
1293 const char *name = va_arg (ap, const char *);
1294 const CGEN_MACH *mach =
1295 lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1296
1297 machs |= mach->num << 1;
1298 break;
1299 }
1300 case CGEN_CPU_OPEN_ENDIAN :
1301 endian = va_arg (ap, enum cgen_endian);
1302 break;
1303 default :
1304 fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1305 arg_type);
1306 abort (); /* ??? return NULL? */
1307 }
1308 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1309 }
1310 va_end (ap);
1311
1312 /* mach unspecified means "all" */
1313 if (machs == 0)
1314 machs = (1 << MAX_MACHS) - 1;
1315 /* base mach is always selected */
1316 machs |= 1;
1317 /* isa unspecified means "all" */
1318 if (isas == 0)
1319 isas = (1 << MAX_ISAS) - 1;
1320 if (endian == CGEN_ENDIAN_UNKNOWN)
1321 {
1322 /* ??? If target has only one, could have a default. */
1323 fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1324 abort ();
1325 }
1326
1327 cd->isas = isas;
1328 cd->machs = machs;
1329 cd->endian = endian;
1330 /* FIXME: for the sparc case we can determine insn-endianness statically.
1331 The worry here is where both data and insn endian can be independently
1332 chosen, in which case this function will need another argument.
1333 Actually, will want to allow for more arguments in the future anyway. */
1334 cd->insn_endian = endian;
1335
1336 /* Table (re)builder. */
1337 cd->rebuild_tables = m32r_cgen_rebuild_tables;
1338 m32r_cgen_rebuild_tables (cd);
1339
1340 return (CGEN_CPU_DESC) cd;
1341}
1342
1343/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1344 MACH_NAME is the bfd name of the mach. */
1345
1346CGEN_CPU_DESC
1347m32r_cgen_cpu_open_1 (mach_name, endian)
1348 const char *mach_name;
1349 enum cgen_endian endian;
1350{
1351 return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1352 CGEN_CPU_OPEN_ENDIAN, endian,
1353 CGEN_CPU_OPEN_END);
1354}
1355
1356/* Close a cpu table.
1357 ??? This can live in a machine independent file, but there's currently
1358 no place to put this file (there's no libcgen). libopcodes is the wrong
1359 place as some simulator ports use this but they don't use libopcodes. */
1360
1361void
1362m32r_cgen_cpu_close (cd)
1363 CGEN_CPU_DESC cd;
1364{
1365 if (cd->insn_table.init_entries)
1366 free ((CGEN_INSN *) cd->insn_table.init_entries);
1367 if (cd->hw_table.entries)
1368 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1369 free (cd);
1370}
1371
GDB Binutils - Deliverables
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