projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Oops. Fix e-mail address.
[deliverable/binutils-gdb.git] / opcodes / m32r-desc.c
CommitLineData
252b5132
RH		 1/* CPU data for m32r.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include <ctype.h>
27#include <stdio.h>
28#include <stdarg.h>
29#include "ansidecl.h"
30#include "bfd.h"
31#include "symcat.h"
32#include "m32r-desc.h"
33#include "m32r-opc.h"
34#include "opintl.h"
35
36/* Attributes. */
37
38static const CGEN_ATTR_ENTRY bool_attr[] =
39{
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
43};
44
45static const CGEN_ATTR_ENTRY MACH_attr[] =
46{
47 { "base", MACH_BASE },
48 { "m32r", MACH_M32R },
1fa60b5d 49 { "m32rx", MACH_M32RX },
252b5132
RH		 50 { "max", MACH_MAX },
51 { 0, 0 }
52};
53
54static const CGEN_ATTR_ENTRY ISA_attr[] =
55{
56 { "m32r", ISA_M32R },
57 { "max", ISA_MAX },
58 { 0, 0 }
59};
60
1fa60b5d
DE		 61static const CGEN_ATTR_ENTRY PIPE_attr[] =
62{
63 { "NONE", PIPE_NONE },
64 { "O", PIPE_O },
65 { "S", PIPE_S },
66 { "OS", PIPE_OS },
67 { 0, 0 }
68};
69
252b5132
RH		 70const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
71{
72 { "MACH", & MACH_attr[0] },
73 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
74 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
75 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
76 { "RESERVED", &bool_attr[0], &bool_attr[0] },
77 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
78 { "SIGNED", &bool_attr[0], &bool_attr[0] },
79 { "RELOC", &bool_attr[0], &bool_attr[0] },
80 { 0, 0, 0 }
81};
82
83const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
84{
85 { "MACH", & MACH_attr[0] },
86 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "PC", &bool_attr[0], &bool_attr[0] },
89 { "PROFILE", &bool_attr[0], &bool_attr[0] },
90 { 0, 0, 0 }
91};
92
93const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
94{
95 { "MACH", & MACH_attr[0] },
96 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
97 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
98 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
99 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
100 { "SIGNED", &bool_attr[0], &bool_attr[0] },
101 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
102 { "RELAX", &bool_attr[0], &bool_attr[0] },
103 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
104 { "RELOC", &bool_attr[0], &bool_attr[0] },
105 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
106 { 0, 0, 0 }
107};
108
109const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
110{
111 { "MACH", & MACH_attr[0] },
1fa60b5d 112 { "PIPE", & PIPE_attr[0] },
252b5132
RH		 113 { "ALIAS", &bool_attr[0], &bool_attr[0] },
114 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
115 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
116 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
117 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
118 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
119 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
120 { "RELAX", &bool_attr[0], &bool_attr[0] },
121 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
122 { "PBB", &bool_attr[0], &bool_attr[0] },
123 { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
1fa60b5d 124 { "SPECIAL", &bool_attr[0], &bool_attr[0] },
252b5132
RH		 125 { 0, 0, 0 }
126};
127
128/* Instruction set variants. */
129
130static const CGEN_ISA m32r_cgen_isa_table[] = {
131 { "m32r", 32, 32, 16, 32, },
132 { 0 }
133};
134
135/* Machine variants. */
136
137static const CGEN_MACH m32r_cgen_mach_table[] = {
138 { "m32r", "m32r", MACH_M32R },
1fa60b5d 139 { "m32rx", "m32rx", MACH_M32RX },
252b5132
RH		 140 { 0 }
141};
142
143static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
144{
145 { "fp", 13 },
146 { "lr", 14 },
147 { "sp", 15 },
148 { "r0", 0 },
149 { "r1", 1 },
150 { "r2", 2 },
151 { "r3", 3 },
152 { "r4", 4 },
153 { "r5", 5 },
154 { "r6", 6 },
155 { "r7", 7 },
156 { "r8", 8 },
157 { "r9", 9 },
158 { "r10", 10 },
159 { "r11", 11 },
160 { "r12", 12 },
161 { "r13", 13 },
162 { "r14", 14 },
163 { "r15", 15 }
164};
165
166CGEN_KEYWORD m32r_cgen_opval_gr_names =
167{
168 & m32r_cgen_opval_gr_names_entries[0],
169 19
170};
171
172static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
173{
174 { "psw", 0 },
175 { "cbr", 1 },
176 { "spi", 2 },
177 { "spu", 3 },
178 { "bpc", 6 },
179 { "bbpsw", 8 },
180 { "bbpc", 14 },
181 { "cr0", 0 },
182 { "cr1", 1 },
183 { "cr2", 2 },
184 { "cr3", 3 },
185 { "cr4", 4 },
186 { "cr5", 5 },
187 { "cr6", 6 },
188 { "cr7", 7 },
189 { "cr8", 8 },
190 { "cr9", 9 },
191 { "cr10", 10 },
192 { "cr11", 11 },
193 { "cr12", 12 },
194 { "cr13", 13 },
195 { "cr14", 14 },
196 { "cr15", 15 }
197};
198
199CGEN_KEYWORD m32r_cgen_opval_cr_names =
200{
201 & m32r_cgen_opval_cr_names_entries[0],
202 23
203};
204
1fa60b5d
DE		 205static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
206{
207 { "a0", 0 },
208 { "a1", 1 }
209};
210
211CGEN_KEYWORD m32r_cgen_opval_h_accums =
212{
213 & m32r_cgen_opval_h_accums_entries[0],
214 2
215};
216
252b5132
RH		 217
218
219/* The hardware table. */
220
221#define A(a) (1 << CONCAT2 (CGEN_HW_,a))
222
223const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
224{
225 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
226 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
227 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
228 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
229 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
230 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
231 { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
232 { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
233 { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
234 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
235 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
236 { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1fa60b5d 237 { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
252b5132
RH		 238 { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
239 { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
240 { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
241 { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
242 { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
243 { 0 }
244};
245
246#undef A
247
248/* The instruction field table. */
249
250#define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
251
252const CGEN_IFLD m32r_cgen_ifld_table[] =
253{
254 { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
cfcdbe97 255 { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
252b5132
RH		 256 { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
257 { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
258 { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
259 { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
260 { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
261 { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
262 { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
263 { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
264 { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
265 { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
266 { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
267 { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
268 { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
269 { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
270 { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
271 { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
1fa60b5d
DE		 272 { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } },
273 { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } },
274 { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } },
275 { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
276 { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
277 { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
278 { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
279 { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
252b5132
RH		 280 { 0 }
281};
282
283#undef A
284
285/* The operand table. */
286
287#define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
288#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
289
290const CGEN_OPERAND m32r_cgen_operand_table[] =
291{
292/* pc: program counter */
293 { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
294 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
295/* sr: source register */
296 { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
297 { 0, { (1<<MACH_BASE) } } },
298/* dr: destination register */
299 { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
300 { 0, { (1<<MACH_BASE) } } },
301/* src1: source register 1 */
302 { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
303 { 0, { (1<<MACH_BASE) } } },
304/* src2: source register 2 */
305 { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
306 { 0, { (1<<MACH_BASE) } } },
307/* scr: source control register */
308 { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
309 { 0, { (1<<MACH_BASE) } } },
310/* dcr: destination control register */
311 { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
312 { 0, { (1<<MACH_BASE) } } },
313/* simm8: 8 bit signed immediate */
314 { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
315 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
316/* simm16: 16 bit signed immediate */
317 { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
318 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
319/* uimm4: 4 bit trap number */
320 { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
321 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
322/* uimm5: 5 bit shift count */
323 { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
324 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
325/* uimm16: 16 bit unsigned immediate */
326 { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
327 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
1fa60b5d
DE		 328/* imm1: 1 bit immediate */
329 { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
330 { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
331/* accd: accumulator destination register */
332 { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
333 { 0, { (1<<MACH_M32RX) } } },
334/* accs: accumulator source register */
335 { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
336 { 0, { (1<<MACH_M32RX) } } },
337/* acc: accumulator reg (d) */
338 { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
339 { 0, { (1<<MACH_M32RX) } } },
252b5132
RH		 340/* hash: # prefix */
341 { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
342 { 0, { (1<<MACH_BASE) } } },
343/* hi16: high 16 bit immediate, sign optional */
344 { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
345 { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
346/* slo16: 16 bit signed immediate, for low() */
347 { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
348 { 0, { (1<<MACH_BASE) } } },
349/* ulo16: 16 bit unsigned immediate, for low() */
350 { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
351 { 0, { (1<<MACH_BASE) } } },
352/* uimm24: 24 bit address */
353 { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
354 { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
355/* disp8: 8 bit displacement */
356 { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
357 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
358/* disp16: 16 bit displacement */
359 { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
360 { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
361/* disp24: 24 bit displacement */
362 { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
363 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
364/* condbit: condition bit */
365 { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
366 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
367/* accum: accumulator */
368 { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
369 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
370 { 0 }
371};
372
373#undef A
374
375#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
376#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
377
378/* The instruction table. */
379
380static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
381{
382 /* Special null first entry.
383 A `num' value of zero is thus invalid.
384 Also, the special `invalid' insn resides here. */
385 { 0, 0, 0 },
386/* add $dr,$sr */
387 {
388 M32R_INSN_ADD, "add", "add", 16,
1fa60b5d 389 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 390 },
391/* add3 $dr,$sr,$hash$slo16 */
392 {
393 M32R_INSN_ADD3, "add3", "add3", 32,
1fa60b5d 394 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 395 },
396/* and $dr,$sr */
397 {
398 M32R_INSN_AND, "and", "and", 16,
1fa60b5d 399 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 400 },
401/* and3 $dr,$sr,$uimm16 */
402 {
403 M32R_INSN_AND3, "and3", "and3", 32,
1fa60b5d 404 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 405 },
406/* or $dr,$sr */
407 {
408 M32R_INSN_OR, "or", "or", 16,
1fa60b5d 409 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 410 },
411/* or3 $dr,$sr,$hash$ulo16 */
412 {
413 M32R_INSN_OR3, "or3", "or3", 32,
1fa60b5d 414 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 415 },
416/* xor $dr,$sr */
417 {
418 M32R_INSN_XOR, "xor", "xor", 16,
1fa60b5d 419 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 420 },
421/* xor3 $dr,$sr,$uimm16 */
422 {
423 M32R_INSN_XOR3, "xor3", "xor3", 32,
1fa60b5d 424 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 425 },
426/* addi $dr,$simm8 */
427 {
428 M32R_INSN_ADDI, "addi", "addi", 16,
1fa60b5d 429 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 430 },
431/* addv $dr,$sr */
432 {
433 M32R_INSN_ADDV, "addv", "addv", 16,
1fa60b5d 434 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 435 },
436/* addv3 $dr,$sr,$simm16 */
437 {
438 M32R_INSN_ADDV3, "addv3", "addv3", 32,
1fa60b5d 439 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 440 },
441/* addx $dr,$sr */
442 {
443 M32R_INSN_ADDX, "addx", "addx", 16,
1fa60b5d 444 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 445 },
446/* bc.s $disp8 */
447 {
448 M32R_INSN_BC8, "bc8", "bc.s", 16,
1fa60b5d 449 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 450 },
451/* bc.l $disp24 */
452 {
453 M32R_INSN_BC24, "bc24", "bc.l", 32,
1fa60b5d 454 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 455 },
456/* beq $src1,$src2,$disp16 */
457 {
458 M32R_INSN_BEQ, "beq", "beq", 32,
1fa60b5d 459 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 460 },
461/* beqz $src2,$disp16 */
462 {
463 M32R_INSN_BEQZ, "beqz", "beqz", 32,
1fa60b5d 464 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 465 },
466/* bgez $src2,$disp16 */
467 {
468 M32R_INSN_BGEZ, "bgez", "bgez", 32,
1fa60b5d 469 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 470 },
471/* bgtz $src2,$disp16 */
472 {
473 M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
1fa60b5d 474 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 475 },
476/* blez $src2,$disp16 */
477 {
478 M32R_INSN_BLEZ, "blez", "blez", 32,
1fa60b5d 479 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 480 },
481/* bltz $src2,$disp16 */
482 {
483 M32R_INSN_BLTZ, "bltz", "bltz", 32,
1fa60b5d 484 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 485 },
486/* bnez $src2,$disp16 */
487 {
488 M32R_INSN_BNEZ, "bnez", "bnez", 32,
1fa60b5d 489 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 490 },
491/* bl.s $disp8 */
492 {
493 M32R_INSN_BL8, "bl8", "bl.s", 16,
1fa60b5d 494 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 495 },
496/* bl.l $disp24 */
497 {
498 M32R_INSN_BL24, "bl24", "bl.l", 32,
1fa60b5d
DE		 499 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
500 },
501/* bcl.s $disp8 */
502 {
503 M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
504 { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
505 },
506/* bcl.l $disp24 */
507 {
508 M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
509 { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
252b5132
RH		 510 },
511/* bnc.s $disp8 */
512 {
513 M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
1fa60b5d 514 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 515 },
516/* bnc.l $disp24 */
517 {
518 M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
1fa60b5d 519 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 520 },
521/* bne $src1,$src2,$disp16 */
522 {
523 M32R_INSN_BNE, "bne", "bne", 32,
1fa60b5d 524 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 525 },
526/* bra.s $disp8 */
527 {
528 M32R_INSN_BRA8, "bra8", "bra.s", 16,
1fa60b5d 529 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 530 },
531/* bra.l $disp24 */
532 {
533 M32R_INSN_BRA24, "bra24", "bra.l", 32,
1fa60b5d
DE		 534 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
535 },
536/* bncl.s $disp8 */
537 {
538 M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
539 { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
540 },
541/* bncl.l $disp24 */
542 {
543 M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
544 { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
252b5132
RH		 545 },
546/* cmp $src1,$src2 */
547 {
548 M32R_INSN_CMP, "cmp", "cmp", 16,
1fa60b5d 549 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 550 },
551/* cmpi $src2,$simm16 */
552 {
553 M32R_INSN_CMPI, "cmpi", "cmpi", 32,
1fa60b5d 554 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 555 },
556/* cmpu $src1,$src2 */
557 {
558 M32R_INSN_CMPU, "cmpu", "cmpu", 16,
1fa60b5d 559 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 560 },
561/* cmpui $src2,$simm16 */
562 {
563 M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
1fa60b5d
DE		 564 { 0, { (1<<MACH_BASE), PIPE_NONE } }
565 },
566/* cmpeq $src1,$src2 */
567 {
568 M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
569 { 0, { (1<<MACH_M32RX), PIPE_OS } }
570 },
571/* cmpz $src2 */
572 {
573 M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
574 { 0, { (1<<MACH_M32RX), PIPE_OS } }
252b5132
RH		 575 },
576/* div $dr,$sr */
577 {
578 M32R_INSN_DIV, "div", "div", 32,
1fa60b5d 579 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 580 },
581/* divu $dr,$sr */
582 {
583 M32R_INSN_DIVU, "divu", "divu", 32,
1fa60b5d 584 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 585 },
586/* rem $dr,$sr */
587 {
588 M32R_INSN_REM, "rem", "rem", 32,
1fa60b5d 589 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 590 },
591/* remu $dr,$sr */
592 {
593 M32R_INSN_REMU, "remu", "remu", 32,
1fa60b5d
DE		 594 { 0, { (1<<MACH_BASE), PIPE_NONE } }
595 },
596/* divh $dr,$sr */
597 {
598 M32R_INSN_DIVH, "divh", "divh", 32,
599 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
600 },
601/* jc $sr */
602 {
603 M32R_INSN_JC, "jc", "jc", 16,
604 { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
605 },
606/* jnc $sr */
607 {
608 M32R_INSN_JNC, "jnc", "jnc", 16,
609 { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
252b5132
RH		 610 },
611/* jl $sr */
612 {
613 M32R_INSN_JL, "jl", "jl", 16,
1fa60b5d 614 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 615 },
616/* jmp $sr */
617 {
618 M32R_INSN_JMP, "jmp", "jmp", 16,
1fa60b5d 619 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 620 },
621/* ld $dr,@$sr */
622 {
623 M32R_INSN_LD, "ld", "ld", 16,
1fa60b5d 624 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 625 },
626/* ld $dr,@($slo16,$sr) */
627 {
628 M32R_INSN_LD_D, "ld-d", "ld", 32,
1fa60b5d 629 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 630 },
631/* ldb $dr,@$sr */
632 {
633 M32R_INSN_LDB, "ldb", "ldb", 16,
1fa60b5d 634 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 635 },
636/* ldb $dr,@($slo16,$sr) */
637 {
638 M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
1fa60b5d 639 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 640 },
641/* ldh $dr,@$sr */
642 {
643 M32R_INSN_LDH, "ldh", "ldh", 16,
1fa60b5d 644 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 645 },
646/* ldh $dr,@($slo16,$sr) */
647 {
648 M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
1fa60b5d 649 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 650 },
651/* ldub $dr,@$sr */
652 {
653 M32R_INSN_LDUB, "ldub", "ldub", 16,
1fa60b5d 654 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 655 },
656/* ldub $dr,@($slo16,$sr) */
657 {
658 M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
1fa60b5d 659 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 660 },
661/* lduh $dr,@$sr */
662 {
663 M32R_INSN_LDUH, "lduh", "lduh", 16,
1fa60b5d 664 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 665 },
666/* lduh $dr,@($slo16,$sr) */
667 {
668 M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
1fa60b5d 669 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 670 },
671/* ld $dr,@$sr+ */
672 {
673 M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
1fa60b5d 674 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 675 },
676/* ld24 $dr,$uimm24 */
677 {
678 M32R_INSN_LD24, "ld24", "ld24", 32,
1fa60b5d 679 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 680 },
681/* ldi8 $dr,$simm8 */
682 {
683 M32R_INSN_LDI8, "ldi8", "ldi8", 16,
1fa60b5d 684 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 685 },
686/* ldi16 $dr,$hash$slo16 */
687 {
688 M32R_INSN_LDI16, "ldi16", "ldi16", 32,
1fa60b5d 689 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 690 },
691/* lock $dr,@$sr */
692 {
693 M32R_INSN_LOCK, "lock", "lock", 16,
1fa60b5d 694 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 695 },
696/* machi $src1,$src2 */
697 {
698 M32R_INSN_MACHI, "machi", "machi", 16,
1fa60b5d
DE		 699 { 0, { (1<<MACH_M32R), PIPE_S } }
700 },
701/* machi $src1,$src2,$acc */
702 {
703 M32R_INSN_MACHI_A, "machi-a", "machi", 16,
704 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 705 },
706/* maclo $src1,$src2 */
707 {
708 M32R_INSN_MACLO, "maclo", "maclo", 16,
1fa60b5d
DE		 709 { 0, { (1<<MACH_M32R), PIPE_S } }
710 },
711/* maclo $src1,$src2,$acc */
712 {
713 M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
714 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 715 },
716/* macwhi $src1,$src2 */
717 {
718 M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
1fa60b5d
DE		 719 { 0, { (1<<MACH_M32R), PIPE_S } }
720 },
721/* macwhi $src1,$src2,$acc */
722 {
723 M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
724 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 725 },
726/* macwlo $src1,$src2 */
727 {
728 M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
1fa60b5d
DE		 729 { 0, { (1<<MACH_M32R), PIPE_S } }
730 },
731/* macwlo $src1,$src2,$acc */
732 {
733 M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
734 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 735 },
736/* mul $dr,$sr */
737 {
738 M32R_INSN_MUL, "mul", "mul", 16,
1fa60b5d 739 { 0, { (1<<MACH_BASE), PIPE_S } }
252b5132
RH		 740 },
741/* mulhi $src1,$src2 */
742 {
743 M32R_INSN_MULHI, "mulhi", "mulhi", 16,
1fa60b5d
DE		 744 { 0, { (1<<MACH_M32R), PIPE_S } }
745 },
746/* mulhi $src1,$src2,$acc */
747 {
748 M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
749 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 750 },
751/* mullo $src1,$src2 */
752 {
753 M32R_INSN_MULLO, "mullo", "mullo", 16,
1fa60b5d
DE		 754 { 0, { (1<<MACH_M32R), PIPE_S } }
755 },
756/* mullo $src1,$src2,$acc */
757 {
758 M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
759 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 760 },
761/* mulwhi $src1,$src2 */
762 {
763 M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
1fa60b5d
DE		 764 { 0, { (1<<MACH_M32R), PIPE_S } }
765 },
766/* mulwhi $src1,$src2,$acc */
767 {
768 M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
769 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 770 },
771/* mulwlo $src1,$src2 */
772 {
773 M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
1fa60b5d
DE		 774 { 0, { (1<<MACH_M32R), PIPE_S } }
775 },
776/* mulwlo $src1,$src2,$acc */
777 {
778 M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
779 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 780 },
781/* mv $dr,$sr */
782 {
783 M32R_INSN_MV, "mv", "mv", 16,
1fa60b5d 784 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 785 },
786/* mvfachi $dr */
787 {
788 M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
1fa60b5d
DE		 789 { 0, { (1<<MACH_M32R), PIPE_S } }
790 },
791/* mvfachi $dr,$accs */
792 {
793 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
794 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 795 },
796/* mvfaclo $dr */
797 {
798 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
1fa60b5d
DE		 799 { 0, { (1<<MACH_M32R), PIPE_S } }
800 },
801/* mvfaclo $dr,$accs */
802 {
803 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
804 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 805 },
806/* mvfacmi $dr */
807 {
808 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
1fa60b5d
DE		 809 { 0, { (1<<MACH_M32R), PIPE_S } }
810 },
811/* mvfacmi $dr,$accs */
812 {
813 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
814 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 815 },
816/* mvfc $dr,$scr */
817 {
818 M32R_INSN_MVFC, "mvfc", "mvfc", 16,
1fa60b5d 819 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 820 },
821/* mvtachi $src1 */
822 {
823 M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
1fa60b5d
DE		 824 { 0, { (1<<MACH_M32R), PIPE_S } }
825 },
826/* mvtachi $src1,$accs */
827 {
828 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
829 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 830 },
831/* mvtaclo $src1 */
832 {
833 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
1fa60b5d
DE		 834 { 0, { (1<<MACH_M32R), PIPE_S } }
835 },
836/* mvtaclo $src1,$accs */
837 {
838 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
839 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 840 },
841/* mvtc $sr,$dcr */
842 {
843 M32R_INSN_MVTC, "mvtc", "mvtc", 16,
1fa60b5d 844 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 845 },
846/* neg $dr,$sr */
847 {
848 M32R_INSN_NEG, "neg", "neg", 16,
1fa60b5d 849 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 850 },
851/* nop */
852 {
853 M32R_INSN_NOP, "nop", "nop", 16,
1fa60b5d 854 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 855 },
856/* not $dr,$sr */
857 {
858 M32R_INSN_NOT, "not", "not", 16,
1fa60b5d 859 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 860 },
861/* rac */
862 {
863 M32R_INSN_RAC, "rac", "rac", 16,
1fa60b5d
DE		 864 { 0, { (1<<MACH_M32R), PIPE_S } }
865 },
866/* rac $accd,$accs,$imm1 */
867 {
868 M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
869 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 870 },
871/* rach */
872 {
873 M32R_INSN_RACH, "rach", "rach", 16,
1fa60b5d
DE		 874 { 0, { (1<<MACH_M32R), PIPE_S } }
875 },
876/* rach $accd,$accs,$imm1 */
877 {
878 M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
879 { 0, { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 880 },
881/* rte */
882 {
883 M32R_INSN_RTE, "rte", "rte", 16,
1fa60b5d 884 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 885 },
886/* seth $dr,$hash$hi16 */
887 {
888 M32R_INSN_SETH, "seth", "seth", 32,
1fa60b5d 889 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 890 },
891/* sll $dr,$sr */
892 {
893 M32R_INSN_SLL, "sll", "sll", 16,
1fa60b5d 894 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 895 },
896/* sll3 $dr,$sr,$simm16 */
897 {
898 M32R_INSN_SLL3, "sll3", "sll3", 32,
1fa60b5d 899 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 900 },
901/* slli $dr,$uimm5 */
902 {
903 M32R_INSN_SLLI, "slli", "slli", 16,
1fa60b5d 904 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 905 },
906/* sra $dr,$sr */
907 {
908 M32R_INSN_SRA, "sra", "sra", 16,
1fa60b5d 909 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 910 },
911/* sra3 $dr,$sr,$simm16 */
912 {
913 M32R_INSN_SRA3, "sra3", "sra3", 32,
1fa60b5d 914 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 915 },
916/* srai $dr,$uimm5 */
917 {
918 M32R_INSN_SRAI, "srai", "srai", 16,
1fa60b5d 919 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 920 },
921/* srl $dr,$sr */
922 {
923 M32R_INSN_SRL, "srl", "srl", 16,
1fa60b5d 924 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 925 },
926/* srl3 $dr,$sr,$simm16 */
927 {
928 M32R_INSN_SRL3, "srl3", "srl3", 32,
1fa60b5d 929 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 930 },
931/* srli $dr,$uimm5 */
932 {
933 M32R_INSN_SRLI, "srli", "srli", 16,
1fa60b5d 934 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 935 },
936/* st $src1,@$src2 */
937 {
938 M32R_INSN_ST, "st", "st", 16,
1fa60b5d 939 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 940 },
941/* st $src1,@($slo16,$src2) */
942 {
943 M32R_INSN_ST_D, "st-d", "st", 32,
1fa60b5d 944 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 945 },
946/* stb $src1,@$src2 */
947 {
948 M32R_INSN_STB, "stb", "stb", 16,
1fa60b5d 949 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 950 },
951/* stb $src1,@($slo16,$src2) */
952 {
953 M32R_INSN_STB_D, "stb-d", "stb", 32,
1fa60b5d 954 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 955 },
956/* sth $src1,@$src2 */
957 {
958 M32R_INSN_STH, "sth", "sth", 16,
1fa60b5d 959 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 960 },
961/* sth $src1,@($slo16,$src2) */
962 {
963 M32R_INSN_STH_D, "sth-d", "sth", 32,
1fa60b5d 964 { 0, { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 965 },
966/* st $src1,@+$src2 */
967 {
968 M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1fa60b5d 969 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 970 },
971/* st $src1,@-$src2 */
972 {
973 M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1fa60b5d 974 { 0, { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 975 },
976/* sub $dr,$sr */
977 {
978 M32R_INSN_SUB, "sub", "sub", 16,
1fa60b5d 979 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 980 },
981/* subv $dr,$sr */
982 {
983 M32R_INSN_SUBV, "subv", "subv", 16,
1fa60b5d 984 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 985 },
986/* subx $dr,$sr */
987 {
988 M32R_INSN_SUBX, "subx", "subx", 16,
1fa60b5d 989 { 0, { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 990 },
991/* trap $uimm4 */
992 {
993 M32R_INSN_TRAP, "trap", "trap", 16,
1fa60b5d 994 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 995 },
996/* unlock $src1,@$src2 */
997 {
998 M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1fa60b5d
DE		 999 { 0, { (1<<MACH_BASE), PIPE_O } }
1000 },
1001/* satb $dr,$sr */
1002 {
1003 M32R_INSN_SATB, "satb", "satb", 32,
1004 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1005 },
1006/* sath $dr,$sr */
1007 {
1008 M32R_INSN_SATH, "sath", "sath", 32,
1009 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1010 },
1011/* sat $dr,$sr */
1012 {
1013 M32R_INSN_SAT, "sat", "sat", 32,
1014 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1015 },
1016/* pcmpbz $src2 */
1017 {
1018 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
cfcdbe97 1019 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
1fa60b5d
DE		 1020 },
1021/* sadd */
1022 {
1023 M32R_INSN_SADD, "sadd", "sadd", 16,
1024 { 0, { (1<<MACH_M32RX), PIPE_S } }
1025 },
1026/* macwu1 $src1,$src2 */
1027 {
1028 M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1029 { 0, { (1<<MACH_M32RX), PIPE_S } }
1030 },
1031/* msblo $src1,$src2 */
1032 {
1033 M32R_INSN_MSBLO, "msblo", "msblo", 16,
1034 { 0, { (1<<MACH_M32RX), PIPE_S } }
1035 },
1036/* mulwu1 $src1,$src2 */
1037 {
1038 M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1039 { 0, { (1<<MACH_M32RX), PIPE_S } }
1040 },
1041/* maclh1 $src1,$src2 */
1042 {
1043 M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1044 { 0, { (1<<MACH_M32RX), PIPE_S } }
1045 },
1046/* sc */
1047 {
1048 M32R_INSN_SC, "sc", "sc", 16,
1049 { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1050 },
1051/* snc */
1052 {
1053 M32R_INSN_SNC, "snc", "snc", 16,
1054 { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
252b5132
RH		 1055 },
1056};
1057
1058#undef A
1059#undef MNEM
1060#undef OP
1061
1062/* Initialize anything needed to be done once, before any cpu_open call. */
1063
1064static void
1065init_tables ()
1066{
1067}
1068
1069/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */
1070
1071static const CGEN_MACH *
1072lookup_mach_via_bfd_name (table, name)
1073 const CGEN_MACH *table;
1074 const char *name;
1075{
1076 while (table->name)
1077 {
1078 if (strcmp (name, table->bfd_name) == 0)
1079 return table;
1080 ++table;
1081 }
1082 abort ();
1083}
1084
1085/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1086
1087static void
1088build_hw_table (cd)
1089 CGEN_CPU_TABLE *cd;
1090{
1091 int i;
1092 int machs = cd->machs;
1093 const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1094 /* MAX_HW is only an upper bound on the number of selected entries.
1095 However each entry is indexed by it's enum so there can be holes in
1096 the table. */
1097 const CGEN_HW_ENTRY **selected =
1098 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1099
1100 cd->hw_table.init_entries = init;
1101 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1102 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1103 /* ??? For now we just use machs to determine which ones we want. */
1104 for (i = 0; init[i].name != NULL; ++i)
1105 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1106 & machs)
1107 selected[init[i].type] = &init[i];
1108 cd->hw_table.entries = selected;
1109 cd->hw_table.num_entries = MAX_HW;
1110}
1111
1112/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1113
1114static void
1115build_ifield_table (cd)
1116 CGEN_CPU_TABLE *cd;
1117{
1118 cd->ifld_table = & m32r_cgen_ifld_table[0];
1119}
1120
1121/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1122
1123static void
1124build_operand_table (cd)
1125 CGEN_CPU_TABLE *cd;
1126{
1127 int i;
1128 int machs = cd->machs;
1129 const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1130 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1131 However each entry is indexed by it's enum so there can be holes in
1132 the table. */
1133 const CGEN_OPERAND **selected =
1134 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1135
1136 cd->operand_table.init_entries = init;
1137 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1138 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1139 /* ??? For now we just use mach to determine which ones we want. */
1140 for (i = 0; init[i].name != NULL; ++i)
1141 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1142 & machs)
1143 selected[init[i].type] = &init[i];
1144 cd->operand_table.entries = selected;
1145 cd->operand_table.num_entries = MAX_OPERANDS;
1146}
1147
1148/* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1149 ??? This could leave out insns not supported by the specified mach/isa,
1150 but that would cause errors like "foo only supported by bar" to become
1151 "unknown insn", so for now we include all insns and require the app to
1152 do the checking later.
1153 ??? On the other hand, parsing of such insns may require their hardware or
1154 operand elements to be in the table [which they mightn't be]. */
1155
1156static void
1157build_insn_table (cd)
1158 CGEN_CPU_TABLE *cd;
1159{
1160 int i;
1161 const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1162 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1163
1164 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1165 for (i = 0; i < MAX_INSNS; ++i)
1166 insns[i].base = &ib[i];
1167 cd->insn_table.init_entries = insns;
1168 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1169 cd->insn_table.num_init_entries = MAX_INSNS;
1170}
1171
1172/* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */
1173
1174static void
1175m32r_cgen_rebuild_tables (cd)
1176 CGEN_CPU_TABLE *cd;
1177{
1178 int i,n_isas,n_machs;
1179 unsigned int isas = cd->isas;
1180 unsigned int machs = cd->machs;
1181
1182 cd->int_insn_p = CGEN_INT_INSN_P;
1183
1184 /* Data derived from the isa spec. */
1185#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1186 cd->default_insn_bitsize = UNSET;
1187 cd->base_insn_bitsize = UNSET;
1188 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1189 cd->max_insn_bitsize = 0;
1190 for (i = 0; i < MAX_ISAS; ++i)
1191 if (((1 << i) & isas) != 0)
1192 {
1193 const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1194
1195 /* Default insn sizes of all selected isas must be equal or we set
1196 the result to 0, meaning "unknown". */
1197 if (cd->default_insn_bitsize == UNSET)
1198 cd->default_insn_bitsize = isa->default_insn_bitsize;
1199 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1200 ; /* this is ok */
1201 else
1202 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1203
1204 /* Base insn sizes of all selected isas must be equal or we set
1205 the result to 0, meaning "unknown". */
1206 if (cd->base_insn_bitsize == UNSET)
1207 cd->base_insn_bitsize = isa->base_insn_bitsize;
1208 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1209 ; /* this is ok */
1210 else
1211 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1212
1213 /* Set min,max insn sizes. */
1214 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1215 cd->min_insn_bitsize = isa->min_insn_bitsize;
1216 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1217 cd->max_insn_bitsize = isa->max_insn_bitsize;
1218
1219 ++n_isas;
1220 }
1221
1222 /* Data derived from the mach spec. */
1223 for (i = 0; i < MAX_MACHS; ++i)
1224 if (((1 << i) & machs) != 0)
1225 {
1226 const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1227
1228 ++n_machs;
1229 }
1230
1231 /* Determine which hw elements are used by MACH. */
1232 build_hw_table (cd);
1233
1234 /* Build the ifield table. */
1235 build_ifield_table (cd);
1236
1237 /* Determine which operands are used by MACH/ISA. */
1238 build_operand_table (cd);
1239
1240 /* Build the instruction table. */
1241 build_insn_table (cd);
1242}
1243
1244/* Initialize a cpu table and return a descriptor.
1245 It's much like opening a file, and must be the first function called.
1246 The arguments are a set of (type/value) pairs, terminated with
1247 CGEN_CPU_OPEN_END.
1248
1249 Currently supported values:
1250 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1251 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1252 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1253 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1254 CGEN_CPU_OPEN_END: terminates arguments
1255
1256 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1257 precluded.
1258
1259 ??? We only support ISO C stdargs here, not K&R.
1260 Laziness, plus experiment to see if anything requires K&R - eventually
1261 K&R will no longer be supported - e.g. GDB is currently trying this. */
1262
1263CGEN_CPU_DESC
1264m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1265{
1266 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1267 static int init_p;
1268 unsigned int isas = 0; /* 0 = "unspecified" */
1269 unsigned int machs = 0; /* 0 = "unspecified" */
1270 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1271 va_list ap;
1272
1273 if (! init_p)
1274 {
1275 init_tables ();
1276 init_p = 1;
1277 }
1278
1279 memset (cd, 0, sizeof (*cd));
1280
1281 va_start (ap, arg_type);
1282 while (arg_type != CGEN_CPU_OPEN_END)
1283 {
1284 switch (arg_type)
1285 {
1286 case CGEN_CPU_OPEN_ISAS :
1287 isas = va_arg (ap, unsigned int);
1288 break;
1289 case CGEN_CPU_OPEN_MACHS :
1290 machs = va_arg (ap, unsigned int);
1291 break;
1292 case CGEN_CPU_OPEN_BFDMACH :
1293 {
1294 const char *name = va_arg (ap, const char *);
1295 const CGEN_MACH *mach =
1296 lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1297
1298 machs |= mach->num << 1;
1299 break;
1300 }
1301 case CGEN_CPU_OPEN_ENDIAN :
1302 endian = va_arg (ap, enum cgen_endian);
1303 break;
1304 default :
1305 fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1306 arg_type);
1307 abort (); /* ??? return NULL? */
1308 }
1309 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1310 }
1311 va_end (ap);
1312
1313 /* mach unspecified means "all" */
1314 if (machs == 0)
1315 machs = (1 << MAX_MACHS) - 1;
1316 /* base mach is always selected */
1317 machs |= 1;
1318 /* isa unspecified means "all" */
1319 if (isas == 0)
1320 isas = (1 << MAX_ISAS) - 1;
1321 if (endian == CGEN_ENDIAN_UNKNOWN)
1322 {
1323 /* ??? If target has only one, could have a default. */
1324 fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1325 abort ();
1326 }
1327
1328 cd->isas = isas;
1329 cd->machs = machs;
1330 cd->endian = endian;
1331 /* FIXME: for the sparc case we can determine insn-endianness statically.
1332 The worry here is where both data and insn endian can be independently
1333 chosen, in which case this function will need another argument.
1334 Actually, will want to allow for more arguments in the future anyway. */
1335 cd->insn_endian = endian;
1336
1337 /* Table (re)builder. */
1338 cd->rebuild_tables = m32r_cgen_rebuild_tables;
1339 m32r_cgen_rebuild_tables (cd);
1340
cfcdbe97
AH		 1341 /* Initialise flags. */
1342 cd->flags = 0;
1343
252b5132
RH		 1344 return (CGEN_CPU_DESC) cd;
1345}
1346
1347/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1348 MACH_NAME is the bfd name of the mach. */
1349
1350CGEN_CPU_DESC
1351m32r_cgen_cpu_open_1 (mach_name, endian)
1352 const char *mach_name;
1353 enum cgen_endian endian;
1354{
1355 return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1356 CGEN_CPU_OPEN_ENDIAN, endian,
1357 CGEN_CPU_OPEN_END);
1358}
1359
1360/* Close a cpu table.
1361 ??? This can live in a machine independent file, but there's currently
1362 no place to put this file (there's no libcgen). libopcodes is the wrong
1363 place as some simulator ports use this but they don't use libopcodes. */
1364
1365void
1366m32r_cgen_cpu_close (cd)
1367 CGEN_CPU_DESC cd;
1368{
1369 if (cd->insn_table.init_entries)
1370 free ((CGEN_INSN *) cd->insn_table.init_entries);
1371 if (cd->hw_table.entries)
1372 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1373 free (cd);
1374}
1375
GDB Binutils - Deliverables
This page took 0.144308 seconds and 4 git commands to generate.