Commit | Line | Data |
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252b5132 RH |
1 | /* Disassembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | - the resultant file is machine generated, cgen-dis.in isn't | |
6 | ||
060d22b0 | 7 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
252b5132 RH |
8 | |
9 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software Foundation, Inc., | |
23 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
26 | Keep that in mind. */ | |
27 | ||
28 | #include "sysdep.h" | |
29 | #include <stdio.h> | |
30 | #include "ansidecl.h" | |
31 | #include "dis-asm.h" | |
32 | #include "bfd.h" | |
33 | #include "symcat.h" | |
34 | #include "m32r-desc.h" | |
35 | #include "m32r-opc.h" | |
36 | #include "opintl.h" | |
37 | ||
38 | /* Default text to print if an instruction isn't recognized. */ | |
39 | #define UNKNOWN_INSN_MSG _("*unknown*") | |
40 | ||
41 | static void print_normal | |
42 | PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); | |
43 | static void print_address | |
44 | PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); | |
45 | static void print_keyword | |
46 | PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); | |
47 | static void print_insn_normal | |
48 | PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, | |
49 | bfd_vma, int)); | |
fc05c67f | 50 | static int print_insn |
0e2ee3ca NC |
51 | PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); |
52 | static int default_print_insn | |
252b5132 | 53 | PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); |
fc05c67f NC |
54 | static int read_insn |
55 | PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, | |
56 | CGEN_EXTRACT_INFO *, unsigned long *)); | |
252b5132 RH |
57 | \f |
58 | /* -- disassembler routines inserted here */ | |
59 | ||
60 | /* -- dis.c */ | |
0e2ee3ca NC |
61 | static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); |
62 | static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); | |
252b5132 RH |
63 | |
64 | /* Immediate values are prefixed with '#'. */ | |
65 | ||
0e2ee3ca NC |
66 | #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ |
67 | do \ | |
68 | { \ | |
69 | if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \ | |
70 | (*info->fprintf_func) (info->stream, "#"); \ | |
71 | } \ | |
72 | while (0) | |
252b5132 RH |
73 | |
74 | /* Handle '#' prefixes as operands. */ | |
75 | ||
76 | static void | |
77 | print_hash (cd, dis_info, value, attrs, pc, length) | |
9a2e995d | 78 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
252b5132 | 79 | PTR dis_info; |
9a2e995d GH |
80 | long value ATTRIBUTE_UNUSED; |
81 | unsigned int attrs ATTRIBUTE_UNUSED; | |
82 | bfd_vma pc ATTRIBUTE_UNUSED; | |
83 | int length ATTRIBUTE_UNUSED; | |
252b5132 RH |
84 | { |
85 | disassemble_info *info = (disassemble_info *) dis_info; | |
86 | (*info->fprintf_func) (info->stream, "#"); | |
87 | } | |
88 | ||
0e2ee3ca | 89 | #undef CGEN_PRINT_INSN |
252b5132 RH |
90 | #define CGEN_PRINT_INSN my_print_insn |
91 | ||
92 | static int | |
93 | my_print_insn (cd, pc, info) | |
94 | CGEN_CPU_DESC cd; | |
95 | bfd_vma pc; | |
96 | disassemble_info *info; | |
97 | { | |
98 | char buffer[CGEN_MAX_INSN_SIZE]; | |
99 | char *buf = buffer; | |
100 | int status; | |
101 | int buflen = (pc & 3) == 0 ? 4 : 2; | |
102 | ||
103 | /* Read the base part of the insn. */ | |
104 | ||
105 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
106 | if (status != 0) | |
107 | { | |
108 | (*info->memory_error_func) (status, pc, info); | |
109 | return -1; | |
110 | } | |
111 | ||
112 | /* 32 bit insn? */ | |
113 | if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) | |
114 | return print_insn (cd, pc, info, buf, buflen); | |
115 | ||
116 | /* Print the first insn. */ | |
117 | if ((pc & 3) == 0) | |
118 | { | |
119 | if (print_insn (cd, pc, info, buf, 2) == 0) | |
120 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
121 | buf += 2; | |
122 | } | |
123 | ||
124 | if (buf[0] & 0x80) | |
125 | { | |
126 | /* Parallel. */ | |
127 | (*info->fprintf_func) (info->stream, " || "); | |
128 | buf[0] &= 0x7f; | |
129 | } | |
130 | else | |
131 | (*info->fprintf_func) (info->stream, " -> "); | |
132 | ||
133 | /* The "& 3" is to pass a consistent address. | |
134 | Parallel insns arguably both begin on the word boundary. | |
135 | Also, branch insns are calculated relative to the word boundary. */ | |
136 | if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0) | |
137 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
138 | ||
139 | return (pc & 3) ? 2 : 4; | |
140 | } | |
141 | ||
142 | /* -- */ | |
143 | ||
0e2ee3ca NC |
144 | void m32r_cgen_print_operand |
145 | PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, | |
146 | void const *, bfd_vma, int)); | |
147 | ||
252b5132 RH |
148 | /* Main entry point for printing operands. |
149 | XINFO is a `void *' and not a `disassemble_info *' to not put a requirement | |
150 | of dis-asm.h on cgen.h. | |
151 | ||
152 | This function is basically just a big switch statement. Earlier versions | |
153 | used tables to look up the function to use, but | |
154 | - if the table contains both assembler and disassembler functions then | |
155 | the disassembler contains much of the assembler and vice-versa, | |
156 | - there's a lot of inlining possibilities as things grow, | |
157 | - using a switch statement avoids the function call overhead. | |
158 | ||
159 | This function could be moved into `print_insn_normal', but keeping it | |
160 | separate makes clear the interface between `print_insn_normal' and each of | |
9a2e995d | 161 | the handlers. */ |
252b5132 RH |
162 | |
163 | void | |
164 | m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) | |
165 | CGEN_CPU_DESC cd; | |
166 | int opindex; | |
167 | PTR xinfo; | |
168 | CGEN_FIELDS *fields; | |
fc05c67f | 169 | void const *attrs ATTRIBUTE_UNUSED; |
252b5132 RH |
170 | bfd_vma pc; |
171 | int length; | |
172 | { | |
173 | disassemble_info *info = (disassemble_info *) xinfo; | |
174 | ||
175 | switch (opindex) | |
176 | { | |
1fa60b5d DE |
177 | case M32R_OPERAND_ACC : |
178 | print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0); | |
179 | break; | |
180 | case M32R_OPERAND_ACCD : | |
181 | print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0); | |
182 | break; | |
183 | case M32R_OPERAND_ACCS : | |
184 | print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0); | |
185 | break; | |
252b5132 RH |
186 | case M32R_OPERAND_DCR : |
187 | print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0); | |
188 | break; | |
189 | case M32R_OPERAND_DISP16 : | |
190 | print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
191 | break; | |
192 | case M32R_OPERAND_DISP24 : | |
193 | print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
194 | break; | |
195 | case M32R_OPERAND_DISP8 : | |
196 | print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
197 | break; | |
198 | case M32R_OPERAND_DR : | |
199 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); | |
200 | break; | |
201 | case M32R_OPERAND_HASH : | |
eb1b03df | 202 | print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
252b5132 RH |
203 | break; |
204 | case M32R_OPERAND_HI16 : | |
205 | print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); | |
206 | break; | |
1fa60b5d DE |
207 | case M32R_OPERAND_IMM1 : |
208 | print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
209 | break; | |
252b5132 RH |
210 | case M32R_OPERAND_SCR : |
211 | print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0); | |
212 | break; | |
213 | case M32R_OPERAND_SIMM16 : | |
214 | print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
215 | break; | |
216 | case M32R_OPERAND_SIMM8 : | |
217 | print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
218 | break; | |
219 | case M32R_OPERAND_SLO16 : | |
220 | print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); | |
221 | break; | |
222 | case M32R_OPERAND_SR : | |
223 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); | |
224 | break; | |
225 | case M32R_OPERAND_SRC1 : | |
226 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); | |
227 | break; | |
228 | case M32R_OPERAND_SRC2 : | |
229 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); | |
230 | break; | |
231 | case M32R_OPERAND_UIMM16 : | |
232 | print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
233 | break; | |
234 | case M32R_OPERAND_UIMM24 : | |
235 | print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); | |
236 | break; | |
237 | case M32R_OPERAND_UIMM4 : | |
238 | print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
239 | break; | |
240 | case M32R_OPERAND_UIMM5 : | |
241 | print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
242 | break; | |
243 | case M32R_OPERAND_ULO16 : | |
244 | print_normal (cd, info, fields->f_uimm16, 0, pc, length); | |
245 | break; | |
246 | ||
247 | default : | |
248 | /* xgettext:c-format */ | |
249 | fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), | |
250 | opindex); | |
251 | abort (); | |
252 | } | |
253 | } | |
254 | ||
255 | cgen_print_fn * const m32r_cgen_print_handlers[] = | |
256 | { | |
257 | print_insn_normal, | |
258 | }; | |
259 | ||
260 | ||
261 | void | |
262 | m32r_cgen_init_dis (cd) | |
263 | CGEN_CPU_DESC cd; | |
264 | { | |
265 | m32r_cgen_init_opcode_table (cd); | |
266 | m32r_cgen_init_ibld_table (cd); | |
267 | cd->print_handlers = & m32r_cgen_print_handlers[0]; | |
268 | cd->print_operand = m32r_cgen_print_operand; | |
269 | } | |
270 | ||
271 | \f | |
272 | /* Default print handler. */ | |
273 | ||
274 | static void | |
275 | print_normal (cd, dis_info, value, attrs, pc, length) | |
6bb95a0f | 276 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
252b5132 RH |
277 | PTR dis_info; |
278 | long value; | |
279 | unsigned int attrs; | |
fc05c67f NC |
280 | bfd_vma pc ATTRIBUTE_UNUSED; |
281 | int length ATTRIBUTE_UNUSED; | |
252b5132 RH |
282 | { |
283 | disassemble_info *info = (disassemble_info *) dis_info; | |
284 | ||
285 | #ifdef CGEN_PRINT_NORMAL | |
286 | CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); | |
287 | #endif | |
288 | ||
289 | /* Print the operand as directed by the attributes. */ | |
290 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
291 | ; /* nothing to do */ | |
292 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
293 | (*info->fprintf_func) (info->stream, "%ld", value); | |
294 | else | |
295 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
296 | } | |
297 | ||
298 | /* Default address handler. */ | |
299 | ||
300 | static void | |
301 | print_address (cd, dis_info, value, attrs, pc, length) | |
6bb95a0f | 302 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
252b5132 RH |
303 | PTR dis_info; |
304 | bfd_vma value; | |
305 | unsigned int attrs; | |
6bb95a0f DB |
306 | bfd_vma pc ATTRIBUTE_UNUSED; |
307 | int length ATTRIBUTE_UNUSED; | |
252b5132 RH |
308 | { |
309 | disassemble_info *info = (disassemble_info *) dis_info; | |
310 | ||
311 | #ifdef CGEN_PRINT_ADDRESS | |
312 | CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); | |
313 | #endif | |
314 | ||
315 | /* Print the operand as directed by the attributes. */ | |
316 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
317 | ; /* nothing to do */ | |
318 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) | |
319 | (*info->print_address_func) (value, info); | |
320 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) | |
321 | (*info->print_address_func) (value, info); | |
322 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
323 | (*info->fprintf_func) (info->stream, "%ld", (long) value); | |
324 | else | |
325 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value); | |
326 | } | |
327 | ||
328 | /* Keyword print handler. */ | |
329 | ||
330 | static void | |
331 | print_keyword (cd, dis_info, keyword_table, value, attrs) | |
6bb95a0f | 332 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
252b5132 RH |
333 | PTR dis_info; |
334 | CGEN_KEYWORD *keyword_table; | |
335 | long value; | |
6bb95a0f | 336 | unsigned int attrs ATTRIBUTE_UNUSED; |
252b5132 RH |
337 | { |
338 | disassemble_info *info = (disassemble_info *) dis_info; | |
339 | const CGEN_KEYWORD_ENTRY *ke; | |
340 | ||
341 | ke = cgen_keyword_lookup_value (keyword_table, value); | |
342 | if (ke != NULL) | |
343 | (*info->fprintf_func) (info->stream, "%s", ke->name); | |
344 | else | |
345 | (*info->fprintf_func) (info->stream, "???"); | |
346 | } | |
347 | \f | |
348 | /* Default insn printer. | |
349 | ||
350 | DIS_INFO is defined as `PTR' so the disassembler needn't know anything | |
351 | about disassemble_info. */ | |
352 | ||
353 | static void | |
354 | print_insn_normal (cd, dis_info, insn, fields, pc, length) | |
355 | CGEN_CPU_DESC cd; | |
356 | PTR dis_info; | |
357 | const CGEN_INSN *insn; | |
358 | CGEN_FIELDS *fields; | |
359 | bfd_vma pc; | |
360 | int length; | |
361 | { | |
362 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
363 | disassemble_info *info = (disassemble_info *) dis_info; | |
b3466c39 | 364 | const CGEN_SYNTAX_CHAR_TYPE *syn; |
252b5132 RH |
365 | |
366 | CGEN_INIT_PRINT (cd); | |
367 | ||
368 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
369 | { | |
370 | if (CGEN_SYNTAX_MNEMONIC_P (*syn)) | |
371 | { | |
372 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); | |
373 | continue; | |
374 | } | |
375 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
376 | { | |
377 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); | |
378 | continue; | |
379 | } | |
380 | ||
381 | /* We have an operand. */ | |
382 | m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, | |
383 | fields, CGEN_INSN_ATTRS (insn), pc, length); | |
384 | } | |
385 | } | |
386 | \f | |
6bb95a0f DB |
387 | /* Subroutine of print_insn. Reads an insn into the given buffers and updates |
388 | the extract info. | |
389 | Returns 0 if all is well, non-zero otherwise. */ | |
0e2ee3ca | 390 | |
252b5132 | 391 | static int |
6bb95a0f | 392 | read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) |
fc05c67f | 393 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
252b5132 RH |
394 | bfd_vma pc; |
395 | disassemble_info *info; | |
396 | char *buf; | |
397 | int buflen; | |
6bb95a0f DB |
398 | CGEN_EXTRACT_INFO *ex_info; |
399 | unsigned long *insn_value; | |
252b5132 | 400 | { |
6bb95a0f DB |
401 | int status = (*info->read_memory_func) (pc, buf, buflen, info); |
402 | if (status != 0) | |
403 | { | |
404 | (*info->memory_error_func) (status, pc, info); | |
405 | return -1; | |
406 | } | |
252b5132 | 407 | |
6bb95a0f DB |
408 | ex_info->dis_info = info; |
409 | ex_info->valid = (1 << buflen) - 1; | |
410 | ex_info->insn_bytes = buf; | |
252b5132 | 411 | |
b3466c39 | 412 | *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); |
6bb95a0f DB |
413 | return 0; |
414 | } | |
415 | ||
416 | /* Utility to print an insn. | |
417 | BUF is the base part of the insn, target byte order, BUFLEN bytes long. | |
418 | The result is the size of the insn in bytes or zero for an unknown insn | |
419 | or -1 if an error occurs fetching data (memory_error_func will have | |
420 | been called). */ | |
421 | ||
422 | static int | |
423 | print_insn (cd, pc, info, buf, buflen) | |
424 | CGEN_CPU_DESC cd; | |
425 | bfd_vma pc; | |
426 | disassemble_info *info; | |
427 | char *buf; | |
0e2ee3ca | 428 | unsigned int buflen; |
6bb95a0f | 429 | { |
fc7bc883 | 430 | CGEN_INSN_INT insn_value; |
6bb95a0f DB |
431 | const CGEN_INSN_LIST *insn_list; |
432 | CGEN_EXTRACT_INFO ex_info; | |
2e1ef6b4 | 433 | int basesize; |
b3466c39 | 434 | |
52646233 | 435 | /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ |
2e1ef6b4 DB |
436 | basesize = cd->base_insn_bitsize < buflen * 8 ? |
437 | cd->base_insn_bitsize : buflen * 8; | |
438 | insn_value = cgen_get_insn_value (cd, buf, basesize); | |
439 | ||
52646233 FCE |
440 | |
441 | /* Fill in ex_info fields like read_insn would. Don't actually call | |
442 | read_insn, since the incoming buffer is already read (and possibly | |
443 | modified a la m32r). */ | |
444 | ex_info.valid = (1 << buflen) - 1; | |
445 | ex_info.dis_info = info; | |
446 | ex_info.insn_bytes = buf; | |
6bb95a0f | 447 | |
252b5132 RH |
448 | /* The instructions are stored in hash lists. |
449 | Pick the first one and keep trying until we find the right one. */ | |
450 | ||
451 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); | |
452 | while (insn_list != NULL) | |
453 | { | |
454 | const CGEN_INSN *insn = insn_list->insn; | |
455 | CGEN_FIELDS fields; | |
456 | int length; | |
52646233 | 457 | unsigned long insn_value_cropped; |
252b5132 | 458 | |
cfcdbe97 | 459 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED |
0e2ee3ca | 460 | /* Not needed as insn shouldn't be in hash lists if not supported. */ |
252b5132 RH |
461 | /* Supported by this cpu? */ |
462 | if (! m32r_cgen_insn_supported (cd, insn)) | |
cfcdbe97 AH |
463 | { |
464 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
465 | continue; | |
466 | } | |
252b5132 RH |
467 | #endif |
468 | ||
469 | /* Basic bit mask must be correct. */ | |
470 | /* ??? May wish to allow target to defer this check until the extract | |
471 | handler. */ | |
52646233 FCE |
472 | |
473 | /* Base size may exceed this instruction's size. Extract the | |
474 | relevant part from the buffer. */ | |
0e2ee3ca NC |
475 | if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && |
476 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
52646233 FCE |
477 | insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), |
478 | info->endian == BFD_ENDIAN_BIG); | |
479 | else | |
480 | insn_value_cropped = insn_value; | |
481 | ||
482 | if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) | |
252b5132 RH |
483 | == CGEN_INSN_BASE_VALUE (insn)) |
484 | { | |
485 | /* Printing is handled in two passes. The first pass parses the | |
486 | machine insn and extracts the fields. The second pass prints | |
487 | them. */ | |
488 | ||
54faae25 NC |
489 | /* Make sure the entire insn is loaded into insn_value, if it |
490 | can fit. */ | |
0e2ee3ca NC |
491 | if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && |
492 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
6bb95a0f DB |
493 | { |
494 | unsigned long full_insn_value; | |
495 | int rc = read_insn (cd, pc, info, buf, | |
496 | CGEN_INSN_BITSIZE (insn) / 8, | |
497 | & ex_info, & full_insn_value); | |
498 | if (rc != 0) | |
499 | return rc; | |
500 | length = CGEN_EXTRACT_FN (cd, insn) | |
501 | (cd, insn, &ex_info, full_insn_value, &fields, pc); | |
502 | } | |
503 | else | |
54faae25 | 504 | length = CGEN_EXTRACT_FN (cd, insn) |
fc7bc883 | 505 | (cd, insn, &ex_info, insn_value_cropped, &fields, pc); |
b3466c39 | 506 | |
252b5132 RH |
507 | /* length < 0 -> error */ |
508 | if (length < 0) | |
509 | return length; | |
510 | if (length > 0) | |
511 | { | |
512 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); | |
513 | /* length is in bits, result is in bytes */ | |
514 | return length / 8; | |
515 | } | |
516 | } | |
517 | ||
518 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
519 | } | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | /* Default value for CGEN_PRINT_INSN. | |
525 | The result is the size of the insn in bytes or zero for an unknown insn | |
526 | or -1 if an error occured fetching bytes. */ | |
527 | ||
528 | #ifndef CGEN_PRINT_INSN | |
529 | #define CGEN_PRINT_INSN default_print_insn | |
0e2ee3ca | 530 | #endif |
252b5132 RH |
531 | |
532 | static int | |
533 | default_print_insn (cd, pc, info) | |
534 | CGEN_CPU_DESC cd; | |
535 | bfd_vma pc; | |
536 | disassemble_info *info; | |
537 | { | |
538 | char buf[CGEN_MAX_INSN_SIZE]; | |
fc7bc883 | 539 | int buflen; |
252b5132 RH |
540 | int status; |
541 | ||
fc7bc883 RH |
542 | /* Attempt to read the base part of the insn. */ |
543 | buflen = cd->base_insn_bitsize / 8; | |
544 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
545 | ||
546 | /* Try again with the minimum part, if min < base. */ | |
547 | if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) | |
548 | { | |
549 | buflen = cd->min_insn_bitsize / 8; | |
550 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
551 | } | |
252b5132 | 552 | |
252b5132 RH |
553 | if (status != 0) |
554 | { | |
555 | (*info->memory_error_func) (status, pc, info); | |
556 | return -1; | |
557 | } | |
558 | ||
fc7bc883 | 559 | return print_insn (cd, pc, info, buf, buflen); |
252b5132 RH |
560 | } |
561 | ||
562 | /* Main entry point. | |
563 | Print one instruction from PC on INFO->STREAM. | |
564 | Return the size of the instruction (in bytes). */ | |
565 | ||
566 | int | |
567 | print_insn_m32r (pc, info) | |
568 | bfd_vma pc; | |
569 | disassemble_info *info; | |
570 | { | |
571 | static CGEN_CPU_DESC cd = 0; | |
6bb95a0f DB |
572 | static int prev_isa; |
573 | static int prev_mach; | |
574 | static int prev_endian; | |
252b5132 RH |
575 | int length; |
576 | int isa,mach; | |
577 | int endian = (info->endian == BFD_ENDIAN_BIG | |
578 | ? CGEN_ENDIAN_BIG | |
579 | : CGEN_ENDIAN_LITTLE); | |
580 | enum bfd_architecture arch; | |
581 | ||
582 | /* ??? gdb will set mach but leave the architecture as "unknown" */ | |
583 | #ifndef CGEN_BFD_ARCH | |
584 | #define CGEN_BFD_ARCH bfd_arch_m32r | |
585 | #endif | |
586 | arch = info->arch; | |
587 | if (arch == bfd_arch_unknown) | |
588 | arch = CGEN_BFD_ARCH; | |
27fca2d8 PM |
589 | |
590 | /* There's no standard way to compute the machine or isa number | |
252b5132 | 591 | so we leave it to the target. */ |
27fca2d8 PM |
592 | #ifdef CGEN_COMPUTE_MACH |
593 | mach = CGEN_COMPUTE_MACH (info); | |
594 | #else | |
595 | mach = info->mach; | |
596 | #endif | |
597 | ||
252b5132 RH |
598 | #ifdef CGEN_COMPUTE_ISA |
599 | isa = CGEN_COMPUTE_ISA (info); | |
600 | #else | |
601 | isa = 0; | |
602 | #endif | |
603 | ||
252b5132 RH |
604 | /* If we've switched cpu's, close the current table and open a new one. */ |
605 | if (cd | |
606 | && (isa != prev_isa | |
607 | || mach != prev_mach | |
608 | || endian != prev_endian)) | |
609 | { | |
610 | m32r_cgen_cpu_close (cd); | |
611 | cd = 0; | |
612 | } | |
613 | ||
614 | /* If we haven't initialized yet, initialize the opcode table. */ | |
615 | if (! cd) | |
616 | { | |
617 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); | |
618 | const char *mach_name; | |
619 | ||
620 | if (!arch_type) | |
621 | abort (); | |
622 | mach_name = arch_type->printable_name; | |
623 | ||
624 | prev_isa = isa; | |
625 | prev_mach = mach; | |
626 | prev_endian = endian; | |
627 | cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, | |
628 | CGEN_CPU_OPEN_BFDMACH, mach_name, | |
629 | CGEN_CPU_OPEN_ENDIAN, prev_endian, | |
630 | CGEN_CPU_OPEN_END); | |
631 | if (!cd) | |
632 | abort (); | |
633 | m32r_cgen_init_dis (cd); | |
634 | } | |
635 | ||
636 | /* We try to have as much common code as possible. | |
637 | But at this point some targets need to take over. */ | |
638 | /* ??? Some targets may need a hook elsewhere. Try to avoid this, | |
639 | but if not possible try to move this hook elsewhere rather than | |
640 | have two hooks. */ | |
641 | length = CGEN_PRINT_INSN (cd, pc, info); | |
642 | if (length > 0) | |
643 | return length; | |
644 | if (length < 0) | |
645 | return -1; | |
646 | ||
647 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
648 | return cd->default_insn_bitsize / 8; | |
649 | } |