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252b5132 RH |
1 | /* Disassembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | - the resultant file is machine generated, cgen-dis.in isn't | |
6 | ||
060d22b0 | 7 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
252b5132 RH |
8 | |
9 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software Foundation, Inc., | |
23 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
26 | Keep that in mind. */ | |
27 | ||
28 | #include "sysdep.h" | |
29 | #include <stdio.h> | |
30 | #include "ansidecl.h" | |
31 | #include "dis-asm.h" | |
32 | #include "bfd.h" | |
33 | #include "symcat.h" | |
34 | #include "m32r-desc.h" | |
35 | #include "m32r-opc.h" | |
36 | #include "opintl.h" | |
37 | ||
38 | /* Default text to print if an instruction isn't recognized. */ | |
39 | #define UNKNOWN_INSN_MSG _("*unknown*") | |
40 | ||
41 | static void print_normal | |
42 | PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); | |
43 | static void print_address | |
44 | PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); | |
45 | static void print_keyword | |
46 | PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); | |
47 | static void print_insn_normal | |
48 | PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, | |
49 | bfd_vma, int)); | |
50 | static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, | |
51 | disassemble_info *, char *, int)); | |
52 | static int default_print_insn | |
53 | PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); | |
54 | \f | |
55 | /* -- disassembler routines inserted here */ | |
56 | ||
57 | /* -- dis.c */ | |
58 | ||
59 | /* Immediate values are prefixed with '#'. */ | |
60 | ||
61 | #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ | |
62 | do { \ | |
63 | if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \ | |
64 | (*info->fprintf_func) (info->stream, "#"); \ | |
65 | } while (0) | |
66 | ||
67 | /* Handle '#' prefixes as operands. */ | |
68 | ||
69 | static void | |
70 | print_hash (cd, dis_info, value, attrs, pc, length) | |
b3466c39 | 71 | CGEN_CPU_DESC cd; |
252b5132 | 72 | PTR dis_info; |
b3466c39 DB |
73 | long value; |
74 | unsigned int attrs; | |
75 | bfd_vma pc; | |
76 | int length; | |
252b5132 RH |
77 | { |
78 | disassemble_info *info = (disassemble_info *) dis_info; | |
79 | (*info->fprintf_func) (info->stream, "#"); | |
80 | } | |
81 | ||
82 | #undef CGEN_PRINT_INSN | |
83 | #define CGEN_PRINT_INSN my_print_insn | |
84 | ||
85 | static int | |
86 | my_print_insn (cd, pc, info) | |
87 | CGEN_CPU_DESC cd; | |
88 | bfd_vma pc; | |
89 | disassemble_info *info; | |
90 | { | |
91 | char buffer[CGEN_MAX_INSN_SIZE]; | |
92 | char *buf = buffer; | |
93 | int status; | |
94 | int buflen = (pc & 3) == 0 ? 4 : 2; | |
95 | ||
96 | /* Read the base part of the insn. */ | |
97 | ||
98 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
99 | if (status != 0) | |
100 | { | |
101 | (*info->memory_error_func) (status, pc, info); | |
102 | return -1; | |
103 | } | |
104 | ||
105 | /* 32 bit insn? */ | |
106 | if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) | |
107 | return print_insn (cd, pc, info, buf, buflen); | |
108 | ||
109 | /* Print the first insn. */ | |
110 | if ((pc & 3) == 0) | |
111 | { | |
112 | if (print_insn (cd, pc, info, buf, 2) == 0) | |
113 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
114 | buf += 2; | |
115 | } | |
116 | ||
117 | if (buf[0] & 0x80) | |
118 | { | |
119 | /* Parallel. */ | |
120 | (*info->fprintf_func) (info->stream, " || "); | |
121 | buf[0] &= 0x7f; | |
122 | } | |
123 | else | |
124 | (*info->fprintf_func) (info->stream, " -> "); | |
125 | ||
126 | /* The "& 3" is to pass a consistent address. | |
127 | Parallel insns arguably both begin on the word boundary. | |
128 | Also, branch insns are calculated relative to the word boundary. */ | |
129 | if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0) | |
130 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
131 | ||
132 | return (pc & 3) ? 2 : 4; | |
133 | } | |
134 | ||
135 | /* -- */ | |
136 | ||
137 | /* Main entry point for printing operands. | |
138 | XINFO is a `void *' and not a `disassemble_info *' to not put a requirement | |
139 | of dis-asm.h on cgen.h. | |
140 | ||
141 | This function is basically just a big switch statement. Earlier versions | |
142 | used tables to look up the function to use, but | |
143 | - if the table contains both assembler and disassembler functions then | |
144 | the disassembler contains much of the assembler and vice-versa, | |
145 | - there's a lot of inlining possibilities as things grow, | |
146 | - using a switch statement avoids the function call overhead. | |
147 | ||
148 | This function could be moved into `print_insn_normal', but keeping it | |
149 | separate makes clear the interface between `print_insn_normal' and each of | |
150 | the handlers. | |
151 | */ | |
152 | ||
153 | void | |
154 | m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) | |
155 | CGEN_CPU_DESC cd; | |
156 | int opindex; | |
157 | PTR xinfo; | |
158 | CGEN_FIELDS *fields; | |
b3466c39 | 159 | void const *attrs; |
252b5132 RH |
160 | bfd_vma pc; |
161 | int length; | |
162 | { | |
163 | disassemble_info *info = (disassemble_info *) xinfo; | |
164 | ||
165 | switch (opindex) | |
166 | { | |
1fa60b5d DE |
167 | case M32R_OPERAND_ACC : |
168 | print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0); | |
169 | break; | |
170 | case M32R_OPERAND_ACCD : | |
171 | print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0); | |
172 | break; | |
173 | case M32R_OPERAND_ACCS : | |
174 | print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0); | |
175 | break; | |
252b5132 RH |
176 | case M32R_OPERAND_DCR : |
177 | print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0); | |
178 | break; | |
179 | case M32R_OPERAND_DISP16 : | |
180 | print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
181 | break; | |
182 | case M32R_OPERAND_DISP24 : | |
183 | print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
184 | break; | |
185 | case M32R_OPERAND_DISP8 : | |
186 | print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
187 | break; | |
188 | case M32R_OPERAND_DR : | |
189 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); | |
190 | break; | |
191 | case M32R_OPERAND_HASH : | |
eb1b03df | 192 | print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
252b5132 RH |
193 | break; |
194 | case M32R_OPERAND_HI16 : | |
195 | print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); | |
196 | break; | |
1fa60b5d DE |
197 | case M32R_OPERAND_IMM1 : |
198 | print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
199 | break; | |
252b5132 RH |
200 | case M32R_OPERAND_SCR : |
201 | print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0); | |
202 | break; | |
203 | case M32R_OPERAND_SIMM16 : | |
204 | print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
205 | break; | |
206 | case M32R_OPERAND_SIMM8 : | |
207 | print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
208 | break; | |
209 | case M32R_OPERAND_SLO16 : | |
210 | print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); | |
211 | break; | |
212 | case M32R_OPERAND_SR : | |
213 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); | |
214 | break; | |
215 | case M32R_OPERAND_SRC1 : | |
216 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); | |
217 | break; | |
218 | case M32R_OPERAND_SRC2 : | |
219 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); | |
220 | break; | |
221 | case M32R_OPERAND_UIMM16 : | |
222 | print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
223 | break; | |
224 | case M32R_OPERAND_UIMM24 : | |
225 | print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); | |
226 | break; | |
227 | case M32R_OPERAND_UIMM4 : | |
228 | print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
229 | break; | |
230 | case M32R_OPERAND_UIMM5 : | |
231 | print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
232 | break; | |
233 | case M32R_OPERAND_ULO16 : | |
234 | print_normal (cd, info, fields->f_uimm16, 0, pc, length); | |
235 | break; | |
236 | ||
237 | default : | |
238 | /* xgettext:c-format */ | |
239 | fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), | |
240 | opindex); | |
241 | abort (); | |
242 | } | |
243 | } | |
244 | ||
245 | cgen_print_fn * const m32r_cgen_print_handlers[] = | |
246 | { | |
247 | print_insn_normal, | |
248 | }; | |
249 | ||
250 | ||
251 | void | |
252 | m32r_cgen_init_dis (cd) | |
253 | CGEN_CPU_DESC cd; | |
254 | { | |
255 | m32r_cgen_init_opcode_table (cd); | |
256 | m32r_cgen_init_ibld_table (cd); | |
257 | cd->print_handlers = & m32r_cgen_print_handlers[0]; | |
258 | cd->print_operand = m32r_cgen_print_operand; | |
259 | } | |
260 | ||
261 | \f | |
262 | /* Default print handler. */ | |
263 | ||
264 | static void | |
265 | print_normal (cd, dis_info, value, attrs, pc, length) | |
b3466c39 DB |
266 | #ifdef CGEN_PRINT_NORMAL |
267 | CGEN_CPU_DESC cd; | |
268 | #else | |
6bb95a0f | 269 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
b3466c39 | 270 | #endif |
252b5132 RH |
271 | PTR dis_info; |
272 | long value; | |
273 | unsigned int attrs; | |
b3466c39 DB |
274 | #ifdef CGEN_PRINT_NORMAL |
275 | bfd_vma pc; | |
276 | int length; | |
277 | #else | |
6bb95a0f DB |
278 | bfd_vma pc ATTRIBUTE_UNUSED; |
279 | int length ATTRIBUTE_UNUSED; | |
b3466c39 | 280 | #endif |
252b5132 RH |
281 | { |
282 | disassemble_info *info = (disassemble_info *) dis_info; | |
283 | ||
284 | #ifdef CGEN_PRINT_NORMAL | |
285 | CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); | |
286 | #endif | |
287 | ||
288 | /* Print the operand as directed by the attributes. */ | |
289 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
290 | ; /* nothing to do */ | |
291 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
292 | (*info->fprintf_func) (info->stream, "%ld", value); | |
293 | else | |
294 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
295 | } | |
296 | ||
297 | /* Default address handler. */ | |
298 | ||
299 | static void | |
300 | print_address (cd, dis_info, value, attrs, pc, length) | |
b3466c39 DB |
301 | #ifdef CGEN_PRINT_NORMAL |
302 | CGEN_CPU_DESC cd; | |
303 | #else | |
6bb95a0f | 304 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
b3466c39 | 305 | #endif |
252b5132 RH |
306 | PTR dis_info; |
307 | bfd_vma value; | |
308 | unsigned int attrs; | |
b3466c39 DB |
309 | #ifdef CGEN_PRINT_NORMAL |
310 | bfd_vma pc; | |
311 | int length; | |
312 | #else | |
6bb95a0f DB |
313 | bfd_vma pc ATTRIBUTE_UNUSED; |
314 | int length ATTRIBUTE_UNUSED; | |
b3466c39 | 315 | #endif |
252b5132 RH |
316 | { |
317 | disassemble_info *info = (disassemble_info *) dis_info; | |
318 | ||
319 | #ifdef CGEN_PRINT_ADDRESS | |
320 | CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); | |
321 | #endif | |
322 | ||
323 | /* Print the operand as directed by the attributes. */ | |
324 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
325 | ; /* nothing to do */ | |
326 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) | |
327 | (*info->print_address_func) (value, info); | |
328 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) | |
329 | (*info->print_address_func) (value, info); | |
330 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
331 | (*info->fprintf_func) (info->stream, "%ld", (long) value); | |
332 | else | |
333 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value); | |
334 | } | |
335 | ||
336 | /* Keyword print handler. */ | |
337 | ||
338 | static void | |
339 | print_keyword (cd, dis_info, keyword_table, value, attrs) | |
6bb95a0f | 340 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
252b5132 RH |
341 | PTR dis_info; |
342 | CGEN_KEYWORD *keyword_table; | |
343 | long value; | |
6bb95a0f | 344 | unsigned int attrs ATTRIBUTE_UNUSED; |
252b5132 RH |
345 | { |
346 | disassemble_info *info = (disassemble_info *) dis_info; | |
347 | const CGEN_KEYWORD_ENTRY *ke; | |
348 | ||
349 | ke = cgen_keyword_lookup_value (keyword_table, value); | |
350 | if (ke != NULL) | |
351 | (*info->fprintf_func) (info->stream, "%s", ke->name); | |
352 | else | |
353 | (*info->fprintf_func) (info->stream, "???"); | |
354 | } | |
355 | \f | |
356 | /* Default insn printer. | |
357 | ||
358 | DIS_INFO is defined as `PTR' so the disassembler needn't know anything | |
359 | about disassemble_info. */ | |
360 | ||
361 | static void | |
362 | print_insn_normal (cd, dis_info, insn, fields, pc, length) | |
363 | CGEN_CPU_DESC cd; | |
364 | PTR dis_info; | |
365 | const CGEN_INSN *insn; | |
366 | CGEN_FIELDS *fields; | |
367 | bfd_vma pc; | |
368 | int length; | |
369 | { | |
370 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
371 | disassemble_info *info = (disassemble_info *) dis_info; | |
b3466c39 | 372 | const CGEN_SYNTAX_CHAR_TYPE *syn; |
252b5132 RH |
373 | |
374 | CGEN_INIT_PRINT (cd); | |
375 | ||
376 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
377 | { | |
378 | if (CGEN_SYNTAX_MNEMONIC_P (*syn)) | |
379 | { | |
380 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); | |
381 | continue; | |
382 | } | |
383 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
384 | { | |
385 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); | |
386 | continue; | |
387 | } | |
388 | ||
389 | /* We have an operand. */ | |
390 | m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, | |
391 | fields, CGEN_INSN_ATTRS (insn), pc, length); | |
392 | } | |
393 | } | |
394 | \f | |
6bb95a0f DB |
395 | /* Subroutine of print_insn. Reads an insn into the given buffers and updates |
396 | the extract info. | |
397 | Returns 0 if all is well, non-zero otherwise. */ | |
252b5132 | 398 | static int |
6bb95a0f | 399 | read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) |
b3466c39 | 400 | CGEN_CPU_DESC cd; |
252b5132 RH |
401 | bfd_vma pc; |
402 | disassemble_info *info; | |
403 | char *buf; | |
404 | int buflen; | |
6bb95a0f DB |
405 | CGEN_EXTRACT_INFO *ex_info; |
406 | unsigned long *insn_value; | |
252b5132 | 407 | { |
6bb95a0f DB |
408 | int status = (*info->read_memory_func) (pc, buf, buflen, info); |
409 | if (status != 0) | |
410 | { | |
411 | (*info->memory_error_func) (status, pc, info); | |
412 | return -1; | |
413 | } | |
252b5132 | 414 | |
6bb95a0f DB |
415 | ex_info->dis_info = info; |
416 | ex_info->valid = (1 << buflen) - 1; | |
417 | ex_info->insn_bytes = buf; | |
252b5132 | 418 | |
b3466c39 | 419 | *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); |
6bb95a0f DB |
420 | return 0; |
421 | } | |
422 | ||
423 | /* Utility to print an insn. | |
424 | BUF is the base part of the insn, target byte order, BUFLEN bytes long. | |
425 | The result is the size of the insn in bytes or zero for an unknown insn | |
426 | or -1 if an error occurs fetching data (memory_error_func will have | |
427 | been called). */ | |
428 | ||
429 | static int | |
430 | print_insn (cd, pc, info, buf, buflen) | |
431 | CGEN_CPU_DESC cd; | |
432 | bfd_vma pc; | |
433 | disassemble_info *info; | |
434 | char *buf; | |
435 | int buflen; | |
436 | { | |
437 | unsigned long insn_value; | |
438 | const CGEN_INSN_LIST *insn_list; | |
439 | CGEN_EXTRACT_INFO ex_info; | |
b3466c39 | 440 | |
52646233 FCE |
441 | /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ |
442 | insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); | |
443 | ||
444 | /* Fill in ex_info fields like read_insn would. Don't actually call | |
445 | read_insn, since the incoming buffer is already read (and possibly | |
446 | modified a la m32r). */ | |
447 | ex_info.valid = (1 << buflen) - 1; | |
448 | ex_info.dis_info = info; | |
449 | ex_info.insn_bytes = buf; | |
6bb95a0f | 450 | |
252b5132 RH |
451 | /* The instructions are stored in hash lists. |
452 | Pick the first one and keep trying until we find the right one. */ | |
453 | ||
454 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); | |
455 | while (insn_list != NULL) | |
456 | { | |
457 | const CGEN_INSN *insn = insn_list->insn; | |
458 | CGEN_FIELDS fields; | |
459 | int length; | |
52646233 | 460 | unsigned long insn_value_cropped; |
252b5132 | 461 | |
cfcdbe97 AH |
462 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED |
463 | /* not needed as insn shouldn't be in hash lists if not supported */ | |
252b5132 RH |
464 | /* Supported by this cpu? */ |
465 | if (! m32r_cgen_insn_supported (cd, insn)) | |
cfcdbe97 AH |
466 | { |
467 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
468 | continue; | |
469 | } | |
252b5132 RH |
470 | #endif |
471 | ||
472 | /* Basic bit mask must be correct. */ | |
473 | /* ??? May wish to allow target to defer this check until the extract | |
474 | handler. */ | |
52646233 FCE |
475 | |
476 | /* Base size may exceed this instruction's size. Extract the | |
477 | relevant part from the buffer. */ | |
478 | if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen && | |
479 | (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
480 | insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), | |
481 | info->endian == BFD_ENDIAN_BIG); | |
482 | else | |
483 | insn_value_cropped = insn_value; | |
484 | ||
485 | if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) | |
252b5132 RH |
486 | == CGEN_INSN_BASE_VALUE (insn)) |
487 | { | |
488 | /* Printing is handled in two passes. The first pass parses the | |
489 | machine insn and extracts the fields. The second pass prints | |
490 | them. */ | |
491 | ||
54faae25 NC |
492 | /* Make sure the entire insn is loaded into insn_value, if it |
493 | can fit. */ | |
b3466c39 DB |
494 | if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && |
495 | (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
6bb95a0f DB |
496 | { |
497 | unsigned long full_insn_value; | |
498 | int rc = read_insn (cd, pc, info, buf, | |
499 | CGEN_INSN_BITSIZE (insn) / 8, | |
500 | & ex_info, & full_insn_value); | |
501 | if (rc != 0) | |
502 | return rc; | |
503 | length = CGEN_EXTRACT_FN (cd, insn) | |
504 | (cd, insn, &ex_info, full_insn_value, &fields, pc); | |
505 | } | |
506 | else | |
54faae25 NC |
507 | length = CGEN_EXTRACT_FN (cd, insn) |
508 | (cd, insn, &ex_info, insn_value, &fields, pc); | |
b3466c39 | 509 | |
252b5132 RH |
510 | /* length < 0 -> error */ |
511 | if (length < 0) | |
512 | return length; | |
513 | if (length > 0) | |
514 | { | |
515 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); | |
516 | /* length is in bits, result is in bytes */ | |
517 | return length / 8; | |
518 | } | |
519 | } | |
520 | ||
521 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
522 | } | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | /* Default value for CGEN_PRINT_INSN. | |
528 | The result is the size of the insn in bytes or zero for an unknown insn | |
529 | or -1 if an error occured fetching bytes. */ | |
530 | ||
531 | #ifndef CGEN_PRINT_INSN | |
532 | #define CGEN_PRINT_INSN default_print_insn | |
b3466c39 | 533 | #endif |
252b5132 RH |
534 | |
535 | static int | |
536 | default_print_insn (cd, pc, info) | |
537 | CGEN_CPU_DESC cd; | |
538 | bfd_vma pc; | |
539 | disassemble_info *info; | |
540 | { | |
541 | char buf[CGEN_MAX_INSN_SIZE]; | |
542 | int status; | |
543 | ||
544 | /* Read the base part of the insn. */ | |
545 | ||
546 | status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info); | |
547 | if (status != 0) | |
548 | { | |
549 | (*info->memory_error_func) (status, pc, info); | |
550 | return -1; | |
551 | } | |
552 | ||
553 | return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8); | |
554 | } | |
555 | ||
556 | /* Main entry point. | |
557 | Print one instruction from PC on INFO->STREAM. | |
558 | Return the size of the instruction (in bytes). */ | |
559 | ||
560 | int | |
561 | print_insn_m32r (pc, info) | |
562 | bfd_vma pc; | |
563 | disassemble_info *info; | |
564 | { | |
565 | static CGEN_CPU_DESC cd = 0; | |
6bb95a0f DB |
566 | static int prev_isa; |
567 | static int prev_mach; | |
568 | static int prev_endian; | |
252b5132 RH |
569 | int length; |
570 | int isa,mach; | |
571 | int endian = (info->endian == BFD_ENDIAN_BIG | |
572 | ? CGEN_ENDIAN_BIG | |
573 | : CGEN_ENDIAN_LITTLE); | |
574 | enum bfd_architecture arch; | |
575 | ||
576 | /* ??? gdb will set mach but leave the architecture as "unknown" */ | |
577 | #ifndef CGEN_BFD_ARCH | |
578 | #define CGEN_BFD_ARCH bfd_arch_m32r | |
579 | #endif | |
580 | arch = info->arch; | |
581 | if (arch == bfd_arch_unknown) | |
582 | arch = CGEN_BFD_ARCH; | |
27fca2d8 PM |
583 | |
584 | /* There's no standard way to compute the machine or isa number | |
252b5132 | 585 | so we leave it to the target. */ |
27fca2d8 PM |
586 | #ifdef CGEN_COMPUTE_MACH |
587 | mach = CGEN_COMPUTE_MACH (info); | |
588 | #else | |
589 | mach = info->mach; | |
590 | #endif | |
591 | ||
252b5132 RH |
592 | #ifdef CGEN_COMPUTE_ISA |
593 | isa = CGEN_COMPUTE_ISA (info); | |
594 | #else | |
595 | isa = 0; | |
596 | #endif | |
597 | ||
252b5132 RH |
598 | /* If we've switched cpu's, close the current table and open a new one. */ |
599 | if (cd | |
600 | && (isa != prev_isa | |
601 | || mach != prev_mach | |
602 | || endian != prev_endian)) | |
603 | { | |
604 | m32r_cgen_cpu_close (cd); | |
605 | cd = 0; | |
606 | } | |
607 | ||
608 | /* If we haven't initialized yet, initialize the opcode table. */ | |
609 | if (! cd) | |
610 | { | |
611 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); | |
612 | const char *mach_name; | |
613 | ||
614 | if (!arch_type) | |
615 | abort (); | |
616 | mach_name = arch_type->printable_name; | |
617 | ||
618 | prev_isa = isa; | |
619 | prev_mach = mach; | |
620 | prev_endian = endian; | |
621 | cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, | |
622 | CGEN_CPU_OPEN_BFDMACH, mach_name, | |
623 | CGEN_CPU_OPEN_ENDIAN, prev_endian, | |
624 | CGEN_CPU_OPEN_END); | |
625 | if (!cd) | |
626 | abort (); | |
627 | m32r_cgen_init_dis (cd); | |
628 | } | |
629 | ||
630 | /* We try to have as much common code as possible. | |
631 | But at this point some targets need to take over. */ | |
632 | /* ??? Some targets may need a hook elsewhere. Try to avoid this, | |
633 | but if not possible try to move this hook elsewhere rather than | |
634 | have two hooks. */ | |
635 | length = CGEN_PRINT_INSN (cd, pc, info); | |
636 | if (length > 0) | |
637 | return length; | |
638 | if (length < 0) | |
639 | return -1; | |
640 | ||
641 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
642 | return cd->default_insn_bitsize / 8; | |
643 | } |