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252b5132 RH |
1 | /* Disassembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | - the resultant file is machine generated, cgen-dis.in isn't | |
6 | ||
7 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
8 | ||
9 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software Foundation, Inc., | |
23 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
26 | Keep that in mind. */ | |
27 | ||
28 | #include "sysdep.h" | |
29 | #include <stdio.h> | |
30 | #include "ansidecl.h" | |
31 | #include "dis-asm.h" | |
32 | #include "bfd.h" | |
33 | #include "symcat.h" | |
34 | #include "m32r-desc.h" | |
35 | #include "m32r-opc.h" | |
36 | #include "opintl.h" | |
37 | ||
38 | /* Default text to print if an instruction isn't recognized. */ | |
39 | #define UNKNOWN_INSN_MSG _("*unknown*") | |
40 | ||
41 | static void print_normal | |
42 | PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); | |
43 | static void print_address | |
44 | PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); | |
45 | static void print_keyword | |
46 | PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); | |
47 | static void print_insn_normal | |
48 | PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, | |
49 | bfd_vma, int)); | |
50 | static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, | |
51 | disassemble_info *, char *, int)); | |
52 | static int default_print_insn | |
53 | PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); | |
54 | \f | |
55 | /* -- disassembler routines inserted here */ | |
56 | ||
57 | /* -- dis.c */ | |
58 | ||
59 | /* Immediate values are prefixed with '#'. */ | |
60 | ||
61 | #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ | |
62 | do { \ | |
63 | if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \ | |
64 | (*info->fprintf_func) (info->stream, "#"); \ | |
65 | } while (0) | |
66 | ||
67 | /* Handle '#' prefixes as operands. */ | |
68 | ||
69 | static void | |
70 | print_hash (cd, dis_info, value, attrs, pc, length) | |
71 | CGEN_CPU_DESC cd; | |
72 | PTR dis_info; | |
73 | long value; | |
74 | unsigned int attrs; | |
75 | bfd_vma pc; | |
76 | int length; | |
77 | { | |
78 | disassemble_info *info = (disassemble_info *) dis_info; | |
79 | (*info->fprintf_func) (info->stream, "#"); | |
80 | } | |
81 | ||
82 | #undef CGEN_PRINT_INSN | |
83 | #define CGEN_PRINT_INSN my_print_insn | |
84 | ||
85 | static int | |
86 | my_print_insn (cd, pc, info) | |
87 | CGEN_CPU_DESC cd; | |
88 | bfd_vma pc; | |
89 | disassemble_info *info; | |
90 | { | |
91 | char buffer[CGEN_MAX_INSN_SIZE]; | |
92 | char *buf = buffer; | |
93 | int status; | |
94 | int buflen = (pc & 3) == 0 ? 4 : 2; | |
95 | ||
96 | /* Read the base part of the insn. */ | |
97 | ||
98 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
99 | if (status != 0) | |
100 | { | |
101 | (*info->memory_error_func) (status, pc, info); | |
102 | return -1; | |
103 | } | |
104 | ||
105 | /* 32 bit insn? */ | |
106 | if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) | |
107 | return print_insn (cd, pc, info, buf, buflen); | |
108 | ||
109 | /* Print the first insn. */ | |
110 | if ((pc & 3) == 0) | |
111 | { | |
112 | if (print_insn (cd, pc, info, buf, 2) == 0) | |
113 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
114 | buf += 2; | |
115 | } | |
116 | ||
117 | if (buf[0] & 0x80) | |
118 | { | |
119 | /* Parallel. */ | |
120 | (*info->fprintf_func) (info->stream, " || "); | |
121 | buf[0] &= 0x7f; | |
122 | } | |
123 | else | |
124 | (*info->fprintf_func) (info->stream, " -> "); | |
125 | ||
126 | /* The "& 3" is to pass a consistent address. | |
127 | Parallel insns arguably both begin on the word boundary. | |
128 | Also, branch insns are calculated relative to the word boundary. */ | |
129 | if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0) | |
130 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
131 | ||
132 | return (pc & 3) ? 2 : 4; | |
133 | } | |
134 | ||
135 | /* -- */ | |
136 | ||
137 | /* Main entry point for printing operands. | |
138 | XINFO is a `void *' and not a `disassemble_info *' to not put a requirement | |
139 | of dis-asm.h on cgen.h. | |
140 | ||
141 | This function is basically just a big switch statement. Earlier versions | |
142 | used tables to look up the function to use, but | |
143 | - if the table contains both assembler and disassembler functions then | |
144 | the disassembler contains much of the assembler and vice-versa, | |
145 | - there's a lot of inlining possibilities as things grow, | |
146 | - using a switch statement avoids the function call overhead. | |
147 | ||
148 | This function could be moved into `print_insn_normal', but keeping it | |
149 | separate makes clear the interface between `print_insn_normal' and each of | |
150 | the handlers. | |
151 | */ | |
152 | ||
153 | void | |
154 | m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) | |
155 | CGEN_CPU_DESC cd; | |
156 | int opindex; | |
157 | PTR xinfo; | |
158 | CGEN_FIELDS *fields; | |
159 | void const *attrs; | |
160 | bfd_vma pc; | |
161 | int length; | |
162 | { | |
163 | disassemble_info *info = (disassemble_info *) xinfo; | |
164 | ||
165 | switch (opindex) | |
166 | { | |
167 | case M32R_OPERAND_DCR : | |
168 | print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0); | |
169 | break; | |
170 | case M32R_OPERAND_DISP16 : | |
171 | print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
172 | break; | |
173 | case M32R_OPERAND_DISP24 : | |
174 | print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
175 | break; | |
176 | case M32R_OPERAND_DISP8 : | |
177 | print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
178 | break; | |
179 | case M32R_OPERAND_DR : | |
180 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); | |
181 | break; | |
182 | case M32R_OPERAND_HASH : | |
183 | print_hash (cd, info, fields->f_nil, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); | |
184 | break; | |
185 | case M32R_OPERAND_HI16 : | |
186 | print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); | |
187 | break; | |
188 | case M32R_OPERAND_SCR : | |
189 | print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0); | |
190 | break; | |
191 | case M32R_OPERAND_SIMM16 : | |
192 | print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
193 | break; | |
194 | case M32R_OPERAND_SIMM8 : | |
195 | print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
196 | break; | |
197 | case M32R_OPERAND_SLO16 : | |
198 | print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); | |
199 | break; | |
200 | case M32R_OPERAND_SR : | |
201 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); | |
202 | break; | |
203 | case M32R_OPERAND_SRC1 : | |
204 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); | |
205 | break; | |
206 | case M32R_OPERAND_SRC2 : | |
207 | print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); | |
208 | break; | |
209 | case M32R_OPERAND_UIMM16 : | |
210 | print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
211 | break; | |
212 | case M32R_OPERAND_UIMM24 : | |
213 | print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); | |
214 | break; | |
215 | case M32R_OPERAND_UIMM4 : | |
216 | print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
217 | break; | |
218 | case M32R_OPERAND_UIMM5 : | |
219 | print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
220 | break; | |
221 | case M32R_OPERAND_ULO16 : | |
222 | print_normal (cd, info, fields->f_uimm16, 0, pc, length); | |
223 | break; | |
224 | ||
225 | default : | |
226 | /* xgettext:c-format */ | |
227 | fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), | |
228 | opindex); | |
229 | abort (); | |
230 | } | |
231 | } | |
232 | ||
233 | cgen_print_fn * const m32r_cgen_print_handlers[] = | |
234 | { | |
235 | print_insn_normal, | |
236 | }; | |
237 | ||
238 | ||
239 | void | |
240 | m32r_cgen_init_dis (cd) | |
241 | CGEN_CPU_DESC cd; | |
242 | { | |
243 | m32r_cgen_init_opcode_table (cd); | |
244 | m32r_cgen_init_ibld_table (cd); | |
245 | cd->print_handlers = & m32r_cgen_print_handlers[0]; | |
246 | cd->print_operand = m32r_cgen_print_operand; | |
247 | } | |
248 | ||
249 | \f | |
250 | /* Default print handler. */ | |
251 | ||
252 | static void | |
253 | print_normal (cd, dis_info, value, attrs, pc, length) | |
254 | CGEN_CPU_DESC cd; | |
255 | PTR dis_info; | |
256 | long value; | |
257 | unsigned int attrs; | |
258 | bfd_vma pc; | |
259 | int length; | |
260 | { | |
261 | disassemble_info *info = (disassemble_info *) dis_info; | |
262 | ||
263 | #ifdef CGEN_PRINT_NORMAL | |
264 | CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); | |
265 | #endif | |
266 | ||
267 | /* Print the operand as directed by the attributes. */ | |
268 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
269 | ; /* nothing to do */ | |
270 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
271 | (*info->fprintf_func) (info->stream, "%ld", value); | |
272 | else | |
273 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
274 | } | |
275 | ||
276 | /* Default address handler. */ | |
277 | ||
278 | static void | |
279 | print_address (cd, dis_info, value, attrs, pc, length) | |
280 | CGEN_CPU_DESC cd; | |
281 | PTR dis_info; | |
282 | bfd_vma value; | |
283 | unsigned int attrs; | |
284 | bfd_vma pc; | |
285 | int length; | |
286 | { | |
287 | disassemble_info *info = (disassemble_info *) dis_info; | |
288 | ||
289 | #ifdef CGEN_PRINT_ADDRESS | |
290 | CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); | |
291 | #endif | |
292 | ||
293 | /* Print the operand as directed by the attributes. */ | |
294 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
295 | ; /* nothing to do */ | |
296 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) | |
297 | (*info->print_address_func) (value, info); | |
298 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) | |
299 | (*info->print_address_func) (value, info); | |
300 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
301 | (*info->fprintf_func) (info->stream, "%ld", (long) value); | |
302 | else | |
303 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value); | |
304 | } | |
305 | ||
306 | /* Keyword print handler. */ | |
307 | ||
308 | static void | |
309 | print_keyword (cd, dis_info, keyword_table, value, attrs) | |
310 | CGEN_CPU_DESC cd; | |
311 | PTR dis_info; | |
312 | CGEN_KEYWORD *keyword_table; | |
313 | long value; | |
314 | unsigned int attrs; | |
315 | { | |
316 | disassemble_info *info = (disassemble_info *) dis_info; | |
317 | const CGEN_KEYWORD_ENTRY *ke; | |
318 | ||
319 | ke = cgen_keyword_lookup_value (keyword_table, value); | |
320 | if (ke != NULL) | |
321 | (*info->fprintf_func) (info->stream, "%s", ke->name); | |
322 | else | |
323 | (*info->fprintf_func) (info->stream, "???"); | |
324 | } | |
325 | \f | |
326 | /* Default insn printer. | |
327 | ||
328 | DIS_INFO is defined as `PTR' so the disassembler needn't know anything | |
329 | about disassemble_info. */ | |
330 | ||
331 | static void | |
332 | print_insn_normal (cd, dis_info, insn, fields, pc, length) | |
333 | CGEN_CPU_DESC cd; | |
334 | PTR dis_info; | |
335 | const CGEN_INSN *insn; | |
336 | CGEN_FIELDS *fields; | |
337 | bfd_vma pc; | |
338 | int length; | |
339 | { | |
340 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
341 | disassemble_info *info = (disassemble_info *) dis_info; | |
342 | const unsigned char *syn; | |
343 | ||
344 | CGEN_INIT_PRINT (cd); | |
345 | ||
346 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
347 | { | |
348 | if (CGEN_SYNTAX_MNEMONIC_P (*syn)) | |
349 | { | |
350 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); | |
351 | continue; | |
352 | } | |
353 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
354 | { | |
355 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); | |
356 | continue; | |
357 | } | |
358 | ||
359 | /* We have an operand. */ | |
360 | m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, | |
361 | fields, CGEN_INSN_ATTRS (insn), pc, length); | |
362 | } | |
363 | } | |
364 | \f | |
365 | /* Utility to print an insn. | |
366 | BUF is the base part of the insn, target byte order, BUFLEN bytes long. | |
367 | The result is the size of the insn in bytes or zero for an unknown insn | |
368 | or -1 if an error occurs fetching data (memory_error_func will have | |
369 | been called). */ | |
370 | ||
371 | static int | |
372 | print_insn (cd, pc, info, buf, buflen) | |
373 | CGEN_CPU_DESC cd; | |
374 | bfd_vma pc; | |
375 | disassemble_info *info; | |
376 | char *buf; | |
377 | int buflen; | |
378 | { | |
379 | unsigned long insn_value; | |
380 | const CGEN_INSN_LIST *insn_list; | |
381 | CGEN_EXTRACT_INFO ex_info; | |
382 | ||
383 | ex_info.dis_info = info; | |
384 | ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1; | |
385 | ex_info.insn_bytes = buf; | |
386 | ||
387 | switch (buflen) | |
388 | { | |
389 | case 1: | |
390 | insn_value = buf[0]; | |
391 | break; | |
392 | case 2: | |
393 | insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); | |
394 | break; | |
395 | case 4: | |
396 | insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); | |
397 | break; | |
398 | default: | |
399 | abort (); | |
400 | } | |
401 | ||
402 | /* The instructions are stored in hash lists. | |
403 | Pick the first one and keep trying until we find the right one. */ | |
404 | ||
405 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); | |
406 | while (insn_list != NULL) | |
407 | { | |
408 | const CGEN_INSN *insn = insn_list->insn; | |
409 | CGEN_FIELDS fields; | |
410 | int length; | |
411 | ||
412 | #if 0 /* not needed as insn shouldn't be in hash lists if not supported */ | |
413 | /* Supported by this cpu? */ | |
414 | if (! m32r_cgen_insn_supported (cd, insn)) | |
415 | continue; | |
416 | #endif | |
417 | ||
418 | /* Basic bit mask must be correct. */ | |
419 | /* ??? May wish to allow target to defer this check until the extract | |
420 | handler. */ | |
421 | if ((insn_value & CGEN_INSN_BASE_MASK (insn)) | |
422 | == CGEN_INSN_BASE_VALUE (insn)) | |
423 | { | |
424 | /* Printing is handled in two passes. The first pass parses the | |
425 | machine insn and extracts the fields. The second pass prints | |
426 | them. */ | |
427 | ||
428 | length = CGEN_EXTRACT_FN (cd, insn) | |
429 | (cd, insn, &ex_info, insn_value, &fields, pc); | |
430 | /* length < 0 -> error */ | |
431 | if (length < 0) | |
432 | return length; | |
433 | if (length > 0) | |
434 | { | |
435 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); | |
436 | /* length is in bits, result is in bytes */ | |
437 | return length / 8; | |
438 | } | |
439 | } | |
440 | ||
441 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
442 | } | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | /* Default value for CGEN_PRINT_INSN. | |
448 | The result is the size of the insn in bytes or zero for an unknown insn | |
449 | or -1 if an error occured fetching bytes. */ | |
450 | ||
451 | #ifndef CGEN_PRINT_INSN | |
452 | #define CGEN_PRINT_INSN default_print_insn | |
453 | #endif | |
454 | ||
455 | static int | |
456 | default_print_insn (cd, pc, info) | |
457 | CGEN_CPU_DESC cd; | |
458 | bfd_vma pc; | |
459 | disassemble_info *info; | |
460 | { | |
461 | char buf[CGEN_MAX_INSN_SIZE]; | |
462 | int status; | |
463 | ||
464 | /* Read the base part of the insn. */ | |
465 | ||
466 | status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info); | |
467 | if (status != 0) | |
468 | { | |
469 | (*info->memory_error_func) (status, pc, info); | |
470 | return -1; | |
471 | } | |
472 | ||
473 | return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8); | |
474 | } | |
475 | ||
476 | /* Main entry point. | |
477 | Print one instruction from PC on INFO->STREAM. | |
478 | Return the size of the instruction (in bytes). */ | |
479 | ||
480 | int | |
481 | print_insn_m32r (pc, info) | |
482 | bfd_vma pc; | |
483 | disassemble_info *info; | |
484 | { | |
485 | static CGEN_CPU_DESC cd = 0; | |
486 | static prev_isa,prev_mach,prev_endian; | |
487 | int length; | |
488 | int isa,mach; | |
489 | int endian = (info->endian == BFD_ENDIAN_BIG | |
490 | ? CGEN_ENDIAN_BIG | |
491 | : CGEN_ENDIAN_LITTLE); | |
492 | enum bfd_architecture arch; | |
493 | ||
494 | /* ??? gdb will set mach but leave the architecture as "unknown" */ | |
495 | #ifndef CGEN_BFD_ARCH | |
496 | #define CGEN_BFD_ARCH bfd_arch_m32r | |
497 | #endif | |
498 | arch = info->arch; | |
499 | if (arch == bfd_arch_unknown) | |
500 | arch = CGEN_BFD_ARCH; | |
501 | ||
502 | /* There's no standard way to compute the isa number (e.g. for arm thumb) | |
503 | so we leave it to the target. */ | |
504 | #ifdef CGEN_COMPUTE_ISA | |
505 | isa = CGEN_COMPUTE_ISA (info); | |
506 | #else | |
507 | isa = 0; | |
508 | #endif | |
509 | ||
510 | mach = info->mach; | |
511 | ||
512 | /* If we've switched cpu's, close the current table and open a new one. */ | |
513 | if (cd | |
514 | && (isa != prev_isa | |
515 | || mach != prev_mach | |
516 | || endian != prev_endian)) | |
517 | { | |
518 | m32r_cgen_cpu_close (cd); | |
519 | cd = 0; | |
520 | } | |
521 | ||
522 | /* If we haven't initialized yet, initialize the opcode table. */ | |
523 | if (! cd) | |
524 | { | |
525 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); | |
526 | const char *mach_name; | |
527 | ||
528 | if (!arch_type) | |
529 | abort (); | |
530 | mach_name = arch_type->printable_name; | |
531 | ||
532 | prev_isa = isa; | |
533 | prev_mach = mach; | |
534 | prev_endian = endian; | |
535 | cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, | |
536 | CGEN_CPU_OPEN_BFDMACH, mach_name, | |
537 | CGEN_CPU_OPEN_ENDIAN, prev_endian, | |
538 | CGEN_CPU_OPEN_END); | |
539 | if (!cd) | |
540 | abort (); | |
541 | m32r_cgen_init_dis (cd); | |
542 | } | |
543 | ||
544 | /* We try to have as much common code as possible. | |
545 | But at this point some targets need to take over. */ | |
546 | /* ??? Some targets may need a hook elsewhere. Try to avoid this, | |
547 | but if not possible try to move this hook elsewhere rather than | |
548 | have two hooks. */ | |
549 | length = CGEN_PRINT_INSN (cd, pc, info); | |
550 | if (length > 0) | |
551 | return length; | |
552 | if (length < 0) | |
553 | return -1; | |
554 | ||
555 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
556 | return cd->default_insn_bitsize / 8; | |
557 | } |