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* Fix for PR 18665, from sky branch.
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
CommitLineData
ab0bd049
DE		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
9c03036a 3
fbc8134d 4THIS FILE IS USED TO GENERATE m32r-opc.c.
7c26196f 5
ab0bd049 6Copyright (C) 1998 Free Software Foundation, Inc.
9c03036a 7
ab0bd049 8This file is part of the GNU Binutils and GDB, the GNU debugger.
9c03036a
DE		 9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
ab0bd049 20You should have received a copy of the GNU General Public License
fbc8134d
DE		 21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
9c03036a 23
23cf992f 24#include "sysdep.h"
9c03036a
DE		 25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
ab0bd049 29#include "symcat.h"
9c03036a 30#include "m32r-opc.h"
fbc8134d 31#include "opintl.h"
9c03036a 32
5730d39d
DE		 33/* Used by the ifield rtx function. */
34#define FLD(f) (fields->f)
35
c2009f4a
DE		 36/* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40static unsigned int asm_hash_insn PARAMS ((const char *));
41static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
5730d39d 42static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
52a53d1f 43
ab0bd049 44/* Look up instruction INSN_VALUE and extract its fields.
1294c286 45 INSN, if non-null, is the insn table entry.
ab0bd049
DE		 46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
52a53d1f 48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
1294c286 49 If INSN != NULL, LENGTH must be valid.
390bd87d 50 ALIAS_P is non-zero if alias insns are to be included in the search.
1294c286 51
5730d39d 52 The result is a pointer to the insn table entry, or NULL if the instruction
ab0bd049
DE		 53 wasn't recognized. */
54
55const CGEN_INSN *
c2009f4a
DE		 56m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
ab0bd049 58 const CGEN_INSN *insn;
52a53d1f 59 CGEN_INSN_BYTES insn_value;
ab0bd049
DE		 60 int length;
61 CGEN_FIELDS *fields;
1294c286 62 int alias_p;
ab0bd049 63{
5730d39d 64 unsigned char buf[CGEN_MAX_INSN_SIZE];
52a53d1f 65 unsigned char *bufp;
5730d39d 66 CGEN_INSN_INT base_insn;
52a53d1f
DE		 67#if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69#else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72#endif
73
5730d39d
DE		 74#if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78#else
52a53d1f 79 ex_info.dis_info = NULL;
5730d39d 80 ex_info.insn_bytes = insn_value;
52a53d1f 81 ex_info.valid = -1;
5730d39d
DE		 82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
52a53d1f 84#endif
ab0bd049
DE		 85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
ab0bd049
DE		 90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
52a53d1f 93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
ab0bd049
DE		 94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
390bd87d
DE		 98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
ab0bd049 100 {
390bd87d
DE		 101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
5730d39d
DE		 104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
390bd87d 106 {
fbc8134d 107 /* ??? 0 is passed for `pc' */
52a53d1f 108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
5730d39d 109 base_insn, fields,
fbc8134d 110 (bfd_vma) 0);
1294c286
DE		 111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
390bd87d 118 }
ab0bd049
DE		 119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
390bd87d
DE		 126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
1294c286
DE		 130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
390bd87d 133
fbc8134d 134 /* ??? 0 is passed for `pc' */
5730d39d 135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
fbc8134d 136 (bfd_vma) 0);
1294c286
DE		 137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
ab0bd049
DE		 142 }
143
144 return NULL;
145}
146
1294c286 147/* Fill in the operand instances used by INSN whose operands are FIELDS.
b02643b5 148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
1294c286 149 in. */
ab0bd049 150
1294c286 151void
c2009f4a
DE		 152m32r_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
1294c286
DE		 154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
ab0bd049
DE		 156 int *indices;
157{
ab0bd049
DE		 158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
ab0bd049 161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
b2f18612
DE		 162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
ab0bd049
DE		 164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
0cc2fbf3
DE		 170 indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
ab0bd049 172 }
1294c286 173}
ab0bd049 174
1294c286
DE		 175/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 m32r_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183const CGEN_INSN *
c2009f4a
DE		 184m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
1294c286 186 const CGEN_INSN *insn;
52a53d1f 187 CGEN_INSN_BYTES insn_value;
1294c286
DE		 188 int length;
189 int *indices;
190{
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
c2009f4a 195 insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
1294c286
DE		 196 insn != NULL);
197 if (! insn)
198 return NULL;
199
c2009f4a 200 m32r_cgen_get_insn_operands (od, insn, &fields, indices);
ab0bd049
DE		 201 return insn;
202}
23cf992f
NC		 203/* Attributes. */
204
5730d39d
DE		 205static const CGEN_ATTR_ENTRY bool_attr[] =
206{
207 { "#f", 0 },
208 { "#t", 1 },
209 { 0, 0 }
210};
211
7c26196f 212static const CGEN_ATTR_ENTRY MACH_attr[] =
5d07b6cf 213{
52a53d1f 214 { "base", MACH_BASE },
5d07b6cf 215 { "m32r", MACH_M32R },
7c26196f
DE		 216/* start-sanitize-m32rx */
217 { "m32rx", MACH_M32RX },
218/* end-sanitize-m32rx */
219 { "max", MACH_MAX },
220 { 0, 0 }
221};
222
223/* start-sanitize-m32rx */
224static const CGEN_ATTR_ENTRY PIPE_attr[] =
225{
226 { "NONE", PIPE_NONE },
227 { "O", PIPE_O },
228 { "S", PIPE_S },
229 { "OS", PIPE_OS },
23cf992f
NC		 230 { 0, 0 }
231};
232
7c26196f 233/* end-sanitize-m32rx */
5730d39d
DE		 234const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
235{
236 { "MACH", & MACH_attr[0] },
237 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
238 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
239 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
240 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
241 { "RESERVED", &bool_attr[0], &bool_attr[0] },
242 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
243 { "RELOC", &bool_attr[0], &bool_attr[0] },
244 { 0, 0, 0 }
245};
246
52a53d1f
DE		 247const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
248{
249 { "MACH", & MACH_attr[0] },
5730d39d
DE		 250 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
251 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
252 { "SIGNED", &bool_attr[0], &bool_attr[0] },
253 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
254 { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
255 { "PC", &bool_attr[0], &bool_attr[0] },
256 { "PROFILE", &bool_attr[0], &bool_attr[0] },
257 { 0, 0, 0 }
52a53d1f
DE		 258};
259
7c26196f 260const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
5d07b6cf 261{
5730d39d
DE		 262 { "MACH", & MACH_attr[0] },
263 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
264 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
265 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
266 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
267 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
268 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
269 { "RELAX", &bool_attr[0], &bool_attr[0] },
270 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
271 { "RELOC", &bool_attr[0], &bool_attr[0] },
272 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
273 { 0, 0, 0 }
23cf992f
NC		 274};
275
7c26196f 276const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
5d07b6cf 277{
7c26196f
DE		 278 { "MACH", & MACH_attr[0] },
279/* start-sanitize-m32rx */
280 { "PIPE", & PIPE_attr[0] },
281/* end-sanitize-m32rx */
5730d39d
DE		 282 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
283 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
284 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
285 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
286 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
287 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
288 { "RELAX", &bool_attr[0], &bool_attr[0] },
289 { "ALIAS", &bool_attr[0], &bool_attr[0] },
290 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
291 { "PBB", &bool_attr[0], &bool_attr[0] },
292 { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
293/* start-sanitize-m32rx */
294 { "SPECIAL", &bool_attr[0], &bool_attr[0] },
295/* end-sanitize-m32rx */
296 { 0, 0, 0 }
9c03036a
DE		 297};
298
853713a7 299CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
5d07b6cf
DE		 300{
301 { "fp", 13 },
9c03036a
DE		 302 { "lr", 14 },
303 { "sp", 15 },
304 { "r0", 0 },
305 { "r1", 1 },
306 { "r2", 2 },
307 { "r3", 3 },
308 { "r4", 4 },
309 { "r5", 5 },
310 { "r6", 6 },
311 { "r7", 7 },
312 { "r8", 8 },
313 { "r9", 9 },
314 { "r10", 10 },
315 { "r11", 11 },
316 { "r12", 12 },
317 { "r13", 13 },
318 { "r14", 14 },
319 { "r15", 15 }
320};
321
853713a7 322CGEN_KEYWORD m32r_cgen_opval_h_gr =
5d07b6cf
DE		 323{
324 & m32r_cgen_opval_h_gr_entries[0],
9c03036a
DE		 325 19
326};
327
853713a7 328CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
5d07b6cf
DE		 329{
330 { "psw", 0 },
9c03036a
DE		 331 { "cbr", 1 },
332 { "spi", 2 },
333 { "spu", 3 },
334 { "bpc", 6 },
52a53d1f
DE		 335 { "bbpsw", 8 },
336 { "bbpc", 14 },
9c03036a
DE		 337 { "cr0", 0 },
338 { "cr1", 1 },
339 { "cr2", 2 },
340 { "cr3", 3 },
341 { "cr4", 4 },
342 { "cr5", 5 },
b2ddf0c4
NC		 343 { "cr6", 6 },
344 { "cr7", 7 },
345 { "cr8", 8 },
346 { "cr9", 9 },
347 { "cr10", 10 },
348 { "cr11", 11 },
349 { "cr12", 12 },
350 { "cr13", 13 },
351 { "cr14", 14 },
352 { "cr15", 15 }
9c03036a
DE		 353};
354
853713a7 355CGEN_KEYWORD m32r_cgen_opval_h_cr =
5d07b6cf
DE		 356{
357 & m32r_cgen_opval_h_cr_entries[0],
52a53d1f 358 23
9c03036a
DE		 359};
360
7c26196f
DE		 361/* start-sanitize-m32rx */
362CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
363{
364 { "a0", 0 },
365 { "a1", 1 }
366};
23cf992f 367
7c26196f 368CGEN_KEYWORD m32r_cgen_opval_h_accums =
5d07b6cf 369{
7c26196f
DE		 370 & m32r_cgen_opval_h_accums_entries[0],
371 2
9c03036a
DE		 372};
373
7c26196f
DE		 374/* end-sanitize-m32rx */
375
ab0bd049
DE		 376/* The hardware table. */
377
378#define HW_ENT(n) m32r_cgen_hw_entries[n]
379static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
7c26196f 380{
52a53d1f
DE		 381 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
382 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
383 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
384 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
385 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
386 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
5730d39d 387 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
52a53d1f
DE		 388 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
389 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
390 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
391 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
392 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
7c26196f 393/* start-sanitize-m32rx */
52a53d1f 394 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_M32RX) } } },
7c26196f 395/* end-sanitize-m32rx */
52a53d1f
DE		 396 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
397 { HW_H_PSW, & HW_ENT (HW_H_PSW + 1), "h-psw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
398 { HW_H_BPSW, & HW_ENT (HW_H_BPSW + 1), "h-bpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
399 { HW_H_BBPSW, & HW_ENT (HW_H_BBPSW + 1), "h-bbpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
400 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
7c26196f
DE		 401 { 0 }
402};
9c03036a 403
5730d39d
DE		 404/* The instruction field table. */
405
406static const CGEN_IFLD m32r_cgen_ifld_table[] =
407{
408 { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
409 { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
410 { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
411 { M32R_F_COND, "f-cond", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
412 { M32R_F_R1, "f-r1", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
413 { M32R_F_R2, "f-r2", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
414 { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
415 { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
416 { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
417 { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
418 { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
419 { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
420 { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
421 { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
422 { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
423 { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
424 { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
425/* start-sanitize-m32rx */
426 { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
427/* end-sanitize-m32rx */
428/* start-sanitize-m32rx */
429 { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
430/* end-sanitize-m32rx */
431/* start-sanitize-m32rx */
432 { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
433/* end-sanitize-m32rx */
434/* start-sanitize-m32rx */
435 { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
436/* end-sanitize-m32rx */
437/* start-sanitize-m32rx */
438 { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
439/* end-sanitize-m32rx */
440/* start-sanitize-m32rx */
441 { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
442/* end-sanitize-m32rx */
443/* start-sanitize-m32rx */
444 { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
445/* end-sanitize-m32rx */
446/* start-sanitize-m32rx */
447 { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
448/* end-sanitize-m32rx */
449 { 0 }
450};
451
ab0bd049
DE		 452/* The operand table. */
453
8d157f96
DE		 454#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
455#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
0bf55db8 456
7c26196f 457const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
9c03036a 458{
23cf992f 459/* pc: program counter */
ab0bd049 460 { "pc", & HW_ENT (HW_H_PC), 0, 0,
5730d39d 461 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
9c03036a 462/* sr: source register */
ab0bd049 463 { "sr", & HW_ENT (HW_H_GR), 12, 4,
5730d39d 464 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 465/* dr: destination register */
ab0bd049 466 { "dr", & HW_ENT (HW_H_GR), 4, 4,
5730d39d 467 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 468/* src1: source register 1 */
ab0bd049 469 { "src1", & HW_ENT (HW_H_GR), 4, 4,
5730d39d 470 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 471/* src2: source register 2 */
ab0bd049 472 { "src2", & HW_ENT (HW_H_GR), 12, 4,
5730d39d 473 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 474/* scr: source control register */
ab0bd049 475 { "scr", & HW_ENT (HW_H_CR), 12, 4,
5730d39d 476 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 477/* dcr: destination control register */
ab0bd049 478 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
5730d39d 479 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 480/* simm8: 8 bit signed immediate */
ab0bd049 481 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
5730d39d 482 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
9c03036a 483/* simm16: 16 bit signed immediate */
ab0bd049 484 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
5730d39d 485 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
9c03036a 486/* uimm4: 4 bit trap number */
ab0bd049 487 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
5730d39d 488 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 489/* uimm5: 5 bit shift count */
ab0bd049 490 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
5730d39d 491 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 492/* uimm16: 16 bit unsigned immediate */
ab0bd049 493 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
5730d39d 494 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
ab0bd049
DE		 495/* start-sanitize-m32rx */
496/* imm1: 1 bit immediate */
497 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
5730d39d 498 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
ab0bd049
DE		 499/* end-sanitize-m32rx */
500/* start-sanitize-m32rx */
501/* accd: accumulator destination register */
502 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
5730d39d 503 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
ab0bd049 504/* end-sanitize-m32rx */
7c26196f 505/* start-sanitize-m32rx */
ab0bd049
DE		 506/* accs: accumulator source register */
507 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
5730d39d 508 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
7c26196f
DE		 509/* end-sanitize-m32rx */
510/* start-sanitize-m32rx */
511/* acc: accumulator reg (d) */
ab0bd049 512 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
5730d39d 513 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
7c26196f 514/* end-sanitize-m32rx */
a6cefe4f
DE		 515/* hash: # prefix */
516 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
5730d39d 517 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
9c03036a 518/* hi16: high 16 bit immediate, sign optional */
ab0bd049 519 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
5730d39d 520 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 521/* slo16: 16 bit signed immediate, for low() */
ab0bd049 522 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
5730d39d 523 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
9c03036a 524/* ulo16: 16 bit unsigned immediate, for low() */
ab0bd049 525 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
5730d39d 526 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 527/* uimm24: 24 bit address */
ab0bd049 528 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
5730d39d 529 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
9c03036a 530/* disp8: 8 bit displacement */
ab0bd049 531 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
5730d39d 532 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
9c03036a 533/* disp16: 16 bit displacement */
ab0bd049 534 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
5730d39d 535 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
9c03036a 536/* disp24: 24 bit displacement */
ab0bd049 537 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
5730d39d 538 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
23cf992f 539/* condbit: condition bit */
ab0bd049 540 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
5730d39d 541 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
23cf992f 542/* accum: accumulator */
ab0bd049 543 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
5730d39d 544 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
23cf992f
NC		 545};
546
ab0bd049
DE		 547/* Operand references. */
548
7caa7497
DE		 549#define INPUT CGEN_OPERAND_INSTANCE_INPUT
550#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
5730d39d 551#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
7caa7497 552
1294c286 553static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
5730d39d
DE		 554 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
555 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
556 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 557 { 0 }
558};
559
1294c286 560static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
5730d39d
DE		 561 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
562 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
563 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 564 { 0 }
565};
566
1294c286 567static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
5730d39d
DE		 568 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
569 { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0, 0 },
570 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 571 { 0 }
572};
573
1294c286 574static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
5730d39d
DE		 575 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
576 { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0, 0 },
577 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 578 { 0 }
579};
580
1294c286 581static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
5730d39d
DE		 582 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
583 { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 },
584 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 585 { 0 }
586};
587
1294c286 588static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
5730d39d
DE		 589 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
590 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
591 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
592 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
390bd87d
DE		 593 { 0 }
594};
595
1294c286 596static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
5730d39d
DE		 597 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
598 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
599 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
600 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
ab0bd049
DE		 601 { 0 }
602};
603
1294c286 604static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
5730d39d
DE		 605 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
606 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
607 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
608 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
609 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
ab0bd049
DE		 610 { 0 }
611};
612
1294c286 613static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
5730d39d
DE		 614 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
615 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF },
616 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
ab0bd049
DE		 617 { 0 }
618};
619
1294c286 620static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
5730d39d
DE		 621 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
622 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF },
623 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
ab0bd049
DE		 624 { 0 }
625};
626
1294c286 627static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
5730d39d
DE		 628 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
629 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
630 { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
631 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
ab0bd049
DE		 632 { 0 }
633};
634
1294c286 635static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
5730d39d
DE		 636 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
637 { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
638 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
ab0bd049
DE		 639 { 0 }
640};
641
1294c286 642static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
5730d39d
DE		 643 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
644 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 },
645 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
646 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
ab0bd049
DE		 647 { 0 }
648};
649
1294c286 650static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
5730d39d
DE		 651 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
652 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 },
653 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
654 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
ab0bd049
DE		 655 { 0 }
656};
657
b2ddf0c4 658/* start-sanitize-m32rx */
1294c286 659static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
5730d39d
DE		 660 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
661 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
662 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF },
663 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
664 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
ab0bd049
DE		 665 { 0 }
666};
667
b2ddf0c4
NC		 668/* end-sanitize-m32rx */
669/* start-sanitize-m32rx */
1294c286 670static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
5730d39d
DE		 671 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
672 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
673 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF },
674 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
675 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
ab0bd049
DE		 676 { 0 }
677};
678
b2ddf0c4 679/* end-sanitize-m32rx */
1294c286 680static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
5730d39d
DE		 681 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 },
682 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
ab0bd049
DE		 683 { 0 }
684};
685
1294c286 686static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
5730d39d
DE		 687 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 },
688 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
ab0bd049
DE		 689 { 0 }
690};
691
1294c286 692static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
5730d39d
DE		 693 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
694 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
695 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
ab0bd049
DE		 696 { 0 }
697};
698
1294c286 699static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
5730d39d
DE		 700 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
701 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
702 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
ab0bd049
DE		 703 { 0 }
704};
705
b2ddf0c4 706/* start-sanitize-m32rx */
1294c286 707static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
5730d39d
DE		 708 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
709 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
ab0bd049
DE		 710 { 0 }
711};
712
b2ddf0c4 713/* end-sanitize-m32rx */
1294c286 714static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
5730d39d
DE		 715 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
716 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
717 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
ab0bd049
DE		 718 { 0 }
719};
720
b2ddf0c4 721/* start-sanitize-m32rx */
1294c286 722static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
5730d39d
DE		 723 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
724 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF },
725 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
ab0bd049
DE		 726 { 0 }
727};
728
b2ddf0c4 729/* end-sanitize-m32rx */
1294c286 730static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
5730d39d
DE		 731 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
732 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
733 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
734 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
ab0bd049
DE		 735 { 0 }
736};
737
1294c286 738static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
5730d39d
DE		 739 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
740 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
ab0bd049
DE		 741 { 0 }
742};
743
1294c286 744static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
5730d39d
DE		 745 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
746 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
747 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 748 { 0 }
749};
750
1294c286 751static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
5730d39d
DE		 752 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
753 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
754 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
755 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 756 { 0 }
757};
758
1294c286 759static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
5730d39d
DE		 760 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
761 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
762 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 763 { 0 }
764};
765
1294c286 766static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
5730d39d
DE		 767 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
768 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
769 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
770 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 771 { 0 }
772};
773
1294c286 774static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
5730d39d
DE		 775 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
776 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
777 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 778 { 0 }
779};
780
1294c286 781static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
5730d39d
DE		 782 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
783 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
784 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
785 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 786 { 0 }
787};
788
1294c286 789static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
5730d39d
DE		 790 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
791 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
792 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
793 { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
390bd87d
DE		 794 { 0 }
795};
796
1294c286 797static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
5730d39d
DE		 798 { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0, 0 },
799 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 800 { 0 }
801};
802
1294c286 803static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
5730d39d
DE		 804 { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 },
805 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 806 { 0 }
807};
808
1294c286 809static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
5730d39d
DE		 810 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
811 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 812 { 0 }
813};
814
1294c286 815static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
5730d39d
DE		 816 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
817 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
818 { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
819 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
390bd87d
DE		 820 { 0 }
821};
822
1294c286 823static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
5730d39d
DE		 824 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
825 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
826 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
827 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
ab0bd049
DE		 828 { 0 }
829};
830
b2ddf0c4 831/* start-sanitize-m32rx */
1294c286 832static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
5730d39d
DE		 833 { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
834 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
835 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
836 { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
ab0bd049
DE		 837 { 0 }
838};
839
b2ddf0c4 840/* end-sanitize-m32rx */
1294c286 841static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
5730d39d
DE		 842 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
843 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
844 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
390bd87d
DE		 845 { 0 }
846};
847
b2ddf0c4 848/* start-sanitize-m32rx */
1294c286 849static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
5730d39d
DE		 850 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
851 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
852 { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
ab0bd049
DE		 853 { 0 }
854};
855
b2ddf0c4 856/* end-sanitize-m32rx */
1294c286 857static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
5730d39d
DE		 858 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
859 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 860 { 0 }
861};
862
1294c286 863static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
5730d39d
DE		 864 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
865 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 866 { 0 }
867};
868
b2ddf0c4 869/* start-sanitize-m32rx */
1294c286 870static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
5730d39d
DE		 871 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
872 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 873 { 0 }
874};
875
b2ddf0c4 876/* end-sanitize-m32rx */
1294c286 877static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
5730d39d
DE		 878 { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0, 0 },
879 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 880 { 0 }
881};
882
1294c286 883static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
5730d39d
DE		 884 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
885 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
886 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
ab0bd049
DE		 887 { 0 }
888};
889
b2ddf0c4 890/* start-sanitize-m32rx */
1294c286 891static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
5730d39d
DE		 892 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
893 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
894 { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
ab0bd049
DE		 895 { 0 }
896};
897
b2ddf0c4 898/* end-sanitize-m32rx */
1294c286 899static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
5730d39d
DE		 900 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
901 { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0, 0 },
ab0bd049
DE		 902 { 0 }
903};
904
1294c286 905static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
5730d39d
DE		 906 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
907 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
ab0bd049
DE		 908 { 0 }
909};
910
b2ddf0c4 911/* start-sanitize-m32rx */
1294c286 912static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
5730d39d
DE		 913 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
914 { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0, 0 },
915 { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0, 0 },
ab0bd049
DE		 916 { 0 }
917};
918
b2ddf0c4 919/* end-sanitize-m32rx */
1294c286 920static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
5730d39d
DE		 921 { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
922 { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
923 { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
924 { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
925 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
926 { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
927 { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
928 { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
ab0bd049
DE		 929 { 0 }
930};
931
1294c286 932static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
5730d39d
DE		 933 { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0, 0 },
934 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 935 { 0 }
936};
937
1294c286 938static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
5730d39d
DE		 939 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
940 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
941 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
390bd87d
DE		 942 { 0 }
943};
944
1294c286 945static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
5730d39d
DE		 946 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
947 { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0, 0 },
948 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 949 { 0 }
950};
951
1294c286 952static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
5730d39d
DE		 953 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
954 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
955 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
390bd87d
DE		 956 { 0 }
957};
958
1294c286 959static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
5730d39d
DE		 960 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
961 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
962 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
963 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
ab0bd049
DE		 964 { 0 }
965};
966
1294c286 967static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
5730d39d
DE		 968 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
969 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
970 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
390bd87d
DE		 971 { 0 }
972};
973
1294c286 974static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
5730d39d
DE		 975 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
976 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
977 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
978 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
390bd87d
DE		 979 { 0 }
980};
981
1294c286 982static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
5730d39d
DE		 983 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
984 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
985 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
390bd87d
DE		 986 { 0 }
987};
988
1294c286 989static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
5730d39d
DE		 990 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
991 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
992 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
993 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
390bd87d
DE		 994 { 0 }
995};
996
1294c286 997static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
5730d39d
DE		 998 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
999 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1000 { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1001 { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
390bd87d
DE		 1002 { 0 }
1003};
1004
1294c286 1005static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
5730d39d
DE		 1006 { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
1007 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1008 { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
1009 { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
1010 { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0, 0 },
1011 { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
1012 { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
1013 { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
1014 { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
1015 { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
1016 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
ab0bd049
DE		 1017 { 0 }
1018};
1019
1294c286 1020static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
5730d39d
DE		 1021 { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
1022 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF },
1023 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, COND_REF },
1024 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1025 { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
390bd87d
DE		 1026 { 0 }
1027};
1028
b2ddf0c4 1029/* start-sanitize-m32rx */
1294c286 1030static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
5730d39d
DE		 1031 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
1032 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 1033 { 0 }
1034};
1035
b2ddf0c4
NC		 1036/* end-sanitize-m32rx */
1037/* start-sanitize-m32rx */
1294c286 1038static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
5730d39d
DE		 1039 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
1040 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF },
1041 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
ab0bd049
DE		 1042 { 0 }
1043};
1044
b2ddf0c4
NC		 1045/* end-sanitize-m32rx */
1046/* start-sanitize-m32rx */
1294c286 1047static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
5730d39d
DE		 1048 { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
1049 { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
1050 { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
ab0bd049
DE		 1051 { 0 }
1052};
1053
b2ddf0c4
NC		 1054/* end-sanitize-m32rx */
1055/* start-sanitize-m32rx */
1294c286 1056static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
5730d39d
DE		 1057 { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
1058 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1059 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
1060 { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
ab0bd049
DE		 1061 { 0 }
1062};
1063
b2ddf0c4
NC		 1064/* end-sanitize-m32rx */
1065/* start-sanitize-m32rx */
1294c286 1066static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
5730d39d
DE		 1067 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1068 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
1069 { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
390bd87d
DE		 1070 { 0 }
1071};
1072
b2ddf0c4
NC		 1073/* end-sanitize-m32rx */
1074/* start-sanitize-m32rx */
1294c286 1075static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
5730d39d 1076 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
ab0bd049
DE		 1077 { 0 }
1078};
1079
b2ddf0c4 1080/* end-sanitize-m32rx */
7caa7497
DE		 1081#undef INPUT
1082#undef OUTPUT
5730d39d
DE		 1083#undef COND_REF
1084
1085/* Instruction formats. */
1086
1087#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
1088
1089static const CGEN_IFMT fmt_empty = {
1090 0, 0, 0x0, { 0 }
1091};
1092
1093static const CGEN_IFMT fmt_add = {
1094 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1095};
1096
1097static const CGEN_IFMT fmt_add3 = {
1098 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1099};
1100
1101static const CGEN_IFMT fmt_and3 = {
1102 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1103};
1104
1105static const CGEN_IFMT fmt_or3 = {
1106 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1107};
1108
1109static const CGEN_IFMT fmt_addi = {
1110 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
1111};
1112
1113static const CGEN_IFMT fmt_addv = {
1114 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1115};
1116
1117static const CGEN_IFMT fmt_addv3 = {
1118 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1119};
1120
1121static const CGEN_IFMT fmt_addx = {
1122 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1123};
1124
1125static const CGEN_IFMT fmt_bc8 = {
1126 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1127};
1128
1129static const CGEN_IFMT fmt_bc24 = {
1130 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1131};
1132
1133static const CGEN_IFMT fmt_beq = {
1134 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
1135};
1136
1137static const CGEN_IFMT fmt_beqz = {
1138 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
1139};
1140
1141static const CGEN_IFMT fmt_bl8 = {
1142 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1143};
1144
1145static const CGEN_IFMT fmt_bl24 = {
1146 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1147};
1148
1149/* start-sanitize-m32rx */
1150static const CGEN_IFMT fmt_bcl8 = {
1151 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1152};
1153
1154/* end-sanitize-m32rx */
1155/* start-sanitize-m32rx */
1156static const CGEN_IFMT fmt_bcl24 = {
1157 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1158};
1159
1160/* end-sanitize-m32rx */
1161static const CGEN_IFMT fmt_bra8 = {
1162 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1163};
1164
1165static const CGEN_IFMT fmt_bra24 = {
1166 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1167};
1168
1169static const CGEN_IFMT fmt_cmp = {
1170 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1171};
1172
1173static const CGEN_IFMT fmt_cmpi = {
1174 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1175};
1176
1177/* start-sanitize-m32rx */
1178static const CGEN_IFMT fmt_cmpz = {
1179 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1180};
1181
1182/* end-sanitize-m32rx */
1183static const CGEN_IFMT fmt_div = {
1184 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1185};
1186
1187/* start-sanitize-m32rx */
1188static const CGEN_IFMT fmt_jc = {
1189 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1190};
1191
1192/* end-sanitize-m32rx */
1193static const CGEN_IFMT fmt_jl = {
1194 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1195};
1196
1197static const CGEN_IFMT fmt_jmp = {
1198 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1199};
1200
1201static const CGEN_IFMT fmt_ld = {
1202 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1203};
1204
1205static const CGEN_IFMT fmt_ld_d = {
1206 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1207};
1208
1209static const CGEN_IFMT fmt_ldb = {
1210 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1211};
1212
1213static const CGEN_IFMT fmt_ldb_d = {
1214 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1215};
1216
1217static const CGEN_IFMT fmt_ldh = {
1218 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1219};
1220
1221static const CGEN_IFMT fmt_ldh_d = {
1222 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1223};
1224
1225static const CGEN_IFMT fmt_ld_plus = {
1226 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1227};
1228
1229static const CGEN_IFMT fmt_ld24 = {
1230 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 }
1231};
1232
1233static const CGEN_IFMT fmt_ldi8 = {
1234 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
1235};
1236
1237static const CGEN_IFMT fmt_ldi16 = {
1238 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1239};
1240
1241static const CGEN_IFMT fmt_lock = {
1242 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1243};
1244
1245static const CGEN_IFMT fmt_machi = {
1246 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1247};
1248
1249/* start-sanitize-m32rx */
1250static const CGEN_IFMT fmt_machi_a = {
1251 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
1252};
1253
1254/* end-sanitize-m32rx */
1255static const CGEN_IFMT fmt_mulhi = {
1256 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1257};
1258
1259/* start-sanitize-m32rx */
1260static const CGEN_IFMT fmt_mulhi_a = {
1261 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
1262};
1263
1264/* end-sanitize-m32rx */
1265static const CGEN_IFMT fmt_mv = {
1266 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1267};
1268
1269static const CGEN_IFMT fmt_mvfachi = {
1270 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1271};
1272
1273/* start-sanitize-m32rx */
1274static const CGEN_IFMT fmt_mvfachi_a = {
1275 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
1276};
1277
1278/* end-sanitize-m32rx */
1279static const CGEN_IFMT fmt_mvfc = {
1280 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1281};
1282
1283static const CGEN_IFMT fmt_mvtachi = {
1284 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1285};
1286
1287/* start-sanitize-m32rx */
1288static const CGEN_IFMT fmt_mvtachi_a = {
1289 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
1290};
1291
1292/* end-sanitize-m32rx */
1293static const CGEN_IFMT fmt_mvtc = {
1294 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1295};
1296
1297static const CGEN_IFMT fmt_nop = {
1298 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1299};
1300
1301static const CGEN_IFMT fmt_rac = {
1302 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1303};
1304
1305/* start-sanitize-m32rx */
1306static const CGEN_IFMT fmt_rac_dsi = {
1307 16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
1308};
1309
1310/* end-sanitize-m32rx */
1311static const CGEN_IFMT fmt_rte = {
1312 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1313};
1314
1315static const CGEN_IFMT fmt_seth = {
1316 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 }
1317};
1318
1319static const CGEN_IFMT fmt_sll3 = {
1320 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1321};
1322
1323static const CGEN_IFMT fmt_slli = {
1324 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 }
1325};
1326
1327static const CGEN_IFMT fmt_st = {
1328 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1329};
1330
1331static const CGEN_IFMT fmt_st_d = {
1332 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1333};
1334
1335static const CGEN_IFMT fmt_stb = {
1336 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1337};
1338
1339static const CGEN_IFMT fmt_stb_d = {
1340 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1341};
1342
1343static const CGEN_IFMT fmt_sth = {
1344 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1345};
1346
1347static const CGEN_IFMT fmt_sth_d = {
1348 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1349};
1350
1351static const CGEN_IFMT fmt_st_plus = {
1352 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1353};
1354
1355static const CGEN_IFMT fmt_trap = {
1356 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 }
1357};
1358
1359static const CGEN_IFMT fmt_unlock = {
1360 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1361};
1362
1363/* start-sanitize-m32rx */
1364static const CGEN_IFMT fmt_satb = {
1365 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1366};
1367
1368/* end-sanitize-m32rx */
1369/* start-sanitize-m32rx */
1370static const CGEN_IFMT fmt_sat = {
1371 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1372};
1373
1374/* end-sanitize-m32rx */
1375/* start-sanitize-m32rx */
1376static const CGEN_IFMT fmt_sadd = {
1377 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1378};
1379
1380/* end-sanitize-m32rx */
1381/* start-sanitize-m32rx */
1382static const CGEN_IFMT fmt_macwu1 = {
1383 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1384};
1385
1386/* end-sanitize-m32rx */
1387/* start-sanitize-m32rx */
1388static const CGEN_IFMT fmt_mulwu1 = {
1389 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1390};
1391
1392/* end-sanitize-m32rx */
1393/* start-sanitize-m32rx */
1394static const CGEN_IFMT fmt_sc = {
1395 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1396};
1397
1398/* end-sanitize-m32rx */
1399#undef F
7caa7497 1400
0bf55db8 1401#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
8d157f96
DE		 1402#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1403#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
23cf992f 1404
1294c286
DE		 1405/* The instruction table.
1406 This is currently non-static because the simulator accesses it
1407 directly. */
ab0bd049 1408
7c26196f 1409const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
5d07b6cf 1410{
1294c286 1411 /* Special null first entry.
52a53d1f
DE		 1412 A `num' value of zero is thus invalid.
1413 Also, the special `invalid' insn resides here. */
23cf992f 1414 { { 0 }, 0 },
9c03036a
DE		 1415/* add $dr,$sr */
1416 {
23cf992f 1417 { 1, 1, 1, 1 },
1294c286 1418 M32R_INSN_ADD, "add", "add",
2e6dfccc 1419 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1420 & fmt_add, { 0xa0 },
1294c286 1421 (PTR) & fmt_add_ops[0],
52a53d1f 1422 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a 1423 },
a6cefe4f 1424/* add3 $dr,$sr,$hash$slo16 */
9c03036a 1425 {
23cf992f 1426 { 1, 1, 1, 1 },
1294c286 1427 M32R_INSN_ADD3, "add3", "add3",
2e6dfccc 1428 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
5730d39d 1429 & fmt_add3, { 0x80a00000 },
1294c286 1430 (PTR) & fmt_add3_ops[0],
52a53d1f 1431 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
7c26196f 1432 },
9c03036a
DE		 1433/* and $dr,$sr */
1434 {
23cf992f 1435 { 1, 1, 1, 1 },
1294c286 1436 M32R_INSN_AND, "and", "and",
2e6dfccc 1437 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1438 & fmt_add, { 0xc0 },
1294c286 1439 (PTR) & fmt_add_ops[0],
52a53d1f 1440 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1441 },
9c03036a
DE		 1442/* and3 $dr,$sr,$uimm16 */
1443 {
23cf992f 1444 { 1, 1, 1, 1 },
1294c286 1445 M32R_INSN_AND3, "and3", "and3",
2e6dfccc 1446 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
5730d39d 1447 & fmt_and3, { 0x80c00000 },
1294c286 1448 (PTR) & fmt_and3_ops[0],
52a53d1f 1449 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1450 },
1451/* or $dr,$sr */
1452 {
23cf992f 1453 { 1, 1, 1, 1 },
1294c286 1454 M32R_INSN_OR, "or", "or",
2e6dfccc 1455 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1456 & fmt_add, { 0xe0 },
1294c286 1457 (PTR) & fmt_add_ops[0],
52a53d1f 1458 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1459 },
a6cefe4f 1460/* or3 $dr,$sr,$hash$ulo16 */
7c26196f
DE		 1461 {
1462 { 1, 1, 1, 1 },
1294c286 1463 M32R_INSN_OR3, "or3", "or3",
2e6dfccc 1464 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
5730d39d 1465 & fmt_or3, { 0x80e00000 },
1294c286 1466 (PTR) & fmt_or3_ops[0],
52a53d1f 1467 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1468 },
9c03036a
DE		 1469/* xor $dr,$sr */
1470 {
23cf992f 1471 { 1, 1, 1, 1 },
1294c286 1472 M32R_INSN_XOR, "xor", "xor",
2e6dfccc 1473 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1474 & fmt_add, { 0xd0 },
1294c286 1475 (PTR) & fmt_add_ops[0],
52a53d1f 1476 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1477 },
9c03036a
DE		 1478/* xor3 $dr,$sr,$uimm16 */
1479 {
23cf992f 1480 { 1, 1, 1, 1 },
1294c286 1481 M32R_INSN_XOR3, "xor3", "xor3",
2e6dfccc 1482 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
5730d39d 1483 & fmt_and3, { 0x80d00000 },
1294c286 1484 (PTR) & fmt_and3_ops[0],
52a53d1f 1485 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1486 },
1487/* addi $dr,$simm8 */
1488 {
23cf992f 1489 { 1, 1, 1, 1 },
1294c286 1490 M32R_INSN_ADDI, "addi", "addi",
2e6dfccc 1491 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
5730d39d 1492 & fmt_addi, { 0x4000 },
1294c286 1493 (PTR) & fmt_addi_ops[0],
52a53d1f 1494 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 1495 },
1496/* addv $dr,$sr */
1497 {
23cf992f 1498 { 1, 1, 1, 1 },
1294c286 1499 M32R_INSN_ADDV, "addv", "addv",
2e6dfccc 1500 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1501 & fmt_addv, { 0x80 },
1294c286 1502 (PTR) & fmt_addv_ops[0],
52a53d1f 1503 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1504 },
9c03036a
DE		 1505/* addv3 $dr,$sr,$simm16 */
1506 {
23cf992f 1507 { 1, 1, 1, 1 },
1294c286 1508 M32R_INSN_ADDV3, "addv3", "addv3",
2e6dfccc 1509 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
5730d39d 1510 & fmt_addv3, { 0x80800000 },
1294c286 1511 (PTR) & fmt_addv3_ops[0],
52a53d1f 1512 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1513 },
1514/* addx $dr,$sr */
1515 {
23cf992f 1516 { 1, 1, 1, 1 },
1294c286 1517 M32R_INSN_ADDX, "addx", "addx",
2e6dfccc 1518 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1519 & fmt_addx, { 0x90 },
1294c286 1520 (PTR) & fmt_addx_ops[0],
52a53d1f 1521 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a 1522 },
9c03036a
DE		 1523/* bc.s $disp8 */
1524 {
23cf992f 1525 { 1, 1, 1, 1 },
1294c286 1526 M32R_INSN_BC8, "bc8", "bc.s",
2e6dfccc 1527 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 1528 & fmt_bc8, { 0x7c00 },
1294c286 1529 (PTR) & fmt_bc8_ops[0],
52a53d1f 1530 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1531 },
1532/* bc.l $disp24 */
1533 {
23cf992f 1534 { 1, 1, 1, 1 },
1294c286 1535 M32R_INSN_BC24, "bc24", "bc.l",
2e6dfccc 1536 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 1537 & fmt_bc24, { 0xfc000000 },
1294c286 1538 (PTR) & fmt_bc24_ops[0],
52a53d1f 1539 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1540 },
1541/* beq $src1,$src2,$disp16 */
1542 {
23cf992f 1543 { 1, 1, 1, 1 },
1294c286 1544 M32R_INSN_BEQ, "beq", "beq",
2e6dfccc 1545 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1546 & fmt_beq, { 0xb0000000 },
1294c286 1547 (PTR) & fmt_beq_ops[0],
52a53d1f 1548 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1549 },
1550/* beqz $src2,$disp16 */
1551 {
23cf992f 1552 { 1, 1, 1, 1 },
1294c286 1553 M32R_INSN_BEQZ, "beqz", "beqz",
2e6dfccc 1554 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1555 & fmt_beqz, { 0xb0800000 },
1294c286 1556 (PTR) & fmt_beqz_ops[0],
52a53d1f 1557 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1558 },
1559/* bgez $src2,$disp16 */
1560 {
23cf992f 1561 { 1, 1, 1, 1 },
1294c286 1562 M32R_INSN_BGEZ, "bgez", "bgez",
2e6dfccc 1563 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1564 & fmt_beqz, { 0xb0b00000 },
1294c286 1565 (PTR) & fmt_beqz_ops[0],
52a53d1f 1566 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1567 },
1568/* bgtz $src2,$disp16 */
1569 {
23cf992f 1570 { 1, 1, 1, 1 },
1294c286 1571 M32R_INSN_BGTZ, "bgtz", "bgtz",
2e6dfccc 1572 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1573 & fmt_beqz, { 0xb0d00000 },
1294c286 1574 (PTR) & fmt_beqz_ops[0],
52a53d1f 1575 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1576 },
1577/* blez $src2,$disp16 */
1578 {
23cf992f 1579 { 1, 1, 1, 1 },
1294c286 1580 M32R_INSN_BLEZ, "blez", "blez",
2e6dfccc 1581 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1582 & fmt_beqz, { 0xb0c00000 },
1294c286 1583 (PTR) & fmt_beqz_ops[0],
52a53d1f 1584 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1585 },
1586/* bltz $src2,$disp16 */
1587 {
23cf992f 1588 { 1, 1, 1, 1 },
1294c286 1589 M32R_INSN_BLTZ, "bltz", "bltz",
2e6dfccc 1590 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1591 & fmt_beqz, { 0xb0a00000 },
1294c286 1592 (PTR) & fmt_beqz_ops[0],
52a53d1f 1593 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1594 },
1595/* bnez $src2,$disp16 */
1596 {
23cf992f 1597 { 1, 1, 1, 1 },
1294c286 1598 M32R_INSN_BNEZ, "bnez", "bnez",
2e6dfccc 1599 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1600 & fmt_beqz, { 0xb0900000 },
1294c286 1601 (PTR) & fmt_beqz_ops[0],
52a53d1f 1602 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1603 },
9c03036a
DE		 1604/* bl.s $disp8 */
1605 {
23cf992f 1606 { 1, 1, 1, 1 },
1294c286 1607 M32R_INSN_BL8, "bl8", "bl.s",
2e6dfccc 1608 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 1609 & fmt_bl8, { 0x7e00 },
1294c286 1610 (PTR) & fmt_bl8_ops[0],
52a53d1f 1611 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1612 },
1613/* bl.l $disp24 */
1614 {
23cf992f 1615 { 1, 1, 1, 1 },
1294c286 1616 M32R_INSN_BL24, "bl24", "bl.l",
2e6dfccc 1617 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 1618 & fmt_bl24, { 0xfe000000 },
1294c286 1619 (PTR) & fmt_bl24_ops[0],
52a53d1f 1620 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
7c26196f 1621 },
7c26196f
DE		 1622/* start-sanitize-m32rx */
1623/* bcl.s $disp8 */
1624 {
1625 { 1, 1, 1, 1 },
1294c286 1626 M32R_INSN_BCL8, "bcl8", "bcl.s",
2e6dfccc 1627 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 1628 & fmt_bcl8, { 0x7800 },
1294c286 1629 (PTR) & fmt_bcl8_ops[0],
52a53d1f 1630 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1631 },
1632/* end-sanitize-m32rx */
1633/* start-sanitize-m32rx */
1634/* bcl.l $disp24 */
1635 {
1636 { 1, 1, 1, 1 },
1294c286 1637 M32R_INSN_BCL24, "bcl24", "bcl.l",
2e6dfccc 1638 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 1639 & fmt_bcl24, { 0xf8000000 },
1294c286
DE		 1640 (PTR) & fmt_bcl24_ops[0],
1641 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
9c03036a 1642 },
7c26196f 1643/* end-sanitize-m32rx */
9c03036a
DE		 1644/* bnc.s $disp8 */
1645 {
23cf992f 1646 { 1, 1, 1, 1 },
1294c286 1647 M32R_INSN_BNC8, "bnc8", "bnc.s",
2e6dfccc 1648 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 1649 & fmt_bc8, { 0x7d00 },
1294c286 1650 (PTR) & fmt_bc8_ops[0],
52a53d1f 1651 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1652 },
1653/* bnc.l $disp24 */
1654 {
23cf992f 1655 { 1, 1, 1, 1 },
1294c286 1656 M32R_INSN_BNC24, "bnc24", "bnc.l",
2e6dfccc 1657 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 1658 & fmt_bc24, { 0xfd000000 },
1294c286 1659 (PTR) & fmt_bc24_ops[0],
52a53d1f 1660 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1661 },
1662/* bne $src1,$src2,$disp16 */
1663 {
23cf992f 1664 { 1, 1, 1, 1 },
1294c286 1665 M32R_INSN_BNE, "bne", "bne",
2e6dfccc 1666 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
5730d39d 1667 & fmt_beq, { 0xb0100000 },
1294c286 1668 (PTR) & fmt_beq_ops[0],
52a53d1f 1669 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1670 },
9c03036a
DE		 1671/* bra.s $disp8 */
1672 {
23cf992f 1673 { 1, 1, 1, 1 },
1294c286 1674 M32R_INSN_BRA8, "bra8", "bra.s",
2e6dfccc 1675 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 1676 & fmt_bra8, { 0x7f00 },
1294c286 1677 (PTR) & fmt_bra8_ops[0],
52a53d1f 1678 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1679 },
1680/* bra.l $disp24 */
1681 {
23cf992f 1682 { 1, 1, 1, 1 },
1294c286 1683 M32R_INSN_BRA24, "bra24", "bra.l",
2e6dfccc 1684 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 1685 & fmt_bra24, { 0xff000000 },
1294c286 1686 (PTR) & fmt_bra24_ops[0],
52a53d1f 1687 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
7c26196f
DE		 1688 },
1689/* start-sanitize-m32rx */
7c26196f
DE		 1690/* bncl.s $disp8 */
1691 {
1692 { 1, 1, 1, 1 },
1294c286 1693 M32R_INSN_BNCL8, "bncl8", "bncl.s",
2e6dfccc 1694 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 1695 & fmt_bcl8, { 0x7900 },
1294c286 1696 (PTR) & fmt_bcl8_ops[0],
52a53d1f 1697 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1698 },
1699/* end-sanitize-m32rx */
1700/* start-sanitize-m32rx */
1701/* bncl.l $disp24 */
1702 {
1703 { 1, 1, 1, 1 },
1294c286 1704 M32R_INSN_BNCL24, "bncl24", "bncl.l",
2e6dfccc 1705 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 1706 & fmt_bcl24, { 0xf9000000 },
1294c286
DE		 1707 (PTR) & fmt_bcl24_ops[0],
1708 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 1709 },
1710/* end-sanitize-m32rx */
9c03036a
DE		 1711/* cmp $src1,$src2 */
1712 {
23cf992f 1713 { 1, 1, 1, 1 },
1294c286 1714 M32R_INSN_CMP, "cmp", "cmp",
2e6dfccc 1715 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 1716 & fmt_cmp, { 0x40 },
1294c286 1717 (PTR) & fmt_cmp_ops[0],
52a53d1f 1718 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1719 },
9c03036a
DE		 1720/* cmpi $src2,$simm16 */
1721 {
23cf992f 1722 { 1, 1, 1, 1 },
1294c286 1723 M32R_INSN_CMPI, "cmpi", "cmpi",
2e6dfccc 1724 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
5730d39d 1725 & fmt_cmpi, { 0x80400000 },
1294c286 1726 (PTR) & fmt_cmpi_ops[0],
52a53d1f 1727 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1728 },
1729/* cmpu $src1,$src2 */
1730 {
23cf992f 1731 { 1, 1, 1, 1 },
1294c286 1732 M32R_INSN_CMPU, "cmpu", "cmpu",
2e6dfccc 1733 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 1734 & fmt_cmp, { 0x50 },
1294c286 1735 (PTR) & fmt_cmp_ops[0],
52a53d1f 1736 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1737 },
1294c286 1738/* cmpui $src2,$simm16 */
23cf992f
NC		 1739 {
1740 { 1, 1, 1, 1 },
1294c286 1741 M32R_INSN_CMPUI, "cmpui", "cmpui",
2e6dfccc 1742 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
5730d39d 1743 & fmt_cmpi, { 0x80500000 },
1294c286 1744 (PTR) & fmt_cmpi_ops[0],
52a53d1f 1745 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
7c26196f
DE		 1746 },
1747/* start-sanitize-m32rx */
1748/* cmpeq $src1,$src2 */
1749 {
1750 { 1, 1, 1, 1 },
1294c286 1751 M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
2e6dfccc 1752 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 1753 & fmt_cmp, { 0x60 },
1294c286 1754 (PTR) & fmt_cmp_ops[0],
8d157f96 1755 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 1756 },
1757/* end-sanitize-m32rx */
1758/* start-sanitize-m32rx */
1759/* cmpz $src2 */
1760 {
1761 { 1, 1, 1, 1 },
1294c286 1762 M32R_INSN_CMPZ, "cmpz", "cmpz",
2e6dfccc 1763 { { MNEM, ' ', OP (SRC2), 0 } },
5730d39d 1764 & fmt_cmpz, { 0x70 },
1294c286 1765 (PTR) & fmt_cmpz_ops[0],
8d157f96 1766 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
9c03036a 1767 },
7c26196f 1768/* end-sanitize-m32rx */
9c03036a
DE		 1769/* div $dr,$sr */
1770 {
23cf992f 1771 { 1, 1, 1, 1 },
1294c286 1772 M32R_INSN_DIV, "div", "div",
2e6dfccc 1773 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1774 & fmt_div, { 0x90000000 },
1294c286 1775 (PTR) & fmt_div_ops[0],
52a53d1f 1776 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1777 },
1778/* divu $dr,$sr */
1779 {
23cf992f 1780 { 1, 1, 1, 1 },
1294c286 1781 M32R_INSN_DIVU, "divu", "divu",
2e6dfccc 1782 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1783 & fmt_div, { 0x90100000 },
1294c286 1784 (PTR) & fmt_div_ops[0],
52a53d1f 1785 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1786 },
1787/* rem $dr,$sr */
1788 {
23cf992f 1789 { 1, 1, 1, 1 },
1294c286 1790 M32R_INSN_REM, "rem", "rem",
2e6dfccc 1791 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1792 & fmt_div, { 0x90200000 },
1294c286 1793 (PTR) & fmt_div_ops[0],
52a53d1f 1794 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1795 },
1796/* remu $dr,$sr */
1797 {
23cf992f 1798 { 1, 1, 1, 1 },
1294c286 1799 M32R_INSN_REMU, "remu", "remu",
2e6dfccc 1800 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1801 & fmt_div, { 0x90300000 },
1294c286 1802 (PTR) & fmt_div_ops[0],
52a53d1f 1803 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
ab0bd049
DE		 1804 },
1805/* start-sanitize-m32rx */
1806/* divh $dr,$sr */
1807 {
1808 { 1, 1, 1, 1 },
1294c286 1809 M32R_INSN_DIVH, "divh", "divh",
2e6dfccc 1810 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 1811 & fmt_div, { 0x90000010 },
1294c286 1812 (PTR) & fmt_div_ops[0],
8d157f96 1813 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f 1814 },
ab0bd049 1815/* end-sanitize-m32rx */
7c26196f
DE		 1816/* start-sanitize-m32rx */
1817/* jc $sr */
1818 {
1819 { 1, 1, 1, 1 },
1294c286 1820 M32R_INSN_JC, "jc", "jc",
2e6dfccc 1821 { { MNEM, ' ', OP (SR), 0 } },
5730d39d 1822 & fmt_jc, { 0x1cc0 },
1294c286 1823 (PTR) & fmt_jc_ops[0],
fbc8134d 1824 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1825 },
1826/* end-sanitize-m32rx */
1827/* start-sanitize-m32rx */
1828/* jnc $sr */
1829 {
1830 { 1, 1, 1, 1 },
1294c286 1831 M32R_INSN_JNC, "jnc", "jnc",
2e6dfccc 1832 { { MNEM, ' ', OP (SR), 0 } },
5730d39d 1833 & fmt_jc, { 0x1dc0 },
1294c286 1834 (PTR) & fmt_jc_ops[0],
fbc8134d 1835 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
9c03036a 1836 },
7c26196f 1837/* end-sanitize-m32rx */
9c03036a
DE		 1838/* jl $sr */
1839 {
23cf992f 1840 { 1, 1, 1, 1 },
1294c286 1841 M32R_INSN_JL, "jl", "jl",
2e6dfccc 1842 { { MNEM, ' ', OP (SR), 0 } },
5730d39d 1843 & fmt_jl, { 0x1ec0 },
1294c286 1844 (PTR) & fmt_jl_ops[0],
52a53d1f 1845 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1846 },
1847/* jmp $sr */
1848 {
23cf992f 1849 { 1, 1, 1, 1 },
1294c286 1850 M32R_INSN_JMP, "jmp", "jmp",
2e6dfccc 1851 { { MNEM, ' ', OP (SR), 0 } },
5730d39d 1852 & fmt_jmp, { 0x1fc0 },
1294c286 1853 (PTR) & fmt_jmp_ops[0],
52a53d1f 1854 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1855 },
1856/* ld $dr,@$sr */
1857 {
23cf992f 1858 { 1, 1, 1, 1 },
1294c286 1859 M32R_INSN_LD, "ld", "ld",
2e6dfccc 1860 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
5730d39d 1861 & fmt_ld, { 0x20c0 },
1294c286 1862 (PTR) & fmt_ld_ops[0],
52a53d1f 1863 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1864 },
9c03036a
DE		 1865/* ld $dr,@($slo16,$sr) */
1866 {
23cf992f 1867 { 1, 1, 1, 1 },
1294c286 1868 M32R_INSN_LD_D, "ld-d", "ld",
2e6dfccc 1869 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
5730d39d 1870 & fmt_ld_d, { 0xa0c00000 },
1294c286 1871 (PTR) & fmt_ld_d_ops[0],
52a53d1f 1872 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1873 },
9c03036a
DE		 1874/* ldb $dr,@$sr */
1875 {
23cf992f 1876 { 1, 1, 1, 1 },
1294c286 1877 M32R_INSN_LDB, "ldb", "ldb",
2e6dfccc 1878 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
5730d39d 1879 & fmt_ldb, { 0x2080 },
1294c286 1880 (PTR) & fmt_ldb_ops[0],
52a53d1f 1881 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1882 },
9c03036a
DE		 1883/* ldb $dr,@($slo16,$sr) */
1884 {
23cf992f 1885 { 1, 1, 1, 1 },
1294c286 1886 M32R_INSN_LDB_D, "ldb-d", "ldb",
2e6dfccc 1887 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
5730d39d 1888 & fmt_ldb_d, { 0xa0800000 },
1294c286 1889 (PTR) & fmt_ldb_d_ops[0],
52a53d1f 1890 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1891 },
9c03036a
DE		 1892/* ldh $dr,@$sr */
1893 {
23cf992f 1894 { 1, 1, 1, 1 },
1294c286 1895 M32R_INSN_LDH, "ldh", "ldh",
2e6dfccc 1896 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
5730d39d 1897 & fmt_ldh, { 0x20a0 },
1294c286 1898 (PTR) & fmt_ldh_ops[0],
52a53d1f 1899 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1900 },
9c03036a
DE		 1901/* ldh $dr,@($slo16,$sr) */
1902 {
23cf992f 1903 { 1, 1, 1, 1 },
1294c286 1904 M32R_INSN_LDH_D, "ldh-d", "ldh",
2e6dfccc 1905 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
5730d39d 1906 & fmt_ldh_d, { 0xa0a00000 },
1294c286 1907 (PTR) & fmt_ldh_d_ops[0],
52a53d1f 1908 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1909 },
9c03036a
DE		 1910/* ldub $dr,@$sr */
1911 {
23cf992f 1912 { 1, 1, 1, 1 },
1294c286 1913 M32R_INSN_LDUB, "ldub", "ldub",
2e6dfccc 1914 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
5730d39d 1915 & fmt_ldb, { 0x2090 },
1294c286 1916 (PTR) & fmt_ldb_ops[0],
52a53d1f 1917 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1918 },
9c03036a
DE		 1919/* ldub $dr,@($slo16,$sr) */
1920 {
23cf992f 1921 { 1, 1, 1, 1 },
1294c286 1922 M32R_INSN_LDUB_D, "ldub-d", "ldub",
2e6dfccc 1923 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
5730d39d 1924 & fmt_ldb_d, { 0xa0900000 },
1294c286 1925 (PTR) & fmt_ldb_d_ops[0],
52a53d1f 1926 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1927 },
9c03036a
DE		 1928/* lduh $dr,@$sr */
1929 {
23cf992f 1930 { 1, 1, 1, 1 },
1294c286 1931 M32R_INSN_LDUH, "lduh", "lduh",
2e6dfccc 1932 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
5730d39d 1933 & fmt_ldh, { 0x20b0 },
1294c286 1934 (PTR) & fmt_ldh_ops[0],
52a53d1f 1935 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1936 },
9c03036a
DE		 1937/* lduh $dr,@($slo16,$sr) */
1938 {
23cf992f 1939 { 1, 1, 1, 1 },
1294c286 1940 M32R_INSN_LDUH_D, "lduh-d", "lduh",
2e6dfccc 1941 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
5730d39d 1942 & fmt_ldh_d, { 0xa0b00000 },
1294c286 1943 (PTR) & fmt_ldh_d_ops[0],
52a53d1f 1944 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1945 },
9c03036a
DE		 1946/* ld $dr,@$sr+ */
1947 {
23cf992f 1948 { 1, 1, 1, 1 },
1294c286 1949 M32R_INSN_LD_PLUS, "ld-plus", "ld",
2e6dfccc 1950 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
5730d39d 1951 & fmt_ld_plus, { 0x20e0 },
1294c286 1952 (PTR) & fmt_ld_plus_ops[0],
52a53d1f 1953 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 1954 },
9c03036a
DE		 1955/* ld24 $dr,$uimm24 */
1956 {
23cf992f 1957 { 1, 1, 1, 1 },
1294c286 1958 M32R_INSN_LD24, "ld24", "ld24",
2e6dfccc 1959 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
5730d39d 1960 & fmt_ld24, { 0xe0000000 },
1294c286 1961 (PTR) & fmt_ld24_ops[0],
52a53d1f 1962 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1963 },
9c03036a
DE		 1964/* ldi8 $dr,$simm8 */
1965 {
23cf992f 1966 { 1, 1, 1, 1 },
1294c286 1967 M32R_INSN_LDI8, "ldi8", "ldi8",
2e6dfccc 1968 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
5730d39d 1969 & fmt_ldi8, { 0x6000 },
1294c286 1970 (PTR) & fmt_ldi8_ops[0],
52a53d1f 1971 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a 1972 },
a6cefe4f 1973/* ldi16 $dr,$hash$slo16 */
9c03036a 1974 {
23cf992f 1975 { 1, 1, 1, 1 },
1294c286 1976 M32R_INSN_LDI16, "ldi16", "ldi16",
2e6dfccc 1977 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
5730d39d 1978 & fmt_ldi16, { 0x90f00000 },
1294c286 1979 (PTR) & fmt_ldi16_ops[0],
52a53d1f 1980 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1981 },
1982/* lock $dr,@$sr */
1983 {
23cf992f 1984 { 1, 1, 1, 1 },
1294c286 1985 M32R_INSN_LOCK, "lock", "lock",
2e6dfccc 1986 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
5730d39d 1987 & fmt_lock, { 0x20d0 },
1294c286 1988 (PTR) & fmt_lock_ops[0],
52a53d1f 1989 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1990 },
1991/* machi $src1,$src2 */
1992 {
23cf992f 1993 { 1, 1, 1, 1 },
1294c286 1994 M32R_INSN_MACHI, "machi", "machi",
2e6dfccc 1995 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 1996 & fmt_machi, { 0x3040 },
1294c286 1997 (PTR) & fmt_machi_ops[0],
8d157f96 1998 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1999 },
2000/* start-sanitize-m32rx */
2001/* machi $src1,$src2,$acc */
2002 {
2003 { 1, 1, 1, 1 },
1294c286 2004 M32R_INSN_MACHI_A, "machi-a", "machi",
2e6dfccc 2005 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2006 & fmt_machi_a, { 0x3040 },
1294c286 2007 (PTR) & fmt_machi_a_ops[0],
8d157f96 2008 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2009 },
7c26196f 2010/* end-sanitize-m32rx */
9c03036a
DE		 2011/* maclo $src1,$src2 */
2012 {
23cf992f 2013 { 1, 1, 1, 1 },
1294c286 2014 M32R_INSN_MACLO, "maclo", "maclo",
2e6dfccc 2015 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2016 & fmt_machi, { 0x3050 },
1294c286 2017 (PTR) & fmt_machi_ops[0],
8d157f96 2018 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2019 },
7c26196f
DE		 2020/* start-sanitize-m32rx */
2021/* maclo $src1,$src2,$acc */
2022 {
2023 { 1, 1, 1, 1 },
1294c286 2024 M32R_INSN_MACLO_A, "maclo-a", "maclo",
2e6dfccc 2025 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2026 & fmt_machi_a, { 0x3050 },
1294c286 2027 (PTR) & fmt_machi_a_ops[0],
8d157f96 2028 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2029 },
2030/* end-sanitize-m32rx */
9c03036a
DE		 2031/* macwhi $src1,$src2 */
2032 {
23cf992f 2033 { 1, 1, 1, 1 },
1294c286 2034 M32R_INSN_MACWHI, "macwhi", "macwhi",
2e6dfccc 2035 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2036 & fmt_machi, { 0x3060 },
1294c286 2037 (PTR) & fmt_machi_ops[0],
8d157f96 2038 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2039 },
c2009f4a
DE		 2040/* start-sanitize-m32rx */
2041/* macwhi $src1,$src2,$acc */
2042 {
2043 { 1, 1, 1, 1 },
2044 M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
2045 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2046 & fmt_machi_a, { 0x3060 },
c2009f4a
DE		 2047 (PTR) & fmt_machi_a_ops[0],
2048 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2049 },
2050/* end-sanitize-m32rx */
9c03036a
DE		 2051/* macwlo $src1,$src2 */
2052 {
23cf992f 2053 { 1, 1, 1, 1 },
1294c286 2054 M32R_INSN_MACWLO, "macwlo", "macwlo",
2e6dfccc 2055 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2056 & fmt_machi, { 0x3070 },
1294c286 2057 (PTR) & fmt_machi_ops[0],
8d157f96 2058 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2059 },
c2009f4a
DE		 2060/* start-sanitize-m32rx */
2061/* macwlo $src1,$src2,$acc */
2062 {
2063 { 1, 1, 1, 1 },
2064 M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
2065 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2066 & fmt_machi_a, { 0x3070 },
c2009f4a
DE		 2067 (PTR) & fmt_machi_a_ops[0],
2068 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2069 },
2070/* end-sanitize-m32rx */
9c03036a
DE		 2071/* mul $dr,$sr */
2072 {
23cf992f 2073 { 1, 1, 1, 1 },
1294c286 2074 M32R_INSN_MUL, "mul", "mul",
2e6dfccc 2075 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2076 & fmt_add, { 0x1060 },
1294c286 2077 (PTR) & fmt_add_ops[0],
52a53d1f 2078 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } }
9c03036a
DE		 2079 },
2080/* mulhi $src1,$src2 */
2081 {
23cf992f 2082 { 1, 1, 1, 1 },
1294c286 2083 M32R_INSN_MULHI, "mulhi", "mulhi",
2e6dfccc 2084 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2085 & fmt_mulhi, { 0x3000 },
1294c286 2086 (PTR) & fmt_mulhi_ops[0],
8d157f96 2087 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 2088 },
2089/* start-sanitize-m32rx */
2090/* mulhi $src1,$src2,$acc */
2091 {
2092 { 1, 1, 1, 1 },
1294c286 2093 M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
2e6dfccc 2094 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2095 & fmt_mulhi_a, { 0x3000 },
1294c286 2096 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 2097 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2098 },
7c26196f 2099/* end-sanitize-m32rx */
9c03036a
DE		 2100/* mullo $src1,$src2 */
2101 {
23cf992f 2102 { 1, 1, 1, 1 },
1294c286 2103 M32R_INSN_MULLO, "mullo", "mullo",
2e6dfccc 2104 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2105 & fmt_mulhi, { 0x3010 },
1294c286 2106 (PTR) & fmt_mulhi_ops[0],
8d157f96 2107 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2108 },
7c26196f
DE		 2109/* start-sanitize-m32rx */
2110/* mullo $src1,$src2,$acc */
2111 {
2112 { 1, 1, 1, 1 },
1294c286 2113 M32R_INSN_MULLO_A, "mullo-a", "mullo",
2e6dfccc 2114 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2115 & fmt_mulhi_a, { 0x3010 },
1294c286 2116 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 2117 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2118 },
2119/* end-sanitize-m32rx */
9c03036a
DE		 2120/* mulwhi $src1,$src2 */
2121 {
23cf992f 2122 { 1, 1, 1, 1 },
1294c286 2123 M32R_INSN_MULWHI, "mulwhi", "mulwhi",
2e6dfccc 2124 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2125 & fmt_mulhi, { 0x3020 },
1294c286 2126 (PTR) & fmt_mulhi_ops[0],
8d157f96 2127 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2128 },
c2009f4a
DE		 2129/* start-sanitize-m32rx */
2130/* mulwhi $src1,$src2,$acc */
2131 {
2132 { 1, 1, 1, 1 },
2133 M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
2134 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2135 & fmt_mulhi_a, { 0x3020 },
c2009f4a
DE		 2136 (PTR) & fmt_mulhi_a_ops[0],
2137 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2138 },
2139/* end-sanitize-m32rx */
9c03036a
DE		 2140/* mulwlo $src1,$src2 */
2141 {
23cf992f 2142 { 1, 1, 1, 1 },
1294c286 2143 M32R_INSN_MULWLO, "mulwlo", "mulwlo",
2e6dfccc 2144 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2145 & fmt_mulhi, { 0x3030 },
1294c286 2146 (PTR) & fmt_mulhi_ops[0],
8d157f96 2147 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2148 },
c2009f4a
DE		 2149/* start-sanitize-m32rx */
2150/* mulwlo $src1,$src2,$acc */
2151 {
2152 { 1, 1, 1, 1 },
2153 M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
2154 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
5730d39d 2155 & fmt_mulhi_a, { 0x3030 },
c2009f4a
DE		 2156 (PTR) & fmt_mulhi_a_ops[0],
2157 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2158 },
2159/* end-sanitize-m32rx */
9c03036a
DE		 2160/* mv $dr,$sr */
2161 {
23cf992f 2162 { 1, 1, 1, 1 },
1294c286 2163 M32R_INSN_MV, "mv", "mv",
2e6dfccc 2164 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2165 & fmt_mv, { 0x1080 },
1294c286 2166 (PTR) & fmt_mv_ops[0],
52a53d1f 2167 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2168 },
2169/* mvfachi $dr */
2170 {
23cf992f 2171 { 1, 1, 1, 1 },
1294c286 2172 M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
2e6dfccc 2173 { { MNEM, ' ', OP (DR), 0 } },
5730d39d 2174 & fmt_mvfachi, { 0x50f0 },
1294c286 2175 (PTR) & fmt_mvfachi_ops[0],
8d157f96 2176 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 2177 },
2178/* start-sanitize-m32rx */
2179/* mvfachi $dr,$accs */
2180 {
2181 { 1, 1, 1, 1 },
1294c286 2182 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
2e6dfccc 2183 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
5730d39d 2184 & fmt_mvfachi_a, { 0x50f0 },
1294c286 2185 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 2186 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2187 },
7c26196f 2188/* end-sanitize-m32rx */
9c03036a
DE		 2189/* mvfaclo $dr */
2190 {
23cf992f 2191 { 1, 1, 1, 1 },
1294c286 2192 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
2e6dfccc 2193 { { MNEM, ' ', OP (DR), 0 } },
5730d39d 2194 & fmt_mvfachi, { 0x50f1 },
1294c286 2195 (PTR) & fmt_mvfachi_ops[0],
8d157f96 2196 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2197 },
7c26196f
DE		 2198/* start-sanitize-m32rx */
2199/* mvfaclo $dr,$accs */
2200 {
2201 { 1, 1, 1, 1 },
1294c286 2202 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
2e6dfccc 2203 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
5730d39d 2204 & fmt_mvfachi_a, { 0x50f1 },
1294c286 2205 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 2206 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2207 },
2208/* end-sanitize-m32rx */
9c03036a
DE		 2209/* mvfacmi $dr */
2210 {
23cf992f 2211 { 1, 1, 1, 1 },
1294c286 2212 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
2e6dfccc 2213 { { MNEM, ' ', OP (DR), 0 } },
5730d39d 2214 & fmt_mvfachi, { 0x50f2 },
1294c286 2215 (PTR) & fmt_mvfachi_ops[0],
8d157f96 2216 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 2217 },
2218/* start-sanitize-m32rx */
2219/* mvfacmi $dr,$accs */
2220 {
2221 { 1, 1, 1, 1 },
1294c286 2222 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
2e6dfccc 2223 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
5730d39d 2224 & fmt_mvfachi_a, { 0x50f2 },
1294c286 2225 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 2226 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2227 },
7c26196f 2228/* end-sanitize-m32rx */
9c03036a
DE		 2229/* mvfc $dr,$scr */
2230 {
23cf992f 2231 { 1, 1, 1, 1 },
1294c286 2232 M32R_INSN_MVFC, "mvfc", "mvfc",
2e6dfccc 2233 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
5730d39d 2234 & fmt_mvfc, { 0x1090 },
1294c286 2235 (PTR) & fmt_mvfc_ops[0],
52a53d1f 2236 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2237 },
2238/* mvtachi $src1 */
2239 {
23cf992f 2240 { 1, 1, 1, 1 },
1294c286 2241 M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
2e6dfccc 2242 { { MNEM, ' ', OP (SRC1), 0 } },
5730d39d 2243 & fmt_mvtachi, { 0x5070 },
1294c286 2244 (PTR) & fmt_mvtachi_ops[0],
8d157f96 2245 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 2246 },
7c26196f
DE		 2247/* start-sanitize-m32rx */
2248/* mvtachi $src1,$accs */
2249 {
2250 { 1, 1, 1, 1 },
1294c286 2251 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
2e6dfccc 2252 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
5730d39d 2253 & fmt_mvtachi_a, { 0x5070 },
1294c286 2254 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 2255 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2256 },
2257/* end-sanitize-m32rx */
9c03036a
DE		 2258/* mvtaclo $src1 */
2259 {
23cf992f 2260 { 1, 1, 1, 1 },
1294c286 2261 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
2e6dfccc 2262 { { MNEM, ' ', OP (SRC1), 0 } },
5730d39d 2263 & fmt_mvtachi, { 0x5071 },
1294c286 2264 (PTR) & fmt_mvtachi_ops[0],
8d157f96 2265 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 2266 },
2267/* start-sanitize-m32rx */
2268/* mvtaclo $src1,$accs */
2269 {
2270 { 1, 1, 1, 1 },
1294c286 2271 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
2e6dfccc 2272 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
5730d39d 2273 & fmt_mvtachi_a, { 0x5071 },
1294c286 2274 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 2275 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2276 },
7c26196f 2277/* end-sanitize-m32rx */
9c03036a
DE		 2278/* mvtc $sr,$dcr */
2279 {
23cf992f 2280 { 1, 1, 1, 1 },
1294c286 2281 M32R_INSN_MVTC, "mvtc", "mvtc",
2e6dfccc 2282 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
5730d39d 2283 & fmt_mvtc, { 0x10a0 },
1294c286 2284 (PTR) & fmt_mvtc_ops[0],
52a53d1f 2285 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2286 },
2287/* neg $dr,$sr */
2288 {
23cf992f 2289 { 1, 1, 1, 1 },
1294c286 2290 M32R_INSN_NEG, "neg", "neg",
2e6dfccc 2291 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2292 & fmt_mv, { 0x30 },
1294c286 2293 (PTR) & fmt_mv_ops[0],
52a53d1f 2294 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2295 },
2296/* nop */
2297 {
23cf992f 2298 { 1, 1, 1, 1 },
1294c286 2299 M32R_INSN_NOP, "nop", "nop",
2e6dfccc 2300 { { MNEM, 0 } },
5730d39d 2301 & fmt_nop, { 0x7000 },
1294c286 2302 (PTR) 0,
52a53d1f 2303 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2304 },
2305/* not $dr,$sr */
2306 {
23cf992f 2307 { 1, 1, 1, 1 },
1294c286 2308 M32R_INSN_NOT, "not", "not",
2e6dfccc 2309 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2310 & fmt_mv, { 0xb0 },
1294c286 2311 (PTR) & fmt_mv_ops[0],
52a53d1f 2312 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2313 },
2314/* rac */
2315 {
23cf992f 2316 { 1, 1, 1, 1 },
1294c286 2317 M32R_INSN_RAC, "rac", "rac",
2e6dfccc 2318 { { MNEM, 0 } },
5730d39d 2319 & fmt_rac, { 0x5090 },
1294c286 2320 (PTR) & fmt_rac_ops[0],
8d157f96 2321 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 2322 },
2323/* start-sanitize-m32rx */
a6cefe4f 2324/* rac $accd,$accs,$imm1 */
ab0bd049
DE		 2325 {
2326 { 1, 1, 1, 1 },
1294c286 2327 M32R_INSN_RAC_DSI, "rac-dsi", "rac",
2e6dfccc 2328 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
5730d39d 2329 & fmt_rac_dsi, { 0x5090 },
1294c286 2330 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 2331 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2332 },
7c26196f 2333/* end-sanitize-m32rx */
9c03036a
DE		 2334/* rach */
2335 {
23cf992f 2336 { 1, 1, 1, 1 },
1294c286 2337 M32R_INSN_RACH, "rach", "rach",
2e6dfccc 2338 { { MNEM, 0 } },
5730d39d 2339 & fmt_rac, { 0x5080 },
1294c286 2340 (PTR) & fmt_rac_ops[0],
8d157f96 2341 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
ab0bd049
DE		 2342 },
2343/* start-sanitize-m32rx */
a6cefe4f 2344/* rach $accd,$accs,$imm1 */
7c26196f
DE		 2345 {
2346 { 1, 1, 1, 1 },
1294c286 2347 M32R_INSN_RACH_DSI, "rach-dsi", "rach",
2e6dfccc 2348 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
5730d39d 2349 & fmt_rac_dsi, { 0x5080 },
1294c286 2350 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 2351 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2352 },
7c26196f 2353/* end-sanitize-m32rx */
9c03036a
DE		 2354/* rte */
2355 {
23cf992f 2356 { 1, 1, 1, 1 },
1294c286 2357 M32R_INSN_RTE, "rte", "rte",
2e6dfccc 2358 { { MNEM, 0 } },
5730d39d 2359 & fmt_rte, { 0x10d6 },
1294c286 2360 (PTR) & fmt_rte_ops[0],
52a53d1f 2361 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
7c26196f 2362 },
a6cefe4f 2363/* seth $dr,$hash$hi16 */
7c26196f
DE		 2364 {
2365 { 1, 1, 1, 1 },
1294c286 2366 M32R_INSN_SETH, "seth", "seth",
2e6dfccc 2367 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
5730d39d 2368 & fmt_seth, { 0xd0c00000 },
1294c286 2369 (PTR) & fmt_seth_ops[0],
52a53d1f 2370 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2371 },
9c03036a
DE		 2372/* sll $dr,$sr */
2373 {
23cf992f 2374 { 1, 1, 1, 1 },
1294c286 2375 M32R_INSN_SLL, "sll", "sll",
2e6dfccc 2376 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2377 & fmt_add, { 0x1040 },
1294c286 2378 (PTR) & fmt_add_ops[0],
52a53d1f 2379 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 2380 },
9c03036a
DE		 2381/* sll3 $dr,$sr,$simm16 */
2382 {
23cf992f 2383 { 1, 1, 1, 1 },
1294c286 2384 M32R_INSN_SLL3, "sll3", "sll3",
2e6dfccc 2385 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
5730d39d 2386 & fmt_sll3, { 0x90c00000 },
1294c286 2387 (PTR) & fmt_sll3_ops[0],
52a53d1f 2388 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 2389 },
2390/* slli $dr,$uimm5 */
2391 {
23cf992f 2392 { 1, 1, 1, 1 },
1294c286 2393 M32R_INSN_SLLI, "slli", "slli",
2e6dfccc 2394 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
5730d39d 2395 & fmt_slli, { 0x5040 },
1294c286 2396 (PTR) & fmt_slli_ops[0],
52a53d1f 2397 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2398 },
2399/* sra $dr,$sr */
2400 {
23cf992f 2401 { 1, 1, 1, 1 },
1294c286 2402 M32R_INSN_SRA, "sra", "sra",
2e6dfccc 2403 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2404 & fmt_add, { 0x1020 },
1294c286 2405 (PTR) & fmt_add_ops[0],
52a53d1f 2406 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 2407 },
9c03036a
DE		 2408/* sra3 $dr,$sr,$simm16 */
2409 {
23cf992f 2410 { 1, 1, 1, 1 },
1294c286 2411 M32R_INSN_SRA3, "sra3", "sra3",
2e6dfccc 2412 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
5730d39d 2413 & fmt_sll3, { 0x90a00000 },
1294c286 2414 (PTR) & fmt_sll3_ops[0],
52a53d1f 2415 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 2416 },
2417/* srai $dr,$uimm5 */
2418 {
23cf992f 2419 { 1, 1, 1, 1 },
1294c286 2420 M32R_INSN_SRAI, "srai", "srai",
2e6dfccc 2421 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
5730d39d 2422 & fmt_slli, { 0x5020 },
1294c286 2423 (PTR) & fmt_slli_ops[0],
52a53d1f 2424 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2425 },
2426/* srl $dr,$sr */
2427 {
23cf992f 2428 { 1, 1, 1, 1 },
1294c286 2429 M32R_INSN_SRL, "srl", "srl",
2e6dfccc 2430 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2431 & fmt_add, { 0x1000 },
1294c286 2432 (PTR) & fmt_add_ops[0],
52a53d1f 2433 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 2434 },
9c03036a
DE		 2435/* srl3 $dr,$sr,$simm16 */
2436 {
23cf992f 2437 { 1, 1, 1, 1 },
1294c286 2438 M32R_INSN_SRL3, "srl3", "srl3",
2e6dfccc 2439 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
5730d39d 2440 & fmt_sll3, { 0x90800000 },
1294c286 2441 (PTR) & fmt_sll3_ops[0],
52a53d1f 2442 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 2443 },
2444/* srli $dr,$uimm5 */
2445 {
23cf992f 2446 { 1, 1, 1, 1 },
1294c286 2447 M32R_INSN_SRLI, "srli", "srli",
2e6dfccc 2448 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
5730d39d 2449 & fmt_slli, { 0x5000 },
1294c286 2450 (PTR) & fmt_slli_ops[0],
52a53d1f 2451 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2452 },
2453/* st $src1,@$src2 */
2454 {
23cf992f 2455 { 1, 1, 1, 1 },
1294c286 2456 M32R_INSN_ST, "st", "st",
2e6dfccc 2457 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
5730d39d 2458 & fmt_st, { 0x2040 },
1294c286 2459 (PTR) & fmt_st_ops[0],
52a53d1f 2460 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2461 },
9c03036a
DE		 2462/* st $src1,@($slo16,$src2) */
2463 {
23cf992f 2464 { 1, 1, 1, 1 },
1294c286 2465 M32R_INSN_ST_D, "st-d", "st",
2e6dfccc 2466 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
5730d39d 2467 & fmt_st_d, { 0xa0400000 },
1294c286 2468 (PTR) & fmt_st_d_ops[0],
52a53d1f 2469 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2470 },
9c03036a
DE		 2471/* stb $src1,@$src2 */
2472 {
23cf992f 2473 { 1, 1, 1, 1 },
1294c286 2474 M32R_INSN_STB, "stb", "stb",
2e6dfccc 2475 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
5730d39d 2476 & fmt_stb, { 0x2000 },
1294c286 2477 (PTR) & fmt_stb_ops[0],
52a53d1f 2478 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2479 },
1294c286 2480/* stb $src1,@($slo16,$src2) */
9c03036a 2481 {
23cf992f 2482 { 1, 1, 1, 1 },
1294c286 2483 M32R_INSN_STB_D, "stb-d", "stb",
2e6dfccc 2484 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
5730d39d 2485 & fmt_stb_d, { 0xa0000000 },
1294c286 2486 (PTR) & fmt_stb_d_ops[0],
52a53d1f 2487 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2488 },
9c03036a
DE		 2489/* sth $src1,@$src2 */
2490 {
23cf992f 2491 { 1, 1, 1, 1 },
1294c286 2492 M32R_INSN_STH, "sth", "sth",
2e6dfccc 2493 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
5730d39d 2494 & fmt_sth, { 0x2020 },
1294c286 2495 (PTR) & fmt_sth_ops[0],
52a53d1f 2496 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2497 },
9c03036a
DE		 2498/* sth $src1,@($slo16,$src2) */
2499 {
23cf992f 2500 { 1, 1, 1, 1 },
1294c286 2501 M32R_INSN_STH_D, "sth-d", "sth",
2e6dfccc 2502 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
5730d39d 2503 & fmt_sth_d, { 0xa0200000 },
1294c286 2504 (PTR) & fmt_sth_d_ops[0],
52a53d1f 2505 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2506 },
9c03036a
DE		 2507/* st $src1,@+$src2 */
2508 {
23cf992f 2509 { 1, 1, 1, 1 },
1294c286 2510 M32R_INSN_ST_PLUS, "st-plus", "st",
2e6dfccc 2511 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
5730d39d 2512 & fmt_st_plus, { 0x2060 },
1294c286 2513 (PTR) & fmt_st_plus_ops[0],
52a53d1f 2514 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2515 },
2516/* st $src1,@-$src2 */
2517 {
23cf992f 2518 { 1, 1, 1, 1 },
1294c286 2519 M32R_INSN_ST_MINUS, "st-minus", "st",
2e6dfccc 2520 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
5730d39d 2521 & fmt_st_plus, { 0x2070 },
1294c286 2522 (PTR) & fmt_st_plus_ops[0],
52a53d1f 2523 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2524 },
2525/* sub $dr,$sr */
2526 {
23cf992f 2527 { 1, 1, 1, 1 },
1294c286 2528 M32R_INSN_SUB, "sub", "sub",
2e6dfccc 2529 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2530 & fmt_add, { 0x20 },
1294c286 2531 (PTR) & fmt_add_ops[0],
52a53d1f 2532 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2533 },
2534/* subv $dr,$sr */
2535 {
23cf992f 2536 { 1, 1, 1, 1 },
1294c286 2537 M32R_INSN_SUBV, "subv", "subv",
2e6dfccc 2538 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2539 & fmt_addv, { 0x0 },
1294c286 2540 (PTR) & fmt_addv_ops[0],
52a53d1f 2541 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2542 },
2543/* subx $dr,$sr */
2544 {
23cf992f 2545 { 1, 1, 1, 1 },
1294c286 2546 M32R_INSN_SUBX, "subx", "subx",
2e6dfccc 2547 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2548 & fmt_addx, { 0x10 },
1294c286 2549 (PTR) & fmt_addx_ops[0],
52a53d1f 2550 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 2551 },
a6cefe4f 2552/* trap $uimm4 */
7c26196f
DE		 2553 {
2554 { 1, 1, 1, 1 },
1294c286 2555 M32R_INSN_TRAP, "trap", "trap",
2e6dfccc 2556 { { MNEM, ' ', OP (UIMM4), 0 } },
5730d39d 2557 & fmt_trap, { 0x10f0 },
1294c286 2558 (PTR) & fmt_trap_ops[0],
52a53d1f 2559 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a 2560 },
9c03036a
DE		 2561/* unlock $src1,@$src2 */
2562 {
23cf992f 2563 { 1, 1, 1, 1 },
1294c286 2564 M32R_INSN_UNLOCK, "unlock", "unlock",
2e6dfccc 2565 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
5730d39d 2566 & fmt_unlock, { 0x2050 },
1294c286 2567 (PTR) & fmt_unlock_ops[0],
52a53d1f 2568 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2569 },
7c26196f 2570/* start-sanitize-m32rx */
b02643b5 2571/* satb $dr,$sr */
7c26196f
DE		 2572 {
2573 { 1, 1, 1, 1 },
1294c286 2574 M32R_INSN_SATB, "satb", "satb",
2e6dfccc 2575 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2576 & fmt_satb, { 0x80600300 },
1294c286 2577 (PTR) & fmt_satb_ops[0],
8d157f96 2578 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2579 },
2580/* end-sanitize-m32rx */
2581/* start-sanitize-m32rx */
b02643b5 2582/* sath $dr,$sr */
7c26196f
DE		 2583 {
2584 { 1, 1, 1, 1 },
1294c286 2585 M32R_INSN_SATH, "sath", "sath",
2e6dfccc 2586 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2587 & fmt_satb, { 0x80600200 },
1294c286 2588 (PTR) & fmt_satb_ops[0],
8d157f96 2589 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2590 },
2591/* end-sanitize-m32rx */
2592/* start-sanitize-m32rx */
b02643b5 2593/* sat $dr,$sr */
7c26196f
DE		 2594 {
2595 { 1, 1, 1, 1 },
1294c286 2596 M32R_INSN_SAT, "sat", "sat",
2e6dfccc 2597 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
5730d39d 2598 & fmt_sat, { 0x80600000 },
1294c286 2599 (PTR) & fmt_sat_ops[0],
fbc8134d 2600 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2601 },
2602/* end-sanitize-m32rx */
2603/* start-sanitize-m32rx */
2604/* pcmpbz $src2 */
2605 {
2606 { 1, 1, 1, 1 },
1294c286 2607 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2e6dfccc 2608 { { MNEM, ' ', OP (SRC2), 0 } },
5730d39d 2609 & fmt_cmpz, { 0x370 },
1294c286 2610 (PTR) & fmt_cmpz_ops[0],
c2009f4a 2611 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 2612 },
2613/* end-sanitize-m32rx */
2614/* start-sanitize-m32rx */
2615/* sadd */
2616 {
2617 { 1, 1, 1, 1 },
1294c286 2618 M32R_INSN_SADD, "sadd", "sadd",
2e6dfccc 2619 { { MNEM, 0 } },
5730d39d 2620 & fmt_sadd, { 0x50e4 },
1294c286 2621 (PTR) & fmt_sadd_ops[0],
8d157f96 2622 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2623 },
7c26196f
DE		 2624/* end-sanitize-m32rx */
2625/* start-sanitize-m32rx */
2626/* macwu1 $src1,$src2 */
2627 {
2628 { 1, 1, 1, 1 },
1294c286 2629 M32R_INSN_MACWU1, "macwu1", "macwu1",
2e6dfccc 2630 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2631 & fmt_macwu1, { 0x50b0 },
1294c286 2632 (PTR) & fmt_macwu1_ops[0],
8d157f96 2633 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2634 },
2635/* end-sanitize-m32rx */
2636/* start-sanitize-m32rx */
2637/* msblo $src1,$src2 */
2638 {
2639 { 1, 1, 1, 1 },
1294c286 2640 M32R_INSN_MSBLO, "msblo", "msblo",
2e6dfccc 2641 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2642 & fmt_machi, { 0x50d0 },
1294c286 2643 (PTR) & fmt_machi_ops[0],
8d157f96 2644 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2645 },
2646/* end-sanitize-m32rx */
2647/* start-sanitize-m32rx */
2648/* mulwu1 $src1,$src2 */
2649 {
2650 { 1, 1, 1, 1 },
1294c286 2651 M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2e6dfccc 2652 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2653 & fmt_mulwu1, { 0x50a0 },
1294c286 2654 (PTR) & fmt_mulwu1_ops[0],
8d157f96 2655 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2656 },
2657/* end-sanitize-m32rx */
2658/* start-sanitize-m32rx */
ab0bd049 2659/* maclh1 $src1,$src2 */
7c26196f
DE		 2660 {
2661 { 1, 1, 1, 1 },
1294c286 2662 M32R_INSN_MACLH1, "maclh1", "maclh1",
2e6dfccc 2663 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
5730d39d 2664 & fmt_macwu1, { 0x50c0 },
1294c286 2665 (PTR) & fmt_macwu1_ops[0],
8d157f96 2666 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2667 },
2668/* end-sanitize-m32rx */
2669/* start-sanitize-m32rx */
2670/* sc */
2671 {
2672 { 1, 1, 1, 1 },
1294c286 2673 M32R_INSN_SC, "sc", "sc",
2e6dfccc 2674 { { MNEM, 0 } },
5730d39d 2675 & fmt_sc, { 0x7401 },
1294c286 2676 (PTR) & fmt_sc_ops[0],
52a53d1f 2677 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2678 },
2679/* end-sanitize-m32rx */
2680/* start-sanitize-m32rx */
2681/* snc */
2682 {
2683 { 1, 1, 1, 1 },
1294c286 2684 M32R_INSN_SNC, "snc", "snc",
2e6dfccc 2685 { { MNEM, 0 } },
5730d39d 2686 & fmt_sc, { 0x7501 },
1294c286 2687 (PTR) & fmt_sc_ops[0],
52a53d1f 2688 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2689 },
2690/* end-sanitize-m32rx */
9c03036a
DE		 2691};
2692
23cf992f 2693#undef A
0bf55db8
DE		 2694#undef MNEM
2695#undef OP
23cf992f 2696
c2009f4a 2697static const CGEN_INSN_TABLE insn_table =
853713a7 2698{
9c03036a 2699 & m32r_cgen_insn_table_entries[0],
23cf992f 2700 sizeof (CGEN_INSN),
7c26196f 2701 MAX_INSNS,
1294c286
DE		 2702 NULL
2703};
2704
5730d39d
DE		 2705/* Formats for ALIAS macro-insns. */
2706
2707#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
2708
2709static const CGEN_IFMT fmt_bc8r = {
2710 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2711};
2712
2713static const CGEN_IFMT fmt_bc24r = {
2714 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2715};
2716
2717static const CGEN_IFMT fmt_bl8r = {
2718 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2719};
2720
2721static const CGEN_IFMT fmt_bl24r = {
2722 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2723};
2724
2725/* start-sanitize-m32rx */
2726static const CGEN_IFMT fmt_bcl8r = {
2727 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2728};
2729
2730/* end-sanitize-m32rx */
2731/* start-sanitize-m32rx */
2732static const CGEN_IFMT fmt_bcl24r = {
2733 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2734};
2735
2736/* end-sanitize-m32rx */
2737static const CGEN_IFMT fmt_bnc8r = {
2738 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2739};
2740
2741static const CGEN_IFMT fmt_bnc24r = {
2742 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2743};
2744
2745static const CGEN_IFMT fmt_bra8r = {
2746 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2747};
2748
2749static const CGEN_IFMT fmt_bra24r = {
2750 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2751};
2752
2753/* start-sanitize-m32rx */
2754static const CGEN_IFMT fmt_bncl8r = {
2755 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2756};
2757
2758/* end-sanitize-m32rx */
2759/* start-sanitize-m32rx */
2760static const CGEN_IFMT fmt_bncl24r = {
2761 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2762};
2763
2764/* end-sanitize-m32rx */
2765static const CGEN_IFMT fmt_ld_2 = {
2766 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2767};
2768
2769static const CGEN_IFMT fmt_ld_d2 = {
2770 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2771};
2772
2773static const CGEN_IFMT fmt_ldb_2 = {
2774 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2775};
2776
2777static const CGEN_IFMT fmt_ldb_d2 = {
2778 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2779};
2780
2781static const CGEN_IFMT fmt_ldh_2 = {
2782 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2783};
2784
2785static const CGEN_IFMT fmt_ldh_d2 = {
2786 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2787};
2788
2789static const CGEN_IFMT fmt_ldub_2 = {
2790 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2791};
2792
2793static const CGEN_IFMT fmt_ldub_d2 = {
2794 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2795};
2796
2797static const CGEN_IFMT fmt_lduh_2 = {
2798 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2799};
2800
2801static const CGEN_IFMT fmt_lduh_d2 = {
2802 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2803};
2804
2805static const CGEN_IFMT fmt_pop = {
2806 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2807};
2808
2809static const CGEN_IFMT fmt_ldi8a = {
2810 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
2811};
2812
2813static const CGEN_IFMT fmt_ldi16a = {
2814 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2815};
2816
2817/* start-sanitize-m32rx */
2818static const CGEN_IFMT fmt_rac_d = {
2819 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2820};
2821
2822/* end-sanitize-m32rx */
2823/* start-sanitize-m32rx */
2824static const CGEN_IFMT fmt_rac_ds = {
2825 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2826};
2827
2828/* end-sanitize-m32rx */
2829/* start-sanitize-m32rx */
2830static const CGEN_IFMT fmt_rach_d = {
2831 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2832};
2833
2834/* end-sanitize-m32rx */
2835/* start-sanitize-m32rx */
2836static const CGEN_IFMT fmt_rach_ds = {
2837 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2838};
2839
2840/* end-sanitize-m32rx */
2841static const CGEN_IFMT fmt_st_2 = {
2842 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2843};
2844
2845static const CGEN_IFMT fmt_st_d2 = {
2846 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2847};
2848
2849static const CGEN_IFMT fmt_stb_2 = {
2850 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2851};
2852
2853static const CGEN_IFMT fmt_stb_d2 = {
2854 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2855};
2856
2857static const CGEN_IFMT fmt_sth_2 = {
2858 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2859};
2860
2861static const CGEN_IFMT fmt_sth_d2 = {
2862 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2863};
2864
2865static const CGEN_IFMT fmt_push = {
2866 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2867};
2868
2869#undef F
2870
1294c286
DE		 2871/* Each non-simple macro entry points to an array of expansion possibilities. */
2872
2873#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2874#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2875#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2876
2877/* The macro instruction table. */
2878
2879static const CGEN_INSN macro_insn_table_entries[] =
2880{
2881/* bc $disp8 */
2882 {
2883 { 1, 1, 1, 1 },
2884 -1, "bc8r", "bc",
2e6dfccc 2885 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 2886 & fmt_bc8r, { 0x7c00 },
1294c286 2887 (PTR) 0,
52a53d1f 2888 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2889 },
2890/* bc $disp24 */
2891 {
2892 { 1, 1, 1, 1 },
2893 -1, "bc24r", "bc",
2e6dfccc 2894 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 2895 & fmt_bc24r, { 0xfc000000 },
1294c286 2896 (PTR) 0,
52a53d1f 2897 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2898 },
2899/* bl $disp8 */
2900 {
2901 { 1, 1, 1, 1 },
2902 -1, "bl8r", "bl",
2e6dfccc 2903 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 2904 & fmt_bl8r, { 0x7e00 },
1294c286 2905 (PTR) 0,
52a53d1f 2906 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2907 },
2908/* bl $disp24 */
2909 {
2910 { 1, 1, 1, 1 },
2911 -1, "bl24r", "bl",
2e6dfccc 2912 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 2913 & fmt_bl24r, { 0xfe000000 },
1294c286 2914 (PTR) 0,
52a53d1f 2915 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286 2916 },
5730d39d 2917/* start-sanitize-m32rx */
1294c286
DE		 2918/* bcl $disp8 */
2919 {
2920 { 1, 1, 1, 1 },
2921 -1, "bcl8r", "bcl",
2e6dfccc 2922 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 2923 & fmt_bcl8r, { 0x7800 },
1294c286 2924 (PTR) 0,
52a53d1f 2925 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1294c286 2926 },
5730d39d
DE		 2927/* end-sanitize-m32rx */
2928/* start-sanitize-m32rx */
1294c286
DE		 2929/* bcl $disp24 */
2930 {
2931 { 1, 1, 1, 1 },
2932 -1, "bcl24r", "bcl",
2e6dfccc 2933 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 2934 & fmt_bcl24r, { 0xf8000000 },
1294c286
DE		 2935 (PTR) 0,
2936 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2937 },
5730d39d 2938/* end-sanitize-m32rx */
1294c286
DE		 2939/* bnc $disp8 */
2940 {
2941 { 1, 1, 1, 1 },
2942 -1, "bnc8r", "bnc",
2e6dfccc 2943 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 2944 & fmt_bnc8r, { 0x7d00 },
1294c286 2945 (PTR) 0,
52a53d1f 2946 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2947 },
2948/* bnc $disp24 */
2949 {
2950 { 1, 1, 1, 1 },
2951 -1, "bnc24r", "bnc",
2e6dfccc 2952 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 2953 & fmt_bnc24r, { 0xfd000000 },
1294c286 2954 (PTR) 0,
52a53d1f 2955 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2956 },
2957/* bra $disp8 */
2958 {
2959 { 1, 1, 1, 1 },
2960 -1, "bra8r", "bra",
2e6dfccc 2961 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 2962 & fmt_bra8r, { 0x7f00 },
1294c286 2963 (PTR) 0,
52a53d1f 2964 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2965 },
2966/* bra $disp24 */
2967 {
2968 { 1, 1, 1, 1 },
2969 -1, "bra24r", "bra",
2e6dfccc 2970 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 2971 & fmt_bra24r, { 0xff000000 },
1294c286 2972 (PTR) 0,
52a53d1f 2973 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286 2974 },
5730d39d 2975/* start-sanitize-m32rx */
1294c286
DE		 2976/* bncl $disp8 */
2977 {
2978 { 1, 1, 1, 1 },
2979 -1, "bncl8r", "bncl",
2e6dfccc 2980 { { MNEM, ' ', OP (DISP8), 0 } },
5730d39d 2981 & fmt_bncl8r, { 0x7900 },
1294c286 2982 (PTR) 0,
52a53d1f 2983 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1294c286 2984 },
5730d39d
DE		 2985/* end-sanitize-m32rx */
2986/* start-sanitize-m32rx */
1294c286
DE		 2987/* bncl $disp24 */
2988 {
2989 { 1, 1, 1, 1 },
2990 -1, "bncl24r", "bncl",
2e6dfccc 2991 { { MNEM, ' ', OP (DISP24), 0 } },
5730d39d 2992 & fmt_bncl24r, { 0xf9000000 },
1294c286
DE		 2993 (PTR) 0,
2994 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2995 },
5730d39d 2996/* end-sanitize-m32rx */
1294c286
DE		 2997/* ld $dr,@($sr) */
2998 {
2999 { 1, 1, 1, 1 },
3000 -1, "ld-2", "ld",
2e6dfccc 3001 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
5730d39d 3002 & fmt_ld_2, { 0x20c0 },
1294c286 3003 (PTR) 0,
52a53d1f 3004 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3005 },
3006/* ld $dr,@($sr,$slo16) */
3007 {
3008 { 1, 1, 1, 1 },
3009 -1, "ld-d2", "ld",
2e6dfccc 3010 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
5730d39d 3011 & fmt_ld_d2, { 0xa0c00000 },
1294c286 3012 (PTR) 0,
52a53d1f 3013 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3014 },
3015/* ldb $dr,@($sr) */
3016 {
3017 { 1, 1, 1, 1 },
3018 -1, "ldb-2", "ldb",
2e6dfccc 3019 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
5730d39d 3020 & fmt_ldb_2, { 0x2080 },
1294c286 3021 (PTR) 0,
52a53d1f 3022 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3023 },
3024/* ldb $dr,@($sr,$slo16) */
3025 {
3026 { 1, 1, 1, 1 },
3027 -1, "ldb-d2", "ldb",
2e6dfccc 3028 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
5730d39d 3029 & fmt_ldb_d2, { 0xa0800000 },
1294c286 3030 (PTR) 0,
52a53d1f 3031 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3032 },
3033/* ldh $dr,@($sr) */
3034 {
3035 { 1, 1, 1, 1 },
3036 -1, "ldh-2", "ldh",
2e6dfccc 3037 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
5730d39d 3038 & fmt_ldh_2, { 0x20a0 },
1294c286 3039 (PTR) 0,
52a53d1f 3040 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3041 },
3042/* ldh $dr,@($sr,$slo16) */
3043 {
3044 { 1, 1, 1, 1 },
3045 -1, "ldh-d2", "ldh",
2e6dfccc 3046 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
5730d39d 3047 & fmt_ldh_d2, { 0xa0a00000 },
1294c286 3048 (PTR) 0,
52a53d1f 3049 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3050 },
3051/* ldub $dr,@($sr) */
3052 {
3053 { 1, 1, 1, 1 },
3054 -1, "ldub-2", "ldub",
2e6dfccc 3055 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
5730d39d 3056 & fmt_ldub_2, { 0x2090 },
1294c286 3057 (PTR) 0,
52a53d1f 3058 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3059 },
3060/* ldub $dr,@($sr,$slo16) */
3061 {
3062 { 1, 1, 1, 1 },
3063 -1, "ldub-d2", "ldub",
2e6dfccc 3064 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
5730d39d 3065 & fmt_ldub_d2, { 0xa0900000 },
1294c286 3066 (PTR) 0,
52a53d1f 3067 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3068 },
3069/* lduh $dr,@($sr) */
3070 {
3071 { 1, 1, 1, 1 },
3072 -1, "lduh-2", "lduh",
2e6dfccc 3073 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
5730d39d 3074 & fmt_lduh_2, { 0x20b0 },
1294c286 3075 (PTR) 0,
52a53d1f 3076 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3077 },
3078/* lduh $dr,@($sr,$slo16) */
3079 {
3080 { 1, 1, 1, 1 },
3081 -1, "lduh-d2", "lduh",
2e6dfccc 3082 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
5730d39d 3083 & fmt_lduh_d2, { 0xa0b00000 },
1294c286 3084 (PTR) 0,
52a53d1f 3085 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3086 },
3087/* pop $dr */
3088 {
3089 { 1, 1, 1, 1 },
3090 -1, "pop", "pop",
2e6dfccc 3091 { { MNEM, ' ', OP (DR), 0 } },
5730d39d 3092 & fmt_pop, { 0x20ef },
1294c286 3093 (PTR) 0,
52a53d1f 3094 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3095 },
3096/* ldi $dr,$simm8 */
3097 {
3098 { 1, 1, 1, 1 },
3099 -1, "ldi8a", "ldi",
2e6dfccc 3100 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
5730d39d 3101 & fmt_ldi8a, { 0x6000 },
1294c286 3102 (PTR) 0,
52a53d1f 3103 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
1294c286
DE		 3104 },
3105/* ldi $dr,$hash$slo16 */
3106 {
3107 { 1, 1, 1, 1 },
3108 -1, "ldi16a", "ldi",
2e6dfccc 3109 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
5730d39d 3110 & fmt_ldi16a, { 0x90f00000 },
1294c286 3111 (PTR) 0,
52a53d1f 3112 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286 3113 },
5730d39d 3114/* start-sanitize-m32rx */
1294c286
DE		 3115/* rac $accd */
3116 {
3117 { 1, 1, 1, 1 },
3118 -1, "rac-d", "rac",
2e6dfccc 3119 { { MNEM, ' ', OP (ACCD), 0 } },
5730d39d 3120 & fmt_rac_d, { 0x5090 },
1294c286
DE		 3121 (PTR) 0,
3122 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3123 },
5730d39d
DE		 3124/* end-sanitize-m32rx */
3125/* start-sanitize-m32rx */
1294c286
DE		 3126/* rac $accd,$accs */
3127 {
3128 { 1, 1, 1, 1 },
3129 -1, "rac-ds", "rac",
2e6dfccc 3130 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
5730d39d 3131 & fmt_rac_ds, { 0x5090 },
1294c286
DE		 3132 (PTR) 0,
3133 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3134 },
5730d39d
DE		 3135/* end-sanitize-m32rx */
3136/* start-sanitize-m32rx */
1294c286
DE		 3137/* rach $accd */
3138 {
3139 { 1, 1, 1, 1 },
3140 -1, "rach-d", "rach",
2e6dfccc 3141 { { MNEM, ' ', OP (ACCD), 0 } },
5730d39d 3142 & fmt_rach_d, { 0x5080 },
1294c286
DE		 3143 (PTR) 0,
3144 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3145 },
5730d39d
DE		 3146/* end-sanitize-m32rx */
3147/* start-sanitize-m32rx */
1294c286
DE		 3148/* rach $accd,$accs */
3149 {
3150 { 1, 1, 1, 1 },
3151 -1, "rach-ds", "rach",
2e6dfccc 3152 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
5730d39d 3153 & fmt_rach_ds, { 0x5080 },
1294c286
DE		 3154 (PTR) 0,
3155 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3156 },
5730d39d 3157/* end-sanitize-m32rx */
1294c286
DE		 3158/* st $src1,@($src2) */
3159 {
3160 { 1, 1, 1, 1 },
3161 -1, "st-2", "st",
2e6dfccc 3162 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
5730d39d 3163 & fmt_st_2, { 0x2040 },
1294c286 3164 (PTR) 0,
52a53d1f 3165 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3166 },
3167/* st $src1,@($src2,$slo16) */
3168 {
3169 { 1, 1, 1, 1 },
3170 -1, "st-d2", "st",
2e6dfccc 3171 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
5730d39d 3172 & fmt_st_d2, { 0xa0400000 },
1294c286 3173 (PTR) 0,
52a53d1f 3174 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3175 },
3176/* stb $src1,@($src2) */
3177 {
3178 { 1, 1, 1, 1 },
3179 -1, "stb-2", "stb",
2e6dfccc 3180 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
5730d39d 3181 & fmt_stb_2, { 0x2000 },
1294c286 3182 (PTR) 0,
52a53d1f 3183 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3184 },
3185/* stb $src1,@($src2,$slo16) */
3186 {
3187 { 1, 1, 1, 1 },
3188 -1, "stb-d2", "stb",
2e6dfccc 3189 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
5730d39d 3190 & fmt_stb_d2, { 0xa0000000 },
1294c286 3191 (PTR) 0,
52a53d1f 3192 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3193 },
3194/* sth $src1,@($src2) */
3195 {
3196 { 1, 1, 1, 1 },
3197 -1, "sth-2", "sth",
2e6dfccc 3198 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
5730d39d 3199 & fmt_sth_2, { 0x2020 },
1294c286 3200 (PTR) 0,
52a53d1f 3201 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 3202 },
3203/* sth $src1,@($src2,$slo16) */
3204 {
3205 { 1, 1, 1, 1 },
3206 -1, "sth-d2", "sth",
2e6dfccc 3207 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
5730d39d 3208 & fmt_sth_d2, { 0xa0200000 },
1294c286 3209 (PTR) 0,
52a53d1f 3210 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3211 },
3212/* push $src1 */
3213 {
3214 { 1, 1, 1, 1 },
3215 -1, "push", "push",
2e6dfccc 3216 { { MNEM, ' ', OP (SRC1), 0 } },
5730d39d 3217 & fmt_push, { 0x207f },
1294c286 3218 (PTR) 0,
52a53d1f 3219 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 3220 },
3221};
3222
3223#undef A
3224#undef MNEM
3225#undef OP
3226
c2009f4a 3227static const CGEN_INSN_TABLE macro_insn_table =
1294c286
DE		 3228{
3229 & macro_insn_table_entries[0],
3230 sizeof (CGEN_INSN),
3231 (sizeof (macro_insn_table_entries) /
3232 sizeof (macro_insn_table_entries[0])),
3233 NULL
9c03036a
DE		 3234};
3235
c2009f4a
DE		 3236static void
3237init_tables ()
3238{
3239}
1294c286
DE		 3240
3241/* Return non-zero if INSN is to be added to the hash table.
3242 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3243
3244static int
3245asm_hash_insn_p (insn)
3246 const CGEN_INSN * insn;
3247{
3248 return CGEN_ASM_HASH_P (insn);
3249}
3250
3251static int
3252dis_hash_insn_p (insn)
3253 const CGEN_INSN * insn;
3254{
3255 /* If building the hash table and the NO-DIS attribute is present,
3256 ignore. */
3257 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3258 return 0;
3259 return CGEN_DIS_HASH_P (insn);
3260}
3261
3262/* The result is the hash value of the insn.
3263 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
9c03036a 3264
1294c286
DE		 3265static unsigned int
3266asm_hash_insn (mnem)
3267 const char * mnem;
9c03036a 3268{
1294c286 3269 return CGEN_ASM_HASH (mnem);
9c03036a
DE		 3270}
3271
52a53d1f
DE		 3272/* BUF is a pointer to the insn's bytes in target order.
3273 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3274 host order. */
3275
1294c286
DE		 3276static unsigned int
3277dis_hash_insn (buf, value)
5d07b6cf 3278 const char * buf;
5730d39d 3279 CGEN_INSN_INT value;
9c03036a
DE		 3280{
3281 return CGEN_DIS_HASH (buf, value);
3282}
3283
c2009f4a
DE		 3284/* Initialize an opcode table and return a descriptor.
3285 It's much like opening a file, and must be the first function called. */
3286
3287CGEN_OPCODE_DESC
3288m32r_cgen_opcode_open (mach, endian)
3289 int mach;
3290 enum cgen_endian endian;
5d07b6cf 3291{
c2009f4a
DE		 3292 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3293 static int init_p;
3294
3295 if (! init_p)
3296 {
3297 init_tables ();
3298 init_p = 1;
3299 }
3300
3301 memset (table, 0, sizeof (*table));
3302
3303 CGEN_OPCODE_MACH (table) = mach;
3304 CGEN_OPCODE_ENDIAN (table) = endian;
52a53d1f
DE		 3305 /* FIXME: for the sparc case we can determine insn-endianness statically.
3306 The worry here is where both data and insn endian can be independently
3307 chosen, in which case this function will need another argument.
3308 Actually, will want to allow for more arguments in the future anyway. */
3309 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
c2009f4a
DE		 3310
3311 CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
3312
5730d39d
DE		 3313 CGEN_OPCODE_IFLD_TABLE (table) = & m32r_cgen_ifld_table[0];
3314
c2009f4a
DE		 3315 CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
3316
3317 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3318
3319 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3320
3321 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3322 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3323 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3324
3325 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3326 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3327 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3328
3329 return (CGEN_OPCODE_DESC) table;
3330}
3331
3332/* Close an opcode table. */
9c03036a
DE		 3333
3334void
c2009f4a
DE		 3335m32r_cgen_opcode_close (desc)
3336 CGEN_OPCODE_DESC desc;
9c03036a 3337{
c2009f4a 3338 free (desc);
9c03036a
DE		 3339}
3340
fbc8134d
DE		 3341/* Getting values from cgen_fields is handled by a collection of functions.
3342 They are distinguished by the type of the VALUE argument they return.
3343 TODO: floating point, inlining support, remove cases where result type
3344 not appropriate. */
9c03036a 3345
fbc8134d
DE		 3346int
3347m32r_cgen_get_int_operand (opindex, fields)
9c03036a 3348 int opindex;
fbc8134d 3349 const CGEN_FIELDS * fields;
9c03036a 3350{
fbc8134d
DE		 3351 int value;
3352
9c03036a
DE		 3353 switch (opindex)
3354 {
23cf992f 3355 case M32R_OPERAND_SR :
fbc8134d 3356 value = fields->f_r2;
9c03036a 3357 break;
23cf992f 3358 case M32R_OPERAND_DR :
fbc8134d 3359 value = fields->f_r1;
9c03036a 3360 break;
23cf992f 3361 case M32R_OPERAND_SRC1 :
fbc8134d 3362 value = fields->f_r1;
9c03036a 3363 break;
23cf992f 3364 case M32R_OPERAND_SRC2 :
fbc8134d 3365 value = fields->f_r2;
9c03036a 3366 break;
23cf992f 3367 case M32R_OPERAND_SCR :
fbc8134d 3368 value = fields->f_r2;
9c03036a 3369 break;
23cf992f 3370 case M32R_OPERAND_DCR :
fbc8134d 3371 value = fields->f_r1;
9c03036a 3372 break;
23cf992f 3373 case M32R_OPERAND_SIMM8 :
fbc8134d 3374 value = fields->f_simm8;
9c03036a 3375 break;
23cf992f 3376 case M32R_OPERAND_SIMM16 :
fbc8134d 3377 value = fields->f_simm16;
9c03036a 3378 break;
23cf992f 3379 case M32R_OPERAND_UIMM4 :
fbc8134d 3380 value = fields->f_uimm4;
9c03036a 3381 break;
23cf992f 3382 case M32R_OPERAND_UIMM5 :
fbc8134d 3383 value = fields->f_uimm5;
9c03036a 3384 break;
23cf992f 3385 case M32R_OPERAND_UIMM16 :
fbc8134d 3386 value = fields->f_uimm16;
23cf992f 3387 break;
ab0bd049
DE		 3388/* start-sanitize-m32rx */
3389 case M32R_OPERAND_IMM1 :
fbc8134d 3390 value = fields->f_imm1;
ab0bd049
DE		 3391 break;
3392/* end-sanitize-m32rx */
3393/* start-sanitize-m32rx */
3394 case M32R_OPERAND_ACCD :
fbc8134d 3395 value = fields->f_accd;
ab0bd049
DE		 3396 break;
3397/* end-sanitize-m32rx */
7c26196f
DE		 3398/* start-sanitize-m32rx */
3399 case M32R_OPERAND_ACCS :
fbc8134d 3400 value = fields->f_accs;
7c26196f
DE		 3401 break;
3402/* end-sanitize-m32rx */
3403/* start-sanitize-m32rx */
3404 case M32R_OPERAND_ACC :
fbc8134d 3405 value = fields->f_acc;
7c26196f
DE		 3406 break;
3407/* end-sanitize-m32rx */
a6cefe4f 3408 case M32R_OPERAND_HASH :
fbc8134d 3409 value = fields->f_nil;
a6cefe4f 3410 break;
23cf992f 3411 case M32R_OPERAND_HI16 :
fbc8134d 3412 value = fields->f_hi16;
9c03036a 3413 break;
23cf992f 3414 case M32R_OPERAND_SLO16 :
fbc8134d 3415 value = fields->f_simm16;
9c03036a 3416 break;
23cf992f 3417 case M32R_OPERAND_ULO16 :
fbc8134d 3418 value = fields->f_uimm16;
9c03036a 3419 break;
23cf992f 3420 case M32R_OPERAND_UIMM24 :
fbc8134d 3421 value = fields->f_uimm24;
9c03036a 3422 break;
23cf992f 3423 case M32R_OPERAND_DISP8 :
fbc8134d 3424 value = fields->f_disp8;
9c03036a 3425 break;
23cf992f 3426 case M32R_OPERAND_DISP16 :
fbc8134d 3427 value = fields->f_disp16;
9c03036a 3428 break;
23cf992f 3429 case M32R_OPERAND_DISP24 :
fbc8134d 3430 value = fields->f_disp24;
9c03036a
DE		 3431 break;
3432
3433 default :
fbc8134d
DE		 3434 /* xgettext:c-format */
3435 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
9c03036a
DE		 3436 opindex);
3437 abort ();
3438 }
9c03036a 3439
fbc8134d
DE		 3440 return value;
3441}
9c03036a 3442
fbc8134d
DE		 3443bfd_vma
3444m32r_cgen_get_vma_operand (opindex, fields)
5d07b6cf 3445 int opindex;
853713a7 3446 const CGEN_FIELDS * fields;
9c03036a 3447{
fbc8134d 3448 bfd_vma value;
9c03036a
DE		 3449
3450 switch (opindex)
3451 {
23cf992f 3452 case M32R_OPERAND_SR :
9c03036a
DE		 3453 value = fields->f_r2;
3454 break;
23cf992f 3455 case M32R_OPERAND_DR :
9c03036a
DE		 3456 value = fields->f_r1;
3457 break;
23cf992f 3458 case M32R_OPERAND_SRC1 :
9c03036a
DE		 3459 value = fields->f_r1;
3460 break;
23cf992f 3461 case M32R_OPERAND_SRC2 :
9c03036a
DE		 3462 value = fields->f_r2;
3463 break;
23cf992f 3464 case M32R_OPERAND_SCR :
9c03036a
DE		 3465 value = fields->f_r2;
3466 break;
23cf992f 3467 case M32R_OPERAND_DCR :
9c03036a
DE		 3468 value = fields->f_r1;
3469 break;
23cf992f 3470 case M32R_OPERAND_SIMM8 :
9c03036a
DE		 3471 value = fields->f_simm8;
3472 break;
23cf992f 3473 case M32R_OPERAND_SIMM16 :
9c03036a
DE		 3474 value = fields->f_simm16;
3475 break;
23cf992f 3476 case M32R_OPERAND_UIMM4 :
9c03036a
DE		 3477 value = fields->f_uimm4;
3478 break;
23cf992f 3479 case M32R_OPERAND_UIMM5 :
9c03036a
DE		 3480 value = fields->f_uimm5;
3481 break;
23cf992f 3482 case M32R_OPERAND_UIMM16 :
9c03036a
DE		 3483 value = fields->f_uimm16;
3484 break;
ab0bd049
DE		 3485/* start-sanitize-m32rx */
3486 case M32R_OPERAND_IMM1 :
3487 value = fields->f_imm1;
3488 break;
3489/* end-sanitize-m32rx */
3490/* start-sanitize-m32rx */
3491 case M32R_OPERAND_ACCD :
3492 value = fields->f_accd;
3493 break;
3494/* end-sanitize-m32rx */
7c26196f
DE		 3495/* start-sanitize-m32rx */
3496 case M32R_OPERAND_ACCS :
3497 value = fields->f_accs;
3498 break;
3499/* end-sanitize-m32rx */
3500/* start-sanitize-m32rx */
3501 case M32R_OPERAND_ACC :
3502 value = fields->f_acc;
3503 break;
3504/* end-sanitize-m32rx */
a6cefe4f
DE		 3505 case M32R_OPERAND_HASH :
3506 value = fields->f_nil;
3507 break;
23cf992f 3508 case M32R_OPERAND_HI16 :
9c03036a
DE		 3509 value = fields->f_hi16;
3510 break;
23cf992f 3511 case M32R_OPERAND_SLO16 :
9c03036a
DE		 3512 value = fields->f_simm16;
3513 break;
23cf992f 3514 case M32R_OPERAND_ULO16 :
9c03036a
DE		 3515 value = fields->f_uimm16;
3516 break;
23cf992f 3517 case M32R_OPERAND_UIMM24 :
9c03036a
DE		 3518 value = fields->f_uimm24;
3519 break;
23cf992f 3520 case M32R_OPERAND_DISP8 :
9c03036a
DE		 3521 value = fields->f_disp8;
3522 break;
23cf992f 3523 case M32R_OPERAND_DISP16 :
9c03036a
DE		 3524 value = fields->f_disp16;
3525 break;
23cf992f 3526 case M32R_OPERAND_DISP24 :
9c03036a
DE		 3527 value = fields->f_disp24;
3528 break;
3529
3530 default :
fbc8134d
DE		 3531 /* xgettext:c-format */
3532 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
9c03036a
DE		 3533 opindex);
3534 abort ();
3535 }
3536
3537 return value;
3538}
3539
fbc8134d
DE		 3540/* Stuffing values in cgen_fields is handled by a collection of functions.
3541 They are distinguished by the type of the VALUE argument they accept.
3542 TODO: floating point, inlining support, remove cases where argument type
3543 not appropriate. */
3544
3545void
3546m32r_cgen_set_int_operand (opindex, fields, value)
3547 int opindex;
3548 CGEN_FIELDS * fields;
3549 int value;
3550{
3551 switch (opindex)
3552 {
3553 case M32R_OPERAND_SR :
3554 fields->f_r2 = value;
3555 break;
3556 case M32R_OPERAND_DR :
3557 fields->f_r1 = value;
3558 break;
3559 case M32R_OPERAND_SRC1 :
3560 fields->f_r1 = value;
3561 break;
3562 case M32R_OPERAND_SRC2 :
3563 fields->f_r2 = value;
3564 break;
3565 case M32R_OPERAND_SCR :
3566 fields->f_r2 = value;
3567 break;
3568 case M32R_OPERAND_DCR :
3569 fields->f_r1 = value;
3570 break;
3571 case M32R_OPERAND_SIMM8 :
3572 fields->f_simm8 = value;
3573 break;
3574 case M32R_OPERAND_SIMM16 :
3575 fields->f_simm16 = value;
3576 break;
3577 case M32R_OPERAND_UIMM4 :
3578 fields->f_uimm4 = value;
3579 break;
3580 case M32R_OPERAND_UIMM5 :
3581 fields->f_uimm5 = value;
3582 break;
3583 case M32R_OPERAND_UIMM16 :
3584 fields->f_uimm16 = value;
3585 break;
3586/* start-sanitize-m32rx */
3587 case M32R_OPERAND_IMM1 :
3588 fields->f_imm1 = value;
3589 break;
3590/* end-sanitize-m32rx */
3591/* start-sanitize-m32rx */
3592 case M32R_OPERAND_ACCD :
3593 fields->f_accd = value;
3594 break;
3595/* end-sanitize-m32rx */
3596/* start-sanitize-m32rx */
3597 case M32R_OPERAND_ACCS :
3598 fields->f_accs = value;
3599 break;
3600/* end-sanitize-m32rx */
3601/* start-sanitize-m32rx */
3602 case M32R_OPERAND_ACC :
3603 fields->f_acc = value;
3604 break;
3605/* end-sanitize-m32rx */
3606 case M32R_OPERAND_HASH :
3607 fields->f_nil = value;
3608 break;
3609 case M32R_OPERAND_HI16 :
3610 fields->f_hi16 = value;
3611 break;
3612 case M32R_OPERAND_SLO16 :
3613 fields->f_simm16 = value;
3614 break;
3615 case M32R_OPERAND_ULO16 :
3616 fields->f_uimm16 = value;
3617 break;
3618 case M32R_OPERAND_UIMM24 :
3619 fields->f_uimm24 = value;
3620 break;
3621 case M32R_OPERAND_DISP8 :
3622 fields->f_disp8 = value;
3623 break;
3624 case M32R_OPERAND_DISP16 :
3625 fields->f_disp16 = value;
3626 break;
3627 case M32R_OPERAND_DISP24 :
3628 fields->f_disp24 = value;
3629 break;
3630
3631 default :
3632 /* xgettext:c-format */
3633 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3634 opindex);
3635 abort ();
3636 }
3637}
3638
3639void
3640m32r_cgen_set_vma_operand (opindex, fields, value)
3641 int opindex;
3642 CGEN_FIELDS * fields;
3643 bfd_vma value;
3644{
3645 switch (opindex)
3646 {
3647 case M32R_OPERAND_SR :
3648 fields->f_r2 = value;
3649 break;
3650 case M32R_OPERAND_DR :
3651 fields->f_r1 = value;
3652 break;
3653 case M32R_OPERAND_SRC1 :
3654 fields->f_r1 = value;
3655 break;
3656 case M32R_OPERAND_SRC2 :
3657 fields->f_r2 = value;
3658 break;
3659 case M32R_OPERAND_SCR :
3660 fields->f_r2 = value;
3661 break;
3662 case M32R_OPERAND_DCR :
3663 fields->f_r1 = value;
3664 break;
3665 case M32R_OPERAND_SIMM8 :
3666 fields->f_simm8 = value;
3667 break;
3668 case M32R_OPERAND_SIMM16 :
3669 fields->f_simm16 = value;
3670 break;
3671 case M32R_OPERAND_UIMM4 :
3672 fields->f_uimm4 = value;
3673 break;
3674 case M32R_OPERAND_UIMM5 :
3675 fields->f_uimm5 = value;
3676 break;
3677 case M32R_OPERAND_UIMM16 :
3678 fields->f_uimm16 = value;
3679 break;
3680/* start-sanitize-m32rx */
3681 case M32R_OPERAND_IMM1 :
3682 fields->f_imm1 = value;
3683 break;
3684/* end-sanitize-m32rx */
3685/* start-sanitize-m32rx */
3686 case M32R_OPERAND_ACCD :
3687 fields->f_accd = value;
3688 break;
3689/* end-sanitize-m32rx */
3690/* start-sanitize-m32rx */
3691 case M32R_OPERAND_ACCS :
3692 fields->f_accs = value;
3693 break;
3694/* end-sanitize-m32rx */
3695/* start-sanitize-m32rx */
3696 case M32R_OPERAND_ACC :
3697 fields->f_acc = value;
3698 break;
3699/* end-sanitize-m32rx */
3700 case M32R_OPERAND_HASH :
3701 fields->f_nil = value;
3702 break;
3703 case M32R_OPERAND_HI16 :
3704 fields->f_hi16 = value;
3705 break;
3706 case M32R_OPERAND_SLO16 :
3707 fields->f_simm16 = value;
3708 break;
3709 case M32R_OPERAND_ULO16 :
3710 fields->f_uimm16 = value;
3711 break;
3712 case M32R_OPERAND_UIMM24 :
3713 fields->f_uimm24 = value;
3714 break;
3715 case M32R_OPERAND_DISP8 :
3716 fields->f_disp8 = value;
3717 break;
3718 case M32R_OPERAND_DISP16 :
3719 fields->f_disp16 = value;
3720 break;
3721 case M32R_OPERAND_DISP24 :
3722 fields->f_disp24 = value;
3723 break;
3724
3725 default :
3726 /* xgettext:c-format */
3727 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3728 opindex);
3729 abort ();
3730 }
3731}
3732
GDB Binutils - Deliverables
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