Commit | Line | Data |
---|---|---|
252b5132 RH |
1 | /* Instruction opcode table for m32r. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #include "sysdep.h" | |
26 | #include "ansidecl.h" | |
27 | #include "bfd.h" | |
28 | #include "symcat.h" | |
29 | #include "m32r-desc.h" | |
30 | #include "m32r-opc.h" | |
6bb95a0f | 31 | #include "libiberty.h" |
252b5132 RH |
32 | |
33 | /* The hash functions are recorded here to help keep assembler code out of | |
34 | the disassembler and vice versa. */ | |
35 | ||
36 | static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); | |
37 | static unsigned int asm_hash_insn PARAMS ((const char *)); | |
38 | static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); | |
39 | static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); | |
40 | ||
41 | /* Instruction formats. */ | |
42 | ||
43 | #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] | |
44 | ||
45 | static const CGEN_IFMT ifmt_empty = { | |
6bb95a0f | 46 | 0, 0, 0x0, { { 0 } } |
252b5132 RH |
47 | }; |
48 | ||
49 | static const CGEN_IFMT ifmt_add = { | |
6bb95a0f | 50 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
51 | }; |
52 | ||
53 | static const CGEN_IFMT ifmt_add3 = { | |
6bb95a0f | 54 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
55 | }; |
56 | ||
57 | static const CGEN_IFMT ifmt_and3 = { | |
6bb95a0f | 58 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } |
252b5132 RH |
59 | }; |
60 | ||
61 | static const CGEN_IFMT ifmt_or3 = { | |
6bb95a0f | 62 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } |
252b5132 RH |
63 | }; |
64 | ||
65 | static const CGEN_IFMT ifmt_addi = { | |
6bb95a0f | 66 | 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } |
252b5132 RH |
67 | }; |
68 | ||
69 | static const CGEN_IFMT ifmt_addv3 = { | |
6bb95a0f | 70 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
71 | }; |
72 | ||
73 | static const CGEN_IFMT ifmt_bc8 = { | |
6bb95a0f | 74 | 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } |
252b5132 RH |
75 | }; |
76 | ||
77 | static const CGEN_IFMT ifmt_bc24 = { | |
6bb95a0f | 78 | 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } |
252b5132 RH |
79 | }; |
80 | ||
81 | static const CGEN_IFMT ifmt_beq = { | |
6bb95a0f | 82 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } |
252b5132 RH |
83 | }; |
84 | ||
85 | static const CGEN_IFMT ifmt_beqz = { | |
6bb95a0f | 86 | 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } |
252b5132 RH |
87 | }; |
88 | ||
89 | static const CGEN_IFMT ifmt_cmp = { | |
6bb95a0f | 90 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
91 | }; |
92 | ||
93 | static const CGEN_IFMT ifmt_cmpi = { | |
6bb95a0f | 94 | 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
95 | }; |
96 | ||
1fa60b5d | 97 | static const CGEN_IFMT ifmt_cmpz = { |
6bb95a0f | 98 | 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
1fa60b5d DE |
99 | }; |
100 | ||
252b5132 | 101 | static const CGEN_IFMT ifmt_div = { |
6bb95a0f | 102 | 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
103 | }; |
104 | ||
1fa60b5d | 105 | static const CGEN_IFMT ifmt_jc = { |
6bb95a0f | 106 | 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
107 | }; |
108 | ||
109 | static const CGEN_IFMT ifmt_ld24 = { | |
6bb95a0f | 110 | 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } } |
252b5132 RH |
111 | }; |
112 | ||
113 | static const CGEN_IFMT ifmt_ldi16 = { | |
6bb95a0f | 114 | 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
115 | }; |
116 | ||
1fa60b5d | 117 | static const CGEN_IFMT ifmt_machi_a = { |
6bb95a0f | 118 | 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } } |
1fa60b5d DE |
119 | }; |
120 | ||
252b5132 | 121 | static const CGEN_IFMT ifmt_mvfachi = { |
6bb95a0f | 122 | 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
123 | }; |
124 | ||
1fa60b5d | 125 | static const CGEN_IFMT ifmt_mvfachi_a = { |
6bb95a0f | 126 | 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } |
1fa60b5d DE |
127 | }; |
128 | ||
252b5132 | 129 | static const CGEN_IFMT ifmt_mvfc = { |
6bb95a0f | 130 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
131 | }; |
132 | ||
133 | static const CGEN_IFMT ifmt_mvtachi = { | |
6bb95a0f | 134 | 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
135 | }; |
136 | ||
1fa60b5d | 137 | static const CGEN_IFMT ifmt_mvtachi_a = { |
6bb95a0f | 138 | 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } |
1fa60b5d DE |
139 | }; |
140 | ||
252b5132 | 141 | static const CGEN_IFMT ifmt_mvtc = { |
6bb95a0f | 142 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
143 | }; |
144 | ||
145 | static const CGEN_IFMT ifmt_nop = { | |
6bb95a0f | 146 | 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
147 | }; |
148 | ||
1fa60b5d | 149 | static const CGEN_IFMT ifmt_rac_dsi = { |
6bb95a0f | 150 | 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } |
1fa60b5d DE |
151 | }; |
152 | ||
252b5132 | 153 | static const CGEN_IFMT ifmt_seth = { |
6bb95a0f | 154 | 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } } |
252b5132 RH |
155 | }; |
156 | ||
157 | static const CGEN_IFMT ifmt_slli = { | |
6bb95a0f | 158 | 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } } |
252b5132 RH |
159 | }; |
160 | ||
161 | static const CGEN_IFMT ifmt_st_d = { | |
6bb95a0f | 162 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
163 | }; |
164 | ||
165 | static const CGEN_IFMT ifmt_trap = { | |
6bb95a0f | 166 | 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } } |
252b5132 RH |
167 | }; |
168 | ||
1fa60b5d | 169 | static const CGEN_IFMT ifmt_satb = { |
6bb95a0f | 170 | 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } |
1fa60b5d DE |
171 | }; |
172 | ||
252b5132 RH |
173 | #undef F |
174 | ||
175 | #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) | |
176 | #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ | |
177 | #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) | |
178 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) | |
179 | ||
180 | /* The instruction table. */ | |
181 | ||
182 | static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = | |
183 | { | |
184 | /* Special null first entry. | |
185 | A `num' value of zero is thus invalid. | |
186 | Also, the special `invalid' insn resides here. */ | |
6bb95a0f | 187 | { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, |
252b5132 RH |
188 | /* add $dr,$sr */ |
189 | { | |
190 | { 0, 0, 0, 0 }, | |
191 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
192 | & ifmt_add, { 0xa0 } | |
193 | }, | |
194 | /* add3 $dr,$sr,$hash$slo16 */ | |
195 | { | |
196 | { 0, 0, 0, 0 }, | |
197 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, | |
198 | & ifmt_add3, { 0x80a00000 } | |
199 | }, | |
200 | /* and $dr,$sr */ | |
201 | { | |
202 | { 0, 0, 0, 0 }, | |
203 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
204 | & ifmt_add, { 0xc0 } | |
205 | }, | |
206 | /* and3 $dr,$sr,$uimm16 */ | |
207 | { | |
208 | { 0, 0, 0, 0 }, | |
209 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, | |
210 | & ifmt_and3, { 0x80c00000 } | |
211 | }, | |
212 | /* or $dr,$sr */ | |
213 | { | |
214 | { 0, 0, 0, 0 }, | |
215 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
216 | & ifmt_add, { 0xe0 } | |
217 | }, | |
218 | /* or3 $dr,$sr,$hash$ulo16 */ | |
219 | { | |
220 | { 0, 0, 0, 0 }, | |
221 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, | |
222 | & ifmt_or3, { 0x80e00000 } | |
223 | }, | |
224 | /* xor $dr,$sr */ | |
225 | { | |
226 | { 0, 0, 0, 0 }, | |
227 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
228 | & ifmt_add, { 0xd0 } | |
229 | }, | |
230 | /* xor3 $dr,$sr,$uimm16 */ | |
231 | { | |
232 | { 0, 0, 0, 0 }, | |
233 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, | |
234 | & ifmt_and3, { 0x80d00000 } | |
235 | }, | |
236 | /* addi $dr,$simm8 */ | |
237 | { | |
238 | { 0, 0, 0, 0 }, | |
239 | { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, | |
240 | & ifmt_addi, { 0x4000 } | |
241 | }, | |
242 | /* addv $dr,$sr */ | |
243 | { | |
244 | { 0, 0, 0, 0 }, | |
245 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
246 | & ifmt_add, { 0x80 } | |
247 | }, | |
248 | /* addv3 $dr,$sr,$simm16 */ | |
249 | { | |
250 | { 0, 0, 0, 0 }, | |
251 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, | |
252 | & ifmt_addv3, { 0x80800000 } | |
253 | }, | |
254 | /* addx $dr,$sr */ | |
255 | { | |
256 | { 0, 0, 0, 0 }, | |
257 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
258 | & ifmt_add, { 0x90 } | |
259 | }, | |
260 | /* bc.s $disp8 */ | |
261 | { | |
262 | { 0, 0, 0, 0 }, | |
263 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
264 | & ifmt_bc8, { 0x7c00 } | |
265 | }, | |
266 | /* bc.l $disp24 */ | |
267 | { | |
268 | { 0, 0, 0, 0 }, | |
269 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
270 | & ifmt_bc24, { 0xfc000000 } | |
271 | }, | |
272 | /* beq $src1,$src2,$disp16 */ | |
273 | { | |
274 | { 0, 0, 0, 0 }, | |
275 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, | |
276 | & ifmt_beq, { 0xb0000000 } | |
277 | }, | |
278 | /* beqz $src2,$disp16 */ | |
279 | { | |
280 | { 0, 0, 0, 0 }, | |
281 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, | |
282 | & ifmt_beqz, { 0xb0800000 } | |
283 | }, | |
284 | /* bgez $src2,$disp16 */ | |
285 | { | |
286 | { 0, 0, 0, 0 }, | |
287 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, | |
288 | & ifmt_beqz, { 0xb0b00000 } | |
289 | }, | |
290 | /* bgtz $src2,$disp16 */ | |
291 | { | |
292 | { 0, 0, 0, 0 }, | |
293 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, | |
294 | & ifmt_beqz, { 0xb0d00000 } | |
295 | }, | |
296 | /* blez $src2,$disp16 */ | |
297 | { | |
298 | { 0, 0, 0, 0 }, | |
299 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, | |
300 | & ifmt_beqz, { 0xb0c00000 } | |
301 | }, | |
302 | /* bltz $src2,$disp16 */ | |
303 | { | |
304 | { 0, 0, 0, 0 }, | |
305 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, | |
306 | & ifmt_beqz, { 0xb0a00000 } | |
307 | }, | |
308 | /* bnez $src2,$disp16 */ | |
309 | { | |
310 | { 0, 0, 0, 0 }, | |
311 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, | |
312 | & ifmt_beqz, { 0xb0900000 } | |
313 | }, | |
314 | /* bl.s $disp8 */ | |
315 | { | |
316 | { 0, 0, 0, 0 }, | |
317 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
318 | & ifmt_bc8, { 0x7e00 } | |
319 | }, | |
320 | /* bl.l $disp24 */ | |
321 | { | |
322 | { 0, 0, 0, 0 }, | |
323 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
324 | & ifmt_bc24, { 0xfe000000 } | |
325 | }, | |
1fa60b5d DE |
326 | /* bcl.s $disp8 */ |
327 | { | |
328 | { 0, 0, 0, 0 }, | |
329 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
330 | & ifmt_bc8, { 0x7800 } | |
331 | }, | |
332 | /* bcl.l $disp24 */ | |
333 | { | |
334 | { 0, 0, 0, 0 }, | |
335 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
336 | & ifmt_bc24, { 0xf8000000 } | |
337 | }, | |
252b5132 RH |
338 | /* bnc.s $disp8 */ |
339 | { | |
340 | { 0, 0, 0, 0 }, | |
341 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
342 | & ifmt_bc8, { 0x7d00 } | |
343 | }, | |
344 | /* bnc.l $disp24 */ | |
345 | { | |
346 | { 0, 0, 0, 0 }, | |
347 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
348 | & ifmt_bc24, { 0xfd000000 } | |
349 | }, | |
350 | /* bne $src1,$src2,$disp16 */ | |
351 | { | |
352 | { 0, 0, 0, 0 }, | |
353 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, | |
354 | & ifmt_beq, { 0xb0100000 } | |
355 | }, | |
356 | /* bra.s $disp8 */ | |
357 | { | |
358 | { 0, 0, 0, 0 }, | |
359 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
360 | & ifmt_bc8, { 0x7f00 } | |
361 | }, | |
362 | /* bra.l $disp24 */ | |
363 | { | |
364 | { 0, 0, 0, 0 }, | |
365 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
366 | & ifmt_bc24, { 0xff000000 } | |
367 | }, | |
1fa60b5d DE |
368 | /* bncl.s $disp8 */ |
369 | { | |
370 | { 0, 0, 0, 0 }, | |
371 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
372 | & ifmt_bc8, { 0x7900 } | |
373 | }, | |
374 | /* bncl.l $disp24 */ | |
375 | { | |
376 | { 0, 0, 0, 0 }, | |
377 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
378 | & ifmt_bc24, { 0xf9000000 } | |
379 | }, | |
252b5132 RH |
380 | /* cmp $src1,$src2 */ |
381 | { | |
382 | { 0, 0, 0, 0 }, | |
383 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
384 | & ifmt_cmp, { 0x40 } | |
385 | }, | |
386 | /* cmpi $src2,$simm16 */ | |
387 | { | |
388 | { 0, 0, 0, 0 }, | |
389 | { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, | |
390 | & ifmt_cmpi, { 0x80400000 } | |
391 | }, | |
392 | /* cmpu $src1,$src2 */ | |
393 | { | |
394 | { 0, 0, 0, 0 }, | |
395 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
396 | & ifmt_cmp, { 0x50 } | |
397 | }, | |
398 | /* cmpui $src2,$simm16 */ | |
399 | { | |
400 | { 0, 0, 0, 0 }, | |
401 | { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, | |
402 | & ifmt_cmpi, { 0x80500000 } | |
403 | }, | |
1fa60b5d DE |
404 | /* cmpeq $src1,$src2 */ |
405 | { | |
406 | { 0, 0, 0, 0 }, | |
407 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
408 | & ifmt_cmp, { 0x60 } | |
409 | }, | |
410 | /* cmpz $src2 */ | |
411 | { | |
412 | { 0, 0, 0, 0 }, | |
413 | { { MNEM, ' ', OP (SRC2), 0 } }, | |
414 | & ifmt_cmpz, { 0x70 } | |
415 | }, | |
252b5132 RH |
416 | /* div $dr,$sr */ |
417 | { | |
418 | { 0, 0, 0, 0 }, | |
419 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
420 | & ifmt_div, { 0x90000000 } | |
421 | }, | |
422 | /* divu $dr,$sr */ | |
423 | { | |
424 | { 0, 0, 0, 0 }, | |
425 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
426 | & ifmt_div, { 0x90100000 } | |
427 | }, | |
428 | /* rem $dr,$sr */ | |
429 | { | |
430 | { 0, 0, 0, 0 }, | |
431 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
432 | & ifmt_div, { 0x90200000 } | |
433 | }, | |
434 | /* remu $dr,$sr */ | |
435 | { | |
436 | { 0, 0, 0, 0 }, | |
437 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
438 | & ifmt_div, { 0x90300000 } | |
439 | }, | |
1fa60b5d DE |
440 | /* divh $dr,$sr */ |
441 | { | |
442 | { 0, 0, 0, 0 }, | |
443 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
444 | & ifmt_div, { 0x90000010 } | |
445 | }, | |
446 | /* jc $sr */ | |
447 | { | |
448 | { 0, 0, 0, 0 }, | |
449 | { { MNEM, ' ', OP (SR), 0 } }, | |
450 | & ifmt_jc, { 0x1cc0 } | |
451 | }, | |
452 | /* jnc $sr */ | |
453 | { | |
454 | { 0, 0, 0, 0 }, | |
455 | { { MNEM, ' ', OP (SR), 0 } }, | |
456 | & ifmt_jc, { 0x1dc0 } | |
457 | }, | |
252b5132 RH |
458 | /* jl $sr */ |
459 | { | |
460 | { 0, 0, 0, 0 }, | |
461 | { { MNEM, ' ', OP (SR), 0 } }, | |
1fa60b5d | 462 | & ifmt_jc, { 0x1ec0 } |
252b5132 RH |
463 | }, |
464 | /* jmp $sr */ | |
465 | { | |
466 | { 0, 0, 0, 0 }, | |
467 | { { MNEM, ' ', OP (SR), 0 } }, | |
1fa60b5d | 468 | & ifmt_jc, { 0x1fc0 } |
252b5132 RH |
469 | }, |
470 | /* ld $dr,@$sr */ | |
471 | { | |
472 | { 0, 0, 0, 0 }, | |
473 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, | |
474 | & ifmt_add, { 0x20c0 } | |
475 | }, | |
476 | /* ld $dr,@($slo16,$sr) */ | |
477 | { | |
478 | { 0, 0, 0, 0 }, | |
479 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, | |
480 | & ifmt_add3, { 0xa0c00000 } | |
481 | }, | |
482 | /* ldb $dr,@$sr */ | |
483 | { | |
484 | { 0, 0, 0, 0 }, | |
485 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, | |
486 | & ifmt_add, { 0x2080 } | |
487 | }, | |
488 | /* ldb $dr,@($slo16,$sr) */ | |
489 | { | |
490 | { 0, 0, 0, 0 }, | |
491 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, | |
492 | & ifmt_add3, { 0xa0800000 } | |
493 | }, | |
494 | /* ldh $dr,@$sr */ | |
495 | { | |
496 | { 0, 0, 0, 0 }, | |
497 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, | |
498 | & ifmt_add, { 0x20a0 } | |
499 | }, | |
500 | /* ldh $dr,@($slo16,$sr) */ | |
501 | { | |
502 | { 0, 0, 0, 0 }, | |
503 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, | |
504 | & ifmt_add3, { 0xa0a00000 } | |
505 | }, | |
506 | /* ldub $dr,@$sr */ | |
507 | { | |
508 | { 0, 0, 0, 0 }, | |
509 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, | |
510 | & ifmt_add, { 0x2090 } | |
511 | }, | |
512 | /* ldub $dr,@($slo16,$sr) */ | |
513 | { | |
514 | { 0, 0, 0, 0 }, | |
515 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, | |
516 | & ifmt_add3, { 0xa0900000 } | |
517 | }, | |
518 | /* lduh $dr,@$sr */ | |
519 | { | |
520 | { 0, 0, 0, 0 }, | |
521 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, | |
522 | & ifmt_add, { 0x20b0 } | |
523 | }, | |
524 | /* lduh $dr,@($slo16,$sr) */ | |
525 | { | |
526 | { 0, 0, 0, 0 }, | |
527 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, | |
528 | & ifmt_add3, { 0xa0b00000 } | |
529 | }, | |
530 | /* ld $dr,@$sr+ */ | |
531 | { | |
532 | { 0, 0, 0, 0 }, | |
533 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, | |
534 | & ifmt_add, { 0x20e0 } | |
535 | }, | |
536 | /* ld24 $dr,$uimm24 */ | |
537 | { | |
538 | { 0, 0, 0, 0 }, | |
539 | { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, | |
540 | & ifmt_ld24, { 0xe0000000 } | |
541 | }, | |
542 | /* ldi8 $dr,$simm8 */ | |
543 | { | |
544 | { 0, 0, 0, 0 }, | |
545 | { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, | |
546 | & ifmt_addi, { 0x6000 } | |
547 | }, | |
548 | /* ldi16 $dr,$hash$slo16 */ | |
549 | { | |
550 | { 0, 0, 0, 0 }, | |
551 | { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, | |
552 | & ifmt_ldi16, { 0x90f00000 } | |
553 | }, | |
554 | /* lock $dr,@$sr */ | |
555 | { | |
556 | { 0, 0, 0, 0 }, | |
557 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, | |
558 | & ifmt_add, { 0x20d0 } | |
559 | }, | |
560 | /* machi $src1,$src2 */ | |
561 | { | |
562 | { 0, 0, 0, 0 }, | |
563 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
564 | & ifmt_cmp, { 0x3040 } | |
565 | }, | |
1fa60b5d DE |
566 | /* machi $src1,$src2,$acc */ |
567 | { | |
568 | { 0, 0, 0, 0 }, | |
569 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
570 | & ifmt_machi_a, { 0x3040 } | |
571 | }, | |
252b5132 RH |
572 | /* maclo $src1,$src2 */ |
573 | { | |
574 | { 0, 0, 0, 0 }, | |
575 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
576 | & ifmt_cmp, { 0x3050 } | |
577 | }, | |
1fa60b5d DE |
578 | /* maclo $src1,$src2,$acc */ |
579 | { | |
580 | { 0, 0, 0, 0 }, | |
581 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
582 | & ifmt_machi_a, { 0x3050 } | |
583 | }, | |
252b5132 RH |
584 | /* macwhi $src1,$src2 */ |
585 | { | |
586 | { 0, 0, 0, 0 }, | |
587 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
588 | & ifmt_cmp, { 0x3060 } | |
589 | }, | |
1fa60b5d DE |
590 | /* macwhi $src1,$src2,$acc */ |
591 | { | |
592 | { 0, 0, 0, 0 }, | |
593 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
594 | & ifmt_machi_a, { 0x3060 } | |
595 | }, | |
252b5132 RH |
596 | /* macwlo $src1,$src2 */ |
597 | { | |
598 | { 0, 0, 0, 0 }, | |
599 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
600 | & ifmt_cmp, { 0x3070 } | |
601 | }, | |
1fa60b5d DE |
602 | /* macwlo $src1,$src2,$acc */ |
603 | { | |
604 | { 0, 0, 0, 0 }, | |
605 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
606 | & ifmt_machi_a, { 0x3070 } | |
607 | }, | |
252b5132 RH |
608 | /* mul $dr,$sr */ |
609 | { | |
610 | { 0, 0, 0, 0 }, | |
611 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
612 | & ifmt_add, { 0x1060 } | |
613 | }, | |
614 | /* mulhi $src1,$src2 */ | |
615 | { | |
616 | { 0, 0, 0, 0 }, | |
617 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
618 | & ifmt_cmp, { 0x3000 } | |
619 | }, | |
1fa60b5d DE |
620 | /* mulhi $src1,$src2,$acc */ |
621 | { | |
622 | { 0, 0, 0, 0 }, | |
623 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
624 | & ifmt_machi_a, { 0x3000 } | |
625 | }, | |
252b5132 RH |
626 | /* mullo $src1,$src2 */ |
627 | { | |
628 | { 0, 0, 0, 0 }, | |
629 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
630 | & ifmt_cmp, { 0x3010 } | |
631 | }, | |
1fa60b5d DE |
632 | /* mullo $src1,$src2,$acc */ |
633 | { | |
634 | { 0, 0, 0, 0 }, | |
635 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
636 | & ifmt_machi_a, { 0x3010 } | |
637 | }, | |
252b5132 RH |
638 | /* mulwhi $src1,$src2 */ |
639 | { | |
640 | { 0, 0, 0, 0 }, | |
641 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
642 | & ifmt_cmp, { 0x3020 } | |
643 | }, | |
1fa60b5d DE |
644 | /* mulwhi $src1,$src2,$acc */ |
645 | { | |
646 | { 0, 0, 0, 0 }, | |
647 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
648 | & ifmt_machi_a, { 0x3020 } | |
649 | }, | |
252b5132 RH |
650 | /* mulwlo $src1,$src2 */ |
651 | { | |
652 | { 0, 0, 0, 0 }, | |
653 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
654 | & ifmt_cmp, { 0x3030 } | |
655 | }, | |
1fa60b5d DE |
656 | /* mulwlo $src1,$src2,$acc */ |
657 | { | |
658 | { 0, 0, 0, 0 }, | |
659 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, | |
660 | & ifmt_machi_a, { 0x3030 } | |
661 | }, | |
252b5132 RH |
662 | /* mv $dr,$sr */ |
663 | { | |
664 | { 0, 0, 0, 0 }, | |
665 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
666 | & ifmt_add, { 0x1080 } | |
667 | }, | |
668 | /* mvfachi $dr */ | |
669 | { | |
670 | { 0, 0, 0, 0 }, | |
671 | { { MNEM, ' ', OP (DR), 0 } }, | |
672 | & ifmt_mvfachi, { 0x50f0 } | |
673 | }, | |
1fa60b5d DE |
674 | /* mvfachi $dr,$accs */ |
675 | { | |
676 | { 0, 0, 0, 0 }, | |
677 | { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, | |
678 | & ifmt_mvfachi_a, { 0x50f0 } | |
679 | }, | |
252b5132 RH |
680 | /* mvfaclo $dr */ |
681 | { | |
682 | { 0, 0, 0, 0 }, | |
683 | { { MNEM, ' ', OP (DR), 0 } }, | |
684 | & ifmt_mvfachi, { 0x50f1 } | |
685 | }, | |
1fa60b5d DE |
686 | /* mvfaclo $dr,$accs */ |
687 | { | |
688 | { 0, 0, 0, 0 }, | |
689 | { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, | |
690 | & ifmt_mvfachi_a, { 0x50f1 } | |
691 | }, | |
252b5132 RH |
692 | /* mvfacmi $dr */ |
693 | { | |
694 | { 0, 0, 0, 0 }, | |
695 | { { MNEM, ' ', OP (DR), 0 } }, | |
696 | & ifmt_mvfachi, { 0x50f2 } | |
697 | }, | |
1fa60b5d DE |
698 | /* mvfacmi $dr,$accs */ |
699 | { | |
700 | { 0, 0, 0, 0 }, | |
701 | { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, | |
702 | & ifmt_mvfachi_a, { 0x50f2 } | |
703 | }, | |
252b5132 RH |
704 | /* mvfc $dr,$scr */ |
705 | { | |
706 | { 0, 0, 0, 0 }, | |
707 | { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, | |
708 | & ifmt_mvfc, { 0x1090 } | |
709 | }, | |
710 | /* mvtachi $src1 */ | |
711 | { | |
712 | { 0, 0, 0, 0 }, | |
713 | { { MNEM, ' ', OP (SRC1), 0 } }, | |
714 | & ifmt_mvtachi, { 0x5070 } | |
715 | }, | |
1fa60b5d DE |
716 | /* mvtachi $src1,$accs */ |
717 | { | |
718 | { 0, 0, 0, 0 }, | |
719 | { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, | |
720 | & ifmt_mvtachi_a, { 0x5070 } | |
721 | }, | |
252b5132 RH |
722 | /* mvtaclo $src1 */ |
723 | { | |
724 | { 0, 0, 0, 0 }, | |
725 | { { MNEM, ' ', OP (SRC1), 0 } }, | |
726 | & ifmt_mvtachi, { 0x5071 } | |
727 | }, | |
1fa60b5d DE |
728 | /* mvtaclo $src1,$accs */ |
729 | { | |
730 | { 0, 0, 0, 0 }, | |
731 | { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, | |
732 | & ifmt_mvtachi_a, { 0x5071 } | |
733 | }, | |
252b5132 RH |
734 | /* mvtc $sr,$dcr */ |
735 | { | |
736 | { 0, 0, 0, 0 }, | |
737 | { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, | |
738 | & ifmt_mvtc, { 0x10a0 } | |
739 | }, | |
740 | /* neg $dr,$sr */ | |
741 | { | |
742 | { 0, 0, 0, 0 }, | |
743 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
744 | & ifmt_add, { 0x30 } | |
745 | }, | |
746 | /* nop */ | |
747 | { | |
748 | { 0, 0, 0, 0 }, | |
749 | { { MNEM, 0 } }, | |
750 | & ifmt_nop, { 0x7000 } | |
751 | }, | |
752 | /* not $dr,$sr */ | |
753 | { | |
754 | { 0, 0, 0, 0 }, | |
755 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
756 | & ifmt_add, { 0xb0 } | |
757 | }, | |
758 | /* rac */ | |
759 | { | |
760 | { 0, 0, 0, 0 }, | |
761 | { { MNEM, 0 } }, | |
762 | & ifmt_nop, { 0x5090 } | |
763 | }, | |
1fa60b5d DE |
764 | /* rac $accd,$accs,$imm1 */ |
765 | { | |
766 | { 0, 0, 0, 0 }, | |
767 | { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, | |
768 | & ifmt_rac_dsi, { 0x5090 } | |
769 | }, | |
252b5132 RH |
770 | /* rach */ |
771 | { | |
772 | { 0, 0, 0, 0 }, | |
773 | { { MNEM, 0 } }, | |
774 | & ifmt_nop, { 0x5080 } | |
775 | }, | |
1fa60b5d DE |
776 | /* rach $accd,$accs,$imm1 */ |
777 | { | |
778 | { 0, 0, 0, 0 }, | |
779 | { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, | |
780 | & ifmt_rac_dsi, { 0x5080 } | |
781 | }, | |
252b5132 RH |
782 | /* rte */ |
783 | { | |
784 | { 0, 0, 0, 0 }, | |
785 | { { MNEM, 0 } }, | |
786 | & ifmt_nop, { 0x10d6 } | |
787 | }, | |
788 | /* seth $dr,$hash$hi16 */ | |
789 | { | |
790 | { 0, 0, 0, 0 }, | |
791 | { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, | |
792 | & ifmt_seth, { 0xd0c00000 } | |
793 | }, | |
794 | /* sll $dr,$sr */ | |
795 | { | |
796 | { 0, 0, 0, 0 }, | |
797 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
798 | & ifmt_add, { 0x1040 } | |
799 | }, | |
800 | /* sll3 $dr,$sr,$simm16 */ | |
801 | { | |
802 | { 0, 0, 0, 0 }, | |
803 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, | |
804 | & ifmt_addv3, { 0x90c00000 } | |
805 | }, | |
806 | /* slli $dr,$uimm5 */ | |
807 | { | |
808 | { 0, 0, 0, 0 }, | |
809 | { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, | |
810 | & ifmt_slli, { 0x5040 } | |
811 | }, | |
812 | /* sra $dr,$sr */ | |
813 | { | |
814 | { 0, 0, 0, 0 }, | |
815 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
816 | & ifmt_add, { 0x1020 } | |
817 | }, | |
818 | /* sra3 $dr,$sr,$simm16 */ | |
819 | { | |
820 | { 0, 0, 0, 0 }, | |
821 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, | |
822 | & ifmt_addv3, { 0x90a00000 } | |
823 | }, | |
824 | /* srai $dr,$uimm5 */ | |
825 | { | |
826 | { 0, 0, 0, 0 }, | |
827 | { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, | |
828 | & ifmt_slli, { 0x5020 } | |
829 | }, | |
830 | /* srl $dr,$sr */ | |
831 | { | |
832 | { 0, 0, 0, 0 }, | |
833 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
834 | & ifmt_add, { 0x1000 } | |
835 | }, | |
836 | /* srl3 $dr,$sr,$simm16 */ | |
837 | { | |
838 | { 0, 0, 0, 0 }, | |
839 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, | |
840 | & ifmt_addv3, { 0x90800000 } | |
841 | }, | |
842 | /* srli $dr,$uimm5 */ | |
843 | { | |
844 | { 0, 0, 0, 0 }, | |
845 | { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, | |
846 | & ifmt_slli, { 0x5000 } | |
847 | }, | |
848 | /* st $src1,@$src2 */ | |
849 | { | |
850 | { 0, 0, 0, 0 }, | |
851 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, | |
852 | & ifmt_cmp, { 0x2040 } | |
853 | }, | |
854 | /* st $src1,@($slo16,$src2) */ | |
855 | { | |
856 | { 0, 0, 0, 0 }, | |
857 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, | |
858 | & ifmt_st_d, { 0xa0400000 } | |
859 | }, | |
860 | /* stb $src1,@$src2 */ | |
861 | { | |
862 | { 0, 0, 0, 0 }, | |
863 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, | |
864 | & ifmt_cmp, { 0x2000 } | |
865 | }, | |
866 | /* stb $src1,@($slo16,$src2) */ | |
867 | { | |
868 | { 0, 0, 0, 0 }, | |
869 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, | |
870 | & ifmt_st_d, { 0xa0000000 } | |
871 | }, | |
872 | /* sth $src1,@$src2 */ | |
873 | { | |
874 | { 0, 0, 0, 0 }, | |
875 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, | |
876 | & ifmt_cmp, { 0x2020 } | |
877 | }, | |
878 | /* sth $src1,@($slo16,$src2) */ | |
879 | { | |
880 | { 0, 0, 0, 0 }, | |
881 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, | |
882 | & ifmt_st_d, { 0xa0200000 } | |
883 | }, | |
884 | /* st $src1,@+$src2 */ | |
885 | { | |
886 | { 0, 0, 0, 0 }, | |
887 | { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, | |
888 | & ifmt_cmp, { 0x2060 } | |
889 | }, | |
890 | /* st $src1,@-$src2 */ | |
891 | { | |
892 | { 0, 0, 0, 0 }, | |
893 | { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, | |
894 | & ifmt_cmp, { 0x2070 } | |
895 | }, | |
896 | /* sub $dr,$sr */ | |
897 | { | |
898 | { 0, 0, 0, 0 }, | |
899 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
900 | & ifmt_add, { 0x20 } | |
901 | }, | |
902 | /* subv $dr,$sr */ | |
903 | { | |
904 | { 0, 0, 0, 0 }, | |
905 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
906 | & ifmt_add, { 0x0 } | |
907 | }, | |
908 | /* subx $dr,$sr */ | |
909 | { | |
910 | { 0, 0, 0, 0 }, | |
911 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
912 | & ifmt_add, { 0x10 } | |
913 | }, | |
914 | /* trap $uimm4 */ | |
915 | { | |
916 | { 0, 0, 0, 0 }, | |
917 | { { MNEM, ' ', OP (UIMM4), 0 } }, | |
918 | & ifmt_trap, { 0x10f0 } | |
919 | }, | |
920 | /* unlock $src1,@$src2 */ | |
921 | { | |
922 | { 0, 0, 0, 0 }, | |
923 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, | |
924 | & ifmt_cmp, { 0x2050 } | |
925 | }, | |
1fa60b5d DE |
926 | /* satb $dr,$sr */ |
927 | { | |
928 | { 0, 0, 0, 0 }, | |
929 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
930 | & ifmt_satb, { 0x80600300 } | |
931 | }, | |
932 | /* sath $dr,$sr */ | |
933 | { | |
934 | { 0, 0, 0, 0 }, | |
935 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
936 | & ifmt_satb, { 0x80600200 } | |
937 | }, | |
938 | /* sat $dr,$sr */ | |
939 | { | |
940 | { 0, 0, 0, 0 }, | |
941 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, | |
942 | & ifmt_satb, { 0x80600000 } | |
943 | }, | |
944 | /* pcmpbz $src2 */ | |
945 | { | |
946 | { 0, 0, 0, 0 }, | |
947 | { { MNEM, ' ', OP (SRC2), 0 } }, | |
948 | & ifmt_cmpz, { 0x370 } | |
949 | }, | |
950 | /* sadd */ | |
951 | { | |
952 | { 0, 0, 0, 0 }, | |
953 | { { MNEM, 0 } }, | |
954 | & ifmt_nop, { 0x50e4 } | |
955 | }, | |
956 | /* macwu1 $src1,$src2 */ | |
957 | { | |
958 | { 0, 0, 0, 0 }, | |
959 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
960 | & ifmt_cmp, { 0x50b0 } | |
961 | }, | |
962 | /* msblo $src1,$src2 */ | |
963 | { | |
964 | { 0, 0, 0, 0 }, | |
965 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
966 | & ifmt_cmp, { 0x50d0 } | |
967 | }, | |
968 | /* mulwu1 $src1,$src2 */ | |
969 | { | |
970 | { 0, 0, 0, 0 }, | |
971 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
972 | & ifmt_cmp, { 0x50a0 } | |
973 | }, | |
974 | /* maclh1 $src1,$src2 */ | |
975 | { | |
976 | { 0, 0, 0, 0 }, | |
977 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, | |
978 | & ifmt_cmp, { 0x50c0 } | |
979 | }, | |
980 | /* sc */ | |
981 | { | |
982 | { 0, 0, 0, 0 }, | |
983 | { { MNEM, 0 } }, | |
984 | & ifmt_nop, { 0x7401 } | |
985 | }, | |
986 | /* snc */ | |
987 | { | |
988 | { 0, 0, 0, 0 }, | |
989 | { { MNEM, 0 } }, | |
990 | & ifmt_nop, { 0x7501 } | |
991 | }, | |
252b5132 RH |
992 | }; |
993 | ||
994 | #undef A | |
995 | #undef MNEM | |
996 | #undef OPERAND | |
997 | #undef OP | |
998 | ||
999 | /* Formats for ALIAS macro-insns. */ | |
1000 | ||
1001 | #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] | |
1002 | ||
1003 | static const CGEN_IFMT ifmt_bc8r = { | |
6bb95a0f | 1004 | 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } |
252b5132 RH |
1005 | }; |
1006 | ||
1007 | static const CGEN_IFMT ifmt_bc24r = { | |
6bb95a0f | 1008 | 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } |
252b5132 RH |
1009 | }; |
1010 | ||
1011 | static const CGEN_IFMT ifmt_bl8r = { | |
6bb95a0f | 1012 | 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } |
252b5132 RH |
1013 | }; |
1014 | ||
1015 | static const CGEN_IFMT ifmt_bl24r = { | |
6bb95a0f | 1016 | 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } |
252b5132 RH |
1017 | }; |
1018 | ||
1fa60b5d | 1019 | static const CGEN_IFMT ifmt_bcl8r = { |
6bb95a0f | 1020 | 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } |
1fa60b5d DE |
1021 | }; |
1022 | ||
1023 | static const CGEN_IFMT ifmt_bcl24r = { | |
6bb95a0f | 1024 | 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } |
1fa60b5d DE |
1025 | }; |
1026 | ||
252b5132 | 1027 | static const CGEN_IFMT ifmt_bnc8r = { |
6bb95a0f | 1028 | 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } |
252b5132 RH |
1029 | }; |
1030 | ||
1031 | static const CGEN_IFMT ifmt_bnc24r = { | |
6bb95a0f | 1032 | 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } |
252b5132 RH |
1033 | }; |
1034 | ||
1035 | static const CGEN_IFMT ifmt_bra8r = { | |
6bb95a0f | 1036 | 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } |
252b5132 RH |
1037 | }; |
1038 | ||
1039 | static const CGEN_IFMT ifmt_bra24r = { | |
6bb95a0f | 1040 | 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } |
252b5132 RH |
1041 | }; |
1042 | ||
1fa60b5d | 1043 | static const CGEN_IFMT ifmt_bncl8r = { |
6bb95a0f | 1044 | 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } |
1fa60b5d DE |
1045 | }; |
1046 | ||
1047 | static const CGEN_IFMT ifmt_bncl24r = { | |
6bb95a0f | 1048 | 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } |
1fa60b5d DE |
1049 | }; |
1050 | ||
252b5132 | 1051 | static const CGEN_IFMT ifmt_ld_2 = { |
6bb95a0f | 1052 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1053 | }; |
1054 | ||
1055 | static const CGEN_IFMT ifmt_ld_d2 = { | |
6bb95a0f | 1056 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1057 | }; |
1058 | ||
1059 | static const CGEN_IFMT ifmt_ldb_2 = { | |
6bb95a0f | 1060 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1061 | }; |
1062 | ||
1063 | static const CGEN_IFMT ifmt_ldb_d2 = { | |
6bb95a0f | 1064 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1065 | }; |
1066 | ||
1067 | static const CGEN_IFMT ifmt_ldh_2 = { | |
6bb95a0f | 1068 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1069 | }; |
1070 | ||
1071 | static const CGEN_IFMT ifmt_ldh_d2 = { | |
6bb95a0f | 1072 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1073 | }; |
1074 | ||
1075 | static const CGEN_IFMT ifmt_ldub_2 = { | |
6bb95a0f | 1076 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1077 | }; |
1078 | ||
1079 | static const CGEN_IFMT ifmt_ldub_d2 = { | |
6bb95a0f | 1080 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1081 | }; |
1082 | ||
1083 | static const CGEN_IFMT ifmt_lduh_2 = { | |
6bb95a0f | 1084 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1085 | }; |
1086 | ||
1087 | static const CGEN_IFMT ifmt_lduh_d2 = { | |
6bb95a0f | 1088 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1089 | }; |
1090 | ||
1091 | static const CGEN_IFMT ifmt_pop = { | |
6bb95a0f | 1092 | 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1093 | }; |
1094 | ||
1095 | static const CGEN_IFMT ifmt_ldi8a = { | |
6bb95a0f | 1096 | 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } |
252b5132 RH |
1097 | }; |
1098 | ||
1099 | static const CGEN_IFMT ifmt_ldi16a = { | |
6bb95a0f | 1100 | 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1101 | }; |
1102 | ||
1fa60b5d | 1103 | static const CGEN_IFMT ifmt_rac_d = { |
6bb95a0f | 1104 | 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } |
1fa60b5d DE |
1105 | }; |
1106 | ||
1107 | static const CGEN_IFMT ifmt_rac_ds = { | |
6bb95a0f | 1108 | 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } |
1fa60b5d DE |
1109 | }; |
1110 | ||
1111 | static const CGEN_IFMT ifmt_rach_d = { | |
6bb95a0f | 1112 | 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } |
1fa60b5d DE |
1113 | }; |
1114 | ||
1115 | static const CGEN_IFMT ifmt_rach_ds = { | |
6bb95a0f | 1116 | 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } |
1fa60b5d DE |
1117 | }; |
1118 | ||
252b5132 | 1119 | static const CGEN_IFMT ifmt_st_2 = { |
6bb95a0f | 1120 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1121 | }; |
1122 | ||
1123 | static const CGEN_IFMT ifmt_st_d2 = { | |
6bb95a0f | 1124 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1125 | }; |
1126 | ||
1127 | static const CGEN_IFMT ifmt_stb_2 = { | |
6bb95a0f | 1128 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1129 | }; |
1130 | ||
1131 | static const CGEN_IFMT ifmt_stb_d2 = { | |
6bb95a0f | 1132 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1133 | }; |
1134 | ||
1135 | static const CGEN_IFMT ifmt_sth_2 = { | |
6bb95a0f | 1136 | 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1137 | }; |
1138 | ||
1139 | static const CGEN_IFMT ifmt_sth_d2 = { | |
6bb95a0f | 1140 | 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } |
252b5132 RH |
1141 | }; |
1142 | ||
1143 | static const CGEN_IFMT ifmt_push = { | |
6bb95a0f | 1144 | 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } |
252b5132 RH |
1145 | }; |
1146 | ||
1147 | #undef F | |
1148 | ||
1149 | /* Each non-simple macro entry points to an array of expansion possibilities. */ | |
1150 | ||
1151 | #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) | |
1152 | #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ | |
1153 | #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) | |
1154 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) | |
1155 | ||
1156 | /* The macro instruction table. */ | |
1157 | ||
1158 | static const CGEN_IBASE m32r_cgen_macro_insn_table[] = | |
1159 | { | |
1160 | /* bc $disp8 */ | |
1161 | { | |
1162 | -1, "bc8r", "bc", 16, | |
1fa60b5d | 1163 | { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1164 | }, |
1165 | /* bc $disp24 */ | |
1166 | { | |
1167 | -1, "bc24r", "bc", 32, | |
1fa60b5d | 1168 | { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1169 | }, |
1170 | /* bl $disp8 */ | |
1171 | { | |
1172 | -1, "bl8r", "bl", 16, | |
1fa60b5d | 1173 | { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1174 | }, |
1175 | /* bl $disp24 */ | |
1176 | { | |
1177 | -1, "bl24r", "bl", 32, | |
1fa60b5d DE |
1178 | { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
1179 | }, | |
1180 | /* bcl $disp8 */ | |
1181 | { | |
1182 | -1, "bcl8r", "bcl", 16, | |
1183 | { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } | |
1184 | }, | |
1185 | /* bcl $disp24 */ | |
1186 | { | |
1187 | -1, "bcl24r", "bcl", 32, | |
1188 | { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } | |
252b5132 RH |
1189 | }, |
1190 | /* bnc $disp8 */ | |
1191 | { | |
1192 | -1, "bnc8r", "bnc", 16, | |
1fa60b5d | 1193 | { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1194 | }, |
1195 | /* bnc $disp24 */ | |
1196 | { | |
1197 | -1, "bnc24r", "bnc", 32, | |
1fa60b5d | 1198 | { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1199 | }, |
1200 | /* bra $disp8 */ | |
1201 | { | |
1202 | -1, "bra8r", "bra", 16, | |
1fa60b5d | 1203 | { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1204 | }, |
1205 | /* bra $disp24 */ | |
1206 | { | |
1207 | -1, "bra24r", "bra", 32, | |
1fa60b5d DE |
1208 | { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
1209 | }, | |
1210 | /* bncl $disp8 */ | |
1211 | { | |
1212 | -1, "bncl8r", "bncl", 16, | |
1213 | { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } | |
1214 | }, | |
1215 | /* bncl $disp24 */ | |
1216 | { | |
1217 | -1, "bncl24r", "bncl", 32, | |
1218 | { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } | |
252b5132 RH |
1219 | }, |
1220 | /* ld $dr,@($sr) */ | |
1221 | { | |
1222 | -1, "ld-2", "ld", 16, | |
1fa60b5d | 1223 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1224 | }, |
1225 | /* ld $dr,@($sr,$slo16) */ | |
1226 | { | |
1227 | -1, "ld-d2", "ld", 32, | |
1fa60b5d | 1228 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1229 | }, |
1230 | /* ldb $dr,@($sr) */ | |
1231 | { | |
1232 | -1, "ldb-2", "ldb", 16, | |
1fa60b5d | 1233 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1234 | }, |
1235 | /* ldb $dr,@($sr,$slo16) */ | |
1236 | { | |
1237 | -1, "ldb-d2", "ldb", 32, | |
1fa60b5d | 1238 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1239 | }, |
1240 | /* ldh $dr,@($sr) */ | |
1241 | { | |
1242 | -1, "ldh-2", "ldh", 16, | |
1fa60b5d | 1243 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1244 | }, |
1245 | /* ldh $dr,@($sr,$slo16) */ | |
1246 | { | |
1247 | -1, "ldh-d2", "ldh", 32, | |
1fa60b5d | 1248 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1249 | }, |
1250 | /* ldub $dr,@($sr) */ | |
1251 | { | |
1252 | -1, "ldub-2", "ldub", 16, | |
1fa60b5d | 1253 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1254 | }, |
1255 | /* ldub $dr,@($sr,$slo16) */ | |
1256 | { | |
1257 | -1, "ldub-d2", "ldub", 32, | |
1fa60b5d | 1258 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1259 | }, |
1260 | /* lduh $dr,@($sr) */ | |
1261 | { | |
1262 | -1, "lduh-2", "lduh", 16, | |
1fa60b5d | 1263 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1264 | }, |
1265 | /* lduh $dr,@($sr,$slo16) */ | |
1266 | { | |
1267 | -1, "lduh-d2", "lduh", 32, | |
1fa60b5d | 1268 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1269 | }, |
1270 | /* pop $dr */ | |
1271 | { | |
1272 | -1, "pop", "pop", 16, | |
1fa60b5d | 1273 | { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1274 | }, |
1275 | /* ldi $dr,$simm8 */ | |
1276 | { | |
1277 | -1, "ldi8a", "ldi", 16, | |
1fa60b5d | 1278 | { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
1279 | }, |
1280 | /* ldi $dr,$hash$slo16 */ | |
1281 | { | |
1282 | -1, "ldi16a", "ldi", 32, | |
1fa60b5d DE |
1283 | { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
1284 | }, | |
1285 | /* rac $accd */ | |
1286 | { | |
1287 | -1, "rac-d", "rac", 16, | |
1288 | { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } | |
1289 | }, | |
1290 | /* rac $accd,$accs */ | |
1291 | { | |
1292 | -1, "rac-ds", "rac", 16, | |
1293 | { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } | |
1294 | }, | |
1295 | /* rach $accd */ | |
1296 | { | |
1297 | -1, "rach-d", "rach", 16, | |
1298 | { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } | |
1299 | }, | |
1300 | /* rach $accd,$accs */ | |
1301 | { | |
1302 | -1, "rach-ds", "rach", 16, | |
1303 | { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
1304 | }, |
1305 | /* st $src1,@($src2) */ | |
1306 | { | |
1307 | -1, "st-2", "st", 16, | |
1fa60b5d | 1308 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1309 | }, |
1310 | /* st $src1,@($src2,$slo16) */ | |
1311 | { | |
1312 | -1, "st-d2", "st", 32, | |
1fa60b5d | 1313 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1314 | }, |
1315 | /* stb $src1,@($src2) */ | |
1316 | { | |
1317 | -1, "stb-2", "stb", 16, | |
1fa60b5d | 1318 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1319 | }, |
1320 | /* stb $src1,@($src2,$slo16) */ | |
1321 | { | |
1322 | -1, "stb-d2", "stb", 32, | |
1fa60b5d | 1323 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1324 | }, |
1325 | /* sth $src1,@($src2) */ | |
1326 | { | |
1327 | -1, "sth-2", "sth", 16, | |
1fa60b5d | 1328 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1329 | }, |
1330 | /* sth $src1,@($src2,$slo16) */ | |
1331 | { | |
1332 | -1, "sth-d2", "sth", 32, | |
1fa60b5d | 1333 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1334 | }, |
1335 | /* push $src1 */ | |
1336 | { | |
1337 | -1, "push", "push", 16, | |
1fa60b5d | 1338 | { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
1339 | }, |
1340 | }; | |
1341 | ||
1342 | /* The macro instruction opcode table. */ | |
1343 | ||
1344 | static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] = | |
1345 | { | |
1346 | /* bc $disp8 */ | |
1347 | { | |
1348 | { 0, 0, 0, 0 }, | |
1349 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
1350 | & ifmt_bc8r, { 0x7c00 } | |
1351 | }, | |
1352 | /* bc $disp24 */ | |
1353 | { | |
1354 | { 0, 0, 0, 0 }, | |
1355 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
1356 | & ifmt_bc24r, { 0xfc000000 } | |
1357 | }, | |
1358 | /* bl $disp8 */ | |
1359 | { | |
1360 | { 0, 0, 0, 0 }, | |
1361 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
1362 | & ifmt_bl8r, { 0x7e00 } | |
1363 | }, | |
1364 | /* bl $disp24 */ | |
1365 | { | |
1366 | { 0, 0, 0, 0 }, | |
1367 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
1368 | & ifmt_bl24r, { 0xfe000000 } | |
1369 | }, | |
1fa60b5d DE |
1370 | /* bcl $disp8 */ |
1371 | { | |
1372 | { 0, 0, 0, 0 }, | |
1373 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
1374 | & ifmt_bcl8r, { 0x7800 } | |
1375 | }, | |
1376 | /* bcl $disp24 */ | |
1377 | { | |
1378 | { 0, 0, 0, 0 }, | |
1379 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
1380 | & ifmt_bcl24r, { 0xf8000000 } | |
1381 | }, | |
252b5132 RH |
1382 | /* bnc $disp8 */ |
1383 | { | |
1384 | { 0, 0, 0, 0 }, | |
1385 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
1386 | & ifmt_bnc8r, { 0x7d00 } | |
1387 | }, | |
1388 | /* bnc $disp24 */ | |
1389 | { | |
1390 | { 0, 0, 0, 0 }, | |
1391 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
1392 | & ifmt_bnc24r, { 0xfd000000 } | |
1393 | }, | |
1394 | /* bra $disp8 */ | |
1395 | { | |
1396 | { 0, 0, 0, 0 }, | |
1397 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
1398 | & ifmt_bra8r, { 0x7f00 } | |
1399 | }, | |
1400 | /* bra $disp24 */ | |
1401 | { | |
1402 | { 0, 0, 0, 0 }, | |
1403 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
1404 | & ifmt_bra24r, { 0xff000000 } | |
1405 | }, | |
1fa60b5d DE |
1406 | /* bncl $disp8 */ |
1407 | { | |
1408 | { 0, 0, 0, 0 }, | |
1409 | { { MNEM, ' ', OP (DISP8), 0 } }, | |
1410 | & ifmt_bncl8r, { 0x7900 } | |
1411 | }, | |
1412 | /* bncl $disp24 */ | |
1413 | { | |
1414 | { 0, 0, 0, 0 }, | |
1415 | { { MNEM, ' ', OP (DISP24), 0 } }, | |
1416 | & ifmt_bncl24r, { 0xf9000000 } | |
1417 | }, | |
252b5132 RH |
1418 | /* ld $dr,@($sr) */ |
1419 | { | |
1420 | { 0, 0, 0, 0 }, | |
1421 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, | |
1422 | & ifmt_ld_2, { 0x20c0 } | |
1423 | }, | |
1424 | /* ld $dr,@($sr,$slo16) */ | |
1425 | { | |
1426 | { 0, 0, 0, 0 }, | |
1427 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, | |
1428 | & ifmt_ld_d2, { 0xa0c00000 } | |
1429 | }, | |
1430 | /* ldb $dr,@($sr) */ | |
1431 | { | |
1432 | { 0, 0, 0, 0 }, | |
1433 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, | |
1434 | & ifmt_ldb_2, { 0x2080 } | |
1435 | }, | |
1436 | /* ldb $dr,@($sr,$slo16) */ | |
1437 | { | |
1438 | { 0, 0, 0, 0 }, | |
1439 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, | |
1440 | & ifmt_ldb_d2, { 0xa0800000 } | |
1441 | }, | |
1442 | /* ldh $dr,@($sr) */ | |
1443 | { | |
1444 | { 0, 0, 0, 0 }, | |
1445 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, | |
1446 | & ifmt_ldh_2, { 0x20a0 } | |
1447 | }, | |
1448 | /* ldh $dr,@($sr,$slo16) */ | |
1449 | { | |
1450 | { 0, 0, 0, 0 }, | |
1451 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, | |
1452 | & ifmt_ldh_d2, { 0xa0a00000 } | |
1453 | }, | |
1454 | /* ldub $dr,@($sr) */ | |
1455 | { | |
1456 | { 0, 0, 0, 0 }, | |
1457 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, | |
1458 | & ifmt_ldub_2, { 0x2090 } | |
1459 | }, | |
1460 | /* ldub $dr,@($sr,$slo16) */ | |
1461 | { | |
1462 | { 0, 0, 0, 0 }, | |
1463 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, | |
1464 | & ifmt_ldub_d2, { 0xa0900000 } | |
1465 | }, | |
1466 | /* lduh $dr,@($sr) */ | |
1467 | { | |
1468 | { 0, 0, 0, 0 }, | |
1469 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, | |
1470 | & ifmt_lduh_2, { 0x20b0 } | |
1471 | }, | |
1472 | /* lduh $dr,@($sr,$slo16) */ | |
1473 | { | |
1474 | { 0, 0, 0, 0 }, | |
1475 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, | |
1476 | & ifmt_lduh_d2, { 0xa0b00000 } | |
1477 | }, | |
1478 | /* pop $dr */ | |
1479 | { | |
1480 | { 0, 0, 0, 0 }, | |
1481 | { { MNEM, ' ', OP (DR), 0 } }, | |
1482 | & ifmt_pop, { 0x20ef } | |
1483 | }, | |
1484 | /* ldi $dr,$simm8 */ | |
1485 | { | |
1486 | { 0, 0, 0, 0 }, | |
1487 | { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, | |
1488 | & ifmt_ldi8a, { 0x6000 } | |
1489 | }, | |
1490 | /* ldi $dr,$hash$slo16 */ | |
1491 | { | |
1492 | { 0, 0, 0, 0 }, | |
1493 | { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, | |
1494 | & ifmt_ldi16a, { 0x90f00000 } | |
1495 | }, | |
1fa60b5d DE |
1496 | /* rac $accd */ |
1497 | { | |
1498 | { 0, 0, 0, 0 }, | |
1499 | { { MNEM, ' ', OP (ACCD), 0 } }, | |
1500 | & ifmt_rac_d, { 0x5090 } | |
1501 | }, | |
1502 | /* rac $accd,$accs */ | |
1503 | { | |
1504 | { 0, 0, 0, 0 }, | |
1505 | { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, | |
1506 | & ifmt_rac_ds, { 0x5090 } | |
1507 | }, | |
1508 | /* rach $accd */ | |
1509 | { | |
1510 | { 0, 0, 0, 0 }, | |
1511 | { { MNEM, ' ', OP (ACCD), 0 } }, | |
1512 | & ifmt_rach_d, { 0x5080 } | |
1513 | }, | |
1514 | /* rach $accd,$accs */ | |
1515 | { | |
1516 | { 0, 0, 0, 0 }, | |
1517 | { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, | |
1518 | & ifmt_rach_ds, { 0x5080 } | |
1519 | }, | |
252b5132 RH |
1520 | /* st $src1,@($src2) */ |
1521 | { | |
1522 | { 0, 0, 0, 0 }, | |
1523 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, | |
1524 | & ifmt_st_2, { 0x2040 } | |
1525 | }, | |
1526 | /* st $src1,@($src2,$slo16) */ | |
1527 | { | |
1528 | { 0, 0, 0, 0 }, | |
1529 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, | |
1530 | & ifmt_st_d2, { 0xa0400000 } | |
1531 | }, | |
1532 | /* stb $src1,@($src2) */ | |
1533 | { | |
1534 | { 0, 0, 0, 0 }, | |
1535 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, | |
1536 | & ifmt_stb_2, { 0x2000 } | |
1537 | }, | |
1538 | /* stb $src1,@($src2,$slo16) */ | |
1539 | { | |
1540 | { 0, 0, 0, 0 }, | |
1541 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, | |
1542 | & ifmt_stb_d2, { 0xa0000000 } | |
1543 | }, | |
1544 | /* sth $src1,@($src2) */ | |
1545 | { | |
1546 | { 0, 0, 0, 0 }, | |
1547 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, | |
1548 | & ifmt_sth_2, { 0x2020 } | |
1549 | }, | |
1550 | /* sth $src1,@($src2,$slo16) */ | |
1551 | { | |
1552 | { 0, 0, 0, 0 }, | |
1553 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, | |
1554 | & ifmt_sth_d2, { 0xa0200000 } | |
1555 | }, | |
1556 | /* push $src1 */ | |
1557 | { | |
1558 | { 0, 0, 0, 0 }, | |
1559 | { { MNEM, ' ', OP (SRC1), 0 } }, | |
1560 | & ifmt_push, { 0x207f } | |
1561 | }, | |
1562 | }; | |
1563 | ||
1564 | #undef A | |
1565 | #undef MNEM | |
1566 | #undef OPERAND | |
1567 | #undef OP | |
1568 | ||
1569 | #ifndef CGEN_ASM_HASH_P | |
1570 | #define CGEN_ASM_HASH_P(insn) 1 | |
1571 | #endif | |
1572 | ||
1573 | #ifndef CGEN_DIS_HASH_P | |
1574 | #define CGEN_DIS_HASH_P(insn) 1 | |
1575 | #endif | |
1576 | ||
1577 | /* Return non-zero if INSN is to be added to the hash table. | |
1578 | Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ | |
1579 | ||
1580 | static int | |
1581 | asm_hash_insn_p (insn) | |
1582 | const CGEN_INSN *insn; | |
1583 | { | |
1584 | return CGEN_ASM_HASH_P (insn); | |
1585 | } | |
1586 | ||
1587 | static int | |
1588 | dis_hash_insn_p (insn) | |
1589 | const CGEN_INSN *insn; | |
1590 | { | |
1591 | /* If building the hash table and the NO-DIS attribute is present, | |
1592 | ignore. */ | |
1593 | if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) | |
1594 | return 0; | |
1595 | return CGEN_DIS_HASH_P (insn); | |
1596 | } | |
1597 | ||
1598 | #ifndef CGEN_ASM_HASH | |
1599 | #define CGEN_ASM_HASH_SIZE 127 | |
1600 | #ifdef CGEN_MNEMONIC_OPERANDS | |
1601 | #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) | |
1602 | #else | |
1603 | #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ | |
1604 | #endif | |
1605 | #endif | |
1606 | ||
1607 | /* It doesn't make much sense to provide a default here, | |
1608 | but while this is under development we do. | |
1609 | BUFFER is a pointer to the bytes of the insn, target order. | |
1610 | VALUE is the first base_insn_bitsize bits as an int in host order. */ | |
1611 | ||
1612 | #ifndef CGEN_DIS_HASH | |
1613 | #define CGEN_DIS_HASH_SIZE 256 | |
1614 | #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) | |
1615 | #endif | |
1616 | ||
1617 | /* The result is the hash value of the insn. | |
1618 | Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ | |
1619 | ||
1620 | static unsigned int | |
1621 | asm_hash_insn (mnem) | |
1622 | const char * mnem; | |
1623 | { | |
1624 | return CGEN_ASM_HASH (mnem); | |
1625 | } | |
1626 | ||
1627 | /* BUF is a pointer to the bytes of the insn, target order. | |
1628 | VALUE is the first base_insn_bitsize bits as an int in host order. */ | |
1629 | ||
1630 | static unsigned int | |
1631 | dis_hash_insn (buf, value) | |
1632 | const char * buf; | |
1633 | CGEN_INSN_INT value; | |
1634 | { | |
1635 | return CGEN_DIS_HASH (buf, value); | |
1636 | } | |
1637 | ||
1638 | /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ | |
1639 | ||
1640 | static void | |
1641 | set_fields_bitsize (fields, size) | |
1642 | CGEN_FIELDS *fields; | |
1643 | int size; | |
1644 | { | |
1645 | CGEN_FIELDS_BITSIZE (fields) = size; | |
1646 | } | |
1647 | ||
1648 | /* Function to call before using the operand instance table. | |
1649 | This plugs the opcode entries and macro instructions into the cpu table. */ | |
1650 | ||
1651 | void | |
1652 | m32r_cgen_init_opcode_table (cd) | |
1653 | CGEN_CPU_DESC cd; | |
1654 | { | |
1655 | int i; | |
1656 | int num_macros = (sizeof (m32r_cgen_macro_insn_table) / | |
1657 | sizeof (m32r_cgen_macro_insn_table[0])); | |
1658 | const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0]; | |
1659 | const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0]; | |
1660 | CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); | |
1661 | memset (insns, 0, num_macros * sizeof (CGEN_INSN)); | |
1662 | for (i = 0; i < num_macros; ++i) | |
1663 | { | |
1664 | insns[i].base = &ib[i]; | |
1665 | insns[i].opcode = &oc[i]; | |
1666 | } | |
1667 | cd->macro_insn_table.init_entries = insns; | |
1668 | cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); | |
1669 | cd->macro_insn_table.num_init_entries = num_macros; | |
1670 | ||
1671 | oc = & m32r_cgen_insn_opcode_table[0]; | |
1672 | insns = (CGEN_INSN *) cd->insn_table.init_entries; | |
1673 | for (i = 0; i < MAX_INSNS; ++i) | |
1674 | insns[i].opcode = &oc[i]; | |
1675 | ||
1676 | cd->sizeof_fields = sizeof (CGEN_FIELDS); | |
1677 | cd->set_fields_bitsize = set_fields_bitsize; | |
1678 | ||
1679 | cd->asm_hash_p = asm_hash_insn_p; | |
1680 | cd->asm_hash = asm_hash_insn; | |
1681 | cd->asm_hash_size = CGEN_ASM_HASH_SIZE; | |
1682 | ||
1683 | cd->dis_hash_p = dis_hash_insn_p; | |
1684 | cd->dis_hash = dis_hash_insn; | |
1685 | cd->dis_hash_size = CGEN_DIS_HASH_SIZE; | |
1686 | } |