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Move all global state data into opcode table struct, and treat
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
CommitLineData
ab0bd049
DE		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
9c03036a 3
fbc8134d 4THIS FILE IS USED TO GENERATE m32r-opc.c.
7c26196f 5
ab0bd049 6Copyright (C) 1998 Free Software Foundation, Inc.
9c03036a 7
ab0bd049 8This file is part of the GNU Binutils and GDB, the GNU debugger.
9c03036a
DE		 9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
ab0bd049 20You should have received a copy of the GNU General Public License
fbc8134d
DE		 21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
9c03036a 23
23cf992f 24#include "sysdep.h"
9c03036a
DE		 25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
ab0bd049 29#include "symcat.h"
9c03036a 30#include "m32r-opc.h"
fbc8134d 31#include "opintl.h"
9c03036a 32
ab0bd049 33/* Look up instruction INSN_VALUE and extract its fields.
1294c286 34 INSN, if non-null, is the insn table entry.
ab0bd049
DE		 35 Otherwise INSN_VALUE is examined to compute it.
36 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
1294c286
DE		 37 0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
38 If INSN != NULL, LENGTH must be valid.
390bd87d 39 ALIAS_P is non-zero if alias insns are to be included in the search.
1294c286 40
ab0bd049
DE		 41 The result a pointer to the insn table entry, or NULL if the instruction
42 wasn't recognized. */
43
44const CGEN_INSN *
390bd87d 45m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
ab0bd049
DE		 46 const CGEN_INSN *insn;
47 cgen_insn_t insn_value;
48 int length;
49 CGEN_FIELDS *fields;
1294c286 50 int alias_p;
ab0bd049 51{
390bd87d 52 char buf[16];
ab0bd049
DE		 53
54 if (!insn)
55 {
56 const CGEN_INSN_LIST *insn_list;
57
58#ifdef CGEN_INT_INSN
59 switch (length)
60 {
61 case 8:
62 buf[0] = insn_value;
63 break;
64 case 16:
65 if (cgen_current_endian == CGEN_ENDIAN_BIG)
66 bfd_putb16 (insn_value, buf);
67 else
68 bfd_putl16 (insn_value, buf);
69 break;
70 case 32:
71 if (cgen_current_endian == CGEN_ENDIAN_BIG)
72 bfd_putb32 (insn_value, buf);
73 else
74 bfd_putl32 (insn_value, buf);
75 break;
76 default:
77 abort ();
78 }
79#else
80 abort (); /* FIXME: unfinished */
81#endif
82
83 /* The instructions are stored in hash lists.
84 Pick the first one and keep trying until we find the right one. */
85
86 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
87 while (insn_list != NULL)
88 {
89 insn = insn_list->insn;
90
390bd87d
DE		 91 if (alias_p
92 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
ab0bd049 93 {
390bd87d
DE		 94 /* Basic bit mask must be correct. */
95 /* ??? May wish to allow target to defer this check until the
96 extract handler. */
97 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
98 {
fbc8134d 99 /* ??? 0 is passed for `pc' */
1294c286 100 int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
fbc8134d
DE		 101 insn_value, fields,
102 (bfd_vma) 0);
1294c286
DE		 103 if (elength > 0)
104 {
105 /* sanity check */
106 if (length != 0 && length != elength)
107 abort ();
108 return insn;
109 }
390bd87d 110 }
ab0bd049
DE		 111 }
112
113 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
114 }
115 }
116 else
117 {
390bd87d
DE		 118 /* Sanity check: can't pass an alias insn if ! alias_p. */
119 if (! alias_p
120 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
121 abort ();
1294c286
DE		 122 /* Sanity check: length must be correct. */
123 if (length != CGEN_INSN_BITSIZE (insn))
124 abort ();
390bd87d 125
fbc8134d
DE		 126 /* ??? 0 is passed for `pc' */
127 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields,
128 (bfd_vma) 0);
1294c286
DE		 129 /* Sanity check: must succeed.
130 Could relax this later if it ever proves useful. */
131 if (length == 0)
132 abort ();
133 return insn;
ab0bd049
DE		 134 }
135
136 return NULL;
137}
138
1294c286 139/* Fill in the operand instances used by INSN whose operands are FIELDS.
b02643b5 140 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
1294c286 141 in. */
ab0bd049 142
1294c286
DE		 143void
144m32r_cgen_get_insn_operands (insn, fields, indices)
145 const CGEN_INSN * insn;
146 const CGEN_FIELDS * fields;
ab0bd049
DE		 147 int *indices;
148{
ab0bd049
DE		 149 const CGEN_OPERAND_INSTANCE *opinst;
150 int i;
151
ab0bd049 152 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
b2f18612
DE		 153 opinst != NULL
154 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
ab0bd049
DE		 155 ++i, ++opinst)
156 {
157 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
158 if (op == NULL)
159 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
160 else
0cc2fbf3
DE		 161 indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
162 fields);
ab0bd049 163 }
1294c286 164}
ab0bd049 165
1294c286
DE		 166/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
167 isn't known.
168 The INSN, INSN_VALUE, and LENGTH arguments are passed to
169 m32r_cgen_lookup_insn unchanged.
170
171 The result is the insn table entry or NULL if the instruction wasn't
172 recognized. */
173
174const CGEN_INSN *
175m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
176 const CGEN_INSN *insn;
177 cgen_insn_t insn_value;
178 int length;
179 int *indices;
180{
181 CGEN_FIELDS fields;
182
183 /* Pass non-zero for ALIAS_P only if INSN != NULL.
184 If INSN == NULL, we want a real insn. */
185 insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields,
186 insn != NULL);
187 if (! insn)
188 return NULL;
189
190 m32r_cgen_get_insn_operands (insn, &fields, indices);
ab0bd049
DE		 191 return insn;
192}
23cf992f
NC		 193/* Attributes. */
194
7c26196f 195static const CGEN_ATTR_ENTRY MACH_attr[] =
5d07b6cf
DE		 196{
197 { "m32r", MACH_M32R },
7c26196f
DE		 198/* start-sanitize-m32rx */
199 { "m32rx", MACH_M32RX },
200/* end-sanitize-m32rx */
201 { "max", MACH_MAX },
202 { 0, 0 }
203};
204
205/* start-sanitize-m32rx */
206static const CGEN_ATTR_ENTRY PIPE_attr[] =
207{
208 { "NONE", PIPE_NONE },
209 { "O", PIPE_O },
210 { "S", PIPE_S },
211 { "OS", PIPE_OS },
23cf992f
NC		 212 { 0, 0 }
213};
214
7c26196f
DE		 215/* end-sanitize-m32rx */
216const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
5d07b6cf
DE		 217{
218 { "ABS-ADDR", NULL },
23cf992f 219 { "FAKE", NULL },
a6cefe4f 220 { "HASH-PREFIX", NULL },
23cf992f 221 { "NEGATIVE", NULL },
23cf992f
NC		 222 { "PCREL-ADDR", NULL },
223 { "RELAX", NULL },
224 { "RELOC", NULL },
225 { "SIGN-OPT", NULL },
226 { "UNSIGNED", NULL },
227 { 0, 0 }
228};
229
7c26196f 230const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
5d07b6cf 231{
7c26196f
DE		 232 { "MACH", & MACH_attr[0] },
233/* start-sanitize-m32rx */
234 { "PIPE", & PIPE_attr[0] },
235/* end-sanitize-m32rx */
5d07b6cf 236 { "ALIAS", NULL },
23cf992f
NC		 237 { "COND-CTI", NULL },
238 { "FILL-SLOT", NULL },
1294c286 239 { "NO-DIS", NULL },
7c26196f 240 { "PARALLEL", NULL },
23cf992f 241 { "RELAX", NULL },
23cf992f 242 { "RELAXABLE", NULL },
fbc8134d 243 { "SPECIAL", NULL },
23cf992f
NC		 244 { "UNCOND-CTI", NULL },
245 { 0, 0 }
9c03036a
DE		 246};
247
853713a7 248CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
5d07b6cf
DE		 249{
250 { "fp", 13 },
9c03036a
DE		 251 { "lr", 14 },
252 { "sp", 15 },
253 { "r0", 0 },
254 { "r1", 1 },
255 { "r2", 2 },
256 { "r3", 3 },
257 { "r4", 4 },
258 { "r5", 5 },
259 { "r6", 6 },
260 { "r7", 7 },
261 { "r8", 8 },
262 { "r9", 9 },
263 { "r10", 10 },
264 { "r11", 11 },
265 { "r12", 12 },
266 { "r13", 13 },
267 { "r14", 14 },
268 { "r15", 15 }
269};
270
853713a7 271CGEN_KEYWORD m32r_cgen_opval_h_gr =
5d07b6cf
DE		 272{
273 & m32r_cgen_opval_h_gr_entries[0],
9c03036a
DE		 274 19
275};
276
853713a7 277CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
5d07b6cf
DE		 278{
279 { "psw", 0 },
9c03036a
DE		 280 { "cbr", 1 },
281 { "spi", 2 },
282 { "spu", 3 },
283 { "bpc", 6 },
284 { "cr0", 0 },
285 { "cr1", 1 },
286 { "cr2", 2 },
287 { "cr3", 3 },
288 { "cr4", 4 },
289 { "cr5", 5 },
b2ddf0c4
NC		 290 { "cr6", 6 },
291 { "cr7", 7 },
292 { "cr8", 8 },
293 { "cr9", 9 },
294 { "cr10", 10 },
295 { "cr11", 11 },
296 { "cr12", 12 },
297 { "cr13", 13 },
298 { "cr14", 14 },
299 { "cr15", 15 }
9c03036a
DE		 300};
301
853713a7 302CGEN_KEYWORD m32r_cgen_opval_h_cr =
5d07b6cf
DE		 303{
304 & m32r_cgen_opval_h_cr_entries[0],
b2ddf0c4 305 21
9c03036a
DE		 306};
307
7c26196f
DE		 308/* start-sanitize-m32rx */
309CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
310{
311 { "a0", 0 },
312 { "a1", 1 }
313};
23cf992f 314
7c26196f 315CGEN_KEYWORD m32r_cgen_opval_h_accums =
5d07b6cf 316{
7c26196f
DE		 317 & m32r_cgen_opval_h_accums_entries[0],
318 2
9c03036a
DE		 319};
320
7c26196f
DE		 321/* end-sanitize-m32rx */
322
ab0bd049
DE		 323/* The hardware table. */
324
325#define HW_ENT(n) m32r_cgen_hw_entries[n]
326static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
7c26196f 327{
ab0bd049
DE		 328 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
329 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
330 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
331 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
332 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
333 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
334 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
335 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
336 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
337 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
338 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
339 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
7c26196f 340/* start-sanitize-m32rx */
ab0bd049 341 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
7c26196f 342/* end-sanitize-m32rx */
ab0bd049
DE		 343 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
344 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
345 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
346 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
347 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
348 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
349 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
8d157f96 350 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
7c26196f
DE		 351 { 0 }
352};
9c03036a 353
ab0bd049
DE		 354/* The operand table. */
355
8d157f96
DE		 356#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
357#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
0bf55db8 358
7c26196f 359const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
9c03036a 360{
23cf992f 361/* pc: program counter */
ab0bd049 362 { "pc", & HW_ENT (HW_H_PC), 0, 0,
fbc8134d 363 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
9c03036a 364/* sr: source register */
ab0bd049
DE		 365 { "sr", & HW_ENT (HW_H_GR), 12, 4,
366 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 367/* dr: destination register */
ab0bd049
DE		 368 { "dr", & HW_ENT (HW_H_GR), 4, 4,
369 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 370/* src1: source register 1 */
ab0bd049
DE		 371 { "src1", & HW_ENT (HW_H_GR), 4, 4,
372 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 373/* src2: source register 2 */
ab0bd049
DE		 374 { "src2", & HW_ENT (HW_H_GR), 12, 4,
375 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 376/* scr: source control register */
ab0bd049
DE		 377 { "scr", & HW_ENT (HW_H_CR), 12, 4,
378 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 379/* dcr: destination control register */
ab0bd049
DE		 380 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
381 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 382/* simm8: 8 bit signed immediate */
ab0bd049 383 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
a6cefe4f 384 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 385/* simm16: 16 bit signed immediate */
ab0bd049 386 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
a6cefe4f 387 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 388/* uimm4: 4 bit trap number */
ab0bd049 389 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
a6cefe4f 390 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 391/* uimm5: 5 bit shift count */
ab0bd049 392 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
a6cefe4f 393 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 394/* uimm16: 16 bit unsigned immediate */
ab0bd049 395 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
a6cefe4f 396 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 397/* start-sanitize-m32rx */
398/* imm1: 1 bit immediate */
399 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
a6cefe4f 400 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 401/* end-sanitize-m32rx */
402/* start-sanitize-m32rx */
403/* accd: accumulator destination register */
404 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
405 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
406/* end-sanitize-m32rx */
7c26196f 407/* start-sanitize-m32rx */
ab0bd049
DE		 408/* accs: accumulator source register */
409 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
410 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f
DE		 411/* end-sanitize-m32rx */
412/* start-sanitize-m32rx */
413/* acc: accumulator reg (d) */
ab0bd049
DE		 414 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
415 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f 416/* end-sanitize-m32rx */
a6cefe4f
DE		 417/* hash: # prefix */
418 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
419 { 0, 0, { 0 } } },
9c03036a 420/* hi16: high 16 bit immediate, sign optional */
ab0bd049
DE		 421 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
422 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 423/* slo16: 16 bit signed immediate, for low() */
ab0bd049
DE		 424 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
425 { 0, 0, { 0 } } },
9c03036a 426/* ulo16: 16 bit unsigned immediate, for low() */
ab0bd049
DE		 427 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
428 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 429/* uimm24: 24 bit address */
ab0bd049 430 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
a6cefe4f 431 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 432/* disp8: 8 bit displacement */
ab0bd049
DE		 433 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
434 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 435/* disp16: 16 bit displacement */
ab0bd049
DE		 436 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
437 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 438/* disp24: 24 bit displacement */
ab0bd049
DE		 439 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
440 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
23cf992f 441/* condbit: condition bit */
ab0bd049
DE		 442 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
443 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f 444/* accum: accumulator */
ab0bd049
DE		 445 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
446 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f
NC		 447};
448
ab0bd049
DE		 449/* Operand references. */
450
7caa7497
DE		 451#define INPUT CGEN_OPERAND_INSTANCE_INPUT
452#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
453
1294c286 454static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
7caa7497
DE		 455 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
456 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
457 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 458 { 0 }
459};
460
1294c286 461static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
7caa7497 462 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 463 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 464 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 465 { 0 }
466};
467
1294c286 468static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
7caa7497
DE		 469 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
470 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
471 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 472 { 0 }
473};
474
1294c286 475static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
7caa7497
DE		 476 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
477 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
478 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 479 { 0 }
480};
481
1294c286 482static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
7caa7497
DE		 483 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
484 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
485 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 486 { 0 }
487};
488
1294c286 489static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
390bd87d
DE		 490 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
491 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
390bd87d 492 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 493 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 494 { 0 }
495};
496
1294c286 497static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
7caa7497 498 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 499 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
7caa7497 500 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 501 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 502 { 0 }
503};
504
1294c286 505static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
7caa7497
DE		 506 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
507 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 508 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
7caa7497 509 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 510 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 511 { 0 }
512};
513
1294c286 514static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
390bd87d 515 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
fbc8134d 516 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
8d157f96 517 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 518 { 0 }
519};
520
1294c286 521static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
390bd87d 522 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
fbc8134d 523 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
8d157f96 524 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 525 { 0 }
526};
527
1294c286 528static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
7caa7497
DE		 529 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
530 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 531 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
8d157f96 532 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 533 { 0 }
534};
535
1294c286 536static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
7caa7497 537 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 538 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
8d157f96 539 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 540 { 0 }
541};
542
1294c286 543static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
390bd87d 544 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 545 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
7caa7497 546 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 547 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 548 { 0 }
549};
550
1294c286 551static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
390bd87d 552 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 553 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
7caa7497 554 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 555 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 556 { 0 }
557};
558
b2ddf0c4 559/* start-sanitize-m32rx */
1294c286 560static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
390bd87d 561 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d 562 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 563 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
7caa7497 564 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 565 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 566 { 0 }
567};
568
b2ddf0c4
NC		 569/* end-sanitize-m32rx */
570/* start-sanitize-m32rx */
1294c286 571static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
390bd87d 572 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d 573 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 574 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
7caa7497 575 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 576 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 577 { 0 }
578};
579
b2ddf0c4 580/* end-sanitize-m32rx */
1294c286 581static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
fbc8134d 582 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
8d157f96 583 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 584 { 0 }
585};
586
1294c286 587static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
fbc8134d 588 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
8d157f96 589 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 590 { 0 }
591};
592
1294c286 593static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
7caa7497
DE		 594 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
595 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 596 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 597 { 0 }
598};
599
1294c286 600static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
7caa7497 601 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 602 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
390bd87d 603 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 604 { 0 }
605};
606
b2ddf0c4 607/* start-sanitize-m32rx */
1294c286 608static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
7caa7497 609 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 610 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 611 { 0 }
612};
613
b2ddf0c4 614/* end-sanitize-m32rx */
1294c286 615static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
7caa7497
DE		 616 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
617 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
618 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 619 { 0 }
620};
621
b2ddf0c4 622/* start-sanitize-m32rx */
1294c286 623static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
390bd87d 624 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
7caa7497 625 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
8d157f96 626 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 627 { 0 }
628};
629
b2ddf0c4 630/* end-sanitize-m32rx */
1294c286 631static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
390bd87d 632 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
7caa7497
DE		 633 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
634 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 635 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 636 { 0 }
637};
638
1294c286 639static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
7caa7497 640 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
8d157f96 641 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 642 { 0 }
643};
644
1294c286 645static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
7caa7497 646 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
fbc8134d 647 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 648 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 649 { 0 }
650};
651
1294c286 652static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
7caa7497 653 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
7caa7497 654 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 655 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 656 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 657 { 0 }
658};
659
1294c286 660static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
7caa7497 661 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
fbc8134d 662 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 663 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 664 { 0 }
665};
666
1294c286 667static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
7caa7497 668 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
7caa7497 669 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 670 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 671 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 672 { 0 }
673};
674
1294c286 675static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
7caa7497 676 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
fbc8134d 677 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 678 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 679 { 0 }
680};
681
1294c286 682static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
7caa7497 683 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
7caa7497 684 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 685 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 686 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 687 { 0 }
688};
689
1294c286 690static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
390bd87d
DE		 691 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
692 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
693 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
694 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
695 { 0 }
696};
697
1294c286 698static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
fbc8134d 699 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
7caa7497 700 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 701 { 0 }
702};
703
1294c286 704static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
7caa7497
DE		 705 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
706 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 707 { 0 }
708};
709
1294c286 710static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
7caa7497
DE		 711 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
712 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 713 { 0 }
714};
715
1294c286 716static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
8d157f96 717 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
fbc8134d 718 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
8d157f96 719 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
fbc8134d 720 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
390bd87d
DE		 721 { 0 }
722};
723
1294c286 724static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
390bd87d 725 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497
DE		 726 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
727 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 728 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 729 { 0 }
730};
731
b2ddf0c4 732/* start-sanitize-m32rx */
1294c286 733static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
7caa7497
DE		 734 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
735 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
736 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
737 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 738 { 0 }
739};
740
b2ddf0c4 741/* end-sanitize-m32rx */
1294c286 742static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
390bd87d
DE		 743 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
744 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
745 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
746 { 0 }
747};
748
b2ddf0c4 749/* start-sanitize-m32rx */
1294c286 750static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
7caa7497
DE		 751 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
752 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
753 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 754 { 0 }
755};
756
b2ddf0c4 757/* end-sanitize-m32rx */
1294c286 758static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
7caa7497
DE		 759 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
760 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 761 { 0 }
762};
763
1294c286 764static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
390bd87d 765 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497 766 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 767 { 0 }
768};
769
b2ddf0c4 770/* start-sanitize-m32rx */
1294c286 771static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
7caa7497
DE		 772 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
773 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 774 { 0 }
775};
776
b2ddf0c4 777/* end-sanitize-m32rx */
1294c286 778static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
b02643b5 779 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
7caa7497 780 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 781 { 0 }
782};
783
1294c286 784static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
390bd87d 785 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497 786 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d 787 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 788 { 0 }
789};
790
b2ddf0c4 791/* start-sanitize-m32rx */
1294c286 792static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
7caa7497
DE		 793 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
794 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
795 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
ab0bd049
DE		 796 { 0 }
797};
798
b2ddf0c4 799/* end-sanitize-m32rx */
1294c286 800static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
7caa7497 801 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
b02643b5 802 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
ab0bd049
DE		 803 { 0 }
804};
805
1294c286 806static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
390bd87d
DE		 807 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
808 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 809 { 0 }
810};
811
b2ddf0c4 812/* start-sanitize-m32rx */
1294c286 813static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
7caa7497
DE		 814 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
815 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
816 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
ab0bd049
DE		 817 { 0 }
818};
819
b2ddf0c4 820/* end-sanitize-m32rx */
1294c286 821static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
fbc8134d
DE		 822 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
823 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
824 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
825 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
826 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
827 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 828 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
829 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 830 { 0 }
831};
832
1294c286 833static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
fbc8134d 834 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
7caa7497 835 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 836 { 0 }
837};
838
1294c286 839static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
390bd87d 840 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 841 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
390bd87d
DE		 842 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
843 { 0 }
844};
845
1294c286 846static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
7caa7497
DE		 847 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
848 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
849 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 850 { 0 }
851};
852
1294c286 853static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
fbc8134d 854 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
390bd87d 855 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 856 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
857 { 0 }
858};
859
1294c286 860static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
fbc8134d 861 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
7caa7497
DE		 862 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
863 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
7caa7497 864 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 865 { 0 }
866};
867
1294c286 868static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
fbc8134d
DE		 869 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
870 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 871 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
872 { 0 }
873};
874
1294c286 875static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
390bd87d 876 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d
DE		 877 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
878 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 879 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
880 { 0 }
881};
882
1294c286 883static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
fbc8134d
DE		 884 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
885 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 886 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
887 { 0 }
888};
889
1294c286 890static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
390bd87d 891 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d
DE		 892 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
893 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 894 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
895 { 0 }
896};
897
1294c286 898static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
390bd87d 899 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 900 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 901 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
902 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
903 { 0 }
904};
905
1294c286 906static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
8d157f96 907 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d
DE		 908 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
909 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
910 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
911 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
912 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 913 { 0 }
914};
915
1294c286 916static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
8d157f96 917 { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
fbc8134d 918 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
390bd87d 919 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
8d157f96
DE		 920 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
921 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 922 { 0 }
923};
924
b2ddf0c4 925/* start-sanitize-m32rx */
1294c286 926static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
b02643b5 927 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
7caa7497 928 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 929 { 0 }
930};
931
b2ddf0c4
NC		 932/* end-sanitize-m32rx */
933/* start-sanitize-m32rx */
1294c286 934static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
390bd87d 935 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
b02643b5 936 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
7caa7497 937 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 938 { 0 }
939};
940
b2ddf0c4
NC		 941/* end-sanitize-m32rx */
942/* start-sanitize-m32rx */
1294c286 943static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
7caa7497 944 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
fbc8134d 945 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
7caa7497 946 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 947 { 0 }
948};
949
b2ddf0c4
NC		 950/* end-sanitize-m32rx */
951/* start-sanitize-m32rx */
1294c286 952static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
7caa7497
DE		 953 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
954 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
955 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
956 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
ab0bd049
DE		 957 { 0 }
958};
959
b2ddf0c4
NC		 960/* end-sanitize-m32rx */
961/* start-sanitize-m32rx */
1294c286 962static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
390bd87d
DE		 963 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
964 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
965 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
966 { 0 }
967};
968
b2ddf0c4
NC		 969/* end-sanitize-m32rx */
970/* start-sanitize-m32rx */
1294c286 971static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
390bd87d 972 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 973 { 0 }
974};
975
b2ddf0c4 976/* end-sanitize-m32rx */
7caa7497
DE		 977#undef INPUT
978#undef OUTPUT
979
0bf55db8 980#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
8d157f96
DE		 981#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
982#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
23cf992f 983
1294c286
DE		 984/* The instruction table.
985 This is currently non-static because the simulator accesses it
986 directly. */
ab0bd049 987
7c26196f 988const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
5d07b6cf 989{
1294c286
DE		 990 /* Special null first entry.
991 A `num' value of zero is thus illegal.
992 Also, the special `illegal' insn resides here. */
23cf992f 993 { { 0 }, 0 },
9c03036a
DE		 994/* add $dr,$sr */
995 {
23cf992f 996 { 1, 1, 1, 1 },
1294c286 997 M32R_INSN_ADD, "add", "add",
2e6dfccc 998 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 999 { 16, 16, 0xf0f0 }, 0xa0,
1294c286 1000 (PTR) & fmt_add_ops[0],
8d157f96 1001 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1002 },
a6cefe4f 1003/* add3 $dr,$sr,$hash$slo16 */
9c03036a 1004 {
23cf992f 1005 { 1, 1, 1, 1 },
1294c286 1006 M32R_INSN_ADD3, "add3", "add3",
2e6dfccc 1007 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
0bf55db8 1008 { 32, 32, 0xf0f00000 }, 0x80a00000,
1294c286 1009 (PTR) & fmt_add3_ops[0],
8d157f96 1010 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
7c26196f 1011 },
9c03036a
DE		 1012/* and $dr,$sr */
1013 {
23cf992f 1014 { 1, 1, 1, 1 },
1294c286 1015 M32R_INSN_AND, "and", "and",
2e6dfccc 1016 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1017 { 16, 16, 0xf0f0 }, 0xc0,
1294c286 1018 (PTR) & fmt_add_ops[0],
8d157f96 1019 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1020 },
9c03036a
DE		 1021/* and3 $dr,$sr,$uimm16 */
1022 {
23cf992f 1023 { 1, 1, 1, 1 },
1294c286 1024 M32R_INSN_AND3, "and3", "and3",
2e6dfccc 1025 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
0bf55db8 1026 { 32, 32, 0xf0f00000 }, 0x80c00000,
1294c286 1027 (PTR) & fmt_and3_ops[0],
a6cefe4f 1028 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1029 },
1030/* or $dr,$sr */
1031 {
23cf992f 1032 { 1, 1, 1, 1 },
1294c286 1033 M32R_INSN_OR, "or", "or",
2e6dfccc 1034 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1035 { 16, 16, 0xf0f0 }, 0xe0,
1294c286 1036 (PTR) & fmt_add_ops[0],
8d157f96 1037 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1038 },
a6cefe4f 1039/* or3 $dr,$sr,$hash$ulo16 */
7c26196f
DE		 1040 {
1041 { 1, 1, 1, 1 },
1294c286 1042 M32R_INSN_OR3, "or3", "or3",
2e6dfccc 1043 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
0bf55db8 1044 { 32, 32, 0xf0f00000 }, 0x80e00000,
1294c286 1045 (PTR) & fmt_or3_ops[0],
8d157f96 1046 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1047 },
9c03036a
DE		 1048/* xor $dr,$sr */
1049 {
23cf992f 1050 { 1, 1, 1, 1 },
1294c286 1051 M32R_INSN_XOR, "xor", "xor",
2e6dfccc 1052 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1053 { 16, 16, 0xf0f0 }, 0xd0,
1294c286 1054 (PTR) & fmt_add_ops[0],
8d157f96 1055 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1056 },
9c03036a
DE		 1057/* xor3 $dr,$sr,$uimm16 */
1058 {
23cf992f 1059 { 1, 1, 1, 1 },
1294c286 1060 M32R_INSN_XOR3, "xor3", "xor3",
2e6dfccc 1061 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
0bf55db8 1062 { 32, 32, 0xf0f00000 }, 0x80d00000,
1294c286 1063 (PTR) & fmt_and3_ops[0],
a6cefe4f 1064 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1065 },
1066/* addi $dr,$simm8 */
1067 {
23cf992f 1068 { 1, 1, 1, 1 },
1294c286 1069 M32R_INSN_ADDI, "addi", "addi",
2e6dfccc 1070 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
0bf55db8 1071 { 16, 16, 0xf000 }, 0x4000,
1294c286 1072 (PTR) & fmt_addi_ops[0],
a6cefe4f 1073 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1074 },
1075/* addv $dr,$sr */
1076 {
23cf992f 1077 { 1, 1, 1, 1 },
1294c286 1078 M32R_INSN_ADDV, "addv", "addv",
2e6dfccc 1079 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1080 { 16, 16, 0xf0f0 }, 0x80,
1294c286 1081 (PTR) & fmt_addv_ops[0],
8d157f96 1082 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1083 },
9c03036a
DE		 1084/* addv3 $dr,$sr,$simm16 */
1085 {
23cf992f 1086 { 1, 1, 1, 1 },
1294c286 1087 M32R_INSN_ADDV3, "addv3", "addv3",
2e6dfccc 1088 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 1089 { 32, 32, 0xf0f00000 }, 0x80800000,
1294c286 1090 (PTR) & fmt_addv3_ops[0],
a6cefe4f 1091 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1092 },
1093/* addx $dr,$sr */
1094 {
23cf992f 1095 { 1, 1, 1, 1 },
1294c286 1096 M32R_INSN_ADDX, "addx", "addx",
2e6dfccc 1097 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1098 { 16, 16, 0xf0f0 }, 0x90,
1294c286 1099 (PTR) & fmt_addx_ops[0],
8d157f96 1100 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1101 },
9c03036a
DE		 1102/* bc.s $disp8 */
1103 {
23cf992f 1104 { 1, 1, 1, 1 },
1294c286 1105 M32R_INSN_BC8, "bc8", "bc.s",
2e6dfccc 1106 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1107 { 16, 16, 0xff00 }, 0x7c00,
1294c286
DE		 1108 (PTR) & fmt_bc8_ops[0],
1109 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1110 },
1111/* bc.l $disp24 */
1112 {
23cf992f 1113 { 1, 1, 1, 1 },
1294c286 1114 M32R_INSN_BC24, "bc24", "bc.l",
2e6dfccc 1115 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1116 { 32, 32, 0xff000000 }, 0xfc000000,
1294c286
DE		 1117 (PTR) & fmt_bc24_ops[0],
1118 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1119 },
1120/* beq $src1,$src2,$disp16 */
1121 {
23cf992f 1122 { 1, 1, 1, 1 },
1294c286 1123 M32R_INSN_BEQ, "beq", "beq",
2e6dfccc 1124 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1125 { 32, 32, 0xf0f00000 }, 0xb0000000,
1294c286 1126 (PTR) & fmt_beq_ops[0],
8d157f96 1127 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1128 },
1129/* beqz $src2,$disp16 */
1130 {
23cf992f 1131 { 1, 1, 1, 1 },
1294c286 1132 M32R_INSN_BEQZ, "beqz", "beqz",
2e6dfccc 1133 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1134 { 32, 32, 0xfff00000 }, 0xb0800000,
1294c286 1135 (PTR) & fmt_beqz_ops[0],
8d157f96 1136 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1137 },
1138/* bgez $src2,$disp16 */
1139 {
23cf992f 1140 { 1, 1, 1, 1 },
1294c286 1141 M32R_INSN_BGEZ, "bgez", "bgez",
2e6dfccc 1142 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1143 { 32, 32, 0xfff00000 }, 0xb0b00000,
1294c286 1144 (PTR) & fmt_beqz_ops[0],
8d157f96 1145 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1146 },
1147/* bgtz $src2,$disp16 */
1148 {
23cf992f 1149 { 1, 1, 1, 1 },
1294c286 1150 M32R_INSN_BGTZ, "bgtz", "bgtz",
2e6dfccc 1151 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1152 { 32, 32, 0xfff00000 }, 0xb0d00000,
1294c286 1153 (PTR) & fmt_beqz_ops[0],
8d157f96 1154 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1155 },
1156/* blez $src2,$disp16 */
1157 {
23cf992f 1158 { 1, 1, 1, 1 },
1294c286 1159 M32R_INSN_BLEZ, "blez", "blez",
2e6dfccc 1160 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1161 { 32, 32, 0xfff00000 }, 0xb0c00000,
1294c286 1162 (PTR) & fmt_beqz_ops[0],
8d157f96 1163 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1164 },
1165/* bltz $src2,$disp16 */
1166 {
23cf992f 1167 { 1, 1, 1, 1 },
1294c286 1168 M32R_INSN_BLTZ, "bltz", "bltz",
2e6dfccc 1169 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1170 { 32, 32, 0xfff00000 }, 0xb0a00000,
1294c286 1171 (PTR) & fmt_beqz_ops[0],
8d157f96 1172 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1173 },
1174/* bnez $src2,$disp16 */
1175 {
23cf992f 1176 { 1, 1, 1, 1 },
1294c286 1177 M32R_INSN_BNEZ, "bnez", "bnez",
2e6dfccc 1178 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1179 { 32, 32, 0xfff00000 }, 0xb0900000,
1294c286 1180 (PTR) & fmt_beqz_ops[0],
8d157f96 1181 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1182 },
9c03036a
DE		 1183/* bl.s $disp8 */
1184 {
23cf992f 1185 { 1, 1, 1, 1 },
1294c286 1186 M32R_INSN_BL8, "bl8", "bl.s",
2e6dfccc 1187 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1188 { 16, 16, 0xff00 }, 0x7e00,
1294c286
DE		 1189 (PTR) & fmt_bl8_ops[0],
1190 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1191 },
1192/* bl.l $disp24 */
1193 {
23cf992f 1194 { 1, 1, 1, 1 },
1294c286 1195 M32R_INSN_BL24, "bl24", "bl.l",
2e6dfccc 1196 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1197 { 32, 32, 0xff000000 }, 0xfe000000,
1294c286
DE		 1198 (PTR) & fmt_bl24_ops[0],
1199 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
7c26196f 1200 },
7c26196f
DE		 1201/* start-sanitize-m32rx */
1202/* bcl.s $disp8 */
1203 {
1204 { 1, 1, 1, 1 },
1294c286 1205 M32R_INSN_BCL8, "bcl8", "bcl.s",
2e6dfccc 1206 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1207 { 16, 16, 0xff00 }, 0x7800,
1294c286
DE		 1208 (PTR) & fmt_bcl8_ops[0],
1209 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1210 },
1211/* end-sanitize-m32rx */
1212/* start-sanitize-m32rx */
1213/* bcl.l $disp24 */
1214 {
1215 { 1, 1, 1, 1 },
1294c286 1216 M32R_INSN_BCL24, "bcl24", "bcl.l",
2e6dfccc 1217 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1218 { 32, 32, 0xff000000 }, 0xf8000000,
1294c286
DE		 1219 (PTR) & fmt_bcl24_ops[0],
1220 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
9c03036a 1221 },
7c26196f 1222/* end-sanitize-m32rx */
9c03036a
DE		 1223/* bnc.s $disp8 */
1224 {
23cf992f 1225 { 1, 1, 1, 1 },
1294c286 1226 M32R_INSN_BNC8, "bnc8", "bnc.s",
2e6dfccc 1227 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1228 { 16, 16, 0xff00 }, 0x7d00,
1294c286
DE		 1229 (PTR) & fmt_bc8_ops[0],
1230 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1231 },
1232/* bnc.l $disp24 */
1233 {
23cf992f 1234 { 1, 1, 1, 1 },
1294c286 1235 M32R_INSN_BNC24, "bnc24", "bnc.l",
2e6dfccc 1236 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1237 { 32, 32, 0xff000000 }, 0xfd000000,
1294c286
DE		 1238 (PTR) & fmt_bc24_ops[0],
1239 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1240 },
1241/* bne $src1,$src2,$disp16 */
1242 {
23cf992f 1243 { 1, 1, 1, 1 },
1294c286 1244 M32R_INSN_BNE, "bne", "bne",
2e6dfccc 1245 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1246 { 32, 32, 0xf0f00000 }, 0xb0100000,
1294c286 1247 (PTR) & fmt_beq_ops[0],
8d157f96 1248 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1249 },
9c03036a
DE		 1250/* bra.s $disp8 */
1251 {
23cf992f 1252 { 1, 1, 1, 1 },
1294c286 1253 M32R_INSN_BRA8, "bra8", "bra.s",
2e6dfccc 1254 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1255 { 16, 16, 0xff00 }, 0x7f00,
1294c286
DE		 1256 (PTR) & fmt_bra8_ops[0],
1257 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1258 },
1259/* bra.l $disp24 */
1260 {
23cf992f 1261 { 1, 1, 1, 1 },
1294c286 1262 M32R_INSN_BRA24, "bra24", "bra.l",
2e6dfccc 1263 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1264 { 32, 32, 0xff000000 }, 0xff000000,
1294c286
DE		 1265 (PTR) & fmt_bra24_ops[0],
1266 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
7c26196f
DE		 1267 },
1268/* start-sanitize-m32rx */
7c26196f
DE		 1269/* bncl.s $disp8 */
1270 {
1271 { 1, 1, 1, 1 },
1294c286 1272 M32R_INSN_BNCL8, "bncl8", "bncl.s",
2e6dfccc 1273 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1274 { 16, 16, 0xff00 }, 0x7900,
1294c286
DE		 1275 (PTR) & fmt_bcl8_ops[0],
1276 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1277 },
1278/* end-sanitize-m32rx */
1279/* start-sanitize-m32rx */
1280/* bncl.l $disp24 */
1281 {
1282 { 1, 1, 1, 1 },
1294c286 1283 M32R_INSN_BNCL24, "bncl24", "bncl.l",
2e6dfccc 1284 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1285 { 32, 32, 0xff000000 }, 0xf9000000,
1294c286
DE		 1286 (PTR) & fmt_bcl24_ops[0],
1287 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 1288 },
1289/* end-sanitize-m32rx */
9c03036a
DE		 1290/* cmp $src1,$src2 */
1291 {
23cf992f 1292 { 1, 1, 1, 1 },
1294c286 1293 M32R_INSN_CMP, "cmp", "cmp",
2e6dfccc 1294 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1295 { 16, 16, 0xf0f0 }, 0x40,
1294c286 1296 (PTR) & fmt_cmp_ops[0],
8d157f96 1297 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1298 },
9c03036a
DE		 1299/* cmpi $src2,$simm16 */
1300 {
23cf992f 1301 { 1, 1, 1, 1 },
1294c286 1302 M32R_INSN_CMPI, "cmpi", "cmpi",
2e6dfccc 1303 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
0bf55db8 1304 { 32, 32, 0xfff00000 }, 0x80400000,
1294c286 1305 (PTR) & fmt_cmpi_ops[0],
a6cefe4f 1306 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1307 },
1308/* cmpu $src1,$src2 */
1309 {
23cf992f 1310 { 1, 1, 1, 1 },
1294c286 1311 M32R_INSN_CMPU, "cmpu", "cmpu",
2e6dfccc 1312 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1313 { 16, 16, 0xf0f0 }, 0x50,
1294c286 1314 (PTR) & fmt_cmp_ops[0],
8d157f96 1315 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1316 },
1294c286 1317/* cmpui $src2,$simm16 */
23cf992f
NC		 1318 {
1319 { 1, 1, 1, 1 },
1294c286 1320 M32R_INSN_CMPUI, "cmpui", "cmpui",
2e6dfccc 1321 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
0bf55db8 1322 { 32, 32, 0xfff00000 }, 0x80500000,
1294c286 1323 (PTR) & fmt_cmpi_ops[0],
a6cefe4f 1324 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
7c26196f
DE		 1325 },
1326/* start-sanitize-m32rx */
1327/* cmpeq $src1,$src2 */
1328 {
1329 { 1, 1, 1, 1 },
1294c286 1330 M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
2e6dfccc 1331 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1332 { 16, 16, 0xf0f0 }, 0x60,
1294c286 1333 (PTR) & fmt_cmp_ops[0],
8d157f96 1334 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 1335 },
1336/* end-sanitize-m32rx */
1337/* start-sanitize-m32rx */
1338/* cmpz $src2 */
1339 {
1340 { 1, 1, 1, 1 },
1294c286 1341 M32R_INSN_CMPZ, "cmpz", "cmpz",
2e6dfccc 1342 { { MNEM, ' ', OP (SRC2), 0 } },
0bf55db8 1343 { 16, 16, 0xfff0 }, 0x70,
1294c286 1344 (PTR) & fmt_cmpz_ops[0],
8d157f96 1345 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
9c03036a 1346 },
7c26196f 1347/* end-sanitize-m32rx */
9c03036a
DE		 1348/* div $dr,$sr */
1349 {
23cf992f 1350 { 1, 1, 1, 1 },
1294c286 1351 M32R_INSN_DIV, "div", "div",
2e6dfccc 1352 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1353 { 32, 32, 0xf0f0ffff }, 0x90000000,
1294c286 1354 (PTR) & fmt_div_ops[0],
8d157f96 1355 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1356 },
1357/* divu $dr,$sr */
1358 {
23cf992f 1359 { 1, 1, 1, 1 },
1294c286 1360 M32R_INSN_DIVU, "divu", "divu",
2e6dfccc 1361 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1362 { 32, 32, 0xf0f0ffff }, 0x90100000,
1294c286 1363 (PTR) & fmt_div_ops[0],
8d157f96 1364 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1365 },
1366/* rem $dr,$sr */
1367 {
23cf992f 1368 { 1, 1, 1, 1 },
1294c286 1369 M32R_INSN_REM, "rem", "rem",
2e6dfccc 1370 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1371 { 32, 32, 0xf0f0ffff }, 0x90200000,
1294c286 1372 (PTR) & fmt_div_ops[0],
8d157f96 1373 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1374 },
1375/* remu $dr,$sr */
1376 {
23cf992f 1377 { 1, 1, 1, 1 },
1294c286 1378 M32R_INSN_REMU, "remu", "remu",
2e6dfccc 1379 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1380 { 32, 32, 0xf0f0ffff }, 0x90300000,
1294c286 1381 (PTR) & fmt_div_ops[0],
8d157f96 1382 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
ab0bd049
DE		 1383 },
1384/* start-sanitize-m32rx */
1385/* divh $dr,$sr */
1386 {
1387 { 1, 1, 1, 1 },
1294c286 1388 M32R_INSN_DIVH, "divh", "divh",
2e6dfccc 1389 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1390 { 32, 32, 0xf0f0ffff }, 0x90000010,
1294c286 1391 (PTR) & fmt_div_ops[0],
8d157f96 1392 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f 1393 },
ab0bd049 1394/* end-sanitize-m32rx */
7c26196f
DE		 1395/* start-sanitize-m32rx */
1396/* jc $sr */
1397 {
1398 { 1, 1, 1, 1 },
1294c286 1399 M32R_INSN_JC, "jc", "jc",
2e6dfccc 1400 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1401 { 16, 16, 0xfff0 }, 0x1cc0,
1294c286 1402 (PTR) & fmt_jc_ops[0],
fbc8134d 1403 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1404 },
1405/* end-sanitize-m32rx */
1406/* start-sanitize-m32rx */
1407/* jnc $sr */
1408 {
1409 { 1, 1, 1, 1 },
1294c286 1410 M32R_INSN_JNC, "jnc", "jnc",
2e6dfccc 1411 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1412 { 16, 16, 0xfff0 }, 0x1dc0,
1294c286 1413 (PTR) & fmt_jc_ops[0],
fbc8134d 1414 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
9c03036a 1415 },
7c26196f 1416/* end-sanitize-m32rx */
9c03036a
DE		 1417/* jl $sr */
1418 {
23cf992f 1419 { 1, 1, 1, 1 },
1294c286 1420 M32R_INSN_JL, "jl", "jl",
2e6dfccc 1421 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1422 { 16, 16, 0xfff0 }, 0x1ec0,
1294c286 1423 (PTR) & fmt_jl_ops[0],
8d157f96 1424 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1425 },
1426/* jmp $sr */
1427 {
23cf992f 1428 { 1, 1, 1, 1 },
1294c286 1429 M32R_INSN_JMP, "jmp", "jmp",
2e6dfccc 1430 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1431 { 16, 16, 0xfff0 }, 0x1fc0,
1294c286 1432 (PTR) & fmt_jmp_ops[0],
8d157f96 1433 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1434 },
1435/* ld $dr,@$sr */
1436 {
23cf992f 1437 { 1, 1, 1, 1 },
1294c286 1438 M32R_INSN_LD, "ld", "ld",
2e6dfccc 1439 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1440 { 16, 16, 0xf0f0 }, 0x20c0,
1294c286 1441 (PTR) & fmt_ld_ops[0],
8d157f96 1442 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1443 },
9c03036a
DE		 1444/* ld $dr,@($slo16,$sr) */
1445 {
23cf992f 1446 { 1, 1, 1, 1 },
1294c286 1447 M32R_INSN_LD_D, "ld-d", "ld",
2e6dfccc 1448 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1449 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1294c286 1450 (PTR) & fmt_ld_d_ops[0],
8d157f96 1451 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1452 },
9c03036a
DE		 1453/* ldb $dr,@$sr */
1454 {
23cf992f 1455 { 1, 1, 1, 1 },
1294c286 1456 M32R_INSN_LDB, "ldb", "ldb",
2e6dfccc 1457 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1458 { 16, 16, 0xf0f0 }, 0x2080,
1294c286 1459 (PTR) & fmt_ldb_ops[0],
8d157f96 1460 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1461 },
9c03036a
DE		 1462/* ldb $dr,@($slo16,$sr) */
1463 {
23cf992f 1464 { 1, 1, 1, 1 },
1294c286 1465 M32R_INSN_LDB_D, "ldb-d", "ldb",
2e6dfccc 1466 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1467 { 32, 32, 0xf0f00000 }, 0xa0800000,
1294c286 1468 (PTR) & fmt_ldb_d_ops[0],
8d157f96 1469 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1470 },
9c03036a
DE		 1471/* ldh $dr,@$sr */
1472 {
23cf992f 1473 { 1, 1, 1, 1 },
1294c286 1474 M32R_INSN_LDH, "ldh", "ldh",
2e6dfccc 1475 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1476 { 16, 16, 0xf0f0 }, 0x20a0,
1294c286 1477 (PTR) & fmt_ldh_ops[0],
8d157f96 1478 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1479 },
9c03036a
DE		 1480/* ldh $dr,@($slo16,$sr) */
1481 {
23cf992f 1482 { 1, 1, 1, 1 },
1294c286 1483 M32R_INSN_LDH_D, "ldh-d", "ldh",
2e6dfccc 1484 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1485 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1294c286 1486 (PTR) & fmt_ldh_d_ops[0],
8d157f96 1487 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1488 },
9c03036a
DE		 1489/* ldub $dr,@$sr */
1490 {
23cf992f 1491 { 1, 1, 1, 1 },
1294c286 1492 M32R_INSN_LDUB, "ldub", "ldub",
2e6dfccc 1493 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1494 { 16, 16, 0xf0f0 }, 0x2090,
1294c286 1495 (PTR) & fmt_ldb_ops[0],
8d157f96 1496 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1497 },
9c03036a
DE		 1498/* ldub $dr,@($slo16,$sr) */
1499 {
23cf992f 1500 { 1, 1, 1, 1 },
1294c286 1501 M32R_INSN_LDUB_D, "ldub-d", "ldub",
2e6dfccc 1502 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1503 { 32, 32, 0xf0f00000 }, 0xa0900000,
1294c286 1504 (PTR) & fmt_ldb_d_ops[0],
8d157f96 1505 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1506 },
9c03036a
DE		 1507/* lduh $dr,@$sr */
1508 {
23cf992f 1509 { 1, 1, 1, 1 },
1294c286 1510 M32R_INSN_LDUH, "lduh", "lduh",
2e6dfccc 1511 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1512 { 16, 16, 0xf0f0 }, 0x20b0,
1294c286 1513 (PTR) & fmt_ldh_ops[0],
8d157f96 1514 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1515 },
9c03036a
DE		 1516/* lduh $dr,@($slo16,$sr) */
1517 {
23cf992f 1518 { 1, 1, 1, 1 },
1294c286 1519 M32R_INSN_LDUH_D, "lduh-d", "lduh",
2e6dfccc 1520 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1521 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1294c286 1522 (PTR) & fmt_ldh_d_ops[0],
8d157f96 1523 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1524 },
9c03036a
DE		 1525/* ld $dr,@$sr+ */
1526 {
23cf992f 1527 { 1, 1, 1, 1 },
1294c286 1528 M32R_INSN_LD_PLUS, "ld-plus", "ld",
2e6dfccc 1529 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
0bf55db8 1530 { 16, 16, 0xf0f0 }, 0x20e0,
1294c286 1531 (PTR) & fmt_ld_plus_ops[0],
8d157f96 1532 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1533 },
9c03036a
DE		 1534/* ld24 $dr,$uimm24 */
1535 {
23cf992f 1536 { 1, 1, 1, 1 },
1294c286 1537 M32R_INSN_LD24, "ld24", "ld24",
2e6dfccc 1538 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
0bf55db8 1539 { 32, 32, 0xf0000000 }, 0xe0000000,
1294c286 1540 (PTR) & fmt_ld24_ops[0],
a6cefe4f 1541 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1542 },
9c03036a
DE		 1543/* ldi8 $dr,$simm8 */
1544 {
23cf992f 1545 { 1, 1, 1, 1 },
1294c286 1546 M32R_INSN_LDI8, "ldi8", "ldi8",
2e6dfccc 1547 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
0bf55db8 1548 { 16, 16, 0xf000 }, 0x6000,
1294c286
DE		 1549 (PTR) & fmt_ldi8_ops[0],
1550 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1551 },
a6cefe4f 1552/* ldi16 $dr,$hash$slo16 */
9c03036a 1553 {
23cf992f 1554 { 1, 1, 1, 1 },
1294c286 1555 M32R_INSN_LDI16, "ldi16", "ldi16",
2e6dfccc 1556 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
0bf55db8 1557 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1294c286
DE		 1558 (PTR) & fmt_ldi16_ops[0],
1559 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1560 },
1561/* lock $dr,@$sr */
1562 {
23cf992f 1563 { 1, 1, 1, 1 },
1294c286 1564 M32R_INSN_LOCK, "lock", "lock",
2e6dfccc 1565 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1566 { 16, 16, 0xf0f0 }, 0x20d0,
1294c286 1567 (PTR) & fmt_lock_ops[0],
8d157f96 1568 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1569 },
1570/* machi $src1,$src2 */
1571 {
23cf992f 1572 { 1, 1, 1, 1 },
1294c286 1573 M32R_INSN_MACHI, "machi", "machi",
2e6dfccc 1574 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1575 { 16, 16, 0xf0f0 }, 0x3040,
1294c286 1576 (PTR) & fmt_machi_ops[0],
8d157f96 1577 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1578 },
1579/* start-sanitize-m32rx */
1580/* machi $src1,$src2,$acc */
1581 {
1582 { 1, 1, 1, 1 },
1294c286 1583 M32R_INSN_MACHI_A, "machi-a", "machi",
2e6dfccc 1584 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1585 { 16, 16, 0xf070 }, 0x3040,
1294c286 1586 (PTR) & fmt_machi_a_ops[0],
8d157f96 1587 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1588 },
7c26196f 1589/* end-sanitize-m32rx */
9c03036a
DE		 1590/* maclo $src1,$src2 */
1591 {
23cf992f 1592 { 1, 1, 1, 1 },
1294c286 1593 M32R_INSN_MACLO, "maclo", "maclo",
2e6dfccc 1594 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1595 { 16, 16, 0xf0f0 }, 0x3050,
1294c286 1596 (PTR) & fmt_machi_ops[0],
8d157f96 1597 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1598 },
7c26196f
DE		 1599/* start-sanitize-m32rx */
1600/* maclo $src1,$src2,$acc */
1601 {
1602 { 1, 1, 1, 1 },
1294c286 1603 M32R_INSN_MACLO_A, "maclo-a", "maclo",
2e6dfccc 1604 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1605 { 16, 16, 0xf070 }, 0x3050,
1294c286 1606 (PTR) & fmt_machi_a_ops[0],
8d157f96 1607 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1608 },
1609/* end-sanitize-m32rx */
9c03036a
DE		 1610/* macwhi $src1,$src2 */
1611 {
23cf992f 1612 { 1, 1, 1, 1 },
1294c286 1613 M32R_INSN_MACWHI, "macwhi", "macwhi",
2e6dfccc 1614 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1615 { 16, 16, 0xf0f0 }, 0x3060,
1294c286 1616 (PTR) & fmt_machi_ops[0],
8d157f96 1617 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1618 },
1619/* macwlo $src1,$src2 */
1620 {
23cf992f 1621 { 1, 1, 1, 1 },
1294c286 1622 M32R_INSN_MACWLO, "macwlo", "macwlo",
2e6dfccc 1623 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1624 { 16, 16, 0xf0f0 }, 0x3070,
1294c286 1625 (PTR) & fmt_machi_ops[0],
8d157f96 1626 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1627 },
1628/* mul $dr,$sr */
1629 {
23cf992f 1630 { 1, 1, 1, 1 },
1294c286 1631 M32R_INSN_MUL, "mul", "mul",
2e6dfccc 1632 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1633 { 16, 16, 0xf0f0 }, 0x1060,
1294c286 1634 (PTR) & fmt_add_ops[0],
8d157f96 1635 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1636 },
1637/* mulhi $src1,$src2 */
1638 {
23cf992f 1639 { 1, 1, 1, 1 },
1294c286 1640 M32R_INSN_MULHI, "mulhi", "mulhi",
2e6dfccc 1641 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1642 { 16, 16, 0xf0f0 }, 0x3000,
1294c286 1643 (PTR) & fmt_mulhi_ops[0],
8d157f96 1644 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1645 },
1646/* start-sanitize-m32rx */
1647/* mulhi $src1,$src2,$acc */
1648 {
1649 { 1, 1, 1, 1 },
1294c286 1650 M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
2e6dfccc 1651 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1652 { 16, 16, 0xf070 }, 0x3000,
1294c286 1653 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1654 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1655 },
7c26196f 1656/* end-sanitize-m32rx */
9c03036a
DE		 1657/* mullo $src1,$src2 */
1658 {
23cf992f 1659 { 1, 1, 1, 1 },
1294c286 1660 M32R_INSN_MULLO, "mullo", "mullo",
2e6dfccc 1661 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1662 { 16, 16, 0xf0f0 }, 0x3010,
1294c286 1663 (PTR) & fmt_mulhi_ops[0],
8d157f96 1664 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1665 },
7c26196f
DE		 1666/* start-sanitize-m32rx */
1667/* mullo $src1,$src2,$acc */
1668 {
1669 { 1, 1, 1, 1 },
1294c286 1670 M32R_INSN_MULLO_A, "mullo-a", "mullo",
2e6dfccc 1671 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1672 { 16, 16, 0xf070 }, 0x3010,
1294c286 1673 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1674 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1675 },
1676/* end-sanitize-m32rx */
9c03036a
DE		 1677/* mulwhi $src1,$src2 */
1678 {
23cf992f 1679 { 1, 1, 1, 1 },
1294c286 1680 M32R_INSN_MULWHI, "mulwhi", "mulwhi",
2e6dfccc 1681 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1682 { 16, 16, 0xf0f0 }, 0x3020,
1294c286 1683 (PTR) & fmt_mulhi_ops[0],
8d157f96 1684 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1685 },
1686/* mulwlo $src1,$src2 */
1687 {
23cf992f 1688 { 1, 1, 1, 1 },
1294c286 1689 M32R_INSN_MULWLO, "mulwlo", "mulwlo",
2e6dfccc 1690 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1691 { 16, 16, 0xf0f0 }, 0x3030,
1294c286 1692 (PTR) & fmt_mulhi_ops[0],
8d157f96 1693 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1694 },
1695/* mv $dr,$sr */
1696 {
23cf992f 1697 { 1, 1, 1, 1 },
1294c286 1698 M32R_INSN_MV, "mv", "mv",
2e6dfccc 1699 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1700 { 16, 16, 0xf0f0 }, 0x1080,
1294c286 1701 (PTR) & fmt_mv_ops[0],
8d157f96 1702 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1703 },
1704/* mvfachi $dr */
1705 {
23cf992f 1706 { 1, 1, 1, 1 },
1294c286 1707 M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
2e6dfccc 1708 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1709 { 16, 16, 0xf0ff }, 0x50f0,
1294c286 1710 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1711 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1712 },
1713/* start-sanitize-m32rx */
1714/* mvfachi $dr,$accs */
1715 {
1716 { 1, 1, 1, 1 },
1294c286 1717 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
2e6dfccc 1718 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1719 { 16, 16, 0xf0f3 }, 0x50f0,
1294c286 1720 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1721 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1722 },
7c26196f 1723/* end-sanitize-m32rx */
9c03036a
DE		 1724/* mvfaclo $dr */
1725 {
23cf992f 1726 { 1, 1, 1, 1 },
1294c286 1727 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
2e6dfccc 1728 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1729 { 16, 16, 0xf0ff }, 0x50f1,
1294c286 1730 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1731 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1732 },
7c26196f
DE		 1733/* start-sanitize-m32rx */
1734/* mvfaclo $dr,$accs */
1735 {
1736 { 1, 1, 1, 1 },
1294c286 1737 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
2e6dfccc 1738 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1739 { 16, 16, 0xf0f3 }, 0x50f1,
1294c286 1740 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1741 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1742 },
1743/* end-sanitize-m32rx */
9c03036a
DE		 1744/* mvfacmi $dr */
1745 {
23cf992f 1746 { 1, 1, 1, 1 },
1294c286 1747 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
2e6dfccc 1748 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1749 { 16, 16, 0xf0ff }, 0x50f2,
1294c286 1750 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1751 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1752 },
1753/* start-sanitize-m32rx */
1754/* mvfacmi $dr,$accs */
1755 {
1756 { 1, 1, 1, 1 },
1294c286 1757 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
2e6dfccc 1758 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1759 { 16, 16, 0xf0f3 }, 0x50f2,
1294c286 1760 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1761 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1762 },
7c26196f 1763/* end-sanitize-m32rx */
9c03036a
DE		 1764/* mvfc $dr,$scr */
1765 {
23cf992f 1766 { 1, 1, 1, 1 },
1294c286 1767 M32R_INSN_MVFC, "mvfc", "mvfc",
2e6dfccc 1768 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
0bf55db8 1769 { 16, 16, 0xf0f0 }, 0x1090,
1294c286 1770 (PTR) & fmt_mvfc_ops[0],
8d157f96 1771 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1772 },
1773/* mvtachi $src1 */
1774 {
23cf992f 1775 { 1, 1, 1, 1 },
1294c286 1776 M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
2e6dfccc 1777 { { MNEM, ' ', OP (SRC1), 0 } },
0bf55db8 1778 { 16, 16, 0xf0ff }, 0x5070,
1294c286 1779 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1780 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1781 },
7c26196f
DE		 1782/* start-sanitize-m32rx */
1783/* mvtachi $src1,$accs */
1784 {
1785 { 1, 1, 1, 1 },
1294c286 1786 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
2e6dfccc 1787 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
0bf55db8 1788 { 16, 16, 0xf0f3 }, 0x5070,
1294c286 1789 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1790 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1791 },
1792/* end-sanitize-m32rx */
9c03036a
DE		 1793/* mvtaclo $src1 */
1794 {
23cf992f 1795 { 1, 1, 1, 1 },
1294c286 1796 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
2e6dfccc 1797 { { MNEM, ' ', OP (SRC1), 0 } },
0bf55db8 1798 { 16, 16, 0xf0ff }, 0x5071,
1294c286 1799 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1800 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1801 },
1802/* start-sanitize-m32rx */
1803/* mvtaclo $src1,$accs */
1804 {
1805 { 1, 1, 1, 1 },
1294c286 1806 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
2e6dfccc 1807 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
0bf55db8 1808 { 16, 16, 0xf0f3 }, 0x5071,
1294c286 1809 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1810 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1811 },
7c26196f 1812/* end-sanitize-m32rx */
9c03036a
DE		 1813/* mvtc $sr,$dcr */
1814 {
23cf992f 1815 { 1, 1, 1, 1 },
1294c286 1816 M32R_INSN_MVTC, "mvtc", "mvtc",
2e6dfccc 1817 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
0bf55db8 1818 { 16, 16, 0xf0f0 }, 0x10a0,
1294c286 1819 (PTR) & fmt_mvtc_ops[0],
8d157f96 1820 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1821 },
1822/* neg $dr,$sr */
1823 {
23cf992f 1824 { 1, 1, 1, 1 },
1294c286 1825 M32R_INSN_NEG, "neg", "neg",
2e6dfccc 1826 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1827 { 16, 16, 0xf0f0 }, 0x30,
1294c286 1828 (PTR) & fmt_mv_ops[0],
8d157f96 1829 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1830 },
1831/* nop */
1832 {
23cf992f 1833 { 1, 1, 1, 1 },
1294c286 1834 M32R_INSN_NOP, "nop", "nop",
2e6dfccc 1835 { { MNEM, 0 } },
0bf55db8 1836 { 16, 16, 0xffff }, 0x7000,
1294c286 1837 (PTR) 0,
8d157f96 1838 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1839 },
1840/* not $dr,$sr */
1841 {
23cf992f 1842 { 1, 1, 1, 1 },
1294c286 1843 M32R_INSN_NOT, "not", "not",
2e6dfccc 1844 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1845 { 16, 16, 0xf0f0 }, 0xb0,
1294c286 1846 (PTR) & fmt_mv_ops[0],
8d157f96 1847 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1848 },
1849/* rac */
1850 {
23cf992f 1851 { 1, 1, 1, 1 },
1294c286 1852 M32R_INSN_RAC, "rac", "rac",
2e6dfccc 1853 { { MNEM, 0 } },
0bf55db8 1854 { 16, 16, 0xffff }, 0x5090,
1294c286 1855 (PTR) & fmt_rac_ops[0],
8d157f96 1856 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1857 },
1858/* start-sanitize-m32rx */
a6cefe4f 1859/* rac $accd,$accs,$imm1 */
ab0bd049
DE		 1860 {
1861 { 1, 1, 1, 1 },
1294c286 1862 M32R_INSN_RAC_DSI, "rac-dsi", "rac",
2e6dfccc 1863 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
0bf55db8 1864 { 16, 16, 0xf3f2 }, 0x5090,
1294c286 1865 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 1866 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1867 },
7c26196f 1868/* end-sanitize-m32rx */
9c03036a
DE		 1869/* rach */
1870 {
23cf992f 1871 { 1, 1, 1, 1 },
1294c286 1872 M32R_INSN_RACH, "rach", "rach",
2e6dfccc 1873 { { MNEM, 0 } },
0bf55db8 1874 { 16, 16, 0xffff }, 0x5080,
1294c286 1875 (PTR) & fmt_rac_ops[0],
8d157f96 1876 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
ab0bd049
DE		 1877 },
1878/* start-sanitize-m32rx */
a6cefe4f 1879/* rach $accd,$accs,$imm1 */
7c26196f
DE		 1880 {
1881 { 1, 1, 1, 1 },
1294c286 1882 M32R_INSN_RACH_DSI, "rach-dsi", "rach",
2e6dfccc 1883 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
0bf55db8 1884 { 16, 16, 0xf3f2 }, 0x5080,
1294c286 1885 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 1886 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1887 },
7c26196f 1888/* end-sanitize-m32rx */
9c03036a
DE		 1889/* rte */
1890 {
23cf992f 1891 { 1, 1, 1, 1 },
1294c286 1892 M32R_INSN_RTE, "rte", "rte",
2e6dfccc 1893 { { MNEM, 0 } },
0bf55db8 1894 { 16, 16, 0xffff }, 0x10d6,
1294c286 1895 (PTR) & fmt_rte_ops[0],
8d157f96 1896 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
7c26196f 1897 },
a6cefe4f 1898/* seth $dr,$hash$hi16 */
7c26196f
DE		 1899 {
1900 { 1, 1, 1, 1 },
1294c286 1901 M32R_INSN_SETH, "seth", "seth",
2e6dfccc 1902 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
0bf55db8 1903 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
1294c286 1904 (PTR) & fmt_seth_ops[0],
8d157f96 1905 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1906 },
9c03036a
DE		 1907/* sll $dr,$sr */
1908 {
23cf992f 1909 { 1, 1, 1, 1 },
1294c286 1910 M32R_INSN_SLL, "sll", "sll",
2e6dfccc 1911 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1912 { 16, 16, 0xf0f0 }, 0x1040,
1294c286 1913 (PTR) & fmt_add_ops[0],
8d157f96 1914 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1915 },
9c03036a
DE		 1916/* sll3 $dr,$sr,$simm16 */
1917 {
23cf992f 1918 { 1, 1, 1, 1 },
1294c286 1919 M32R_INSN_SLL3, "sll3", "sll3",
2e6dfccc 1920 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 1921 { 32, 32, 0xf0f00000 }, 0x90c00000,
1294c286 1922 (PTR) & fmt_sll3_ops[0],
a6cefe4f 1923 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1924 },
1925/* slli $dr,$uimm5 */
1926 {
23cf992f 1927 { 1, 1, 1, 1 },
1294c286 1928 M32R_INSN_SLLI, "slli", "slli",
2e6dfccc 1929 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 1930 { 16, 16, 0xf0e0 }, 0x5040,
1294c286 1931 (PTR) & fmt_slli_ops[0],
a6cefe4f 1932 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1933 },
1934/* sra $dr,$sr */
1935 {
23cf992f 1936 { 1, 1, 1, 1 },
1294c286 1937 M32R_INSN_SRA, "sra", "sra",
2e6dfccc 1938 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1939 { 16, 16, 0xf0f0 }, 0x1020,
1294c286 1940 (PTR) & fmt_add_ops[0],
8d157f96 1941 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1942 },
9c03036a
DE		 1943/* sra3 $dr,$sr,$simm16 */
1944 {
23cf992f 1945 { 1, 1, 1, 1 },
1294c286 1946 M32R_INSN_SRA3, "sra3", "sra3",
2e6dfccc 1947 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 1948 { 32, 32, 0xf0f00000 }, 0x90a00000,
1294c286 1949 (PTR) & fmt_sll3_ops[0],
a6cefe4f 1950 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1951 },
1952/* srai $dr,$uimm5 */
1953 {
23cf992f 1954 { 1, 1, 1, 1 },
1294c286 1955 M32R_INSN_SRAI, "srai", "srai",
2e6dfccc 1956 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 1957 { 16, 16, 0xf0e0 }, 0x5020,
1294c286 1958 (PTR) & fmt_slli_ops[0],
a6cefe4f 1959 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1960 },
1961/* srl $dr,$sr */
1962 {
23cf992f 1963 { 1, 1, 1, 1 },
1294c286 1964 M32R_INSN_SRL, "srl", "srl",
2e6dfccc 1965 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1966 { 16, 16, 0xf0f0 }, 0x1000,
1294c286 1967 (PTR) & fmt_add_ops[0],
8d157f96 1968 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1969 },
9c03036a
DE		 1970/* srl3 $dr,$sr,$simm16 */
1971 {
23cf992f 1972 { 1, 1, 1, 1 },
1294c286 1973 M32R_INSN_SRL3, "srl3", "srl3",
2e6dfccc 1974 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 1975 { 32, 32, 0xf0f00000 }, 0x90800000,
1294c286 1976 (PTR) & fmt_sll3_ops[0],
a6cefe4f 1977 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1978 },
1979/* srli $dr,$uimm5 */
1980 {
23cf992f 1981 { 1, 1, 1, 1 },
1294c286 1982 M32R_INSN_SRLI, "srli", "srli",
2e6dfccc 1983 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 1984 { 16, 16, 0xf0e0 }, 0x5000,
1294c286 1985 (PTR) & fmt_slli_ops[0],
a6cefe4f 1986 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1987 },
1988/* st $src1,@$src2 */
1989 {
23cf992f 1990 { 1, 1, 1, 1 },
1294c286 1991 M32R_INSN_ST, "st", "st",
2e6dfccc 1992 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 1993 { 16, 16, 0xf0f0 }, 0x2040,
1294c286 1994 (PTR) & fmt_st_ops[0],
8d157f96 1995 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1996 },
9c03036a
DE		 1997/* st $src1,@($slo16,$src2) */
1998 {
23cf992f 1999 { 1, 1, 1, 1 },
1294c286 2000 M32R_INSN_ST_D, "st-d", "st",
2e6dfccc 2001 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2002 { 32, 32, 0xf0f00000 }, 0xa0400000,
1294c286 2003 (PTR) & fmt_st_d_ops[0],
8d157f96 2004 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2005 },
9c03036a
DE		 2006/* stb $src1,@$src2 */
2007 {
23cf992f 2008 { 1, 1, 1, 1 },
1294c286 2009 M32R_INSN_STB, "stb", "stb",
2e6dfccc 2010 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2011 { 16, 16, 0xf0f0 }, 0x2000,
1294c286 2012 (PTR) & fmt_stb_ops[0],
8d157f96 2013 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2014 },
1294c286 2015/* stb $src1,@($slo16,$src2) */
9c03036a 2016 {
23cf992f 2017 { 1, 1, 1, 1 },
1294c286 2018 M32R_INSN_STB_D, "stb-d", "stb",
2e6dfccc 2019 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2020 { 32, 32, 0xf0f00000 }, 0xa0000000,
1294c286 2021 (PTR) & fmt_stb_d_ops[0],
8d157f96 2022 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2023 },
9c03036a
DE		 2024/* sth $src1,@$src2 */
2025 {
23cf992f 2026 { 1, 1, 1, 1 },
1294c286 2027 M32R_INSN_STH, "sth", "sth",
2e6dfccc 2028 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2029 { 16, 16, 0xf0f0 }, 0x2020,
1294c286 2030 (PTR) & fmt_sth_ops[0],
8d157f96 2031 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2032 },
9c03036a
DE		 2033/* sth $src1,@($slo16,$src2) */
2034 {
23cf992f 2035 { 1, 1, 1, 1 },
1294c286 2036 M32R_INSN_STH_D, "sth-d", "sth",
2e6dfccc 2037 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2038 { 32, 32, 0xf0f00000 }, 0xa0200000,
1294c286 2039 (PTR) & fmt_sth_d_ops[0],
8d157f96 2040 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2041 },
9c03036a
DE		 2042/* st $src1,@+$src2 */
2043 {
23cf992f 2044 { 1, 1, 1, 1 },
1294c286 2045 M32R_INSN_ST_PLUS, "st-plus", "st",
2e6dfccc 2046 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
0bf55db8 2047 { 16, 16, 0xf0f0 }, 0x2060,
1294c286 2048 (PTR) & fmt_st_plus_ops[0],
8d157f96 2049 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2050 },
2051/* st $src1,@-$src2 */
2052 {
23cf992f 2053 { 1, 1, 1, 1 },
1294c286 2054 M32R_INSN_ST_MINUS, "st-minus", "st",
2e6dfccc 2055 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
0bf55db8 2056 { 16, 16, 0xf0f0 }, 0x2070,
1294c286 2057 (PTR) & fmt_st_plus_ops[0],
8d157f96 2058 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2059 },
2060/* sub $dr,$sr */
2061 {
23cf992f 2062 { 1, 1, 1, 1 },
1294c286 2063 M32R_INSN_SUB, "sub", "sub",
2e6dfccc 2064 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2065 { 16, 16, 0xf0f0 }, 0x20,
1294c286 2066 (PTR) & fmt_add_ops[0],
8d157f96 2067 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 2068 },
2069/* subv $dr,$sr */
2070 {
23cf992f 2071 { 1, 1, 1, 1 },
1294c286 2072 M32R_INSN_SUBV, "subv", "subv",
2e6dfccc 2073 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2074 { 16, 16, 0xf0f0 }, 0x0,
1294c286 2075 (PTR) & fmt_addv_ops[0],
8d157f96 2076 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 2077 },
2078/* subx $dr,$sr */
2079 {
23cf992f 2080 { 1, 1, 1, 1 },
1294c286 2081 M32R_INSN_SUBX, "subx", "subx",
2e6dfccc 2082 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2083 { 16, 16, 0xf0f0 }, 0x10,
1294c286 2084 (PTR) & fmt_addx_ops[0],
8d157f96 2085 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 2086 },
a6cefe4f 2087/* trap $uimm4 */
7c26196f
DE		 2088 {
2089 { 1, 1, 1, 1 },
1294c286 2090 M32R_INSN_TRAP, "trap", "trap",
2e6dfccc 2091 { { MNEM, ' ', OP (UIMM4), 0 } },
0bf55db8 2092 { 16, 16, 0xfff0 }, 0x10f0,
1294c286 2093 (PTR) & fmt_trap_ops[0],
8d157f96 2094 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a 2095 },
9c03036a
DE		 2096/* unlock $src1,@$src2 */
2097 {
23cf992f 2098 { 1, 1, 1, 1 },
1294c286 2099 M32R_INSN_UNLOCK, "unlock", "unlock",
2e6dfccc 2100 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2101 { 16, 16, 0xf0f0 }, 0x2050,
1294c286 2102 (PTR) & fmt_unlock_ops[0],
8d157f96 2103 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2104 },
7c26196f 2105/* start-sanitize-m32rx */
b02643b5 2106/* satb $dr,$sr */
7c26196f
DE		 2107 {
2108 { 1, 1, 1, 1 },
1294c286 2109 M32R_INSN_SATB, "satb", "satb",
2e6dfccc 2110 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
d8ca5fae 2111 { 32, 32, 0xf0f0ffff }, 0x80600300,
1294c286 2112 (PTR) & fmt_satb_ops[0],
8d157f96 2113 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2114 },
2115/* end-sanitize-m32rx */
2116/* start-sanitize-m32rx */
b02643b5 2117/* sath $dr,$sr */
7c26196f
DE		 2118 {
2119 { 1, 1, 1, 1 },
1294c286 2120 M32R_INSN_SATH, "sath", "sath",
2e6dfccc 2121 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
b2ddf0c4 2122 { 32, 32, 0xf0f0ffff }, 0x80600200,
1294c286 2123 (PTR) & fmt_satb_ops[0],
8d157f96 2124 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2125 },
2126/* end-sanitize-m32rx */
2127/* start-sanitize-m32rx */
b02643b5 2128/* sat $dr,$sr */
7c26196f
DE		 2129 {
2130 { 1, 1, 1, 1 },
1294c286 2131 M32R_INSN_SAT, "sat", "sat",
2e6dfccc 2132 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
d8ca5fae 2133 { 32, 32, 0xf0f0ffff }, 0x80600000,
1294c286 2134 (PTR) & fmt_sat_ops[0],
fbc8134d 2135 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2136 },
2137/* end-sanitize-m32rx */
2138/* start-sanitize-m32rx */
2139/* pcmpbz $src2 */
2140 {
2141 { 1, 1, 1, 1 },
1294c286 2142 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2e6dfccc 2143 { { MNEM, ' ', OP (SRC2), 0 } },
0bf55db8 2144 { 16, 16, 0xfff0 }, 0x370,
1294c286 2145 (PTR) & fmt_cmpz_ops[0],
fbc8134d 2146 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 2147 },
2148/* end-sanitize-m32rx */
2149/* start-sanitize-m32rx */
2150/* sadd */
2151 {
2152 { 1, 1, 1, 1 },
1294c286 2153 M32R_INSN_SADD, "sadd", "sadd",
2e6dfccc 2154 { { MNEM, 0 } },
0bf55db8 2155 { 16, 16, 0xffff }, 0x50e4,
1294c286 2156 (PTR) & fmt_sadd_ops[0],
8d157f96 2157 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2158 },
7c26196f
DE		 2159/* end-sanitize-m32rx */
2160/* start-sanitize-m32rx */
2161/* macwu1 $src1,$src2 */
2162 {
2163 { 1, 1, 1, 1 },
1294c286 2164 M32R_INSN_MACWU1, "macwu1", "macwu1",
2e6dfccc 2165 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2166 { 16, 16, 0xf0f0 }, 0x50b0,
1294c286 2167 (PTR) & fmt_macwu1_ops[0],
8d157f96 2168 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2169 },
2170/* end-sanitize-m32rx */
2171/* start-sanitize-m32rx */
2172/* msblo $src1,$src2 */
2173 {
2174 { 1, 1, 1, 1 },
1294c286 2175 M32R_INSN_MSBLO, "msblo", "msblo",
2e6dfccc 2176 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2177 { 16, 16, 0xf0f0 }, 0x50d0,
1294c286 2178 (PTR) & fmt_machi_ops[0],
8d157f96 2179 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2180 },
2181/* end-sanitize-m32rx */
2182/* start-sanitize-m32rx */
2183/* mulwu1 $src1,$src2 */
2184 {
2185 { 1, 1, 1, 1 },
1294c286 2186 M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2e6dfccc 2187 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2188 { 16, 16, 0xf0f0 }, 0x50a0,
1294c286 2189 (PTR) & fmt_mulwu1_ops[0],
8d157f96 2190 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2191 },
2192/* end-sanitize-m32rx */
2193/* start-sanitize-m32rx */
ab0bd049 2194/* maclh1 $src1,$src2 */
7c26196f
DE		 2195 {
2196 { 1, 1, 1, 1 },
1294c286 2197 M32R_INSN_MACLH1, "maclh1", "maclh1",
2e6dfccc 2198 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2199 { 16, 16, 0xf0f0 }, 0x50c0,
1294c286 2200 (PTR) & fmt_macwu1_ops[0],
8d157f96 2201 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2202 },
2203/* end-sanitize-m32rx */
2204/* start-sanitize-m32rx */
2205/* sc */
2206 {
2207 { 1, 1, 1, 1 },
1294c286 2208 M32R_INSN_SC, "sc", "sc",
2e6dfccc 2209 { { MNEM, 0 } },
0bf55db8 2210 { 16, 16, 0xffff }, 0x7401,
1294c286 2211 (PTR) & fmt_sc_ops[0],
fbc8134d 2212 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2213 },
2214/* end-sanitize-m32rx */
2215/* start-sanitize-m32rx */
2216/* snc */
2217 {
2218 { 1, 1, 1, 1 },
1294c286 2219 M32R_INSN_SNC, "snc", "snc",
2e6dfccc 2220 { { MNEM, 0 } },
0bf55db8 2221 { 16, 16, 0xffff }, 0x7501,
1294c286 2222 (PTR) & fmt_sc_ops[0],
fbc8134d 2223 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2224 },
2225/* end-sanitize-m32rx */
9c03036a
DE		 2226};
2227
23cf992f 2228#undef A
0bf55db8
DE		 2229#undef MNEM
2230#undef OP
23cf992f 2231
1294c286 2232static CGEN_INSN_TABLE insn_table =
853713a7 2233{
9c03036a 2234 & m32r_cgen_insn_table_entries[0],
23cf992f 2235 sizeof (CGEN_INSN),
7c26196f 2236 MAX_INSNS,
1294c286
DE		 2237 NULL
2238};
2239
2240/* Each non-simple macro entry points to an array of expansion possibilities. */
2241
2242#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2243#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2244#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2245
2246/* The macro instruction table. */
2247
2248static const CGEN_INSN macro_insn_table_entries[] =
2249{
2250/* bc $disp8 */
2251 {
2252 { 1, 1, 1, 1 },
2253 -1, "bc8r", "bc",
2e6dfccc 2254 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2255 { 16, 16, 0xff00 }, 0x7c00,
2256 (PTR) 0,
2257 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2258 },
2259/* bc $disp24 */
2260 {
2261 { 1, 1, 1, 1 },
2262 -1, "bc24r", "bc",
2e6dfccc 2263 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2264 { 32, 32, 0xff000000 }, 0xfc000000,
2265 (PTR) 0,
2266 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2267 },
2268/* bl $disp8 */
2269 {
2270 { 1, 1, 1, 1 },
2271 -1, "bl8r", "bl",
2e6dfccc 2272 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2273 { 16, 16, 0xff00 }, 0x7e00,
2274 (PTR) 0,
2275 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2276 },
2277/* bl $disp24 */
2278 {
2279 { 1, 1, 1, 1 },
2280 -1, "bl24r", "bl",
2e6dfccc 2281 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2282 { 32, 32, 0xff000000 }, 0xfe000000,
2283 (PTR) 0,
2284 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2285 },
2286/* bcl $disp8 */
2287 {
2288 { 1, 1, 1, 1 },
2289 -1, "bcl8r", "bcl",
2e6dfccc 2290 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2291 { 16, 16, 0xff00 }, 0x7800,
2292 (PTR) 0,
2293 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2294 },
2295/* bcl $disp24 */
2296 {
2297 { 1, 1, 1, 1 },
2298 -1, "bcl24r", "bcl",
2e6dfccc 2299 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2300 { 32, 32, 0xff000000 }, 0xf8000000,
2301 (PTR) 0,
2302 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2303 },
2304/* bnc $disp8 */
2305 {
2306 { 1, 1, 1, 1 },
2307 -1, "bnc8r", "bnc",
2e6dfccc 2308 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2309 { 16, 16, 0xff00 }, 0x7d00,
2310 (PTR) 0,
2311 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2312 },
2313/* bnc $disp24 */
2314 {
2315 { 1, 1, 1, 1 },
2316 -1, "bnc24r", "bnc",
2e6dfccc 2317 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2318 { 32, 32, 0xff000000 }, 0xfd000000,
2319 (PTR) 0,
2320 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2321 },
2322/* bra $disp8 */
2323 {
2324 { 1, 1, 1, 1 },
2325 -1, "bra8r", "bra",
2e6dfccc 2326 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2327 { 16, 16, 0xff00 }, 0x7f00,
2328 (PTR) 0,
2329 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2330 },
2331/* bra $disp24 */
2332 {
2333 { 1, 1, 1, 1 },
2334 -1, "bra24r", "bra",
2e6dfccc 2335 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2336 { 32, 32, 0xff000000 }, 0xff000000,
2337 (PTR) 0,
2338 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2339 },
2340/* bncl $disp8 */
2341 {
2342 { 1, 1, 1, 1 },
2343 -1, "bncl8r", "bncl",
2e6dfccc 2344 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2345 { 16, 16, 0xff00 }, 0x7900,
2346 (PTR) 0,
2347 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2348 },
2349/* bncl $disp24 */
2350 {
2351 { 1, 1, 1, 1 },
2352 -1, "bncl24r", "bncl",
2e6dfccc 2353 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2354 { 32, 32, 0xff000000 }, 0xf9000000,
2355 (PTR) 0,
2356 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2357 },
2358/* ld $dr,@($sr) */
2359 {
2360 { 1, 1, 1, 1 },
2361 -1, "ld-2", "ld",
2e6dfccc 2362 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2363 { 16, 16, 0xf0f0 }, 0x20c0,
2364 (PTR) 0,
2365 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2366 },
2367/* ld $dr,@($sr,$slo16) */
2368 {
2369 { 1, 1, 1, 1 },
2370 -1, "ld-d2", "ld",
2e6dfccc 2371 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2372 { 32, 32, 0xf0f00000 }, 0xa0c00000,
2373 (PTR) 0,
2374 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2375 },
2376/* ldb $dr,@($sr) */
2377 {
2378 { 1, 1, 1, 1 },
2379 -1, "ldb-2", "ldb",
2e6dfccc 2380 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2381 { 16, 16, 0xf0f0 }, 0x2080,
2382 (PTR) 0,
2383 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2384 },
2385/* ldb $dr,@($sr,$slo16) */
2386 {
2387 { 1, 1, 1, 1 },
2388 -1, "ldb-d2", "ldb",
2e6dfccc 2389 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2390 { 32, 32, 0xf0f00000 }, 0xa0800000,
2391 (PTR) 0,
2392 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2393 },
2394/* ldh $dr,@($sr) */
2395 {
2396 { 1, 1, 1, 1 },
2397 -1, "ldh-2", "ldh",
2e6dfccc 2398 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2399 { 16, 16, 0xf0f0 }, 0x20a0,
2400 (PTR) 0,
2401 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2402 },
2403/* ldh $dr,@($sr,$slo16) */
2404 {
2405 { 1, 1, 1, 1 },
2406 -1, "ldh-d2", "ldh",
2e6dfccc 2407 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2408 { 32, 32, 0xf0f00000 }, 0xa0a00000,
2409 (PTR) 0,
2410 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2411 },
2412/* ldub $dr,@($sr) */
2413 {
2414 { 1, 1, 1, 1 },
2415 -1, "ldub-2", "ldub",
2e6dfccc 2416 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2417 { 16, 16, 0xf0f0 }, 0x2090,
2418 (PTR) 0,
2419 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2420 },
2421/* ldub $dr,@($sr,$slo16) */
2422 {
2423 { 1, 1, 1, 1 },
2424 -1, "ldub-d2", "ldub",
2e6dfccc 2425 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2426 { 32, 32, 0xf0f00000 }, 0xa0900000,
2427 (PTR) 0,
2428 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2429 },
2430/* lduh $dr,@($sr) */
2431 {
2432 { 1, 1, 1, 1 },
2433 -1, "lduh-2", "lduh",
2e6dfccc 2434 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2435 { 16, 16, 0xf0f0 }, 0x20b0,
2436 (PTR) 0,
2437 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2438 },
2439/* lduh $dr,@($sr,$slo16) */
2440 {
2441 { 1, 1, 1, 1 },
2442 -1, "lduh-d2", "lduh",
2e6dfccc 2443 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2444 { 32, 32, 0xf0f00000 }, 0xa0b00000,
2445 (PTR) 0,
2446 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2447 },
2448/* pop $dr */
2449 {
2450 { 1, 1, 1, 1 },
2451 -1, "pop", "pop",
2e6dfccc 2452 { { MNEM, ' ', OP (DR), 0 } },
1294c286
DE		 2453 { 16, 16, 0xf0ff }, 0x20ef,
2454 (PTR) 0,
2455 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2456 },
2457/* ldi $dr,$simm8 */
2458 {
2459 { 1, 1, 1, 1 },
2460 -1, "ldi8a", "ldi",
2e6dfccc 2461 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1294c286
DE		 2462 { 16, 16, 0xf000 }, 0x6000,
2463 (PTR) 0,
2464 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2465 },
2466/* ldi $dr,$hash$slo16 */
2467 {
2468 { 1, 1, 1, 1 },
2469 -1, "ldi16a", "ldi",
2e6dfccc 2470 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1294c286
DE		 2471 { 32, 32, 0xf0ff0000 }, 0x90f00000,
2472 (PTR) 0,
2473 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2474 },
2475/* rac $accd */
2476 {
2477 { 1, 1, 1, 1 },
2478 -1, "rac-d", "rac",
2e6dfccc 2479 { { MNEM, ' ', OP (ACCD), 0 } },
1294c286
DE		 2480 { 16, 16, 0xf3ff }, 0x5090,
2481 (PTR) 0,
2482 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2483 },
2484/* rac $accd,$accs */
2485 {
2486 { 1, 1, 1, 1 },
2487 -1, "rac-ds", "rac",
2e6dfccc 2488 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1294c286
DE		 2489 { 16, 16, 0xf3f3 }, 0x5090,
2490 (PTR) 0,
2491 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2492 },
2493/* rach $accd */
2494 {
2495 { 1, 1, 1, 1 },
2496 -1, "rach-d", "rach",
2e6dfccc 2497 { { MNEM, ' ', OP (ACCD), 0 } },
1294c286
DE		 2498 { 16, 16, 0xf3ff }, 0x5080,
2499 (PTR) 0,
2500 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2501 },
2502/* rach $accd,$accs */
2503 {
2504 { 1, 1, 1, 1 },
2505 -1, "rach-ds", "rach",
2e6dfccc 2506 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1294c286
DE		 2507 { 16, 16, 0xf3f3 }, 0x5080,
2508 (PTR) 0,
2509 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2510 },
2511/* st $src1,@($src2) */
2512 {
2513 { 1, 1, 1, 1 },
2514 -1, "st-2", "st",
2e6dfccc 2515 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286
DE		 2516 { 16, 16, 0xf0f0 }, 0x2040,
2517 (PTR) 0,
2518 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2519 },
2520/* st $src1,@($src2,$slo16) */
2521 {
2522 { 1, 1, 1, 1 },
2523 -1, "st-d2", "st",
2e6dfccc 2524 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2525 { 32, 32, 0xf0f00000 }, 0xa0400000,
2526 (PTR) 0,
2527 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2528 },
2529/* stb $src1,@($src2) */
2530 {
2531 { 1, 1, 1, 1 },
2532 -1, "stb-2", "stb",
2e6dfccc 2533 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286
DE		 2534 { 16, 16, 0xf0f0 }, 0x2000,
2535 (PTR) 0,
2536 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2537 },
2538/* stb $src1,@($src2,$slo16) */
2539 {
2540 { 1, 1, 1, 1 },
2541 -1, "stb-d2", "stb",
2e6dfccc 2542 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2543 { 32, 32, 0xf0f00000 }, 0xa0000000,
2544 (PTR) 0,
2545 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2546 },
2547/* sth $src1,@($src2) */
2548 {
2549 { 1, 1, 1, 1 },
2550 -1, "sth-2", "sth",
2e6dfccc 2551 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286
DE		 2552 { 16, 16, 0xf0f0 }, 0x2020,
2553 (PTR) 0,
2554 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2555 },
2556/* sth $src1,@($src2,$slo16) */
2557 {
2558 { 1, 1, 1, 1 },
2559 -1, "sth-d2", "sth",
2e6dfccc 2560 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2561 { 32, 32, 0xf0f00000 }, 0xa0200000,
2562 (PTR) 0,
2563 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2564 },
2565/* push $src1 */
2566 {
2567 { 1, 1, 1, 1 },
2568 -1, "push", "push",
2e6dfccc 2569 { { MNEM, ' ', OP (SRC1), 0 } },
1294c286
DE		 2570 { 16, 16, 0xf0ff }, 0x207f,
2571 (PTR) 0,
2572 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2573 },
2574};
2575
2576#undef A
2577#undef MNEM
2578#undef OP
2579
2580static CGEN_INSN_TABLE macro_insn_table =
2581{
2582 & macro_insn_table_entries[0],
2583 sizeof (CGEN_INSN),
2584 (sizeof (macro_insn_table_entries) /
2585 sizeof (macro_insn_table_entries[0])),
2586 NULL
9c03036a
DE		 2587};
2588
2589/* The hash functions are recorded here to help keep assembler code out of
2e6dfccc 2590 the disassembler and vice versa. */
1294c286
DE		 2591
2592static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
2593static unsigned int asm_hash_insn PARAMS ((const char *));
2594static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
2595static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
2596
2597/* Return non-zero if INSN is to be added to the hash table.
2598 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2599
2600static int
2601asm_hash_insn_p (insn)
2602 const CGEN_INSN * insn;
2603{
2604 return CGEN_ASM_HASH_P (insn);
2605}
2606
2607static int
2608dis_hash_insn_p (insn)
2609 const CGEN_INSN * insn;
2610{
2611 /* If building the hash table and the NO-DIS attribute is present,
2612 ignore. */
2613 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2614 return 0;
2615 return CGEN_DIS_HASH_P (insn);
2616}
2617
2618/* The result is the hash value of the insn.
2619 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
9c03036a 2620
1294c286
DE		 2621static unsigned int
2622asm_hash_insn (mnem)
2623 const char * mnem;
9c03036a 2624{
1294c286 2625 return CGEN_ASM_HASH (mnem);
9c03036a
DE		 2626}
2627
1294c286
DE		 2628static unsigned int
2629dis_hash_insn (buf, value)
5d07b6cf 2630 const char * buf;
9c03036a
DE		 2631 unsigned long value;
2632{
2633 return CGEN_DIS_HASH (buf, value);
2634}
2635
1294c286 2636const CGEN_OPCODE_TABLE m32r_cgen_opcode_table =
5d07b6cf
DE		 2637{
2638 & m32r_cgen_hw_entries[0],
1294c286
DE		 2639 /*& m32r_cgen_operand_table[0], - FIXME:wip */
2640 & insn_table,
2641 & macro_insn_table,
2642 asm_hash_insn_p, asm_hash_insn, CGEN_ASM_HASH_SIZE,
2643 dis_hash_insn_p, dis_hash_insn, CGEN_DIS_HASH_SIZE
9c03036a
DE		 2644};
2645
2646void
2647m32r_cgen_init_tables (mach)
2648 int mach;
2649{
2650}
2651
fbc8134d
DE		 2652/* Getting values from cgen_fields is handled by a collection of functions.
2653 They are distinguished by the type of the VALUE argument they return.
2654 TODO: floating point, inlining support, remove cases where result type
2655 not appropriate. */
9c03036a 2656
fbc8134d
DE		 2657int
2658m32r_cgen_get_int_operand (opindex, fields)
9c03036a 2659 int opindex;
fbc8134d 2660 const CGEN_FIELDS * fields;
9c03036a 2661{
fbc8134d
DE		 2662 int value;
2663
9c03036a
DE		 2664 switch (opindex)
2665 {
23cf992f 2666 case M32R_OPERAND_SR :
fbc8134d 2667 value = fields->f_r2;
9c03036a 2668 break;
23cf992f 2669 case M32R_OPERAND_DR :
fbc8134d 2670 value = fields->f_r1;
9c03036a 2671 break;
23cf992f 2672 case M32R_OPERAND_SRC1 :
fbc8134d 2673 value = fields->f_r1;
9c03036a 2674 break;
23cf992f 2675 case M32R_OPERAND_SRC2 :
fbc8134d 2676 value = fields->f_r2;
9c03036a 2677 break;
23cf992f 2678 case M32R_OPERAND_SCR :
fbc8134d 2679 value = fields->f_r2;
9c03036a 2680 break;
23cf992f 2681 case M32R_OPERAND_DCR :
fbc8134d 2682 value = fields->f_r1;
9c03036a 2683 break;
23cf992f 2684 case M32R_OPERAND_SIMM8 :
fbc8134d 2685 value = fields->f_simm8;
9c03036a 2686 break;
23cf992f 2687 case M32R_OPERAND_SIMM16 :
fbc8134d 2688 value = fields->f_simm16;
9c03036a 2689 break;
23cf992f 2690 case M32R_OPERAND_UIMM4 :
fbc8134d 2691 value = fields->f_uimm4;
9c03036a 2692 break;
23cf992f 2693 case M32R_OPERAND_UIMM5 :
fbc8134d 2694 value = fields->f_uimm5;
9c03036a 2695 break;
23cf992f 2696 case M32R_OPERAND_UIMM16 :
fbc8134d 2697 value = fields->f_uimm16;
23cf992f 2698 break;
ab0bd049
DE		 2699/* start-sanitize-m32rx */
2700 case M32R_OPERAND_IMM1 :
fbc8134d 2701 value = fields->f_imm1;
ab0bd049
DE		 2702 break;
2703/* end-sanitize-m32rx */
2704/* start-sanitize-m32rx */
2705 case M32R_OPERAND_ACCD :
fbc8134d 2706 value = fields->f_accd;
ab0bd049
DE		 2707 break;
2708/* end-sanitize-m32rx */
7c26196f
DE		 2709/* start-sanitize-m32rx */
2710 case M32R_OPERAND_ACCS :
fbc8134d 2711 value = fields->f_accs;
7c26196f
DE		 2712 break;
2713/* end-sanitize-m32rx */
2714/* start-sanitize-m32rx */
2715 case M32R_OPERAND_ACC :
fbc8134d 2716 value = fields->f_acc;
7c26196f
DE		 2717 break;
2718/* end-sanitize-m32rx */
a6cefe4f 2719 case M32R_OPERAND_HASH :
fbc8134d 2720 value = fields->f_nil;
a6cefe4f 2721 break;
23cf992f 2722 case M32R_OPERAND_HI16 :
fbc8134d 2723 value = fields->f_hi16;
9c03036a 2724 break;
23cf992f 2725 case M32R_OPERAND_SLO16 :
fbc8134d 2726 value = fields->f_simm16;
9c03036a 2727 break;
23cf992f 2728 case M32R_OPERAND_ULO16 :
fbc8134d 2729 value = fields->f_uimm16;
9c03036a 2730 break;
23cf992f 2731 case M32R_OPERAND_UIMM24 :
fbc8134d 2732 value = fields->f_uimm24;
9c03036a 2733 break;
23cf992f 2734 case M32R_OPERAND_DISP8 :
fbc8134d 2735 value = fields->f_disp8;
9c03036a 2736 break;
23cf992f 2737 case M32R_OPERAND_DISP16 :
fbc8134d 2738 value = fields->f_disp16;
9c03036a 2739 break;
23cf992f 2740 case M32R_OPERAND_DISP24 :
fbc8134d 2741 value = fields->f_disp24;
9c03036a
DE		 2742 break;
2743
2744 default :
fbc8134d
DE		 2745 /* xgettext:c-format */
2746 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
9c03036a
DE		 2747 opindex);
2748 abort ();
2749 }
9c03036a 2750
fbc8134d
DE		 2751 return value;
2752}
9c03036a 2753
fbc8134d
DE		 2754bfd_vma
2755m32r_cgen_get_vma_operand (opindex, fields)
5d07b6cf 2756 int opindex;
853713a7 2757 const CGEN_FIELDS * fields;
9c03036a 2758{
fbc8134d 2759 bfd_vma value;
9c03036a
DE		 2760
2761 switch (opindex)
2762 {
23cf992f 2763 case M32R_OPERAND_SR :
9c03036a
DE		 2764 value = fields->f_r2;
2765 break;
23cf992f 2766 case M32R_OPERAND_DR :
9c03036a
DE		 2767 value = fields->f_r1;
2768 break;
23cf992f 2769 case M32R_OPERAND_SRC1 :
9c03036a
DE		 2770 value = fields->f_r1;
2771 break;
23cf992f 2772 case M32R_OPERAND_SRC2 :
9c03036a
DE		 2773 value = fields->f_r2;
2774 break;
23cf992f 2775 case M32R_OPERAND_SCR :
9c03036a
DE		 2776 value = fields->f_r2;
2777 break;
23cf992f 2778 case M32R_OPERAND_DCR :
9c03036a
DE		 2779 value = fields->f_r1;
2780 break;
23cf992f 2781 case M32R_OPERAND_SIMM8 :
9c03036a
DE		 2782 value = fields->f_simm8;
2783 break;
23cf992f 2784 case M32R_OPERAND_SIMM16 :
9c03036a
DE		 2785 value = fields->f_simm16;
2786 break;
23cf992f 2787 case M32R_OPERAND_UIMM4 :
9c03036a
DE		 2788 value = fields->f_uimm4;
2789 break;
23cf992f 2790 case M32R_OPERAND_UIMM5 :
9c03036a
DE		 2791 value = fields->f_uimm5;
2792 break;
23cf992f 2793 case M32R_OPERAND_UIMM16 :
9c03036a
DE		 2794 value = fields->f_uimm16;
2795 break;
ab0bd049
DE		 2796/* start-sanitize-m32rx */
2797 case M32R_OPERAND_IMM1 :
2798 value = fields->f_imm1;
2799 break;
2800/* end-sanitize-m32rx */
2801/* start-sanitize-m32rx */
2802 case M32R_OPERAND_ACCD :
2803 value = fields->f_accd;
2804 break;
2805/* end-sanitize-m32rx */
7c26196f
DE		 2806/* start-sanitize-m32rx */
2807 case M32R_OPERAND_ACCS :
2808 value = fields->f_accs;
2809 break;
2810/* end-sanitize-m32rx */
2811/* start-sanitize-m32rx */
2812 case M32R_OPERAND_ACC :
2813 value = fields->f_acc;
2814 break;
2815/* end-sanitize-m32rx */
a6cefe4f
DE		 2816 case M32R_OPERAND_HASH :
2817 value = fields->f_nil;
2818 break;
23cf992f 2819 case M32R_OPERAND_HI16 :
9c03036a
DE		 2820 value = fields->f_hi16;
2821 break;
23cf992f 2822 case M32R_OPERAND_SLO16 :
9c03036a
DE		 2823 value = fields->f_simm16;
2824 break;
23cf992f 2825 case M32R_OPERAND_ULO16 :
9c03036a
DE		 2826 value = fields->f_uimm16;
2827 break;
23cf992f 2828 case M32R_OPERAND_UIMM24 :
9c03036a
DE		 2829 value = fields->f_uimm24;
2830 break;
23cf992f 2831 case M32R_OPERAND_DISP8 :
9c03036a
DE		 2832 value = fields->f_disp8;
2833 break;
23cf992f 2834 case M32R_OPERAND_DISP16 :
9c03036a
DE		 2835 value = fields->f_disp16;
2836 break;
23cf992f 2837 case M32R_OPERAND_DISP24 :
9c03036a
DE		 2838 value = fields->f_disp24;
2839 break;
2840
2841 default :
fbc8134d
DE		 2842 /* xgettext:c-format */
2843 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
9c03036a
DE		 2844 opindex);
2845 abort ();
2846 }
2847
2848 return value;
2849}
2850
fbc8134d
DE		 2851/* Stuffing values in cgen_fields is handled by a collection of functions.
2852 They are distinguished by the type of the VALUE argument they accept.
2853 TODO: floating point, inlining support, remove cases where argument type
2854 not appropriate. */
2855
2856void
2857m32r_cgen_set_int_operand (opindex, fields, value)
2858 int opindex;
2859 CGEN_FIELDS * fields;
2860 int value;
2861{
2862 switch (opindex)
2863 {
2864 case M32R_OPERAND_SR :
2865 fields->f_r2 = value;
2866 break;
2867 case M32R_OPERAND_DR :
2868 fields->f_r1 = value;
2869 break;
2870 case M32R_OPERAND_SRC1 :
2871 fields->f_r1 = value;
2872 break;
2873 case M32R_OPERAND_SRC2 :
2874 fields->f_r2 = value;
2875 break;
2876 case M32R_OPERAND_SCR :
2877 fields->f_r2 = value;
2878 break;
2879 case M32R_OPERAND_DCR :
2880 fields->f_r1 = value;
2881 break;
2882 case M32R_OPERAND_SIMM8 :
2883 fields->f_simm8 = value;
2884 break;
2885 case M32R_OPERAND_SIMM16 :
2886 fields->f_simm16 = value;
2887 break;
2888 case M32R_OPERAND_UIMM4 :
2889 fields->f_uimm4 = value;
2890 break;
2891 case M32R_OPERAND_UIMM5 :
2892 fields->f_uimm5 = value;
2893 break;
2894 case M32R_OPERAND_UIMM16 :
2895 fields->f_uimm16 = value;
2896 break;
2897/* start-sanitize-m32rx */
2898 case M32R_OPERAND_IMM1 :
2899 fields->f_imm1 = value;
2900 break;
2901/* end-sanitize-m32rx */
2902/* start-sanitize-m32rx */
2903 case M32R_OPERAND_ACCD :
2904 fields->f_accd = value;
2905 break;
2906/* end-sanitize-m32rx */
2907/* start-sanitize-m32rx */
2908 case M32R_OPERAND_ACCS :
2909 fields->f_accs = value;
2910 break;
2911/* end-sanitize-m32rx */
2912/* start-sanitize-m32rx */
2913 case M32R_OPERAND_ACC :
2914 fields->f_acc = value;
2915 break;
2916/* end-sanitize-m32rx */
2917 case M32R_OPERAND_HASH :
2918 fields->f_nil = value;
2919 break;
2920 case M32R_OPERAND_HI16 :
2921 fields->f_hi16 = value;
2922 break;
2923 case M32R_OPERAND_SLO16 :
2924 fields->f_simm16 = value;
2925 break;
2926 case M32R_OPERAND_ULO16 :
2927 fields->f_uimm16 = value;
2928 break;
2929 case M32R_OPERAND_UIMM24 :
2930 fields->f_uimm24 = value;
2931 break;
2932 case M32R_OPERAND_DISP8 :
2933 fields->f_disp8 = value;
2934 break;
2935 case M32R_OPERAND_DISP16 :
2936 fields->f_disp16 = value;
2937 break;
2938 case M32R_OPERAND_DISP24 :
2939 fields->f_disp24 = value;
2940 break;
2941
2942 default :
2943 /* xgettext:c-format */
2944 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2945 opindex);
2946 abort ();
2947 }
2948}
2949
2950void
2951m32r_cgen_set_vma_operand (opindex, fields, value)
2952 int opindex;
2953 CGEN_FIELDS * fields;
2954 bfd_vma value;
2955{
2956 switch (opindex)
2957 {
2958 case M32R_OPERAND_SR :
2959 fields->f_r2 = value;
2960 break;
2961 case M32R_OPERAND_DR :
2962 fields->f_r1 = value;
2963 break;
2964 case M32R_OPERAND_SRC1 :
2965 fields->f_r1 = value;
2966 break;
2967 case M32R_OPERAND_SRC2 :
2968 fields->f_r2 = value;
2969 break;
2970 case M32R_OPERAND_SCR :
2971 fields->f_r2 = value;
2972 break;
2973 case M32R_OPERAND_DCR :
2974 fields->f_r1 = value;
2975 break;
2976 case M32R_OPERAND_SIMM8 :
2977 fields->f_simm8 = value;
2978 break;
2979 case M32R_OPERAND_SIMM16 :
2980 fields->f_simm16 = value;
2981 break;
2982 case M32R_OPERAND_UIMM4 :
2983 fields->f_uimm4 = value;
2984 break;
2985 case M32R_OPERAND_UIMM5 :
2986 fields->f_uimm5 = value;
2987 break;
2988 case M32R_OPERAND_UIMM16 :
2989 fields->f_uimm16 = value;
2990 break;
2991/* start-sanitize-m32rx */
2992 case M32R_OPERAND_IMM1 :
2993 fields->f_imm1 = value;
2994 break;
2995/* end-sanitize-m32rx */
2996/* start-sanitize-m32rx */
2997 case M32R_OPERAND_ACCD :
2998 fields->f_accd = value;
2999 break;
3000/* end-sanitize-m32rx */
3001/* start-sanitize-m32rx */
3002 case M32R_OPERAND_ACCS :
3003 fields->f_accs = value;
3004 break;
3005/* end-sanitize-m32rx */
3006/* start-sanitize-m32rx */
3007 case M32R_OPERAND_ACC :
3008 fields->f_acc = value;
3009 break;
3010/* end-sanitize-m32rx */
3011 case M32R_OPERAND_HASH :
3012 fields->f_nil = value;
3013 break;
3014 case M32R_OPERAND_HI16 :
3015 fields->f_hi16 = value;
3016 break;
3017 case M32R_OPERAND_SLO16 :
3018 fields->f_simm16 = value;
3019 break;
3020 case M32R_OPERAND_ULO16 :
3021 fields->f_uimm16 = value;
3022 break;
3023 case M32R_OPERAND_UIMM24 :
3024 fields->f_uimm24 = value;
3025 break;
3026 case M32R_OPERAND_DISP8 :
3027 fields->f_disp8 = value;
3028 break;
3029 case M32R_OPERAND_DISP16 :
3030 fields->f_disp16 = value;
3031 break;
3032 case M32R_OPERAND_DISP24 :
3033 fields->f_disp24 = value;
3034 break;
3035
3036 default :
3037 /* xgettext:c-format */
3038 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3039 opindex);
3040 abort ();
3041 }
3042}
3043
GDB Binutils - Deliverables
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