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Move all global state data into opcode table struct, and treat
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
CommitLineData
ab0bd049
DE		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
9c03036a 3
fbc8134d 4THIS FILE IS USED TO GENERATE m32r-opc.c.
7c26196f 5
ab0bd049 6Copyright (C) 1998 Free Software Foundation, Inc.
9c03036a 7
ab0bd049 8This file is part of the GNU Binutils and GDB, the GNU debugger.
9c03036a
DE		 9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
ab0bd049 20You should have received a copy of the GNU General Public License
fbc8134d
DE		 21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
9c03036a 23
23cf992f 24#include "sysdep.h"
9c03036a
DE		 25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
ab0bd049 29#include "symcat.h"
9c03036a 30#include "m32r-opc.h"
fbc8134d 31#include "opintl.h"
9c03036a 32
c2009f4a
DE		 33/* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
35
36static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37static unsigned int asm_hash_insn PARAMS ((const char *));
38static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
39static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
40
ab0bd049 41/* Look up instruction INSN_VALUE and extract its fields.
1294c286 42 INSN, if non-null, is the insn table entry.
ab0bd049
DE		 43 Otherwise INSN_VALUE is examined to compute it.
44 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
1294c286
DE		 45 0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
46 If INSN != NULL, LENGTH must be valid.
390bd87d 47 ALIAS_P is non-zero if alias insns are to be included in the search.
1294c286 48
ab0bd049
DE		 49 The result a pointer to the insn table entry, or NULL if the instruction
50 wasn't recognized. */
51
52const CGEN_INSN *
c2009f4a
DE		 53m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
54 CGEN_OPCODE_DESC od;
ab0bd049
DE		 55 const CGEN_INSN *insn;
56 cgen_insn_t insn_value;
57 int length;
58 CGEN_FIELDS *fields;
1294c286 59 int alias_p;
ab0bd049 60{
390bd87d 61 char buf[16];
ab0bd049
DE		 62
63 if (!insn)
64 {
65 const CGEN_INSN_LIST *insn_list;
66
67#ifdef CGEN_INT_INSN
68 switch (length)
69 {
70 case 8:
71 buf[0] = insn_value;
72 break;
73 case 16:
c2009f4a 74 if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
ab0bd049
DE		 75 bfd_putb16 (insn_value, buf);
76 else
77 bfd_putl16 (insn_value, buf);
78 break;
79 case 32:
c2009f4a 80 if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
ab0bd049
DE		 81 bfd_putb32 (insn_value, buf);
82 else
83 bfd_putl32 (insn_value, buf);
84 break;
85 default:
86 abort ();
87 }
88#else
89 abort (); /* FIXME: unfinished */
90#endif
91
92 /* The instructions are stored in hash lists.
93 Pick the first one and keep trying until we find the right one. */
94
c2009f4a 95 insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
ab0bd049
DE		 96 while (insn_list != NULL)
97 {
98 insn = insn_list->insn;
99
390bd87d
DE		 100 if (alias_p
101 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
ab0bd049 102 {
390bd87d
DE		 103 /* Basic bit mask must be correct. */
104 /* ??? May wish to allow target to defer this check until the
105 extract handler. */
106 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
107 {
fbc8134d 108 /* ??? 0 is passed for `pc' */
c2009f4a 109 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL,
fbc8134d
DE		 110 insn_value, fields,
111 (bfd_vma) 0);
1294c286
DE		 112 if (elength > 0)
113 {
114 /* sanity check */
115 if (length != 0 && length != elength)
116 abort ();
117 return insn;
118 }
390bd87d 119 }
ab0bd049
DE		 120 }
121
122 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
123 }
124 }
125 else
126 {
390bd87d
DE		 127 /* Sanity check: can't pass an alias insn if ! alias_p. */
128 if (! alias_p
129 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
130 abort ();
1294c286
DE		 131 /* Sanity check: length must be correct. */
132 if (length != CGEN_INSN_BITSIZE (insn))
133 abort ();
390bd87d 134
fbc8134d 135 /* ??? 0 is passed for `pc' */
c2009f4a 136 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL, insn_value, fields,
fbc8134d 137 (bfd_vma) 0);
1294c286
DE		 138 /* Sanity check: must succeed.
139 Could relax this later if it ever proves useful. */
140 if (length == 0)
141 abort ();
142 return insn;
ab0bd049
DE		 143 }
144
145 return NULL;
146}
147
1294c286 148/* Fill in the operand instances used by INSN whose operands are FIELDS.
b02643b5 149 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
1294c286 150 in. */
ab0bd049 151
1294c286 152void
c2009f4a
DE		 153m32r_cgen_get_insn_operands (od, insn, fields, indices)
154 CGEN_OPCODE_DESC od;
1294c286
DE		 155 const CGEN_INSN * insn;
156 const CGEN_FIELDS * fields;
ab0bd049
DE		 157 int *indices;
158{
ab0bd049
DE		 159 const CGEN_OPERAND_INSTANCE *opinst;
160 int i;
161
ab0bd049 162 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
b2f18612
DE		 163 opinst != NULL
164 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
ab0bd049
DE		 165 ++i, ++opinst)
166 {
167 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
168 if (op == NULL)
169 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
170 else
0cc2fbf3
DE		 171 indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
172 fields);
ab0bd049 173 }
1294c286 174}
ab0bd049 175
1294c286
DE		 176/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
177 isn't known.
178 The INSN, INSN_VALUE, and LENGTH arguments are passed to
179 m32r_cgen_lookup_insn unchanged.
180
181 The result is the insn table entry or NULL if the instruction wasn't
182 recognized. */
183
184const CGEN_INSN *
c2009f4a
DE		 185m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
186 CGEN_OPCODE_DESC od;
1294c286
DE		 187 const CGEN_INSN *insn;
188 cgen_insn_t insn_value;
189 int length;
190 int *indices;
191{
192 CGEN_FIELDS fields;
193
194 /* Pass non-zero for ALIAS_P only if INSN != NULL.
195 If INSN == NULL, we want a real insn. */
c2009f4a 196 insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
1294c286
DE		 197 insn != NULL);
198 if (! insn)
199 return NULL;
200
c2009f4a 201 m32r_cgen_get_insn_operands (od, insn, &fields, indices);
ab0bd049
DE		 202 return insn;
203}
23cf992f
NC		 204/* Attributes. */
205
7c26196f 206static const CGEN_ATTR_ENTRY MACH_attr[] =
5d07b6cf
DE		 207{
208 { "m32r", MACH_M32R },
7c26196f
DE		 209/* start-sanitize-m32rx */
210 { "m32rx", MACH_M32RX },
211/* end-sanitize-m32rx */
212 { "max", MACH_MAX },
213 { 0, 0 }
214};
215
216/* start-sanitize-m32rx */
217static const CGEN_ATTR_ENTRY PIPE_attr[] =
218{
219 { "NONE", PIPE_NONE },
220 { "O", PIPE_O },
221 { "S", PIPE_S },
222 { "OS", PIPE_OS },
23cf992f
NC		 223 { 0, 0 }
224};
225
7c26196f
DE		 226/* end-sanitize-m32rx */
227const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
5d07b6cf
DE		 228{
229 { "ABS-ADDR", NULL },
23cf992f 230 { "FAKE", NULL },
a6cefe4f 231 { "HASH-PREFIX", NULL },
23cf992f 232 { "NEGATIVE", NULL },
23cf992f
NC		 233 { "PCREL-ADDR", NULL },
234 { "RELAX", NULL },
235 { "RELOC", NULL },
236 { "SIGN-OPT", NULL },
237 { "UNSIGNED", NULL },
238 { 0, 0 }
239};
240
7c26196f 241const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
5d07b6cf 242{
7c26196f
DE		 243 { "MACH", & MACH_attr[0] },
244/* start-sanitize-m32rx */
245 { "PIPE", & PIPE_attr[0] },
246/* end-sanitize-m32rx */
5d07b6cf 247 { "ALIAS", NULL },
23cf992f
NC		 248 { "COND-CTI", NULL },
249 { "FILL-SLOT", NULL },
1294c286 250 { "NO-DIS", NULL },
7c26196f 251 { "PARALLEL", NULL },
23cf992f 252 { "RELAX", NULL },
23cf992f 253 { "RELAXABLE", NULL },
fbc8134d 254 { "SPECIAL", NULL },
23cf992f
NC		 255 { "UNCOND-CTI", NULL },
256 { 0, 0 }
9c03036a
DE		 257};
258
853713a7 259CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
5d07b6cf
DE		 260{
261 { "fp", 13 },
9c03036a
DE		 262 { "lr", 14 },
263 { "sp", 15 },
264 { "r0", 0 },
265 { "r1", 1 },
266 { "r2", 2 },
267 { "r3", 3 },
268 { "r4", 4 },
269 { "r5", 5 },
270 { "r6", 6 },
271 { "r7", 7 },
272 { "r8", 8 },
273 { "r9", 9 },
274 { "r10", 10 },
275 { "r11", 11 },
276 { "r12", 12 },
277 { "r13", 13 },
278 { "r14", 14 },
279 { "r15", 15 }
280};
281
853713a7 282CGEN_KEYWORD m32r_cgen_opval_h_gr =
5d07b6cf
DE		 283{
284 & m32r_cgen_opval_h_gr_entries[0],
9c03036a
DE		 285 19
286};
287
853713a7 288CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
5d07b6cf
DE		 289{
290 { "psw", 0 },
9c03036a
DE		 291 { "cbr", 1 },
292 { "spi", 2 },
293 { "spu", 3 },
294 { "bpc", 6 },
295 { "cr0", 0 },
296 { "cr1", 1 },
297 { "cr2", 2 },
298 { "cr3", 3 },
299 { "cr4", 4 },
300 { "cr5", 5 },
b2ddf0c4
NC		 301 { "cr6", 6 },
302 { "cr7", 7 },
303 { "cr8", 8 },
304 { "cr9", 9 },
305 { "cr10", 10 },
306 { "cr11", 11 },
307 { "cr12", 12 },
308 { "cr13", 13 },
309 { "cr14", 14 },
310 { "cr15", 15 }
9c03036a
DE		 311};
312
853713a7 313CGEN_KEYWORD m32r_cgen_opval_h_cr =
5d07b6cf
DE		 314{
315 & m32r_cgen_opval_h_cr_entries[0],
b2ddf0c4 316 21
9c03036a
DE		 317};
318
7c26196f
DE		 319/* start-sanitize-m32rx */
320CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
321{
322 { "a0", 0 },
323 { "a1", 1 }
324};
23cf992f 325
7c26196f 326CGEN_KEYWORD m32r_cgen_opval_h_accums =
5d07b6cf 327{
7c26196f
DE		 328 & m32r_cgen_opval_h_accums_entries[0],
329 2
9c03036a
DE		 330};
331
7c26196f
DE		 332/* end-sanitize-m32rx */
333
ab0bd049
DE		 334/* The hardware table. */
335
336#define HW_ENT(n) m32r_cgen_hw_entries[n]
337static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
7c26196f 338{
ab0bd049
DE		 339 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
340 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
341 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
342 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
343 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
344 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
345 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
346 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
347 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
348 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
349 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
350 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
7c26196f 351/* start-sanitize-m32rx */
ab0bd049 352 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
7c26196f 353/* end-sanitize-m32rx */
ab0bd049
DE		 354 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
355 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
356 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
357 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
358 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
359 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
360 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
8d157f96 361 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
7c26196f
DE		 362 { 0 }
363};
9c03036a 364
ab0bd049
DE		 365/* The operand table. */
366
8d157f96
DE		 367#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
368#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
0bf55db8 369
7c26196f 370const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
9c03036a 371{
23cf992f 372/* pc: program counter */
ab0bd049 373 { "pc", & HW_ENT (HW_H_PC), 0, 0,
fbc8134d 374 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
9c03036a 375/* sr: source register */
ab0bd049
DE		 376 { "sr", & HW_ENT (HW_H_GR), 12, 4,
377 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 378/* dr: destination register */
ab0bd049
DE		 379 { "dr", & HW_ENT (HW_H_GR), 4, 4,
380 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 381/* src1: source register 1 */
ab0bd049
DE		 382 { "src1", & HW_ENT (HW_H_GR), 4, 4,
383 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 384/* src2: source register 2 */
ab0bd049
DE		 385 { "src2", & HW_ENT (HW_H_GR), 12, 4,
386 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 387/* scr: source control register */
ab0bd049
DE		 388 { "scr", & HW_ENT (HW_H_CR), 12, 4,
389 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 390/* dcr: destination control register */
ab0bd049
DE		 391 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
392 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 393/* simm8: 8 bit signed immediate */
ab0bd049 394 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
a6cefe4f 395 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 396/* simm16: 16 bit signed immediate */
ab0bd049 397 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
a6cefe4f 398 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 399/* uimm4: 4 bit trap number */
ab0bd049 400 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
a6cefe4f 401 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 402/* uimm5: 5 bit shift count */
ab0bd049 403 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
a6cefe4f 404 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 405/* uimm16: 16 bit unsigned immediate */
ab0bd049 406 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
a6cefe4f 407 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 408/* start-sanitize-m32rx */
409/* imm1: 1 bit immediate */
410 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
a6cefe4f 411 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 412/* end-sanitize-m32rx */
413/* start-sanitize-m32rx */
414/* accd: accumulator destination register */
415 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
416 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
417/* end-sanitize-m32rx */
7c26196f 418/* start-sanitize-m32rx */
ab0bd049
DE		 419/* accs: accumulator source register */
420 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
421 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f
DE		 422/* end-sanitize-m32rx */
423/* start-sanitize-m32rx */
424/* acc: accumulator reg (d) */
ab0bd049
DE		 425 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
426 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f 427/* end-sanitize-m32rx */
a6cefe4f
DE		 428/* hash: # prefix */
429 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
430 { 0, 0, { 0 } } },
9c03036a 431/* hi16: high 16 bit immediate, sign optional */
ab0bd049
DE		 432 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
433 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 434/* slo16: 16 bit signed immediate, for low() */
ab0bd049
DE		 435 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
436 { 0, 0, { 0 } } },
9c03036a 437/* ulo16: 16 bit unsigned immediate, for low() */
ab0bd049
DE		 438 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
439 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 440/* uimm24: 24 bit address */
ab0bd049 441 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
a6cefe4f 442 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 443/* disp8: 8 bit displacement */
ab0bd049
DE		 444 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
445 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 446/* disp16: 16 bit displacement */
ab0bd049
DE		 447 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
448 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 449/* disp24: 24 bit displacement */
ab0bd049
DE		 450 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
451 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
23cf992f 452/* condbit: condition bit */
ab0bd049
DE		 453 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
454 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f 455/* accum: accumulator */
ab0bd049
DE		 456 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
457 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f
NC		 458};
459
ab0bd049
DE		 460/* Operand references. */
461
7caa7497
DE		 462#define INPUT CGEN_OPERAND_INSTANCE_INPUT
463#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
464
1294c286 465static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
7caa7497
DE		 466 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
467 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
468 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 469 { 0 }
470};
471
1294c286 472static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
7caa7497 473 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 474 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 475 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 476 { 0 }
477};
478
1294c286 479static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
7caa7497
DE		 480 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
481 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
482 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 483 { 0 }
484};
485
1294c286 486static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
7caa7497
DE		 487 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
488 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
489 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 490 { 0 }
491};
492
1294c286 493static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
7caa7497
DE		 494 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
495 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
496 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 497 { 0 }
498};
499
1294c286 500static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
390bd87d
DE		 501 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
502 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
390bd87d 503 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 504 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 505 { 0 }
506};
507
1294c286 508static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
7caa7497 509 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 510 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
7caa7497 511 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 512 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 513 { 0 }
514};
515
1294c286 516static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
7caa7497
DE		 517 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
518 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 519 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
7caa7497 520 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 521 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 522 { 0 }
523};
524
1294c286 525static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
390bd87d 526 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
fbc8134d 527 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
8d157f96 528 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 529 { 0 }
530};
531
1294c286 532static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
390bd87d 533 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
fbc8134d 534 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
8d157f96 535 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 536 { 0 }
537};
538
1294c286 539static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
7caa7497
DE		 540 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
541 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 542 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
8d157f96 543 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 544 { 0 }
545};
546
1294c286 547static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
7caa7497 548 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 549 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
8d157f96 550 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 551 { 0 }
552};
553
1294c286 554static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
390bd87d 555 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 556 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
7caa7497 557 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 558 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 559 { 0 }
560};
561
1294c286 562static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
390bd87d 563 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 564 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
7caa7497 565 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 566 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 567 { 0 }
568};
569
b2ddf0c4 570/* start-sanitize-m32rx */
1294c286 571static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
390bd87d 572 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d 573 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 574 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
7caa7497 575 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 576 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 577 { 0 }
578};
579
b2ddf0c4
NC		 580/* end-sanitize-m32rx */
581/* start-sanitize-m32rx */
1294c286 582static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
390bd87d 583 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d 584 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 585 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
7caa7497 586 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 587 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 588 { 0 }
589};
590
b2ddf0c4 591/* end-sanitize-m32rx */
1294c286 592static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
fbc8134d 593 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
8d157f96 594 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 595 { 0 }
596};
597
1294c286 598static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
fbc8134d 599 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
8d157f96 600 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 601 { 0 }
602};
603
1294c286 604static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
7caa7497
DE		 605 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
606 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 607 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 608 { 0 }
609};
610
1294c286 611static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
7caa7497 612 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 613 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
390bd87d 614 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 615 { 0 }
616};
617
b2ddf0c4 618/* start-sanitize-m32rx */
1294c286 619static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
7caa7497 620 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 621 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 622 { 0 }
623};
624
b2ddf0c4 625/* end-sanitize-m32rx */
1294c286 626static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
7caa7497
DE		 627 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
628 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
629 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 630 { 0 }
631};
632
b2ddf0c4 633/* start-sanitize-m32rx */
1294c286 634static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
390bd87d 635 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
7caa7497 636 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
8d157f96 637 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 638 { 0 }
639};
640
b2ddf0c4 641/* end-sanitize-m32rx */
1294c286 642static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
390bd87d 643 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
7caa7497
DE		 644 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
645 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 646 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 647 { 0 }
648};
649
1294c286 650static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
7caa7497 651 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
8d157f96 652 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 653 { 0 }
654};
655
1294c286 656static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
7caa7497 657 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
fbc8134d 658 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 659 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 660 { 0 }
661};
662
1294c286 663static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
7caa7497 664 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
7caa7497 665 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 666 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 667 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 668 { 0 }
669};
670
1294c286 671static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
7caa7497 672 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
fbc8134d 673 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 674 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 675 { 0 }
676};
677
1294c286 678static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
7caa7497 679 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
7caa7497 680 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 681 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 682 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 683 { 0 }
684};
685
1294c286 686static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
7caa7497 687 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
fbc8134d 688 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 689 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 690 { 0 }
691};
692
1294c286 693static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
7caa7497 694 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
7caa7497 695 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 696 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 697 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 698 { 0 }
699};
700
1294c286 701static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
390bd87d
DE		 702 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
703 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
704 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
705 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
706 { 0 }
707};
708
1294c286 709static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
fbc8134d 710 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
7caa7497 711 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 712 { 0 }
713};
714
1294c286 715static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
7caa7497
DE		 716 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
717 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 718 { 0 }
719};
720
1294c286 721static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
7caa7497
DE		 722 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
723 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 724 { 0 }
725};
726
1294c286 727static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
8d157f96 728 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
fbc8134d 729 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
8d157f96 730 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
fbc8134d 731 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
390bd87d
DE		 732 { 0 }
733};
734
1294c286 735static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
390bd87d 736 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497
DE		 737 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
738 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 739 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 740 { 0 }
741};
742
b2ddf0c4 743/* start-sanitize-m32rx */
1294c286 744static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
7caa7497
DE		 745 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
746 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
747 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
748 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 749 { 0 }
750};
751
b2ddf0c4 752/* end-sanitize-m32rx */
1294c286 753static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
390bd87d
DE		 754 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
755 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
756 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
757 { 0 }
758};
759
b2ddf0c4 760/* start-sanitize-m32rx */
1294c286 761static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
7caa7497
DE		 762 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
763 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
764 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 765 { 0 }
766};
767
b2ddf0c4 768/* end-sanitize-m32rx */
1294c286 769static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
7caa7497
DE		 770 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
771 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 772 { 0 }
773};
774
1294c286 775static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
390bd87d 776 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497 777 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 778 { 0 }
779};
780
b2ddf0c4 781/* start-sanitize-m32rx */
1294c286 782static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
7caa7497
DE		 783 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
784 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 785 { 0 }
786};
787
b2ddf0c4 788/* end-sanitize-m32rx */
1294c286 789static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
b02643b5 790 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
7caa7497 791 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 792 { 0 }
793};
794
1294c286 795static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
390bd87d 796 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497 797 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d 798 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 799 { 0 }
800};
801
b2ddf0c4 802/* start-sanitize-m32rx */
1294c286 803static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
7caa7497
DE		 804 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
805 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
806 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
ab0bd049
DE		 807 { 0 }
808};
809
b2ddf0c4 810/* end-sanitize-m32rx */
1294c286 811static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
7caa7497 812 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
b02643b5 813 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
ab0bd049
DE		 814 { 0 }
815};
816
1294c286 817static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
390bd87d
DE		 818 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
819 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 820 { 0 }
821};
822
b2ddf0c4 823/* start-sanitize-m32rx */
1294c286 824static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
7caa7497
DE		 825 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
826 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
827 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
ab0bd049
DE		 828 { 0 }
829};
830
b2ddf0c4 831/* end-sanitize-m32rx */
1294c286 832static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
fbc8134d
DE		 833 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
834 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
835 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
836 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
837 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
838 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 839 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
840 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 841 { 0 }
842};
843
1294c286 844static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
fbc8134d 845 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
7caa7497 846 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 847 { 0 }
848};
849
1294c286 850static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
390bd87d 851 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 852 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
390bd87d
DE		 853 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
854 { 0 }
855};
856
1294c286 857static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
7caa7497
DE		 858 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
859 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
860 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 861 { 0 }
862};
863
1294c286 864static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
fbc8134d 865 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
390bd87d 866 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 867 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
868 { 0 }
869};
870
1294c286 871static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
fbc8134d 872 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
7caa7497
DE		 873 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
874 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
7caa7497 875 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 876 { 0 }
877};
878
1294c286 879static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
fbc8134d
DE		 880 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
881 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 882 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
883 { 0 }
884};
885
1294c286 886static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
390bd87d 887 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d
DE		 888 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
889 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 890 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
891 { 0 }
892};
893
1294c286 894static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
fbc8134d
DE		 895 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
896 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 897 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
898 { 0 }
899};
900
1294c286 901static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
390bd87d 902 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d
DE		 903 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
904 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 905 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
906 { 0 }
907};
908
1294c286 909static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
390bd87d 910 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 911 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 912 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
913 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
914 { 0 }
915};
916
1294c286 917static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
8d157f96 918 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d
DE		 919 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
920 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
921 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
922 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
923 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 924 { 0 }
925};
926
1294c286 927static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
8d157f96 928 { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
fbc8134d 929 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
390bd87d 930 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
8d157f96
DE		 931 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
932 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 933 { 0 }
934};
935
b2ddf0c4 936/* start-sanitize-m32rx */
1294c286 937static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
b02643b5 938 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
7caa7497 939 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 940 { 0 }
941};
942
b2ddf0c4
NC		 943/* end-sanitize-m32rx */
944/* start-sanitize-m32rx */
1294c286 945static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
390bd87d 946 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
b02643b5 947 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
7caa7497 948 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 949 { 0 }
950};
951
b2ddf0c4
NC		 952/* end-sanitize-m32rx */
953/* start-sanitize-m32rx */
1294c286 954static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
7caa7497 955 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
fbc8134d 956 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
7caa7497 957 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 958 { 0 }
959};
960
b2ddf0c4
NC		 961/* end-sanitize-m32rx */
962/* start-sanitize-m32rx */
1294c286 963static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
7caa7497
DE		 964 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
965 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
966 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
967 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
ab0bd049
DE		 968 { 0 }
969};
970
b2ddf0c4
NC		 971/* end-sanitize-m32rx */
972/* start-sanitize-m32rx */
1294c286 973static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
390bd87d
DE		 974 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
975 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
976 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
977 { 0 }
978};
979
b2ddf0c4
NC		 980/* end-sanitize-m32rx */
981/* start-sanitize-m32rx */
1294c286 982static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
390bd87d 983 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 984 { 0 }
985};
986
b2ddf0c4 987/* end-sanitize-m32rx */
7caa7497
DE		 988#undef INPUT
989#undef OUTPUT
990
0bf55db8 991#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
8d157f96
DE		 992#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
993#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
23cf992f 994
1294c286
DE		 995/* The instruction table.
996 This is currently non-static because the simulator accesses it
997 directly. */
ab0bd049 998
7c26196f 999const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
5d07b6cf 1000{
1294c286
DE		 1001 /* Special null first entry.
1002 A `num' value of zero is thus illegal.
1003 Also, the special `illegal' insn resides here. */
23cf992f 1004 { { 0 }, 0 },
9c03036a
DE		 1005/* add $dr,$sr */
1006 {
23cf992f 1007 { 1, 1, 1, 1 },
1294c286 1008 M32R_INSN_ADD, "add", "add",
2e6dfccc 1009 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1010 { 16, 16, 0xf0f0 }, 0xa0,
c2009f4a 1011 "(set dr (add dr sr))",
1294c286 1012 (PTR) & fmt_add_ops[0],
8d157f96 1013 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1014 },
a6cefe4f 1015/* add3 $dr,$sr,$hash$slo16 */
9c03036a 1016 {
23cf992f 1017 { 1, 1, 1, 1 },
1294c286 1018 M32R_INSN_ADD3, "add3", "add3",
2e6dfccc 1019 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
0bf55db8 1020 { 32, 32, 0xf0f00000 }, 0x80a00000,
c2009f4a 1021 "(set dr (add sr slo16))",
1294c286 1022 (PTR) & fmt_add3_ops[0],
8d157f96 1023 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
7c26196f 1024 },
9c03036a
DE		 1025/* and $dr,$sr */
1026 {
23cf992f 1027 { 1, 1, 1, 1 },
1294c286 1028 M32R_INSN_AND, "and", "and",
2e6dfccc 1029 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1030 { 16, 16, 0xf0f0 }, 0xc0,
c2009f4a 1031 "(set dr (and dr sr))",
1294c286 1032 (PTR) & fmt_add_ops[0],
8d157f96 1033 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1034 },
9c03036a
DE		 1035/* and3 $dr,$sr,$uimm16 */
1036 {
23cf992f 1037 { 1, 1, 1, 1 },
1294c286 1038 M32R_INSN_AND3, "and3", "and3",
2e6dfccc 1039 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
0bf55db8 1040 { 32, 32, 0xf0f00000 }, 0x80c00000,
c2009f4a 1041 "(set dr (and sr uimm16))",
1294c286 1042 (PTR) & fmt_and3_ops[0],
a6cefe4f 1043 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1044 },
1045/* or $dr,$sr */
1046 {
23cf992f 1047 { 1, 1, 1, 1 },
1294c286 1048 M32R_INSN_OR, "or", "or",
2e6dfccc 1049 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1050 { 16, 16, 0xf0f0 }, 0xe0,
c2009f4a 1051 "(set dr (or dr sr))",
1294c286 1052 (PTR) & fmt_add_ops[0],
8d157f96 1053 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1054 },
a6cefe4f 1055/* or3 $dr,$sr,$hash$ulo16 */
7c26196f
DE		 1056 {
1057 { 1, 1, 1, 1 },
1294c286 1058 M32R_INSN_OR3, "or3", "or3",
2e6dfccc 1059 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
0bf55db8 1060 { 32, 32, 0xf0f00000 }, 0x80e00000,
c2009f4a 1061 "(set dr (or sr ulo16))",
1294c286 1062 (PTR) & fmt_or3_ops[0],
8d157f96 1063 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1064 },
9c03036a
DE		 1065/* xor $dr,$sr */
1066 {
23cf992f 1067 { 1, 1, 1, 1 },
1294c286 1068 M32R_INSN_XOR, "xor", "xor",
2e6dfccc 1069 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1070 { 16, 16, 0xf0f0 }, 0xd0,
c2009f4a 1071 "(set dr (xor dr sr))",
1294c286 1072 (PTR) & fmt_add_ops[0],
8d157f96 1073 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1074 },
9c03036a
DE		 1075/* xor3 $dr,$sr,$uimm16 */
1076 {
23cf992f 1077 { 1, 1, 1, 1 },
1294c286 1078 M32R_INSN_XOR3, "xor3", "xor3",
2e6dfccc 1079 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
0bf55db8 1080 { 32, 32, 0xf0f00000 }, 0x80d00000,
c2009f4a 1081 "(set dr (xor sr uimm16))",
1294c286 1082 (PTR) & fmt_and3_ops[0],
a6cefe4f 1083 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1084 },
1085/* addi $dr,$simm8 */
1086 {
23cf992f 1087 { 1, 1, 1, 1 },
1294c286 1088 M32R_INSN_ADDI, "addi", "addi",
2e6dfccc 1089 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
0bf55db8 1090 { 16, 16, 0xf000 }, 0x4000,
c2009f4a 1091 "(set dr (add dr simm8))",
1294c286 1092 (PTR) & fmt_addi_ops[0],
a6cefe4f 1093 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1094 },
1095/* addv $dr,$sr */
1096 {
23cf992f 1097 { 1, 1, 1, 1 },
1294c286 1098 M32R_INSN_ADDV, "addv", "addv",
2e6dfccc 1099 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1100 { 16, 16, 0xf0f0 }, 0x80,
c2009f4a 1101 "(parallel () (set dr (add dr sr)) (set condbit (add-oflag dr sr (const 0))))",
1294c286 1102 (PTR) & fmt_addv_ops[0],
8d157f96 1103 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1104 },
9c03036a
DE		 1105/* addv3 $dr,$sr,$simm16 */
1106 {
23cf992f 1107 { 1, 1, 1, 1 },
1294c286 1108 M32R_INSN_ADDV3, "addv3", "addv3",
2e6dfccc 1109 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 1110 { 32, 32, 0xf0f00000 }, 0x80800000,
c2009f4a 1111 "(parallel () (set dr (add sr simm16)) (set condbit (add-oflag sr simm16 (const 0))))",
1294c286 1112 (PTR) & fmt_addv3_ops[0],
a6cefe4f 1113 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1114 },
1115/* addx $dr,$sr */
1116 {
23cf992f 1117 { 1, 1, 1, 1 },
1294c286 1118 M32R_INSN_ADDX, "addx", "addx",
2e6dfccc 1119 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1120 { 16, 16, 0xf0f0 }, 0x90,
c2009f4a 1121 "(parallel () (set dr (addc dr sr condbit)) (set condbit (add-cflag dr sr condbit)))",
1294c286 1122 (PTR) & fmt_addx_ops[0],
8d157f96 1123 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1124 },
9c03036a
DE		 1125/* bc.s $disp8 */
1126 {
23cf992f 1127 { 1, 1, 1, 1 },
1294c286 1128 M32R_INSN_BC8, "bc8", "bc.s",
2e6dfccc 1129 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1130 { 16, 16, 0xff00 }, 0x7c00,
c2009f4a 1131 "(if condbit (set pc disp8))",
1294c286
DE		 1132 (PTR) & fmt_bc8_ops[0],
1133 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1134 },
1135/* bc.l $disp24 */
1136 {
23cf992f 1137 { 1, 1, 1, 1 },
1294c286 1138 M32R_INSN_BC24, "bc24", "bc.l",
2e6dfccc 1139 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1140 { 32, 32, 0xff000000 }, 0xfc000000,
c2009f4a 1141 "(if condbit (set pc disp24))",
1294c286
DE		 1142 (PTR) & fmt_bc24_ops[0],
1143 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1144 },
1145/* beq $src1,$src2,$disp16 */
1146 {
23cf992f 1147 { 1, 1, 1, 1 },
1294c286 1148 M32R_INSN_BEQ, "beq", "beq",
2e6dfccc 1149 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1150 { 32, 32, 0xf0f00000 }, 0xb0000000,
c2009f4a 1151 "(if (eq src1 src2) (set pc disp16))",
1294c286 1152 (PTR) & fmt_beq_ops[0],
8d157f96 1153 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1154 },
1155/* beqz $src2,$disp16 */
1156 {
23cf992f 1157 { 1, 1, 1, 1 },
1294c286 1158 M32R_INSN_BEQZ, "beqz", "beqz",
2e6dfccc 1159 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1160 { 32, 32, 0xfff00000 }, 0xb0800000,
c2009f4a 1161 "(if (eq src2 (const: WI 0)) (set pc disp16))",
1294c286 1162 (PTR) & fmt_beqz_ops[0],
8d157f96 1163 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1164 },
1165/* bgez $src2,$disp16 */
1166 {
23cf992f 1167 { 1, 1, 1, 1 },
1294c286 1168 M32R_INSN_BGEZ, "bgez", "bgez",
2e6dfccc 1169 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1170 { 32, 32, 0xfff00000 }, 0xb0b00000,
c2009f4a 1171 "(if (ge src2 (const: WI 0)) (set pc disp16))",
1294c286 1172 (PTR) & fmt_beqz_ops[0],
8d157f96 1173 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1174 },
1175/* bgtz $src2,$disp16 */
1176 {
23cf992f 1177 { 1, 1, 1, 1 },
1294c286 1178 M32R_INSN_BGTZ, "bgtz", "bgtz",
2e6dfccc 1179 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1180 { 32, 32, 0xfff00000 }, 0xb0d00000,
c2009f4a 1181 "(if (gt src2 (const: WI 0)) (set pc disp16))",
1294c286 1182 (PTR) & fmt_beqz_ops[0],
8d157f96 1183 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1184 },
1185/* blez $src2,$disp16 */
1186 {
23cf992f 1187 { 1, 1, 1, 1 },
1294c286 1188 M32R_INSN_BLEZ, "blez", "blez",
2e6dfccc 1189 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1190 { 32, 32, 0xfff00000 }, 0xb0c00000,
c2009f4a 1191 "(if (le src2 (const: WI 0)) (set pc disp16))",
1294c286 1192 (PTR) & fmt_beqz_ops[0],
8d157f96 1193 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1194 },
1195/* bltz $src2,$disp16 */
1196 {
23cf992f 1197 { 1, 1, 1, 1 },
1294c286 1198 M32R_INSN_BLTZ, "bltz", "bltz",
2e6dfccc 1199 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1200 { 32, 32, 0xfff00000 }, 0xb0a00000,
c2009f4a 1201 "(if (lt src2 (const: WI 0)) (set pc disp16))",
1294c286 1202 (PTR) & fmt_beqz_ops[0],
8d157f96 1203 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1204 },
1205/* bnez $src2,$disp16 */
1206 {
23cf992f 1207 { 1, 1, 1, 1 },
1294c286 1208 M32R_INSN_BNEZ, "bnez", "bnez",
2e6dfccc 1209 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1210 { 32, 32, 0xfff00000 }, 0xb0900000,
c2009f4a 1211 "(if (ne src2 (const: WI 0)) (set pc disp16))",
1294c286 1212 (PTR) & fmt_beqz_ops[0],
8d157f96 1213 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1214 },
9c03036a
DE		 1215/* bl.s $disp8 */
1216 {
23cf992f 1217 { 1, 1, 1, 1 },
1294c286 1218 M32R_INSN_BL8, "bl8", "bl.s",
2e6dfccc 1219 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1220 { 16, 16, 0xff00 }, 0x7e00,
c2009f4a 1221 "(sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8))",
1294c286
DE		 1222 (PTR) & fmt_bl8_ops[0],
1223 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1224 },
1225/* bl.l $disp24 */
1226 {
23cf992f 1227 { 1, 1, 1, 1 },
1294c286 1228 M32R_INSN_BL24, "bl24", "bl.l",
2e6dfccc 1229 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1230 { 32, 32, 0xff000000 }, 0xfe000000,
c2009f4a 1231 "(sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24))",
1294c286
DE		 1232 (PTR) & fmt_bl24_ops[0],
1233 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
7c26196f 1234 },
7c26196f
DE		 1235/* start-sanitize-m32rx */
1236/* bcl.s $disp8 */
1237 {
1238 { 1, 1, 1, 1 },
1294c286 1239 M32R_INSN_BCL8, "bcl8", "bcl.s",
2e6dfccc 1240 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1241 { 16, 16, 0xff00 }, 0x7800,
c2009f4a 1242 "(if condbit (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
1294c286
DE		 1243 (PTR) & fmt_bcl8_ops[0],
1244 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1245 },
1246/* end-sanitize-m32rx */
1247/* start-sanitize-m32rx */
1248/* bcl.l $disp24 */
1249 {
1250 { 1, 1, 1, 1 },
1294c286 1251 M32R_INSN_BCL24, "bcl24", "bcl.l",
2e6dfccc 1252 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1253 { 32, 32, 0xff000000 }, 0xf8000000,
c2009f4a 1254 "(if condbit (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
1294c286
DE		 1255 (PTR) & fmt_bcl24_ops[0],
1256 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
9c03036a 1257 },
7c26196f 1258/* end-sanitize-m32rx */
9c03036a
DE		 1259/* bnc.s $disp8 */
1260 {
23cf992f 1261 { 1, 1, 1, 1 },
1294c286 1262 M32R_INSN_BNC8, "bnc8", "bnc.s",
2e6dfccc 1263 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1264 { 16, 16, 0xff00 }, 0x7d00,
c2009f4a 1265 "(if (not condbit) (set pc disp8))",
1294c286
DE		 1266 (PTR) & fmt_bc8_ops[0],
1267 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1268 },
1269/* bnc.l $disp24 */
1270 {
23cf992f 1271 { 1, 1, 1, 1 },
1294c286 1272 M32R_INSN_BNC24, "bnc24", "bnc.l",
2e6dfccc 1273 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1274 { 32, 32, 0xff000000 }, 0xfd000000,
c2009f4a 1275 "(if (not condbit) (set pc disp24))",
1294c286
DE		 1276 (PTR) & fmt_bc24_ops[0],
1277 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1278 },
1279/* bne $src1,$src2,$disp16 */
1280 {
23cf992f 1281 { 1, 1, 1, 1 },
1294c286 1282 M32R_INSN_BNE, "bne", "bne",
2e6dfccc 1283 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1284 { 32, 32, 0xf0f00000 }, 0xb0100000,
c2009f4a 1285 "(if (ne src1 src2) (set pc disp16))",
1294c286 1286 (PTR) & fmt_beq_ops[0],
8d157f96 1287 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1288 },
9c03036a
DE		 1289/* bra.s $disp8 */
1290 {
23cf992f 1291 { 1, 1, 1, 1 },
1294c286 1292 M32R_INSN_BRA8, "bra8", "bra.s",
2e6dfccc 1293 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1294 { 16, 16, 0xff00 }, 0x7f00,
c2009f4a 1295 "(set pc disp8)",
1294c286
DE		 1296 (PTR) & fmt_bra8_ops[0],
1297 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1298 },
1299/* bra.l $disp24 */
1300 {
23cf992f 1301 { 1, 1, 1, 1 },
1294c286 1302 M32R_INSN_BRA24, "bra24", "bra.l",
2e6dfccc 1303 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1304 { 32, 32, 0xff000000 }, 0xff000000,
c2009f4a 1305 "(set pc disp24)",
1294c286
DE		 1306 (PTR) & fmt_bra24_ops[0],
1307 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
7c26196f
DE		 1308 },
1309/* start-sanitize-m32rx */
7c26196f
DE		 1310/* bncl.s $disp8 */
1311 {
1312 { 1, 1, 1, 1 },
1294c286 1313 M32R_INSN_BNCL8, "bncl8", "bncl.s",
2e6dfccc 1314 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1315 { 16, 16, 0xff00 }, 0x7900,
c2009f4a 1316 "(if (not condbit) (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
1294c286
DE		 1317 (PTR) & fmt_bcl8_ops[0],
1318 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1319 },
1320/* end-sanitize-m32rx */
1321/* start-sanitize-m32rx */
1322/* bncl.l $disp24 */
1323 {
1324 { 1, 1, 1, 1 },
1294c286 1325 M32R_INSN_BNCL24, "bncl24", "bncl.l",
2e6dfccc 1326 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1327 { 32, 32, 0xff000000 }, 0xf9000000,
c2009f4a 1328 "(if (not condbit) (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
1294c286
DE		 1329 (PTR) & fmt_bcl24_ops[0],
1330 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 1331 },
1332/* end-sanitize-m32rx */
9c03036a
DE		 1333/* cmp $src1,$src2 */
1334 {
23cf992f 1335 { 1, 1, 1, 1 },
1294c286 1336 M32R_INSN_CMP, "cmp", "cmp",
2e6dfccc 1337 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1338 { 16, 16, 0xf0f0 }, 0x40,
c2009f4a 1339 "(set condbit (lt src1 src2))",
1294c286 1340 (PTR) & fmt_cmp_ops[0],
8d157f96 1341 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1342 },
9c03036a
DE		 1343/* cmpi $src2,$simm16 */
1344 {
23cf992f 1345 { 1, 1, 1, 1 },
1294c286 1346 M32R_INSN_CMPI, "cmpi", "cmpi",
2e6dfccc 1347 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
0bf55db8 1348 { 32, 32, 0xfff00000 }, 0x80400000,
c2009f4a 1349 "(set condbit (lt src2 simm16))",
1294c286 1350 (PTR) & fmt_cmpi_ops[0],
a6cefe4f 1351 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1352 },
1353/* cmpu $src1,$src2 */
1354 {
23cf992f 1355 { 1, 1, 1, 1 },
1294c286 1356 M32R_INSN_CMPU, "cmpu", "cmpu",
2e6dfccc 1357 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1358 { 16, 16, 0xf0f0 }, 0x50,
c2009f4a 1359 "(set condbit (ltu src1 src2))",
1294c286 1360 (PTR) & fmt_cmp_ops[0],
8d157f96 1361 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1362 },
1294c286 1363/* cmpui $src2,$simm16 */
23cf992f
NC		 1364 {
1365 { 1, 1, 1, 1 },
1294c286 1366 M32R_INSN_CMPUI, "cmpui", "cmpui",
2e6dfccc 1367 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
0bf55db8 1368 { 32, 32, 0xfff00000 }, 0x80500000,
c2009f4a 1369 "(set condbit (ltu src2 simm16))",
1294c286 1370 (PTR) & fmt_cmpi_ops[0],
a6cefe4f 1371 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
7c26196f
DE		 1372 },
1373/* start-sanitize-m32rx */
1374/* cmpeq $src1,$src2 */
1375 {
1376 { 1, 1, 1, 1 },
1294c286 1377 M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
2e6dfccc 1378 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1379 { 16, 16, 0xf0f0 }, 0x60,
c2009f4a 1380 "(set condbit (eq src1 src2))",
1294c286 1381 (PTR) & fmt_cmp_ops[0],
8d157f96 1382 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 1383 },
1384/* end-sanitize-m32rx */
1385/* start-sanitize-m32rx */
1386/* cmpz $src2 */
1387 {
1388 { 1, 1, 1, 1 },
1294c286 1389 M32R_INSN_CMPZ, "cmpz", "cmpz",
2e6dfccc 1390 { { MNEM, ' ', OP (SRC2), 0 } },
0bf55db8 1391 { 16, 16, 0xfff0 }, 0x70,
c2009f4a 1392 "(set condbit (eq src2 (const 0)))",
1294c286 1393 (PTR) & fmt_cmpz_ops[0],
8d157f96 1394 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
9c03036a 1395 },
7c26196f 1396/* end-sanitize-m32rx */
9c03036a
DE		 1397/* div $dr,$sr */
1398 {
23cf992f 1399 { 1, 1, 1, 1 },
1294c286 1400 M32R_INSN_DIV, "div", "div",
2e6dfccc 1401 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1402 { 32, 32, 0xf0f0ffff }, 0x90000000,
c2009f4a 1403 "(if (ne sr (const 0)) (set dr (div dr sr)))",
1294c286 1404 (PTR) & fmt_div_ops[0],
8d157f96 1405 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1406 },
1407/* divu $dr,$sr */
1408 {
23cf992f 1409 { 1, 1, 1, 1 },
1294c286 1410 M32R_INSN_DIVU, "divu", "divu",
2e6dfccc 1411 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1412 { 32, 32, 0xf0f0ffff }, 0x90100000,
c2009f4a 1413 "(if (ne sr (const 0)) (set dr (udiv dr sr)))",
1294c286 1414 (PTR) & fmt_div_ops[0],
8d157f96 1415 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1416 },
1417/* rem $dr,$sr */
1418 {
23cf992f 1419 { 1, 1, 1, 1 },
1294c286 1420 M32R_INSN_REM, "rem", "rem",
2e6dfccc 1421 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1422 { 32, 32, 0xf0f0ffff }, 0x90200000,
c2009f4a 1423 "(if (ne sr (const 0)) (set dr (mod dr sr)))",
1294c286 1424 (PTR) & fmt_div_ops[0],
8d157f96 1425 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1426 },
1427/* remu $dr,$sr */
1428 {
23cf992f 1429 { 1, 1, 1, 1 },
1294c286 1430 M32R_INSN_REMU, "remu", "remu",
2e6dfccc 1431 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1432 { 32, 32, 0xf0f0ffff }, 0x90300000,
c2009f4a 1433 "(if (ne sr (const 0)) (set dr (umod dr sr)))",
1294c286 1434 (PTR) & fmt_div_ops[0],
8d157f96 1435 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
ab0bd049
DE		 1436 },
1437/* start-sanitize-m32rx */
1438/* divh $dr,$sr */
1439 {
1440 { 1, 1, 1, 1 },
1294c286 1441 M32R_INSN_DIVH, "divh", "divh",
2e6dfccc 1442 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1443 { 32, 32, 0xf0f0ffff }, 0x90000010,
c2009f4a 1444 "(if (ne sr (const 0)) (set dr (div (ext: WI (trunc: HI dr)) sr)))",
1294c286 1445 (PTR) & fmt_div_ops[0],
8d157f96 1446 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f 1447 },
ab0bd049 1448/* end-sanitize-m32rx */
7c26196f
DE		 1449/* start-sanitize-m32rx */
1450/* jc $sr */
1451 {
1452 { 1, 1, 1, 1 },
1294c286 1453 M32R_INSN_JC, "jc", "jc",
2e6dfccc 1454 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1455 { 16, 16, 0xfff0 }, 0x1cc0,
c2009f4a 1456 "(if condbit (set pc (and sr (const -4))))",
1294c286 1457 (PTR) & fmt_jc_ops[0],
fbc8134d 1458 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1459 },
1460/* end-sanitize-m32rx */
1461/* start-sanitize-m32rx */
1462/* jnc $sr */
1463 {
1464 { 1, 1, 1, 1 },
1294c286 1465 M32R_INSN_JNC, "jnc", "jnc",
2e6dfccc 1466 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1467 { 16, 16, 0xfff0 }, 0x1dc0,
c2009f4a 1468 "(if (not condbit) (set pc (and sr (const -4))))",
1294c286 1469 (PTR) & fmt_jc_ops[0],
fbc8134d 1470 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
9c03036a 1471 },
7c26196f 1472/* end-sanitize-m32rx */
9c03036a
DE		 1473/* jl $sr */
1474 {
23cf992f 1475 { 1, 1, 1, 1 },
1294c286 1476 M32R_INSN_JL, "jl", "jl",
2e6dfccc 1477 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1478 { 16, 16, 0xfff0 }, 0x1ec0,
c2009f4a 1479 "(parallel () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc (and sr (const -4))))",
1294c286 1480 (PTR) & fmt_jl_ops[0],
8d157f96 1481 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1482 },
1483/* jmp $sr */
1484 {
23cf992f 1485 { 1, 1, 1, 1 },
1294c286 1486 M32R_INSN_JMP, "jmp", "jmp",
2e6dfccc 1487 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1488 { 16, 16, 0xfff0 }, 0x1fc0,
c2009f4a 1489 "(set pc (and sr (const -4)))",
1294c286 1490 (PTR) & fmt_jmp_ops[0],
8d157f96 1491 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1492 },
1493/* ld $dr,@$sr */
1494 {
23cf992f 1495 { 1, 1, 1, 1 },
1294c286 1496 M32R_INSN_LD, "ld", "ld",
2e6dfccc 1497 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1498 { 16, 16, 0xf0f0 }, 0x20c0,
c2009f4a 1499 "(set dr (mem: WI sr))",
1294c286 1500 (PTR) & fmt_ld_ops[0],
8d157f96 1501 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1502 },
9c03036a
DE		 1503/* ld $dr,@($slo16,$sr) */
1504 {
23cf992f 1505 { 1, 1, 1, 1 },
1294c286 1506 M32R_INSN_LD_D, "ld-d", "ld",
2e6dfccc 1507 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1508 { 32, 32, 0xf0f00000 }, 0xa0c00000,
c2009f4a 1509 "(set dr (mem: WI (add sr slo16)))",
1294c286 1510 (PTR) & fmt_ld_d_ops[0],
8d157f96 1511 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1512 },
9c03036a
DE		 1513/* ldb $dr,@$sr */
1514 {
23cf992f 1515 { 1, 1, 1, 1 },
1294c286 1516 M32R_INSN_LDB, "ldb", "ldb",
2e6dfccc 1517 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1518 { 16, 16, 0xf0f0 }, 0x2080,
c2009f4a 1519 "(set dr (ext: WI (mem: QI sr)))",
1294c286 1520 (PTR) & fmt_ldb_ops[0],
8d157f96 1521 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1522 },
9c03036a
DE		 1523/* ldb $dr,@($slo16,$sr) */
1524 {
23cf992f 1525 { 1, 1, 1, 1 },
1294c286 1526 M32R_INSN_LDB_D, "ldb-d", "ldb",
2e6dfccc 1527 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1528 { 32, 32, 0xf0f00000 }, 0xa0800000,
c2009f4a 1529 "(set dr (ext: WI (mem: QI (add sr slo16))))",
1294c286 1530 (PTR) & fmt_ldb_d_ops[0],
8d157f96 1531 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1532 },
9c03036a
DE		 1533/* ldh $dr,@$sr */
1534 {
23cf992f 1535 { 1, 1, 1, 1 },
1294c286 1536 M32R_INSN_LDH, "ldh", "ldh",
2e6dfccc 1537 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1538 { 16, 16, 0xf0f0 }, 0x20a0,
c2009f4a 1539 "(set dr (ext: WI (mem: HI sr)))",
1294c286 1540 (PTR) & fmt_ldh_ops[0],
8d157f96 1541 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1542 },
9c03036a
DE		 1543/* ldh $dr,@($slo16,$sr) */
1544 {
23cf992f 1545 { 1, 1, 1, 1 },
1294c286 1546 M32R_INSN_LDH_D, "ldh-d", "ldh",
2e6dfccc 1547 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1548 { 32, 32, 0xf0f00000 }, 0xa0a00000,
c2009f4a 1549 "(set dr (ext: WI (mem: HI (add sr slo16))))",
1294c286 1550 (PTR) & fmt_ldh_d_ops[0],
8d157f96 1551 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1552 },
9c03036a
DE		 1553/* ldub $dr,@$sr */
1554 {
23cf992f 1555 { 1, 1, 1, 1 },
1294c286 1556 M32R_INSN_LDUB, "ldub", "ldub",
2e6dfccc 1557 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1558 { 16, 16, 0xf0f0 }, 0x2090,
c2009f4a 1559 "(set dr (zext: WI (mem: QI sr)))",
1294c286 1560 (PTR) & fmt_ldb_ops[0],
8d157f96 1561 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1562 },
9c03036a
DE		 1563/* ldub $dr,@($slo16,$sr) */
1564 {
23cf992f 1565 { 1, 1, 1, 1 },
1294c286 1566 M32R_INSN_LDUB_D, "ldub-d", "ldub",
2e6dfccc 1567 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1568 { 32, 32, 0xf0f00000 }, 0xa0900000,
c2009f4a 1569 "(set dr (zext: WI (mem: QI (add sr slo16))))",
1294c286 1570 (PTR) & fmt_ldb_d_ops[0],
8d157f96 1571 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1572 },
9c03036a
DE		 1573/* lduh $dr,@$sr */
1574 {
23cf992f 1575 { 1, 1, 1, 1 },
1294c286 1576 M32R_INSN_LDUH, "lduh", "lduh",
2e6dfccc 1577 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1578 { 16, 16, 0xf0f0 }, 0x20b0,
c2009f4a 1579 "(set dr (zext: WI (mem: HI sr)))",
1294c286 1580 (PTR) & fmt_ldh_ops[0],
8d157f96 1581 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1582 },
9c03036a
DE		 1583/* lduh $dr,@($slo16,$sr) */
1584 {
23cf992f 1585 { 1, 1, 1, 1 },
1294c286 1586 M32R_INSN_LDUH_D, "lduh-d", "lduh",
2e6dfccc 1587 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1588 { 32, 32, 0xf0f00000 }, 0xa0b00000,
c2009f4a 1589 "(set dr (zext: WI (mem: HI (add sr slo16))))",
1294c286 1590 (PTR) & fmt_ldh_d_ops[0],
8d157f96 1591 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1592 },
9c03036a
DE		 1593/* ld $dr,@$sr+ */
1594 {
23cf992f 1595 { 1, 1, 1, 1 },
1294c286 1596 M32R_INSN_LD_PLUS, "ld-plus", "ld",
2e6dfccc 1597 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
0bf55db8 1598 { 16, 16, 0xf0f0 }, 0x20e0,
c2009f4a 1599 "(parallel () (set dr (mem: WI sr)) (set sr (add sr (const 4))))",
1294c286 1600 (PTR) & fmt_ld_plus_ops[0],
8d157f96 1601 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1602 },
9c03036a
DE		 1603/* ld24 $dr,$uimm24 */
1604 {
23cf992f 1605 { 1, 1, 1, 1 },
1294c286 1606 M32R_INSN_LD24, "ld24", "ld24",
2e6dfccc 1607 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
0bf55db8 1608 { 32, 32, 0xf0000000 }, 0xe0000000,
c2009f4a 1609 "(set dr uimm24)",
1294c286 1610 (PTR) & fmt_ld24_ops[0],
a6cefe4f 1611 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1612 },
9c03036a
DE		 1613/* ldi8 $dr,$simm8 */
1614 {
23cf992f 1615 { 1, 1, 1, 1 },
1294c286 1616 M32R_INSN_LDI8, "ldi8", "ldi8",
2e6dfccc 1617 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
0bf55db8 1618 { 16, 16, 0xf000 }, 0x6000,
c2009f4a 1619 "(set dr simm8)",
1294c286
DE		 1620 (PTR) & fmt_ldi8_ops[0],
1621 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1622 },
a6cefe4f 1623/* ldi16 $dr,$hash$slo16 */
9c03036a 1624 {
23cf992f 1625 { 1, 1, 1, 1 },
1294c286 1626 M32R_INSN_LDI16, "ldi16", "ldi16",
2e6dfccc 1627 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
0bf55db8 1628 { 32, 32, 0xf0ff0000 }, 0x90f00000,
c2009f4a 1629 "(set dr slo16)",
1294c286
DE		 1630 (PTR) & fmt_ldi16_ops[0],
1631 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1632 },
1633/* lock $dr,@$sr */
1634 {
23cf992f 1635 { 1, 1, 1, 1 },
1294c286 1636 M32R_INSN_LOCK, "lock", "lock",
2e6dfccc 1637 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1638 { 16, 16, 0xf0f0 }, 0x20d0,
c2009f4a 1639 "(sequence () (set (reg h-lock) (const: UBI 1)) (set dr (mem: WI sr)))",
1294c286 1640 (PTR) & fmt_lock_ops[0],
8d157f96 1641 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1642 },
1643/* machi $src1,$src2 */
1644 {
23cf992f 1645 { 1, 1, 1, 1 },
1294c286 1646 M32R_INSN_MACHI, "machi", "machi",
2e6dfccc 1647 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1648 { 16, 16, 0xf0f0 }, 0x3040,
c2009f4a 1649 "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
1294c286 1650 (PTR) & fmt_machi_ops[0],
8d157f96 1651 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1652 },
1653/* start-sanitize-m32rx */
1654/* machi $src1,$src2,$acc */
1655 {
1656 { 1, 1, 1, 1 },
1294c286 1657 M32R_INSN_MACHI_A, "machi-a", "machi",
2e6dfccc 1658 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1659 { 16, 16, 0xf070 }, 0x3040,
c2009f4a 1660 "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
1294c286 1661 (PTR) & fmt_machi_a_ops[0],
8d157f96 1662 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1663 },
7c26196f 1664/* end-sanitize-m32rx */
9c03036a
DE		 1665/* maclo $src1,$src2 */
1666 {
23cf992f 1667 { 1, 1, 1, 1 },
1294c286 1668 M32R_INSN_MACLO, "maclo", "maclo",
2e6dfccc 1669 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1670 { 16, 16, 0xf0f0 }, 0x3050,
c2009f4a 1671 "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
1294c286 1672 (PTR) & fmt_machi_ops[0],
8d157f96 1673 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1674 },
7c26196f
DE		 1675/* start-sanitize-m32rx */
1676/* maclo $src1,$src2,$acc */
1677 {
1678 { 1, 1, 1, 1 },
1294c286 1679 M32R_INSN_MACLO_A, "maclo-a", "maclo",
2e6dfccc 1680 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1681 { 16, 16, 0xf070 }, 0x3050,
c2009f4a 1682 "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
1294c286 1683 (PTR) & fmt_machi_a_ops[0],
8d157f96 1684 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1685 },
1686/* end-sanitize-m32rx */
9c03036a
DE		 1687/* macwhi $src1,$src2 */
1688 {
23cf992f 1689 { 1, 1, 1, 1 },
1294c286 1690 M32R_INSN_MACWHI, "macwhi", "macwhi",
2e6dfccc 1691 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1692 { 16, 16, 0xf0f0 }, 0x3060,
c2009f4a 1693 "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
1294c286 1694 (PTR) & fmt_machi_ops[0],
8d157f96 1695 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1696 },
c2009f4a
DE		 1697/* start-sanitize-m32rx */
1698/* macwhi $src1,$src2,$acc */
1699 {
1700 { 1, 1, 1, 1 },
1701 M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
1702 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1703 { 16, 16, 0xf070 }, 0x3060,
1704 "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16)))))))",
1705 (PTR) & fmt_machi_a_ops[0],
1706 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1707 },
1708/* end-sanitize-m32rx */
9c03036a
DE		 1709/* macwlo $src1,$src2 */
1710 {
23cf992f 1711 { 1, 1, 1, 1 },
1294c286 1712 M32R_INSN_MACWLO, "macwlo", "macwlo",
2e6dfccc 1713 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1714 { 16, 16, 0xf0f0 }, 0x3070,
c2009f4a 1715 "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
1294c286 1716 (PTR) & fmt_machi_ops[0],
8d157f96 1717 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1718 },
c2009f4a
DE		 1719/* start-sanitize-m32rx */
1720/* macwlo $src1,$src2,$acc */
1721 {
1722 { 1, 1, 1, 1 },
1723 M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
1724 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1725 { 16, 16, 0xf070 }, 0x3070,
1726 "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI src2)))))",
1727 (PTR) & fmt_machi_a_ops[0],
1728 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1729 },
1730/* end-sanitize-m32rx */
9c03036a
DE		 1731/* mul $dr,$sr */
1732 {
23cf992f 1733 { 1, 1, 1, 1 },
1294c286 1734 M32R_INSN_MUL, "mul", "mul",
2e6dfccc 1735 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1736 { 16, 16, 0xf0f0 }, 0x1060,
c2009f4a 1737 "(set dr (mul dr sr))",
1294c286 1738 (PTR) & fmt_add_ops[0],
8d157f96 1739 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1740 },
1741/* mulhi $src1,$src2 */
1742 {
23cf992f 1743 { 1, 1, 1, 1 },
1294c286 1744 M32R_INSN_MULHI, "mulhi", "mulhi",
2e6dfccc 1745 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1746 { 16, 16, 0xf0f0 }, 0x3000,
c2009f4a 1747 "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
1294c286 1748 (PTR) & fmt_mulhi_ops[0],
8d157f96 1749 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1750 },
1751/* start-sanitize-m32rx */
1752/* mulhi $src1,$src2,$acc */
1753 {
1754 { 1, 1, 1, 1 },
1294c286 1755 M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
2e6dfccc 1756 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1757 { 16, 16, 0xf070 }, 0x3000,
c2009f4a 1758 "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
1294c286 1759 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1760 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1761 },
7c26196f 1762/* end-sanitize-m32rx */
9c03036a
DE		 1763/* mullo $src1,$src2 */
1764 {
23cf992f 1765 { 1, 1, 1, 1 },
1294c286 1766 M32R_INSN_MULLO, "mullo", "mullo",
2e6dfccc 1767 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1768 { 16, 16, 0xf0f0 }, 0x3010,
c2009f4a 1769 "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
1294c286 1770 (PTR) & fmt_mulhi_ops[0],
8d157f96 1771 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1772 },
7c26196f
DE		 1773/* start-sanitize-m32rx */
1774/* mullo $src1,$src2,$acc */
1775 {
1776 { 1, 1, 1, 1 },
1294c286 1777 M32R_INSN_MULLO_A, "mullo-a", "mullo",
2e6dfccc 1778 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1779 { 16, 16, 0xf070 }, 0x3010,
c2009f4a 1780 "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
1294c286 1781 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1782 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1783 },
1784/* end-sanitize-m32rx */
9c03036a
DE		 1785/* mulwhi $src1,$src2 */
1786 {
23cf992f 1787 { 1, 1, 1, 1 },
1294c286 1788 M32R_INSN_MULWHI, "mulwhi", "mulwhi",
2e6dfccc 1789 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1790 { 16, 16, 0xf0f0 }, 0x3020,
c2009f4a 1791 "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 8)) (const 8)))",
1294c286 1792 (PTR) & fmt_mulhi_ops[0],
8d157f96 1793 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1794 },
c2009f4a
DE		 1795/* start-sanitize-m32rx */
1796/* mulwhi $src1,$src2,$acc */
1797 {
1798 { 1, 1, 1, 1 },
1799 M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
1800 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1801 { 16, 16, 0xf070 }, 0x3020,
1802 "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16))))))",
1803 (PTR) & fmt_mulhi_a_ops[0],
1804 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1805 },
1806/* end-sanitize-m32rx */
9c03036a
DE		 1807/* mulwlo $src1,$src2 */
1808 {
23cf992f 1809 { 1, 1, 1, 1 },
1294c286 1810 M32R_INSN_MULWLO, "mulwlo", "mulwlo",
2e6dfccc 1811 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1812 { 16, 16, 0xf0f0 }, 0x3030,
c2009f4a 1813 "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2))) (const 8)) (const 8)))",
1294c286 1814 (PTR) & fmt_mulhi_ops[0],
8d157f96 1815 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1816 },
c2009f4a
DE		 1817/* start-sanitize-m32rx */
1818/* mulwlo $src1,$src2,$acc */
1819 {
1820 { 1, 1, 1, 1 },
1821 M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
1822 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1823 { 16, 16, 0xf070 }, 0x3030,
1824 "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI src2))))",
1825 (PTR) & fmt_mulhi_a_ops[0],
1826 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1827 },
1828/* end-sanitize-m32rx */
9c03036a
DE		 1829/* mv $dr,$sr */
1830 {
23cf992f 1831 { 1, 1, 1, 1 },
1294c286 1832 M32R_INSN_MV, "mv", "mv",
2e6dfccc 1833 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1834 { 16, 16, 0xf0f0 }, 0x1080,
c2009f4a 1835 "(set dr sr)",
1294c286 1836 (PTR) & fmt_mv_ops[0],
8d157f96 1837 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1838 },
1839/* mvfachi $dr */
1840 {
23cf992f 1841 { 1, 1, 1, 1 },
1294c286 1842 M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
2e6dfccc 1843 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1844 { 16, 16, 0xf0ff }, 0x50f0,
c2009f4a 1845 "(set dr (trunc: WI (sra: DI accum (const 32))))",
1294c286 1846 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1847 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1848 },
1849/* start-sanitize-m32rx */
1850/* mvfachi $dr,$accs */
1851 {
1852 { 1, 1, 1, 1 },
1294c286 1853 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
2e6dfccc 1854 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1855 { 16, 16, 0xf0f3 }, 0x50f0,
c2009f4a 1856 "(set dr (trunc: WI (sra: DI accs (const 32))))",
1294c286 1857 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1858 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1859 },
7c26196f 1860/* end-sanitize-m32rx */
9c03036a
DE		 1861/* mvfaclo $dr */
1862 {
23cf992f 1863 { 1, 1, 1, 1 },
1294c286 1864 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
2e6dfccc 1865 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1866 { 16, 16, 0xf0ff }, 0x50f1,
c2009f4a 1867 "(set dr (trunc: WI accum))",
1294c286 1868 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1869 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1870 },
7c26196f
DE		 1871/* start-sanitize-m32rx */
1872/* mvfaclo $dr,$accs */
1873 {
1874 { 1, 1, 1, 1 },
1294c286 1875 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
2e6dfccc 1876 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1877 { 16, 16, 0xf0f3 }, 0x50f1,
c2009f4a 1878 "(set dr (trunc: WI accs))",
1294c286 1879 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1880 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1881 },
1882/* end-sanitize-m32rx */
9c03036a
DE		 1883/* mvfacmi $dr */
1884 {
23cf992f 1885 { 1, 1, 1, 1 },
1294c286 1886 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
2e6dfccc 1887 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1888 { 16, 16, 0xf0ff }, 0x50f2,
c2009f4a 1889 "(set dr (trunc: WI (sra: DI accum (const 16))))",
1294c286 1890 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1891 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1892 },
1893/* start-sanitize-m32rx */
1894/* mvfacmi $dr,$accs */
1895 {
1896 { 1, 1, 1, 1 },
1294c286 1897 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
2e6dfccc 1898 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1899 { 16, 16, 0xf0f3 }, 0x50f2,
c2009f4a 1900 "(set dr (trunc: WI (sra: DI accs (const 16))))",
1294c286 1901 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1902 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1903 },
7c26196f 1904/* end-sanitize-m32rx */
9c03036a
DE		 1905/* mvfc $dr,$scr */
1906 {
23cf992f 1907 { 1, 1, 1, 1 },
1294c286 1908 M32R_INSN_MVFC, "mvfc", "mvfc",
2e6dfccc 1909 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
0bf55db8 1910 { 16, 16, 0xf0f0 }, 0x1090,
c2009f4a 1911 "(set dr scr)",
1294c286 1912 (PTR) & fmt_mvfc_ops[0],
8d157f96 1913 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1914 },
1915/* mvtachi $src1 */
1916 {
23cf992f 1917 { 1, 1, 1, 1 },
1294c286 1918 M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
2e6dfccc 1919 { { MNEM, ' ', OP (SRC1), 0 } },
0bf55db8 1920 { 16, 16, 0xf0ff }, 0x5070,
c2009f4a 1921 "(set accum (or: DI (and: DI accum (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
1294c286 1922 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1923 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1924 },
7c26196f
DE		 1925/* start-sanitize-m32rx */
1926/* mvtachi $src1,$accs */
1927 {
1928 { 1, 1, 1, 1 },
1294c286 1929 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
2e6dfccc 1930 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
0bf55db8 1931 { 16, 16, 0xf0f3 }, 0x5070,
c2009f4a 1932 "(set accs (or: DI (and: DI accs (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
1294c286 1933 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1934 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1935 },
1936/* end-sanitize-m32rx */
9c03036a
DE		 1937/* mvtaclo $src1 */
1938 {
23cf992f 1939 { 1, 1, 1, 1 },
1294c286 1940 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
2e6dfccc 1941 { { MNEM, ' ', OP (SRC1), 0 } },
0bf55db8 1942 { 16, 16, 0xf0ff }, 0x5071,
c2009f4a 1943 "(set accum (or: DI (and: DI accum (const: DI 18446744069414584320)) (zext: DI src1)))",
1294c286 1944 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1945 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1946 },
1947/* start-sanitize-m32rx */
1948/* mvtaclo $src1,$accs */
1949 {
1950 { 1, 1, 1, 1 },
1294c286 1951 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
2e6dfccc 1952 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
0bf55db8 1953 { 16, 16, 0xf0f3 }, 0x5071,
c2009f4a 1954 "(set accs (or: DI (and: DI accs (const: DI 18446744069414584320)) (zext: DI src1)))",
1294c286 1955 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1956 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1957 },
7c26196f 1958/* end-sanitize-m32rx */
9c03036a
DE		 1959/* mvtc $sr,$dcr */
1960 {
23cf992f 1961 { 1, 1, 1, 1 },
1294c286 1962 M32R_INSN_MVTC, "mvtc", "mvtc",
2e6dfccc 1963 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
0bf55db8 1964 { 16, 16, 0xf0f0 }, 0x10a0,
c2009f4a 1965 "(set dcr sr)",
1294c286 1966 (PTR) & fmt_mvtc_ops[0],
8d157f96 1967 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1968 },
1969/* neg $dr,$sr */
1970 {
23cf992f 1971 { 1, 1, 1, 1 },
1294c286 1972 M32R_INSN_NEG, "neg", "neg",
2e6dfccc 1973 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1974 { 16, 16, 0xf0f0 }, 0x30,
c2009f4a 1975 "(set dr (neg sr))",
1294c286 1976 (PTR) & fmt_mv_ops[0],
8d157f96 1977 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1978 },
1979/* nop */
1980 {
23cf992f 1981 { 1, 1, 1, 1 },
1294c286 1982 M32R_INSN_NOP, "nop", "nop",
2e6dfccc 1983 { { MNEM, 0 } },
0bf55db8 1984 { 16, 16, 0xffff }, 0x7000,
c2009f4a
DE		 1985 "(c-code: VM PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1986)",
1294c286 1987 (PTR) 0,
8d157f96 1988 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1989 },
1990/* not $dr,$sr */
1991 {
23cf992f 1992 { 1, 1, 1, 1 },
1294c286 1993 M32R_INSN_NOT, "not", "not",
2e6dfccc 1994 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1995 { 16, 16, 0xf0f0 }, 0xb0,
c2009f4a 1996 "(set dr (inv sr))",
1294c286 1997 (PTR) & fmt_mv_ops[0],
8d157f96 1998 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1999 },
2000/* rac */
2001 {
23cf992f 2002 { 1, 1, 1, 1 },
1294c286 2003 M32R_INSN_RAC, "rac", "rac",
2e6dfccc 2004 { { MNEM, 0 } },
0bf55db8 2005 { 16, 16, 0xffff }, 0x5090,
c2009f4a 2006 "(sequence ((DI tmp1)) (set tmp1 (sll: DI accum (const 1))) (set tmp1 (add: DI tmp1 (const: DI 32768))) (set accum (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
1294c286 2007 (PTR) & fmt_rac_ops[0],
8d157f96 2008 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 2009 },
2010/* start-sanitize-m32rx */
a6cefe4f 2011/* rac $accd,$accs,$imm1 */
ab0bd049
DE		 2012 {
2013 { 1, 1, 1, 1 },
1294c286 2014 M32R_INSN_RAC_DSI, "rac-dsi", "rac",
2e6dfccc 2015 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
0bf55db8 2016 { 16, 16, 0xf3f2 }, 0x5090,
c2009f4a 2017 "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 32768))) (set accd (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
1294c286 2018 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 2019 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2020 },
7c26196f 2021/* end-sanitize-m32rx */
9c03036a
DE		 2022/* rach */
2023 {
23cf992f 2024 { 1, 1, 1, 1 },
1294c286 2025 M32R_INSN_RACH, "rach", "rach",
2e6dfccc 2026 { { MNEM, 0 } },
0bf55db8 2027 { 16, 16, 0xffff }, 0x5080,
c2009f4a 2028 "(sequence ((DI tmp1)) (set tmp1 (and accum (const: DI 72057594037927935))) (if (andif: WI (ge tmp1 (const: DI 70366596694016)) (le tmp1 (const: DI 36028797018963967))) (set tmp1 (const: DI 70366596694016)) (if (andif: WI (ge tmp1 (const: DI 36028797018963968)) (le tmp1 (const: DI 71987225293750272))) (set tmp1 (const: DI 71987225293750272)) (set tmp1 (and (add accum (const: DI 1073741824)) (const: DI 18446744071562067968))))) (set tmp1 (sll tmp1 (const 1))) (set accum (sra: DI (sll: DI tmp1 (const 7)) (const 7))))",
1294c286 2029 (PTR) & fmt_rac_ops[0],
8d157f96 2030 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
ab0bd049
DE		 2031 },
2032/* start-sanitize-m32rx */
a6cefe4f 2033/* rach $accd,$accs,$imm1 */
7c26196f
DE		 2034 {
2035 { 1, 1, 1, 1 },
1294c286 2036 M32R_INSN_RACH_DSI, "rach-dsi", "rach",
2e6dfccc 2037 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
0bf55db8 2038 { 16, 16, 0xf3f2 }, 0x5080,
c2009f4a 2039 "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 2147483648))) (set accd (cond: DI ((gt tmp1 (const: DI 140733193388032)) (const: DI 140733193388032)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744069414584320))))))",
1294c286 2040 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 2041 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2042 },
7c26196f 2043/* end-sanitize-m32rx */
9c03036a
DE		 2044/* rte */
2045 {
23cf992f 2046 { 1, 1, 1, 1 },
1294c286 2047 M32R_INSN_RTE, "rte", "rte",
2e6dfccc 2048 { { MNEM, 0 } },
0bf55db8 2049 { 16, 16, 0xffff }, 0x10d6,
c2009f4a 2050 "(sequence () (set (reg h-sm) (reg h-bsm)) (set (reg h-ie) (reg h-bie)) (set condbit (reg h-bcond)) (set pc (and (reg h-bpc) (const -4))))",
1294c286 2051 (PTR) & fmt_rte_ops[0],
8d157f96 2052 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
7c26196f 2053 },
a6cefe4f 2054/* seth $dr,$hash$hi16 */
7c26196f
DE		 2055 {
2056 { 1, 1, 1, 1 },
1294c286 2057 M32R_INSN_SETH, "seth", "seth",
2e6dfccc 2058 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
0bf55db8 2059 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
c2009f4a 2060 "(set dr (sll: WI hi16 (const 16)))",
1294c286 2061 (PTR) & fmt_seth_ops[0],
8d157f96 2062 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2063 },
9c03036a
DE		 2064/* sll $dr,$sr */
2065 {
23cf992f 2066 { 1, 1, 1, 1 },
1294c286 2067 M32R_INSN_SLL, "sll", "sll",
2e6dfccc 2068 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2069 { 16, 16, 0xf0f0 }, 0x1040,
c2009f4a 2070 "(set dr (sll dr (and sr (const 31))))",
1294c286 2071 (PTR) & fmt_add_ops[0],
8d157f96 2072 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 2073 },
9c03036a
DE		 2074/* sll3 $dr,$sr,$simm16 */
2075 {
23cf992f 2076 { 1, 1, 1, 1 },
1294c286 2077 M32R_INSN_SLL3, "sll3", "sll3",
2e6dfccc 2078 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 2079 { 32, 32, 0xf0f00000 }, 0x90c00000,
c2009f4a 2080 "(set dr (sll sr (and: WI simm16 (const 31))))",
1294c286 2081 (PTR) & fmt_sll3_ops[0],
a6cefe4f 2082 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 2083 },
2084/* slli $dr,$uimm5 */
2085 {
23cf992f 2086 { 1, 1, 1, 1 },
1294c286 2087 M32R_INSN_SLLI, "slli", "slli",
2e6dfccc 2088 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 2089 { 16, 16, 0xf0e0 }, 0x5040,
c2009f4a 2090 "(set dr (sll dr uimm5))",
1294c286 2091 (PTR) & fmt_slli_ops[0],
a6cefe4f 2092 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2093 },
2094/* sra $dr,$sr */
2095 {
23cf992f 2096 { 1, 1, 1, 1 },
1294c286 2097 M32R_INSN_SRA, "sra", "sra",
2e6dfccc 2098 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2099 { 16, 16, 0xf0f0 }, 0x1020,
c2009f4a 2100 "(set dr (sra dr (and sr (const 31))))",
1294c286 2101 (PTR) & fmt_add_ops[0],
8d157f96 2102 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 2103 },
9c03036a
DE		 2104/* sra3 $dr,$sr,$simm16 */
2105 {
23cf992f 2106 { 1, 1, 1, 1 },
1294c286 2107 M32R_INSN_SRA3, "sra3", "sra3",
2e6dfccc 2108 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 2109 { 32, 32, 0xf0f00000 }, 0x90a00000,
c2009f4a 2110 "(set dr (sra sr (and: WI simm16 (const 31))))",
1294c286 2111 (PTR) & fmt_sll3_ops[0],
a6cefe4f 2112 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 2113 },
2114/* srai $dr,$uimm5 */
2115 {
23cf992f 2116 { 1, 1, 1, 1 },
1294c286 2117 M32R_INSN_SRAI, "srai", "srai",
2e6dfccc 2118 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 2119 { 16, 16, 0xf0e0 }, 0x5020,
c2009f4a 2120 "(set dr (sra dr uimm5))",
1294c286 2121 (PTR) & fmt_slli_ops[0],
a6cefe4f 2122 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2123 },
2124/* srl $dr,$sr */
2125 {
23cf992f 2126 { 1, 1, 1, 1 },
1294c286 2127 M32R_INSN_SRL, "srl", "srl",
2e6dfccc 2128 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2129 { 16, 16, 0xf0f0 }, 0x1000,
c2009f4a 2130 "(set dr (srl dr (and sr (const 31))))",
1294c286 2131 (PTR) & fmt_add_ops[0],
8d157f96 2132 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 2133 },
9c03036a
DE		 2134/* srl3 $dr,$sr,$simm16 */
2135 {
23cf992f 2136 { 1, 1, 1, 1 },
1294c286 2137 M32R_INSN_SRL3, "srl3", "srl3",
2e6dfccc 2138 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 2139 { 32, 32, 0xf0f00000 }, 0x90800000,
c2009f4a 2140 "(set dr (srl sr (and: WI simm16 (const 31))))",
1294c286 2141 (PTR) & fmt_sll3_ops[0],
a6cefe4f 2142 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 2143 },
2144/* srli $dr,$uimm5 */
2145 {
23cf992f 2146 { 1, 1, 1, 1 },
1294c286 2147 M32R_INSN_SRLI, "srli", "srli",
2e6dfccc 2148 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 2149 { 16, 16, 0xf0e0 }, 0x5000,
c2009f4a 2150 "(set dr (srl dr uimm5))",
1294c286 2151 (PTR) & fmt_slli_ops[0],
a6cefe4f 2152 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2153 },
2154/* st $src1,@$src2 */
2155 {
23cf992f 2156 { 1, 1, 1, 1 },
1294c286 2157 M32R_INSN_ST, "st", "st",
2e6dfccc 2158 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2159 { 16, 16, 0xf0f0 }, 0x2040,
c2009f4a 2160 "(set: WI (mem: WI src2) src1)",
1294c286 2161 (PTR) & fmt_st_ops[0],
8d157f96 2162 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2163 },
9c03036a
DE		 2164/* st $src1,@($slo16,$src2) */
2165 {
23cf992f 2166 { 1, 1, 1, 1 },
1294c286 2167 M32R_INSN_ST_D, "st-d", "st",
2e6dfccc 2168 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2169 { 32, 32, 0xf0f00000 }, 0xa0400000,
c2009f4a 2170 "(set: WI (mem: WI (add src2 slo16)) src1)",
1294c286 2171 (PTR) & fmt_st_d_ops[0],
8d157f96 2172 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2173 },
9c03036a
DE		 2174/* stb $src1,@$src2 */
2175 {
23cf992f 2176 { 1, 1, 1, 1 },
1294c286 2177 M32R_INSN_STB, "stb", "stb",
2e6dfccc 2178 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2179 { 16, 16, 0xf0f0 }, 0x2000,
c2009f4a 2180 "(set: QI (mem: QI src2) src1)",
1294c286 2181 (PTR) & fmt_stb_ops[0],
8d157f96 2182 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2183 },
1294c286 2184/* stb $src1,@($slo16,$src2) */
9c03036a 2185 {
23cf992f 2186 { 1, 1, 1, 1 },
1294c286 2187 M32R_INSN_STB_D, "stb-d", "stb",
2e6dfccc 2188 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2189 { 32, 32, 0xf0f00000 }, 0xa0000000,
c2009f4a 2190 "(set: QI (mem: QI (add src2 slo16)) src1)",
1294c286 2191 (PTR) & fmt_stb_d_ops[0],
8d157f96 2192 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2193 },
9c03036a
DE		 2194/* sth $src1,@$src2 */
2195 {
23cf992f 2196 { 1, 1, 1, 1 },
1294c286 2197 M32R_INSN_STH, "sth", "sth",
2e6dfccc 2198 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2199 { 16, 16, 0xf0f0 }, 0x2020,
c2009f4a 2200 "(set: HI (mem: HI src2) src1)",
1294c286 2201 (PTR) & fmt_sth_ops[0],
8d157f96 2202 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2203 },
9c03036a
DE		 2204/* sth $src1,@($slo16,$src2) */
2205 {
23cf992f 2206 { 1, 1, 1, 1 },
1294c286 2207 M32R_INSN_STH_D, "sth-d", "sth",
2e6dfccc 2208 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2209 { 32, 32, 0xf0f00000 }, 0xa0200000,
c2009f4a 2210 "(set: HI (mem: HI (add src2 slo16)) src1)",
1294c286 2211 (PTR) & fmt_sth_d_ops[0],
8d157f96 2212 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2213 },
9c03036a
DE		 2214/* st $src1,@+$src2 */
2215 {
23cf992f 2216 { 1, 1, 1, 1 },
1294c286 2217 M32R_INSN_ST_PLUS, "st-plus", "st",
2e6dfccc 2218 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
0bf55db8 2219 { 16, 16, 0xf0f0 }, 0x2060,
c2009f4a 2220 "(sequence ((WI new-src2)) (set new-src2 (add: WI src2 (const: WI 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
1294c286 2221 (PTR) & fmt_st_plus_ops[0],
8d157f96 2222 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2223 },
2224/* st $src1,@-$src2 */
2225 {
23cf992f 2226 { 1, 1, 1, 1 },
1294c286 2227 M32R_INSN_ST_MINUS, "st-minus", "st",
2e6dfccc 2228 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
0bf55db8 2229 { 16, 16, 0xf0f0 }, 0x2070,
c2009f4a 2230 "(sequence ((WI new-src2)) (set new-src2 (sub src2 (const 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
1294c286 2231 (PTR) & fmt_st_plus_ops[0],
8d157f96 2232 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2233 },
2234/* sub $dr,$sr */
2235 {
23cf992f 2236 { 1, 1, 1, 1 },
1294c286 2237 M32R_INSN_SUB, "sub", "sub",
2e6dfccc 2238 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2239 { 16, 16, 0xf0f0 }, 0x20,
c2009f4a 2240 "(set dr (sub dr sr))",
1294c286 2241 (PTR) & fmt_add_ops[0],
8d157f96 2242 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 2243 },
2244/* subv $dr,$sr */
2245 {
23cf992f 2246 { 1, 1, 1, 1 },
1294c286 2247 M32R_INSN_SUBV, "subv", "subv",
2e6dfccc 2248 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2249 { 16, 16, 0xf0f0 }, 0x0,
c2009f4a 2250 "(parallel () (set dr (sub dr sr)) (set condbit (sub-oflag dr sr (const 0))))",
1294c286 2251 (PTR) & fmt_addv_ops[0],
8d157f96 2252 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 2253 },
2254/* subx $dr,$sr */
2255 {
23cf992f 2256 { 1, 1, 1, 1 },
1294c286 2257 M32R_INSN_SUBX, "subx", "subx",
2e6dfccc 2258 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2259 { 16, 16, 0xf0f0 }, 0x10,
c2009f4a 2260 "(parallel () (set dr (subc dr sr condbit)) (set condbit (sub-cflag dr sr condbit)))",
1294c286 2261 (PTR) & fmt_addx_ops[0],
8d157f96 2262 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 2263 },
a6cefe4f 2264/* trap $uimm4 */
7c26196f
DE		 2265 {
2266 { 1, 1, 1, 1 },
1294c286 2267 M32R_INSN_TRAP, "trap", "trap",
2e6dfccc 2268 { { MNEM, ' ', OP (UIMM4), 0 } },
0bf55db8 2269 { 16, 16, 0xfff0 }, 0x10f0,
c2009f4a 2270 "(sequence () (set (reg h-cr 6) (add pc (const 4))) (set (reg h-cr 0) (and (sll (reg h-cr 0) (const 8)) (const 65408))) (set: WI pc (c-call: WI m32r_trap uimm4)))",
1294c286 2271 (PTR) & fmt_trap_ops[0],
8d157f96 2272 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a 2273 },
9c03036a
DE		 2274/* unlock $src1,@$src2 */
2275 {
23cf992f 2276 { 1, 1, 1, 1 },
1294c286 2277 M32R_INSN_UNLOCK, "unlock", "unlock",
2e6dfccc 2278 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2279 { 16, 16, 0xf0f0 }, 0x2050,
c2009f4a 2280 "(sequence () (if (reg h-lock) (set (mem: WI src2) src1)) (set (reg h-lock) (const: UBI 0)))",
1294c286 2281 (PTR) & fmt_unlock_ops[0],
8d157f96 2282 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2283 },
7c26196f 2284/* start-sanitize-m32rx */
b02643b5 2285/* satb $dr,$sr */
7c26196f
DE		 2286 {
2287 { 1, 1, 1, 1 },
1294c286 2288 M32R_INSN_SATB, "satb", "satb",
2e6dfccc 2289 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
d8ca5fae 2290 { 32, 32, 0xf0f0ffff }, 0x80600300,
c2009f4a 2291 "(set dr (cond: WI ((ge sr (const 127)) (const 127)) ((le sr (const -128)) (const -128)) (else sr)))",
1294c286 2292 (PTR) & fmt_satb_ops[0],
8d157f96 2293 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2294 },
2295/* end-sanitize-m32rx */
2296/* start-sanitize-m32rx */
b02643b5 2297/* sath $dr,$sr */
7c26196f
DE		 2298 {
2299 { 1, 1, 1, 1 },
1294c286 2300 M32R_INSN_SATH, "sath", "sath",
2e6dfccc 2301 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
b2ddf0c4 2302 { 32, 32, 0xf0f0ffff }, 0x80600200,
c2009f4a 2303 "(set dr (cond: WI ((ge sr (const 32767)) (const 32767)) ((le sr (const -32768)) (const -32768)) (else sr)))",
1294c286 2304 (PTR) & fmt_satb_ops[0],
8d157f96 2305 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2306 },
2307/* end-sanitize-m32rx */
2308/* start-sanitize-m32rx */
b02643b5 2309/* sat $dr,$sr */
7c26196f
DE		 2310 {
2311 { 1, 1, 1, 1 },
1294c286 2312 M32R_INSN_SAT, "sat", "sat",
2e6dfccc 2313 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
d8ca5fae 2314 { 32, 32, 0xf0f0ffff }, 0x80600000,
c2009f4a 2315 "(set dr (if: WI condbit (if: WI (lt sr (const 0)) (const 2147483647) (const 2147483648)) sr))",
1294c286 2316 (PTR) & fmt_sat_ops[0],
fbc8134d 2317 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2318 },
2319/* end-sanitize-m32rx */
2320/* start-sanitize-m32rx */
2321/* pcmpbz $src2 */
2322 {
2323 { 1, 1, 1, 1 },
1294c286 2324 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2e6dfccc 2325 { { MNEM, ' ', OP (SRC2), 0 } },
0bf55db8 2326 { 16, 16, 0xfff0 }, 0x370,
c2009f4a 2327 "(set condbit (cond: BI ((eq (and src2 (const 255)) (const 0)) (const: BI 1)) ((eq (and src2 (const 65280)) (const 0)) (const: BI 1)) ((eq (and src2 (const 16711680)) (const 0)) (const: BI 1)) ((eq (and src2 (const 4278190080)) (const 0)) (const: BI 1)) (else (const: BI 0))))",
1294c286 2328 (PTR) & fmt_cmpz_ops[0],
c2009f4a 2329 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 2330 },
2331/* end-sanitize-m32rx */
2332/* start-sanitize-m32rx */
2333/* sadd */
2334 {
2335 { 1, 1, 1, 1 },
1294c286 2336 M32R_INSN_SADD, "sadd", "sadd",
2e6dfccc 2337 { { MNEM, 0 } },
0bf55db8 2338 { 16, 16, 0xffff }, 0x50e4,
c2009f4a 2339 "(set (reg h-accums 0) (add (sra (reg h-accums 1) (const 16)) (reg h-accums 0)))",
1294c286 2340 (PTR) & fmt_sadd_ops[0],
8d157f96 2341 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2342 },
7c26196f
DE		 2343/* end-sanitize-m32rx */
2344/* start-sanitize-m32rx */
2345/* macwu1 $src1,$src2 */
2346 {
2347 { 1, 1, 1, 1 },
1294c286 2348 M32R_INSN_MACWU1, "macwu1", "macwu1",
2e6dfccc 2349 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2350 { 16, 16, 0xf0f0 }, 0x50b0,
c2009f4a 2351 "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535))))) (const 8)) (const 8)))",
1294c286 2352 (PTR) & fmt_macwu1_ops[0],
8d157f96 2353 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2354 },
2355/* end-sanitize-m32rx */
2356/* start-sanitize-m32rx */
2357/* msblo $src1,$src2 */
2358 {
2359 { 1, 1, 1, 1 },
1294c286 2360 M32R_INSN_MSBLO, "msblo", "msblo",
2e6dfccc 2361 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2362 { 16, 16, 0xf0f0 }, 0x50d0,
c2009f4a 2363 "(set accum (sra: DI (sll: DI (sub accum (sra: DI (sll: DI (mul: DI (ext: DI (trunc: HI src1)) (ext: DI (trunc: HI src2))) (const 32)) (const 16))) (const 8)) (const 8)))",
1294c286 2364 (PTR) & fmt_machi_ops[0],
8d157f96 2365 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2366 },
2367/* end-sanitize-m32rx */
2368/* start-sanitize-m32rx */
2369/* mulwu1 $src1,$src2 */
2370 {
2371 { 1, 1, 1, 1 },
1294c286 2372 M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2e6dfccc 2373 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2374 { 16, 16, 0xf0f0 }, 0x50a0,
c2009f4a 2375 "(set (reg h-accums 1) (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535)))) (const 16)) (const 16)))",
1294c286 2376 (PTR) & fmt_mulwu1_ops[0],
8d157f96 2377 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2378 },
2379/* end-sanitize-m32rx */
2380/* start-sanitize-m32rx */
ab0bd049 2381/* maclh1 $src1,$src2 */
7c26196f
DE		 2382 {
2383 { 1, 1, 1, 1 },
1294c286 2384 M32R_INSN_MACLH1, "maclh1", "maclh1",
2e6dfccc 2385 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2386 { 16, 16, 0xf0f0 }, 0x50c0,
c2009f4a 2387 "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (sll: DI (ext: DI (mul: SI (ext: SI (trunc: HI src1)) (sra: SI src2 (const: SI 16)))) (const 16))) (const 8)) (const 8)))",
1294c286 2388 (PTR) & fmt_macwu1_ops[0],
8d157f96 2389 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2390 },
2391/* end-sanitize-m32rx */
2392/* start-sanitize-m32rx */
2393/* sc */
2394 {
2395 { 1, 1, 1, 1 },
1294c286 2396 M32R_INSN_SC, "sc", "sc",
2e6dfccc 2397 { { MNEM, 0 } },
0bf55db8 2398 { 16, 16, 0xffff }, 0x7401,
c2009f4a
DE		 2399 "(if condbit (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
2400))",
1294c286 2401 (PTR) & fmt_sc_ops[0],
fbc8134d 2402 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2403 },
2404/* end-sanitize-m32rx */
2405/* start-sanitize-m32rx */
2406/* snc */
2407 {
2408 { 1, 1, 1, 1 },
1294c286 2409 M32R_INSN_SNC, "snc", "snc",
2e6dfccc 2410 { { MNEM, 0 } },
0bf55db8 2411 { 16, 16, 0xffff }, 0x7501,
c2009f4a
DE		 2412 "(if (not condbit) (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
2413))",
1294c286 2414 (PTR) & fmt_sc_ops[0],
fbc8134d 2415 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2416 },
2417/* end-sanitize-m32rx */
9c03036a
DE		 2418};
2419
23cf992f 2420#undef A
0bf55db8
DE		 2421#undef MNEM
2422#undef OP
23cf992f 2423
c2009f4a 2424static const CGEN_INSN_TABLE insn_table =
853713a7 2425{
9c03036a 2426 & m32r_cgen_insn_table_entries[0],
23cf992f 2427 sizeof (CGEN_INSN),
7c26196f 2428 MAX_INSNS,
1294c286
DE		 2429 NULL
2430};
2431
2432/* Each non-simple macro entry points to an array of expansion possibilities. */
2433
2434#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2435#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2436#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2437
2438/* The macro instruction table. */
2439
2440static const CGEN_INSN macro_insn_table_entries[] =
2441{
2442/* bc $disp8 */
2443 {
2444 { 1, 1, 1, 1 },
2445 -1, "bc8r", "bc",
2e6dfccc 2446 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286 2447 { 16, 16, 0xff00 }, 0x7c00,
c2009f4a 2448 0,
1294c286
DE		 2449 (PTR) 0,
2450 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2451 },
2452/* bc $disp24 */
2453 {
2454 { 1, 1, 1, 1 },
2455 -1, "bc24r", "bc",
2e6dfccc 2456 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286 2457 { 32, 32, 0xff000000 }, 0xfc000000,
c2009f4a 2458 0,
1294c286
DE		 2459 (PTR) 0,
2460 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2461 },
2462/* bl $disp8 */
2463 {
2464 { 1, 1, 1, 1 },
2465 -1, "bl8r", "bl",
2e6dfccc 2466 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286 2467 { 16, 16, 0xff00 }, 0x7e00,
c2009f4a 2468 0,
1294c286
DE		 2469 (PTR) 0,
2470 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2471 },
2472/* bl $disp24 */
2473 {
2474 { 1, 1, 1, 1 },
2475 -1, "bl24r", "bl",
2e6dfccc 2476 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286 2477 { 32, 32, 0xff000000 }, 0xfe000000,
c2009f4a 2478 0,
1294c286
DE		 2479 (PTR) 0,
2480 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2481 },
2482/* bcl $disp8 */
2483 {
2484 { 1, 1, 1, 1 },
2485 -1, "bcl8r", "bcl",
2e6dfccc 2486 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286 2487 { 16, 16, 0xff00 }, 0x7800,
c2009f4a 2488 0,
1294c286
DE		 2489 (PTR) 0,
2490 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2491 },
2492/* bcl $disp24 */
2493 {
2494 { 1, 1, 1, 1 },
2495 -1, "bcl24r", "bcl",
2e6dfccc 2496 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286 2497 { 32, 32, 0xff000000 }, 0xf8000000,
c2009f4a 2498 0,
1294c286
DE		 2499 (PTR) 0,
2500 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2501 },
2502/* bnc $disp8 */
2503 {
2504 { 1, 1, 1, 1 },
2505 -1, "bnc8r", "bnc",
2e6dfccc 2506 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286 2507 { 16, 16, 0xff00 }, 0x7d00,
c2009f4a 2508 0,
1294c286
DE		 2509 (PTR) 0,
2510 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2511 },
2512/* bnc $disp24 */
2513 {
2514 { 1, 1, 1, 1 },
2515 -1, "bnc24r", "bnc",
2e6dfccc 2516 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286 2517 { 32, 32, 0xff000000 }, 0xfd000000,
c2009f4a 2518 0,
1294c286
DE		 2519 (PTR) 0,
2520 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2521 },
2522/* bra $disp8 */
2523 {
2524 { 1, 1, 1, 1 },
2525 -1, "bra8r", "bra",
2e6dfccc 2526 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286 2527 { 16, 16, 0xff00 }, 0x7f00,
c2009f4a 2528 0,
1294c286
DE		 2529 (PTR) 0,
2530 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2531 },
2532/* bra $disp24 */
2533 {
2534 { 1, 1, 1, 1 },
2535 -1, "bra24r", "bra",
2e6dfccc 2536 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286 2537 { 32, 32, 0xff000000 }, 0xff000000,
c2009f4a 2538 0,
1294c286
DE		 2539 (PTR) 0,
2540 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2541 },
2542/* bncl $disp8 */
2543 {
2544 { 1, 1, 1, 1 },
2545 -1, "bncl8r", "bncl",
2e6dfccc 2546 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286 2547 { 16, 16, 0xff00 }, 0x7900,
c2009f4a 2548 0,
1294c286
DE		 2549 (PTR) 0,
2550 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2551 },
2552/* bncl $disp24 */
2553 {
2554 { 1, 1, 1, 1 },
2555 -1, "bncl24r", "bncl",
2e6dfccc 2556 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286 2557 { 32, 32, 0xff000000 }, 0xf9000000,
c2009f4a 2558 0,
1294c286
DE		 2559 (PTR) 0,
2560 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2561 },
2562/* ld $dr,@($sr) */
2563 {
2564 { 1, 1, 1, 1 },
2565 -1, "ld-2", "ld",
2e6dfccc 2566 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286 2567 { 16, 16, 0xf0f0 }, 0x20c0,
c2009f4a 2568 0,
1294c286
DE		 2569 (PTR) 0,
2570 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2571 },
2572/* ld $dr,@($sr,$slo16) */
2573 {
2574 { 1, 1, 1, 1 },
2575 -1, "ld-d2", "ld",
2e6dfccc 2576 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286 2577 { 32, 32, 0xf0f00000 }, 0xa0c00000,
c2009f4a 2578 0,
1294c286
DE		 2579 (PTR) 0,
2580 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2581 },
2582/* ldb $dr,@($sr) */
2583 {
2584 { 1, 1, 1, 1 },
2585 -1, "ldb-2", "ldb",
2e6dfccc 2586 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286 2587 { 16, 16, 0xf0f0 }, 0x2080,
c2009f4a 2588 0,
1294c286
DE		 2589 (PTR) 0,
2590 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2591 },
2592/* ldb $dr,@($sr,$slo16) */
2593 {
2594 { 1, 1, 1, 1 },
2595 -1, "ldb-d2", "ldb",
2e6dfccc 2596 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286 2597 { 32, 32, 0xf0f00000 }, 0xa0800000,
c2009f4a 2598 0,
1294c286
DE		 2599 (PTR) 0,
2600 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2601 },
2602/* ldh $dr,@($sr) */
2603 {
2604 { 1, 1, 1, 1 },
2605 -1, "ldh-2", "ldh",
2e6dfccc 2606 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286 2607 { 16, 16, 0xf0f0 }, 0x20a0,
c2009f4a 2608 0,
1294c286
DE		 2609 (PTR) 0,
2610 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2611 },
2612/* ldh $dr,@($sr,$slo16) */
2613 {
2614 { 1, 1, 1, 1 },
2615 -1, "ldh-d2", "ldh",
2e6dfccc 2616 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286 2617 { 32, 32, 0xf0f00000 }, 0xa0a00000,
c2009f4a 2618 0,
1294c286
DE		 2619 (PTR) 0,
2620 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2621 },
2622/* ldub $dr,@($sr) */
2623 {
2624 { 1, 1, 1, 1 },
2625 -1, "ldub-2", "ldub",
2e6dfccc 2626 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286 2627 { 16, 16, 0xf0f0 }, 0x2090,
c2009f4a 2628 0,
1294c286
DE		 2629 (PTR) 0,
2630 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2631 },
2632/* ldub $dr,@($sr,$slo16) */
2633 {
2634 { 1, 1, 1, 1 },
2635 -1, "ldub-d2", "ldub",
2e6dfccc 2636 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286 2637 { 32, 32, 0xf0f00000 }, 0xa0900000,
c2009f4a 2638 0,
1294c286
DE		 2639 (PTR) 0,
2640 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2641 },
2642/* lduh $dr,@($sr) */
2643 {
2644 { 1, 1, 1, 1 },
2645 -1, "lduh-2", "lduh",
2e6dfccc 2646 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286 2647 { 16, 16, 0xf0f0 }, 0x20b0,
c2009f4a 2648 0,
1294c286
DE		 2649 (PTR) 0,
2650 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2651 },
2652/* lduh $dr,@($sr,$slo16) */
2653 {
2654 { 1, 1, 1, 1 },
2655 -1, "lduh-d2", "lduh",
2e6dfccc 2656 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286 2657 { 32, 32, 0xf0f00000 }, 0xa0b00000,
c2009f4a 2658 0,
1294c286
DE		 2659 (PTR) 0,
2660 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2661 },
2662/* pop $dr */
2663 {
2664 { 1, 1, 1, 1 },
2665 -1, "pop", "pop",
2e6dfccc 2666 { { MNEM, ' ', OP (DR), 0 } },
1294c286 2667 { 16, 16, 0xf0ff }, 0x20ef,
c2009f4a 2668 0,
1294c286
DE		 2669 (PTR) 0,
2670 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2671 },
2672/* ldi $dr,$simm8 */
2673 {
2674 { 1, 1, 1, 1 },
2675 -1, "ldi8a", "ldi",
2e6dfccc 2676 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1294c286 2677 { 16, 16, 0xf000 }, 0x6000,
c2009f4a 2678 0,
1294c286
DE		 2679 (PTR) 0,
2680 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2681 },
2682/* ldi $dr,$hash$slo16 */
2683 {
2684 { 1, 1, 1, 1 },
2685 -1, "ldi16a", "ldi",
2e6dfccc 2686 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1294c286 2687 { 32, 32, 0xf0ff0000 }, 0x90f00000,
c2009f4a 2688 0,
1294c286
DE		 2689 (PTR) 0,
2690 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2691 },
2692/* rac $accd */
2693 {
2694 { 1, 1, 1, 1 },
2695 -1, "rac-d", "rac",
2e6dfccc 2696 { { MNEM, ' ', OP (ACCD), 0 } },
1294c286 2697 { 16, 16, 0xf3ff }, 0x5090,
c2009f4a 2698 0,
1294c286
DE		 2699 (PTR) 0,
2700 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2701 },
2702/* rac $accd,$accs */
2703 {
2704 { 1, 1, 1, 1 },
2705 -1, "rac-ds", "rac",
2e6dfccc 2706 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1294c286 2707 { 16, 16, 0xf3f3 }, 0x5090,
c2009f4a 2708 0,
1294c286
DE		 2709 (PTR) 0,
2710 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2711 },
2712/* rach $accd */
2713 {
2714 { 1, 1, 1, 1 },
2715 -1, "rach-d", "rach",
2e6dfccc 2716 { { MNEM, ' ', OP (ACCD), 0 } },
1294c286 2717 { 16, 16, 0xf3ff }, 0x5080,
c2009f4a 2718 0,
1294c286
DE		 2719 (PTR) 0,
2720 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2721 },
2722/* rach $accd,$accs */
2723 {
2724 { 1, 1, 1, 1 },
2725 -1, "rach-ds", "rach",
2e6dfccc 2726 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1294c286 2727 { 16, 16, 0xf3f3 }, 0x5080,
c2009f4a 2728 0,
1294c286
DE		 2729 (PTR) 0,
2730 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2731 },
2732/* st $src1,@($src2) */
2733 {
2734 { 1, 1, 1, 1 },
2735 -1, "st-2", "st",
2e6dfccc 2736 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286 2737 { 16, 16, 0xf0f0 }, 0x2040,
c2009f4a 2738 0,
1294c286
DE		 2739 (PTR) 0,
2740 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2741 },
2742/* st $src1,@($src2,$slo16) */
2743 {
2744 { 1, 1, 1, 1 },
2745 -1, "st-d2", "st",
2e6dfccc 2746 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286 2747 { 32, 32, 0xf0f00000 }, 0xa0400000,
c2009f4a 2748 0,
1294c286
DE		 2749 (PTR) 0,
2750 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2751 },
2752/* stb $src1,@($src2) */
2753 {
2754 { 1, 1, 1, 1 },
2755 -1, "stb-2", "stb",
2e6dfccc 2756 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286 2757 { 16, 16, 0xf0f0 }, 0x2000,
c2009f4a 2758 0,
1294c286
DE		 2759 (PTR) 0,
2760 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2761 },
2762/* stb $src1,@($src2,$slo16) */
2763 {
2764 { 1, 1, 1, 1 },
2765 -1, "stb-d2", "stb",
2e6dfccc 2766 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286 2767 { 32, 32, 0xf0f00000 }, 0xa0000000,
c2009f4a 2768 0,
1294c286
DE		 2769 (PTR) 0,
2770 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2771 },
2772/* sth $src1,@($src2) */
2773 {
2774 { 1, 1, 1, 1 },
2775 -1, "sth-2", "sth",
2e6dfccc 2776 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286 2777 { 16, 16, 0xf0f0 }, 0x2020,
c2009f4a 2778 0,
1294c286
DE		 2779 (PTR) 0,
2780 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2781 },
2782/* sth $src1,@($src2,$slo16) */
2783 {
2784 { 1, 1, 1, 1 },
2785 -1, "sth-d2", "sth",
2e6dfccc 2786 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286 2787 { 32, 32, 0xf0f00000 }, 0xa0200000,
c2009f4a 2788 0,
1294c286
DE		 2789 (PTR) 0,
2790 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2791 },
2792/* push $src1 */
2793 {
2794 { 1, 1, 1, 1 },
2795 -1, "push", "push",
2e6dfccc 2796 { { MNEM, ' ', OP (SRC1), 0 } },
1294c286 2797 { 16, 16, 0xf0ff }, 0x207f,
c2009f4a 2798 0,
1294c286
DE		 2799 (PTR) 0,
2800 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2801 },
2802};
2803
2804#undef A
2805#undef MNEM
2806#undef OP
2807
c2009f4a 2808static const CGEN_INSN_TABLE macro_insn_table =
1294c286
DE		 2809{
2810 & macro_insn_table_entries[0],
2811 sizeof (CGEN_INSN),
2812 (sizeof (macro_insn_table_entries) /
2813 sizeof (macro_insn_table_entries[0])),
2814 NULL
9c03036a
DE		 2815};
2816
c2009f4a
DE		 2817static void
2818init_tables ()
2819{
2820}
1294c286
DE		 2821
2822/* Return non-zero if INSN is to be added to the hash table.
2823 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2824
2825static int
2826asm_hash_insn_p (insn)
2827 const CGEN_INSN * insn;
2828{
2829 return CGEN_ASM_HASH_P (insn);
2830}
2831
2832static int
2833dis_hash_insn_p (insn)
2834 const CGEN_INSN * insn;
2835{
2836 /* If building the hash table and the NO-DIS attribute is present,
2837 ignore. */
2838 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2839 return 0;
2840 return CGEN_DIS_HASH_P (insn);
2841}
2842
2843/* The result is the hash value of the insn.
2844 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
9c03036a 2845
1294c286
DE		 2846static unsigned int
2847asm_hash_insn (mnem)
2848 const char * mnem;
9c03036a 2849{
1294c286 2850 return CGEN_ASM_HASH (mnem);
9c03036a
DE		 2851}
2852
1294c286
DE		 2853static unsigned int
2854dis_hash_insn (buf, value)
5d07b6cf 2855 const char * buf;
9c03036a
DE		 2856 unsigned long value;
2857{
2858 return CGEN_DIS_HASH (buf, value);
2859}
2860
c2009f4a
DE		 2861/* Initialize an opcode table and return a descriptor.
2862 It's much like opening a file, and must be the first function called. */
2863
2864CGEN_OPCODE_DESC
2865m32r_cgen_opcode_open (mach, endian)
2866 int mach;
2867 enum cgen_endian endian;
5d07b6cf 2868{
c2009f4a
DE		 2869 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2870 static int init_p;
2871
2872 if (! init_p)
2873 {
2874 init_tables ();
2875 init_p = 1;
2876 }
2877
2878 memset (table, 0, sizeof (*table));
2879
2880 CGEN_OPCODE_MACH (table) = mach;
2881 CGEN_OPCODE_ENDIAN (table) = endian;
2882
2883 CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
2884
2885 CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
2886
2887 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2888
2889 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2890
2891 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2892 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2893 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2894
2895 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2896 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2897 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2898
2899 return (CGEN_OPCODE_DESC) table;
2900}
2901
2902/* Close an opcode table. */
9c03036a
DE		 2903
2904void
c2009f4a
DE		 2905m32r_cgen_opcode_close (desc)
2906 CGEN_OPCODE_DESC desc;
9c03036a 2907{
c2009f4a 2908 free (desc);
9c03036a
DE		 2909}
2910
fbc8134d
DE		 2911/* Getting values from cgen_fields is handled by a collection of functions.
2912 They are distinguished by the type of the VALUE argument they return.
2913 TODO: floating point, inlining support, remove cases where result type
2914 not appropriate. */
9c03036a 2915
fbc8134d
DE		 2916int
2917m32r_cgen_get_int_operand (opindex, fields)
9c03036a 2918 int opindex;
fbc8134d 2919 const CGEN_FIELDS * fields;
9c03036a 2920{
fbc8134d
DE		 2921 int value;
2922
9c03036a
DE		 2923 switch (opindex)
2924 {
23cf992f 2925 case M32R_OPERAND_SR :
fbc8134d 2926 value = fields->f_r2;
9c03036a 2927 break;
23cf992f 2928 case M32R_OPERAND_DR :
fbc8134d 2929 value = fields->f_r1;
9c03036a 2930 break;
23cf992f 2931 case M32R_OPERAND_SRC1 :
fbc8134d 2932 value = fields->f_r1;
9c03036a 2933 break;
23cf992f 2934 case M32R_OPERAND_SRC2 :
fbc8134d 2935 value = fields->f_r2;
9c03036a 2936 break;
23cf992f 2937 case M32R_OPERAND_SCR :
fbc8134d 2938 value = fields->f_r2;
9c03036a 2939 break;
23cf992f 2940 case M32R_OPERAND_DCR :
fbc8134d 2941 value = fields->f_r1;
9c03036a 2942 break;
23cf992f 2943 case M32R_OPERAND_SIMM8 :
fbc8134d 2944 value = fields->f_simm8;
9c03036a 2945 break;
23cf992f 2946 case M32R_OPERAND_SIMM16 :
fbc8134d 2947 value = fields->f_simm16;
9c03036a 2948 break;
23cf992f 2949 case M32R_OPERAND_UIMM4 :
fbc8134d 2950 value = fields->f_uimm4;
9c03036a 2951 break;
23cf992f 2952 case M32R_OPERAND_UIMM5 :
fbc8134d 2953 value = fields->f_uimm5;
9c03036a 2954 break;
23cf992f 2955 case M32R_OPERAND_UIMM16 :
fbc8134d 2956 value = fields->f_uimm16;
23cf992f 2957 break;
ab0bd049
DE		 2958/* start-sanitize-m32rx */
2959 case M32R_OPERAND_IMM1 :
fbc8134d 2960 value = fields->f_imm1;
ab0bd049
DE		 2961 break;
2962/* end-sanitize-m32rx */
2963/* start-sanitize-m32rx */
2964 case M32R_OPERAND_ACCD :
fbc8134d 2965 value = fields->f_accd;
ab0bd049
DE		 2966 break;
2967/* end-sanitize-m32rx */
7c26196f
DE		 2968/* start-sanitize-m32rx */
2969 case M32R_OPERAND_ACCS :
fbc8134d 2970 value = fields->f_accs;
7c26196f
DE		 2971 break;
2972/* end-sanitize-m32rx */
2973/* start-sanitize-m32rx */
2974 case M32R_OPERAND_ACC :
fbc8134d 2975 value = fields->f_acc;
7c26196f
DE		 2976 break;
2977/* end-sanitize-m32rx */
a6cefe4f 2978 case M32R_OPERAND_HASH :
fbc8134d 2979 value = fields->f_nil;
a6cefe4f 2980 break;
23cf992f 2981 case M32R_OPERAND_HI16 :
fbc8134d 2982 value = fields->f_hi16;
9c03036a 2983 break;
23cf992f 2984 case M32R_OPERAND_SLO16 :
fbc8134d 2985 value = fields->f_simm16;
9c03036a 2986 break;
23cf992f 2987 case M32R_OPERAND_ULO16 :
fbc8134d 2988 value = fields->f_uimm16;
9c03036a 2989 break;
23cf992f 2990 case M32R_OPERAND_UIMM24 :
fbc8134d 2991 value = fields->f_uimm24;
9c03036a 2992 break;
23cf992f 2993 case M32R_OPERAND_DISP8 :
fbc8134d 2994 value = fields->f_disp8;
9c03036a 2995 break;
23cf992f 2996 case M32R_OPERAND_DISP16 :
fbc8134d 2997 value = fields->f_disp16;
9c03036a 2998 break;
23cf992f 2999 case M32R_OPERAND_DISP24 :
fbc8134d 3000 value = fields->f_disp24;
9c03036a
DE		 3001 break;
3002
3003 default :
fbc8134d
DE		 3004 /* xgettext:c-format */
3005 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
9c03036a
DE		 3006 opindex);
3007 abort ();
3008 }
9c03036a 3009
fbc8134d
DE		 3010 return value;
3011}
9c03036a 3012
fbc8134d
DE		 3013bfd_vma
3014m32r_cgen_get_vma_operand (opindex, fields)
5d07b6cf 3015 int opindex;
853713a7 3016 const CGEN_FIELDS * fields;
9c03036a 3017{
fbc8134d 3018 bfd_vma value;
9c03036a
DE		 3019
3020 switch (opindex)
3021 {
23cf992f 3022 case M32R_OPERAND_SR :
9c03036a
DE		 3023 value = fields->f_r2;
3024 break;
23cf992f 3025 case M32R_OPERAND_DR :
9c03036a
DE		 3026 value = fields->f_r1;
3027 break;
23cf992f 3028 case M32R_OPERAND_SRC1 :
9c03036a
DE		 3029 value = fields->f_r1;
3030 break;
23cf992f 3031 case M32R_OPERAND_SRC2 :
9c03036a
DE		 3032 value = fields->f_r2;
3033 break;
23cf992f 3034 case M32R_OPERAND_SCR :
9c03036a
DE		 3035 value = fields->f_r2;
3036 break;
23cf992f 3037 case M32R_OPERAND_DCR :
9c03036a
DE		 3038 value = fields->f_r1;
3039 break;
23cf992f 3040 case M32R_OPERAND_SIMM8 :
9c03036a
DE		 3041 value = fields->f_simm8;
3042 break;
23cf992f 3043 case M32R_OPERAND_SIMM16 :
9c03036a
DE		 3044 value = fields->f_simm16;
3045 break;
23cf992f 3046 case M32R_OPERAND_UIMM4 :
9c03036a
DE		 3047 value = fields->f_uimm4;
3048 break;
23cf992f 3049 case M32R_OPERAND_UIMM5 :
9c03036a
DE		 3050 value = fields->f_uimm5;
3051 break;
23cf992f 3052 case M32R_OPERAND_UIMM16 :
9c03036a
DE		 3053 value = fields->f_uimm16;
3054 break;
ab0bd049
DE		 3055/* start-sanitize-m32rx */
3056 case M32R_OPERAND_IMM1 :
3057 value = fields->f_imm1;
3058 break;
3059/* end-sanitize-m32rx */
3060/* start-sanitize-m32rx */
3061 case M32R_OPERAND_ACCD :
3062 value = fields->f_accd;
3063 break;
3064/* end-sanitize-m32rx */
7c26196f
DE		 3065/* start-sanitize-m32rx */
3066 case M32R_OPERAND_ACCS :
3067 value = fields->f_accs;
3068 break;
3069/* end-sanitize-m32rx */
3070/* start-sanitize-m32rx */
3071 case M32R_OPERAND_ACC :
3072 value = fields->f_acc;
3073 break;
3074/* end-sanitize-m32rx */
a6cefe4f
DE		 3075 case M32R_OPERAND_HASH :
3076 value = fields->f_nil;
3077 break;
23cf992f 3078 case M32R_OPERAND_HI16 :
9c03036a
DE		 3079 value = fields->f_hi16;
3080 break;
23cf992f 3081 case M32R_OPERAND_SLO16 :
9c03036a
DE		 3082 value = fields->f_simm16;
3083 break;
23cf992f 3084 case M32R_OPERAND_ULO16 :
9c03036a
DE		 3085 value = fields->f_uimm16;
3086 break;
23cf992f 3087 case M32R_OPERAND_UIMM24 :
9c03036a
DE		 3088 value = fields->f_uimm24;
3089 break;
23cf992f 3090 case M32R_OPERAND_DISP8 :
9c03036a
DE		 3091 value = fields->f_disp8;
3092 break;
23cf992f 3093 case M32R_OPERAND_DISP16 :
9c03036a
DE		 3094 value = fields->f_disp16;
3095 break;
23cf992f 3096 case M32R_OPERAND_DISP24 :
9c03036a
DE		 3097 value = fields->f_disp24;
3098 break;
3099
3100 default :
fbc8134d
DE		 3101 /* xgettext:c-format */
3102 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
9c03036a
DE		 3103 opindex);
3104 abort ();
3105 }
3106
3107 return value;
3108}
3109
fbc8134d
DE		 3110/* Stuffing values in cgen_fields is handled by a collection of functions.
3111 They are distinguished by the type of the VALUE argument they accept.
3112 TODO: floating point, inlining support, remove cases where argument type
3113 not appropriate. */
3114
3115void
3116m32r_cgen_set_int_operand (opindex, fields, value)
3117 int opindex;
3118 CGEN_FIELDS * fields;
3119 int value;
3120{
3121 switch (opindex)
3122 {
3123 case M32R_OPERAND_SR :
3124 fields->f_r2 = value;
3125 break;
3126 case M32R_OPERAND_DR :
3127 fields->f_r1 = value;
3128 break;
3129 case M32R_OPERAND_SRC1 :
3130 fields->f_r1 = value;
3131 break;
3132 case M32R_OPERAND_SRC2 :
3133 fields->f_r2 = value;
3134 break;
3135 case M32R_OPERAND_SCR :
3136 fields->f_r2 = value;
3137 break;
3138 case M32R_OPERAND_DCR :
3139 fields->f_r1 = value;
3140 break;
3141 case M32R_OPERAND_SIMM8 :
3142 fields->f_simm8 = value;
3143 break;
3144 case M32R_OPERAND_SIMM16 :
3145 fields->f_simm16 = value;
3146 break;
3147 case M32R_OPERAND_UIMM4 :
3148 fields->f_uimm4 = value;
3149 break;
3150 case M32R_OPERAND_UIMM5 :
3151 fields->f_uimm5 = value;
3152 break;
3153 case M32R_OPERAND_UIMM16 :
3154 fields->f_uimm16 = value;
3155 break;
3156/* start-sanitize-m32rx */
3157 case M32R_OPERAND_IMM1 :
3158 fields->f_imm1 = value;
3159 break;
3160/* end-sanitize-m32rx */
3161/* start-sanitize-m32rx */
3162 case M32R_OPERAND_ACCD :
3163 fields->f_accd = value;
3164 break;
3165/* end-sanitize-m32rx */
3166/* start-sanitize-m32rx */
3167 case M32R_OPERAND_ACCS :
3168 fields->f_accs = value;
3169 break;
3170/* end-sanitize-m32rx */
3171/* start-sanitize-m32rx */
3172 case M32R_OPERAND_ACC :
3173 fields->f_acc = value;
3174 break;
3175/* end-sanitize-m32rx */
3176 case M32R_OPERAND_HASH :
3177 fields->f_nil = value;
3178 break;
3179 case M32R_OPERAND_HI16 :
3180 fields->f_hi16 = value;
3181 break;
3182 case M32R_OPERAND_SLO16 :
3183 fields->f_simm16 = value;
3184 break;
3185 case M32R_OPERAND_ULO16 :
3186 fields->f_uimm16 = value;
3187 break;
3188 case M32R_OPERAND_UIMM24 :
3189 fields->f_uimm24 = value;
3190 break;
3191 case M32R_OPERAND_DISP8 :
3192 fields->f_disp8 = value;
3193 break;
3194 case M32R_OPERAND_DISP16 :
3195 fields->f_disp16 = value;
3196 break;
3197 case M32R_OPERAND_DISP24 :
3198 fields->f_disp24 = value;
3199 break;
3200
3201 default :
3202 /* xgettext:c-format */
3203 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3204 opindex);
3205 abort ();
3206 }
3207}
3208
3209void
3210m32r_cgen_set_vma_operand (opindex, fields, value)
3211 int opindex;
3212 CGEN_FIELDS * fields;
3213 bfd_vma value;
3214{
3215 switch (opindex)
3216 {
3217 case M32R_OPERAND_SR :
3218 fields->f_r2 = value;
3219 break;
3220 case M32R_OPERAND_DR :
3221 fields->f_r1 = value;
3222 break;
3223 case M32R_OPERAND_SRC1 :
3224 fields->f_r1 = value;
3225 break;
3226 case M32R_OPERAND_SRC2 :
3227 fields->f_r2 = value;
3228 break;
3229 case M32R_OPERAND_SCR :
3230 fields->f_r2 = value;
3231 break;
3232 case M32R_OPERAND_DCR :
3233 fields->f_r1 = value;
3234 break;
3235 case M32R_OPERAND_SIMM8 :
3236 fields->f_simm8 = value;
3237 break;
3238 case M32R_OPERAND_SIMM16 :
3239 fields->f_simm16 = value;
3240 break;
3241 case M32R_OPERAND_UIMM4 :
3242 fields->f_uimm4 = value;
3243 break;
3244 case M32R_OPERAND_UIMM5 :
3245 fields->f_uimm5 = value;
3246 break;
3247 case M32R_OPERAND_UIMM16 :
3248 fields->f_uimm16 = value;
3249 break;
3250/* start-sanitize-m32rx */
3251 case M32R_OPERAND_IMM1 :
3252 fields->f_imm1 = value;
3253 break;
3254/* end-sanitize-m32rx */
3255/* start-sanitize-m32rx */
3256 case M32R_OPERAND_ACCD :
3257 fields->f_accd = value;
3258 break;
3259/* end-sanitize-m32rx */
3260/* start-sanitize-m32rx */
3261 case M32R_OPERAND_ACCS :
3262 fields->f_accs = value;
3263 break;
3264/* end-sanitize-m32rx */
3265/* start-sanitize-m32rx */
3266 case M32R_OPERAND_ACC :
3267 fields->f_acc = value;
3268 break;
3269/* end-sanitize-m32rx */
3270 case M32R_OPERAND_HASH :
3271 fields->f_nil = value;
3272 break;
3273 case M32R_OPERAND_HI16 :
3274 fields->f_hi16 = value;
3275 break;
3276 case M32R_OPERAND_SLO16 :
3277 fields->f_simm16 = value;
3278 break;
3279 case M32R_OPERAND_ULO16 :
3280 fields->f_uimm16 = value;
3281 break;
3282 case M32R_OPERAND_UIMM24 :
3283 fields->f_uimm24 = value;
3284 break;
3285 case M32R_OPERAND_DISP8 :
3286 fields->f_disp8 = value;
3287 break;
3288 case M32R_OPERAND_DISP16 :
3289 fields->f_disp16 = value;
3290 break;
3291 case M32R_OPERAND_DISP24 :
3292 fields->f_disp24 = value;
3293 break;
3294
3295 default :
3296 /* xgettext:c-format */
3297 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3298 opindex);
3299 abort ();
3300 }
3301}
3302
GDB Binutils - Deliverables
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