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* cgen-opc.in (@arch@_cgen_lookup_insn): Update call to
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
CommitLineData
ab0bd049
DE		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
9c03036a 3
fbc8134d 4THIS FILE IS USED TO GENERATE m32r-opc.c.
7c26196f 5
ab0bd049 6Copyright (C) 1998 Free Software Foundation, Inc.
9c03036a 7
ab0bd049 8This file is part of the GNU Binutils and GDB, the GNU debugger.
9c03036a
DE		 9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
ab0bd049 20You should have received a copy of the GNU General Public License
fbc8134d
DE		 21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
9c03036a 23
23cf992f 24#include "sysdep.h"
9c03036a
DE		 25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
ab0bd049 29#include "symcat.h"
9c03036a 30#include "m32r-opc.h"
fbc8134d 31#include "opintl.h"
9c03036a 32
ab0bd049 33/* Look up instruction INSN_VALUE and extract its fields.
1294c286 34 INSN, if non-null, is the insn table entry.
ab0bd049
DE		 35 Otherwise INSN_VALUE is examined to compute it.
36 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
1294c286
DE		 37 0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
38 If INSN != NULL, LENGTH must be valid.
390bd87d 39 ALIAS_P is non-zero if alias insns are to be included in the search.
1294c286 40
ab0bd049
DE		 41 The result a pointer to the insn table entry, or NULL if the instruction
42 wasn't recognized. */
43
44const CGEN_INSN *
390bd87d 45m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
ab0bd049
DE		 46 const CGEN_INSN *insn;
47 cgen_insn_t insn_value;
48 int length;
49 CGEN_FIELDS *fields;
1294c286 50 int alias_p;
ab0bd049 51{
390bd87d 52 char buf[16];
ab0bd049
DE		 53
54 if (!insn)
55 {
56 const CGEN_INSN_LIST *insn_list;
57
58#ifdef CGEN_INT_INSN
59 switch (length)
60 {
61 case 8:
62 buf[0] = insn_value;
63 break;
64 case 16:
65 if (cgen_current_endian == CGEN_ENDIAN_BIG)
66 bfd_putb16 (insn_value, buf);
67 else
68 bfd_putl16 (insn_value, buf);
69 break;
70 case 32:
71 if (cgen_current_endian == CGEN_ENDIAN_BIG)
72 bfd_putb32 (insn_value, buf);
73 else
74 bfd_putl32 (insn_value, buf);
75 break;
76 default:
77 abort ();
78 }
79#else
80 abort (); /* FIXME: unfinished */
81#endif
82
83 /* The instructions are stored in hash lists.
84 Pick the first one and keep trying until we find the right one. */
85
86 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
87 while (insn_list != NULL)
88 {
89 insn = insn_list->insn;
90
390bd87d
DE		 91 if (alias_p
92 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
ab0bd049 93 {
390bd87d
DE		 94 /* Basic bit mask must be correct. */
95 /* ??? May wish to allow target to defer this check until the
96 extract handler. */
97 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
98 {
fbc8134d 99 /* ??? 0 is passed for `pc' */
1294c286 100 int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
fbc8134d
DE		 101 insn_value, fields,
102 (bfd_vma) 0);
1294c286
DE		 103 if (elength > 0)
104 {
105 /* sanity check */
106 if (length != 0 && length != elength)
107 abort ();
108 return insn;
109 }
390bd87d 110 }
ab0bd049
DE		 111 }
112
113 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
114 }
115 }
116 else
117 {
390bd87d
DE		 118 /* Sanity check: can't pass an alias insn if ! alias_p. */
119 if (! alias_p
120 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
121 abort ();
1294c286
DE		 122 /* Sanity check: length must be correct. */
123 if (length != CGEN_INSN_BITSIZE (insn))
124 abort ();
390bd87d 125
fbc8134d
DE		 126 /* ??? 0 is passed for `pc' */
127 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields,
128 (bfd_vma) 0);
1294c286
DE		 129 /* Sanity check: must succeed.
130 Could relax this later if it ever proves useful. */
131 if (length == 0)
132 abort ();
133 return insn;
ab0bd049
DE		 134 }
135
136 return NULL;
137}
138
1294c286 139/* Fill in the operand instances used by INSN whose operands are FIELDS.
b02643b5 140 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
1294c286 141 in. */
ab0bd049 142
1294c286
DE		 143void
144m32r_cgen_get_insn_operands (insn, fields, indices)
145 const CGEN_INSN * insn;
146 const CGEN_FIELDS * fields;
ab0bd049
DE		 147 int *indices;
148{
ab0bd049
DE		 149 const CGEN_OPERAND_INSTANCE *opinst;
150 int i;
151
ab0bd049 152 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
b2f18612
DE		 153 opinst != NULL
154 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
ab0bd049
DE		 155 ++i, ++opinst)
156 {
157 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
158 if (op == NULL)
159 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
160 else
fbc8134d 161 indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), fields);
ab0bd049 162 }
1294c286 163}
ab0bd049 164
1294c286
DE		 165/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
166 isn't known.
167 The INSN, INSN_VALUE, and LENGTH arguments are passed to
168 m32r_cgen_lookup_insn unchanged.
169
170 The result is the insn table entry or NULL if the instruction wasn't
171 recognized. */
172
173const CGEN_INSN *
174m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
175 const CGEN_INSN *insn;
176 cgen_insn_t insn_value;
177 int length;
178 int *indices;
179{
180 CGEN_FIELDS fields;
181
182 /* Pass non-zero for ALIAS_P only if INSN != NULL.
183 If INSN == NULL, we want a real insn. */
184 insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields,
185 insn != NULL);
186 if (! insn)
187 return NULL;
188
189 m32r_cgen_get_insn_operands (insn, &fields, indices);
ab0bd049
DE		 190 return insn;
191}
23cf992f
NC		 192/* Attributes. */
193
7c26196f 194static const CGEN_ATTR_ENTRY MACH_attr[] =
5d07b6cf
DE		 195{
196 { "m32r", MACH_M32R },
7c26196f
DE		 197/* start-sanitize-m32rx */
198 { "m32rx", MACH_M32RX },
199/* end-sanitize-m32rx */
200 { "max", MACH_MAX },
201 { 0, 0 }
202};
203
204/* start-sanitize-m32rx */
205static const CGEN_ATTR_ENTRY PIPE_attr[] =
206{
207 { "NONE", PIPE_NONE },
208 { "O", PIPE_O },
209 { "S", PIPE_S },
210 { "OS", PIPE_OS },
23cf992f
NC		 211 { 0, 0 }
212};
213
7c26196f
DE		 214/* end-sanitize-m32rx */
215const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
5d07b6cf
DE		 216{
217 { "ABS-ADDR", NULL },
23cf992f 218 { "FAKE", NULL },
a6cefe4f 219 { "HASH-PREFIX", NULL },
23cf992f 220 { "NEGATIVE", NULL },
23cf992f
NC		 221 { "PCREL-ADDR", NULL },
222 { "RELAX", NULL },
223 { "RELOC", NULL },
224 { "SIGN-OPT", NULL },
225 { "UNSIGNED", NULL },
226 { 0, 0 }
227};
228
7c26196f 229const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
5d07b6cf 230{
7c26196f
DE		 231 { "MACH", & MACH_attr[0] },
232/* start-sanitize-m32rx */
233 { "PIPE", & PIPE_attr[0] },
234/* end-sanitize-m32rx */
5d07b6cf 235 { "ALIAS", NULL },
23cf992f
NC		 236 { "COND-CTI", NULL },
237 { "FILL-SLOT", NULL },
1294c286 238 { "NO-DIS", NULL },
7c26196f 239 { "PARALLEL", NULL },
23cf992f 240 { "RELAX", NULL },
23cf992f 241 { "RELAXABLE", NULL },
fbc8134d 242 { "SPECIAL", NULL },
23cf992f
NC		 243 { "UNCOND-CTI", NULL },
244 { 0, 0 }
9c03036a
DE		 245};
246
853713a7 247CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
5d07b6cf
DE		 248{
249 { "fp", 13 },
9c03036a
DE		 250 { "lr", 14 },
251 { "sp", 15 },
252 { "r0", 0 },
253 { "r1", 1 },
254 { "r2", 2 },
255 { "r3", 3 },
256 { "r4", 4 },
257 { "r5", 5 },
258 { "r6", 6 },
259 { "r7", 7 },
260 { "r8", 8 },
261 { "r9", 9 },
262 { "r10", 10 },
263 { "r11", 11 },
264 { "r12", 12 },
265 { "r13", 13 },
266 { "r14", 14 },
267 { "r15", 15 }
268};
269
853713a7 270CGEN_KEYWORD m32r_cgen_opval_h_gr =
5d07b6cf
DE		 271{
272 & m32r_cgen_opval_h_gr_entries[0],
9c03036a
DE		 273 19
274};
275
853713a7 276CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
5d07b6cf
DE		 277{
278 { "psw", 0 },
9c03036a
DE		 279 { "cbr", 1 },
280 { "spi", 2 },
281 { "spu", 3 },
282 { "bpc", 6 },
283 { "cr0", 0 },
284 { "cr1", 1 },
285 { "cr2", 2 },
286 { "cr3", 3 },
287 { "cr4", 4 },
288 { "cr5", 5 },
b2ddf0c4
NC		 289 { "cr6", 6 },
290 { "cr7", 7 },
291 { "cr8", 8 },
292 { "cr9", 9 },
293 { "cr10", 10 },
294 { "cr11", 11 },
295 { "cr12", 12 },
296 { "cr13", 13 },
297 { "cr14", 14 },
298 { "cr15", 15 }
9c03036a
DE		 299};
300
853713a7 301CGEN_KEYWORD m32r_cgen_opval_h_cr =
5d07b6cf
DE		 302{
303 & m32r_cgen_opval_h_cr_entries[0],
b2ddf0c4 304 21
9c03036a
DE		 305};
306
7c26196f
DE		 307/* start-sanitize-m32rx */
308CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
309{
310 { "a0", 0 },
311 { "a1", 1 }
312};
23cf992f 313
7c26196f 314CGEN_KEYWORD m32r_cgen_opval_h_accums =
5d07b6cf 315{
7c26196f
DE		 316 & m32r_cgen_opval_h_accums_entries[0],
317 2
9c03036a
DE		 318};
319
7c26196f
DE		 320/* end-sanitize-m32rx */
321
ab0bd049
DE		 322/* The hardware table. */
323
324#define HW_ENT(n) m32r_cgen_hw_entries[n]
325static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
7c26196f 326{
ab0bd049
DE		 327 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
328 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
329 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
330 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
331 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
332 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
333 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
334 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
335 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
336 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
337 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
338 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
7c26196f 339/* start-sanitize-m32rx */
ab0bd049 340 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
7c26196f 341/* end-sanitize-m32rx */
ab0bd049
DE		 342 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
343 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
344 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
345 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
346 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
347 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
348 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
8d157f96 349 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
7c26196f
DE		 350 { 0 }
351};
9c03036a 352
ab0bd049
DE		 353/* The operand table. */
354
8d157f96
DE		 355#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
356#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
0bf55db8 357
7c26196f 358const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
9c03036a 359{
23cf992f 360/* pc: program counter */
ab0bd049 361 { "pc", & HW_ENT (HW_H_PC), 0, 0,
fbc8134d 362 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
9c03036a 363/* sr: source register */
ab0bd049
DE		 364 { "sr", & HW_ENT (HW_H_GR), 12, 4,
365 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 366/* dr: destination register */
ab0bd049
DE		 367 { "dr", & HW_ENT (HW_H_GR), 4, 4,
368 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 369/* src1: source register 1 */
ab0bd049
DE		 370 { "src1", & HW_ENT (HW_H_GR), 4, 4,
371 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 372/* src2: source register 2 */
ab0bd049
DE		 373 { "src2", & HW_ENT (HW_H_GR), 12, 4,
374 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 375/* scr: source control register */
ab0bd049
DE		 376 { "scr", & HW_ENT (HW_H_CR), 12, 4,
377 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 378/* dcr: destination control register */
ab0bd049
DE		 379 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
380 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 381/* simm8: 8 bit signed immediate */
ab0bd049 382 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
a6cefe4f 383 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 384/* simm16: 16 bit signed immediate */
ab0bd049 385 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
a6cefe4f 386 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 387/* uimm4: 4 bit trap number */
ab0bd049 388 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
a6cefe4f 389 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 390/* uimm5: 5 bit shift count */
ab0bd049 391 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
a6cefe4f 392 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 393/* uimm16: 16 bit unsigned immediate */
ab0bd049 394 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
a6cefe4f 395 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 396/* start-sanitize-m32rx */
397/* imm1: 1 bit immediate */
398 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
a6cefe4f 399 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 400/* end-sanitize-m32rx */
401/* start-sanitize-m32rx */
402/* accd: accumulator destination register */
403 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
404 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
405/* end-sanitize-m32rx */
7c26196f 406/* start-sanitize-m32rx */
ab0bd049
DE		 407/* accs: accumulator source register */
408 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
409 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f
DE		 410/* end-sanitize-m32rx */
411/* start-sanitize-m32rx */
412/* acc: accumulator reg (d) */
ab0bd049
DE		 413 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
414 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f 415/* end-sanitize-m32rx */
a6cefe4f
DE		 416/* hash: # prefix */
417 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
418 { 0, 0, { 0 } } },
9c03036a 419/* hi16: high 16 bit immediate, sign optional */
ab0bd049
DE		 420 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
421 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 422/* slo16: 16 bit signed immediate, for low() */
ab0bd049
DE		 423 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
424 { 0, 0, { 0 } } },
9c03036a 425/* ulo16: 16 bit unsigned immediate, for low() */
ab0bd049
DE		 426 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
427 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 428/* uimm24: 24 bit address */
ab0bd049 429 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
a6cefe4f 430 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 431/* disp8: 8 bit displacement */
ab0bd049
DE		 432 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
433 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 434/* disp16: 16 bit displacement */
ab0bd049
DE		 435 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
436 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 437/* disp24: 24 bit displacement */
ab0bd049
DE		 438 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
439 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
23cf992f 440/* condbit: condition bit */
ab0bd049
DE		 441 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
442 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f 443/* accum: accumulator */
ab0bd049
DE		 444 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
445 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f
NC		 446};
447
ab0bd049
DE		 448/* Operand references. */
449
7caa7497
DE		 450#define INPUT CGEN_OPERAND_INSTANCE_INPUT
451#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
452
1294c286 453static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
7caa7497
DE		 454 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
455 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
456 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 457 { 0 }
458};
459
1294c286 460static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
7caa7497 461 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 462 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 463 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 464 { 0 }
465};
466
1294c286 467static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
7caa7497
DE		 468 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
469 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
470 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 471 { 0 }
472};
473
1294c286 474static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
7caa7497
DE		 475 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
476 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
477 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 478 { 0 }
479};
480
1294c286 481static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
7caa7497
DE		 482 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
483 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
484 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 485 { 0 }
486};
487
1294c286 488static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
390bd87d
DE		 489 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
490 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
390bd87d 491 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 492 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 493 { 0 }
494};
495
1294c286 496static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
7caa7497 497 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 498 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
7caa7497 499 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 500 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 501 { 0 }
502};
503
1294c286 504static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
7caa7497
DE		 505 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
506 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 507 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
7caa7497 508 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
fbc8134d 509 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 510 { 0 }
511};
512
1294c286 513static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
390bd87d 514 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
fbc8134d 515 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
8d157f96 516 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 517 { 0 }
518};
519
1294c286 520static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
390bd87d 521 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
fbc8134d 522 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
8d157f96 523 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 524 { 0 }
525};
526
1294c286 527static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
7caa7497
DE		 528 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
529 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 530 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
8d157f96 531 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 532 { 0 }
533};
534
1294c286 535static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
7caa7497 536 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 537 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
8d157f96 538 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 539 { 0 }
540};
541
1294c286 542static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
390bd87d 543 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 544 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
7caa7497 545 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 546 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 547 { 0 }
548};
549
1294c286 550static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
390bd87d 551 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 552 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
7caa7497 553 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 554 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 555 { 0 }
556};
557
b2ddf0c4 558/* start-sanitize-m32rx */
1294c286 559static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
390bd87d 560 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d 561 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 562 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
7caa7497 563 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 564 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 565 { 0 }
566};
567
b2ddf0c4
NC		 568/* end-sanitize-m32rx */
569/* start-sanitize-m32rx */
1294c286 570static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
390bd87d 571 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
390bd87d 572 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d 573 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
7caa7497 574 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 575 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 576 { 0 }
577};
578
b2ddf0c4 579/* end-sanitize-m32rx */
1294c286 580static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
fbc8134d 581 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
8d157f96 582 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 583 { 0 }
584};
585
1294c286 586static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
fbc8134d 587 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
8d157f96 588 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 589 { 0 }
590};
591
1294c286 592static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
7caa7497
DE		 593 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
594 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 595 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 596 { 0 }
597};
598
1294c286 599static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
7caa7497 600 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 601 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
390bd87d 602 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 603 { 0 }
604};
605
b2ddf0c4 606/* start-sanitize-m32rx */
1294c286 607static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
7caa7497 608 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 609 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 610 { 0 }
611};
612
b2ddf0c4 613/* end-sanitize-m32rx */
1294c286 614static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
7caa7497
DE		 615 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
616 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
617 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 618 { 0 }
619};
620
b2ddf0c4 621/* start-sanitize-m32rx */
1294c286 622static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
390bd87d 623 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
7caa7497 624 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
8d157f96 625 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 626 { 0 }
627};
628
b2ddf0c4 629/* end-sanitize-m32rx */
1294c286 630static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
390bd87d 631 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
7caa7497
DE		 632 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
633 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
fbc8134d 634 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 635 { 0 }
636};
637
1294c286 638static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
7caa7497 639 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
8d157f96 640 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 641 { 0 }
642};
643
1294c286 644static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
7caa7497 645 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
fbc8134d 646 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 647 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 648 { 0 }
649};
650
1294c286 651static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
7caa7497 652 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
7caa7497 653 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 654 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 655 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 656 { 0 }
657};
658
1294c286 659static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
7caa7497 660 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
fbc8134d 661 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 662 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 663 { 0 }
664};
665
1294c286 666static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
7caa7497 667 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
7caa7497 668 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 669 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 670 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 671 { 0 }
672};
673
1294c286 674static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
7caa7497 675 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
fbc8134d 676 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
7caa7497 677 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 678 { 0 }
679};
680
1294c286 681static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
7caa7497 682 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
7caa7497 683 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 684 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
7caa7497 685 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 686 { 0 }
687};
688
1294c286 689static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
390bd87d
DE		 690 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
691 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
692 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
693 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
694 { 0 }
695};
696
1294c286 697static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
fbc8134d 698 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
7caa7497 699 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 700 { 0 }
701};
702
1294c286 703static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
7caa7497
DE		 704 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
705 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 706 { 0 }
707};
708
1294c286 709static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
7caa7497
DE		 710 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
711 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 712 { 0 }
713};
714
1294c286 715static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
8d157f96 716 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
fbc8134d 717 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
8d157f96 718 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
fbc8134d 719 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
390bd87d
DE		 720 { 0 }
721};
722
1294c286 723static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
390bd87d 724 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497
DE		 725 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
726 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d 727 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 728 { 0 }
729};
730
b2ddf0c4 731/* start-sanitize-m32rx */
1294c286 732static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
7caa7497
DE		 733 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
734 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
735 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
736 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 737 { 0 }
738};
739
b2ddf0c4 740/* end-sanitize-m32rx */
1294c286 741static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
390bd87d
DE		 742 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
743 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
744 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
745 { 0 }
746};
747
b2ddf0c4 748/* start-sanitize-m32rx */
1294c286 749static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
7caa7497
DE		 750 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
751 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
752 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 753 { 0 }
754};
755
b2ddf0c4 756/* end-sanitize-m32rx */
1294c286 757static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
7caa7497
DE		 758 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
759 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 760 { 0 }
761};
762
1294c286 763static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
390bd87d 764 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497 765 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 766 { 0 }
767};
768
b2ddf0c4 769/* start-sanitize-m32rx */
1294c286 770static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
7caa7497
DE		 771 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
772 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 773 { 0 }
774};
775
b2ddf0c4 776/* end-sanitize-m32rx */
1294c286 777static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
b02643b5 778 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
7caa7497 779 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 780 { 0 }
781};
782
1294c286 783static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
390bd87d 784 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
7caa7497 785 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d 786 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 787 { 0 }
788};
789
b2ddf0c4 790/* start-sanitize-m32rx */
1294c286 791static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
7caa7497
DE		 792 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
793 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
794 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
ab0bd049
DE		 795 { 0 }
796};
797
b2ddf0c4 798/* end-sanitize-m32rx */
1294c286 799static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
7caa7497 800 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
b02643b5 801 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
ab0bd049
DE		 802 { 0 }
803};
804
1294c286 805static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
390bd87d
DE		 806 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
807 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 808 { 0 }
809};
810
b2ddf0c4 811/* start-sanitize-m32rx */
1294c286 812static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
7caa7497
DE		 813 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
814 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
815 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
ab0bd049
DE		 816 { 0 }
817};
818
b2ddf0c4 819/* end-sanitize-m32rx */
1294c286 820static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
fbc8134d
DE		 821 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
822 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
823 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
824 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
825 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
826 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 827 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
828 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 829 { 0 }
830};
831
1294c286 832static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
fbc8134d 833 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
7caa7497 834 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 835 { 0 }
836};
837
1294c286 838static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
390bd87d 839 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
fbc8134d 840 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
390bd87d
DE		 841 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
842 { 0 }
843};
844
1294c286 845static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
7caa7497
DE		 846 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
847 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
848 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 849 { 0 }
850};
851
1294c286 852static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
fbc8134d 853 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
390bd87d 854 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 855 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
856 { 0 }
857};
858
1294c286 859static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
fbc8134d 860 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
7caa7497
DE		 861 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
862 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
7caa7497 863 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 864 { 0 }
865};
866
1294c286 867static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
fbc8134d
DE		 868 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
869 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 870 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
871 { 0 }
872};
873
1294c286 874static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
390bd87d 875 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d
DE		 876 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
877 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 878 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
879 { 0 }
880};
881
1294c286 882static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
fbc8134d
DE		 883 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
884 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 885 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
886 { 0 }
887};
888
1294c286 889static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
390bd87d 890 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d
DE		 891 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
892 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 893 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
894 { 0 }
895};
896
1294c286 897static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
390bd87d 898 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
fbc8134d 899 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
390bd87d
DE		 900 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
901 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
902 { 0 }
903};
904
1294c286 905static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
8d157f96 906 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
fbc8134d
DE		 907 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
908 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
909 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
910 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
911 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 912 { 0 }
913};
914
1294c286 915static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
8d157f96 916 { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
fbc8134d 917 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
390bd87d 918 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
8d157f96
DE		 919 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
920 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
390bd87d
DE		 921 { 0 }
922};
923
b2ddf0c4 924/* start-sanitize-m32rx */
1294c286 925static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
b02643b5 926 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
7caa7497 927 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 928 { 0 }
929};
930
b2ddf0c4
NC		 931/* end-sanitize-m32rx */
932/* start-sanitize-m32rx */
1294c286 933static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
390bd87d 934 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
b02643b5 935 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
7caa7497 936 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 937 { 0 }
938};
939
b2ddf0c4
NC		 940/* end-sanitize-m32rx */
941/* start-sanitize-m32rx */
1294c286 942static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
7caa7497 943 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
fbc8134d 944 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
7caa7497 945 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 946 { 0 }
947};
948
b2ddf0c4
NC		 949/* end-sanitize-m32rx */
950/* start-sanitize-m32rx */
1294c286 951static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
7caa7497
DE		 952 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
953 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
954 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
955 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
ab0bd049
DE		 956 { 0 }
957};
958
b2ddf0c4
NC		 959/* end-sanitize-m32rx */
960/* start-sanitize-m32rx */
1294c286 961static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
390bd87d
DE		 962 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
963 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
964 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
965 { 0 }
966};
967
b2ddf0c4
NC		 968/* end-sanitize-m32rx */
969/* start-sanitize-m32rx */
1294c286 970static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
390bd87d 971 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
ab0bd049
DE		 972 { 0 }
973};
974
b2ddf0c4 975/* end-sanitize-m32rx */
7caa7497
DE		 976#undef INPUT
977#undef OUTPUT
978
0bf55db8 979#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
8d157f96
DE		 980#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
981#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
23cf992f 982
1294c286
DE		 983/* The instruction table.
984 This is currently non-static because the simulator accesses it
985 directly. */
ab0bd049 986
7c26196f 987const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
5d07b6cf 988{
1294c286
DE		 989 /* Special null first entry.
990 A `num' value of zero is thus illegal.
991 Also, the special `illegal' insn resides here. */
23cf992f 992 { { 0 }, 0 },
9c03036a
DE		 993/* add $dr,$sr */
994 {
23cf992f 995 { 1, 1, 1, 1 },
1294c286 996 M32R_INSN_ADD, "add", "add",
0bf55db8
DE		 997 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
998 { 16, 16, 0xf0f0 }, 0xa0,
1294c286 999 (PTR) & fmt_add_ops[0],
8d157f96 1000 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1001 },
a6cefe4f 1002/* add3 $dr,$sr,$hash$slo16 */
9c03036a 1003 {
23cf992f 1004 { 1, 1, 1, 1 },
1294c286 1005 M32R_INSN_ADD3, "add3", "add3",
a6cefe4f 1006 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
0bf55db8 1007 { 32, 32, 0xf0f00000 }, 0x80a00000,
1294c286 1008 (PTR) & fmt_add3_ops[0],
8d157f96 1009 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
7c26196f 1010 },
9c03036a
DE		 1011/* and $dr,$sr */
1012 {
23cf992f 1013 { 1, 1, 1, 1 },
1294c286 1014 M32R_INSN_AND, "and", "and",
0bf55db8
DE		 1015 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1016 { 16, 16, 0xf0f0 }, 0xc0,
1294c286 1017 (PTR) & fmt_add_ops[0],
8d157f96 1018 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1019 },
9c03036a
DE		 1020/* and3 $dr,$sr,$uimm16 */
1021 {
23cf992f 1022 { 1, 1, 1, 1 },
1294c286 1023 M32R_INSN_AND3, "and3", "and3",
0bf55db8
DE		 1024 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1025 { 32, 32, 0xf0f00000 }, 0x80c00000,
1294c286 1026 (PTR) & fmt_and3_ops[0],
a6cefe4f 1027 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1028 },
1029/* or $dr,$sr */
1030 {
23cf992f 1031 { 1, 1, 1, 1 },
1294c286 1032 M32R_INSN_OR, "or", "or",
0bf55db8
DE		 1033 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1034 { 16, 16, 0xf0f0 }, 0xe0,
1294c286 1035 (PTR) & fmt_add_ops[0],
8d157f96 1036 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1037 },
a6cefe4f 1038/* or3 $dr,$sr,$hash$ulo16 */
7c26196f
DE		 1039 {
1040 { 1, 1, 1, 1 },
1294c286 1041 M32R_INSN_OR3, "or3", "or3",
a6cefe4f 1042 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
0bf55db8 1043 { 32, 32, 0xf0f00000 }, 0x80e00000,
1294c286 1044 (PTR) & fmt_or3_ops[0],
8d157f96 1045 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1046 },
9c03036a
DE		 1047/* xor $dr,$sr */
1048 {
23cf992f 1049 { 1, 1, 1, 1 },
1294c286 1050 M32R_INSN_XOR, "xor", "xor",
0bf55db8
DE		 1051 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1052 { 16, 16, 0xf0f0 }, 0xd0,
1294c286 1053 (PTR) & fmt_add_ops[0],
8d157f96 1054 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1055 },
9c03036a
DE		 1056/* xor3 $dr,$sr,$uimm16 */
1057 {
23cf992f 1058 { 1, 1, 1, 1 },
1294c286 1059 M32R_INSN_XOR3, "xor3", "xor3",
0bf55db8
DE		 1060 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1061 { 32, 32, 0xf0f00000 }, 0x80d00000,
1294c286 1062 (PTR) & fmt_and3_ops[0],
a6cefe4f 1063 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1064 },
1065/* addi $dr,$simm8 */
1066 {
23cf992f 1067 { 1, 1, 1, 1 },
1294c286 1068 M32R_INSN_ADDI, "addi", "addi",
0bf55db8
DE		 1069 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1070 { 16, 16, 0xf000 }, 0x4000,
1294c286 1071 (PTR) & fmt_addi_ops[0],
a6cefe4f 1072 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1073 },
1074/* addv $dr,$sr */
1075 {
23cf992f 1076 { 1, 1, 1, 1 },
1294c286 1077 M32R_INSN_ADDV, "addv", "addv",
0bf55db8
DE		 1078 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1079 { 16, 16, 0xf0f0 }, 0x80,
1294c286 1080 (PTR) & fmt_addv_ops[0],
8d157f96 1081 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1082 },
9c03036a
DE		 1083/* addv3 $dr,$sr,$simm16 */
1084 {
23cf992f 1085 { 1, 1, 1, 1 },
1294c286 1086 M32R_INSN_ADDV3, "addv3", "addv3",
0bf55db8
DE		 1087 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1088 { 32, 32, 0xf0f00000 }, 0x80800000,
1294c286 1089 (PTR) & fmt_addv3_ops[0],
a6cefe4f 1090 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1091 },
1092/* addx $dr,$sr */
1093 {
23cf992f 1094 { 1, 1, 1, 1 },
1294c286 1095 M32R_INSN_ADDX, "addx", "addx",
0bf55db8
DE		 1096 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1097 { 16, 16, 0xf0f0 }, 0x90,
1294c286 1098 (PTR) & fmt_addx_ops[0],
8d157f96 1099 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1100 },
9c03036a
DE		 1101/* bc.s $disp8 */
1102 {
23cf992f 1103 { 1, 1, 1, 1 },
1294c286 1104 M32R_INSN_BC8, "bc8", "bc.s",
0bf55db8
DE		 1105 { MNEM, ' ', OP (DISP8), 0 },
1106 { 16, 16, 0xff00 }, 0x7c00,
1294c286
DE		 1107 (PTR) & fmt_bc8_ops[0],
1108 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1109 },
1110/* bc.l $disp24 */
1111 {
23cf992f 1112 { 1, 1, 1, 1 },
1294c286 1113 M32R_INSN_BC24, "bc24", "bc.l",
0bf55db8
DE		 1114 { MNEM, ' ', OP (DISP24), 0 },
1115 { 32, 32, 0xff000000 }, 0xfc000000,
1294c286
DE		 1116 (PTR) & fmt_bc24_ops[0],
1117 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1118 },
1119/* beq $src1,$src2,$disp16 */
1120 {
23cf992f 1121 { 1, 1, 1, 1 },
1294c286 1122 M32R_INSN_BEQ, "beq", "beq",
0bf55db8
DE		 1123 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1124 { 32, 32, 0xf0f00000 }, 0xb0000000,
1294c286 1125 (PTR) & fmt_beq_ops[0],
8d157f96 1126 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1127 },
1128/* beqz $src2,$disp16 */
1129 {
23cf992f 1130 { 1, 1, 1, 1 },
1294c286 1131 M32R_INSN_BEQZ, "beqz", "beqz",
0bf55db8
DE		 1132 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1133 { 32, 32, 0xfff00000 }, 0xb0800000,
1294c286 1134 (PTR) & fmt_beqz_ops[0],
8d157f96 1135 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1136 },
1137/* bgez $src2,$disp16 */
1138 {
23cf992f 1139 { 1, 1, 1, 1 },
1294c286 1140 M32R_INSN_BGEZ, "bgez", "bgez",
0bf55db8
DE		 1141 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1142 { 32, 32, 0xfff00000 }, 0xb0b00000,
1294c286 1143 (PTR) & fmt_beqz_ops[0],
8d157f96 1144 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1145 },
1146/* bgtz $src2,$disp16 */
1147 {
23cf992f 1148 { 1, 1, 1, 1 },
1294c286 1149 M32R_INSN_BGTZ, "bgtz", "bgtz",
0bf55db8
DE		 1150 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1151 { 32, 32, 0xfff00000 }, 0xb0d00000,
1294c286 1152 (PTR) & fmt_beqz_ops[0],
8d157f96 1153 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1154 },
1155/* blez $src2,$disp16 */
1156 {
23cf992f 1157 { 1, 1, 1, 1 },
1294c286 1158 M32R_INSN_BLEZ, "blez", "blez",
0bf55db8
DE		 1159 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1160 { 32, 32, 0xfff00000 }, 0xb0c00000,
1294c286 1161 (PTR) & fmt_beqz_ops[0],
8d157f96 1162 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1163 },
1164/* bltz $src2,$disp16 */
1165 {
23cf992f 1166 { 1, 1, 1, 1 },
1294c286 1167 M32R_INSN_BLTZ, "bltz", "bltz",
0bf55db8
DE		 1168 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1169 { 32, 32, 0xfff00000 }, 0xb0a00000,
1294c286 1170 (PTR) & fmt_beqz_ops[0],
8d157f96 1171 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1172 },
1173/* bnez $src2,$disp16 */
1174 {
23cf992f 1175 { 1, 1, 1, 1 },
1294c286 1176 M32R_INSN_BNEZ, "bnez", "bnez",
0bf55db8
DE		 1177 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1178 { 32, 32, 0xfff00000 }, 0xb0900000,
1294c286 1179 (PTR) & fmt_beqz_ops[0],
8d157f96 1180 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1181 },
9c03036a
DE		 1182/* bl.s $disp8 */
1183 {
23cf992f 1184 { 1, 1, 1, 1 },
1294c286 1185 M32R_INSN_BL8, "bl8", "bl.s",
0bf55db8
DE		 1186 { MNEM, ' ', OP (DISP8), 0 },
1187 { 16, 16, 0xff00 }, 0x7e00,
1294c286
DE		 1188 (PTR) & fmt_bl8_ops[0],
1189 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1190 },
1191/* bl.l $disp24 */
1192 {
23cf992f 1193 { 1, 1, 1, 1 },
1294c286 1194 M32R_INSN_BL24, "bl24", "bl.l",
0bf55db8
DE		 1195 { MNEM, ' ', OP (DISP24), 0 },
1196 { 32, 32, 0xff000000 }, 0xfe000000,
1294c286
DE		 1197 (PTR) & fmt_bl24_ops[0],
1198 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
7c26196f 1199 },
7c26196f
DE		 1200/* start-sanitize-m32rx */
1201/* bcl.s $disp8 */
1202 {
1203 { 1, 1, 1, 1 },
1294c286 1204 M32R_INSN_BCL8, "bcl8", "bcl.s",
0bf55db8
DE		 1205 { MNEM, ' ', OP (DISP8), 0 },
1206 { 16, 16, 0xff00 }, 0x7800,
1294c286
DE		 1207 (PTR) & fmt_bcl8_ops[0],
1208 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1209 },
1210/* end-sanitize-m32rx */
1211/* start-sanitize-m32rx */
1212/* bcl.l $disp24 */
1213 {
1214 { 1, 1, 1, 1 },
1294c286 1215 M32R_INSN_BCL24, "bcl24", "bcl.l",
0bf55db8
DE		 1216 { MNEM, ' ', OP (DISP24), 0 },
1217 { 32, 32, 0xff000000 }, 0xf8000000,
1294c286
DE		 1218 (PTR) & fmt_bcl24_ops[0],
1219 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
9c03036a 1220 },
7c26196f 1221/* end-sanitize-m32rx */
9c03036a
DE		 1222/* bnc.s $disp8 */
1223 {
23cf992f 1224 { 1, 1, 1, 1 },
1294c286 1225 M32R_INSN_BNC8, "bnc8", "bnc.s",
0bf55db8
DE		 1226 { MNEM, ' ', OP (DISP8), 0 },
1227 { 16, 16, 0xff00 }, 0x7d00,
1294c286
DE		 1228 (PTR) & fmt_bc8_ops[0],
1229 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1230 },
1231/* bnc.l $disp24 */
1232 {
23cf992f 1233 { 1, 1, 1, 1 },
1294c286 1234 M32R_INSN_BNC24, "bnc24", "bnc.l",
0bf55db8
DE		 1235 { MNEM, ' ', OP (DISP24), 0 },
1236 { 32, 32, 0xff000000 }, 0xfd000000,
1294c286
DE		 1237 (PTR) & fmt_bc24_ops[0],
1238 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1239 },
1240/* bne $src1,$src2,$disp16 */
1241 {
23cf992f 1242 { 1, 1, 1, 1 },
1294c286 1243 M32R_INSN_BNE, "bne", "bne",
0bf55db8
DE		 1244 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1245 { 32, 32, 0xf0f00000 }, 0xb0100000,
1294c286 1246 (PTR) & fmt_beq_ops[0],
8d157f96 1247 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1248 },
9c03036a
DE		 1249/* bra.s $disp8 */
1250 {
23cf992f 1251 { 1, 1, 1, 1 },
1294c286 1252 M32R_INSN_BRA8, "bra8", "bra.s",
0bf55db8
DE		 1253 { MNEM, ' ', OP (DISP8), 0 },
1254 { 16, 16, 0xff00 }, 0x7f00,
1294c286
DE		 1255 (PTR) & fmt_bra8_ops[0],
1256 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1257 },
1258/* bra.l $disp24 */
1259 {
23cf992f 1260 { 1, 1, 1, 1 },
1294c286 1261 M32R_INSN_BRA24, "bra24", "bra.l",
0bf55db8
DE		 1262 { MNEM, ' ', OP (DISP24), 0 },
1263 { 32, 32, 0xff000000 }, 0xff000000,
1294c286
DE		 1264 (PTR) & fmt_bra24_ops[0],
1265 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
7c26196f
DE		 1266 },
1267/* start-sanitize-m32rx */
7c26196f
DE		 1268/* bncl.s $disp8 */
1269 {
1270 { 1, 1, 1, 1 },
1294c286 1271 M32R_INSN_BNCL8, "bncl8", "bncl.s",
0bf55db8
DE		 1272 { MNEM, ' ', OP (DISP8), 0 },
1273 { 16, 16, 0xff00 }, 0x7900,
1294c286
DE		 1274 (PTR) & fmt_bcl8_ops[0],
1275 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1276 },
1277/* end-sanitize-m32rx */
1278/* start-sanitize-m32rx */
1279/* bncl.l $disp24 */
1280 {
1281 { 1, 1, 1, 1 },
1294c286 1282 M32R_INSN_BNCL24, "bncl24", "bncl.l",
0bf55db8
DE		 1283 { MNEM, ' ', OP (DISP24), 0 },
1284 { 32, 32, 0xff000000 }, 0xf9000000,
1294c286
DE		 1285 (PTR) & fmt_bcl24_ops[0],
1286 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 1287 },
1288/* end-sanitize-m32rx */
9c03036a
DE		 1289/* cmp $src1,$src2 */
1290 {
23cf992f 1291 { 1, 1, 1, 1 },
1294c286 1292 M32R_INSN_CMP, "cmp", "cmp",
0bf55db8
DE		 1293 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1294 { 16, 16, 0xf0f0 }, 0x40,
1294c286 1295 (PTR) & fmt_cmp_ops[0],
8d157f96 1296 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1297 },
9c03036a
DE		 1298/* cmpi $src2,$simm16 */
1299 {
23cf992f 1300 { 1, 1, 1, 1 },
1294c286 1301 M32R_INSN_CMPI, "cmpi", "cmpi",
0bf55db8
DE		 1302 { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1303 { 32, 32, 0xfff00000 }, 0x80400000,
1294c286 1304 (PTR) & fmt_cmpi_ops[0],
a6cefe4f 1305 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1306 },
1307/* cmpu $src1,$src2 */
1308 {
23cf992f 1309 { 1, 1, 1, 1 },
1294c286 1310 M32R_INSN_CMPU, "cmpu", "cmpu",
0bf55db8
DE		 1311 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1312 { 16, 16, 0xf0f0 }, 0x50,
1294c286 1313 (PTR) & fmt_cmp_ops[0],
8d157f96 1314 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 1315 },
1294c286 1316/* cmpui $src2,$simm16 */
23cf992f
NC		 1317 {
1318 { 1, 1, 1, 1 },
1294c286
DE		 1319 M32R_INSN_CMPUI, "cmpui", "cmpui",
1320 { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
0bf55db8 1321 { 32, 32, 0xfff00000 }, 0x80500000,
1294c286 1322 (PTR) & fmt_cmpi_ops[0],
a6cefe4f 1323 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
7c26196f
DE		 1324 },
1325/* start-sanitize-m32rx */
1326/* cmpeq $src1,$src2 */
1327 {
1328 { 1, 1, 1, 1 },
1294c286 1329 M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
0bf55db8
DE		 1330 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1331 { 16, 16, 0xf0f0 }, 0x60,
1294c286 1332 (PTR) & fmt_cmp_ops[0],
8d157f96 1333 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 1334 },
1335/* end-sanitize-m32rx */
1336/* start-sanitize-m32rx */
1337/* cmpz $src2 */
1338 {
1339 { 1, 1, 1, 1 },
1294c286 1340 M32R_INSN_CMPZ, "cmpz", "cmpz",
0bf55db8
DE		 1341 { MNEM, ' ', OP (SRC2), 0 },
1342 { 16, 16, 0xfff0 }, 0x70,
1294c286 1343 (PTR) & fmt_cmpz_ops[0],
8d157f96 1344 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
9c03036a 1345 },
7c26196f 1346/* end-sanitize-m32rx */
9c03036a
DE		 1347/* div $dr,$sr */
1348 {
23cf992f 1349 { 1, 1, 1, 1 },
1294c286 1350 M32R_INSN_DIV, "div", "div",
0bf55db8
DE		 1351 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1352 { 32, 32, 0xf0f0ffff }, 0x90000000,
1294c286 1353 (PTR) & fmt_div_ops[0],
8d157f96 1354 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1355 },
1356/* divu $dr,$sr */
1357 {
23cf992f 1358 { 1, 1, 1, 1 },
1294c286 1359 M32R_INSN_DIVU, "divu", "divu",
0bf55db8
DE		 1360 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1361 { 32, 32, 0xf0f0ffff }, 0x90100000,
1294c286 1362 (PTR) & fmt_div_ops[0],
8d157f96 1363 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1364 },
1365/* rem $dr,$sr */
1366 {
23cf992f 1367 { 1, 1, 1, 1 },
1294c286 1368 M32R_INSN_REM, "rem", "rem",
0bf55db8
DE		 1369 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1370 { 32, 32, 0xf0f0ffff }, 0x90200000,
1294c286 1371 (PTR) & fmt_div_ops[0],
8d157f96 1372 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1373 },
1374/* remu $dr,$sr */
1375 {
23cf992f 1376 { 1, 1, 1, 1 },
1294c286 1377 M32R_INSN_REMU, "remu", "remu",
0bf55db8
DE		 1378 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1379 { 32, 32, 0xf0f0ffff }, 0x90300000,
1294c286 1380 (PTR) & fmt_div_ops[0],
8d157f96 1381 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
ab0bd049
DE		 1382 },
1383/* start-sanitize-m32rx */
1384/* divh $dr,$sr */
1385 {
1386 { 1, 1, 1, 1 },
1294c286 1387 M32R_INSN_DIVH, "divh", "divh",
0bf55db8
DE		 1388 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1389 { 32, 32, 0xf0f0ffff }, 0x90000010,
1294c286 1390 (PTR) & fmt_div_ops[0],
8d157f96 1391 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f 1392 },
ab0bd049 1393/* end-sanitize-m32rx */
7c26196f
DE		 1394/* start-sanitize-m32rx */
1395/* jc $sr */
1396 {
1397 { 1, 1, 1, 1 },
1294c286 1398 M32R_INSN_JC, "jc", "jc",
0bf55db8
DE		 1399 { MNEM, ' ', OP (SR), 0 },
1400 { 16, 16, 0xfff0 }, 0x1cc0,
1294c286 1401 (PTR) & fmt_jc_ops[0],
fbc8134d 1402 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1403 },
1404/* end-sanitize-m32rx */
1405/* start-sanitize-m32rx */
1406/* jnc $sr */
1407 {
1408 { 1, 1, 1, 1 },
1294c286 1409 M32R_INSN_JNC, "jnc", "jnc",
0bf55db8
DE		 1410 { MNEM, ' ', OP (SR), 0 },
1411 { 16, 16, 0xfff0 }, 0x1dc0,
1294c286 1412 (PTR) & fmt_jc_ops[0],
fbc8134d 1413 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
9c03036a 1414 },
7c26196f 1415/* end-sanitize-m32rx */
9c03036a
DE		 1416/* jl $sr */
1417 {
23cf992f 1418 { 1, 1, 1, 1 },
1294c286 1419 M32R_INSN_JL, "jl", "jl",
0bf55db8
DE		 1420 { MNEM, ' ', OP (SR), 0 },
1421 { 16, 16, 0xfff0 }, 0x1ec0,
1294c286 1422 (PTR) & fmt_jl_ops[0],
8d157f96 1423 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1424 },
1425/* jmp $sr */
1426 {
23cf992f 1427 { 1, 1, 1, 1 },
1294c286 1428 M32R_INSN_JMP, "jmp", "jmp",
0bf55db8
DE		 1429 { MNEM, ' ', OP (SR), 0 },
1430 { 16, 16, 0xfff0 }, 0x1fc0,
1294c286 1431 (PTR) & fmt_jmp_ops[0],
8d157f96 1432 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1433 },
1434/* ld $dr,@$sr */
1435 {
23cf992f 1436 { 1, 1, 1, 1 },
1294c286 1437 M32R_INSN_LD, "ld", "ld",
0bf55db8
DE		 1438 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1439 { 16, 16, 0xf0f0 }, 0x20c0,
1294c286 1440 (PTR) & fmt_ld_ops[0],
8d157f96 1441 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1442 },
9c03036a
DE		 1443/* ld $dr,@($slo16,$sr) */
1444 {
23cf992f 1445 { 1, 1, 1, 1 },
1294c286 1446 M32R_INSN_LD_D, "ld-d", "ld",
0bf55db8
DE		 1447 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1448 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1294c286 1449 (PTR) & fmt_ld_d_ops[0],
8d157f96 1450 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1451 },
9c03036a
DE		 1452/* ldb $dr,@$sr */
1453 {
23cf992f 1454 { 1, 1, 1, 1 },
1294c286 1455 M32R_INSN_LDB, "ldb", "ldb",
0bf55db8
DE		 1456 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1457 { 16, 16, 0xf0f0 }, 0x2080,
1294c286 1458 (PTR) & fmt_ldb_ops[0],
8d157f96 1459 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1460 },
9c03036a
DE		 1461/* ldb $dr,@($slo16,$sr) */
1462 {
23cf992f 1463 { 1, 1, 1, 1 },
1294c286 1464 M32R_INSN_LDB_D, "ldb-d", "ldb",
0bf55db8
DE		 1465 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1466 { 32, 32, 0xf0f00000 }, 0xa0800000,
1294c286 1467 (PTR) & fmt_ldb_d_ops[0],
8d157f96 1468 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1469 },
9c03036a
DE		 1470/* ldh $dr,@$sr */
1471 {
23cf992f 1472 { 1, 1, 1, 1 },
1294c286 1473 M32R_INSN_LDH, "ldh", "ldh",
0bf55db8
DE		 1474 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1475 { 16, 16, 0xf0f0 }, 0x20a0,
1294c286 1476 (PTR) & fmt_ldh_ops[0],
8d157f96 1477 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1478 },
9c03036a
DE		 1479/* ldh $dr,@($slo16,$sr) */
1480 {
23cf992f 1481 { 1, 1, 1, 1 },
1294c286 1482 M32R_INSN_LDH_D, "ldh-d", "ldh",
0bf55db8
DE		 1483 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1484 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1294c286 1485 (PTR) & fmt_ldh_d_ops[0],
8d157f96 1486 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1487 },
9c03036a
DE		 1488/* ldub $dr,@$sr */
1489 {
23cf992f 1490 { 1, 1, 1, 1 },
1294c286 1491 M32R_INSN_LDUB, "ldub", "ldub",
0bf55db8
DE		 1492 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1493 { 16, 16, 0xf0f0 }, 0x2090,
1294c286 1494 (PTR) & fmt_ldb_ops[0],
8d157f96 1495 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1496 },
9c03036a
DE		 1497/* ldub $dr,@($slo16,$sr) */
1498 {
23cf992f 1499 { 1, 1, 1, 1 },
1294c286 1500 M32R_INSN_LDUB_D, "ldub-d", "ldub",
0bf55db8
DE		 1501 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1502 { 32, 32, 0xf0f00000 }, 0xa0900000,
1294c286 1503 (PTR) & fmt_ldb_d_ops[0],
8d157f96 1504 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1505 },
9c03036a
DE		 1506/* lduh $dr,@$sr */
1507 {
23cf992f 1508 { 1, 1, 1, 1 },
1294c286 1509 M32R_INSN_LDUH, "lduh", "lduh",
0bf55db8
DE		 1510 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1511 { 16, 16, 0xf0f0 }, 0x20b0,
1294c286 1512 (PTR) & fmt_ldh_ops[0],
8d157f96 1513 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1514 },
9c03036a
DE		 1515/* lduh $dr,@($slo16,$sr) */
1516 {
23cf992f 1517 { 1, 1, 1, 1 },
1294c286 1518 M32R_INSN_LDUH_D, "lduh-d", "lduh",
0bf55db8
DE		 1519 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1520 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1294c286 1521 (PTR) & fmt_ldh_d_ops[0],
8d157f96 1522 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1523 },
9c03036a
DE		 1524/* ld $dr,@$sr+ */
1525 {
23cf992f 1526 { 1, 1, 1, 1 },
1294c286 1527 M32R_INSN_LD_PLUS, "ld-plus", "ld",
0bf55db8
DE		 1528 { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1529 { 16, 16, 0xf0f0 }, 0x20e0,
1294c286 1530 (PTR) & fmt_ld_plus_ops[0],
8d157f96 1531 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1532 },
9c03036a
DE		 1533/* ld24 $dr,$uimm24 */
1534 {
23cf992f 1535 { 1, 1, 1, 1 },
1294c286 1536 M32R_INSN_LD24, "ld24", "ld24",
0bf55db8
DE		 1537 { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1538 { 32, 32, 0xf0000000 }, 0xe0000000,
1294c286 1539 (PTR) & fmt_ld24_ops[0],
a6cefe4f 1540 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1541 },
9c03036a
DE		 1542/* ldi8 $dr,$simm8 */
1543 {
23cf992f 1544 { 1, 1, 1, 1 },
1294c286 1545 M32R_INSN_LDI8, "ldi8", "ldi8",
0bf55db8
DE		 1546 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1547 { 16, 16, 0xf000 }, 0x6000,
1294c286
DE		 1548 (PTR) & fmt_ldi8_ops[0],
1549 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a 1550 },
a6cefe4f 1551/* ldi16 $dr,$hash$slo16 */
9c03036a 1552 {
23cf992f 1553 { 1, 1, 1, 1 },
1294c286 1554 M32R_INSN_LDI16, "ldi16", "ldi16",
a6cefe4f 1555 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
0bf55db8 1556 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1294c286
DE		 1557 (PTR) & fmt_ldi16_ops[0],
1558 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1559 },
1560/* lock $dr,@$sr */
1561 {
23cf992f 1562 { 1, 1, 1, 1 },
1294c286 1563 M32R_INSN_LOCK, "lock", "lock",
0bf55db8
DE		 1564 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1565 { 16, 16, 0xf0f0 }, 0x20d0,
1294c286 1566 (PTR) & fmt_lock_ops[0],
8d157f96 1567 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1568 },
1569/* machi $src1,$src2 */
1570 {
23cf992f 1571 { 1, 1, 1, 1 },
1294c286 1572 M32R_INSN_MACHI, "machi", "machi",
0bf55db8
DE		 1573 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1574 { 16, 16, 0xf0f0 }, 0x3040,
1294c286 1575 (PTR) & fmt_machi_ops[0],
8d157f96 1576 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1577 },
1578/* start-sanitize-m32rx */
1579/* machi $src1,$src2,$acc */
1580 {
1581 { 1, 1, 1, 1 },
1294c286 1582 M32R_INSN_MACHI_A, "machi-a", "machi",
0bf55db8
DE		 1583 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1584 { 16, 16, 0xf070 }, 0x3040,
1294c286 1585 (PTR) & fmt_machi_a_ops[0],
8d157f96 1586 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1587 },
7c26196f 1588/* end-sanitize-m32rx */
9c03036a
DE		 1589/* maclo $src1,$src2 */
1590 {
23cf992f 1591 { 1, 1, 1, 1 },
1294c286 1592 M32R_INSN_MACLO, "maclo", "maclo",
0bf55db8
DE		 1593 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1594 { 16, 16, 0xf0f0 }, 0x3050,
1294c286 1595 (PTR) & fmt_machi_ops[0],
8d157f96 1596 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1597 },
7c26196f
DE		 1598/* start-sanitize-m32rx */
1599/* maclo $src1,$src2,$acc */
1600 {
1601 { 1, 1, 1, 1 },
1294c286 1602 M32R_INSN_MACLO_A, "maclo-a", "maclo",
0bf55db8
DE		 1603 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1604 { 16, 16, 0xf070 }, 0x3050,
1294c286 1605 (PTR) & fmt_machi_a_ops[0],
8d157f96 1606 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1607 },
1608/* end-sanitize-m32rx */
9c03036a
DE		 1609/* macwhi $src1,$src2 */
1610 {
23cf992f 1611 { 1, 1, 1, 1 },
1294c286 1612 M32R_INSN_MACWHI, "macwhi", "macwhi",
0bf55db8
DE		 1613 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1614 { 16, 16, 0xf0f0 }, 0x3060,
1294c286 1615 (PTR) & fmt_machi_ops[0],
8d157f96 1616 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1617 },
1618/* macwlo $src1,$src2 */
1619 {
23cf992f 1620 { 1, 1, 1, 1 },
1294c286 1621 M32R_INSN_MACWLO, "macwlo", "macwlo",
0bf55db8
DE		 1622 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1623 { 16, 16, 0xf0f0 }, 0x3070,
1294c286 1624 (PTR) & fmt_machi_ops[0],
8d157f96 1625 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1626 },
1627/* mul $dr,$sr */
1628 {
23cf992f 1629 { 1, 1, 1, 1 },
1294c286 1630 M32R_INSN_MUL, "mul", "mul",
0bf55db8
DE		 1631 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1632 { 16, 16, 0xf0f0 }, 0x1060,
1294c286 1633 (PTR) & fmt_add_ops[0],
8d157f96 1634 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1635 },
1636/* mulhi $src1,$src2 */
1637 {
23cf992f 1638 { 1, 1, 1, 1 },
1294c286 1639 M32R_INSN_MULHI, "mulhi", "mulhi",
0bf55db8
DE		 1640 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1641 { 16, 16, 0xf0f0 }, 0x3000,
1294c286 1642 (PTR) & fmt_mulhi_ops[0],
8d157f96 1643 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1644 },
1645/* start-sanitize-m32rx */
1646/* mulhi $src1,$src2,$acc */
1647 {
1648 { 1, 1, 1, 1 },
1294c286 1649 M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
0bf55db8
DE		 1650 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1651 { 16, 16, 0xf070 }, 0x3000,
1294c286 1652 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1653 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1654 },
7c26196f 1655/* end-sanitize-m32rx */
9c03036a
DE		 1656/* mullo $src1,$src2 */
1657 {
23cf992f 1658 { 1, 1, 1, 1 },
1294c286 1659 M32R_INSN_MULLO, "mullo", "mullo",
0bf55db8
DE		 1660 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1661 { 16, 16, 0xf0f0 }, 0x3010,
1294c286 1662 (PTR) & fmt_mulhi_ops[0],
8d157f96 1663 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1664 },
7c26196f
DE		 1665/* start-sanitize-m32rx */
1666/* mullo $src1,$src2,$acc */
1667 {
1668 { 1, 1, 1, 1 },
1294c286 1669 M32R_INSN_MULLO_A, "mullo-a", "mullo",
0bf55db8
DE		 1670 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1671 { 16, 16, 0xf070 }, 0x3010,
1294c286 1672 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1673 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1674 },
1675/* end-sanitize-m32rx */
9c03036a
DE		 1676/* mulwhi $src1,$src2 */
1677 {
23cf992f 1678 { 1, 1, 1, 1 },
1294c286 1679 M32R_INSN_MULWHI, "mulwhi", "mulwhi",
0bf55db8
DE		 1680 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1681 { 16, 16, 0xf0f0 }, 0x3020,
1294c286 1682 (PTR) & fmt_mulhi_ops[0],
8d157f96 1683 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1684 },
1685/* mulwlo $src1,$src2 */
1686 {
23cf992f 1687 { 1, 1, 1, 1 },
1294c286 1688 M32R_INSN_MULWLO, "mulwlo", "mulwlo",
0bf55db8
DE		 1689 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1690 { 16, 16, 0xf0f0 }, 0x3030,
1294c286 1691 (PTR) & fmt_mulhi_ops[0],
8d157f96 1692 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a
DE		 1693 },
1694/* mv $dr,$sr */
1695 {
23cf992f 1696 { 1, 1, 1, 1 },
1294c286 1697 M32R_INSN_MV, "mv", "mv",
0bf55db8
DE		 1698 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1699 { 16, 16, 0xf0f0 }, 0x1080,
1294c286 1700 (PTR) & fmt_mv_ops[0],
8d157f96 1701 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1702 },
1703/* mvfachi $dr */
1704 {
23cf992f 1705 { 1, 1, 1, 1 },
1294c286 1706 M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
0bf55db8
DE		 1707 { MNEM, ' ', OP (DR), 0 },
1708 { 16, 16, 0xf0ff }, 0x50f0,
1294c286 1709 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1710 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1711 },
1712/* start-sanitize-m32rx */
1713/* mvfachi $dr,$accs */
1714 {
1715 { 1, 1, 1, 1 },
1294c286 1716 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
0bf55db8
DE		 1717 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1718 { 16, 16, 0xf0f3 }, 0x50f0,
1294c286 1719 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1720 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1721 },
7c26196f 1722/* end-sanitize-m32rx */
9c03036a
DE		 1723/* mvfaclo $dr */
1724 {
23cf992f 1725 { 1, 1, 1, 1 },
1294c286 1726 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
0bf55db8
DE		 1727 { MNEM, ' ', OP (DR), 0 },
1728 { 16, 16, 0xf0ff }, 0x50f1,
1294c286 1729 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1730 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1731 },
7c26196f
DE		 1732/* start-sanitize-m32rx */
1733/* mvfaclo $dr,$accs */
1734 {
1735 { 1, 1, 1, 1 },
1294c286 1736 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
0bf55db8
DE		 1737 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1738 { 16, 16, 0xf0f3 }, 0x50f1,
1294c286 1739 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1740 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1741 },
1742/* end-sanitize-m32rx */
9c03036a
DE		 1743/* mvfacmi $dr */
1744 {
23cf992f 1745 { 1, 1, 1, 1 },
1294c286 1746 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
0bf55db8
DE		 1747 { MNEM, ' ', OP (DR), 0 },
1748 { 16, 16, 0xf0ff }, 0x50f2,
1294c286 1749 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1750 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1751 },
1752/* start-sanitize-m32rx */
1753/* mvfacmi $dr,$accs */
1754 {
1755 { 1, 1, 1, 1 },
1294c286 1756 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
0bf55db8
DE		 1757 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1758 { 16, 16, 0xf0f3 }, 0x50f2,
1294c286 1759 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1760 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1761 },
7c26196f 1762/* end-sanitize-m32rx */
9c03036a
DE		 1763/* mvfc $dr,$scr */
1764 {
23cf992f 1765 { 1, 1, 1, 1 },
1294c286 1766 M32R_INSN_MVFC, "mvfc", "mvfc",
0bf55db8
DE		 1767 { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
1768 { 16, 16, 0xf0f0 }, 0x1090,
1294c286 1769 (PTR) & fmt_mvfc_ops[0],
8d157f96 1770 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1771 },
1772/* mvtachi $src1 */
1773 {
23cf992f 1774 { 1, 1, 1, 1 },
1294c286 1775 M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
0bf55db8
DE		 1776 { MNEM, ' ', OP (SRC1), 0 },
1777 { 16, 16, 0xf0ff }, 0x5070,
1294c286 1778 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1779 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1780 },
7c26196f
DE		 1781/* start-sanitize-m32rx */
1782/* mvtachi $src1,$accs */
1783 {
1784 { 1, 1, 1, 1 },
1294c286 1785 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
0bf55db8
DE		 1786 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1787 { 16, 16, 0xf0f3 }, 0x5070,
1294c286 1788 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1789 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1790 },
1791/* end-sanitize-m32rx */
9c03036a
DE		 1792/* mvtaclo $src1 */
1793 {
23cf992f 1794 { 1, 1, 1, 1 },
1294c286 1795 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
0bf55db8
DE		 1796 { MNEM, ' ', OP (SRC1), 0 },
1797 { 16, 16, 0xf0ff }, 0x5071,
1294c286 1798 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1799 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1800 },
1801/* start-sanitize-m32rx */
1802/* mvtaclo $src1,$accs */
1803 {
1804 { 1, 1, 1, 1 },
1294c286 1805 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
0bf55db8
DE		 1806 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1807 { 16, 16, 0xf0f3 }, 0x5071,
1294c286 1808 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1809 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1810 },
7c26196f 1811/* end-sanitize-m32rx */
9c03036a
DE		 1812/* mvtc $sr,$dcr */
1813 {
23cf992f 1814 { 1, 1, 1, 1 },
1294c286 1815 M32R_INSN_MVTC, "mvtc", "mvtc",
0bf55db8
DE		 1816 { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
1817 { 16, 16, 0xf0f0 }, 0x10a0,
1294c286 1818 (PTR) & fmt_mvtc_ops[0],
8d157f96 1819 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1820 },
1821/* neg $dr,$sr */
1822 {
23cf992f 1823 { 1, 1, 1, 1 },
1294c286 1824 M32R_INSN_NEG, "neg", "neg",
0bf55db8
DE		 1825 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1826 { 16, 16, 0xf0f0 }, 0x30,
1294c286 1827 (PTR) & fmt_mv_ops[0],
8d157f96 1828 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1829 },
1830/* nop */
1831 {
23cf992f 1832 { 1, 1, 1, 1 },
1294c286 1833 M32R_INSN_NOP, "nop", "nop",
0bf55db8
DE		 1834 { MNEM, 0 },
1835 { 16, 16, 0xffff }, 0x7000,
1294c286 1836 (PTR) 0,
8d157f96 1837 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1838 },
1839/* not $dr,$sr */
1840 {
23cf992f 1841 { 1, 1, 1, 1 },
1294c286 1842 M32R_INSN_NOT, "not", "not",
0bf55db8
DE		 1843 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1844 { 16, 16, 0xf0f0 }, 0xb0,
1294c286 1845 (PTR) & fmt_mv_ops[0],
8d157f96 1846 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 1847 },
1848/* rac */
1849 {
23cf992f 1850 { 1, 1, 1, 1 },
1294c286 1851 M32R_INSN_RAC, "rac", "rac",
0bf55db8
DE		 1852 { MNEM, 0 },
1853 { 16, 16, 0xffff }, 0x5090,
1294c286 1854 (PTR) & fmt_rac_ops[0],
8d157f96 1855 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1856 },
1857/* start-sanitize-m32rx */
a6cefe4f 1858/* rac $accd,$accs,$imm1 */
ab0bd049
DE		 1859 {
1860 { 1, 1, 1, 1 },
1294c286 1861 M32R_INSN_RAC_DSI, "rac-dsi", "rac",
a6cefe4f 1862 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
0bf55db8 1863 { 16, 16, 0xf3f2 }, 0x5090,
1294c286 1864 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 1865 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1866 },
7c26196f 1867/* end-sanitize-m32rx */
9c03036a
DE		 1868/* rach */
1869 {
23cf992f 1870 { 1, 1, 1, 1 },
1294c286 1871 M32R_INSN_RACH, "rach", "rach",
0bf55db8
DE		 1872 { MNEM, 0 },
1873 { 16, 16, 0xffff }, 0x5080,
1294c286 1874 (PTR) & fmt_rac_ops[0],
8d157f96 1875 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
ab0bd049
DE		 1876 },
1877/* start-sanitize-m32rx */
a6cefe4f 1878/* rach $accd,$accs,$imm1 */
7c26196f
DE		 1879 {
1880 { 1, 1, 1, 1 },
1294c286 1881 M32R_INSN_RACH_DSI, "rach-dsi", "rach",
a6cefe4f 1882 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
0bf55db8 1883 { 16, 16, 0xf3f2 }, 0x5080,
1294c286 1884 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 1885 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1886 },
7c26196f 1887/* end-sanitize-m32rx */
9c03036a
DE		 1888/* rte */
1889 {
23cf992f 1890 { 1, 1, 1, 1 },
1294c286 1891 M32R_INSN_RTE, "rte", "rte",
0bf55db8
DE		 1892 { MNEM, 0 },
1893 { 16, 16, 0xffff }, 0x10d6,
1294c286 1894 (PTR) & fmt_rte_ops[0],
8d157f96 1895 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
7c26196f 1896 },
a6cefe4f 1897/* seth $dr,$hash$hi16 */
7c26196f
DE		 1898 {
1899 { 1, 1, 1, 1 },
1294c286 1900 M32R_INSN_SETH, "seth", "seth",
a6cefe4f 1901 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
0bf55db8 1902 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
1294c286 1903 (PTR) & fmt_seth_ops[0],
8d157f96 1904 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 1905 },
9c03036a
DE		 1906/* sll $dr,$sr */
1907 {
23cf992f 1908 { 1, 1, 1, 1 },
1294c286 1909 M32R_INSN_SLL, "sll", "sll",
0bf55db8
DE		 1910 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1911 { 16, 16, 0xf0f0 }, 0x1040,
1294c286 1912 (PTR) & fmt_add_ops[0],
8d157f96 1913 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1914 },
9c03036a
DE		 1915/* sll3 $dr,$sr,$simm16 */
1916 {
23cf992f 1917 { 1, 1, 1, 1 },
1294c286 1918 M32R_INSN_SLL3, "sll3", "sll3",
0bf55db8
DE		 1919 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1920 { 32, 32, 0xf0f00000 }, 0x90c00000,
1294c286 1921 (PTR) & fmt_sll3_ops[0],
a6cefe4f 1922 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1923 },
1924/* slli $dr,$uimm5 */
1925 {
23cf992f 1926 { 1, 1, 1, 1 },
1294c286 1927 M32R_INSN_SLLI, "slli", "slli",
0bf55db8
DE		 1928 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1929 { 16, 16, 0xf0e0 }, 0x5040,
1294c286 1930 (PTR) & fmt_slli_ops[0],
a6cefe4f 1931 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1932 },
1933/* sra $dr,$sr */
1934 {
23cf992f 1935 { 1, 1, 1, 1 },
1294c286 1936 M32R_INSN_SRA, "sra", "sra",
0bf55db8
DE		 1937 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1938 { 16, 16, 0xf0f0 }, 0x1020,
1294c286 1939 (PTR) & fmt_add_ops[0],
8d157f96 1940 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1941 },
9c03036a
DE		 1942/* sra3 $dr,$sr,$simm16 */
1943 {
23cf992f 1944 { 1, 1, 1, 1 },
1294c286 1945 M32R_INSN_SRA3, "sra3", "sra3",
0bf55db8
DE		 1946 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1947 { 32, 32, 0xf0f00000 }, 0x90a00000,
1294c286 1948 (PTR) & fmt_sll3_ops[0],
a6cefe4f 1949 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1950 },
1951/* srai $dr,$uimm5 */
1952 {
23cf992f 1953 { 1, 1, 1, 1 },
1294c286 1954 M32R_INSN_SRAI, "srai", "srai",
0bf55db8
DE		 1955 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1956 { 16, 16, 0xf0e0 }, 0x5020,
1294c286 1957 (PTR) & fmt_slli_ops[0],
a6cefe4f 1958 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1959 },
1960/* srl $dr,$sr */
1961 {
23cf992f 1962 { 1, 1, 1, 1 },
1294c286 1963 M32R_INSN_SRL, "srl", "srl",
0bf55db8
DE		 1964 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1965 { 16, 16, 0xf0f0 }, 0x1000,
1294c286 1966 (PTR) & fmt_add_ops[0],
8d157f96 1967 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
7c26196f 1968 },
9c03036a
DE		 1969/* srl3 $dr,$sr,$simm16 */
1970 {
23cf992f 1971 { 1, 1, 1, 1 },
1294c286 1972 M32R_INSN_SRL3, "srl3", "srl3",
0bf55db8
DE		 1973 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1974 { 32, 32, 0xf0f00000 }, 0x90800000,
1294c286 1975 (PTR) & fmt_sll3_ops[0],
a6cefe4f 1976 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a
DE		 1977 },
1978/* srli $dr,$uimm5 */
1979 {
23cf992f 1980 { 1, 1, 1, 1 },
1294c286 1981 M32R_INSN_SRLI, "srli", "srli",
0bf55db8
DE		 1982 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1983 { 16, 16, 0xf0e0 }, 0x5000,
1294c286 1984 (PTR) & fmt_slli_ops[0],
a6cefe4f 1985 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 1986 },
1987/* st $src1,@$src2 */
1988 {
23cf992f 1989 { 1, 1, 1, 1 },
1294c286 1990 M32R_INSN_ST, "st", "st",
0bf55db8
DE		 1991 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
1992 { 16, 16, 0xf0f0 }, 0x2040,
1294c286 1993 (PTR) & fmt_st_ops[0],
8d157f96 1994 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 1995 },
9c03036a
DE		 1996/* st $src1,@($slo16,$src2) */
1997 {
23cf992f 1998 { 1, 1, 1, 1 },
1294c286 1999 M32R_INSN_ST_D, "st-d", "st",
0bf55db8
DE		 2000 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2001 { 32, 32, 0xf0f00000 }, 0xa0400000,
1294c286 2002 (PTR) & fmt_st_d_ops[0],
8d157f96 2003 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2004 },
9c03036a
DE		 2005/* stb $src1,@$src2 */
2006 {
23cf992f 2007 { 1, 1, 1, 1 },
1294c286 2008 M32R_INSN_STB, "stb", "stb",
0bf55db8
DE		 2009 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2010 { 16, 16, 0xf0f0 }, 0x2000,
1294c286 2011 (PTR) & fmt_stb_ops[0],
8d157f96 2012 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2013 },
1294c286 2014/* stb $src1,@($slo16,$src2) */
9c03036a 2015 {
23cf992f 2016 { 1, 1, 1, 1 },
1294c286 2017 M32R_INSN_STB_D, "stb-d", "stb",
0bf55db8
DE		 2018 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2019 { 32, 32, 0xf0f00000 }, 0xa0000000,
1294c286 2020 (PTR) & fmt_stb_d_ops[0],
8d157f96 2021 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2022 },
9c03036a
DE		 2023/* sth $src1,@$src2 */
2024 {
23cf992f 2025 { 1, 1, 1, 1 },
1294c286 2026 M32R_INSN_STH, "sth", "sth",
0bf55db8
DE		 2027 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2028 { 16, 16, 0xf0f0 }, 0x2020,
1294c286 2029 (PTR) & fmt_sth_ops[0],
8d157f96 2030 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2031 },
9c03036a
DE		 2032/* sth $src1,@($slo16,$src2) */
2033 {
23cf992f 2034 { 1, 1, 1, 1 },
1294c286 2035 M32R_INSN_STH_D, "sth-d", "sth",
0bf55db8
DE		 2036 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2037 { 32, 32, 0xf0f00000 }, 0xa0200000,
1294c286 2038 (PTR) & fmt_sth_d_ops[0],
8d157f96 2039 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
9c03036a 2040 },
9c03036a
DE		 2041/* st $src1,@+$src2 */
2042 {
23cf992f 2043 { 1, 1, 1, 1 },
1294c286 2044 M32R_INSN_ST_PLUS, "st-plus", "st",
0bf55db8
DE		 2045 { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2046 { 16, 16, 0xf0f0 }, 0x2060,
1294c286 2047 (PTR) & fmt_st_plus_ops[0],
8d157f96 2048 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2049 },
2050/* st $src1,@-$src2 */
2051 {
23cf992f 2052 { 1, 1, 1, 1 },
1294c286 2053 M32R_INSN_ST_MINUS, "st-minus", "st",
0bf55db8
DE		 2054 { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2055 { 16, 16, 0xf0f0 }, 0x2070,
1294c286 2056 (PTR) & fmt_st_plus_ops[0],
8d157f96 2057 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a
DE		 2058 },
2059/* sub $dr,$sr */
2060 {
23cf992f 2061 { 1, 1, 1, 1 },
1294c286 2062 M32R_INSN_SUB, "sub", "sub",
0bf55db8
DE		 2063 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2064 { 16, 16, 0xf0f0 }, 0x20,
1294c286 2065 (PTR) & fmt_add_ops[0],
8d157f96 2066 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 2067 },
2068/* subv $dr,$sr */
2069 {
23cf992f 2070 { 1, 1, 1, 1 },
1294c286 2071 M32R_INSN_SUBV, "subv", "subv",
0bf55db8
DE		 2072 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2073 { 16, 16, 0xf0f0 }, 0x0,
1294c286 2074 (PTR) & fmt_addv_ops[0],
8d157f96 2075 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
9c03036a
DE		 2076 },
2077/* subx $dr,$sr */
2078 {
23cf992f 2079 { 1, 1, 1, 1 },
1294c286 2080 M32R_INSN_SUBX, "subx", "subx",
0bf55db8
DE		 2081 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2082 { 16, 16, 0xf0f0 }, 0x10,
1294c286 2083 (PTR) & fmt_addx_ops[0],
8d157f96 2084 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
7c26196f 2085 },
a6cefe4f 2086/* trap $uimm4 */
7c26196f
DE		 2087 {
2088 { 1, 1, 1, 1 },
1294c286 2089 M32R_INSN_TRAP, "trap", "trap",
a6cefe4f 2090 { MNEM, ' ', OP (UIMM4), 0 },
0bf55db8 2091 { 16, 16, 0xfff0 }, 0x10f0,
1294c286 2092 (PTR) & fmt_trap_ops[0],
8d157f96 2093 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
9c03036a 2094 },
9c03036a
DE		 2095/* unlock $src1,@$src2 */
2096 {
23cf992f 2097 { 1, 1, 1, 1 },
1294c286 2098 M32R_INSN_UNLOCK, "unlock", "unlock",
0bf55db8
DE		 2099 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2100 { 16, 16, 0xf0f0 }, 0x2050,
1294c286 2101 (PTR) & fmt_unlock_ops[0],
8d157f96 2102 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
9c03036a 2103 },
7c26196f 2104/* start-sanitize-m32rx */
b02643b5 2105/* satb $dr,$sr */
7c26196f
DE		 2106 {
2107 { 1, 1, 1, 1 },
1294c286 2108 M32R_INSN_SATB, "satb", "satb",
0bf55db8 2109 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
d8ca5fae 2110 { 32, 32, 0xf0f0ffff }, 0x80600300,
1294c286 2111 (PTR) & fmt_satb_ops[0],
8d157f96 2112 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2113 },
2114/* end-sanitize-m32rx */
2115/* start-sanitize-m32rx */
b02643b5 2116/* sath $dr,$sr */
7c26196f
DE		 2117 {
2118 { 1, 1, 1, 1 },
1294c286 2119 M32R_INSN_SATH, "sath", "sath",
0bf55db8 2120 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
b2ddf0c4 2121 { 32, 32, 0xf0f0ffff }, 0x80600200,
1294c286 2122 (PTR) & fmt_satb_ops[0],
8d157f96 2123 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2124 },
2125/* end-sanitize-m32rx */
2126/* start-sanitize-m32rx */
b02643b5 2127/* sat $dr,$sr */
7c26196f
DE		 2128 {
2129 { 1, 1, 1, 1 },
1294c286 2130 M32R_INSN_SAT, "sat", "sat",
0bf55db8 2131 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
d8ca5fae 2132 { 32, 32, 0xf0f0ffff }, 0x80600000,
1294c286 2133 (PTR) & fmt_sat_ops[0],
fbc8134d 2134 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2135 },
2136/* end-sanitize-m32rx */
2137/* start-sanitize-m32rx */
2138/* pcmpbz $src2 */
2139 {
2140 { 1, 1, 1, 1 },
1294c286 2141 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
0bf55db8
DE		 2142 { MNEM, ' ', OP (SRC2), 0 },
2143 { 16, 16, 0xfff0 }, 0x370,
1294c286 2144 (PTR) & fmt_cmpz_ops[0],
fbc8134d 2145 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 2146 },
2147/* end-sanitize-m32rx */
2148/* start-sanitize-m32rx */
2149/* sadd */
2150 {
2151 { 1, 1, 1, 1 },
1294c286 2152 M32R_INSN_SADD, "sadd", "sadd",
0bf55db8
DE		 2153 { MNEM, 0 },
2154 { 16, 16, 0xffff }, 0x50e4,
1294c286 2155 (PTR) & fmt_sadd_ops[0],
8d157f96 2156 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2157 },
7c26196f
DE		 2158/* end-sanitize-m32rx */
2159/* start-sanitize-m32rx */
2160/* macwu1 $src1,$src2 */
2161 {
2162 { 1, 1, 1, 1 },
1294c286 2163 M32R_INSN_MACWU1, "macwu1", "macwu1",
0bf55db8
DE		 2164 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2165 { 16, 16, 0xf0f0 }, 0x50b0,
1294c286 2166 (PTR) & fmt_macwu1_ops[0],
8d157f96 2167 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2168 },
2169/* end-sanitize-m32rx */
2170/* start-sanitize-m32rx */
2171/* msblo $src1,$src2 */
2172 {
2173 { 1, 1, 1, 1 },
1294c286 2174 M32R_INSN_MSBLO, "msblo", "msblo",
0bf55db8
DE		 2175 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2176 { 16, 16, 0xf0f0 }, 0x50d0,
1294c286 2177 (PTR) & fmt_machi_ops[0],
8d157f96 2178 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2179 },
2180/* end-sanitize-m32rx */
2181/* start-sanitize-m32rx */
2182/* mulwu1 $src1,$src2 */
2183 {
2184 { 1, 1, 1, 1 },
1294c286 2185 M32R_INSN_MULWU1, "mulwu1", "mulwu1",
0bf55db8
DE		 2186 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2187 { 16, 16, 0xf0f0 }, 0x50a0,
1294c286 2188 (PTR) & fmt_mulwu1_ops[0],
8d157f96 2189 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2190 },
2191/* end-sanitize-m32rx */
2192/* start-sanitize-m32rx */
ab0bd049 2193/* maclh1 $src1,$src2 */
7c26196f
DE		 2194 {
2195 { 1, 1, 1, 1 },
1294c286 2196 M32R_INSN_MACLH1, "maclh1", "maclh1",
0bf55db8
DE		 2197 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2198 { 16, 16, 0xf0f0 }, 0x50c0,
1294c286 2199 (PTR) & fmt_macwu1_ops[0],
8d157f96 2200 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2201 },
2202/* end-sanitize-m32rx */
2203/* start-sanitize-m32rx */
2204/* sc */
2205 {
2206 { 1, 1, 1, 1 },
1294c286 2207 M32R_INSN_SC, "sc", "sc",
0bf55db8
DE		 2208 { MNEM, 0 },
2209 { 16, 16, 0xffff }, 0x7401,
1294c286 2210 (PTR) & fmt_sc_ops[0],
fbc8134d 2211 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2212 },
2213/* end-sanitize-m32rx */
2214/* start-sanitize-m32rx */
2215/* snc */
2216 {
2217 { 1, 1, 1, 1 },
1294c286 2218 M32R_INSN_SNC, "snc", "snc",
0bf55db8
DE		 2219 { MNEM, 0 },
2220 { 16, 16, 0xffff }, 0x7501,
1294c286 2221 (PTR) & fmt_sc_ops[0],
fbc8134d 2222 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2223 },
2224/* end-sanitize-m32rx */
9c03036a
DE		 2225};
2226
23cf992f 2227#undef A
0bf55db8
DE		 2228#undef MNEM
2229#undef OP
23cf992f 2230
1294c286 2231static CGEN_INSN_TABLE insn_table =
853713a7 2232{
9c03036a 2233 & m32r_cgen_insn_table_entries[0],
23cf992f 2234 sizeof (CGEN_INSN),
7c26196f 2235 MAX_INSNS,
1294c286
DE		 2236 NULL
2237};
2238
2239/* Each non-simple macro entry points to an array of expansion possibilities. */
2240
2241#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2242#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2243#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2244
2245/* The macro instruction table. */
2246
2247static const CGEN_INSN macro_insn_table_entries[] =
2248{
2249/* bc $disp8 */
2250 {
2251 { 1, 1, 1, 1 },
2252 -1, "bc8r", "bc",
2253 { MNEM, ' ', OP (DISP8), 0 },
2254 { 16, 16, 0xff00 }, 0x7c00,
2255 (PTR) 0,
2256 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2257 },
2258/* bc $disp24 */
2259 {
2260 { 1, 1, 1, 1 },
2261 -1, "bc24r", "bc",
2262 { MNEM, ' ', OP (DISP24), 0 },
2263 { 32, 32, 0xff000000 }, 0xfc000000,
2264 (PTR) 0,
2265 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2266 },
2267/* bl $disp8 */
2268 {
2269 { 1, 1, 1, 1 },
2270 -1, "bl8r", "bl",
2271 { MNEM, ' ', OP (DISP8), 0 },
2272 { 16, 16, 0xff00 }, 0x7e00,
2273 (PTR) 0,
2274 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2275 },
2276/* bl $disp24 */
2277 {
2278 { 1, 1, 1, 1 },
2279 -1, "bl24r", "bl",
2280 { MNEM, ' ', OP (DISP24), 0 },
2281 { 32, 32, 0xff000000 }, 0xfe000000,
2282 (PTR) 0,
2283 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2284 },
2285/* bcl $disp8 */
2286 {
2287 { 1, 1, 1, 1 },
2288 -1, "bcl8r", "bcl",
2289 { MNEM, ' ', OP (DISP8), 0 },
2290 { 16, 16, 0xff00 }, 0x7800,
2291 (PTR) 0,
2292 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2293 },
2294/* bcl $disp24 */
2295 {
2296 { 1, 1, 1, 1 },
2297 -1, "bcl24r", "bcl",
2298 { MNEM, ' ', OP (DISP24), 0 },
2299 { 32, 32, 0xff000000 }, 0xf8000000,
2300 (PTR) 0,
2301 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2302 },
2303/* bnc $disp8 */
2304 {
2305 { 1, 1, 1, 1 },
2306 -1, "bnc8r", "bnc",
2307 { MNEM, ' ', OP (DISP8), 0 },
2308 { 16, 16, 0xff00 }, 0x7d00,
2309 (PTR) 0,
2310 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2311 },
2312/* bnc $disp24 */
2313 {
2314 { 1, 1, 1, 1 },
2315 -1, "bnc24r", "bnc",
2316 { MNEM, ' ', OP (DISP24), 0 },
2317 { 32, 32, 0xff000000 }, 0xfd000000,
2318 (PTR) 0,
2319 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2320 },
2321/* bra $disp8 */
2322 {
2323 { 1, 1, 1, 1 },
2324 -1, "bra8r", "bra",
2325 { MNEM, ' ', OP (DISP8), 0 },
2326 { 16, 16, 0xff00 }, 0x7f00,
2327 (PTR) 0,
2328 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2329 },
2330/* bra $disp24 */
2331 {
2332 { 1, 1, 1, 1 },
2333 -1, "bra24r", "bra",
2334 { MNEM, ' ', OP (DISP24), 0 },
2335 { 32, 32, 0xff000000 }, 0xff000000,
2336 (PTR) 0,
2337 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2338 },
2339/* bncl $disp8 */
2340 {
2341 { 1, 1, 1, 1 },
2342 -1, "bncl8r", "bncl",
2343 { MNEM, ' ', OP (DISP8), 0 },
2344 { 16, 16, 0xff00 }, 0x7900,
2345 (PTR) 0,
2346 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2347 },
2348/* bncl $disp24 */
2349 {
2350 { 1, 1, 1, 1 },
2351 -1, "bncl24r", "bncl",
2352 { MNEM, ' ', OP (DISP24), 0 },
2353 { 32, 32, 0xff000000 }, 0xf9000000,
2354 (PTR) 0,
2355 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2356 },
2357/* ld $dr,@($sr) */
2358 {
2359 { 1, 1, 1, 1 },
2360 -1, "ld-2", "ld",
2361 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2362 { 16, 16, 0xf0f0 }, 0x20c0,
2363 (PTR) 0,
2364 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2365 },
2366/* ld $dr,@($sr,$slo16) */
2367 {
2368 { 1, 1, 1, 1 },
2369 -1, "ld-d2", "ld",
2370 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2371 { 32, 32, 0xf0f00000 }, 0xa0c00000,
2372 (PTR) 0,
2373 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2374 },
2375/* ldb $dr,@($sr) */
2376 {
2377 { 1, 1, 1, 1 },
2378 -1, "ldb-2", "ldb",
2379 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2380 { 16, 16, 0xf0f0 }, 0x2080,
2381 (PTR) 0,
2382 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2383 },
2384/* ldb $dr,@($sr,$slo16) */
2385 {
2386 { 1, 1, 1, 1 },
2387 -1, "ldb-d2", "ldb",
2388 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2389 { 32, 32, 0xf0f00000 }, 0xa0800000,
2390 (PTR) 0,
2391 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2392 },
2393/* ldh $dr,@($sr) */
2394 {
2395 { 1, 1, 1, 1 },
2396 -1, "ldh-2", "ldh",
2397 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2398 { 16, 16, 0xf0f0 }, 0x20a0,
2399 (PTR) 0,
2400 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2401 },
2402/* ldh $dr,@($sr,$slo16) */
2403 {
2404 { 1, 1, 1, 1 },
2405 -1, "ldh-d2", "ldh",
2406 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2407 { 32, 32, 0xf0f00000 }, 0xa0a00000,
2408 (PTR) 0,
2409 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2410 },
2411/* ldub $dr,@($sr) */
2412 {
2413 { 1, 1, 1, 1 },
2414 -1, "ldub-2", "ldub",
2415 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2416 { 16, 16, 0xf0f0 }, 0x2090,
2417 (PTR) 0,
2418 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2419 },
2420/* ldub $dr,@($sr,$slo16) */
2421 {
2422 { 1, 1, 1, 1 },
2423 -1, "ldub-d2", "ldub",
2424 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2425 { 32, 32, 0xf0f00000 }, 0xa0900000,
2426 (PTR) 0,
2427 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2428 },
2429/* lduh $dr,@($sr) */
2430 {
2431 { 1, 1, 1, 1 },
2432 -1, "lduh-2", "lduh",
2433 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2434 { 16, 16, 0xf0f0 }, 0x20b0,
2435 (PTR) 0,
2436 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2437 },
2438/* lduh $dr,@($sr,$slo16) */
2439 {
2440 { 1, 1, 1, 1 },
2441 -1, "lduh-d2", "lduh",
2442 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2443 { 32, 32, 0xf0f00000 }, 0xa0b00000,
2444 (PTR) 0,
2445 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2446 },
2447/* pop $dr */
2448 {
2449 { 1, 1, 1, 1 },
2450 -1, "pop", "pop",
2451 { MNEM, ' ', OP (DR), 0 },
2452 { 16, 16, 0xf0ff }, 0x20ef,
2453 (PTR) 0,
2454 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2455 },
2456/* ldi $dr,$simm8 */
2457 {
2458 { 1, 1, 1, 1 },
2459 -1, "ldi8a", "ldi",
2460 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
2461 { 16, 16, 0xf000 }, 0x6000,
2462 (PTR) 0,
2463 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2464 },
2465/* ldi $dr,$hash$slo16 */
2466 {
2467 { 1, 1, 1, 1 },
2468 -1, "ldi16a", "ldi",
2469 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
2470 { 32, 32, 0xf0ff0000 }, 0x90f00000,
2471 (PTR) 0,
2472 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2473 },
2474/* rac $accd */
2475 {
2476 { 1, 1, 1, 1 },
2477 -1, "rac-d", "rac",
2478 { MNEM, ' ', OP (ACCD), 0 },
2479 { 16, 16, 0xf3ff }, 0x5090,
2480 (PTR) 0,
2481 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2482 },
2483/* rac $accd,$accs */
2484 {
2485 { 1, 1, 1, 1 },
2486 -1, "rac-ds", "rac",
2487 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2488 { 16, 16, 0xf3f3 }, 0x5090,
2489 (PTR) 0,
2490 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2491 },
2492/* rach $accd */
2493 {
2494 { 1, 1, 1, 1 },
2495 -1, "rach-d", "rach",
2496 { MNEM, ' ', OP (ACCD), 0 },
2497 { 16, 16, 0xf3ff }, 0x5080,
2498 (PTR) 0,
2499 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2500 },
2501/* rach $accd,$accs */
2502 {
2503 { 1, 1, 1, 1 },
2504 -1, "rach-ds", "rach",
2505 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2506 { 16, 16, 0xf3f3 }, 0x5080,
2507 (PTR) 0,
2508 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2509 },
2510/* st $src1,@($src2) */
2511 {
2512 { 1, 1, 1, 1 },
2513 -1, "st-2", "st",
2514 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2515 { 16, 16, 0xf0f0 }, 0x2040,
2516 (PTR) 0,
2517 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2518 },
2519/* st $src1,@($src2,$slo16) */
2520 {
2521 { 1, 1, 1, 1 },
2522 -1, "st-d2", "st",
2523 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2524 { 32, 32, 0xf0f00000 }, 0xa0400000,
2525 (PTR) 0,
2526 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2527 },
2528/* stb $src1,@($src2) */
2529 {
2530 { 1, 1, 1, 1 },
2531 -1, "stb-2", "stb",
2532 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2533 { 16, 16, 0xf0f0 }, 0x2000,
2534 (PTR) 0,
2535 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2536 },
2537/* stb $src1,@($src2,$slo16) */
2538 {
2539 { 1, 1, 1, 1 },
2540 -1, "stb-d2", "stb",
2541 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2542 { 32, 32, 0xf0f00000 }, 0xa0000000,
2543 (PTR) 0,
2544 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2545 },
2546/* sth $src1,@($src2) */
2547 {
2548 { 1, 1, 1, 1 },
2549 -1, "sth-2", "sth",
2550 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2551 { 16, 16, 0xf0f0 }, 0x2020,
2552 (PTR) 0,
2553 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2554 },
2555/* sth $src1,@($src2,$slo16) */
2556 {
2557 { 1, 1, 1, 1 },
2558 -1, "sth-d2", "sth",
2559 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2560 { 32, 32, 0xf0f00000 }, 0xa0200000,
2561 (PTR) 0,
2562 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2563 },
2564/* push $src1 */
2565 {
2566 { 1, 1, 1, 1 },
2567 -1, "push", "push",
2568 { MNEM, ' ', OP (SRC1), 0 },
2569 { 16, 16, 0xf0ff }, 0x207f,
2570 (PTR) 0,
2571 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2572 },
2573};
2574
2575#undef A
2576#undef MNEM
2577#undef OP
2578
2579static CGEN_INSN_TABLE macro_insn_table =
2580{
2581 & macro_insn_table_entries[0],
2582 sizeof (CGEN_INSN),
2583 (sizeof (macro_insn_table_entries) /
2584 sizeof (macro_insn_table_entries[0])),
2585 NULL
9c03036a
DE		 2586};
2587
2588/* The hash functions are recorded here to help keep assembler code out of
1294c286
DE		 2589 the disassembler and vice versa.
2590
2591static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
2592static unsigned int asm_hash_insn PARAMS ((const char *));
2593static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
2594static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
2595
2596/* Return non-zero if INSN is to be added to the hash table.
2597 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2598
2599static int
2600asm_hash_insn_p (insn)
2601 const CGEN_INSN * insn;
2602{
2603 return CGEN_ASM_HASH_P (insn);
2604}
2605
2606static int
2607dis_hash_insn_p (insn)
2608 const CGEN_INSN * insn;
2609{
2610 /* If building the hash table and the NO-DIS attribute is present,
2611 ignore. */
2612 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2613 return 0;
2614 return CGEN_DIS_HASH_P (insn);
2615}
2616
2617/* The result is the hash value of the insn.
2618 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
9c03036a 2619
1294c286
DE		 2620static unsigned int
2621asm_hash_insn (mnem)
2622 const char * mnem;
9c03036a 2623{
1294c286 2624 return CGEN_ASM_HASH (mnem);
9c03036a
DE		 2625}
2626
1294c286
DE		 2627static unsigned int
2628dis_hash_insn (buf, value)
5d07b6cf 2629 const char * buf;
9c03036a
DE		 2630 unsigned long value;
2631{
2632 return CGEN_DIS_HASH (buf, value);
2633}
2634
1294c286 2635const CGEN_OPCODE_TABLE m32r_cgen_opcode_table =
5d07b6cf
DE		 2636{
2637 & m32r_cgen_hw_entries[0],
1294c286
DE		 2638 /*& m32r_cgen_operand_table[0], - FIXME:wip */
2639 & insn_table,
2640 & macro_insn_table,
2641 asm_hash_insn_p, asm_hash_insn, CGEN_ASM_HASH_SIZE,
2642 dis_hash_insn_p, dis_hash_insn, CGEN_DIS_HASH_SIZE
9c03036a
DE		 2643};
2644
2645void
2646m32r_cgen_init_tables (mach)
2647 int mach;
2648{
2649}
2650
fbc8134d
DE		 2651/* Getting values from cgen_fields is handled by a collection of functions.
2652 They are distinguished by the type of the VALUE argument they return.
2653 TODO: floating point, inlining support, remove cases where result type
2654 not appropriate. */
9c03036a 2655
fbc8134d
DE		 2656int
2657m32r_cgen_get_int_operand (opindex, fields)
9c03036a 2658 int opindex;
fbc8134d 2659 const CGEN_FIELDS * fields;
9c03036a 2660{
fbc8134d
DE		 2661 int value;
2662
9c03036a
DE		 2663 switch (opindex)
2664 {
23cf992f 2665 case M32R_OPERAND_SR :
fbc8134d 2666 value = fields->f_r2;
9c03036a 2667 break;
23cf992f 2668 case M32R_OPERAND_DR :
fbc8134d 2669 value = fields->f_r1;
9c03036a 2670 break;
23cf992f 2671 case M32R_OPERAND_SRC1 :
fbc8134d 2672 value = fields->f_r1;
9c03036a 2673 break;
23cf992f 2674 case M32R_OPERAND_SRC2 :
fbc8134d 2675 value = fields->f_r2;
9c03036a 2676 break;
23cf992f 2677 case M32R_OPERAND_SCR :
fbc8134d 2678 value = fields->f_r2;
9c03036a 2679 break;
23cf992f 2680 case M32R_OPERAND_DCR :
fbc8134d 2681 value = fields->f_r1;
9c03036a 2682 break;
23cf992f 2683 case M32R_OPERAND_SIMM8 :
fbc8134d 2684 value = fields->f_simm8;
9c03036a 2685 break;
23cf992f 2686 case M32R_OPERAND_SIMM16 :
fbc8134d 2687 value = fields->f_simm16;
9c03036a 2688 break;
23cf992f 2689 case M32R_OPERAND_UIMM4 :
fbc8134d 2690 value = fields->f_uimm4;
9c03036a 2691 break;
23cf992f 2692 case M32R_OPERAND_UIMM5 :
fbc8134d 2693 value = fields->f_uimm5;
9c03036a 2694 break;
23cf992f 2695 case M32R_OPERAND_UIMM16 :
fbc8134d 2696 value = fields->f_uimm16;
23cf992f 2697 break;
ab0bd049
DE		 2698/* start-sanitize-m32rx */
2699 case M32R_OPERAND_IMM1 :
fbc8134d 2700 value = fields->f_imm1;
ab0bd049
DE		 2701 break;
2702/* end-sanitize-m32rx */
2703/* start-sanitize-m32rx */
2704 case M32R_OPERAND_ACCD :
fbc8134d 2705 value = fields->f_accd;
ab0bd049
DE		 2706 break;
2707/* end-sanitize-m32rx */
7c26196f
DE		 2708/* start-sanitize-m32rx */
2709 case M32R_OPERAND_ACCS :
fbc8134d 2710 value = fields->f_accs;
7c26196f
DE		 2711 break;
2712/* end-sanitize-m32rx */
2713/* start-sanitize-m32rx */
2714 case M32R_OPERAND_ACC :
fbc8134d 2715 value = fields->f_acc;
7c26196f
DE		 2716 break;
2717/* end-sanitize-m32rx */
a6cefe4f 2718 case M32R_OPERAND_HASH :
fbc8134d 2719 value = fields->f_nil;
a6cefe4f 2720 break;
23cf992f 2721 case M32R_OPERAND_HI16 :
fbc8134d 2722 value = fields->f_hi16;
9c03036a 2723 break;
23cf992f 2724 case M32R_OPERAND_SLO16 :
fbc8134d 2725 value = fields->f_simm16;
9c03036a 2726 break;
23cf992f 2727 case M32R_OPERAND_ULO16 :
fbc8134d 2728 value = fields->f_uimm16;
9c03036a 2729 break;
23cf992f 2730 case M32R_OPERAND_UIMM24 :
fbc8134d 2731 value = fields->f_uimm24;
9c03036a 2732 break;
23cf992f 2733 case M32R_OPERAND_DISP8 :
fbc8134d 2734 value = fields->f_disp8;
9c03036a 2735 break;
23cf992f 2736 case M32R_OPERAND_DISP16 :
fbc8134d 2737 value = fields->f_disp16;
9c03036a 2738 break;
23cf992f 2739 case M32R_OPERAND_DISP24 :
fbc8134d 2740 value = fields->f_disp24;
9c03036a
DE		 2741 break;
2742
2743 default :
fbc8134d
DE		 2744 /* xgettext:c-format */
2745 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
9c03036a
DE		 2746 opindex);
2747 abort ();
2748 }
9c03036a 2749
fbc8134d
DE		 2750 return value;
2751}
9c03036a 2752
fbc8134d
DE		 2753bfd_vma
2754m32r_cgen_get_vma_operand (opindex, fields)
5d07b6cf 2755 int opindex;
853713a7 2756 const CGEN_FIELDS * fields;
9c03036a 2757{
fbc8134d 2758 bfd_vma value;
9c03036a
DE		 2759
2760 switch (opindex)
2761 {
23cf992f 2762 case M32R_OPERAND_SR :
9c03036a
DE		 2763 value = fields->f_r2;
2764 break;
23cf992f 2765 case M32R_OPERAND_DR :
9c03036a
DE		 2766 value = fields->f_r1;
2767 break;
23cf992f 2768 case M32R_OPERAND_SRC1 :
9c03036a
DE		 2769 value = fields->f_r1;
2770 break;
23cf992f 2771 case M32R_OPERAND_SRC2 :
9c03036a
DE		 2772 value = fields->f_r2;
2773 break;
23cf992f 2774 case M32R_OPERAND_SCR :
9c03036a
DE		 2775 value = fields->f_r2;
2776 break;
23cf992f 2777 case M32R_OPERAND_DCR :
9c03036a
DE		 2778 value = fields->f_r1;
2779 break;
23cf992f 2780 case M32R_OPERAND_SIMM8 :
9c03036a
DE		 2781 value = fields->f_simm8;
2782 break;
23cf992f 2783 case M32R_OPERAND_SIMM16 :
9c03036a
DE		 2784 value = fields->f_simm16;
2785 break;
23cf992f 2786 case M32R_OPERAND_UIMM4 :
9c03036a
DE		 2787 value = fields->f_uimm4;
2788 break;
23cf992f 2789 case M32R_OPERAND_UIMM5 :
9c03036a
DE		 2790 value = fields->f_uimm5;
2791 break;
23cf992f 2792 case M32R_OPERAND_UIMM16 :
9c03036a
DE		 2793 value = fields->f_uimm16;
2794 break;
ab0bd049
DE		 2795/* start-sanitize-m32rx */
2796 case M32R_OPERAND_IMM1 :
2797 value = fields->f_imm1;
2798 break;
2799/* end-sanitize-m32rx */
2800/* start-sanitize-m32rx */
2801 case M32R_OPERAND_ACCD :
2802 value = fields->f_accd;
2803 break;
2804/* end-sanitize-m32rx */
7c26196f
DE		 2805/* start-sanitize-m32rx */
2806 case M32R_OPERAND_ACCS :
2807 value = fields->f_accs;
2808 break;
2809/* end-sanitize-m32rx */
2810/* start-sanitize-m32rx */
2811 case M32R_OPERAND_ACC :
2812 value = fields->f_acc;
2813 break;
2814/* end-sanitize-m32rx */
a6cefe4f
DE		 2815 case M32R_OPERAND_HASH :
2816 value = fields->f_nil;
2817 break;
23cf992f 2818 case M32R_OPERAND_HI16 :
9c03036a
DE		 2819 value = fields->f_hi16;
2820 break;
23cf992f 2821 case M32R_OPERAND_SLO16 :
9c03036a
DE		 2822 value = fields->f_simm16;
2823 break;
23cf992f 2824 case M32R_OPERAND_ULO16 :
9c03036a
DE		 2825 value = fields->f_uimm16;
2826 break;
23cf992f 2827 case M32R_OPERAND_UIMM24 :
9c03036a
DE		 2828 value = fields->f_uimm24;
2829 break;
23cf992f 2830 case M32R_OPERAND_DISP8 :
9c03036a
DE		 2831 value = fields->f_disp8;
2832 break;
23cf992f 2833 case M32R_OPERAND_DISP16 :
9c03036a
DE		 2834 value = fields->f_disp16;
2835 break;
23cf992f 2836 case M32R_OPERAND_DISP24 :
9c03036a
DE		 2837 value = fields->f_disp24;
2838 break;
2839
2840 default :
fbc8134d
DE		 2841 /* xgettext:c-format */
2842 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
9c03036a
DE		 2843 opindex);
2844 abort ();
2845 }
2846
2847 return value;
2848}
2849
fbc8134d
DE		 2850/* Stuffing values in cgen_fields is handled by a collection of functions.
2851 They are distinguished by the type of the VALUE argument they accept.
2852 TODO: floating point, inlining support, remove cases where argument type
2853 not appropriate. */
2854
2855void
2856m32r_cgen_set_int_operand (opindex, fields, value)
2857 int opindex;
2858 CGEN_FIELDS * fields;
2859 int value;
2860{
2861 switch (opindex)
2862 {
2863 case M32R_OPERAND_SR :
2864 fields->f_r2 = value;
2865 break;
2866 case M32R_OPERAND_DR :
2867 fields->f_r1 = value;
2868 break;
2869 case M32R_OPERAND_SRC1 :
2870 fields->f_r1 = value;
2871 break;
2872 case M32R_OPERAND_SRC2 :
2873 fields->f_r2 = value;
2874 break;
2875 case M32R_OPERAND_SCR :
2876 fields->f_r2 = value;
2877 break;
2878 case M32R_OPERAND_DCR :
2879 fields->f_r1 = value;
2880 break;
2881 case M32R_OPERAND_SIMM8 :
2882 fields->f_simm8 = value;
2883 break;
2884 case M32R_OPERAND_SIMM16 :
2885 fields->f_simm16 = value;
2886 break;
2887 case M32R_OPERAND_UIMM4 :
2888 fields->f_uimm4 = value;
2889 break;
2890 case M32R_OPERAND_UIMM5 :
2891 fields->f_uimm5 = value;
2892 break;
2893 case M32R_OPERAND_UIMM16 :
2894 fields->f_uimm16 = value;
2895 break;
2896/* start-sanitize-m32rx */
2897 case M32R_OPERAND_IMM1 :
2898 fields->f_imm1 = value;
2899 break;
2900/* end-sanitize-m32rx */
2901/* start-sanitize-m32rx */
2902 case M32R_OPERAND_ACCD :
2903 fields->f_accd = value;
2904 break;
2905/* end-sanitize-m32rx */
2906/* start-sanitize-m32rx */
2907 case M32R_OPERAND_ACCS :
2908 fields->f_accs = value;
2909 break;
2910/* end-sanitize-m32rx */
2911/* start-sanitize-m32rx */
2912 case M32R_OPERAND_ACC :
2913 fields->f_acc = value;
2914 break;
2915/* end-sanitize-m32rx */
2916 case M32R_OPERAND_HASH :
2917 fields->f_nil = value;
2918 break;
2919 case M32R_OPERAND_HI16 :
2920 fields->f_hi16 = value;
2921 break;
2922 case M32R_OPERAND_SLO16 :
2923 fields->f_simm16 = value;
2924 break;
2925 case M32R_OPERAND_ULO16 :
2926 fields->f_uimm16 = value;
2927 break;
2928 case M32R_OPERAND_UIMM24 :
2929 fields->f_uimm24 = value;
2930 break;
2931 case M32R_OPERAND_DISP8 :
2932 fields->f_disp8 = value;
2933 break;
2934 case M32R_OPERAND_DISP16 :
2935 fields->f_disp16 = value;
2936 break;
2937 case M32R_OPERAND_DISP24 :
2938 fields->f_disp24 = value;
2939 break;
2940
2941 default :
2942 /* xgettext:c-format */
2943 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2944 opindex);
2945 abort ();
2946 }
2947}
2948
2949void
2950m32r_cgen_set_vma_operand (opindex, fields, value)
2951 int opindex;
2952 CGEN_FIELDS * fields;
2953 bfd_vma value;
2954{
2955 switch (opindex)
2956 {
2957 case M32R_OPERAND_SR :
2958 fields->f_r2 = value;
2959 break;
2960 case M32R_OPERAND_DR :
2961 fields->f_r1 = value;
2962 break;
2963 case M32R_OPERAND_SRC1 :
2964 fields->f_r1 = value;
2965 break;
2966 case M32R_OPERAND_SRC2 :
2967 fields->f_r2 = value;
2968 break;
2969 case M32R_OPERAND_SCR :
2970 fields->f_r2 = value;
2971 break;
2972 case M32R_OPERAND_DCR :
2973 fields->f_r1 = value;
2974 break;
2975 case M32R_OPERAND_SIMM8 :
2976 fields->f_simm8 = value;
2977 break;
2978 case M32R_OPERAND_SIMM16 :
2979 fields->f_simm16 = value;
2980 break;
2981 case M32R_OPERAND_UIMM4 :
2982 fields->f_uimm4 = value;
2983 break;
2984 case M32R_OPERAND_UIMM5 :
2985 fields->f_uimm5 = value;
2986 break;
2987 case M32R_OPERAND_UIMM16 :
2988 fields->f_uimm16 = value;
2989 break;
2990/* start-sanitize-m32rx */
2991 case M32R_OPERAND_IMM1 :
2992 fields->f_imm1 = value;
2993 break;
2994/* end-sanitize-m32rx */
2995/* start-sanitize-m32rx */
2996 case M32R_OPERAND_ACCD :
2997 fields->f_accd = value;
2998 break;
2999/* end-sanitize-m32rx */
3000/* start-sanitize-m32rx */
3001 case M32R_OPERAND_ACCS :
3002 fields->f_accs = value;
3003 break;
3004/* end-sanitize-m32rx */
3005/* start-sanitize-m32rx */
3006 case M32R_OPERAND_ACC :
3007 fields->f_acc = value;
3008 break;
3009/* end-sanitize-m32rx */
3010 case M32R_OPERAND_HASH :
3011 fields->f_nil = value;
3012 break;
3013 case M32R_OPERAND_HI16 :
3014 fields->f_hi16 = value;
3015 break;
3016 case M32R_OPERAND_SLO16 :
3017 fields->f_simm16 = value;
3018 break;
3019 case M32R_OPERAND_ULO16 :
3020 fields->f_uimm16 = value;
3021 break;
3022 case M32R_OPERAND_UIMM24 :
3023 fields->f_uimm24 = value;
3024 break;
3025 case M32R_OPERAND_DISP8 :
3026 fields->f_disp8 = value;
3027 break;
3028 case M32R_OPERAND_DISP16 :
3029 fields->f_disp16 = value;
3030 break;
3031 case M32R_OPERAND_DISP24 :
3032 fields->f_disp24 = value;
3033 break;
3034
3035 default :
3036 /* xgettext:c-format */
3037 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3038 opindex);
3039 abort ();
3040 }
3041}
3042
GDB Binutils - Deliverables
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