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Regenerated after modifying cgen/m32r.cpu to remove WRITE_LR and WRITE_SRC
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.h
CommitLineData
23cf992f
NC		 1/* Instruction description for m32r.
2
7c26196f
DE		 3This file is machine generated with CGEN.
4
5d07b6cf 5Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
23cf992f
NC		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#ifndef m32r_OPC_H
26#define m32r_OPC_H
27
28#define CGEN_ARCH m32r
35e689de 29
23cf992f
NC		 30/* Given symbol S, return m32r_cgen_<s>. */
31#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
32
35e689de
DE		 33/* Selected cpu families. */
34#define HAVE_CPU_M32R
7c26196f
DE		 35/* start-sanitize-m32rx */
36#define HAVE_CPU_M32RX
37/* end-sanitize-m32rx */
35e689de 38
23cf992f
NC		 39#define CGEN_WORD_BITSIZE 32
40#define CGEN_DEFAULT_INSN_BITSIZE 32
41#define CGEN_BASE_INSN_BITSIZE 32
42#define CGEN_MAX_INSN_BITSIZE 32
43#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
44#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
45#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
46#define CGEN_INT_INSN
47
23cf992f
NC		 48/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
49
50/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
51 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
52 we can't hash on everything up to the space. */
53#define CGEN_MNEMONIC_OPERANDS
54
23cf992f
NC		 55/* Enums. */
56
57/* Enum declaration for insn format enums. */
58typedef enum insn_op1 {
7c26196f
DE		 59 OP1_0, OP1_1, OP1_2, OP1_3
60 , OP1_4, OP1_5, OP1_6, OP1_7
61 , OP1_8, OP1_9, OP1_10, OP1_11
62 , OP1_12, OP1_13, OP1_14, OP1_15
23cf992f
NC		 63} INSN_OP1;
64
65/* Enum declaration for op2 enums. */
66typedef enum insn_op2 {
7c26196f
DE		 67 OP2_0, OP2_1, OP2_2, OP2_3
68 , OP2_4, OP2_5, OP2_6, OP2_7
69 , OP2_8, OP2_9, OP2_10, OP2_11
70 , OP2_12, OP2_13, OP2_14, OP2_15
23cf992f
NC		 71} INSN_OP2;
72
73/* Enum declaration for m32r operand types. */
74typedef enum cgen_operand_type {
7c26196f
DE		 75 M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
76 , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
77 , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
ab0bd049
DE		 78/* start-sanitize-m32rx */
79 , M32R_OPERAND_IMM1
80/* end-sanitize-m32rx */
81/* start-sanitize-m32rx */
82 , M32R_OPERAND_ACCD
83/* end-sanitize-m32rx */
7c26196f
DE		 84/* start-sanitize-m32rx */
85 , M32R_OPERAND_ACCS
86/* end-sanitize-m32rx */
87/* start-sanitize-m32rx */
88 , M32R_OPERAND_ACC
89/* end-sanitize-m32rx */
90 , M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
91 , M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
92 , M32R_OPERAND_ACCUM
93/* start-sanitize-m32rx */
94 , M32R_OPERAND_ABORT_PARALLEL_EXECUTION
95/* end-sanitize-m32rx */
96 , M32R_OPERAND_MAX
23cf992f
NC		 97} CGEN_OPERAND_TYPE;
98
99/* Non-boolean attributes. */
100
101/* Enum declaration for machine type selection. */
102typedef enum mach_attr {
7c26196f
DE		 103 MACH_M32R
104/* start-sanitize-m32rx */
105 , MACH_M32RX
106/* end-sanitize-m32rx */
107 , MACH_MAX
23cf992f
NC		 108} MACH_ATTR;
109
7c26196f
DE		 110/* start-sanitize-m32rx */
111/* Enum declaration for parallel execution pipeline selection. */
112typedef enum pipe_attr {
113 PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
114} PIPE_ATTR;
115
116/* end-sanitize-m32rx */
117/* Number of architecture variants. */
118#define MAX_MACHS ((int) MACH_MAX)
119
ab0bd049 120/* Number of operands types. */
7c26196f
DE		 121#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
122
ab0bd049
DE		 123/* Maximum number of operands referenced by any insn. */
124#define MAX_OPERAND_INSTANCES 8
125
23cf992f
NC		 126/* Operand and instruction attribute indices. */
127
128/* Enum declaration for cgen_operand attrs. */
129typedef enum cgen_operand_attr {
7c26196f
DE		 130 CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC
131 , CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
132 , CGEN_OPERAND_UNSIGNED
23cf992f
NC		 133} CGEN_OPERAND_ATTR;
134
7c26196f
DE		 135/* Number of non-boolean elements in cgen_operand. */
136#define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
137
23cf992f
NC		 138/* Enum declaration for cgen_insn attrs. */
139typedef enum cgen_insn_attr {
7c26196f
DE		 140 CGEN_INSN_MACH
141/* start-sanitize-m32rx */
142 , CGEN_INSN_PIPE
143/* end-sanitize-m32rx */
6eacba2e
NC		 144 , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
145 , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
23cf992f
NC		 146} CGEN_INSN_ATTR;
147
7c26196f
DE		 148/* Number of non-boolean elements in cgen_insn. */
149#define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)
150
23cf992f
NC		 151/* Insn types are used by the simulator. */
152/* Enum declaration for m32r instruction types. */
153typedef enum cgen_insn_type {
7c26196f
DE		 154 M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_ADD3_A
155 , M32R_INSN_AND, M32R_INSN_AND3, M32R_INSN_AND3_A, M32R_INSN_OR
156 , M32R_INSN_OR3, M32R_INSN_OR3_A, M32R_INSN_XOR, M32R_INSN_XOR3
157 , M32R_INSN_XOR3_A, M32R_INSN_ADDI, M32R_INSN_ADDI_A, M32R_INSN_ADDV
158 , M32R_INSN_ADDV3, M32R_INSN_ADDV3_A, M32R_INSN_ADDX, M32R_INSN_BC8
159 , M32R_INSN_BC8_S, M32R_INSN_BC24, M32R_INSN_BC24_L, M32R_INSN_BEQ
160 , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
161 , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL8_S
162 , M32R_INSN_BL24, M32R_INSN_BL24_L
163/* start-sanitize-m32rx */
164 , M32R_INSN_BCL8
165/* end-sanitize-m32rx */
166/* start-sanitize-m32rx */
167 , M32R_INSN_BCL8_S
168/* end-sanitize-m32rx */
169/* start-sanitize-m32rx */
170 , M32R_INSN_BCL24
171/* end-sanitize-m32rx */
172/* start-sanitize-m32rx */
173 , M32R_INSN_BCL24_L
174/* end-sanitize-m32rx */
175 , M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L
176 , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24
177 , M32R_INSN_BRA24_L
178/* start-sanitize-m32rx */
179 , M32R_INSN_BNCL8
180/* end-sanitize-m32rx */
181/* start-sanitize-m32rx */
182 , M32R_INSN_BNCL8_S
183/* end-sanitize-m32rx */
184/* start-sanitize-m32rx */
185 , M32R_INSN_BNCL24
186/* end-sanitize-m32rx */
187/* start-sanitize-m32rx */
188 , M32R_INSN_BNCL24_L
189/* end-sanitize-m32rx */
190 , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPI_A, M32R_INSN_CMPU
191 , M32R_INSN_CMPUI, M32R_INSN_CMPUI_A
192/* start-sanitize-m32rx */
193 , M32R_INSN_CMPEQ
194/* end-sanitize-m32rx */
195/* start-sanitize-m32rx */
196 , M32R_INSN_CMPZ
197/* end-sanitize-m32rx */
198 , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
ab0bd049
DE		 199/* start-sanitize-m32rx */
200 , M32R_INSN_DIVH
201/* end-sanitize-m32rx */
7c26196f
DE		 202/* start-sanitize-m32rx */
203 , M32R_INSN_JC
204/* end-sanitize-m32rx */
205/* start-sanitize-m32rx */
206 , M32R_INSN_JNC
207/* end-sanitize-m32rx */
208 , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_2
209 , M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, M32R_INSN_LDB_2
210 , M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, M32R_INSN_LDH_2
211 , M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, M32R_INSN_LDUB_2
212 , M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, M32R_INSN_LDUH_2
213 , M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, M32R_INSN_LD24
214 , M32R_INSN_LD24_A, M32R_INSN_LDI8, M32R_INSN_LDI8_A, M32R_INSN_LDI8A
215 , M32R_INSN_LDI8A_A, M32R_INSN_LDI16, M32R_INSN_LDI16A, M32R_INSN_LOCK
216 , M32R_INSN_MACHI
217/* start-sanitize-m32rx */
218 , M32R_INSN_MACHI_A
219/* end-sanitize-m32rx */
220 , M32R_INSN_MACLO
221/* start-sanitize-m32rx */
222 , M32R_INSN_MACLO_A
223/* end-sanitize-m32rx */
224 , M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI
225/* start-sanitize-m32rx */
226 , M32R_INSN_MULHI_A
227/* end-sanitize-m32rx */
228 , M32R_INSN_MULLO
229/* start-sanitize-m32rx */
230 , M32R_INSN_MULLO_A
231/* end-sanitize-m32rx */
232 , M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI
233/* start-sanitize-m32rx */
234 , M32R_INSN_MVFACHI_A
235/* end-sanitize-m32rx */
236 , M32R_INSN_MVFACLO
237/* start-sanitize-m32rx */
238 , M32R_INSN_MVFACLO_A
239/* end-sanitize-m32rx */
240 , M32R_INSN_MVFACMI
241/* start-sanitize-m32rx */
242 , M32R_INSN_MVFACMI_A
243/* end-sanitize-m32rx */
244 , M32R_INSN_MVFC, M32R_INSN_MVTACHI
245/* start-sanitize-m32rx */
246 , M32R_INSN_MVTACHI_A
247/* end-sanitize-m32rx */
248 , M32R_INSN_MVTACLO
249/* start-sanitize-m32rx */
250 , M32R_INSN_MVTACLO_A
251/* end-sanitize-m32rx */
252 , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
253 , M32R_INSN_RAC
254/* start-sanitize-m32rx */
ab0bd049
DE		 255 , M32R_INSN_RAC_D
256/* end-sanitize-m32rx */
257/* start-sanitize-m32rx */
258 , M32R_INSN_RAC_DS
259/* end-sanitize-m32rx */
260/* start-sanitize-m32rx */
261 , M32R_INSN_RAC_DSI
7c26196f
DE		 262/* end-sanitize-m32rx */
263 , M32R_INSN_RACH
264/* start-sanitize-m32rx */
ab0bd049
DE		 265 , M32R_INSN_RACH_D
266/* end-sanitize-m32rx */
267/* start-sanitize-m32rx */
268 , M32R_INSN_RACH_DS
269/* end-sanitize-m32rx */
270/* start-sanitize-m32rx */
271 , M32R_INSN_RACH_DSI
7c26196f
DE		 272/* end-sanitize-m32rx */
273 , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
274 , M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
275 , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRA3_A, M32R_INSN_SRAI
276 , M32R_INSN_SRAI_A, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRL3_A
277 , M32R_INSN_SRLI, M32R_INSN_SRLI_A, M32R_INSN_ST, M32R_INSN_ST_2
278 , M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2
279 , M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2
280 , M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS
281 , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
282 , M32R_INSN_TRAP_A, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP
283/* start-sanitize-m32rx */
284 , M32R_INSN_SATB
285/* end-sanitize-m32rx */
286/* start-sanitize-m32rx */
287 , M32R_INSN_SATH
288/* end-sanitize-m32rx */
289/* start-sanitize-m32rx */
290 , M32R_INSN_SAT
291/* end-sanitize-m32rx */
292/* start-sanitize-m32rx */
293 , M32R_INSN_PCMPBZ
294/* end-sanitize-m32rx */
295/* start-sanitize-m32rx */
296 , M32R_INSN_SADD
297/* end-sanitize-m32rx */
298/* start-sanitize-m32rx */
299 , M32R_INSN_MACWU1
300/* end-sanitize-m32rx */
301/* start-sanitize-m32rx */
302 , M32R_INSN_MSBLO
303/* end-sanitize-m32rx */
304/* start-sanitize-m32rx */
305 , M32R_INSN_MULWU1
306/* end-sanitize-m32rx */
307/* start-sanitize-m32rx */
ab0bd049 308 , M32R_INSN_MACLH1
7c26196f
DE		 309/* end-sanitize-m32rx */
310/* start-sanitize-m32rx */
311 , M32R_INSN_SC
312/* end-sanitize-m32rx */
313/* start-sanitize-m32rx */
314 , M32R_INSN_SNC
315/* end-sanitize-m32rx */
316 , M32R_INSN_MAX
23cf992f
NC		 317} CGEN_INSN_TYPE;
318
319/* Index of `illegal' insn place holder. */
320#define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
321/* Total number of insns in table. */
7c26196f 322#define MAX_INSNS ((int) M32R_INSN_MAX)
23cf992f
NC		 323
324/* cgen.h uses things we just defined. */
325#include "opcode/cgen.h"
326
327/* This struct records data prior to insertion or after extraction. */
ab0bd049 328struct cgen_fields
5d07b6cf
DE		 329{
330 long f_nil;
23cf992f
NC		 331 long f_op1;
332 long f_op2;
333 long f_cond;
334 long f_r1;
335 long f_r2;
336 long f_simm8;
337 long f_simm16;
338 long f_shift_op2;
339 long f_uimm4;
340 long f_uimm5;
341 long f_uimm16;
342 long f_uimm24;
343 long f_hi16;
344 long f_disp8;
345 long f_disp16;
346 long f_disp24;
7c26196f
DE		 347/* start-sanitize-m32rx */
348 long f_op23;
349/* end-sanitize-m32rx */
350/* start-sanitize-m32rx */
351 long f_op3;
352/* end-sanitize-m32rx */
353/* start-sanitize-m32rx */
354 long f_acc;
355/* end-sanitize-m32rx */
356/* start-sanitize-m32rx */
357 long f_accs;
ab0bd049
DE		 358/* end-sanitize-m32rx */
359/* start-sanitize-m32rx */
360 long f_accd;
361/* end-sanitize-m32rx */
362/* start-sanitize-m32rx */
363 long f_bits67;
364/* end-sanitize-m32rx */
365/* start-sanitize-m32rx */
366 long f_bit14;
367/* end-sanitize-m32rx */
368/* start-sanitize-m32rx */
369 long f_imm1;
7c26196f 370/* end-sanitize-m32rx */
23cf992f 371 int length;
ab0bd049 372};
23cf992f
NC		 373
374/* Attributes. */
375extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
376extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
377
ab0bd049
DE		 378/* Enum declaration for m32r hardware types. */
379typedef enum hw_type {
380 HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
381 , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
382 , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
383/* start-sanitize-m32rx */
384 , HW_H_ACCUMS
385/* end-sanitize-m32rx */
386/* start-sanitize-m32rx */
387 , HW_H_ABORT
388/* end-sanitize-m32rx */
389 , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
390 , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_MAX
391} HW_TYPE;
392
393#define MAX_HW ((int) HW_MAX)
394
395/* Hardware decls. */
396
23cf992f
NC		 397extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
398extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
7c26196f
DE		 399/* start-sanitize-m32rx */
400extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
401/* end-sanitize-m32rx */
23cf992f
NC		 402
403#define CGEN_INIT_PARSE() \
404{\
405}
406#define CGEN_INIT_INSERT() \
407{\
408}
409#define CGEN_INIT_EXTRACT() \
410{\
411}
412#define CGEN_INIT_PRINT() \
413{\
414}
415
416/* -- opc.h */
417
418#undef CGEN_DIS_HASH_SIZE
419#define CGEN_DIS_HASH_SIZE 256
420#undef CGEN_DIS_HASH
421#define X(b) (((unsigned char *) (b))[0] & 0xf0)
422#define CGEN_DIS_HASH(buffer, insn) \
423(X (buffer) | \
424 (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
425 : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
ab0bd049 426 : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
23cf992f
NC		 427 : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
428
429/* -- */
430
431
432#endif /* m32r_OPC_H */
GDB Binutils - Deliverables
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