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Change source files over to GPLv3.
[deliverable/binutils-gdb.git] / opcodes / mep-desc.c
CommitLineData
bd2f2e55
DB		 1/* CPU data for mep.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
9b201bb5 5Copyright 1996-2007 Free Software Foundation, Inc.
bd2f2e55
DB		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9b201bb5
NC		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
bd2f2e55 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
bd2f2e55 18
9b201bb5
NC		 19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
bd2f2e55
DB		 22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "mep-desc.h"
32#include "mep-opc.h"
33#include "opintl.h"
34#include "libiberty.h"
35#include "xregex.h"
36
37/* Attributes. */
38
39static const CGEN_ATTR_ENTRY bool_attr[] =
40{
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44};
45
46static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47{
48 { "base", MACH_BASE },
49 { "mep", MACH_MEP },
50 { "h1", MACH_H1 },
51 { "max", MACH_MAX },
52 { 0, 0 }
53};
54
55static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
56{
57 { "mep", ISA_MEP },
58 { "ext_core1", ISA_EXT_CORE1 },
59 { "ext_core2", ISA_EXT_CORE2 },
60 { "ext_cop2_16", ISA_EXT_COP2_16 },
61 { "ext_cop2_32", ISA_EXT_COP2_32 },
62 { "ext_cop2_48", ISA_EXT_COP2_48 },
63 { "ext_cop2_64", ISA_EXT_COP2_64 },
64 { "max", ISA_MAX },
65 { 0, 0 }
66};
67
68static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
69{
70 { "LABEL", CDATA_LABEL },
71 { "REGNUM", CDATA_REGNUM },
72 { "FMAX_FLOAT", CDATA_FMAX_FLOAT },
73 { "FMAX_INT", CDATA_FMAX_INT },
74 { "POINTER", CDATA_POINTER },
75 { "LONG", CDATA_LONG },
76 { "ULONG", CDATA_ULONG },
77 { "SHORT", CDATA_SHORT },
78 { "USHORT", CDATA_USHORT },
79 { "CHAR", CDATA_CHAR },
80 { "UCHAR", CDATA_UCHAR },
81 { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
82 { 0, 0 }
83};
84
85static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
86{
87 {"integer", 1},
88 { 0, 0 }
89};
90
91static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
92{
93 {"integer", 0},
94 { 0, 0 }
95};
96
97static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
98{
99 { "NONE", CONFIG_NONE },
100 { "simple", CONFIG_SIMPLE },
101 { "fmax", CONFIG_FMAX },
102 { 0, 0 }
103};
104
105const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
106{
107 { "MACH", & MACH_attr[0], & MACH_attr[0] },
108 { "ISA", & ISA_attr[0], & ISA_attr[0] },
109 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
110 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
111 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
112 { "RESERVED", &bool_attr[0], &bool_attr[0] },
113 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
114 { "SIGNED", &bool_attr[0], &bool_attr[0] },
115 { 0, 0, 0 }
116};
117
118const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
119{
120 { "MACH", & MACH_attr[0], & MACH_attr[0] },
121 { "ISA", & ISA_attr[0], & ISA_attr[0] },
122 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
123 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
124 { "PC", &bool_attr[0], &bool_attr[0] },
125 { "PROFILE", &bool_attr[0], &bool_attr[0] },
126 { "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
127 { 0, 0, 0 }
128};
129
130const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
131{
132 { "MACH", & MACH_attr[0], & MACH_attr[0] },
133 { "ISA", & ISA_attr[0], & ISA_attr[0] },
134 { "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
135 { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
136 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
137 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
138 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
139 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
140 { "SIGNED", &bool_attr[0], &bool_attr[0] },
141 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
142 { "RELAX", &bool_attr[0], &bool_attr[0] },
143 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
144 { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
145 { 0, 0, 0 }
146};
147
148const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
149{
150 { "MACH", & MACH_attr[0], & MACH_attr[0] },
151 { "ISA", & ISA_attr[0], & ISA_attr[0] },
152 { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
153 { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
154 { "ALIAS", &bool_attr[0], &bool_attr[0] },
155 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
156 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
157 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
158 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
159 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
160 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
161 { "RELAXED", &bool_attr[0], &bool_attr[0] },
162 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
163 { "PBB", &bool_attr[0], &bool_attr[0] },
164 { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
165 { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
166 { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
167 { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
168 { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
169 { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
170 { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
171 { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
172 { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
173 { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
174 { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
175 { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
176 { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
177 { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
178 { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
179 { "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
180 { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
181 { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
182 { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
183 { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
184 { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
185 { "VOLATILE", &bool_attr[0], &bool_attr[0] },
186 { 0, 0, 0 }
187};
188
189/* Instruction set variants. */
190
191static const CGEN_ISA mep_cgen_isa_table[] = {
192 { "mep", 32, 32, 16, 32 },
193 { "ext_core1", 32, 32, 16, 32 },
194 { "ext_core2", 32, 32, 16, 32 },
195 { "ext_cop2_16", 32, 32, 65535, 0 },
196 { "ext_cop2_32", 32, 32, 65535, 0 },
197 { "ext_cop2_48", 32, 32, 65535, 0 },
198 { "ext_cop2_64", 32, 32, 65535, 0 },
199 { 0, 0, 0, 0, 0 }
200};
201
202/* Machine variants. */
203
204static const CGEN_MACH mep_cgen_mach_table[] = {
205 { "mep", "mep", MACH_MEP, 16 },
206 { "h1", "h1", MACH_H1, 16 },
207 { 0, 0, 0, 0 }
208};
209
210static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
211{
212 { "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
213 { "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
214 { "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
215 { "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
216 { "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
217 { "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
218 { "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
219 { "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
220 { "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
221 { "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
222 { "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
223 { "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
224 { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
225 { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
226 { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
227 { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
228 { "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
229 { "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
230 { "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
231 { "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
232};
233
234CGEN_KEYWORD mep_cgen_opval_h_gpr =
235{
236 & mep_cgen_opval_h_gpr_entries[0],
237 20,
238 0, 0, 0, 0, ""
239};
240
241static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
242{
243 { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
244 { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
245 { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
246 { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
247 { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
248 { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
249 { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
250 { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
251 { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
252 { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
253 { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
254 { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
255 { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
256 { "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
257 { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
258 { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
259 { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
260 { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
261 { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
262 { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
263 { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
264 { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
265 { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
266 { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 }
267};
268
269CGEN_KEYWORD mep_cgen_opval_h_csr =
270{
271 & mep_cgen_opval_h_csr_entries[0],
272 24,
273 0, 0, 0, 0, ""
274};
275
276static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
277{
278 { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
279 { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
280 { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
281 { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
282 { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
283 { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
284 { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
285 { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
286 { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
287 { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
288 { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
289 { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
290 { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
291 { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
292 { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
293 { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
294 { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
295 { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
296 { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
297 { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
298 { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
299 { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
300 { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
301 { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
302 { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
303 { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
304 { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
305 { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
306 { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
307 { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
308 { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
309 { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
310};
311
312CGEN_KEYWORD mep_cgen_opval_h_cr64 =
313{
314 & mep_cgen_opval_h_cr64_entries[0],
315 32,
316 0, 0, 0, 0, ""
317};
318
319static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
320{
321 { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
322 { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
323 { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
324 { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
325 { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
326 { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
327 { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
328 { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
329 { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
330 { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
331 { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
332 { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
333 { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
334 { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
335 { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
336 { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
337 { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
338 { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
339 { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
340 { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
341 { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
342 { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
343 { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
344 { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
345 { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
346 { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
347 { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
348 { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
349 { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
350 { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
351 { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
352 { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
353};
354
355CGEN_KEYWORD mep_cgen_opval_h_cr =
356{
357 & mep_cgen_opval_h_cr_entries[0],
358 32,
359 0, 0, 0, 0, ""
360};
361
362static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
363{
364 { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
365 { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
366 { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
367 { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
368 { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
369 { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
370 { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
371 { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
372 { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
373 { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
374 { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
375 { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
376 { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
377 { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
378 { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
379 { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
380 { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
381 { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
382 { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
383 { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
384 { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
385 { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
386 { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
387 { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
388 { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
389 { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
390 { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
391 { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
392 { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
393 { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
394 { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
395 { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
396 { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
397 { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
398 { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
399 { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
400 { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
401 { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
402 { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
403 { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
404 { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
405 { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
406 { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
407 { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
408 { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
409 { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
410 { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
411 { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
412 { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
413 { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
414 { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
415 { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
416 { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
417 { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
418 { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
419 { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
420 { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
421 { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
422 { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
423 { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
424 { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
425 { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
426 { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
427 { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
428};
429
430CGEN_KEYWORD mep_cgen_opval_h_ccr =
431{
432 & mep_cgen_opval_h_ccr_entries[0],
433 64,
434 0, 0, 0, 0, ""
435};
436
437static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_fmax_entries[] =
438{
439 { "$fr0", 0, {0, {{{0, 0}}}}, 0, 0 },
440 { "$fr1", 1, {0, {{{0, 0}}}}, 0, 0 },
441 { "$fr2", 2, {0, {{{0, 0}}}}, 0, 0 },
442 { "$fr3", 3, {0, {{{0, 0}}}}, 0, 0 },
443 { "$fr4", 4, {0, {{{0, 0}}}}, 0, 0 },
444 { "$fr5", 5, {0, {{{0, 0}}}}, 0, 0 },
445 { "$fr6", 6, {0, {{{0, 0}}}}, 0, 0 },
446 { "$fr7", 7, {0, {{{0, 0}}}}, 0, 0 },
447 { "$fr8", 8, {0, {{{0, 0}}}}, 0, 0 },
448 { "$fr9", 9, {0, {{{0, 0}}}}, 0, 0 },
449 { "$fr10", 10, {0, {{{0, 0}}}}, 0, 0 },
450 { "$fr11", 11, {0, {{{0, 0}}}}, 0, 0 },
451 { "$fr12", 12, {0, {{{0, 0}}}}, 0, 0 },
452 { "$fr13", 13, {0, {{{0, 0}}}}, 0, 0 },
453 { "$fr14", 14, {0, {{{0, 0}}}}, 0, 0 },
454 { "$fr15", 15, {0, {{{0, 0}}}}, 0, 0 },
455 { "$fr16", 16, {0, {{{0, 0}}}}, 0, 0 },
456 { "$fr17", 17, {0, {{{0, 0}}}}, 0, 0 },
457 { "$fr18", 18, {0, {{{0, 0}}}}, 0, 0 },
458 { "$fr19", 19, {0, {{{0, 0}}}}, 0, 0 },
459 { "$fr20", 20, {0, {{{0, 0}}}}, 0, 0 },
460 { "$fr21", 21, {0, {{{0, 0}}}}, 0, 0 },
461 { "$fr22", 22, {0, {{{0, 0}}}}, 0, 0 },
462 { "$fr23", 23, {0, {{{0, 0}}}}, 0, 0 },
463 { "$fr24", 24, {0, {{{0, 0}}}}, 0, 0 },
464 { "$fr25", 25, {0, {{{0, 0}}}}, 0, 0 },
465 { "$fr26", 26, {0, {{{0, 0}}}}, 0, 0 },
466 { "$fr27", 27, {0, {{{0, 0}}}}, 0, 0 },
467 { "$fr28", 28, {0, {{{0, 0}}}}, 0, 0 },
468 { "$fr29", 29, {0, {{{0, 0}}}}, 0, 0 },
469 { "$fr30", 30, {0, {{{0, 0}}}}, 0, 0 },
470 { "$fr31", 31, {0, {{{0, 0}}}}, 0, 0 },
471 { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
472 { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
473 { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
474 { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
475 { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
476 { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
477 { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
478 { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
479 { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
480 { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
481 { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
482 { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
483 { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
484 { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
485 { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
486 { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
487 { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
488 { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
489 { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
490 { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
491 { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
492 { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
493 { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
494 { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
495 { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
496 { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
497 { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
498 { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
499 { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
500 { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
501 { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
502 { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
503};
504
505CGEN_KEYWORD mep_cgen_opval_h_cr_fmax =
506{
507 & mep_cgen_opval_h_cr_fmax_entries[0],
508 64,
509 0, 0, 0, 0, ""
510};
511
512static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_fmax_entries[] =
513{
514 { "$cirr", 0, {0, {{{0, 0}}}}, 0, 0 },
515 { "$fcr0", 0, {0, {{{0, 0}}}}, 0, 0 },
516 { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
517 { "$cbcr", 1, {0, {{{0, 0}}}}, 0, 0 },
518 { "$fcr1", 1, {0, {{{0, 0}}}}, 0, 0 },
519 { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
520 { "$cerr", 15, {0, {{{0, 0}}}}, 0, 0 },
521 { "$fcr15", 15, {0, {{{0, 0}}}}, 0, 0 },
522 { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 }
523};
524
525CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax =
526{
527 & mep_cgen_opval_h_ccr_fmax_entries[0],
528 9,
529 0, 0, 0, 0, ""
530};
531
532
533/* The hardware table. */
534
535#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
536#define A(a) (1 << CGEN_HW_##a)
537#else
538#define A(a) (1 << CGEN_HW_/**/a)
539#endif
540
541const CGEN_HW_ENTRY mep_cgen_hw_table[] =
542{
543 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
544 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
545 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
546 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
547 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
548 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
549 { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
550 { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
551 { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
552 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
553 { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
554 { "h-cr-fmax", HW_H_CR_FMAX, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_fmax, { 0|A(IS_FLOAT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
555 { "h-ccr-fmax", HW_H_CCR_FMAX, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_fmax, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
556 { "h-fmax-compare-i-p", HW_H_FMAX_COMPARE_I_P, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
557 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
558};
559
560#undef A
561
562
563/* The instruction field table. */
564
565#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
566#define A(a) (1 << CGEN_IFLD_##a)
567#else
568#define A(a) (1 << CGEN_IFLD_/**/a)
569#endif
570
571const CGEN_IFLD mep_cgen_ifld_table[] =
572{
573 { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
574 { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
575 { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
576 { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
577 { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
578 { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
579 { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
580 { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
581 { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
582 { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
583 { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
584 { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
585 { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
586 { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
587 { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
588 { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
589 { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
590 { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
591 { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
592 { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
593 { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
594 { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
595 { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
596 { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
597 { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
598 { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
599 { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
600 { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
601 { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
602 { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
603 { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
604 { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
605 { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
606 { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
607 { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
608 { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
609 { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
610 { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
611 { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
612 { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
613 { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
614 { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
615 { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
616 { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
617 { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
618 { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
619 { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
620 { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
621 { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
622 { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
623 { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
624 { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
625 { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
626 { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
627 { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
628 { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
629 { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
630 { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
631 { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
632 { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
633 { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
634 { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
635 { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
636 { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
637 { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
638 { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
639 { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
640 { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
641 { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
642 { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
643 { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
644 { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
645 { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
646 { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
647 { MEP_F_8S24, "f-8s24", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
648 { MEP_F_8S24A2, "f-8s24a2", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
649 { MEP_F_8S24A4, "f-8s24a4", 0, 32, 24, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
650 { MEP_F_8S24A8, "f-8s24a8", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
651 { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
652 { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
653 { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
654 { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
655 { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
656 { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
657 { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
658 { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
659 { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
660 { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
661 { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
662 { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
663 { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } },
664 { MEP_F_FMAX_0_4, "f-fmax-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
665 { MEP_F_FMAX_4_4, "f-fmax-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
666 { MEP_F_FMAX_8_4, "f-fmax-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
667 { MEP_F_FMAX_12_4, "f-fmax-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
668 { MEP_F_FMAX_16_4, "f-fmax-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
669 { MEP_F_FMAX_20_4, "f-fmax-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
670 { MEP_F_FMAX_24_4, "f-fmax-24-4", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
671 { MEP_F_FMAX_28_1, "f-fmax-28-1", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
672 { MEP_F_FMAX_29_1, "f-fmax-29-1", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
673 { MEP_F_FMAX_30_1, "f-fmax-30-1", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
674 { MEP_F_FMAX_31_1, "f-fmax-31-1", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
675 { MEP_F_FMAX_FRD, "f-fmax-frd", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
676 { MEP_F_FMAX_FRN, "f-fmax-frn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
677 { MEP_F_FMAX_FRM, "f-fmax-frm", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
678 { MEP_F_FMAX_RM, "f-fmax-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
679 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
680};
681
682#undef A
683
684
685
686/* multi ifield declarations */
687
688const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
689const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
690const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
691const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
692const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
693const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
694const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
695const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
696const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
697const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRD_MULTI_IFIELD [];
698const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRN_MULTI_IFIELD [];
699const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRM_MULTI_IFIELD [];
700
701
702/* multi ifield definitions */
703
704const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
705{
706 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
707 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
708 { 0, { (const PTR) 0 } }
709};
710const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
711{
712 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
713 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
714 { 0, { (const PTR) 0 } }
715};
716const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
717{
718 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
719 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
720 { 0, { (const PTR) 0 } }
721};
722const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
723{
724 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
725 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
726 { 0, { (const PTR) 0 } }
727};
728const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
729{
730 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
731 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
732 { 0, { (const PTR) 0 } }
733};
734const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
735{
736 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
737 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
738 { 0, { (const PTR) 0 } }
739};
740const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
741{
742 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
743 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
744 { 0, { (const PTR) 0 } }
745};
746const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
747{
748 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
749 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
750 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
751 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
752 { 0, { (const PTR) 0 } }
753};
754const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
755{
756 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
757 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
758 { 0, { (const PTR) 0 } }
759};
760const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRD_MULTI_IFIELD [] =
761{
762 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_28_1] } },
763 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_4_4] } },
764 { 0, { (const PTR) 0 } }
765};
766const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRN_MULTI_IFIELD [] =
767{
768 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_29_1] } },
769 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_20_4] } },
770 { 0, { (const PTR) 0 } }
771};
772const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRM_MULTI_IFIELD [] =
773{
774 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_30_1] } },
775 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_24_4] } },
776 { 0, { (const PTR) 0 } }
777};
778
779/* The operand table. */
780
781#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
782#define A(a) (1 << CGEN_OPERAND_##a)
783#else
784#define A(a) (1 << CGEN_OPERAND_/**/a)
785#endif
786#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
787#define OPERAND(op) MEP_OPERAND_##op
788#else
789#define OPERAND(op) MEP_OPERAND_/**/op
790#endif
791
792const CGEN_OPERAND mep_cgen_operand_table[] =
793{
794/* pc: program counter */
795 { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
796 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
797 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
798/* r0: register 0 */
799 { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
800 { 0, { (const PTR) 0 } },
801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
802/* rn: register Rn */
803 { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
804 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
805 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
806/* rm: register Rm */
807 { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
808 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
810/* rl: register Rl */
811 { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
812 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
813 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
814/* rn3: register 0-7 */
815 { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
816 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
817 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
818/* rma: register Rm holding pointer */
819 { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
820 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } } },
822/* rnc: register Rn holding char */
823 { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
824 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
825 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CHAR, 0 } }, { { 1, 0 } } } } },
826/* rnuc: register Rn holding unsigned char */
827 { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
828 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_UCHAR, 0 } }, { { 1, 0 } } } } },
830/* rns: register Rn holding short */
831 { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
832 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
833 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_SHORT, 0 } }, { { 1, 0 } } } } },
834/* rnus: register Rn holding unsigned short */
835 { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
836 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
837 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_USHORT, 0 } }, { { 1, 0 } } } } },
838/* rnl: register Rn holding long */
839 { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
840 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
842/* rnul: register Rn holding unsigned long */
843 { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
844 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
845 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
846/* rn3c: register 0-7 holding unsigned char */
847 { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
848 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CHAR, 0 } }, { { 1, 0 } } } } },
850/* rn3uc: register 0-7 holding byte */
851 { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
852 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
853 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_UCHAR, 0 } }, { { 1, 0 } } } } },
854/* rn3s: register 0-7 holding unsigned short */
855 { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
856 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
857 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_SHORT, 0 } }, { { 1, 0 } } } } },
858/* rn3us: register 0-7 holding short */
859 { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
860 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_USHORT, 0 } }, { { 1, 0 } } } } },
862/* rn3l: register 0-7 holding unsigned long */
863 { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
864 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
865 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
866/* rn3ul: register 0-7 holding long */
867 { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
868 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
870/* lp: link pointer */
871 { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
872 { 0, { (const PTR) 0 } },
873 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
874/* sar: shift amount register */
875 { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
876 { 0, { (const PTR) 0 } },
877 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
878/* hi: high result */
879 { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
880 { 0, { (const PTR) 0 } },
881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
882/* lo: low result */
883 { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
884 { 0, { (const PTR) 0 } },
885 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
886/* mb0: modulo begin register 0 */
887 { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
888 { 0, { (const PTR) 0 } },
889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
890/* me0: modulo end register 0 */
891 { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
892 { 0, { (const PTR) 0 } },
893 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
894/* mb1: modulo begin register 1 */
895 { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
896 { 0, { (const PTR) 0 } },
897 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
898/* me1: modulo end register 1 */
899 { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
900 { 0, { (const PTR) 0 } },
901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
902/* psw: program status word */
903 { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
904 { 0, { (const PTR) 0 } },
905 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
906/* epc: exception prog counter */
907 { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
908 { 0, { (const PTR) 0 } },
909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
910/* exc: exception cause */
911 { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
912 { 0, { (const PTR) 0 } },
913 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
914/* npc: nmi program counter */
915 { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
916 { 0, { (const PTR) 0 } },
917 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
918/* dbg: debug register */
919 { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
920 { 0, { (const PTR) 0 } },
921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
922/* depc: debug exception pc */
923 { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
924 { 0, { (const PTR) 0 } },
925 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
926/* opt: option register */
927 { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
928 { 0, { (const PTR) 0 } },
929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
930/* r1: register 1 */
931 { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
932 { 0, { (const PTR) 0 } },
933 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
934/* tp: tiny data area pointer */
935 { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
936 { 0, { (const PTR) 0 } },
937 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
938/* sp: stack pointer */
939 { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
940 { 0, { (const PTR) 0 } },
941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
942/* tpr: comment */
943 { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
944 { 0, { (const PTR) 0 } },
945 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
946/* spr: comment */
947 { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
948 { 0, { (const PTR) 0 } },
949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
950/* csrn: control/special register */
951 { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
952 { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
953 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
954/* csrn-idx: control/special reg idx */
955 { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
956 { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
957 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
958/* crn64: copro Rn (64-bit) */
959 { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
960 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
962/* crn: copro Rn (32-bit) */
963 { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
964 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
965 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
966/* crnx64: copro Rn (0-31, 64-bit) */
967 { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
968 { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
969 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
970/* crnx: copro Rn (0-31, 32-bit) */
971 { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
972 { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
973 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
974/* ccrn: copro control reg CCRn */
975 { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
976 { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
977 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
978/* cccc: copro flags */
979 { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
980 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
982/* pcrel8a2: comment */
983 { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
984 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
985 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
986/* pcrel12a2: comment */
987 { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
988 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
989 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
990/* pcrel17a2: comment */
991 { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
992 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
993 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
994/* pcrel24a2: comment */
995 { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
996 { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
997 { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
998/* pcabs24a2: comment */
999 { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
1000 { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
1001 { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
1002/* sdisp16: comment */
1003 { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
1004 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1005 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1006/* simm16: comment */
1007 { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
1008 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1010/* uimm16: comment */
1011 { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
1012 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1013 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1014/* code16: uci/dsp code (16 bits) */
1015 { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
1016 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1017 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1018/* udisp2: SSARB addend (2 bits) */
1019 { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
1020 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
1021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1022/* uimm2: interrupt (2 bits) */
1023 { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
1024 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
1025 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1026/* simm6: add const (6 bits) */
1027 { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
1028 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
1029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1030/* simm8: mov const (8 bits) */
1031 { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
1032 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
1033 { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1034/* addr24a4: comment */
1035 { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
1036 { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
1037 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
1038/* code24: coprocessor code */
1039 { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
1040 { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
1041 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1042/* callnum: system call number */
1043 { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
1044 { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
1045 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1046/* uimm3: bit immediate (3 bits) */
1047 { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
1048 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
1049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1050/* uimm4: bCC const (4 bits) */
1051 { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
1052 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
1053 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1054/* uimm5: bit/shift val (5 bits) */
1055 { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
1056 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
1057 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1058/* udisp7: comment */
1059 { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
1060 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
1061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1062/* udisp7a2: comment */
1063 { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
1064 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
1065 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } },
1066/* udisp7a4: comment */
1067 { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
1068 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
1070/* uimm7a4: comment */
1071 { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
1072 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1073 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
1074/* uimm24: immediate (24 bits) */
1075 { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
1076 { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
1077 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1078/* cimm4: cache immed'te (4 bits) */
1079 { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
1080 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
1081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1082/* cimm5: clip immediate (5 bits) */
1083 { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
1084 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
1085 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1086/* cdisp8: copro addend (8 bits) */
1087 { "cdisp8", MEP_OPERAND_CDISP8, HW_H_SINT, 24, 8,
1088 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24] } },
1089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1090/* cdisp8a2: comment */
1091 { "cdisp8a2", MEP_OPERAND_CDISP8A2, HW_H_SINT, 24, 7,
1092 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A2] } },
1093 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } },
1094/* cdisp8a4: comment */
1095 { "cdisp8a4", MEP_OPERAND_CDISP8A4, HW_H_SINT, 24, 6,
1096 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A4] } },
1097 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
1098/* cdisp8a8: comment */
1099 { "cdisp8a8", MEP_OPERAND_CDISP8A8, HW_H_SINT, 24, 5,
1100 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A8] } },
1101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 8, 0 } } } } },
1102/* zero: Zero operand */
1103 { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
1104 { 0, { (const PTR) 0 } },
1105 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1106/* cp_flag: branch condition register */
1107 { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
1108 { 0, { (const PTR) 0 } },
1109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1110/* fmax-FRd: FRd */
1111 { "fmax-FRd", MEP_OPERAND_FMAX_FRD, HW_H_CR, 4, 5,
1112 { 2, { (const PTR) &MEP_F_FMAX_FRD_MULTI_IFIELD[0] } },
1113 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } } },
1114/* fmax-FRn: FRn */
1115 { "fmax-FRn", MEP_OPERAND_FMAX_FRN, HW_H_CR, 20, 5,
1116 { 2, { (const PTR) &MEP_F_FMAX_FRN_MULTI_IFIELD[0] } },
1117 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } } },
1118/* fmax-FRm: FRm */
1119 { "fmax-FRm", MEP_OPERAND_FMAX_FRM, HW_H_CR, 24, 5,
1120 { 2, { (const PTR) &MEP_F_FMAX_FRM_MULTI_IFIELD[0] } },
1121 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } } },
1122/* fmax-FRd-int: FRd as an integer */
1123 { "fmax-FRd-int", MEP_OPERAND_FMAX_FRD_INT, HW_H_CR, 4, 5,
1124 { 2, { (const PTR) &MEP_F_FMAX_FRD_MULTI_IFIELD[0] } },
1125 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_INT, 0 } }, { { 1, 0 } } } } },
1126/* fmax-FRn-int: FRn as an integer */
1127 { "fmax-FRn-int", MEP_OPERAND_FMAX_FRN_INT, HW_H_CR, 20, 5,
1128 { 2, { (const PTR) &MEP_F_FMAX_FRN_MULTI_IFIELD[0] } },
1129 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_INT, 0 } }, { { 1, 0 } } } } },
1130/* fmax-CCRn: CCRn */
1131 { "fmax-CCRn", MEP_OPERAND_FMAX_CCRN, HW_H_CCR, 4, 4,
1132 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_4_4] } },
1133 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
1134/* fmax-CIRR: CIRR */
1135 { "fmax-CIRR", MEP_OPERAND_FMAX_CIRR, HW_H_CCR, 0, 0,
1136 { 0, { (const PTR) 0 } },
1137 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1138/* fmax-CBCR: CBCR */
1139 { "fmax-CBCR", MEP_OPERAND_FMAX_CBCR, HW_H_CCR, 0, 0,
1140 { 0, { (const PTR) 0 } },
1141 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1142/* fmax-CERR: CERR */
1143 { "fmax-CERR", MEP_OPERAND_FMAX_CERR, HW_H_CCR, 0, 0,
1144 { 0, { (const PTR) 0 } },
1145 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1146/* fmax-Rm: Rm */
1147 { "fmax-Rm", MEP_OPERAND_FMAX_RM, HW_H_GPR, 8, 4,
1148 { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_RM] } },
1149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1150/* fmax-Compare-i-p: flag */
1151 { "fmax-Compare-i-p", MEP_OPERAND_FMAX_COMPARE_I_P, HW_H_FMAX_COMPARE_I_P, 0, 0,
1152 { 0, { (const PTR) 0 } },
1153 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
1154/* sentinel */
1155 { 0, 0, 0, 0, 0,
1156 { 0, { (const PTR) 0 } },
1157 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
1158};
1159
1160#undef A
1161
1162
1163/* The instruction table. */
1164
1165#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1166#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1167#define A(a) (1 << CGEN_INSN_##a)
1168#else
1169#define A(a) (1 << CGEN_INSN_/**/a)
1170#endif
1171
1172static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
1173{
1174 /* Special null first entry.
1175 A `num' value of zero is thus invalid.
1176 Also, the special `invalid' insn resides here. */
1177 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } },
1178/* sb $rnc,($rma) */
1179 {
1180 MEP_INSN_SB, "sb", "sb", 16,
1181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1182 },
1183/* sh $rns,($rma) */
1184 {
1185 MEP_INSN_SH, "sh", "sh", 16,
1186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1187 },
1188/* sw $rnl,($rma) */
1189 {
1190 MEP_INSN_SW, "sw", "sw", 16,
1191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1192 },
1193/* lb $rnc,($rma) */
1194 {
1195 MEP_INSN_LB, "lb", "lb", 16,
1196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1197 },
1198/* lh $rns,($rma) */
1199 {
1200 MEP_INSN_LH, "lh", "lh", 16,
1201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1202 },
1203/* lw $rnl,($rma) */
1204 {
1205 MEP_INSN_LW, "lw", "lw", 16,
1206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1207 },
1208/* lbu $rnuc,($rma) */
1209 {
1210 MEP_INSN_LBU, "lbu", "lbu", 16,
1211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1212 },
1213/* lhu $rnus,($rma) */
1214 {
1215 MEP_INSN_LHU, "lhu", "lhu", 16,
1216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1217 },
1218/* sw $rnl,$udisp7a4($spr) */
1219 {
1220 MEP_INSN_SW_SP, "sw-sp", "sw", 16,
1221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1222 },
1223/* lw $rnl,$udisp7a4($spr) */
1224 {
1225 MEP_INSN_LW_SP, "lw-sp", "lw", 16,
1226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1227 },
1228/* sb $rn3c,$udisp7($tpr) */
1229 {
1230 MEP_INSN_SB_TP, "sb-tp", "sb", 16,
1231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1232 },
1233/* sh $rn3s,$udisp7a2($tpr) */
1234 {
1235 MEP_INSN_SH_TP, "sh-tp", "sh", 16,
1236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1237 },
1238/* sw $rn3l,$udisp7a4($tpr) */
1239 {
1240 MEP_INSN_SW_TP, "sw-tp", "sw", 16,
1241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1242 },
1243/* lb $rn3c,$udisp7($tpr) */
1244 {
1245 MEP_INSN_LB_TP, "lb-tp", "lb", 16,
1246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1247 },
1248/* lh $rn3s,$udisp7a2($tpr) */
1249 {
1250 MEP_INSN_LH_TP, "lh-tp", "lh", 16,
1251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1252 },
1253/* lw $rn3l,$udisp7a4($tpr) */
1254 {
1255 MEP_INSN_LW_TP, "lw-tp", "lw", 16,
1256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1257 },
1258/* lbu $rn3uc,$udisp7($tpr) */
1259 {
1260 MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
1261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1262 },
1263/* lhu $rn3us,$udisp7a2($tpr) */
1264 {
1265 MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
1266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1267 },
1268/* sb $rnc,$sdisp16($rma) */
1269 {
1270 MEP_INSN_SB16, "sb16", "sb", 32,
1271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1272 },
1273/* sh $rns,$sdisp16($rma) */
1274 {
1275 MEP_INSN_SH16, "sh16", "sh", 32,
1276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1277 },
1278/* sw $rnl,$sdisp16($rma) */
1279 {
1280 MEP_INSN_SW16, "sw16", "sw", 32,
1281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1282 },
1283/* lb $rnc,$sdisp16($rma) */
1284 {
1285 MEP_INSN_LB16, "lb16", "lb", 32,
1286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1287 },
1288/* lh $rns,$sdisp16($rma) */
1289 {
1290 MEP_INSN_LH16, "lh16", "lh", 32,
1291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1292 },
1293/* lw $rnl,$sdisp16($rma) */
1294 {
1295 MEP_INSN_LW16, "lw16", "lw", 32,
1296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1297 },
1298/* lbu $rnuc,$sdisp16($rma) */
1299 {
1300 MEP_INSN_LBU16, "lbu16", "lbu", 32,
1301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1302 },
1303/* lhu $rnus,$sdisp16($rma) */
1304 {
1305 MEP_INSN_LHU16, "lhu16", "lhu", 32,
1306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1307 },
1308/* sw $rnl,($addr24a4) */
1309 {
1310 MEP_INSN_SW24, "sw24", "sw", 32,
1311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1312 },
1313/* lw $rnl,($addr24a4) */
1314 {
1315 MEP_INSN_LW24, "lw24", "lw", 32,
1316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1317 },
1318/* extb $rn */
1319 {
1320 MEP_INSN_EXTB, "extb", "extb", 16,
1321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1322 },
1323/* exth $rn */
1324 {
1325 MEP_INSN_EXTH, "exth", "exth", 16,
1326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1327 },
1328/* extub $rn */
1329 {
1330 MEP_INSN_EXTUB, "extub", "extub", 16,
1331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1332 },
1333/* extuh $rn */
1334 {
1335 MEP_INSN_EXTUH, "extuh", "extuh", 16,
1336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1337 },
1338/* ssarb $udisp2($rm) */
1339 {
1340 MEP_INSN_SSARB, "ssarb", "ssarb", 16,
1341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1342 },
1343/* mov $rn,$rm */
1344 {
1345 MEP_INSN_MOV, "mov", "mov", 16,
1346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1347 },
1348/* mov $rn,$simm8 */
1349 {
1350 MEP_INSN_MOVI8, "movi8", "mov", 16,
1351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1352 },
1353/* mov $rn,$simm16 */
1354 {
1355 MEP_INSN_MOVI16, "movi16", "mov", 32,
1356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1357 },
1358/* movu $rn3,$uimm24 */
1359 {
1360 MEP_INSN_MOVU24, "movu24", "movu", 32,
1361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1362 },
1363/* movu $rn,$uimm16 */
1364 {
1365 MEP_INSN_MOVU16, "movu16", "movu", 32,
1366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1367 },
1368/* movh $rn,$uimm16 */
1369 {
1370 MEP_INSN_MOVH, "movh", "movh", 32,
1371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1372 },
1373/* add3 $rl,$rn,$rm */
1374 {
1375 MEP_INSN_ADD3, "add3", "add3", 16,
1376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1377 },
1378/* add $rn,$simm6 */
1379 {
1380 MEP_INSN_ADD, "add", "add", 16,
1381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1382 },
1383/* add3 $rn,$spr,$uimm7a4 */
1384 {
1385 MEP_INSN_ADD3I, "add3i", "add3", 16,
1386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1387 },
1388/* advck3 \$0,$rn,$rm */
1389 {
1390 MEP_INSN_ADVCK3, "advck3", "advck3", 16,
1391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1392 },
1393/* sub $rn,$rm */
1394 {
1395 MEP_INSN_SUB, "sub", "sub", 16,
1396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1397 },
1398/* sbvck3 \$0,$rn,$rm */
1399 {
1400 MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
1401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1402 },
1403/* neg $rn,$rm */
1404 {
1405 MEP_INSN_NEG, "neg", "neg", 16,
1406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1407 },
1408/* slt3 \$0,$rn,$rm */
1409 {
1410 MEP_INSN_SLT3, "slt3", "slt3", 16,
1411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1412 },
1413/* sltu3 \$0,$rn,$rm */
1414 {
1415 MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
1416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1417 },
1418/* slt3 \$0,$rn,$uimm5 */
1419 {
1420 MEP_INSN_SLT3I, "slt3i", "slt3", 16,
1421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1422 },
1423/* sltu3 \$0,$rn,$uimm5 */
1424 {
1425 MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
1426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1427 },
1428/* sl1ad3 \$0,$rn,$rm */
1429 {
1430 MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
1431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1432 },
1433/* sl2ad3 \$0,$rn,$rm */
1434 {
1435 MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
1436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1437 },
1438/* add3 $rn,$rm,$simm16 */
1439 {
1440 MEP_INSN_ADD3X, "add3x", "add3", 32,
1441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1442 },
1443/* slt3 $rn,$rm,$simm16 */
1444 {
1445 MEP_INSN_SLT3X, "slt3x", "slt3", 32,
1446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1447 },
1448/* sltu3 $rn,$rm,$uimm16 */
1449 {
1450 MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
1451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1452 },
1453/* or $rn,$rm */
1454 {
1455 MEP_INSN_OR, "or", "or", 16,
1456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1457 },
1458/* and $rn,$rm */
1459 {
1460 MEP_INSN_AND, "and", "and", 16,
1461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1462 },
1463/* xor $rn,$rm */
1464 {
1465 MEP_INSN_XOR, "xor", "xor", 16,
1466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1467 },
1468/* nor $rn,$rm */
1469 {
1470 MEP_INSN_NOR, "nor", "nor", 16,
1471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1472 },
1473/* or3 $rn,$rm,$uimm16 */
1474 {
1475 MEP_INSN_OR3, "or3", "or3", 32,
1476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1477 },
1478/* and3 $rn,$rm,$uimm16 */
1479 {
1480 MEP_INSN_AND3, "and3", "and3", 32,
1481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1482 },
1483/* xor3 $rn,$rm,$uimm16 */
1484 {
1485 MEP_INSN_XOR3, "xor3", "xor3", 32,
1486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1487 },
1488/* sra $rn,$rm */
1489 {
1490 MEP_INSN_SRA, "sra", "sra", 16,
1491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1492 },
1493/* srl $rn,$rm */
1494 {
1495 MEP_INSN_SRL, "srl", "srl", 16,
1496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1497 },
1498/* sll $rn,$rm */
1499 {
1500 MEP_INSN_SLL, "sll", "sll", 16,
1501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1502 },
1503/* sra $rn,$uimm5 */
1504 {
1505 MEP_INSN_SRAI, "srai", "sra", 16,
1506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1507 },
1508/* srl $rn,$uimm5 */
1509 {
1510 MEP_INSN_SRLI, "srli", "srl", 16,
1511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1512 },
1513/* sll $rn,$uimm5 */
1514 {
1515 MEP_INSN_SLLI, "slli", "sll", 16,
1516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1517 },
1518/* sll3 \$0,$rn,$uimm5 */
1519 {
1520 MEP_INSN_SLL3, "sll3", "sll3", 16,
1521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1522 },
1523/* fsft $rn,$rm */
1524 {
1525 MEP_INSN_FSFT, "fsft", "fsft", 16,
1526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1527 },
1528/* bra $pcrel12a2 */
1529 {
1530 MEP_INSN_BRA, "bra", "bra", 16,
1531 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1532 },
1533/* beqz $rn,$pcrel8a2 */
1534 {
1535 MEP_INSN_BEQZ, "beqz", "beqz", 16,
1536 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1537 },
1538/* bnez $rn,$pcrel8a2 */
1539 {
1540 MEP_INSN_BNEZ, "bnez", "bnez", 16,
1541 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1542 },
1543/* beqi $rn,$uimm4,$pcrel17a2 */
1544 {
1545 MEP_INSN_BEQI, "beqi", "beqi", 32,
1546 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1547 },
1548/* bnei $rn,$uimm4,$pcrel17a2 */
1549 {
1550 MEP_INSN_BNEI, "bnei", "bnei", 32,
1551 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1552 },
1553/* blti $rn,$uimm4,$pcrel17a2 */
1554 {
1555 MEP_INSN_BLTI, "blti", "blti", 32,
1556 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1557 },
1558/* bgei $rn,$uimm4,$pcrel17a2 */
1559 {
1560 MEP_INSN_BGEI, "bgei", "bgei", 32,
1561 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1562 },
1563/* beq $rn,$rm,$pcrel17a2 */
1564 {
1565 MEP_INSN_BEQ, "beq", "beq", 32,
1566 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1567 },
1568/* bne $rn,$rm,$pcrel17a2 */
1569 {
1570 MEP_INSN_BNE, "bne", "bne", 32,
1571 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1572 },
1573/* bsr $pcrel12a2 */
1574 {
1575 MEP_INSN_BSR12, "bsr12", "bsr", 16,
1576 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1577 },
1578/* bsr $pcrel24a2 */
1579 {
1580 MEP_INSN_BSR24, "bsr24", "bsr", 32,
1581 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1582 },
1583/* jmp $rm */
1584 {
1585 MEP_INSN_JMP, "jmp", "jmp", 16,
1586 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1587 },
1588/* jmp $pcabs24a2 */
1589 {
1590 MEP_INSN_JMP24, "jmp24", "jmp", 32,
1591 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1592 },
1593/* jsr $rm */
1594 {
1595 MEP_INSN_JSR, "jsr", "jsr", 16,
1596 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1597 },
1598/* ret */
1599 {
1600 MEP_INSN_RET, "ret", "ret", 16,
1601 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1602 },
1603/* repeat $rn,$pcrel17a2 */
1604 {
1605 MEP_INSN_REPEAT, "repeat", "repeat", 32,
1606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1607 },
1608/* erepeat $pcrel17a2 */
1609 {
1610 MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
1611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1612 },
1613/* stc $rn,\$lp */
1614 {
1615 MEP_INSN_STC_LP, "stc_lp", "stc", 16,
1616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1617 },
1618/* stc $rn,\$hi */
1619 {
1620 MEP_INSN_STC_HI, "stc_hi", "stc", 16,
1621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1622 },
1623/* stc $rn,\$lo */
1624 {
1625 MEP_INSN_STC_LO, "stc_lo", "stc", 16,
1626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1627 },
1628/* stc $rn,$csrn */
1629 {
1630 MEP_INSN_STC, "stc", "stc", 16,
1631 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1632 },
1633/* ldc $rn,\$lp */
1634 {
1635 MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
1636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1637 },
1638/* ldc $rn,\$hi */
1639 {
1640 MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
1641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1642 },
1643/* ldc $rn,\$lo */
1644 {
1645 MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
1646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1647 },
1648/* ldc $rn,$csrn */
1649 {
1650 MEP_INSN_LDC, "ldc", "ldc", 16,
1651 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1652 },
1653/* di */
1654 {
1655 MEP_INSN_DI, "di", "di", 16,
1656 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1657 },
1658/* ei */
1659 {
1660 MEP_INSN_EI, "ei", "ei", 16,
1661 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1662 },
1663/* reti */
1664 {
1665 MEP_INSN_RETI, "reti", "reti", 16,
1666 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1667 },
1668/* halt */
1669 {
1670 MEP_INSN_HALT, "halt", "halt", 16,
1671 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1672 },
1673/* sleep */
1674 {
1675 MEP_INSN_SLEEP, "sleep", "sleep", 16,
1676 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1677 },
1678/* swi $uimm2 */
1679 {
1680 MEP_INSN_SWI, "swi", "swi", 16,
1681 { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1682 },
1683/* break */
1684 {
1685 MEP_INSN_BREAK, "break", "break", 16,
1686 { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1687 },
1688/* syncm */
1689 {
1690 MEP_INSN_SYNCM, "syncm", "syncm", 16,
1691 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1692 },
1693/* stcb $rn,$uimm16 */
1694 {
1695 MEP_INSN_STCB, "stcb", "stcb", 32,
1696 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1697 },
1698/* ldcb $rn,$uimm16 */
1699 {
1700 MEP_INSN_LDCB, "ldcb", "ldcb", 32,
1701 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1702 },
1703/* bsetm ($rma),$uimm3 */
1704 {
1705 MEP_INSN_BSETM, "bsetm", "bsetm", 16,
1706 { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1707 },
1708/* bclrm ($rma),$uimm3 */
1709 {
1710 MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
1711 { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1712 },
1713/* bnotm ($rma),$uimm3 */
1714 {
1715 MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
1716 { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1717 },
1718/* btstm \$0,($rma),$uimm3 */
1719 {
1720 MEP_INSN_BTSTM, "btstm", "btstm", 16,
1721 { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1722 },
1723/* tas $rn,($rma) */
1724 {
1725 MEP_INSN_TAS, "tas", "tas", 16,
1726 { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1727 },
1728/* cache $cimm4,($rma) */
1729 {
1730 MEP_INSN_CACHE, "cache", "cache", 16,
1731 { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1732 },
1733/* mul $rn,$rm */
1734 {
1735 MEP_INSN_MUL, "mul", "mul", 16,
1736 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1737 },
1738/* mulu $rn,$rm */
1739 {
1740 MEP_INSN_MULU, "mulu", "mulu", 16,
1741 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1742 },
1743/* mulr $rn,$rm */
1744 {
1745 MEP_INSN_MULR, "mulr", "mulr", 16,
1746 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1747 },
1748/* mulru $rn,$rm */
1749 {
1750 MEP_INSN_MULRU, "mulru", "mulru", 16,
1751 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1752 },
1753/* madd $rn,$rm */
1754 {
1755 MEP_INSN_MADD, "madd", "madd", 32,
1756 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1757 },
1758/* maddu $rn,$rm */
1759 {
1760 MEP_INSN_MADDU, "maddu", "maddu", 32,
1761 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1762 },
1763/* maddr $rn,$rm */
1764 {
1765 MEP_INSN_MADDR, "maddr", "maddr", 32,
1766 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1767 },
1768/* maddru $rn,$rm */
1769 {
1770 MEP_INSN_MADDRU, "maddru", "maddru", 32,
1771 { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1772 },
1773/* div $rn,$rm */
1774 {
1775 MEP_INSN_DIV, "div", "div", 16,
1776 { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
1777 },
1778/* divu $rn,$rm */
1779 {
1780 MEP_INSN_DIVU, "divu", "divu", 16,
1781 { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
1782 },
1783/* dret */
1784 {
1785 MEP_INSN_DRET, "dret", "dret", 16,
1786 { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1787 },
1788/* dbreak */
1789 {
1790 MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
1791 { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1792 },
1793/* ldz $rn,$rm */
1794 {
1795 MEP_INSN_LDZ, "ldz", "ldz", 32,
1796 { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1797 },
1798/* abs $rn,$rm */
1799 {
1800 MEP_INSN_ABS, "abs", "abs", 32,
1801 { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1802 },
1803/* ave $rn,$rm */
1804 {
1805 MEP_INSN_AVE, "ave", "ave", 32,
1806 { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1807 },
1808/* min $rn,$rm */
1809 {
1810 MEP_INSN_MIN, "min", "min", 32,
1811 { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1812 },
1813/* max $rn,$rm */
1814 {
1815 MEP_INSN_MAX, "max", "max", 32,
1816 { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1817 },
1818/* minu $rn,$rm */
1819 {
1820 MEP_INSN_MINU, "minu", "minu", 32,
1821 { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1822 },
1823/* maxu $rn,$rm */
1824 {
1825 MEP_INSN_MAXU, "maxu", "maxu", 32,
1826 { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1827 },
1828/* clip $rn,$cimm5 */
1829 {
1830 MEP_INSN_CLIP, "clip", "clip", 32,
1831 { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1832 },
1833/* clipu $rn,$cimm5 */
1834 {
1835 MEP_INSN_CLIPU, "clipu", "clipu", 32,
1836 { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1837 },
1838/* sadd $rn,$rm */
1839 {
1840 MEP_INSN_SADD, "sadd", "sadd", 32,
1841 { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1842 },
1843/* ssub $rn,$rm */
1844 {
1845 MEP_INSN_SSUB, "ssub", "ssub", 32,
1846 { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1847 },
1848/* saddu $rn,$rm */
1849 {
1850 MEP_INSN_SADDU, "saddu", "saddu", 32,
1851 { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1852 },
1853/* ssubu $rn,$rm */
1854 {
1855 MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
1856 { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1857 },
1858/* swcp $crn,($rma) */
1859 {
1860 MEP_INSN_SWCP, "swcp", "swcp", 16,
1861 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1862 },
1863/* lwcp $crn,($rma) */
1864 {
1865 MEP_INSN_LWCP, "lwcp", "lwcp", 16,
1866 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1867 },
1868/* smcp $crn64,($rma) */
1869 {
1870 MEP_INSN_SMCP, "smcp", "smcp", 16,
1871 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1872 },
1873/* lmcp $crn64,($rma) */
1874 {
1875 MEP_INSN_LMCP, "lmcp", "lmcp", 16,
1876 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1877 },
1878/* swcpi $crn,($rma+) */
1879 {
1880 MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
1881 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1882 },
1883/* lwcpi $crn,($rma+) */
1884 {
1885 MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
1886 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1887 },
1888/* smcpi $crn64,($rma+) */
1889 {
1890 MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
1891 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1892 },
1893/* lmcpi $crn64,($rma+) */
1894 {
1895 MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
1896 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1897 },
1898/* swcp $crn,$sdisp16($rma) */
1899 {
1900 MEP_INSN_SWCP16, "swcp16", "swcp", 32,
1901 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1902 },
1903/* lwcp $crn,$sdisp16($rma) */
1904 {
1905 MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
1906 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1907 },
1908/* smcp $crn64,$sdisp16($rma) */
1909 {
1910 MEP_INSN_SMCP16, "smcp16", "smcp", 32,
1911 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1912 },
1913/* lmcp $crn64,$sdisp16($rma) */
1914 {
1915 MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
1916 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1917 },
1918/* sbcpa $crn,($rma+),$cdisp8 */
1919 {
1920 MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
1921 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1922 },
1923/* lbcpa $crn,($rma+),$cdisp8 */
1924 {
1925 MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
1926 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1927 },
1928/* shcpa $crn,($rma+),$cdisp8a2 */
1929 {
1930 MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
1931 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1932 },
1933/* lhcpa $crn,($rma+),$cdisp8a2 */
1934 {
1935 MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
1936 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1937 },
1938/* swcpa $crn,($rma+),$cdisp8a4 */
1939 {
1940 MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
1941 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1942 },
1943/* lwcpa $crn,($rma+),$cdisp8a4 */
1944 {
1945 MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
1946 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1947 },
1948/* smcpa $crn64,($rma+),$cdisp8a8 */
1949 {
1950 MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
1951 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1952 },
1953/* lmcpa $crn64,($rma+),$cdisp8a8 */
1954 {
1955 MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
1956 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1957 },
1958/* sbcpm0 $crn,($rma+),$cdisp8 */
1959 {
1960 MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
1961 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1962 },
1963/* lbcpm0 $crn,($rma+),$cdisp8 */
1964 {
1965 MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
1966 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1967 },
1968/* shcpm0 $crn,($rma+),$cdisp8a2 */
1969 {
1970 MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
1971 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1972 },
1973/* lhcpm0 $crn,($rma+),$cdisp8a2 */
1974 {
1975 MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
1976 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1977 },
1978/* swcpm0 $crn,($rma+),$cdisp8a4 */
1979 {
1980 MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
1981 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1982 },
1983/* lwcpm0 $crn,($rma+),$cdisp8a4 */
1984 {
1985 MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
1986 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1987 },
1988/* smcpm0 $crn64,($rma+),$cdisp8a8 */
1989 {
1990 MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
1991 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1992 },
1993/* lmcpm0 $crn64,($rma+),$cdisp8a8 */
1994 {
1995 MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
1996 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1997 },
1998/* sbcpm1 $crn,($rma+),$cdisp8 */
1999 {
2000 MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
2001 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2002 },
2003/* lbcpm1 $crn,($rma+),$cdisp8 */
2004 {
2005 MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
2006 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2007 },
2008/* shcpm1 $crn,($rma+),$cdisp8a2 */
2009 {
2010 MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
2011 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2012 },
2013/* lhcpm1 $crn,($rma+),$cdisp8a2 */
2014 {
2015 MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
2016 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2017 },
2018/* swcpm1 $crn,($rma+),$cdisp8a4 */
2019 {
2020 MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
2021 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2022 },
2023/* lwcpm1 $crn,($rma+),$cdisp8a4 */
2024 {
2025 MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
2026 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2027 },
2028/* smcpm1 $crn64,($rma+),$cdisp8a8 */
2029 {
2030 MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
2031 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2032 },
2033/* lmcpm1 $crn64,($rma+),$cdisp8a8 */
2034 {
2035 MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
2036 { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2037 },
2038/* bcpeq $cccc,$pcrel17a2 */
2039 {
2040 MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
2041 { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2042 },
2043/* bcpne $cccc,$pcrel17a2 */
2044 {
2045 MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
2046 { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2047 },
2048/* bcpat $cccc,$pcrel17a2 */
2049 {
2050 MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
2051 { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2052 },
2053/* bcpaf $cccc,$pcrel17a2 */
2054 {
2055 MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
2056 { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2057 },
2058/* synccp */
2059 {
2060 MEP_INSN_SYNCCP, "synccp", "synccp", 16,
2061 { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2062 },
2063/* jsrv $rm */
2064 {
2065 MEP_INSN_JSRV, "jsrv", "jsrv", 16,
2066 { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2067 },
2068/* bsrv $pcrel24a2 */
2069 {
2070 MEP_INSN_BSRV, "bsrv", "bsrv", 32,
2071 { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2072 },
2073/* --unused-- */
2074 {
2075 MEP_INSN_SIM_SYSCALL, "sim-syscall", "--unused--", 16,
2076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2077 },
2078/* --reserved-- */
2079 {
2080 MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
2081 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2082 },
2083/* --reserved-- */
2084 {
2085 MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
2086 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2087 },
2088/* --reserved-- */
2089 {
2090 MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
2091 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2092 },
2093/* --reserved-- */
2094 {
2095 MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
2096 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2097 },
2098/* --reserved-- */
2099 {
2100 MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
2101 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2102 },
2103/* --reserved-- */
2104 {
2105 MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
2106 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2107 },
2108/* --reserved-- */
2109 {
2110 MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
2111 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2112 },
2113/* --reserved-- */
2114 {
2115 MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
2116 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2117 },
2118/* --reserved-- */
2119 {
2120 MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
2121 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2122 },
2123/* --reserved-- */
2124 {
2125 MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
2126 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2127 },
2128/* --reserved-- */
2129 {
2130 MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
2131 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2132 },
2133/* --reserved-- */
2134 {
2135 MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
2136 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2137 },
2138/* --reserved-- */
2139 {
2140 MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
2141 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2142 },
2143/* --reserved-- */
2144 {
2145 MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
2146 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2147 },
2148/* --reserved-- */
2149 {
2150 MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
2151 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2152 },
2153/* --reserved-- */
2154 {
2155 MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
2156 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2157 },
2158/* --reserved-- */
2159 {
2160 MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
2161 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2162 },
2163/* --reserved-- */
2164 {
2165 MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
2166 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2167 },
2168/* --reserved-- */
2169 {
2170 MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
2171 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2172 },
2173/* --reserved-- */
2174 {
2175 MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
2176 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2177 },
2178/* --reserved-- */
2179 {
2180 MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
2181 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2182 },
2183/* --reserved-- */
2184 {
2185 MEP_INSN_RI_24, "ri-24", "--reserved--", 16,
2186 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2187 },
2188/* --reserved-- */
2189 {
2190 MEP_INSN_RI_25, "ri-25", "--reserved--", 16,
2191 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2192 },
2193/* --reserved-- */
2194 {
2195 MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
2196 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2197 },
2198/* --reserved-- */
2199 {
2200 MEP_INSN_RI_16, "ri-16", "--reserved--", 16,
2201 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2202 },
2203/* --reserved-- */
2204 {
2205 MEP_INSN_RI_18, "ri-18", "--reserved--", 16,
2206 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2207 },
2208/* --reserved-- */
2209 {
2210 MEP_INSN_RI_19, "ri-19", "--reserved--", 16,
2211 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2212 },
2213/* fadds ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
2214 {
2215 MEP_INSN_FADDS, "fadds", "fadds", 32,
2216 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2217 },
2218/* fsubs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
2219 {
2220 MEP_INSN_FSUBS, "fsubs", "fsubs", 32,
2221 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2222 },
2223/* fmuls ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
2224 {
2225 MEP_INSN_FMULS, "fmuls", "fmuls", 32,
2226 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2227 },
2228/* fdivs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
2229 {
2230 MEP_INSN_FDIVS, "fdivs", "fdivs", 32,
2231 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2232 },
2233/* fsqrts ${fmax-FRd},${fmax-FRn} */
2234 {
2235 MEP_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
2236 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2237 },
2238/* fabss ${fmax-FRd},${fmax-FRn} */
2239 {
2240 MEP_INSN_FABSS, "fabss", "fabss", 32,
2241 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2242 },
2243/* fnegs ${fmax-FRd},${fmax-FRn} */
2244 {
2245 MEP_INSN_FNEGS, "fnegs", "fnegs", 32,
2246 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2247 },
2248/* fmovs ${fmax-FRd},${fmax-FRn} */
2249 {
2250 MEP_INSN_FMOVS, "fmovs", "fmovs", 32,
2251 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2252 },
2253/* froundws ${fmax-FRd-int},${fmax-FRn} */
2254 {
2255 MEP_INSN_FROUNDWS, "froundws", "froundws", 32,
2256 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2257 },
2258/* ftruncws ${fmax-FRd-int},${fmax-FRn} */
2259 {
2260 MEP_INSN_FTRUNCWS, "ftruncws", "ftruncws", 32,
2261 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2262 },
2263/* fceilws ${fmax-FRd-int},${fmax-FRn} */
2264 {
2265 MEP_INSN_FCEILWS, "fceilws", "fceilws", 32,
2266 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2267 },
2268/* ffloorws ${fmax-FRd-int},${fmax-FRn} */
2269 {
2270 MEP_INSN_FFLOORWS, "ffloorws", "ffloorws", 32,
2271 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2272 },
2273/* fcvtws ${fmax-FRd-int},${fmax-FRn} */
2274 {
2275 MEP_INSN_FCVTWS, "fcvtws", "fcvtws", 32,
2276 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2277 },
2278/* fcvtsw ${fmax-FRd},${fmax-FRn-int} */
2279 {
2280 MEP_INSN_FCVTSW, "fcvtsw", "fcvtsw", 32,
2281 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2282 },
2283/* fcmpfs ${fmax-FRn},${fmax-FRm} */
2284 {
2285 MEP_INSN_FCMPFS, "fcmpfs", "fcmpfs", 32,
2286 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2287 },
2288/* fcmpus ${fmax-FRn},${fmax-FRm} */
2289 {
2290 MEP_INSN_FCMPUS, "fcmpus", "fcmpus", 32,
2291 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2292 },
2293/* fcmpes ${fmax-FRn},${fmax-FRm} */
2294 {
2295 MEP_INSN_FCMPES, "fcmpes", "fcmpes", 32,
2296 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2297 },
2298/* fcmpues ${fmax-FRn},${fmax-FRm} */
2299 {
2300 MEP_INSN_FCMPUES, "fcmpues", "fcmpues", 32,
2301 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2302 },
2303/* fcmpls ${fmax-FRn},${fmax-FRm} */
2304 {
2305 MEP_INSN_FCMPLS, "fcmpls", "fcmpls", 32,
2306 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2307 },
2308/* fcmpuls ${fmax-FRn},${fmax-FRm} */
2309 {
2310 MEP_INSN_FCMPULS, "fcmpuls", "fcmpuls", 32,
2311 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2312 },
2313/* fcmples ${fmax-FRn},${fmax-FRm} */
2314 {
2315 MEP_INSN_FCMPLES, "fcmples", "fcmples", 32,
2316 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2317 },
2318/* fcmpules ${fmax-FRn},${fmax-FRm} */
2319 {
2320 MEP_INSN_FCMPULES, "fcmpules", "fcmpules", 32,
2321 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2322 },
2323/* fcmpfis ${fmax-FRn},${fmax-FRm} */
2324 {
2325 MEP_INSN_FCMPFIS, "fcmpfis", "fcmpfis", 32,
2326 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2327 },
2328/* fcmpuis ${fmax-FRn},${fmax-FRm} */
2329 {
2330 MEP_INSN_FCMPUIS, "fcmpuis", "fcmpuis", 32,
2331 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2332 },
2333/* fcmpeis ${fmax-FRn},${fmax-FRm} */
2334 {
2335 MEP_INSN_FCMPEIS, "fcmpeis", "fcmpeis", 32,
2336 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2337 },
2338/* fcmpueis ${fmax-FRn},${fmax-FRm} */
2339 {
2340 MEP_INSN_FCMPUEIS, "fcmpueis", "fcmpueis", 32,
2341 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2342 },
2343/* fcmplis ${fmax-FRn},${fmax-FRm} */
2344 {
2345 MEP_INSN_FCMPLIS, "fcmplis", "fcmplis", 32,
2346 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2347 },
2348/* fcmpulis ${fmax-FRn},${fmax-FRm} */
2349 {
2350 MEP_INSN_FCMPULIS, "fcmpulis", "fcmpulis", 32,
2351 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2352 },
2353/* fcmpleis ${fmax-FRn},${fmax-FRm} */
2354 {
2355 MEP_INSN_FCMPLEIS, "fcmpleis", "fcmpleis", 32,
2356 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2357 },
2358/* fcmpuleis ${fmax-FRn},${fmax-FRm} */
2359 {
2360 MEP_INSN_FCMPULEIS, "fcmpuleis", "fcmpuleis", 32,
2361 { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2362 },
2363/* cmov ${fmax-FRd-int},${fmax-Rm} */
2364 {
2365 MEP_INSN_CMOV_FRN_RM, "cmov-frn-rm", "cmov", 32,
2366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2367 },
2368/* cmov ${fmax-Rm},${fmax-FRd-int} */
2369 {
2370 MEP_INSN_CMOV_RM_FRN, "cmov-rm-frn", "cmov", 32,
2371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2372 },
2373/* cmovc ${fmax-CCRn},${fmax-Rm} */
2374 {
2375 MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32,
2376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2377 },
2378/* cmovc ${fmax-Rm},${fmax-CCRn} */
2379 {
2380 MEP_INSN_CMOVC_RM_CCRN, "cmovc-rm-ccrn", "cmovc", 32,
2381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2382 },
2383};
2384
2385#undef OP
2386#undef A
2387
2388/* Initialize anything needed to be done once, before any cpu_open call. */
2389
2390static void
2391init_tables (void)
2392{
2393}
2394
2395static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
2396static void build_hw_table (CGEN_CPU_TABLE *);
2397static void build_ifield_table (CGEN_CPU_TABLE *);
2398static void build_operand_table (CGEN_CPU_TABLE *);
2399static void build_insn_table (CGEN_CPU_TABLE *);
2400static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *);
2401
2402/* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name. */
2403
2404static const CGEN_MACH *
2405lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
2406{
2407 while (table->name)
2408 {
2409 if (strcmp (name, table->bfd_name) == 0)
2410 return table;
2411 ++table;
2412 }
2413 abort ();
2414}
2415
2416/* Subroutine of mep_cgen_cpu_open to build the hardware table. */
2417
2418static void
2419build_hw_table (CGEN_CPU_TABLE *cd)
2420{
2421 int i;
2422 int machs = cd->machs;
2423 const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0];
2424 /* MAX_HW is only an upper bound on the number of selected entries.
2425 However each entry is indexed by it's enum so there can be holes in
2426 the table. */
2427 const CGEN_HW_ENTRY **selected =
2428 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
2429
2430 cd->hw_table.init_entries = init;
2431 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
2432 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
2433 /* ??? For now we just use machs to determine which ones we want. */
2434 for (i = 0; init[i].name != NULL; ++i)
2435 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
2436 & machs)
2437 selected[init[i].type] = &init[i];
2438 cd->hw_table.entries = selected;
2439 cd->hw_table.num_entries = MAX_HW;
2440}
2441
2442/* Subroutine of mep_cgen_cpu_open to build the hardware table. */
2443
2444static void
2445build_ifield_table (CGEN_CPU_TABLE *cd)
2446{
2447 cd->ifld_table = & mep_cgen_ifld_table[0];
2448}
2449
2450/* Subroutine of mep_cgen_cpu_open to build the hardware table. */
2451
2452static void
2453build_operand_table (CGEN_CPU_TABLE *cd)
2454{
2455 int i;
2456 int machs = cd->machs;
2457 const CGEN_OPERAND *init = & mep_cgen_operand_table[0];
2458 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
2459 However each entry is indexed by it's enum so there can be holes in
2460 the table. */
2461 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
2462
2463 cd->operand_table.init_entries = init;
2464 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
2465 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
2466 /* ??? For now we just use mach to determine which ones we want. */
2467 for (i = 0; init[i].name != NULL; ++i)
2468 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
2469 & machs)
2470 selected[init[i].type] = &init[i];
2471 cd->operand_table.entries = selected;
2472 cd->operand_table.num_entries = MAX_OPERANDS;
2473}
2474
2475/* Subroutine of mep_cgen_cpu_open to build the hardware table.
2476 ??? This could leave out insns not supported by the specified mach/isa,
2477 but that would cause errors like "foo only supported by bar" to become
2478 "unknown insn", so for now we include all insns and require the app to
2479 do the checking later.
2480 ??? On the other hand, parsing of such insns may require their hardware or
2481 operand elements to be in the table [which they mightn't be]. */
2482
2483static void
2484build_insn_table (CGEN_CPU_TABLE *cd)
2485{
2486 int i;
2487 const CGEN_IBASE *ib = & mep_cgen_insn_table[0];
2488 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
2489
2490 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
2491 for (i = 0; i < MAX_INSNS; ++i)
2492 insns[i].base = &ib[i];
2493 cd->insn_table.init_entries = insns;
2494 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
2495 cd->insn_table.num_init_entries = MAX_INSNS;
2496}
2497
2498/* Subroutine of mep_cgen_cpu_open to rebuild the tables. */
2499
2500static void
2501mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
2502{
2503 int i;
2504 CGEN_BITSET *isas = cd->isas;
2505 unsigned int machs = cd->machs;
2506
2507 cd->int_insn_p = CGEN_INT_INSN_P;
2508
2509 /* Data derived from the isa spec. */
2510#define UNSET (CGEN_SIZE_UNKNOWN + 1)
2511 cd->default_insn_bitsize = UNSET;
2512 cd->base_insn_bitsize = UNSET;
2513 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
2514 cd->max_insn_bitsize = 0;
2515 for (i = 0; i < MAX_ISAS; ++i)
2516 if (cgen_bitset_contains (isas, i))
2517 {
2518 const CGEN_ISA *isa = & mep_cgen_isa_table[i];
2519
2520 /* Default insn sizes of all selected isas must be
2521 equal or we set the result to 0, meaning "unknown". */
2522 if (cd->default_insn_bitsize == UNSET)
2523 cd->default_insn_bitsize = isa->default_insn_bitsize;
2524 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2525 ; /* This is ok. */
2526 else
2527 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2528
2529 /* Base insn sizes of all selected isas must be equal
2530 or we set the result to 0, meaning "unknown". */
2531 if (cd->base_insn_bitsize == UNSET)
2532 cd->base_insn_bitsize = isa->base_insn_bitsize;
2533 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2534 ; /* This is ok. */
2535 else
2536 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2537
2538 /* Set min,max insn sizes. */
2539 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2540 cd->min_insn_bitsize = isa->min_insn_bitsize;
2541 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2542 cd->max_insn_bitsize = isa->max_insn_bitsize;
2543 }
2544
2545 /* Data derived from the mach spec. */
2546 for (i = 0; i < MAX_MACHS; ++i)
2547 if (((1 << i) & machs) != 0)
2548 {
2549 const CGEN_MACH *mach = & mep_cgen_mach_table[i];
2550
2551 if (mach->insn_chunk_bitsize != 0)
2552 {
2553 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2554 {
2555 fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
2556 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2557 abort ();
2558 }
2559
2560 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2561 }
2562 }
2563
2564 /* Determine which hw elements are used by MACH. */
2565 build_hw_table (cd);
2566
2567 /* Build the ifield table. */
2568 build_ifield_table (cd);
2569
2570 /* Determine which operands are used by MACH/ISA. */
2571 build_operand_table (cd);
2572
2573 /* Build the instruction table. */
2574 build_insn_table (cd);
2575}
2576
2577/* Initialize a cpu table and return a descriptor.
2578 It's much like opening a file, and must be the first function called.
2579 The arguments are a set of (type/value) pairs, terminated with
2580 CGEN_CPU_OPEN_END.
2581
2582 Currently supported values:
2583 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
2584 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
2585 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2586 CGEN_CPU_OPEN_ENDIAN: specify endian choice
2587 CGEN_CPU_OPEN_END: terminates arguments
2588
2589 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2590 precluded.
2591
2592 ??? We only support ISO C stdargs here, not K&R.
2593 Laziness, plus experiment to see if anything requires K&R - eventually
2594 K&R will no longer be supported - e.g. GDB is currently trying this. */
2595
2596CGEN_CPU_DESC
2597mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2598{
2599 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2600 static int init_p;
2601 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
2602 unsigned int machs = 0; /* 0 = "unspecified" */
2603 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2604 va_list ap;
2605
2606 if (! init_p)
2607 {
2608 init_tables ();
2609 init_p = 1;
2610 }
2611
2612 memset (cd, 0, sizeof (*cd));
2613
2614 va_start (ap, arg_type);
2615 while (arg_type != CGEN_CPU_OPEN_END)
2616 {
2617 switch (arg_type)
2618 {
2619 case CGEN_CPU_OPEN_ISAS :
2620 isas = va_arg (ap, CGEN_BITSET *);
2621 break;
2622 case CGEN_CPU_OPEN_MACHS :
2623 machs = va_arg (ap, unsigned int);
2624 break;
2625 case CGEN_CPU_OPEN_BFDMACH :
2626 {
2627 const char *name = va_arg (ap, const char *);
2628 const CGEN_MACH *mach =
2629 lookup_mach_via_bfd_name (mep_cgen_mach_table, name);
2630
2631 machs |= 1 << mach->num;
2632 break;
2633 }
2634 case CGEN_CPU_OPEN_ENDIAN :
2635 endian = va_arg (ap, enum cgen_endian);
2636 break;
2637 default :
2638 fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n",
2639 arg_type);
2640 abort (); /* ??? return NULL? */
2641 }
2642 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2643 }
2644 va_end (ap);
2645
2646 /* Mach unspecified means "all". */
2647 if (machs == 0)
2648 machs = (1 << MAX_MACHS) - 1;
2649 /* Base mach is always selected. */
2650 machs |= 1;
2651 if (endian == CGEN_ENDIAN_UNKNOWN)
2652 {
2653 /* ??? If target has only one, could have a default. */
2654 fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n");
2655 abort ();
2656 }
2657
2658 cd->isas = cgen_bitset_copy (isas);
2659 cd->machs = machs;
2660 cd->endian = endian;
2661 /* FIXME: for the sparc case we can determine insn-endianness statically.
2662 The worry here is where both data and insn endian can be independently
2663 chosen, in which case this function will need another argument.
2664 Actually, will want to allow for more arguments in the future anyway. */
2665 cd->insn_endian = endian;
2666
2667 /* Table (re)builder. */
2668 cd->rebuild_tables = mep_cgen_rebuild_tables;
2669 mep_cgen_rebuild_tables (cd);
2670
2671 /* Default to not allowing signed overflow. */
2672 cd->signed_overflow_ok_p = 0;
2673
2674 return (CGEN_CPU_DESC) cd;
2675}
2676
2677/* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2678 MACH_NAME is the bfd name of the mach. */
2679
2680CGEN_CPU_DESC
2681mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2682{
2683 return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2684 CGEN_CPU_OPEN_ENDIAN, endian,
2685 CGEN_CPU_OPEN_END);
2686}
2687
2688/* Close a cpu table.
2689 ??? This can live in a machine independent file, but there's currently
2690 no place to put this file (there's no libcgen). libopcodes is the wrong
2691 place as some simulator ports use this but they don't use libopcodes. */
2692
2693void
2694mep_cgen_cpu_close (CGEN_CPU_DESC cd)
2695{
2696 unsigned int i;
2697 const CGEN_INSN *insns;
2698
2699 if (cd->macro_insn_table.init_entries)
2700 {
2701 insns = cd->macro_insn_table.init_entries;
2702 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2703 if (CGEN_INSN_RX ((insns)))
2704 regfree (CGEN_INSN_RX (insns));
2705 }
2706
2707 if (cd->insn_table.init_entries)
2708 {
2709 insns = cd->insn_table.init_entries;
2710 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2711 if (CGEN_INSN_RX (insns))
2712 regfree (CGEN_INSN_RX (insns));
2713 }
2714
2715 if (cd->macro_insn_table.init_entries)
2716 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2717
2718 if (cd->insn_table.init_entries)
2719 free ((CGEN_INSN *) cd->insn_table.init_entries);
2720
2721 if (cd->hw_table.entries)
2722 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2723
2724 if (cd->operand_table.entries)
2725 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2726
2727 free (cd);
2728}
2729
GDB Binutils - Deliverables
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