Commit | Line | Data |
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bd2f2e55 DB |
1 | /* CPU data header for mep. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
9b201bb5 | 5 | Copyright 1996-2007 Free Software Foundation, Inc. |
bd2f2e55 DB |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9b201bb5 NC |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
bd2f2e55 | 13 | |
9b201bb5 NC |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
bd2f2e55 | 18 | |
9b201bb5 NC |
19 | You should have received a copy of the GNU General Public License along |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
bd2f2e55 DB |
22 | |
23 | */ | |
24 | ||
25 | #ifndef MEP_CPU_H | |
26 | #define MEP_CPU_H | |
27 | ||
28 | #include "opcode/cgen-bitset.h" | |
29 | ||
30 | #define CGEN_ARCH mep | |
31 | ||
32 | /* Given symbol S, return mep_cgen_<S>. */ | |
33 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
34 | #define CGEN_SYM(s) mep##_cgen_##s | |
35 | #else | |
36 | #define CGEN_SYM(s) mep/**/_cgen_/**/s | |
37 | #endif | |
38 | ||
39 | ||
40 | /* Selected cpu families. */ | |
41 | #define HAVE_CPU_MEPF | |
42 | ||
43 | #define CGEN_INSN_LSB0_P 0 | |
44 | ||
45 | /* Minimum size of any insn (in bytes). */ | |
46 | #define CGEN_MIN_INSN_SIZE 2 | |
47 | ||
48 | /* Maximum size of any insn (in bytes). */ | |
49 | #define CGEN_MAX_INSN_SIZE 4 | |
50 | ||
51 | #define CGEN_INT_INSN_P 1 | |
52 | ||
53 | /* Maximum number of syntax elements in an instruction. */ | |
3526b680 | 54 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 |
bd2f2e55 DB |
55 | |
56 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. | |
57 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands | |
58 | we can't hash on everything up to the space. */ | |
59 | #define CGEN_MNEMONIC_OPERANDS | |
60 | ||
61 | /* Maximum number of fields in an instruction. */ | |
3526b680 | 62 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10 |
bd2f2e55 DB |
63 | |
64 | /* Enums. */ | |
65 | ||
66 | /* Enum declaration for major opcodes. */ | |
67 | typedef enum major { | |
68 | MAJ_0, MAJ_1, MAJ_2, MAJ_3 | |
69 | , MAJ_4, MAJ_5, MAJ_6, MAJ_7 | |
70 | , MAJ_8, MAJ_9, MAJ_10, MAJ_11 | |
71 | , MAJ_12, MAJ_13, MAJ_14, MAJ_15 | |
72 | } MAJOR; | |
73 | ||
bd2f2e55 DB |
74 | /* Attributes. */ |
75 | ||
76 | /* Enum declaration for machine type selection. */ | |
77 | typedef enum mach_attr { | |
40493983 DD |
78 | MACH_BASE, MACH_MEP, MACH_H1, MACH_C5 |
79 | , MACH_MAX | |
bd2f2e55 DB |
80 | } MACH_ATTR; |
81 | ||
82 | /* Enum declaration for instruction set selection. */ | |
83 | typedef enum isa_attr { | |
3526b680 DD |
84 | ISA_MEP, ISA_EXT_CORE1, ISA_EXT_COP1_16, ISA_EXT_COP1_32 |
85 | , ISA_EXT_COP1_48, ISA_EXT_COP1_64, ISA_MAX | |
bd2f2e55 DB |
86 | } ISA_ATTR; |
87 | ||
88 | /* Enum declaration for datatype to use for C intrinsics mapping. */ | |
89 | typedef enum cdata_attr { | |
90 | CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT | |
91 | , CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT | |
92 | , CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT | |
93 | } CDATA_ATTR; | |
94 | ||
95 | /* Enum declaration for . */ | |
96 | typedef enum config_attr { | |
c1a0a41f | 97 | CONFIG_NONE, CONFIG_DEFAULT |
bd2f2e55 DB |
98 | } CONFIG_ATTR; |
99 | ||
3526b680 DD |
100 | /* Enum declaration for slots for which this opcode is valid - c3, p0s, p0, p1. */ |
101 | typedef enum slots_attr { | |
102 | SLOTS_CORE, SLOTS_C3, SLOTS_P0S, SLOTS_P0 | |
103 | , SLOTS_P1 | |
104 | } SLOTS_ATTR; | |
105 | ||
bd2f2e55 DB |
106 | /* Number of architecture variants. */ |
107 | #define MAX_ISAS ((int) ISA_MAX) | |
108 | #define MAX_MACHS ((int) MACH_MAX) | |
109 | ||
110 | /* Ifield support. */ | |
111 | ||
112 | /* Ifield attribute indices. */ | |
113 | ||
114 | /* Enum declaration for cgen_ifld attrs. */ | |
115 | typedef enum cgen_ifld_attr { | |
116 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED | |
117 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 | |
118 | , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS | |
119 | } CGEN_IFLD_ATTR; | |
120 | ||
121 | /* Number of non-boolean elements in cgen_ifld_attr. */ | |
122 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) | |
123 | ||
124 | /* cgen_ifld attribute accessor macros. */ | |
125 | #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) | |
126 | #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) | |
127 | #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) | |
128 | #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) | |
129 | #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) | |
130 | #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) | |
131 | #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) | |
132 | #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) | |
133 | ||
134 | /* Enum declaration for mep ifield types. */ | |
135 | typedef enum ifield_type { | |
136 | MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN | |
137 | , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2 | |
40493983 DD |
138 | , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_EXT4 |
139 | , MEP_F_EXT62, MEP_F_CRN, MEP_F_CSRN_HI, MEP_F_CSRN_LO | |
140 | , MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO, MEP_F_CRNX | |
141 | , MEP_F_0, MEP_F_1, MEP_F_2, MEP_F_3 | |
142 | , MEP_F_4, MEP_F_5, MEP_F_6, MEP_F_7 | |
143 | , MEP_F_8, MEP_F_9, MEP_F_10, MEP_F_11 | |
144 | , MEP_F_12, MEP_F_13, MEP_F_14, MEP_F_15 | |
145 | , MEP_F_16, MEP_F_17, MEP_F_18, MEP_F_19 | |
146 | , MEP_F_20, MEP_F_21, MEP_F_22, MEP_F_23 | |
147 | , MEP_F_24, MEP_F_25, MEP_F_26, MEP_F_27 | |
148 | , MEP_F_28, MEP_F_29, MEP_F_30, MEP_F_31 | |
149 | , MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2, MEP_F_24S5A2N_HI | |
150 | , MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO | |
151 | , MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9, MEP_F_7U9A2 | |
152 | , MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10, MEP_F_3U5 | |
153 | , MEP_F_4U8, MEP_F_5U8, MEP_F_5U24, MEP_F_6S8 | |
154 | , MEP_F_8S8, MEP_F_16U16, MEP_F_12U16, MEP_F_3U29 | |
155 | , MEP_F_CDISP10, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N | |
156 | , MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI | |
157 | , MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI | |
158 | , MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5 | |
159 | , MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20 | |
160 | , MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20 | |
3526b680 DD |
161 | , MEP_F_C5_RNMUIMM24, MEP_F_IVC2_2U4, MEP_F_IVC2_3U4, MEP_F_IVC2_8U4 |
162 | , MEP_F_IVC2_8S4, MEP_F_IVC2_1U6, MEP_F_IVC2_2U6, MEP_F_IVC2_3U6 | |
163 | , MEP_F_IVC2_6U6, MEP_F_IVC2_5U7, MEP_F_IVC2_4U8, MEP_F_IVC2_3U9 | |
164 | , MEP_F_IVC2_5U16, MEP_F_IVC2_5U21, MEP_F_IVC2_5U26, MEP_F_IVC2_1U31 | |
165 | , MEP_F_IVC2_4U16, MEP_F_IVC2_4U20, MEP_F_IVC2_4U24, MEP_F_IVC2_4U28 | |
166 | , MEP_F_IVC2_2U0, MEP_F_IVC2_3U0, MEP_F_IVC2_4U0, MEP_F_IVC2_5U0 | |
167 | , MEP_F_IVC2_8U0, MEP_F_IVC2_8S0, MEP_F_IVC2_6U2, MEP_F_IVC2_5U3 | |
168 | , MEP_F_IVC2_4U4, MEP_F_IVC2_3U5, MEP_F_IVC2_5U8, MEP_F_IVC2_4U10 | |
169 | , MEP_F_IVC2_3U12, MEP_F_IVC2_5U13, MEP_F_IVC2_2U18, MEP_F_IVC2_5U18 | |
170 | , MEP_F_IVC2_8U20, MEP_F_IVC2_8S20, MEP_F_IVC2_5U23, MEP_F_IVC2_2U23 | |
2f3565a3 DD |
171 | , MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CCRN_C3HI |
172 | , MEP_F_IVC2_CCRN_C3LO, MEP_F_IVC2_CRN, MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1 | |
173 | , MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO, MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2 | |
174 | , MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN_C3, MEP_F_IVC2_CCRN, MEP_F_IVC2_CRNX | |
175 | , MEP_F_MAX | |
bd2f2e55 DB |
176 | } IFIELD_TYPE; |
177 | ||
178 | #define MAX_IFLD ((int) MEP_F_MAX) | |
179 | ||
180 | /* Hardware attribute indices. */ | |
181 | ||
182 | /* Enum declaration for cgen_hw attrs. */ | |
183 | typedef enum cgen_hw_attr { | |
184 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE | |
185 | , CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH | |
186 | , CGEN_HW_ISA, CGEN_HW_END_NBOOLS | |
187 | } CGEN_HW_ATTR; | |
188 | ||
189 | /* Number of non-boolean elements in cgen_hw_attr. */ | |
190 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) | |
191 | ||
192 | /* cgen_hw attribute accessor macros. */ | |
193 | #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) | |
194 | #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) | |
195 | #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) | |
196 | #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) | |
197 | #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) | |
198 | #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) | |
199 | #define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_IS_FLOAT)) != 0) | |
200 | ||
201 | /* Enum declaration for mep hardware types. */ | |
202 | typedef enum cgen_hw_type { | |
203 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR | |
204 | , HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR | |
3526b680 DD |
205 | , HW_H_CR64, HW_H_CR64_W, HW_H_CR, HW_H_CCR |
206 | , HW_H_CCR_W, HW_H_CR_IVC2, HW_H_CCR_IVC2, HW_MAX | |
bd2f2e55 DB |
207 | } CGEN_HW_TYPE; |
208 | ||
209 | #define MAX_HW ((int) HW_MAX) | |
210 | ||
211 | /* Operand attribute indices. */ | |
212 | ||
213 | /* Enum declaration for cgen_operand attrs. */ | |
214 | typedef enum cgen_operand_attr { | |
215 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT | |
216 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY | |
217 | , CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH | |
218 | , CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS | |
219 | } CGEN_OPERAND_ATTR; | |
220 | ||
221 | /* Number of non-boolean elements in cgen_operand_attr. */ | |
222 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) | |
223 | ||
224 | /* cgen_operand attribute accessor macros. */ | |
225 | #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) | |
226 | #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) | |
227 | #define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset) | |
228 | #define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset) | |
229 | #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) | |
230 | #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) | |
231 | #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) | |
232 | #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) | |
233 | #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) | |
234 | #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) | |
235 | #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) | |
236 | #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) | |
237 | #define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0) | |
238 | ||
239 | /* Enum declaration for mep operand types. */ | |
240 | typedef enum cgen_operand_type { | |
241 | MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM | |
242 | , MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC | |
243 | , MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL | |
244 | , MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S | |
245 | , MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP | |
246 | , MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0 | |
247 | , MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW | |
248 | , MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG | |
249 | , MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP | |
250 | , MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN | |
251 | , MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64 | |
252 | , MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2 | |
253 | , MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2 | |
254 | , MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16 | |
255 | , MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8 | |
256 | , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3 | |
257 | , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2 | |
258 | , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4 | |
40493983 DD |
259 | , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4 |
260 | , MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12 | |
3526b680 DD |
261 | , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_CROC |
262 | , MEP_OPERAND_CRQC, MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2 | |
263 | , MEP_OPERAND_IVC_X_6_3, MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8 | |
264 | , MEP_OPERAND_IMM5P7, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4 | |
265 | , MEP_OPERAND_IMM3P5, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10 | |
266 | , MEP_OPERAND_IMM5P8, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23 | |
1d74713b DD |
267 | , MEP_OPERAND_IMM3P25, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20 |
268 | , MEP_OPERAND_IMM8P20, MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP | |
269 | , MEP_OPERAND_IVC_X_0_2, MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5 | |
270 | , MEP_OPERAND_IMM16P0, MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN | |
271 | , MEP_OPERAND_IVC2CCRN, MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX | |
bd2f2e55 DB |
272 | } CGEN_OPERAND_TYPE; |
273 | ||
274 | /* Number of operands types. */ | |
1d74713b | 275 | #define MAX_OPERANDS 122 |
bd2f2e55 DB |
276 | |
277 | /* Maximum number of operands referenced by any insn. */ | |
278 | #define MAX_OPERAND_INSTANCES 8 | |
279 | ||
280 | /* Insn attribute indices. */ | |
281 | ||
282 | /* Enum declaration for cgen_insn attrs. */ | |
283 | typedef enum cgen_insn_attr { | |
284 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI | |
285 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED | |
286 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN | |
287 | , CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN | |
288 | , CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN | |
289 | , CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN | |
290 | , CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP | |
291 | , CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE | |
292 | , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA | |
3526b680 | 293 | , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS |
bd2f2e55 DB |
294 | } CGEN_INSN_ATTR; |
295 | ||
296 | /* Number of non-boolean elements in cgen_insn_attr. */ | |
297 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) | |
298 | ||
299 | /* cgen_insn attribute accessor macros. */ | |
300 | #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
301 | #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) | |
302 | #define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
303 | #define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
3526b680 | 304 | #define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset) |
bd2f2e55 DB |
305 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) |
306 | #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) | |
307 | #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) | |
308 | #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) | |
309 | #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) | |
310 | #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) | |
311 | #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) | |
312 | #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) | |
313 | #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) | |
314 | #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) | |
315 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0) | |
316 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0) | |
317 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0) | |
318 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0) | |
319 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0) | |
320 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0) | |
321 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0) | |
322 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0) | |
323 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0) | |
324 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0) | |
325 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0) | |
326 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0) | |
327 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0) | |
328 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0) | |
329 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0) | |
330 | #define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MAY_TRAP)) != 0) | |
331 | #define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_ALONE)) != 0) | |
332 | #define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0) | |
333 | #define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0) | |
334 | #define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0) | |
335 | #define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0) | |
336 | #define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VOLATILE)) != 0) | |
337 | ||
338 | /* cgen.h uses things we just defined. */ | |
339 | #include "opcode/cgen.h" | |
340 | ||
341 | extern const struct cgen_ifld mep_cgen_ifld_table[]; | |
342 | ||
343 | /* Attributes. */ | |
344 | extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[]; | |
345 | extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[]; | |
346 | extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[]; | |
347 | extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[]; | |
348 | ||
349 | /* Hardware decls. */ | |
350 | ||
351 | extern CGEN_KEYWORD mep_cgen_opval_h_gpr; | |
352 | extern CGEN_KEYWORD mep_cgen_opval_h_csr; | |
353 | extern CGEN_KEYWORD mep_cgen_opval_h_cr64; | |
354 | extern CGEN_KEYWORD mep_cgen_opval_h_cr; | |
355 | extern CGEN_KEYWORD mep_cgen_opval_h_ccr; | |
3526b680 DD |
356 | extern CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2; |
357 | extern CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2; | |
bd2f2e55 DB |
358 | |
359 | extern const CGEN_HW_ENTRY mep_cgen_hw_table[]; | |
360 | ||
361 | ||
362 | ||
363 | #endif /* MEP_CPU_H */ |