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[deliverable/binutils-gdb.git] / opcodes / micromips-opc.c
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df58fc94 1/* micromips-opc.c. microMIPS opcode table.
df7b86aa 2 Copyright 2008, 2012 Free Software Foundation, Inc.
df58fc94
RS		 3 Contributed by Chao-ying Fu, MIPS Technologies, Inc.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
df58fc94 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
df58fc94
RS		 24#include "opcode/mips.h"
25
26#define UBD INSN_UNCOND_BRANCH_DELAY
27#define CBD INSN_COND_BRANCH_DELAY
f65c50ad
RS		 28#define NODS INSN_NO_DELAY_SLOT
29#define TRAP INSN_NO_DELAY_SLOT
df58fc94
RS		 30#define SM INSN_STORE_MEMORY
31#define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */
32#define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */
33
34/* For 16-bit/32-bit microMIPS instructions. They are used in pinfo2. */
35#define UBR INSN2_UNCOND_BRANCH
36#define CBR INSN2_COND_BRANCH
2b0c8b40
MR		 37#define WR_mb INSN2_WRITE_GPR_MB
38#define RD_mc INSN2_READ_GPR_MC
39#define RD_md INSN2_MOD_GPR_MD
40#define WR_md INSN2_MOD_GPR_MD
41#define RD_me INSN2_READ_GPR_ME
42#define RD_mf INSN2_MOD_GPR_MF
43#define WR_mf INSN2_MOD_GPR_MF
44#define RD_mg INSN2_READ_GPR_MG
e76ff5ab 45#define WR_mh INSN2_WRITE_GPR_MH
2b0c8b40
MR		 46#define RD_mj INSN2_READ_GPR_MJ
47#define WR_mj INSN2_WRITE_GPR_MJ
48#define RD_ml RD_mc /* Reuse, since the bit position is the same. */
49#define RD_mmn INSN2_READ_GPR_MMN
50#define RD_mp INSN2_READ_GPR_MP
51#define WR_mp INSN2_WRITE_GPR_MP
52#define RD_mq INSN2_READ_GPR_MQ
53#define RD_sp INSN2_MOD_SP
54#define WR_sp INSN2_MOD_SP
df58fc94
RS		 55#define RD_31 INSN2_READ_GPR_31
56#define RD_gp INSN2_READ_GP
57#define RD_pc INSN2_READ_PC
58
59/* For 32-bit microMIPS instructions. */
2b0c8b40 60#define WR_s INSN_WRITE_GPR_S
df58fc94
RS		 61#define WR_d INSN_WRITE_GPR_D
62#define WR_t INSN_WRITE_GPR_T
63#define WR_31 INSN_WRITE_GPR_31
64#define WR_D INSN_WRITE_FPR_D
65#define WR_T INSN_WRITE_FPR_T
66#define WR_S INSN_WRITE_FPR_S
67#define WR_CC INSN_WRITE_COND_CODE
68
69#define RD_s INSN_READ_GPR_S
70#define RD_b INSN_READ_GPR_S
71#define RD_t INSN_READ_GPR_T
72#define RD_T INSN_READ_FPR_T
73#define RD_S INSN_READ_FPR_S
74#define RD_R INSN_READ_FPR_R
75#define RD_D INSN2_READ_FPR_D /* Used in pinfo2. */
76#define RD_CC INSN_READ_COND_CODE
77#define RD_C0 INSN_COP
78#define RD_C1 INSN_COP
79#define RD_C2 INSN_COP
80#define WR_C0 INSN_COP
81#define WR_C1 INSN_COP
82#define WR_C2 INSN_COP
83#define CP INSN_COP
84
85#define WR_HI INSN_WRITE_HI
86#define RD_HI INSN_READ_HI
87
88#define WR_LO INSN_WRITE_LO
89#define RD_LO INSN_READ_LO
90
91#define WR_HILO WR_HI|WR_LO
92#define RD_HILO RD_HI|RD_LO
93#define MOD_HILO WR_HILO|RD_HILO
94
95/* Reuse INSN_ISA1 for 32-bit microMIPS ISA. All instructions in I1
96 are accepted as 32-bit microMIPS ISA.
97 Reuse INSN_ISA3 for 64-bit microMIPS ISA. All instructions in I3
98 are accepted as 64-bit microMIPS ISA. */
99#define I1 INSN_ISA1
100#define I3 INSN_ISA3
101
03f66e8a
MR		 102/* MIPS DSP ASE support. */
103#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
104#define RD_a RD_HILO /* Read DSP accumulators (reuse RD_HILO). */
105#define MOD_a WR_a|RD_a
106#define DSP_VOLA INSN_NO_DELAY_SLOT
d301a56b
RS		 107#define D32 ASE_DSP
108#define D33 ASE_DSPR2
03f66e8a 109
dec0624d 110/* MIPS MCU (MicroController) ASE support. */
d301a56b 111#define MC ASE_MCU
dec0624d 112
7f3c4072
CM		 113/* MIPS Enhanced VA Scheme. */
114#define EVA ASE_EVA
115
116/* TLB invalidate instruction support. */
117#define TLBINV ASE_EVA
118
ba92f7fb
CF		 119/* MIPS Virtualization ASE. */
120#define IVIRT ASE_VIRT
121#define IVIRT64 ASE_VIRT64
122
df58fc94
RS		 123const struct mips_opcode micromips_opcodes[] =
124{
125/* These instructions appear first so that the disassembler will find
126 them first. The assemblers uses a hash table based on the
127 instruction name anyhow. */
d301a56b 128/* name, args, match, mask, pinfo, pinfo2, membership, [ase], [exclusions] */
df58fc94 129{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
df58fc94
RS		 130{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
131{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I1 },
132{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1 },
133{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
134{"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
135{"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
136{"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
2b0c8b40 137{"li", "md,mI", 0xec00, 0xfc00, 0, WR_md, I1 },
df58fc94
RS		 138{"li", "t,j", 0x30000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
139{"li", "t,i", 0x50000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* ori */
140#if 0
141/* Disabled until we can handle 48-bit opcodes. */
142{"li", "s,I", 0x7c0000010000, 0xfc00001f0000, WR_t, 0, I3 }, /* li48 */
143#endif
144{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
145{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
2b0c8b40 146{"move", "mp,mj", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 },
df58fc94
RS		 147{"move", "d,s", 0x58000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I3 }, /* daddu */
148{"move", "d,s", 0x00000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* addu */
149{"move", "d,s", 0x00000290, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* or */
150{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1 },
151{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* beq 0, 0 */
152{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* bgez 0 */
153{"bal", "p", 0x40600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD32, I1 }, /* bgezal 0 */
154{"bals", "p", 0x42600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD16, I1 }, /* bgezals 0 */
f65c50ad 155{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1 }, /* beqzc 0 */
df58fc94
RS		 156
157{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
158{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
159{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
160{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
d301a56b 161{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
d301a56b 162{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC },
df58fc94
RS		 163{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
164{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
165{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
166{"add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
167{"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
168{"addi", "t,r,j", 0x10000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2b0c8b40
MR		 169{"addiu", "mp,mj,mZ", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
170{"addiu", "md,ms,mW", 0x6c01, 0xfc01, 0, WR_md|RD_sp, I1 }, /* addiur1sp */
171{"addiu", "md,mc,mB", 0x6c00, 0xfc01, 0, WR_md|RD_mc, I1 }, /* addiur2 */
172{"addiu", "ms,mt,mY", 0x4c01, 0xfc01, 0, WR_sp|RD_sp, I1 }, /* addiusp */
173{"addiu", "mp,mt,mX", 0x4c00, 0xfc01, 0, WR_mp|RD_mp, I1 }, /* addius5 */
174{"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, 0, WR_mb|RD_pc, I1 }, /* addiupc */
df58fc94 175{"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2b0c8b40
MR		 176{"addiupc", "mb,mQ", 0x78000000, 0xfc000000, 0, WR_mb|RD_pc, I1 },
177{"addiur1sp", "md,mW", 0x6c01, 0xfc01, 0, WR_md|RD_sp, I1 },
178{"addiur2", "md,mc,mB", 0x6c00, 0xfc01, 0, WR_md|RD_mc, I1 },
179{"addiusp", "mY", 0x4c01, 0xfc01, 0, WR_sp|RD_sp, I1 },
180{"addius5", "mp,mX", 0x4c00, 0xfc01, 0, WR_mp|RD_mp, I1 },
181{"addu", "mp,mj,mz", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
182{"addu", "mp,mz,mj", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
183{"addu", "md,me,ml", 0x0400, 0xfc01, 0, WR_md|RD_me|RD_ml, I1 },
df58fc94
RS		 184{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
185{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
514f48bb 186/* We have no flag to mark the read from "y", so we use NODS to disable
df58fc94 187 delay slot scheduling of ALNV.PS altogether. */
514f48bb 188{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, NODS|WR_D|RD_S|RD_T|FP_D, 0, I1 },
2b0c8b40
MR		 189{"and", "mf,mt,mg", 0x4480, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
190{"and", "mf,mg,mx", 0x4480, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
df58fc94
RS		 191{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
192{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
2b0c8b40 193{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, WR_md|RD_mc, I1 },
df58fc94 194{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
d301a56b 195{"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
d301a56b 196{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC },
df58fc94
RS		 197/* b is at the top of the table. */
198/* bal is at the top of the table. */
199{"bc1f", "p", 0x43800000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
200{"bc1f", "N,p", 0x43800000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
201{"bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
202{"bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
203{"bc2f", "p", 0x42800000, 0xffff0000, CBD|RD_CC, 0, I1 },
204{"bc2f", "N,p", 0x42800000, 0xffe30000, CBD|RD_CC, 0, I1 },
205{"bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
206{"bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
207{"bc1t", "p", 0x43a00000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
208{"bc1t", "N,p", 0x43a00000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
209{"bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
210{"bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
211{"bc2t", "p", 0x42a00000, 0xffff0000, CBD|RD_CC, 0, I1 },
212{"bc2t", "N,p", 0x42a00000, 0xffe30000, CBD|RD_CC, 0, I1 },
213{"bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
214{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
2b0c8b40 215{"beqz", "md,mE", 0x8c00, 0xfc00, CBD, RD_md, I1 },
df58fc94 216{"beqz", "s,p", 0x94000000, 0xffe00000, CBD|RD_s, 0, I1 },
f65c50ad 217{"beqzc", "s,p", 0x40e00000, 0xffe00000, NODS|RD_s, CBR, I1 },
df58fc94 218{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
2b0c8b40
MR		 219{"beq", "md,mz,mE", 0x8c00, 0xfc00, CBD, RD_md, I1 }, /* beqz */
220{"beq", "mz,md,mE", 0x8c00, 0xfc00, CBD, RD_md, I1 }, /* beqz */
df58fc94
RS		 221{"beq", "s,t,p", 0x94000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
222{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
223{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
224{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1 },
225{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
226{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
227{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1 },
228{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1 },
229{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
230{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
231{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1 },
232{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1 },
233{"bgez", "s,p", 0x40400000, 0xffe00000, CBD|RD_s, 0, I1 },
234{"bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1 },
235{"bgezal", "s,p", 0x40600000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
236{"bgezals", "s,p", 0x42600000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
237{"bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1 },
238{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
239{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
240{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1 },
241{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1 },
242{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
243{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
244{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1 },
245{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1 },
246{"bgtz", "s,p", 0x40c00000, 0xffe00000, CBD|RD_s, 0, I1 },
247{"bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1 },
248{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
249{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
250{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1 },
251{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1 },
252{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
253{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
254{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1 },
255{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1 },
256{"blez", "s,p", 0x40800000, 0xffe00000, CBD|RD_s, 0, I1 },
257{"blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1 },
258{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
259{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
260{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1 },
261{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1 },
262{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
263{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
264{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1 },
265{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1 },
266{"bltz", "s,p", 0x40000000, 0xffe00000, CBD|RD_s, 0, I1 },
267{"bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1 },
268{"bltzal", "s,p", 0x40200000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
269{"bltzals", "s,p", 0x42200000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
270{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1 },
2b0c8b40 271{"bnez", "md,mE", 0xac00, 0xfc00, CBD, RD_md, I1 },
df58fc94 272{"bnez", "s,p", 0xb4000000, 0xffe00000, CBD|RD_s, 0, I1 },
f65c50ad 273{"bnezc", "s,p", 0x40a00000, 0xffe00000, NODS|RD_s, CBR, I1 },
df58fc94 274{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1 },
2b0c8b40
MR		 275{"bne", "md,mz,mE", 0xac00, 0xfc00, CBD, RD_md, I1 }, /* bnez */
276{"bne", "mz,md,mE", 0xac00, 0xfc00, CBD, RD_md, I1 }, /* bnez */
df58fc94
RS		 277{"bne", "s,t,p", 0xb4000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
278{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
279{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1 },
280{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1 },
281{"break", "", 0x4680, 0xffff, TRAP, 0, I1 },
282{"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1 },
283{"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1 },
284{"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1 },
285{"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1 },
286{"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
287{"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
288{"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
289{"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
290{"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
291{"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
292{"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
293{"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
294{"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
295{"c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
296{"c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
297{"c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
298{"c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
299{"c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
300{"c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
301{"c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
302{"c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
303{"c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
304{"c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
305{"c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
306{"c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
307{"c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
308{"c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
309{"c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
310{"c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
311{"c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
312{"c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
313{"c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
314{"c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
315{"c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
316{"c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
317{"c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
318{"c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
319{"c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
320{"c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
321{"c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
322{"c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
323{"c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
324{"c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
325{"c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
326{"c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
327{"c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
328{"c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
329{"c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
330{"c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
331{"c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
332{"c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
333{"c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
334{"c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
335{"c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
336{"c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
337{"c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
338{"c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
339{"c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
340{"c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
341{"c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
342{"c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
343{"c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
344{"c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
345{"c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
346{"c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
347{"c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
348{"c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
349{"c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
350{"c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
351{"c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
352{"c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
353{"c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
354{"c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
355{"c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
356{"c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
357{"c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
358{"c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
359{"c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
360{"c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
361{"c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
362{"c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
363{"c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
364{"c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
365{"c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
366{"c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
367{"c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
368{"c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
369{"c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
370{"c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
371{"c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
372{"c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
373{"c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
374{"c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
375{"c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
376{"c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
377{"c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
378{"c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
379{"c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
380{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
381{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
382{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_b, 0, I1 },
df58fc94
RS		 383{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1 },
384{"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
385{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
386{"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
387{"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
388{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_t|RD_C1|FP_S, 0, I1 },
389{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_t|RD_C1|FP_S, 0, I1 },
390{"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
391{"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
392{"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
393{"cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1 },
394{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_t|WR_CC|FP_S, 0, I1 },
395{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_t|WR_CC|FP_S, 0, I1 },
396{"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
397{"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
398{"cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
399{"cvt.d.w", "T,S", 0x5400337b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
400{"cvt.l.d", "T,S", 0x5400413b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
401{"cvt.l.s", "T,S", 0x5400013b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
402{"cvt.s.l", "T,S", 0x54005b7b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
403{"cvt.s.d", "T,S", 0x54001b7b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
404{"cvt.s.w", "T,S", 0x54003b7b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
405{"cvt.s.pl", "T,S", 0x5400213b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
406{"cvt.s.pu", "T,S", 0x5400293b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
407{"cvt.w.d", "T,S", 0x5400493b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
408{"cvt.w.s", "T,S", 0x5400093b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
409{"cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I1 },
410{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
411{"dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
412{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
413{"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_t|RD_s, 0, I3 },
414{"daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
415{"daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_t|RD_s, 0, I3 },
416{"daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
417{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
418{"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
419{"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
f65c50ad 420{"deret", "", 0x0000e37c, 0xffffffff, NODS, 0, I1 },
df58fc94
RS		 421{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I3 },
422{"dext", "t,r,+A,+C",0x5800002c, 0xfc00003f, WR_t|RD_s, 0, I3 },
423{"dextm", "t,r,+A,+G",0x58000024, 0xfc00003f, WR_t|RD_s, 0, I3 },
424{"dextu", "t,r,+E,+H",0x58000014, 0xfc00003f, WR_t|RD_s, 0, I3 },
425/* For ddiv, see the comments about div. */
426{"ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
427{"ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I3 },
428{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
429{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
430/* For ddivu, see the comments about div. */
431{"ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
432{"ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I3 },
433{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
434{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
2b0c8b40
MR		 435{"di", "", 0x0000477c, 0xffffffff, WR_s|RD_C0, 0, I1 },
436{"di", "s", 0x0000477c, 0xffe0ffff, WR_s|RD_C0, 0, I1 },
df58fc94
RS		 437{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I3 },
438{"dins", "t,r,+A,+B",0x5800000c, 0xfc00003f, WR_t|RD_s, 0, I3 },
439{"dinsm", "t,r,+A,+F",0x58000004, 0xfc00003f, WR_t|RD_s, 0, I3 },
440{"dinsu", "t,r,+E,+F",0x58000034, 0xfc00003f, WR_t|RD_s, 0, I3 },
441/* The MIPS assembler treats the div opcode with two operands as
442 though the first operand appeared twice (the first operand is both
443 a source and a destination). To get the div machine instruction,
444 you must use an explicit destination of $0. */
445{"div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
446{"div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I1 },
447{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
448{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
449{"div.d", "D,V,T", 0x540001f0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
450{"div.s", "D,V,T", 0x540000f0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
451/* For divu, see the comments about div. */
452{"divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
453{"divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I1 },
454{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
455{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
456{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
457{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
458{"dli", "t,j", 0x30000000, 0xfc1f0000, WR_t, 0, I3 }, /* addiu */
459{"dli", "t,i", 0x50000000, 0xfc1f0000, WR_t, 0, I3 }, /* ori */
460{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
461{"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_t|RD_C0, 0, I3 },
df58fc94 462{"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I3 },
ba92f7fb 463{"dmfgc0", "t,G", 0x580000e7, 0xfc00ffff, WR_t|RD_C0, 0, 0, IVIRT64 },
ba92f7fb 464{"dmfgc0", "t,G,H", 0x580000e7, 0xfc00c7ff, WR_t|RD_C0, 0, 0, IVIRT64 },
df58fc94 465{"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I3 },
df58fc94 466{"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I3 },
ba92f7fb 467{"dmtgc0", "t,G", 0x580002e7, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 },
ba92f7fb 468{"dmtgc0", "t,G,H", 0x580002e7, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 },
df58fc94
RS		 469{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 },
470{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 },
471{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I3 },
472{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I3 },
473{"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_t|RD_C2, 0, I3 },
474/*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_t|RD_C2, 0, I3 },*/
475{"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I3 },
476/*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_t|WR_C2|WR_CC, 0, I3 },*/
477{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
478{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
479{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
480{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
481{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
482{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
483{"dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
484{"dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
485{"dneg", "d,w", 0x58000190, 0xfc1f07ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
486{"dnegu", "d,w", 0x580001d0, 0xfc1f07ff, WR_d|RD_t, 0, I3 }, /* dsubu 0 */
487{"drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
488{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 },
489{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
490{"dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
491{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
492{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
493{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
494{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
495{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
496{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
497{"dror", "t,r,<", 0x580000c0, 0xfc0007ff, WR_t|RD_s, 0, I3 },
498{"drorv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I3 },
499{"dror32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t|RD_s, 0, I3 },
500{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
501{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
502{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
503{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
504{"drotrv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I3 },
505{"drotr32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t|RD_s, 0, I3 },
506{"dsbh", "t,r", 0x58007b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
507{"dshd", "t,r", 0x5800fb3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
508{"dsllv", "d,t,s", 0x58000010, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
509{"dsll32", "t,r,<", 0x58000008, 0xfc0007ff, WR_t|RD_s, 0, I3 },
510{"dsll", "d,t,s", 0x58000010, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
511{"dsll", "t,r,>", 0x58000008, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsll32 */
512{"dsll", "t,r,<", 0x58000000, 0xfc0007ff, WR_t|RD_s, 0, I3 },
513{"dsrav", "d,t,s", 0x58000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
514{"dsra32", "t,r,<", 0x58000088, 0xfc0007ff, WR_t|RD_s, 0, I3 },
515{"dsra", "d,t,s", 0x58000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
516{"dsra", "t,r,>", 0x58000088, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsra32 */
517{"dsra", "t,r,<", 0x58000080, 0xfc0007ff, WR_t|RD_s, 0, I3 },
518{"dsrlv", "d,t,s", 0x58000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
519{"dsrl32", "t,r,<", 0x58000048, 0xfc0007ff, WR_t|RD_s, 0, I3 },
520{"dsrl", "d,t,s", 0x58000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
521{"dsrl", "t,r,>", 0x58000048, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsrl32 */
522{"dsrl", "t,r,<", 0x58000040, 0xfc0007ff, WR_t|RD_s, 0, I3 },
523{"dsub", "d,v,t", 0x58000190, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
524{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
525{"dsubu", "d,v,t", 0x580001d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
526{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
2b0c8b40
MR		 527{"ei", "", 0x0000577c, 0xffffffff, WR_s|WR_C0, 0, I1 },
528{"ei", "s", 0x0000577c, 0xffe0ffff, WR_s|WR_C0, 0, I1 },
f65c50ad 529{"eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1 },
df58fc94
RS		 530{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_t|RD_s, 0, I1 },
531{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
532{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
533{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
534{"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
ba92f7fb
CF		 535{"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT },
536{"hypcall", "B", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT },
df58fc94 537{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s, 0, I1 },
d301a56b 538{"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, 0, MC },
2b0c8b40 539{"jr", "mj", 0x4580, 0xffe0, UBD, RD_mj, I1 },
df58fc94
RS		 540{"jr", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr */
541{"jrs", "s", 0x00004f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs */
2b0c8b40 542{"jraddiusp", "mP", 0x4700, 0xffe0, NODS, UBR|RD_31|WR_sp|RD_sp, I1 },
833794fc
MR		 543/* This macro is after the real instruction so that it only matches with
544 -minsn32. */
545{"jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1 },
2b0c8b40 546{"jrc", "mj", 0x45a0, 0xffe0, NODS, UBR|RD_mj, I1 },
833794fc
MR		 547/* This macro is after the real instruction so that it only matches with
548 -minsn32. */
549{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1 },
df58fc94
RS		 550{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr.hb */
551{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs.hb */
2b0c8b40 552{"j", "mj", 0x4580, 0xffe0, UBD, RD_mj, I1 }, /* jr */
df58fc94
RS		 553{"j", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jr */
554/* SVR4 PIC code requires special handling for j, so it must be a
555 macro. */
556{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
557/* This form of j is used by the disassembler and internally by the
558 assembler, but will never match user input (because the line above
559 will match first). */
560{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1 },
2b0c8b40
MR		 561{"jalr", "mj", 0x45c0, 0xffe0, UBD|WR_31, RD_mj|BD32, I1 },
562{"jalr", "my,mj", 0x45c0, 0xffe0, UBD|WR_31, RD_mj|BD32, I1 },
df58fc94
RS		 563{"jalr", "s", 0x03e00f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1 },
564{"jalr", "t,s", 0x00000f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1 },
565{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1 },
566{"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1 },
2b0c8b40
MR		 567{"jalrs", "mj", 0x45e0, 0xffe0, UBD|WR_31, RD_mj|BD16, I1 },
568{"jalrs", "my,mj", 0x45e0, 0xffe0, UBD|WR_31, RD_mj|BD16, I1 },
df58fc94
RS		 569{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1 },
570{"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1 },
571{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1 },
572{"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1 },
573/* SVR4 PIC code requires special handling for jal, so it must be a
574 macro. */
575{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
576{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
577{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
578/* This form of jal is used by the disassembler and internally by the
579 assembler, but will never match user input (because the line above
580 will match first). */
581{"jal", "a", 0xf4000000, 0xfc000000, UBD|WR_31, BD32, I1 },
582{"jals", "d,s", 0, (int) M_JALS_2, INSN_MACRO, 0, I1 },
583{"jals", "s", 0, (int) M_JALS_1, INSN_MACRO, 0, I1 },
584{"jals", "a", 0, (int) M_JALS_A, INSN_MACRO, 0, I1 },
585{"jals", "a", 0x74000000, 0xfc000000, UBD|WR_31, BD16, I1 },
27c5c572 586{"jalx", "+i", 0xf0000000, 0xfc000000, UBD|WR_31, BD32, I1 },
df58fc94
RS		 587{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
588{"lb", "t,o(b)", 0x1c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
589{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
2b0c8b40 590{"lbu", "md,mG(ml)", 0x0800, 0xfc00, 0, WR_md|RD_ml, I1 },
df58fc94
RS		 591{"lbu", "t,o(b)", 0x14000000, 0xfc000000, RD_b|WR_t, 0, I1 },
592{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
593{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
594/* The macro has to be first to handle o32 correctly. */
df58fc94 595{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
f2ae14a1 596{"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b|WR_t, 0, I3 },
df58fc94
RS		 597{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
598{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
599{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
600{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
601{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
df58fc94
RS		 602{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1 },
603{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 }, /* ldc1 */
604{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
605{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_t|RD_b, 0, I3 },
df58fc94
RS		 606{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
607{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_b, 0, I3 },
df58fc94
RS		 608{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3 },
609{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, RD_b|WR_t, 0, I3 },
df58fc94
RS		 610{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3 },
611{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_t|RD_b, 0, I3 },
df58fc94
RS		 612{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
613{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
614{"lh", "t,o(b)", 0x3c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
615{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
2b0c8b40 616{"lhu", "md,mH(ml)", 0x2800, 0xfc00, 0, WR_md|RD_ml, I1 },
df58fc94
RS		 617{"lhu", "t,o(b)", 0x34000000, 0xfc000000, RD_b|WR_t, 0, I1 },
618{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
619/* li is at the start of the table. */
620{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1 },
621{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1 },
622{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 },
623{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 },
624{"ll", "t,~(b)", 0x60003000, 0xfc00f000, RD_b|WR_t, 0, I1 },
df58fc94
RS		 625{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1 },
626{"lld", "t,~(b)", 0x60007000, 0xfc00f000, RD_b|WR_t, 0, I3 },
df58fc94 627{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
2b0c8b40 628{"lui", "s,u", 0x41a00000, 0xffe00000, WR_s, 0, I1 },
df58fc94 629{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
2b0c8b40
MR		 630{"lw", "md,mJ(ml)", 0x6800, 0xfc00, 0, WR_md|RD_ml, I1 },
631{"lw", "mp,mU(ms)", 0x4800, 0xfc00, 0, WR_mp|RD_sp, I1 }, /* lwsp */
632{"lw", "md,mA(ma)", 0x6400, 0xfc00, 0, WR_md|RD_gp, I1 }, /* lwgp */
df58fc94
RS		 633{"lw", "t,o(b)", 0xfc000000, 0xfc000000, RD_b|WR_t, 0, I1 },
634{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
635{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 },
636{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 },
637{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
638{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
639{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
df58fc94
RS		 640{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
641{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
642{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
643{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 },
df58fc94
RS		 644{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
645{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
df58fc94 646{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
2b0c8b40 647{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, NODS, RD_sp, I1 },
f65c50ad 648{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_b|NODS, 0, I1 },
df58fc94 649{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1 },
f65c50ad 650{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, RD_b|WR_t|NODS, 0, I1 },
df58fc94
RS		 651{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1 },
652{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 },
df58fc94
RS		 653{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
654{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, RD_b|WR_t, 0, I3 },
df58fc94
RS		 655{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
656{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_D|RD_t|RD_b|FP_S, 0, I1 },
657{"flush", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
df58fc94
RS		 658{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
659{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 },
660{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
d301a56b 661{"madd", "7,s,t", 0x00000abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
df58fc94
RS		 662{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
663{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
664{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
665{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
d301a56b 666{"maddu", "7,s,t", 0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
df58fc94 667{"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t|RD_C0, 0, I1 },
df58fc94
RS		 668{"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
669{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 },
670{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 },
671{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
ba92f7fb 672{"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_t|RD_C0, 0, 0, IVIRT },
ba92f7fb 673{"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_t|RD_C0, 0, 0, IVIRT },
df58fc94
RS		 674{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 },
675{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 },
676{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
2b0c8b40
MR		 677{"mfhi", "mj", 0x4600, 0xffe0, RD_HI, WR_mj, I1 },
678{"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_s|RD_HI, 0, I1 },
d301a56b 679{"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_s|RD_HI, 0, 0, D32 },
2b0c8b40
MR		 680{"mflo", "mj", 0x4640, 0xffe0, RD_LO, WR_mj, I1 },
681{"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_s|RD_LO, 0, I1 },
d301a56b 682{"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_s|RD_LO, 0, 0, D32 },
df58fc94
RS		 683{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
684{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
685{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
e76ff5ab 686{"movep", "mh,mm,mn", 0x8400, 0xfc01, NODS, WR_mh|RD_mmn, I1 },
833794fc
MR		 687/* This macro is after the real instruction so that it only matches with
688 -minsn32. */
e76ff5ab 689{"movep", "mh,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1 },
df58fc94
RS		 690{"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 },
691{"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
692{"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 },
693{"movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
694{"movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
695{"movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
696{"movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
697{"movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
698{"movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 },
699{"movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
700{"movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 },
701{"movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
702{"movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
703{"movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
704{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
705{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
706{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
d301a56b 707{"msub", "7,s,t", 0x00002abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
df58fc94
RS		 708{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
709{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
710{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
711{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
d301a56b 712{"msubu", "7,s,t", 0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
df58fc94 713{"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I1 },
df58fc94
RS		 714{"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
715{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 },
716{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 },
717{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
ba92f7fb 718{"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT },
ba92f7fb 719{"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT },
df58fc94
RS		 720{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
721{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
722{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
723{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_s|WR_HI, 0, I1 },
d301a56b 724{"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_s|WR_HI, 0, 0, D32 },
df58fc94 725{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_s|WR_LO, 0, I1 },
d301a56b 726{"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_s|WR_LO, 0, 0, D32 },
df58fc94
RS		 727{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I1 },
728{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
729{"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
730{"mul.s", "D,V,T", 0x540000b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
731{"mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
732{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
733{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
734{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
735{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
736{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
d301a56b 737{"mult", "7,s,t", 0x00000cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, 0, D32 },
df58fc94 738{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
d301a56b 739{"multu", "7,s,t", 0x00001cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, 0, D32 },
df58fc94
RS		 740{"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
741{"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
742{"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
743{"neg.s", "T,V", 0x54000b7b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
744{"neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
745{"nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
746{"nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
747{"nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
748{"nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
749{"nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
750{"nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
751/* nop is at the start of the table. */
2b0c8b40 752{"not", "mf,mg", 0x4400, 0xffc0, 0, WR_mf|RD_mg, I1 }, /* put not before nor */
df58fc94 753{"not", "d,v", 0x000002d0, 0xffe007ff, WR_d|RD_s|RD_t, 0, I1 }, /* nor d,s,0 */
2b0c8b40
MR		 754{"nor", "mf,mz,mg", 0x4400, 0xffc0, 0, WR_mf|RD_mg, I1 }, /* not */
755{"nor", "mf,mg,mz", 0x4400, 0xffc0, 0, WR_mf|RD_mg, I1 }, /* not */
df58fc94
RS		 756{"nor", "d,v,t", 0x000002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
757{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
2b0c8b40
MR		 758{"or", "mp,mj,mz", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
759{"or", "mp,mz,mj", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
760{"or", "mf,mt,mg", 0x44c0, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
761{"or", "mf,mg,mx", 0x44c0, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
df58fc94
RS		 762{"or", "d,v,t", 0x00000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
763{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
2b0c8b40 764{"ori", "mp,mj,mZ", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
df58fc94
RS		 765{"ori", "t,r,i", 0x50000000, 0xfc000000, WR_t|RD_s, 0, I1 },
766{"pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
767{"plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
768{"pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
769{"puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
770/* pref is at the start of the table. */
771{"recip.d", "T,S", 0x5400523b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
772{"recip.s", "T,S", 0x5400123b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
773{"rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
774{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
775{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
776{"remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
777{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
778{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
779{"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, 0, WR_t, I1 },
780{"rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_t, 0, I1 },
781{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
782{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
783{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
784{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
785{"ror", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t|RD_s, 0, I1 },
786{"rorv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I1 },
787{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
788{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
789{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
790{"rotr", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t|RD_s, 0, I1 },
791{"rotrv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I1 },
792{"round.l.d", "T,S", 0x5400733b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
793{"round.l.s", "T,S", 0x5400333b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
794{"round.w.d", "T,S", 0x54007b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
795{"round.w.s", "T,S", 0x54003b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
796{"rsqrt.d", "T,S", 0x5400423b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
797{"rsqrt.s", "T,S", 0x5400023b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
2b0c8b40 798{"sb", "mq,mL(ml)", 0x8800, 0xfc00, SM, RD_mq|RD_ml, I1 },
df58fc94
RS		 799{"sb", "t,o(b)", 0x18000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
800{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
801{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I1 },
df58fc94
RS		 802{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1 },
803{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I3 },
df58fc94
RS		 804{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
805/* The macro has to be first to handle o32 correctly. */
df58fc94 806{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
f2ae14a1 807{"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
df58fc94
RS		 808{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1 },
809{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1 },
810{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1 },
811{"sdbbp", "B", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1 },
812{"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 },
813{"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 },
814{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
815{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
816{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
df58fc94
RS		 817{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1 },
818{"s.d", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 }, /* sdc1 */
819{"s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
820{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
df58fc94
RS		 821{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
822{"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, SM|RD_b, 0, I3 },
df58fc94
RS		 823{"sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3 },
824{"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
df58fc94
RS		 825{"sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3 },
826{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
df58fc94
RS		 827{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
828{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
829{"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
830{"seh", "t,r", 0x00003b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
831{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
832{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
833{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
834{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
835{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
836{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
837{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
838{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
839{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
840{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
2b0c8b40 841{"sh", "mq,mH(ml)", 0xa800, 0xfc00, SM, RD_mq|RD_ml, I1 },
df58fc94
RS		 842{"sh", "t,o(b)", 0x38000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
843{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
844{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
845{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
846{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
847{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
848{"sllv", "d,t,s", 0x00000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2b0c8b40 849{"sll", "md,mc,mM", 0x2400, 0xfc01, 0, WR_md|RD_mc, I1 },
df58fc94
RS		 850{"sll", "d,w,s", 0x00000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, /* sllv */
851{"sll", "t,r,<", 0x00000000, 0xfc0007ff, WR_t|RD_s, 0, I1 },
852{"slt", "d,v,t", 0x00000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
853{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
854{"slti", "t,r,j", 0x90000000, 0xfc000000, WR_t|RD_s, 0, I1 },
855{"sltiu", "t,r,j", 0xb0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
856{"sltu", "d,v,t", 0x00000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
857{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
858{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
859{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
860{"sqrt.d", "T,S", 0x54004a3b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
861{"sqrt.s", "T,S", 0x54000a3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
862{"srav", "d,t,s", 0x00000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
863{"sra", "d,w,s", 0x00000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
864{"sra", "t,r,<", 0x00000080, 0xfc0007ff, WR_t|RD_s, 0, I1 },
865{"srlv", "d,t,s", 0x00000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2b0c8b40 866{"srl", "md,mc,mM", 0x2401, 0xfc01, 0, WR_md|RD_mc, I1 },
df58fc94
RS		 867{"srl", "d,w,s", 0x00000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
868{"srl", "t,r,<", 0x00000040, 0xfc0007ff, WR_t|RD_s, 0, I1 },
869/* ssnop is at the start of the table. */
870{"sub", "d,v,t", 0x00000190, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
871{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
872{"sub.d", "D,V,T", 0x54000170, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
873{"sub.s", "D,V,T", 0x54000070, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
874{"sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2b0c8b40 875{"subu", "md,me,ml", 0x0401, 0xfc01, 0, WR_md|RD_me|RD_ml, I1 },
df58fc94
RS		 876{"subu", "d,v,t", 0x000001d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
877{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
878{"suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
2b0c8b40
MR		 879{"sw", "mq,mJ(ml)", 0xe800, 0xfc00, SM, RD_mq|RD_ml, I1 },
880{"sw", "mp,mU(ms)", 0xc800, 0xfc00, SM, RD_mp|RD_sp, I1 }, /* swsp */
df58fc94
RS		 881{"sw", "t,o(b)", 0xf8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
882{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
883{"swc1", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
884{"swc1", "E,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
885{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
886{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
887{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
df58fc94
RS		 888{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
889{"s.s", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
890{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
891{"swl", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 },
df58fc94
RS		 892{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
893{"scache", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 }, /* same */
df58fc94 894{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
2b0c8b40 895{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, NODS, RD_sp, I1 },
f65c50ad 896{"swm", "n,~(b)", 0x2000d000, 0xfc00f000, SM|RD_b|NODS, 0, I1 },
df58fc94 897{"swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1 },
f65c50ad 898{"swp", "t,~(b)", 0x20009000, 0xfc00f000, SM|RD_t|RD_b|NODS, 0, I1 },
df58fc94
RS		 899{"swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1 },
900{"swr", "t,~(b)", 0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 },
df58fc94
RS		 901{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
902{"invalidate", "t,~(b)",0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 }, /* same */
df58fc94 903{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
83ea18d0 904{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, SM|RD_t|RD_b|FP_S, RD_D, I1 },
f65c50ad
RS		 905{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1 },
906{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, 0, I1 },
907{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, 0, I1 },
908{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, 0, I1 },
909{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, 0, I1 },
910{"sync", "", 0x00006b7c, 0xffffffff, NODS, 0, I1 },
911{"sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1 },
df58fc94
RS		 912{"synci", "o(b)", 0x42000000, 0xffe00000, SM|RD_b, 0, I1 },
913{"syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1 },
914{"syscall", "B", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1 },
915{"teqi", "s,j", 0x41c00000, 0xffe00000, RD_s|TRAP, 0, I1 },
916{"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
917{"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
918{"teq", "s,j", 0x41c00000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* teqi */
919{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I1 },
920{"tgei", "s,j", 0x41200000, 0xffe00000, RD_s|TRAP, 0, I1 },
921{"tge", "s,t", 0x0000023c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
922{"tge", "s,t,|", 0x0000023c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
923{"tge", "s,j", 0x41200000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgei */
924{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I1 },
925{"tgeiu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 },
926{"tgeu", "s,t", 0x0000043c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
927{"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
928{"tgeu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgeiu */
929{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1 },
7f3c4072
CM		 930{"tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB, 0, 0, TLBINV },
931{"tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB, 0, 0, TLBINV },
ba92f7fb
CF		 932{"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
933{"tlbginvf","", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
934{"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
935{"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
936{"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
937{"tlbgwr", "", 0x0000317c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
df58fc94
RS		 938{"tlbp", "", 0x0000037c, 0xffffffff, INSN_TLB, 0, I1 },
939{"tlbr", "", 0x0000137c, 0xffffffff, INSN_TLB, 0, I1 },
940{"tlbwi", "", 0x0000237c, 0xffffffff, INSN_TLB, 0, I1 },
941{"tlbwr", "", 0x0000337c, 0xffffffff, INSN_TLB, 0, I1 },
942{"tlti", "s,j", 0x41000000, 0xffe00000, RD_s|TRAP, 0, I1 },
943{"tlt", "s,t", 0x0000083c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
944{"tlt", "s,t,|", 0x0000083c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
945{"tlt", "s,j", 0x41000000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tlti */
946{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I1 },
947{"tltiu", "s,j", 0x41400000, 0xffe00000, RD_s|TRAP, 0, I1 },
948{"tltu", "s,t", 0x00000a3c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
949{"tltu", "s,t,|", 0x00000a3c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
950{"tltu", "s,j", 0x41400000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tltiu */
951{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I1 },
952{"tnei", "s,j", 0x41800000, 0xffe00000, RD_s|TRAP, 0, I1 },
953{"tne", "s,t", 0x00000c3c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
954{"tne", "s,t,|", 0x00000c3c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
955{"tne", "s,j", 0x41800000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tnei */
956{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I1 },
957{"trunc.l.d", "T,S", 0x5400633b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
958{"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
959{"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
960{"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
f2ae14a1
RS		 961{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3 },
962{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1 },
963{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1 },
964{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1 },
965{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I1 },
966{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1 },
967{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1 },
f65c50ad
RS		 968{"wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1 },
969{"wait", "B", 0x0000937c, 0xfc00ffff, NODS, 0, I1 },
df58fc94
RS		 970{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_s, 0, I1 },
971{"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
2b0c8b40
MR		 972{"xor", "mf,mt,mg", 0x4440, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
973{"xor", "mf,mg,mx", 0x4440, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
df58fc94
RS		 974{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
975{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
976{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
7f3c4072
CM		 977/* microMIPS Enhanced VA Scheme */
978{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 979{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA },
980{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 981{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA },
982{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 983{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA },
984{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 985{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA },
986{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 987{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA },
988{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 989{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA },
990{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 991{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA },
992{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 993{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA },
994{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 995{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA },
996{"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, SM|RD_t|WR_t|RD_b, 0, 0, EVA },
7f3c4072
CM		 997{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA },
998{"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 999{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA },
1000{"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 1001{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA },
1002{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 1003{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA },
1004{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
7f3c4072
CM		 1005{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA },
1006{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_b, 0, 0, EVA },
7f3c4072
CM		 1007{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA },
1008{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_b, 0, 0, EVA },
7f3c4072 1009{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA },
03f66e8a 1010/* MIPS DSP ASE. */
d301a56b
RS		 1011{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1012{"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1013{"addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1014{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1015{"addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1016{"addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1017{"addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1018{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1019{"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1020{"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1021{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, 0, D32 },
1022{"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
1023{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1024{"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
1025{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1026{"cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
1027{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1028{"cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
1029{"cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
1030{"cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
1031{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1032{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1033{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1034{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1035{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1036{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1037{"dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1038{"dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1039{"extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_t|RD_a|DSP_VOLA, 0, 0, D32 },
1040{"extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_t|RD_a|RD_s|DSP_VOLA, 0, 0, D32 },
1041{"extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
1042{"extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
1043{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
1044{"extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
1045{"extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
1046{"extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
1047{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
1048{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
1049{"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
1050{"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
1051{"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1052{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_d|RD_b|RD_t, 0, 0, D32 },
1053{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_d|RD_b|RD_t, 0, 0, D32 },
1054{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_d|RD_b|RD_t, 0, 0, D32 },
1055{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1056{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1057{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1058{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1059{"modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1060{"mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_s|MOD_a|DSP_VOLA, 0, 0, D32 },
1061{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
1062{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
1063{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
1064{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
1065{"mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
1066{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
1067{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1068{"pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1069{"pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1070{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1071{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1072{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1073{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1074{"preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1075{"preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1076{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1077{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1078{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1079{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1080{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1081{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1082{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1083{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1084{"raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1085{"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_t, 0, 0, D32 },
1086{"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_t, 0, 0, D32 },
1087{"repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_d, 0, 0, D32 },
1088{"repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_t, 0, 0, D32 },
1089{"replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1090{"replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
1091{"shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a, 0, 0, D32 },
1092{"shilov", "7,s", 0x0000127c, 0xffe03fff, MOD_a|RD_s, 0, 0, D32 },
1093{"shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
1094{"shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_t|RD_s, 0, 0, D32 },
1095{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
1096{"shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_t|RD_s, 0, 0, D32 },
1097{"shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1098{"shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1099{"shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1100{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1101{"shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
1102{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
1103{"shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_t|RD_s, 0, 0, D32 },
1104{"shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1105{"shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1106{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1107{"shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_t|RD_s, 0, 0, D32 },
1108{"shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1109{"subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1110{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1111{"subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1112{"subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1113{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
1114{"wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_t|DSP_VOLA, 0, 0, D32 },
1115{"wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_t|DSP_VOLA, 0, 0, D32 },
03f66e8a 1116/* MIPS DSP ASE Rev2. */
d301a56b
RS		 1117{"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_t|RD_s, 0, 0, D33 },
1118{"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1119{"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1120{"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1121{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1122{"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1123{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1124{"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1125{"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1126{"append", "t,s,h", 0x00000215, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
1127{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33 },
1128{"balign", "t,s,2", 0x000008bc, 0xfc003fff, WR_t|RD_t|RD_s, 0, 0, D33 },
1129{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1130{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1131{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1132{"dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1133{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1134{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1135{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1136{"dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1137{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1138{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1139{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1140{"mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
1141{"mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
1142{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
1143{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
1144{"mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
1145{"mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
1146{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1147{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
1148{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
1149{"prepend", "t,s,h", 0x00000255, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
1150{"shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_t|RD_s, 0, 0, D33 },
1151{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t|RD_s, 0, 0, D33 },
1152{"shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1153{"shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1154{"shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_t|RD_s, 0, 0, D33 },
1155{"shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1156{"subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1157{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1158{"subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1159{"subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1160{"subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1161{"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1162{"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
1163{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
df58fc94
RS		 1164};
1165
1166const int bfd_micromips_num_opcodes =
1167 ((sizeof micromips_opcodes) / (sizeof (micromips_opcodes[0])));
GDB Binutils - Deliverables
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