Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print mips instructions for GDB, the GNU debugger, or for objdump. |
060d22b0 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
82f6ea4a | 3 | 2000, 2001, 2002 |
73da6b6b | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). |
6 | ||
7 | This file is part of GDB, GAS, and the GNU binutils. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
22 | ||
252b5132 RH |
23 | #include "sysdep.h" |
24 | #include "dis-asm.h" | |
25 | #include "opcode/mips.h" | |
26 | #include "opintl.h" | |
27 | ||
28 | /* FIXME: These are needed to figure out if the code is mips16 or | |
29 | not. The low bit of the address is often a good indicator. No | |
30 | symbol table is available when this code runs out in an embedded | |
7f6621cd | 31 | system as when it is used for disassembler support in a monitor. */ |
252b5132 RH |
32 | |
33 | #if !defined(EMBEDDED_ENV) | |
34 | #define SYMTAB_AVAILABLE 1 | |
35 | #include "elf-bfd.h" | |
36 | #include "elf/mips.h" | |
37 | #endif | |
38 | ||
aa5f19f2 NC |
39 | /* Mips instructions are at maximum this many bytes long. */ |
40 | #define INSNLEN 4 | |
41 | ||
42 | static int _print_insn_mips | |
43 | PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian)); | |
44 | static int print_insn_mips | |
45 | PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *)); | |
46 | static void print_insn_arg | |
47 | PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *)); | |
7fa108a4 AJ |
48 | static void mips_isa_type |
49 | PARAMS ((int, int *, int *)); | |
aa5f19f2 NC |
50 | static int print_insn_mips16 |
51 | PARAMS ((bfd_vma, struct disassemble_info *)); | |
7fa108a4 AJ |
52 | static int is_newabi |
53 | PARAMS ((Elf_Internal_Ehdr *)); | |
252b5132 RH |
54 | static void print_mips16_insn_arg |
55 | PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma, | |
56 | struct disassemble_info *)); | |
252b5132 | 57 | \f |
aa5f19f2 | 58 | /* FIXME: These should be shared with gdb somehow. */ |
252b5132 RH |
59 | |
60 | /* The mips16 register names. */ | |
7f6621cd | 61 | static const char * const mips16_reg_names[] = { |
252b5132 RH |
62 | "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" |
63 | }; | |
fb48caed | 64 | |
7f6621cd | 65 | static const char * const mips32_reg_names[] = { |
aa5f19f2 NC |
66 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
67 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
68 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
69 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
70 | "sr", "lo", "hi", "bad", "cause", "pc", | |
71 | "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7", | |
72 | "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15", | |
73 | "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23", | |
74 | "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31", | |
75 | "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi", | |
76 | "epc", "prid" | |
77 | }; | |
78 | ||
7f6621cd | 79 | static const char * const mips64_reg_names[] = { |
aa5f19f2 NC |
80 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
81 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
82 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
83 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
84 | "sr", "lo", "hi", "bad", "cause", "pc", | |
85 | "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3", | |
86 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
87 | "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", | |
88 | "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", | |
89 | "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi", | |
90 | "epc", "prid" | |
91 | }; | |
92 | ||
93 | /* Scalar register names. _print_insn_mips() decides which register name | |
fb48caed | 94 | table to use. */ |
aa5f19f2 | 95 | static const char * const *reg_names = NULL; |
252b5132 | 96 | \f |
7f6621cd | 97 | /* Print insn arguments for 32/64-bit code. */ |
aa5f19f2 | 98 | |
252b5132 RH |
99 | static void |
100 | print_insn_arg (d, l, pc, info) | |
101 | const char *d; | |
102 | register unsigned long int l; | |
103 | bfd_vma pc; | |
104 | struct disassemble_info *info; | |
105 | { | |
106 | int delta; | |
107 | ||
108 | switch (*d) | |
109 | { | |
110 | case ',': | |
111 | case '(': | |
112 | case ')': | |
9752cf1b RS |
113 | case '[': |
114 | case ']': | |
252b5132 RH |
115 | (*info->fprintf_func) (info->stream, "%c", *d); |
116 | break; | |
117 | ||
118 | case 's': | |
119 | case 'b': | |
120 | case 'r': | |
121 | case 'v': | |
aa5f19f2 | 122 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
123 | reg_names[(l >> OP_SH_RS) & OP_MASK_RS]); |
124 | break; | |
125 | ||
126 | case 't': | |
127 | case 'w': | |
aa5f19f2 | 128 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
129 | reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
130 | break; | |
131 | ||
132 | case 'i': | |
133 | case 'u': | |
134 | (*info->fprintf_func) (info->stream, "0x%x", | |
7f6621cd | 135 | (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); |
252b5132 RH |
136 | break; |
137 | ||
7f6621cd | 138 | case 'j': /* Same as i, but sign-extended. */ |
252b5132 RH |
139 | case 'o': |
140 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; | |
141 | if (delta & 0x8000) | |
142 | delta |= ~0xffff; | |
143 | (*info->fprintf_func) (info->stream, "%d", | |
144 | delta); | |
145 | break; | |
146 | ||
147 | case 'h': | |
148 | (*info->fprintf_func) (info->stream, "0x%x", | |
149 | (unsigned int) ((l >> OP_SH_PREFX) | |
150 | & OP_MASK_PREFX)); | |
151 | break; | |
152 | ||
153 | case 'k': | |
154 | (*info->fprintf_func) (info->stream, "0x%x", | |
155 | (unsigned int) ((l >> OP_SH_CACHE) | |
156 | & OP_MASK_CACHE)); | |
157 | break; | |
158 | ||
159 | case 'a': | |
9bb28706 CD |
160 | info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) |
161 | | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); | |
162 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
163 | break; |
164 | ||
165 | case 'p': | |
7f6621cd | 166 | /* Sign extend the displacement. */ |
252b5132 RH |
167 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; |
168 | if (delta & 0x8000) | |
169 | delta |= ~0xffff; | |
9bb28706 CD |
170 | info->target = (delta << 2) + pc + INSNLEN; |
171 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
172 | break; |
173 | ||
174 | case 'd': | |
aa5f19f2 | 175 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
176 | reg_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
177 | break; | |
178 | ||
4372b673 NC |
179 | case 'U': |
180 | { | |
7f6621cd KH |
181 | /* First check for both rd and rt being equal. */ |
182 | unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; | |
183 | if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) | |
184 | (*info->fprintf_func) (info->stream, "%s", | |
185 | reg_names[reg]); | |
186 | else | |
187 | { | |
188 | /* If one is zero use the other. */ | |
189 | if (reg == 0) | |
190 | (*info->fprintf_func) (info->stream, "%s", | |
191 | reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
192 | else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) | |
193 | (*info->fprintf_func) (info->stream, "%s", | |
194 | reg_names[reg]); | |
195 | else /* Bogus, result depends on processor. */ | |
196 | (*info->fprintf_func) (info->stream, "%s or %s", | |
197 | reg_names[reg], | |
198 | reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
199 | } | |
4372b673 NC |
200 | } |
201 | break; | |
202 | ||
252b5132 | 203 | case 'z': |
aa5f19f2 | 204 | (*info->fprintf_func) (info->stream, "%s", reg_names[0]); |
252b5132 RH |
205 | break; |
206 | ||
207 | case '<': | |
208 | (*info->fprintf_func) (info->stream, "0x%x", | |
209 | (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); | |
210 | break; | |
211 | ||
212 | case 'c': | |
213 | (*info->fprintf_func) (info->stream, "0x%x", | |
214 | (l >> OP_SH_CODE) & OP_MASK_CODE); | |
215 | break; | |
216 | ||
252b5132 RH |
217 | case 'q': |
218 | (*info->fprintf_func) (info->stream, "0x%x", | |
219 | (l >> OP_SH_CODE2) & OP_MASK_CODE2); | |
220 | break; | |
221 | ||
222 | case 'C': | |
223 | (*info->fprintf_func) (info->stream, "0x%x", | |
224 | (l >> OP_SH_COPZ) & OP_MASK_COPZ); | |
225 | break; | |
226 | ||
227 | case 'B': | |
228 | (*info->fprintf_func) (info->stream, "0x%x", | |
4372b673 NC |
229 | (l >> OP_SH_CODE20) & OP_MASK_CODE20); |
230 | break; | |
231 | ||
232 | case 'J': | |
233 | (*info->fprintf_func) (info->stream, "0x%x", | |
234 | (l >> OP_SH_CODE19) & OP_MASK_CODE19); | |
252b5132 RH |
235 | break; |
236 | ||
237 | case 'S': | |
238 | case 'V': | |
239 | (*info->fprintf_func) (info->stream, "$f%d", | |
240 | (l >> OP_SH_FS) & OP_MASK_FS); | |
241 | break; | |
242 | ||
252b5132 RH |
243 | case 'T': |
244 | case 'W': | |
245 | (*info->fprintf_func) (info->stream, "$f%d", | |
246 | (l >> OP_SH_FT) & OP_MASK_FT); | |
247 | break; | |
248 | ||
249 | case 'D': | |
250 | (*info->fprintf_func) (info->stream, "$f%d", | |
251 | (l >> OP_SH_FD) & OP_MASK_FD); | |
252 | break; | |
253 | ||
254 | case 'R': | |
255 | (*info->fprintf_func) (info->stream, "$f%d", | |
256 | (l >> OP_SH_FR) & OP_MASK_FR); | |
257 | break; | |
258 | ||
259 | case 'E': | |
21d34b1c TS |
260 | (*info->fprintf_func) (info->stream, "$%d", |
261 | (l >> OP_SH_RT) & OP_MASK_RT); | |
252b5132 RH |
262 | break; |
263 | ||
264 | case 'G': | |
21d34b1c TS |
265 | (*info->fprintf_func) (info->stream, "$%d", |
266 | (l >> OP_SH_RD) & OP_MASK_RD); | |
252b5132 RH |
267 | break; |
268 | ||
269 | case 'N': | |
270 | (*info->fprintf_func) (info->stream, "$fcc%d", | |
271 | (l >> OP_SH_BCC) & OP_MASK_BCC); | |
272 | break; | |
273 | ||
274 | case 'M': | |
275 | (*info->fprintf_func) (info->stream, "$fcc%d", | |
276 | (l >> OP_SH_CCC) & OP_MASK_CCC); | |
277 | break; | |
278 | ||
279 | case 'P': | |
280 | (*info->fprintf_func) (info->stream, "%d", | |
281 | (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); | |
282 | break; | |
283 | ||
9752cf1b RS |
284 | case 'e': |
285 | (*info->fprintf_func) (info->stream, "%d", | |
286 | (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); | |
287 | break; | |
288 | ||
289 | case '%': | |
290 | (*info->fprintf_func) (info->stream, "%d", | |
291 | (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); | |
292 | break; | |
293 | ||
156c2f8b | 294 | case 'H': |
e93d7199 | 295 | (*info->fprintf_func) (info->stream, "%d", |
156c2f8b NC |
296 | (l >> OP_SH_SEL) & OP_MASK_SEL); |
297 | break; | |
252b5132 | 298 | |
deec1734 CD |
299 | case 'O': |
300 | (*info->fprintf_func) (info->stream, "%d", | |
301 | (l >> OP_SH_ALN) & OP_MASK_ALN); | |
302 | break; | |
303 | ||
304 | case 'Q': | |
305 | { | |
306 | unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; | |
307 | if ((vsel & 0x10) == 0) | |
308 | { | |
309 | int fmt; | |
310 | vsel &= 0x0f; | |
311 | for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) | |
312 | if ((vsel & 1) == 0) | |
313 | break; | |
314 | (*info->fprintf_func) (info->stream, "$v%d[%d]", | |
315 | (l >> OP_SH_FT) & OP_MASK_FT, | |
316 | vsel >> 1); | |
317 | } | |
318 | else if ((vsel & 0x08) == 0) | |
319 | { | |
320 | (*info->fprintf_func) (info->stream, "$v%d", | |
321 | (l >> OP_SH_FT) & OP_MASK_FT); | |
322 | } | |
323 | else | |
324 | { | |
325 | (*info->fprintf_func) (info->stream, "0x%x", | |
326 | (l >> OP_SH_FT) & OP_MASK_FT); | |
327 | } | |
328 | } | |
329 | break; | |
330 | ||
331 | case 'X': | |
332 | (*info->fprintf_func) (info->stream, "$v%d", | |
333 | (l >> OP_SH_FD) & OP_MASK_FD); | |
334 | break; | |
335 | ||
336 | case 'Y': | |
337 | (*info->fprintf_func) (info->stream, "$v%d", | |
338 | (l >> OP_SH_FS) & OP_MASK_FS); | |
339 | break; | |
340 | ||
341 | case 'Z': | |
342 | (*info->fprintf_func) (info->stream, "$v%d", | |
343 | (l >> OP_SH_FT) & OP_MASK_FT); | |
344 | break; | |
345 | ||
252b5132 RH |
346 | default: |
347 | /* xgettext:c-format */ | |
348 | (*info->fprintf_func) (info->stream, | |
349 | _("# internal error, undefined modifier(%c)"), | |
350 | *d); | |
351 | break; | |
352 | } | |
353 | } | |
354 | \f | |
7f6621cd | 355 | /* Figure out the MIPS ISA and CPU based on the machine number. */ |
252b5132 RH |
356 | |
357 | static void | |
aa5f19f2 | 358 | mips_isa_type (mach, isa, cputype) |
252b5132 RH |
359 | int mach; |
360 | int *isa; | |
361 | int *cputype; | |
362 | { | |
252b5132 RH |
363 | switch (mach) |
364 | { | |
156c2f8b | 365 | case bfd_mach_mips3000: |
aa5f19f2 NC |
366 | *cputype = CPU_R3000; |
367 | *isa = ISA_MIPS1; | |
156c2f8b NC |
368 | break; |
369 | case bfd_mach_mips3900: | |
aa5f19f2 NC |
370 | *cputype = CPU_R3900; |
371 | *isa = ISA_MIPS1; | |
156c2f8b NC |
372 | break; |
373 | case bfd_mach_mips4000: | |
aa5f19f2 NC |
374 | *cputype = CPU_R4000; |
375 | *isa = ISA_MIPS3; | |
156c2f8b NC |
376 | break; |
377 | case bfd_mach_mips4010: | |
aa5f19f2 NC |
378 | *cputype = CPU_R4010; |
379 | *isa = ISA_MIPS2; | |
156c2f8b NC |
380 | break; |
381 | case bfd_mach_mips4100: | |
aa5f19f2 NC |
382 | *cputype = CPU_VR4100; |
383 | *isa = ISA_MIPS3; | |
156c2f8b NC |
384 | break; |
385 | case bfd_mach_mips4111: | |
aa5f19f2 NC |
386 | *cputype = CPU_R4111; |
387 | *isa = ISA_MIPS3; | |
156c2f8b | 388 | break; |
9752cf1b RS |
389 | case bfd_mach_mips4120: |
390 | *cputype = CPU_VR4120; | |
391 | *isa = ISA_MIPS3; | |
392 | break; | |
156c2f8b | 393 | case bfd_mach_mips4300: |
aa5f19f2 NC |
394 | *cputype = CPU_R4300; |
395 | *isa = ISA_MIPS3; | |
156c2f8b NC |
396 | break; |
397 | case bfd_mach_mips4400: | |
aa5f19f2 NC |
398 | *cputype = CPU_R4400; |
399 | *isa = ISA_MIPS3; | |
156c2f8b NC |
400 | break; |
401 | case bfd_mach_mips4600: | |
aa5f19f2 NC |
402 | *cputype = CPU_R4600; |
403 | *isa = ISA_MIPS3; | |
156c2f8b NC |
404 | break; |
405 | case bfd_mach_mips4650: | |
aa5f19f2 NC |
406 | *cputype = CPU_R4650; |
407 | *isa = ISA_MIPS3; | |
156c2f8b NC |
408 | break; |
409 | case bfd_mach_mips5000: | |
aa5f19f2 NC |
410 | *cputype = CPU_R5000; |
411 | *isa = ISA_MIPS4; | |
156c2f8b | 412 | break; |
9752cf1b RS |
413 | case bfd_mach_mips5400: |
414 | *cputype = CPU_VR5400; | |
415 | *isa = ISA_MIPS4; | |
416 | break; | |
417 | case bfd_mach_mips5500: | |
418 | *cputype = CPU_VR5500; | |
419 | *isa = ISA_MIPS4; | |
420 | break; | |
156c2f8b | 421 | case bfd_mach_mips6000: |
aa5f19f2 NC |
422 | *cputype = CPU_R6000; |
423 | *isa = ISA_MIPS2; | |
156c2f8b NC |
424 | break; |
425 | case bfd_mach_mips8000: | |
aa5f19f2 NC |
426 | *cputype = CPU_R8000; |
427 | *isa = ISA_MIPS4; | |
156c2f8b NC |
428 | break; |
429 | case bfd_mach_mips10000: | |
aa5f19f2 NC |
430 | *cputype = CPU_R10000; |
431 | *isa = ISA_MIPS4; | |
156c2f8b | 432 | break; |
d1cf510e NC |
433 | case bfd_mach_mips12000: |
434 | *cputype = CPU_R12000; | |
435 | *isa = ISA_MIPS4; | |
436 | break; | |
156c2f8b | 437 | case bfd_mach_mips16: |
aa5f19f2 | 438 | *cputype = CPU_MIPS16; |
aec421e0 | 439 | *isa = ISA_MIPS3 | INSN_MIPS16; |
e7af610e | 440 | break; |
84ea6cf2 | 441 | case bfd_mach_mips5: |
aa5f19f2 NC |
442 | *cputype = CPU_MIPS5; |
443 | *isa = ISA_MIPS5; | |
84ea6cf2 | 444 | break; |
c6c98b38 | 445 | case bfd_mach_mips_sb1: |
aa5f19f2 | 446 | *cputype = CPU_SB1; |
1f25f5d3 | 447 | *isa = ISA_MIPS64 | INSN_MIPS3D | INSN_SB1; |
c6c98b38 | 448 | break; |
0823fbca | 449 | case bfd_mach_mipsisa32: |
eb7b56d0 | 450 | *cputype = CPU_MIPS32; |
1f25f5d3 | 451 | /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. |
deec1734 CD |
452 | Note that MIPS-3D and MDMX are not applicable to MIPS32. (See |
453 | _MIPS32 Architecture For Programmers Volume I: Introduction to the | |
1f25f5d3 CD |
454 | MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), |
455 | page 1. */ | |
aec421e0 | 456 | *isa = ISA_MIPS32 | INSN_MIPS16; |
0823fbca EC |
457 | break; |
458 | case bfd_mach_mipsisa64: | |
eb7b56d0 | 459 | *cputype = CPU_MIPS64; |
1f25f5d3 | 460 | /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ |
aec421e0 | 461 | *isa = ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX; |
0823fbca EC |
462 | break; |
463 | ||
156c2f8b | 464 | default: |
aa5f19f2 NC |
465 | *cputype = CPU_R3000; |
466 | *isa = ISA_MIPS3; | |
156c2f8b | 467 | break; |
252b5132 | 468 | } |
252b5132 RH |
469 | } |
470 | ||
21d34b1c | 471 | /* Check if the object uses NewABI conventions. */ |
aa5f19f2 NC |
472 | |
473 | static int | |
7f6621cd | 474 | is_newabi (header) |
21d34b1c | 475 | Elf_Internal_Ehdr *header; |
aa5f19f2 | 476 | { |
4c563ebf CD |
477 | /* There are no old-style ABIs which use 64-bit ELF. */ |
478 | if (header->e_ident[EI_CLASS] == ELFCLASS64) | |
479 | return 1; | |
480 | ||
563773fe TS |
481 | /* If a 32-bit ELF file, n32 is a new-style ABI. */ |
482 | if ((header->e_flags & EF_MIPS_ABI2) != 0) | |
21d34b1c | 483 | return 1; |
252b5132 | 484 | |
21d34b1c | 485 | return 0; |
aa5f19f2 NC |
486 | } |
487 | \f | |
252b5132 RH |
488 | /* Print the mips instruction at address MEMADDR in debugged memory, |
489 | on using INFO. Returns length of the instruction, in bytes, which is | |
aa5f19f2 | 490 | always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if |
252b5132 RH |
491 | this is little-endian code. */ |
492 | ||
493 | static int | |
aa5f19f2 | 494 | print_insn_mips (memaddr, word, info) |
252b5132 RH |
495 | bfd_vma memaddr; |
496 | unsigned long int word; | |
497 | struct disassemble_info *info; | |
498 | { | |
499 | register const struct mips_opcode *op; | |
500 | int target_processor, mips_isa; | |
501 | static boolean init = 0; | |
502 | static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; | |
503 | ||
504 | /* Build a hash table to shorten the search time. */ | |
505 | if (! init) | |
506 | { | |
507 | unsigned int i; | |
508 | ||
509 | for (i = 0; i <= OP_MASK_OP; i++) | |
510 | { | |
511 | for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) | |
512 | { | |
513 | if (op->pinfo == INSN_MACRO) | |
514 | continue; | |
515 | if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) | |
516 | { | |
517 | mips_hash[i] = op; | |
518 | break; | |
519 | } | |
520 | } | |
7f6621cd | 521 | } |
252b5132 RH |
522 | |
523 | init = 1; | |
524 | } | |
525 | ||
526 | #if ! SYMTAB_AVAILABLE | |
527 | /* This is running out on a target machine, not in a host tool. | |
528 | FIXME: Where does mips_target_info come from? */ | |
529 | target_processor = mips_target_info.processor; | |
530 | mips_isa = mips_target_info.isa; | |
e93d7199 | 531 | #else |
aa5f19f2 | 532 | mips_isa_type (info->mach, &mips_isa, &target_processor); |
e93d7199 | 533 | #endif |
252b5132 | 534 | |
aa5f19f2 | 535 | info->bytes_per_chunk = INSNLEN; |
252b5132 | 536 | info->display_endian = info->endian; |
9bb28706 CD |
537 | info->insn_info_valid = 1; |
538 | info->branch_delay_insns = 0; | |
def7143b | 539 | info->data_size = 0; |
9bb28706 CD |
540 | info->insn_type = dis_nonbranch; |
541 | info->target = 0; | |
542 | info->target2 = 0; | |
252b5132 RH |
543 | |
544 | op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; | |
545 | if (op != NULL) | |
546 | { | |
547 | for (; op < &mips_opcodes[NUMOPCODES]; op++) | |
548 | { | |
549 | if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) | |
550 | { | |
551 | register const char *d; | |
2bd7f1f3 | 552 | |
3396de36 TS |
553 | /* We always allow to disassemble the jalx instruction. */ |
554 | if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor) | |
555 | && strcmp (op->name, "jalx")) | |
252b5132 RH |
556 | continue; |
557 | ||
9bb28706 CD |
558 | /* Figure out instruction type and branch delay information. */ |
559 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
560 | { | |
561 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
562 | info->insn_type = dis_jsr; | |
563 | else | |
564 | info->insn_type = dis_branch; | |
565 | info->branch_delay_insns = 1; | |
566 | } | |
567 | else if ((op->pinfo & (INSN_COND_BRANCH_DELAY | |
568 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
569 | { | |
570 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
571 | info->insn_type = dis_condjsr; | |
572 | else | |
573 | info->insn_type = dis_condbranch; | |
574 | info->branch_delay_insns = 1; | |
575 | } | |
576 | else if ((op->pinfo & (INSN_STORE_MEMORY | |
577 | | INSN_LOAD_MEMORY_DELAY)) != 0) | |
578 | info->insn_type = dis_dref; | |
579 | ||
252b5132 RH |
580 | (*info->fprintf_func) (info->stream, "%s", op->name); |
581 | ||
582 | d = op->args; | |
583 | if (d != NULL && *d != '\0') | |
584 | { | |
7f6621cd | 585 | (*info->fprintf_func) (info->stream, "\t"); |
252b5132 | 586 | for (; *d != '\0'; d++) |
7f6621cd | 587 | print_insn_arg (d, word, memaddr, info); |
252b5132 RH |
588 | } |
589 | ||
aa5f19f2 | 590 | return INSNLEN; |
252b5132 RH |
591 | } |
592 | } | |
593 | } | |
594 | ||
595 | /* Handle undefined instructions. */ | |
9bb28706 | 596 | info->insn_type = dis_noninsn; |
252b5132 | 597 | (*info->fprintf_func) (info->stream, "0x%x", word); |
aa5f19f2 | 598 | return INSNLEN; |
252b5132 | 599 | } |
aa5f19f2 | 600 | \f |
252b5132 RH |
601 | /* In an environment where we do not know the symbol type of the |
602 | instruction we are forced to assume that the low order bit of the | |
603 | instructions' address may mark it as a mips16 instruction. If we | |
604 | are single stepping, or the pc is within the disassembled function, | |
605 | this works. Otherwise, we need a clue. Sometimes. */ | |
606 | ||
aa5f19f2 NC |
607 | static int |
608 | _print_insn_mips (memaddr, info, endianness) | |
252b5132 RH |
609 | bfd_vma memaddr; |
610 | struct disassemble_info *info; | |
aa5f19f2 | 611 | enum bfd_endian endianness; |
252b5132 | 612 | { |
aa5f19f2 | 613 | bfd_byte buffer[INSNLEN]; |
252b5132 RH |
614 | int status; |
615 | ||
616 | #if 1 | |
617 | /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ | |
618 | /* Only a few tools will work this way. */ | |
619 | if (memaddr & 0x01) | |
620 | return print_insn_mips16 (memaddr, info); | |
e93d7199 | 621 | #endif |
252b5132 RH |
622 | |
623 | #if SYMTAB_AVAILABLE | |
53f32ea5 | 624 | if (info->mach == bfd_mach_mips16 |
252b5132 RH |
625 | || (info->flavour == bfd_target_elf_flavour |
626 | && info->symbols != NULL | |
627 | && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other | |
628 | == STO_MIPS16))) | |
629 | return print_insn_mips16 (memaddr, info); | |
e93d7199 | 630 | #endif |
252b5132 | 631 | |
aa5f19f2 | 632 | /* Use mips64_reg_names for new ABI. */ |
21d34b1c TS |
633 | reg_names = mips32_reg_names; |
634 | ||
635 | if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL) | |
636 | { | |
637 | Elf_Internal_Ehdr *header; | |
638 | ||
7f6621cd KH |
639 | header = elf_elfheader (bfd_asymbol_bfd (*(info->symbols))); |
640 | if (is_newabi (header)) | |
21d34b1c TS |
641 | reg_names = mips64_reg_names; |
642 | } | |
aa5f19f2 NC |
643 | |
644 | status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); | |
252b5132 | 645 | if (status == 0) |
aa5f19f2 NC |
646 | { |
647 | unsigned long insn; | |
648 | ||
649 | if (endianness == BFD_ENDIAN_BIG) | |
7f6621cd | 650 | insn = (unsigned long) bfd_getb32 (buffer); |
aa5f19f2 NC |
651 | else |
652 | insn = (unsigned long) bfd_getl32 (buffer); | |
653 | ||
654 | return print_insn_mips (memaddr, insn, info); | |
655 | } | |
252b5132 RH |
656 | else |
657 | { | |
658 | (*info->memory_error_func) (status, memaddr, info); | |
659 | return -1; | |
660 | } | |
661 | } | |
662 | ||
663 | int | |
aa5f19f2 | 664 | print_insn_big_mips (memaddr, info) |
252b5132 RH |
665 | bfd_vma memaddr; |
666 | struct disassemble_info *info; | |
667 | { | |
aa5f19f2 NC |
668 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); |
669 | } | |
252b5132 | 670 | |
aa5f19f2 NC |
671 | int |
672 | print_insn_little_mips (memaddr, info) | |
673 | bfd_vma memaddr; | |
674 | struct disassemble_info *info; | |
675 | { | |
676 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); | |
252b5132 RH |
677 | } |
678 | \f | |
679 | /* Disassemble mips16 instructions. */ | |
680 | ||
681 | static int | |
682 | print_insn_mips16 (memaddr, info) | |
683 | bfd_vma memaddr; | |
684 | struct disassemble_info *info; | |
685 | { | |
686 | int status; | |
687 | bfd_byte buffer[2]; | |
688 | int length; | |
689 | int insn; | |
690 | boolean use_extend; | |
691 | int extend = 0; | |
692 | const struct mips_opcode *op, *opend; | |
693 | ||
694 | info->bytes_per_chunk = 2; | |
695 | info->display_endian = info->endian; | |
252b5132 RH |
696 | info->insn_info_valid = 1; |
697 | info->branch_delay_insns = 0; | |
698 | info->data_size = 0; | |
699 | info->insn_type = dis_nonbranch; | |
700 | info->target = 0; | |
701 | info->target2 = 0; | |
702 | ||
703 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
704 | if (status != 0) | |
705 | { | |
706 | (*info->memory_error_func) (status, memaddr, info); | |
707 | return -1; | |
708 | } | |
709 | ||
710 | length = 2; | |
711 | ||
712 | if (info->endian == BFD_ENDIAN_BIG) | |
713 | insn = bfd_getb16 (buffer); | |
714 | else | |
715 | insn = bfd_getl16 (buffer); | |
716 | ||
717 | /* Handle the extend opcode specially. */ | |
718 | use_extend = false; | |
719 | if ((insn & 0xf800) == 0xf000) | |
720 | { | |
721 | use_extend = true; | |
722 | extend = insn & 0x7ff; | |
723 | ||
724 | memaddr += 2; | |
725 | ||
726 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
727 | if (status != 0) | |
728 | { | |
729 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
730 | (unsigned int) extend); | |
731 | (*info->memory_error_func) (status, memaddr, info); | |
732 | return -1; | |
733 | } | |
734 | ||
735 | if (info->endian == BFD_ENDIAN_BIG) | |
736 | insn = bfd_getb16 (buffer); | |
737 | else | |
738 | insn = bfd_getl16 (buffer); | |
739 | ||
740 | /* Check for an extend opcode followed by an extend opcode. */ | |
741 | if ((insn & 0xf800) == 0xf000) | |
742 | { | |
743 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
744 | (unsigned int) extend); | |
745 | info->insn_type = dis_noninsn; | |
746 | return length; | |
747 | } | |
748 | ||
749 | length += 2; | |
750 | } | |
751 | ||
752 | /* FIXME: Should probably use a hash table on the major opcode here. */ | |
753 | ||
754 | opend = mips16_opcodes + bfd_mips16_num_opcodes; | |
755 | for (op = mips16_opcodes; op < opend; op++) | |
756 | { | |
757 | if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match) | |
758 | { | |
759 | const char *s; | |
760 | ||
761 | if (strchr (op->args, 'a') != NULL) | |
762 | { | |
763 | if (use_extend) | |
764 | { | |
765 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
766 | (unsigned int) extend); | |
767 | info->insn_type = dis_noninsn; | |
768 | return length - 2; | |
769 | } | |
770 | ||
771 | use_extend = false; | |
772 | ||
773 | memaddr += 2; | |
774 | ||
775 | status = (*info->read_memory_func) (memaddr, buffer, 2, | |
776 | info); | |
777 | if (status == 0) | |
778 | { | |
779 | use_extend = true; | |
780 | if (info->endian == BFD_ENDIAN_BIG) | |
781 | extend = bfd_getb16 (buffer); | |
782 | else | |
783 | extend = bfd_getl16 (buffer); | |
784 | length += 2; | |
785 | } | |
786 | } | |
787 | ||
788 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
789 | if (op->args[0] != '\0') | |
790 | (*info->fprintf_func) (info->stream, "\t"); | |
791 | ||
792 | for (s = op->args; *s != '\0'; s++) | |
793 | { | |
794 | if (*s == ',' | |
795 | && s[1] == 'w' | |
796 | && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) | |
797 | == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) | |
798 | { | |
799 | /* Skip the register and the comma. */ | |
800 | ++s; | |
801 | continue; | |
802 | } | |
803 | if (*s == ',' | |
804 | && s[1] == 'v' | |
805 | && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) | |
806 | == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) | |
807 | { | |
808 | /* Skip the register and the comma. */ | |
809 | ++s; | |
810 | continue; | |
811 | } | |
812 | print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, | |
813 | info); | |
814 | } | |
815 | ||
816 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
817 | { | |
818 | info->branch_delay_insns = 1; | |
819 | if (info->insn_type != dis_jsr) | |
820 | info->insn_type = dis_branch; | |
821 | } | |
822 | ||
823 | return length; | |
824 | } | |
825 | } | |
826 | ||
827 | if (use_extend) | |
828 | (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); | |
829 | (*info->fprintf_func) (info->stream, "0x%x", insn); | |
830 | info->insn_type = dis_noninsn; | |
831 | ||
832 | return length; | |
833 | } | |
834 | ||
835 | /* Disassemble an operand for a mips16 instruction. */ | |
836 | ||
837 | static void | |
838 | print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) | |
aa5f19f2 | 839 | char type; |
252b5132 RH |
840 | const struct mips_opcode *op; |
841 | int l; | |
842 | boolean use_extend; | |
843 | int extend; | |
844 | bfd_vma memaddr; | |
845 | struct disassemble_info *info; | |
846 | { | |
847 | switch (type) | |
848 | { | |
849 | case ',': | |
850 | case '(': | |
851 | case ')': | |
852 | (*info->fprintf_func) (info->stream, "%c", type); | |
853 | break; | |
854 | ||
855 | case 'y': | |
856 | case 'w': | |
aa5f19f2 | 857 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
858 | mips16_reg_names[((l >> MIPS16OP_SH_RY) |
859 | & MIPS16OP_MASK_RY)]); | |
860 | break; | |
861 | ||
862 | case 'x': | |
863 | case 'v': | |
aa5f19f2 | 864 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
865 | mips16_reg_names[((l >> MIPS16OP_SH_RX) |
866 | & MIPS16OP_MASK_RX)]); | |
867 | break; | |
868 | ||
869 | case 'z': | |
aa5f19f2 | 870 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
871 | mips16_reg_names[((l >> MIPS16OP_SH_RZ) |
872 | & MIPS16OP_MASK_RZ)]); | |
873 | break; | |
874 | ||
875 | case 'Z': | |
aa5f19f2 | 876 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
877 | mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) |
878 | & MIPS16OP_MASK_MOVE32Z)]); | |
879 | break; | |
880 | ||
881 | case '0': | |
aa5f19f2 | 882 | (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[0]); |
252b5132 RH |
883 | break; |
884 | ||
885 | case 'S': | |
aa5f19f2 | 886 | (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[29]); |
252b5132 RH |
887 | break; |
888 | ||
889 | case 'P': | |
890 | (*info->fprintf_func) (info->stream, "$pc"); | |
891 | break; | |
892 | ||
893 | case 'R': | |
aa5f19f2 | 894 | (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[31]); |
252b5132 RH |
895 | break; |
896 | ||
897 | case 'X': | |
aa5f19f2 NC |
898 | (*info->fprintf_func) (info->stream, "%s", |
899 | mips32_reg_names[((l >> MIPS16OP_SH_REGR32) | |
7f6621cd | 900 | & MIPS16OP_MASK_REGR32)]); |
252b5132 RH |
901 | break; |
902 | ||
903 | case 'Y': | |
aa5f19f2 NC |
904 | (*info->fprintf_func) (info->stream, "%s", |
905 | mips32_reg_names[MIPS16OP_EXTRACT_REG32R (l)]); | |
252b5132 RH |
906 | break; |
907 | ||
908 | case '<': | |
909 | case '>': | |
910 | case '[': | |
911 | case ']': | |
912 | case '4': | |
913 | case '5': | |
914 | case 'H': | |
915 | case 'W': | |
916 | case 'D': | |
917 | case 'j': | |
918 | case '6': | |
919 | case '8': | |
920 | case 'V': | |
921 | case 'C': | |
922 | case 'U': | |
923 | case 'k': | |
924 | case 'K': | |
925 | case 'p': | |
926 | case 'q': | |
927 | case 'A': | |
928 | case 'B': | |
929 | case 'E': | |
930 | { | |
931 | int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; | |
932 | ||
933 | shift = 0; | |
934 | signedp = 0; | |
935 | extbits = 16; | |
936 | pcrel = 0; | |
937 | extu = 0; | |
938 | branch = 0; | |
939 | switch (type) | |
940 | { | |
941 | case '<': | |
942 | nbits = 3; | |
943 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
944 | extbits = 5; | |
945 | extu = 1; | |
946 | break; | |
947 | case '>': | |
948 | nbits = 3; | |
949 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
950 | extbits = 5; | |
951 | extu = 1; | |
952 | break; | |
953 | case '[': | |
954 | nbits = 3; | |
955 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
956 | extbits = 6; | |
957 | extu = 1; | |
958 | break; | |
959 | case ']': | |
960 | nbits = 3; | |
961 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
962 | extbits = 6; | |
963 | extu = 1; | |
964 | break; | |
965 | case '4': | |
966 | nbits = 4; | |
967 | immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; | |
968 | signedp = 1; | |
969 | extbits = 15; | |
970 | break; | |
971 | case '5': | |
972 | nbits = 5; | |
973 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
974 | info->insn_type = dis_dref; | |
975 | info->data_size = 1; | |
976 | break; | |
977 | case 'H': | |
978 | nbits = 5; | |
979 | shift = 1; | |
980 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
981 | info->insn_type = dis_dref; | |
982 | info->data_size = 2; | |
983 | break; | |
984 | case 'W': | |
985 | nbits = 5; | |
986 | shift = 2; | |
987 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
988 | if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 | |
989 | && (op->pinfo & MIPS16_INSN_READ_SP) == 0) | |
990 | { | |
991 | info->insn_type = dis_dref; | |
992 | info->data_size = 4; | |
993 | } | |
994 | break; | |
995 | case 'D': | |
996 | nbits = 5; | |
997 | shift = 3; | |
998 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
999 | info->insn_type = dis_dref; | |
1000 | info->data_size = 8; | |
1001 | break; | |
1002 | case 'j': | |
1003 | nbits = 5; | |
1004 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1005 | signedp = 1; | |
1006 | break; | |
1007 | case '6': | |
1008 | nbits = 6; | |
1009 | immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1010 | break; | |
1011 | case '8': | |
1012 | nbits = 8; | |
1013 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1014 | break; | |
1015 | case 'V': | |
1016 | nbits = 8; | |
1017 | shift = 2; | |
1018 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1019 | /* FIXME: This might be lw, or it might be addiu to $sp or | |
1020 | $pc. We assume it's load. */ | |
1021 | info->insn_type = dis_dref; | |
1022 | info->data_size = 4; | |
1023 | break; | |
1024 | case 'C': | |
1025 | nbits = 8; | |
1026 | shift = 3; | |
1027 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1028 | info->insn_type = dis_dref; | |
1029 | info->data_size = 8; | |
1030 | break; | |
1031 | case 'U': | |
1032 | nbits = 8; | |
1033 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1034 | extu = 1; | |
1035 | break; | |
1036 | case 'k': | |
1037 | nbits = 8; | |
1038 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1039 | signedp = 1; | |
1040 | break; | |
1041 | case 'K': | |
1042 | nbits = 8; | |
1043 | shift = 3; | |
1044 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1045 | signedp = 1; | |
1046 | break; | |
1047 | case 'p': | |
1048 | nbits = 8; | |
1049 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1050 | signedp = 1; | |
1051 | pcrel = 1; | |
1052 | branch = 1; | |
1053 | info->insn_type = dis_condbranch; | |
1054 | break; | |
1055 | case 'q': | |
1056 | nbits = 11; | |
1057 | immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; | |
1058 | signedp = 1; | |
1059 | pcrel = 1; | |
1060 | branch = 1; | |
1061 | info->insn_type = dis_branch; | |
1062 | break; | |
1063 | case 'A': | |
1064 | nbits = 8; | |
1065 | shift = 2; | |
1066 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1067 | pcrel = 1; | |
1068 | /* FIXME: This can be lw or la. We assume it is lw. */ | |
1069 | info->insn_type = dis_dref; | |
1070 | info->data_size = 4; | |
1071 | break; | |
1072 | case 'B': | |
1073 | nbits = 5; | |
1074 | shift = 3; | |
1075 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1076 | pcrel = 1; | |
1077 | info->insn_type = dis_dref; | |
1078 | info->data_size = 8; | |
1079 | break; | |
1080 | case 'E': | |
1081 | nbits = 5; | |
1082 | shift = 2; | |
1083 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1084 | pcrel = 1; | |
1085 | break; | |
1086 | default: | |
1087 | abort (); | |
1088 | } | |
1089 | ||
1090 | if (! use_extend) | |
1091 | { | |
1092 | if (signedp && immed >= (1 << (nbits - 1))) | |
1093 | immed -= 1 << nbits; | |
1094 | immed <<= shift; | |
1095 | if ((type == '<' || type == '>' || type == '[' || type == ']') | |
1096 | && immed == 0) | |
1097 | immed = 8; | |
1098 | } | |
1099 | else | |
1100 | { | |
1101 | if (extbits == 16) | |
1102 | immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); | |
1103 | else if (extbits == 15) | |
1104 | immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); | |
1105 | else | |
1106 | immed = ((extend >> 6) & 0x1f) | (extend & 0x20); | |
1107 | immed &= (1 << extbits) - 1; | |
1108 | if (! extu && immed >= (1 << (extbits - 1))) | |
1109 | immed -= 1 << extbits; | |
1110 | } | |
1111 | ||
1112 | if (! pcrel) | |
1113 | (*info->fprintf_func) (info->stream, "%d", immed); | |
1114 | else | |
1115 | { | |
1116 | bfd_vma baseaddr; | |
252b5132 RH |
1117 | |
1118 | if (branch) | |
1119 | { | |
1120 | immed *= 2; | |
1121 | baseaddr = memaddr + 2; | |
1122 | } | |
1123 | else if (use_extend) | |
1124 | baseaddr = memaddr - 2; | |
1125 | else | |
1126 | { | |
1127 | int status; | |
1128 | bfd_byte buffer[2]; | |
1129 | ||
1130 | baseaddr = memaddr; | |
1131 | ||
1132 | /* If this instruction is in the delay slot of a jr | |
1133 | instruction, the base address is the address of the | |
1134 | jr instruction. If it is in the delay slot of jalr | |
1135 | instruction, the base address is the address of the | |
1136 | jalr instruction. This test is unreliable: we have | |
1137 | no way of knowing whether the previous word is | |
1138 | instruction or data. */ | |
1139 | status = (*info->read_memory_func) (memaddr - 4, buffer, 2, | |
1140 | info); | |
1141 | if (status == 0 | |
1142 | && (((info->endian == BFD_ENDIAN_BIG | |
1143 | ? bfd_getb16 (buffer) | |
1144 | : bfd_getl16 (buffer)) | |
1145 | & 0xf800) == 0x1800)) | |
1146 | baseaddr = memaddr - 4; | |
1147 | else | |
1148 | { | |
1149 | status = (*info->read_memory_func) (memaddr - 2, buffer, | |
1150 | 2, info); | |
1151 | if (status == 0 | |
1152 | && (((info->endian == BFD_ENDIAN_BIG | |
1153 | ? bfd_getb16 (buffer) | |
1154 | : bfd_getl16 (buffer)) | |
1155 | & 0xf81f) == 0xe800)) | |
1156 | baseaddr = memaddr - 2; | |
1157 | } | |
1158 | } | |
9bb28706 CD |
1159 | info->target = (baseaddr & ~((1 << shift) - 1)) + immed; |
1160 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
1161 | } |
1162 | } | |
1163 | break; | |
1164 | ||
1165 | case 'a': | |
1166 | if (! use_extend) | |
1167 | extend = 0; | |
1168 | l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); | |
9bb28706 CD |
1169 | info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; |
1170 | (*info->print_address_func) (info->target, info); | |
252b5132 | 1171 | info->insn_type = dis_jsr; |
252b5132 RH |
1172 | info->branch_delay_insns = 1; |
1173 | break; | |
1174 | ||
1175 | case 'l': | |
1176 | case 'L': | |
1177 | { | |
1178 | int need_comma, amask, smask; | |
1179 | ||
1180 | need_comma = 0; | |
1181 | ||
1182 | l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1183 | ||
1184 | amask = (l >> 3) & 7; | |
1185 | ||
1186 | if (amask > 0 && amask < 5) | |
1187 | { | |
aa5f19f2 | 1188 | (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[4]); |
252b5132 | 1189 | if (amask > 1) |
aa5f19f2 NC |
1190 | (*info->fprintf_func) (info->stream, "-%s", |
1191 | mips32_reg_names[amask + 3]); | |
252b5132 RH |
1192 | need_comma = 1; |
1193 | } | |
1194 | ||
1195 | smask = (l >> 1) & 3; | |
1196 | if (smask == 3) | |
1197 | { | |
1198 | (*info->fprintf_func) (info->stream, "%s??", | |
1199 | need_comma ? "," : ""); | |
1200 | need_comma = 1; | |
1201 | } | |
1202 | else if (smask > 0) | |
1203 | { | |
aa5f19f2 | 1204 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1205 | need_comma ? "," : "", |
aa5f19f2 | 1206 | mips32_reg_names[16]); |
252b5132 | 1207 | if (smask > 1) |
aa5f19f2 NC |
1208 | (*info->fprintf_func) (info->stream, "-%s", |
1209 | mips32_reg_names[smask + 15]); | |
252b5132 RH |
1210 | need_comma = 1; |
1211 | } | |
1212 | ||
1213 | if (l & 1) | |
1214 | { | |
aa5f19f2 | 1215 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1216 | need_comma ? "," : "", |
aa5f19f2 | 1217 | mips32_reg_names[31]); |
252b5132 RH |
1218 | need_comma = 1; |
1219 | } | |
1220 | ||
1221 | if (amask == 5 || amask == 6) | |
1222 | { | |
1223 | (*info->fprintf_func) (info->stream, "%s$f0", | |
1224 | need_comma ? "," : ""); | |
1225 | if (amask == 6) | |
1226 | (*info->fprintf_func) (info->stream, "-$f1"); | |
1227 | } | |
1228 | } | |
1229 | break; | |
1230 | ||
1231 | default: | |
aa5f19f2 NC |
1232 | /* xgettext:c-format */ |
1233 | (*info->fprintf_func) | |
1234 | (info->stream, | |
1235 | _("# internal disassembler error, unrecognised modifier (%c)"), | |
1236 | type); | |
252b5132 RH |
1237 | abort (); |
1238 | } | |
1239 | } |