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2008-11-06 Chao-ying Fu <fu@mips.com>
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
CommitLineData
252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
060d22b0 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
57b592a3 3 2000, 2001, 2002, 2003, 2005, 2007, 2008
73da6b6b 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
9b201bb5 7 This file is part of the GNU opcodes library.
252b5132 8
9b201bb5 9 This library is free software; you can redistribute it and/or modify
47b0e7ad 10 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
252b5132 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
252b5132 18
47b0e7ad
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
252b5132
RH		 24#include "sysdep.h"
25#include "dis-asm.h"
640c0ccd 26#include "libiberty.h"
252b5132
RH		 27#include "opcode/mips.h"
28#include "opintl.h"
29
30/* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
7f6621cd 33 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 34
35#if !defined(EMBEDDED_ENV)
36#define SYMTAB_AVAILABLE 1
37#include "elf-bfd.h"
38#include "elf/mips.h"
39#endif
40
aa5f19f2
NC		 41/* Mips instructions are at maximum this many bytes long. */
42#define INSNLEN 4
43
252b5132 44\f
aa5f19f2 45/* FIXME: These should be shared with gdb somehow. */
252b5132 46
47b0e7ad
NC		 47struct mips_cp0sel_name
48{
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
bbcc0807
CD		 52};
53
654c225a
TS		 54/* The mips16 registers. */
55static const unsigned int mips16_to_32_reg_map[] =
47b0e7ad 56{
654c225a 57 16, 17, 2, 3, 4, 5, 6, 7
252b5132 58};
fb48caed 59
654c225a
TS		 60#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
47b0e7ad
NC		 63static const char * const mips_gpr_names_numeric[32] =
64{
640c0ccd
CD		 65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 69};
70
47b0e7ad
NC		 71static const char * const mips_gpr_names_oldabi[32] =
72{
640c0ccd
CD		 73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 77};
78
47b0e7ad
NC		 79static const char * const mips_gpr_names_newabi[32] =
80{
640c0ccd 81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
0b14f26e 82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
640c0ccd
CD		 83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85};
86
47b0e7ad
NC		 87static const char * const mips_fpr_names_numeric[32] =
88{
640c0ccd
CD		 89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93};
94
47b0e7ad
NC		 95static const char * const mips_fpr_names_32[32] =
96{
640c0ccd
CD		 97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101};
102
47b0e7ad
NC		 103static const char * const mips_fpr_names_n32[32] =
104{
640c0ccd
CD		 105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109};
110
47b0e7ad
NC		 111static const char * const mips_fpr_names_64[32] =
112{
640c0ccd
CD		 113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117};
118
47b0e7ad
NC		 119static const char * const mips_cp0_names_numeric[32] =
120{
640c0ccd
CD		 121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125};
126
f409fd1e
MR		 127static const char * const mips_cp0_names_r3000[32] =
128{
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137};
138
139static const char * const mips_cp0_names_r4000[32] =
140{
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149};
150
47b0e7ad
NC		 151static const char * const mips_cp0_names_mips3264[32] =
152{
640c0ccd
CD		 153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161};
162
47b0e7ad
NC		 163static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164{
bbcc0807
CD		 165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194};
195
47b0e7ad
NC		 196static const char * const mips_cp0_names_mips3264r2[32] =
197{
af7ee8bf
CD		 198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206};
207
47b0e7ad
NC		 208static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209{
bbcc0807 210 { 4, 1, "c0_contextconfig" },
59c455b3
TS		 211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
bbcc0807 227 { 5, 1, "c0_pagegrain" },
59c455b3
TS		 228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
bbcc0807
CD		 233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282};
283
640c0ccd 284/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
47b0e7ad
NC		 285static const char * const mips_cp0_names_sb1[32] =
286{
640c0ccd
CD		 287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295};
296
47b0e7ad
NC		 297static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298{
bbcc0807
CD		 299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320};
321
47b0e7ad
NC		 322static const char * const mips_hwr_names_numeric[32] =
323{
af7ee8bf
CD		 324 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
325 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
326 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
327 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
328};
329
47b0e7ad
NC		 330static const char * const mips_hwr_names_mips3264r2[32] =
331{
af7ee8bf
CD		 332 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
333 "$4", "$5", "$6", "$7",
334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
336 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
337};
338
47b0e7ad
NC		 339struct mips_abi_choice
340{
341 const char * name;
640c0ccd
CD		 342 const char * const *gpr_names;
343 const char * const *fpr_names;
344};
345
47b0e7ad
NC		 346struct mips_abi_choice mips_abi_choices[] =
347{
640c0ccd
CD		 348 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
349 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
350 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
351 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
352};
353
47b0e7ad
NC		 354struct mips_arch_choice
355{
640c0ccd
CD		 356 const char *name;
357 int bfd_mach_valid;
358 unsigned long bfd_mach;
359 int processor;
360 int isa;
361 const char * const *cp0_names;
bbcc0807
CD		 362 const struct mips_cp0sel_name *cp0sel_names;
363 unsigned int cp0sel_names_len;
af7ee8bf 364 const char * const *hwr_names;
640c0ccd
CD		 365};
366
47b0e7ad
NC		 367const struct mips_arch_choice mips_arch_choices[] =
368{
640c0ccd 369 { "numeric", 0, 0, 0, 0,
bbcc0807
CD		 370 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
371
640c0ccd 372 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
f409fd1e 373 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
640c0ccd 374 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
bbcc0807 375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 376 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
f409fd1e 377 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
640c0ccd 378 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
bbcc0807 379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 380 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
bbcc0807 381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 382 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
bbcc0807 383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 384 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
bbcc0807 385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 386 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
bbcc0807 387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 388 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
f409fd1e 389 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
640c0ccd 390 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
bbcc0807 391 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 392 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
bbcc0807 393 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 394 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
bbcc0807 395 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 396 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
bbcc0807 397 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 398 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
bbcc0807 399 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 400 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
bbcc0807 401 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
5a7ea749
RS		 402 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
403 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
404 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
405 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 406 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
bbcc0807 407 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 408 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
bbcc0807 409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 410 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
bbcc0807 411 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 412 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
bbcc0807
CD		 413 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
414
640c0ccd
CD		 415 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
416 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
417 _MIPS32 Architecture For Programmers Volume I: Introduction to the
418 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
419 page 1. */
420 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
39a7806d 421 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
bbcc0807
CD		 422 mips_cp0_names_mips3264,
423 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
424 mips_hwr_names_numeric },
425
af7ee8bf 426 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
8b082fb1
TS		 427 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
428 | INSN_MIPS3D | INSN_MT),
bbcc0807
CD		 429 mips_cp0_names_mips3264r2,
430 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
431 mips_hwr_names_mips3264r2 },
432
640c0ccd
CD		 433 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
434 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
39a7806d 435 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
bbcc0807
CD		 436 mips_cp0_names_mips3264,
437 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
438 mips_hwr_names_numeric },
439
5f74bc13 440 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
8b082fb1
TS		 441 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
442 | INSN_DSP64 | INSN_MT | INSN_MDMX),
5f74bc13
CD		 443 mips_cp0_names_mips3264r2,
444 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
445 mips_hwr_names_mips3264r2 },
446
640c0ccd
CD		 447 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
448 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
bbcc0807
CD		 449 mips_cp0_names_sb1,
450 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
451 mips_hwr_names_numeric },
640c0ccd 452
350cc38d
MS		 453 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
454 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
455 NULL, 0, mips_hwr_names_numeric },
456
457 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
458 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
459 NULL, 0, mips_hwr_names_numeric },
460
57b592a3
AN		 461 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
462 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
463 mips_hwr_names_numeric },
464
640c0ccd
CD		 465 /* This entry, mips16, is here only for ISA/processor selection; do
466 not print its name. */
467 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
bbcc0807 468 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd
CD		 469};
470
471/* ISA and processor type to disassemble for, and register names to use.
472 set_default_mips_dis_options and parse_mips_dis_options fill in these
473 values. */
474static int mips_processor;
475static int mips_isa;
476static const char * const *mips_gpr_names;
477static const char * const *mips_fpr_names;
478static const char * const *mips_cp0_names;
bbcc0807
CD		 479static const struct mips_cp0sel_name *mips_cp0sel_names;
480static int mips_cp0sel_names_len;
af7ee8bf 481static const char * const *mips_hwr_names;
640c0ccd 482
986e18a5 483/* Other options */
47b0e7ad 484static int no_aliases; /* If set disassemble as most general inst. */
640c0ccd
CD		 485\f
486static const struct mips_abi_choice *
47b0e7ad 487choose_abi_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 488{
489 const struct mips_abi_choice *c;
490 unsigned int i;
491
492 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
47b0e7ad
NC		 493 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
494 && strlen (mips_abi_choices[i].name) == namelen)
495 c = &mips_abi_choices[i];
496
640c0ccd
CD		 497 return c;
498}
499
500static const struct mips_arch_choice *
47b0e7ad 501choose_arch_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 502{
503 const struct mips_arch_choice *c = NULL;
504 unsigned int i;
505
506 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
47b0e7ad
NC		 507 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
508 && strlen (mips_arch_choices[i].name) == namelen)
509 c = &mips_arch_choices[i];
510
640c0ccd
CD		 511 return c;
512}
513
514static const struct mips_arch_choice *
47b0e7ad 515choose_arch_by_number (unsigned long mach)
640c0ccd
CD		 516{
517 static unsigned long hint_bfd_mach;
518 static const struct mips_arch_choice *hint_arch_choice;
519 const struct mips_arch_choice *c;
520 unsigned int i;
521
522 /* We optimize this because even if the user specifies no
523 flags, this will be done for every instruction! */
524 if (hint_bfd_mach == mach
525 && hint_arch_choice != NULL
526 && hint_arch_choice->bfd_mach == hint_bfd_mach)
527 return hint_arch_choice;
528
529 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
530 {
531 if (mips_arch_choices[i].bfd_mach_valid
532 && mips_arch_choices[i].bfd_mach == mach)
533 {
534 c = &mips_arch_choices[i];
535 hint_bfd_mach = mach;
536 hint_arch_choice = c;
537 }
538 }
539 return c;
540}
541
47b0e7ad
NC		 542/* Check if the object uses NewABI conventions. */
543
544static int
545is_newabi (Elf_Internal_Ehdr *header)
546{
547 /* There are no old-style ABIs which use 64-bit ELF. */
548 if (header->e_ident[EI_CLASS] == ELFCLASS64)
549 return 1;
550
551 /* If a 32-bit ELF file, n32 is a new-style ABI. */
552 if ((header->e_flags & EF_MIPS_ABI2) != 0)
553 return 1;
554
555 return 0;
556}
557
558static void
559set_default_mips_dis_options (struct disassemble_info *info)
640c0ccd
CD		 560{
561 const struct mips_arch_choice *chosen_arch;
562
563 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
af7ee8bf 564 and numeric FPR, CP0 register, and HWR names. */
640c0ccd
CD		 565 mips_isa = ISA_MIPS3;
566 mips_processor = CPU_R3000;
567 mips_gpr_names = mips_gpr_names_oldabi;
568 mips_fpr_names = mips_fpr_names_numeric;
569 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 570 mips_cp0sel_names = NULL;
571 mips_cp0sel_names_len = 0;
af7ee8bf 572 mips_hwr_names = mips_hwr_names_numeric;
986e18a5 573 no_aliases = 0;
640c0ccd
CD		 574
575 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
fec06546 576 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
640c0ccd
CD		 577 {
578 Elf_Internal_Ehdr *header;
579
fec06546 580 header = elf_elfheader (info->section->owner);
640c0ccd
CD		 581 if (is_newabi (header))
582 mips_gpr_names = mips_gpr_names_newabi;
583 }
584
585 /* Set ISA, architecture, and cp0 register names as best we can. */
586#if ! SYMTAB_AVAILABLE
587 /* This is running out on a target machine, not in a host tool.
588 FIXME: Where does mips_target_info come from? */
589 target_processor = mips_target_info.processor;
590 mips_isa = mips_target_info.isa;
591#else
592 chosen_arch = choose_arch_by_number (info->mach);
593 if (chosen_arch != NULL)
594 {
595 mips_processor = chosen_arch->processor;
596 mips_isa = chosen_arch->isa;
bbcc0807
CD		 597 mips_cp0_names = chosen_arch->cp0_names;
598 mips_cp0sel_names = chosen_arch->cp0sel_names;
599 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
600 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 601 }
602#endif
603}
604
47b0e7ad
NC		 605static void
606parse_mips_dis_option (const char *option, unsigned int len)
640c0ccd
CD		 607{
608 unsigned int i, optionlen, vallen;
609 const char *val;
610 const struct mips_abi_choice *chosen_abi;
611 const struct mips_arch_choice *chosen_arch;
612
986e18a5 613 /* Try to match options that are simple flags */
0112cd26 614 if (CONST_STRNEQ (option, "no-aliases"))
986e18a5
FF		 615 {
616 no_aliases = 1;
617 return;
618 }
619
640c0ccd
CD		 620 /* Look for the = that delimits the end of the option name. */
621 for (i = 0; i < len; i++)
47b0e7ad
NC		 622 if (option[i] == '=')
623 break;
624
640c0ccd
CD		 625 if (i == 0) /* Invalid option: no name before '='. */
626 return;
627 if (i == len) /* Invalid option: no '='. */
628 return;
629 if (i == (len - 1)) /* Invalid option: no value after '='. */
630 return;
631
632 optionlen = i;
633 val = option + (optionlen + 1);
634 vallen = len - (optionlen + 1);
635
47b0e7ad
NC		 636 if (strncmp ("gpr-names", option, optionlen) == 0
637 && strlen ("gpr-names") == optionlen)
640c0ccd
CD		 638 {
639 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 640 if (chosen_abi != NULL)
640c0ccd
CD		 641 mips_gpr_names = chosen_abi->gpr_names;
642 return;
643 }
644
47b0e7ad
NC		 645 if (strncmp ("fpr-names", option, optionlen) == 0
646 && strlen ("fpr-names") == optionlen)
640c0ccd
CD		 647 {
648 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 649 if (chosen_abi != NULL)
640c0ccd
CD		 650 mips_fpr_names = chosen_abi->fpr_names;
651 return;
652 }
653
47b0e7ad
NC		 654 if (strncmp ("cp0-names", option, optionlen) == 0
655 && strlen ("cp0-names") == optionlen)
640c0ccd
CD		 656 {
657 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 658 if (chosen_arch != NULL)
659 {
660 mips_cp0_names = chosen_arch->cp0_names;
661 mips_cp0sel_names = chosen_arch->cp0sel_names;
662 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
663 }
640c0ccd
CD		 664 return;
665 }
666
47b0e7ad
NC		 667 if (strncmp ("hwr-names", option, optionlen) == 0
668 && strlen ("hwr-names") == optionlen)
af7ee8bf
CD		 669 {
670 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 671 if (chosen_arch != NULL)
af7ee8bf
CD		 672 mips_hwr_names = chosen_arch->hwr_names;
673 return;
674 }
675
47b0e7ad
NC		 676 if (strncmp ("reg-names", option, optionlen) == 0
677 && strlen ("reg-names") == optionlen)
640c0ccd
CD		 678 {
679 /* We check both ABI and ARCH here unconditionally, so
680 that "numeric" will do the desirable thing: select
681 numeric register names for all registers. Other than
682 that, a given name probably won't match both. */
683 chosen_abi = choose_abi_by_name (val, vallen);
684 if (chosen_abi != NULL)
685 {
bbcc0807
CD		 686 mips_gpr_names = chosen_abi->gpr_names;
687 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 688 }
689 chosen_arch = choose_arch_by_name (val, vallen);
690 if (chosen_arch != NULL)
691 {
bbcc0807
CD		 692 mips_cp0_names = chosen_arch->cp0_names;
693 mips_cp0sel_names = chosen_arch->cp0sel_names;
694 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
695 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 696 }
697 return;
698 }
699
700 /* Invalid option. */
701}
702
47b0e7ad
NC		 703static void
704parse_mips_dis_options (const char *options)
640c0ccd
CD		 705{
706 const char *option_end;
707
708 if (options == NULL)
709 return;
710
711 while (*options != '\0')
712 {
713 /* Skip empty options. */
714 if (*options == ',')
715 {
716 options++;
717 continue;
718 }
719
720 /* We know that *options is neither NUL or a comma. */
721 option_end = options + 1;
722 while (*option_end != ',' && *option_end != '\0')
723 option_end++;
724
725 parse_mips_dis_option (options, option_end - options);
726
727 /* Go on to the next one. If option_end points to a comma, it
728 will be skipped above. */
729 options = option_end;
730 }
731}
732
bbcc0807 733static const struct mips_cp0sel_name *
47b0e7ad
NC		 734lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
735 unsigned int len,
736 unsigned int cp0reg,
737 unsigned int sel)
bbcc0807
CD		 738{
739 unsigned int i;
740
741 for (i = 0; i < len; i++)
742 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
743 return &names[i];
744 return NULL;
745}
252b5132 746\f
7f6621cd 747/* Print insn arguments for 32/64-bit code. */
aa5f19f2 748
794ac9d0 749static void
47b0e7ad
NC		 750print_insn_args (const char *d,
751 register unsigned long int l,
752 bfd_vma pc,
cc0ca239
TS		 753 struct disassemble_info *info,
754 const struct mips_opcode *opp)
252b5132 755{
794ac9d0 756 int op, delta;
440cc0bc
CD		 757 unsigned int lsb, msb, msbd;
758
759 lsb = 0;
252b5132 760
794ac9d0 761 for (; *d != '\0'; d++)
252b5132 762 {
af7ee8bf
CD		 763 switch (*d)
764 {
794ac9d0
CD		 765 case ',':
766 case '(':
767 case ')':
768 case '[':
769 case ']':
770 (*info->fprintf_func) (info->stream, "%c", *d);
771 break;
772
773 case '+':
774 /* Extension character; switch for second char. */
775 d++;
776 switch (*d)
777 {
778 case '\0':
779 /* xgettext:c-format */
780 (*info->fprintf_func) (info->stream,
781 _("# internal error, incomplete extension sequence (+)"));
782 return;
783
784 case 'A':
440cc0bc
CD		 785 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
786 (*info->fprintf_func) (info->stream, "0x%x", lsb);
794ac9d0
CD		 787 break;
788
789 case 'B':
440cc0bc
CD		 790 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
791 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
794ac9d0
CD		 792 break;
793
9bcd4f99
TS		 794 case '1':
795 (*info->fprintf_func) (info->stream, "0x%lx",
796 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
797 break;
798
799 case '2':
800 (*info->fprintf_func) (info->stream, "0x%lx",
801 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
802 break;
803
804 case '3':
805 (*info->fprintf_func) (info->stream, "0x%lx",
806 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
807 break;
808
809 case '4':
810 (*info->fprintf_func) (info->stream, "0x%lx",
811 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
812 break;
813
794ac9d0 814 case 'C':
5f74bc13 815 case 'H':
440cc0bc
CD		 816 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
817 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
794ac9d0
CD		 818 break;
819
820 case 'D':
821 {
822 const struct mips_cp0sel_name *n;
823 unsigned int cp0reg, sel;
824
825 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
826 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
827
828 /* CP0 register including 'sel' code for mtcN (et al.), to be
829 printed textually if known. If not known, print both
830 CP0 register name and sel numerically since CP0 register
831 with sel 0 may have a name unrelated to register being
832 printed. */
833 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
834 mips_cp0sel_names_len, cp0reg, sel);
835 if (n != NULL)
836 (*info->fprintf_func) (info->stream, "%s", n->name);
837 else
838 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
839 break;
840 }
841
5f74bc13
CD		 842 case 'E':
843 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
844 (*info->fprintf_func) (info->stream, "0x%x", lsb);
845 break;
846
847 case 'F':
848 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
849 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
850 break;
851
852 case 'G':
853 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
854 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
855 break;
856
61cc0267
CF		 857 case 't': /* Coprocessor 0 reg name */
858 (*info->fprintf_func) (info->stream, "%s",
859 mips_cp0_names[(l >> OP_SH_RT) &
860 OP_MASK_RT]);
861 break;
862
863 case 'T': /* Coprocessor 0 reg name */
864 {
865 const struct mips_cp0sel_name *n;
866 unsigned int cp0reg, sel;
867
868 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
869 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
870
871 /* CP0 register including 'sel' code for mftc0, to be
872 printed textually if known. If not known, print both
873 CP0 register name and sel numerically since CP0 register
874 with sel 0 may have a name unrelated to register being
875 printed. */
876 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
877 mips_cp0sel_names_len, cp0reg, sel);
878 if (n != NULL)
879 (*info->fprintf_func) (info->stream, "%s", n->name);
880 else
881 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
882 break;
883 }
884
bb35fb24
NC		 885 case 'x': /* bbit bit index */
886 (*info->fprintf_func) (info->stream, "0x%lx",
887 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
888 break;
889
890 case 'p': /* cins, cins32, exts and exts32 position */
891 (*info->fprintf_func) (info->stream, "0x%lx",
892 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
893 break;
894
895 case 's': /* cins and exts length-minus-one */
896 (*info->fprintf_func) (info->stream, "0x%lx",
897 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
898 break;
899
900 case 'S': /* cins32 and exts32 length-minus-one field */
901 (*info->fprintf_func) (info->stream, "0x%lx",
902 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
903 break;
904
dd3cbb7e
NC		 905 case 'Q': /* seqi/snei immediate field */
906 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
907 /* Sign-extend it. */
908 op = (op ^ 512) - 512;
909 (*info->fprintf_func) (info->stream, "%d", op);
910 break;
911
794ac9d0
CD		 912 default:
913 /* xgettext:c-format */
914 (*info->fprintf_func) (info->stream,
915 _("# internal error, undefined extension sequence (+%c)"),
916 *d);
917 return;
918 }
919 break;
920
8b082fb1
TS		 921 case '2':
922 (*info->fprintf_func) (info->stream, "0x%lx",
923 (l >> OP_SH_BP) & OP_MASK_BP);
924 break;
925
fd25c5a9
CF		 926 case '3':
927 (*info->fprintf_func) (info->stream, "0x%lx",
928 (l >> OP_SH_SA3) & OP_MASK_SA3);
929 break;
930
931 case '4':
932 (*info->fprintf_func) (info->stream, "0x%lx",
933 (l >> OP_SH_SA4) & OP_MASK_SA4);
934 break;
935
936 case '5':
937 (*info->fprintf_func) (info->stream, "0x%lx",
938 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
939 break;
940
941 case '6':
942 (*info->fprintf_func) (info->stream, "0x%lx",
943 (l >> OP_SH_RS) & OP_MASK_RS);
944 break;
945
946 case '7':
947 (*info->fprintf_func) (info->stream, "$ac%ld",
948 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
949 break;
950
951 case '8':
952 (*info->fprintf_func) (info->stream, "0x%lx",
953 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
954 break;
955
956 case '9':
957 (*info->fprintf_func) (info->stream, "$ac%ld",
958 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
959 break;
960
961 case '0': /* dsp 6-bit signed immediate in bit 20 */
962 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
963 if (delta & 0x20) /* test sign bit */
964 delta |= ~OP_MASK_DSPSFT;
965 (*info->fprintf_func) (info->stream, "%d", delta);
966 break;
967
968 case ':': /* dsp 7-bit signed immediate in bit 19 */
969 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
970 if (delta & 0x40) /* test sign bit */
971 delta |= ~OP_MASK_DSPSFT_7;
972 (*info->fprintf_func) (info->stream, "%d", delta);
973 break;
974
975 case '\'':
976 (*info->fprintf_func) (info->stream, "0x%lx",
977 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
978 break;
979
980 case '@': /* dsp 10-bit signed immediate in bit 16 */
981 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
982 if (delta & 0x200) /* test sign bit */
983 delta |= ~OP_MASK_IMM10;
984 (*info->fprintf_func) (info->stream, "%d", delta);
985 break;
986
61cc0267
CF		 987 case '!':
988 (*info->fprintf_func) (info->stream, "%ld",
989 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
990 break;
991
992 case '$':
993 (*info->fprintf_func) (info->stream, "%ld",
994 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
995 break;
996
997 case '*':
998 (*info->fprintf_func) (info->stream, "$ac%ld",
999 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1000 break;
1001
1002 case '&':
1003 (*info->fprintf_func) (info->stream, "$ac%ld",
1004 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1005 break;
1006
1007 case 'g':
1008 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1009 (*info->fprintf_func) (info->stream, "$%ld",
1010 (l >> OP_SH_RD) & OP_MASK_RD);
1011 break;
1012
794ac9d0
CD		 1013 case 's':
1014 case 'b':
1015 case 'r':
1016 case 'v':
1017 (*info->fprintf_func) (info->stream, "%s",
1018 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1019 break;
1020
1021 case 't':
1022 case 'w':
1023 (*info->fprintf_func) (info->stream, "%s",
1024 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1025 break;
1026
1027 case 'i':
1028 case 'u':
0fd3a477 1029 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1030 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1031 break;
1032
1033 case 'j': /* Same as i, but sign-extended. */
1034 case 'o':
1035 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1036 if (delta & 0x8000)
1037 delta |= ~0xffff;
1038 (*info->fprintf_func) (info->stream, "%d",
1039 delta);
1040 break;
1041
1042 case 'h':
1043 (*info->fprintf_func) (info->stream, "0x%x",
1044 (unsigned int) ((l >> OP_SH_PREFX)
1045 & OP_MASK_PREFX));
1046 break;
1047
1048 case 'k':
1049 (*info->fprintf_func) (info->stream, "0x%x",
1050 (unsigned int) ((l >> OP_SH_CACHE)
1051 & OP_MASK_CACHE));
1052 break;
1053
1054 case 'a':
1055 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1056 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
022fac6d
TS		 1057 /* For gdb disassembler, force odd address on jalx. */
1058 if (info->flavour == bfd_target_unknown_flavour
1059 && strcmp (opp->name, "jalx") == 0)
1060 info->target |= 1;
794ac9d0
CD		 1061 (*info->print_address_func) (info->target, info);
1062 break;
1063
1064 case 'p':
1065 /* Sign extend the displacement. */
1066 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1067 if (delta & 0x8000)
1068 delta |= ~0xffff;
1069 info->target = (delta << 2) + pc + INSNLEN;
1070 (*info->print_address_func) (info->target, info);
1071 break;
1072
1073 case 'd':
1074 (*info->fprintf_func) (info->stream, "%s",
1075 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1076 break;
1077
1078 case 'U':
1079 {
1080 /* First check for both rd and rt being equal. */
1081 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1082 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1083 (*info->fprintf_func) (info->stream, "%s",
1084 mips_gpr_names[reg]);
1085 else
1086 {
1087 /* If one is zero use the other. */
1088 if (reg == 0)
1089 (*info->fprintf_func) (info->stream, "%s",
1090 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1091 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1092 (*info->fprintf_func) (info->stream, "%s",
1093 mips_gpr_names[reg]);
1094 else /* Bogus, result depends on processor. */
1095 (*info->fprintf_func) (info->stream, "%s or %s",
1096 mips_gpr_names[reg],
1097 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1098 }
1099 }
1100 break;
1101
1102 case 'z':
1103 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1104 break;
1105
1106 case '<':
4dc48ef6 1107 case '1':
0fd3a477 1108 (*info->fprintf_func) (info->stream, "0x%lx",
af7ee8bf
CD		 1109 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1110 break;
794ac9d0
CD		 1111
1112 case 'c':
0fd3a477 1113 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1114 (l >> OP_SH_CODE) & OP_MASK_CODE);
1115 break;
1116
1117 case 'q':
0fd3a477 1118 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0 1119 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
af7ee8bf
CD		 1120 break;
1121
1122 case 'C':
0fd3a477 1123 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1124 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1125 break;
1126
1127 case 'B':
0fd3a477
JW		 1128 (*info->fprintf_func) (info->stream, "0x%lx",
1129
794ac9d0
CD		 1130 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1131 break;
1132
1133 case 'J':
0fd3a477 1134 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1135 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1136 break;
1137
1138 case 'S':
1139 case 'V':
1140 (*info->fprintf_func) (info->stream, "%s",
1141 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1142 break;
1143
1144 case 'T':
1145 case 'W':
1146 (*info->fprintf_func) (info->stream, "%s",
1147 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
af7ee8bf
CD		 1148 break;
1149
bbcc0807 1150 case 'D':
794ac9d0
CD		 1151 (*info->fprintf_func) (info->stream, "%s",
1152 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1153 break;
1154
1155 case 'R':
1156 (*info->fprintf_func) (info->stream, "%s",
1157 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1158 break;
1159
1160 case 'E':
1161 /* Coprocessor register for lwcN instructions, et al.
1162
1163 Note that there is no load/store cp0 instructions, and
1164 that FPU (cp1) instructions disassemble this field using
1165 'T' format. Therefore, until we gain understanding of
1166 cp2 register names, we can simply print the register
1167 numbers. */
0fd3a477 1168 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1169 (l >> OP_SH_RT) & OP_MASK_RT);
1170 break;
1171
1172 case 'G':
1173 /* Coprocessor register for mtcN instructions, et al. Note
1174 that FPU (cp1) instructions disassemble this field using
1175 'S' format. Therefore, we only need to worry about cp0,
1176 cp2, and cp3. */
1177 op = (l >> OP_SH_OP) & OP_MASK_OP;
1178 if (op == OP_OP_COP0)
1179 (*info->fprintf_func) (info->stream, "%s",
1180 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1181 else
0fd3a477 1182 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1183 (l >> OP_SH_RD) & OP_MASK_RD);
1184 break;
1185
1186 case 'K':
1187 (*info->fprintf_func) (info->stream, "%s",
1188 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1189 break;
1190
1191 case 'N':
0d09bfe6
TS		 1192 (*info->fprintf_func) (info->stream,
1193 ((opp->pinfo & (FP_D | FP_S)) != 0
1194 ? "$fcc%ld" : "$cc%ld"),
794ac9d0
CD		 1195 (l >> OP_SH_BCC) & OP_MASK_BCC);
1196 break;
1197
1198 case 'M':
0fd3a477 1199 (*info->fprintf_func) (info->stream, "$fcc%ld",
794ac9d0
CD		 1200 (l >> OP_SH_CCC) & OP_MASK_CCC);
1201 break;
1202
1203 case 'P':
0fd3a477 1204 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1205 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1206 break;
1207
1208 case 'e':
0fd3a477 1209 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1210 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1211 break;
1212
1213 case '%':
0fd3a477 1214 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1215 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1216 break;
1217
1218 case 'H':
0fd3a477 1219 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1220 (l >> OP_SH_SEL) & OP_MASK_SEL);
1221 break;
1222
1223 case 'O':
0fd3a477 1224 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1225 (l >> OP_SH_ALN) & OP_MASK_ALN);
1226 break;
1227
1228 case 'Q':
bbcc0807 1229 {
794ac9d0 1230 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
47b0e7ad 1231
794ac9d0
CD		 1232 if ((vsel & 0x10) == 0)
1233 {
1234 int fmt;
47b0e7ad 1235
794ac9d0
CD		 1236 vsel &= 0x0f;
1237 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1238 if ((vsel & 1) == 0)
1239 break;
0fd3a477 1240 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
794ac9d0
CD		 1241 (l >> OP_SH_FT) & OP_MASK_FT,
1242 vsel >> 1);
1243 }
1244 else if ((vsel & 0x08) == 0)
1245 {
0fd3a477 1246 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1247 (l >> OP_SH_FT) & OP_MASK_FT);
1248 }
bbcc0807 1249 else
794ac9d0 1250 {
0fd3a477 1251 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1252 (l >> OP_SH_FT) & OP_MASK_FT);
1253 }
bbcc0807 1254 }
794ac9d0
CD		 1255 break;
1256
1257 case 'X':
0fd3a477 1258 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1259 (l >> OP_SH_FD) & OP_MASK_FD);
1260 break;
1261
1262 case 'Y':
0fd3a477 1263 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1264 (l >> OP_SH_FS) & OP_MASK_FS);
1265 break;
1266
1267 case 'Z':
0fd3a477 1268 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1269 (l >> OP_SH_FT) & OP_MASK_FT);
1270 break;
bbcc0807 1271
af7ee8bf
CD		 1272 default:
1273 /* xgettext:c-format */
1274 (*info->fprintf_func) (info->stream,
168411b1 1275 _("# internal error, undefined modifier (%c)"),
af7ee8bf 1276 *d);
794ac9d0 1277 return;
af7ee8bf 1278 }
252b5132
RH		 1279 }
1280}
1281\f
252b5132
RH		 1282/* Print the mips instruction at address MEMADDR in debugged memory,
1283 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1284 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1285 this is little-endian code. */
1286
1287static int
47b0e7ad
NC		 1288print_insn_mips (bfd_vma memaddr,
1289 unsigned long int word,
1290 struct disassemble_info *info)
252b5132 1291{
47b0e7ad 1292 const struct mips_opcode *op;
b34976b6 1293 static bfd_boolean init = 0;
252b5132
RH		 1294 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1295
1296 /* Build a hash table to shorten the search time. */
1297 if (! init)
1298 {
1299 unsigned int i;
1300
1301 for (i = 0; i <= OP_MASK_OP; i++)
1302 {
1303 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1304 {
986e18a5 1305 if (op->pinfo == INSN_MACRO
9e836e3d 1306 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
252b5132
RH		 1307 continue;
1308 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1309 {
1310 mips_hash[i] = op;
1311 break;
1312 }
1313 }
7f6621cd 1314 }
252b5132
RH		 1315
1316 init = 1;
1317 }
1318
aa5f19f2 1319 info->bytes_per_chunk = INSNLEN;
252b5132 1320 info->display_endian = info->endian;
9bb28706
CD		 1321 info->insn_info_valid = 1;
1322 info->branch_delay_insns = 0;
def7143b 1323 info->data_size = 0;
9bb28706
CD		 1324 info->insn_type = dis_nonbranch;
1325 info->target = 0;
1326 info->target2 = 0;
252b5132
RH		 1327
1328 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1329 if (op != NULL)
1330 {
1331 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1332 {
986e18a5 1333 if (op->pinfo != INSN_MACRO
9e836e3d 1334 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
986e18a5 1335 && (word & op->mask) == op->match)
252b5132 1336 {
47b0e7ad 1337 const char *d;
2bd7f1f3 1338
3396de36 1339 /* We always allow to disassemble the jalx instruction. */
640c0ccd 1340 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3396de36 1341 && strcmp (op->name, "jalx"))
252b5132
RH		 1342 continue;
1343
9bb28706
CD		 1344 /* Figure out instruction type and branch delay information. */
1345 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1346 {
1347 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1348 info->insn_type = dis_jsr;
1349 else
1350 info->insn_type = dis_branch;
1351 info->branch_delay_insns = 1;
1352 }
1353 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1354 | INSN_COND_BRANCH_LIKELY)) != 0)
1355 {
1356 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1357 info->insn_type = dis_condjsr;
1358 else
1359 info->insn_type = dis_condbranch;
1360 info->branch_delay_insns = 1;
1361 }
1362 else if ((op->pinfo & (INSN_STORE_MEMORY
1363 | INSN_LOAD_MEMORY_DELAY)) != 0)
1364 info->insn_type = dis_dref;
1365
252b5132
RH		 1366 (*info->fprintf_func) (info->stream, "%s", op->name);
1367
1368 d = op->args;
1369 if (d != NULL && *d != '\0')
1370 {
7f6621cd 1371 (*info->fprintf_func) (info->stream, "\t");
cc0ca239 1372 print_insn_args (d, word, memaddr, info, op);
252b5132
RH		 1373 }
1374
aa5f19f2 1375 return INSNLEN;
252b5132
RH		 1376 }
1377 }
1378 }
1379
1380 /* Handle undefined instructions. */
9bb28706 1381 info->insn_type = dis_noninsn;
0fd3a477 1382 (*info->fprintf_func) (info->stream, "0x%lx", word);
aa5f19f2 1383 return INSNLEN;
252b5132 1384}
aa5f19f2 1385\f
252b5132
RH		 1386/* Disassemble an operand for a mips16 instruction. */
1387
1388static void
47b0e7ad
NC		 1389print_mips16_insn_arg (char type,
1390 const struct mips_opcode *op,
1391 int l,
1392 bfd_boolean use_extend,
1393 int extend,
1394 bfd_vma memaddr,
1395 struct disassemble_info *info)
252b5132
RH		 1396{
1397 switch (type)
1398 {
1399 case ',':
1400 case '(':
1401 case ')':
1402 (*info->fprintf_func) (info->stream, "%c", type);
1403 break;
1404
1405 case 'y':
1406 case 'w':
aa5f19f2 1407 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1408 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1409 & MIPS16OP_MASK_RY)));
252b5132
RH		 1410 break;
1411
1412 case 'x':
1413 case 'v':
aa5f19f2 1414 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1415 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1416 & MIPS16OP_MASK_RX)));
252b5132
RH		 1417 break;
1418
1419 case 'z':
aa5f19f2 1420 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1421 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1422 & MIPS16OP_MASK_RZ)));
252b5132
RH		 1423 break;
1424
1425 case 'Z':
aa5f19f2 1426 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1427 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1428 & MIPS16OP_MASK_MOVE32Z)));
252b5132
RH		 1429 break;
1430
1431 case '0':
640c0ccd 1432 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
252b5132
RH		 1433 break;
1434
1435 case 'S':
640c0ccd 1436 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
252b5132
RH		 1437 break;
1438
1439 case 'P':
1440 (*info->fprintf_func) (info->stream, "$pc");
1441 break;
1442
1443 case 'R':
640c0ccd 1444 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
252b5132
RH		 1445 break;
1446
1447 case 'X':
aa5f19f2 1448 (*info->fprintf_func) (info->stream, "%s",
640c0ccd
CD		 1449 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1450 & MIPS16OP_MASK_REGR32)]);
252b5132
RH		 1451 break;
1452
1453 case 'Y':
aa5f19f2 1454 (*info->fprintf_func) (info->stream, "%s",
640c0ccd 1455 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
252b5132
RH		 1456 break;
1457
1458 case '<':
1459 case '>':
1460 case '[':
1461 case ']':
1462 case '4':
1463 case '5':
1464 case 'H':
1465 case 'W':
1466 case 'D':
1467 case 'j':
1468 case '6':
1469 case '8':
1470 case 'V':
1471 case 'C':
1472 case 'U':
1473 case 'k':
1474 case 'K':
1475 case 'p':
1476 case 'q':
1477 case 'A':
1478 case 'B':
1479 case 'E':
1480 {
1481 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1482
1483 shift = 0;
1484 signedp = 0;
1485 extbits = 16;
1486 pcrel = 0;
1487 extu = 0;
1488 branch = 0;
1489 switch (type)
1490 {
1491 case '<':
1492 nbits = 3;
1493 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1494 extbits = 5;
1495 extu = 1;
1496 break;
1497 case '>':
1498 nbits = 3;
1499 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1500 extbits = 5;
1501 extu = 1;
1502 break;
1503 case '[':
1504 nbits = 3;
1505 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1506 extbits = 6;
1507 extu = 1;
1508 break;
1509 case ']':
1510 nbits = 3;
1511 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1512 extbits = 6;
1513 extu = 1;
1514 break;
1515 case '4':
1516 nbits = 4;
1517 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1518 signedp = 1;
1519 extbits = 15;
1520 break;
1521 case '5':
1522 nbits = 5;
1523 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1524 info->insn_type = dis_dref;
1525 info->data_size = 1;
1526 break;
1527 case 'H':
1528 nbits = 5;
1529 shift = 1;
1530 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1531 info->insn_type = dis_dref;
1532 info->data_size = 2;
1533 break;
1534 case 'W':
1535 nbits = 5;
1536 shift = 2;
1537 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1538 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1539 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1540 {
1541 info->insn_type = dis_dref;
1542 info->data_size = 4;
1543 }
1544 break;
1545 case 'D':
1546 nbits = 5;
1547 shift = 3;
1548 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1549 info->insn_type = dis_dref;
1550 info->data_size = 8;
1551 break;
1552 case 'j':
1553 nbits = 5;
1554 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1555 signedp = 1;
1556 break;
1557 case '6':
1558 nbits = 6;
1559 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1560 break;
1561 case '8':
1562 nbits = 8;
1563 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1564 break;
1565 case 'V':
1566 nbits = 8;
1567 shift = 2;
1568 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1569 /* FIXME: This might be lw, or it might be addiu to $sp or
1570 $pc. We assume it's load. */
1571 info->insn_type = dis_dref;
1572 info->data_size = 4;
1573 break;
1574 case 'C':
1575 nbits = 8;
1576 shift = 3;
1577 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1578 info->insn_type = dis_dref;
1579 info->data_size = 8;
1580 break;
1581 case 'U':
1582 nbits = 8;
1583 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1584 extu = 1;
1585 break;
1586 case 'k':
1587 nbits = 8;
1588 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1589 signedp = 1;
1590 break;
1591 case 'K':
1592 nbits = 8;
1593 shift = 3;
1594 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1595 signedp = 1;
1596 break;
1597 case 'p':
1598 nbits = 8;
1599 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1600 signedp = 1;
1601 pcrel = 1;
1602 branch = 1;
1603 info->insn_type = dis_condbranch;
1604 break;
1605 case 'q':
1606 nbits = 11;
1607 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1608 signedp = 1;
1609 pcrel = 1;
1610 branch = 1;
1611 info->insn_type = dis_branch;
1612 break;
1613 case 'A':
1614 nbits = 8;
1615 shift = 2;
1616 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1617 pcrel = 1;
1618 /* FIXME: This can be lw or la. We assume it is lw. */
1619 info->insn_type = dis_dref;
1620 info->data_size = 4;
1621 break;
1622 case 'B':
1623 nbits = 5;
1624 shift = 3;
1625 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1626 pcrel = 1;
1627 info->insn_type = dis_dref;
1628 info->data_size = 8;
1629 break;
1630 case 'E':
1631 nbits = 5;
1632 shift = 2;
1633 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1634 pcrel = 1;
1635 break;
1636 default:
1637 abort ();
1638 }
1639
1640 if (! use_extend)
1641 {
1642 if (signedp && immed >= (1 << (nbits - 1)))
1643 immed -= 1 << nbits;
1644 immed <<= shift;
1645 if ((type == '<' || type == '>' || type == '[' || type == ']')
1646 && immed == 0)
1647 immed = 8;
1648 }
1649 else
1650 {
1651 if (extbits == 16)
1652 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1653 else if (extbits == 15)
1654 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1655 else
1656 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1657 immed &= (1 << extbits) - 1;
1658 if (! extu && immed >= (1 << (extbits - 1)))
1659 immed -= 1 << extbits;
1660 }
1661
1662 if (! pcrel)
1663 (*info->fprintf_func) (info->stream, "%d", immed);
1664 else
1665 {
1666 bfd_vma baseaddr;
252b5132
RH		 1667
1668 if (branch)
1669 {
1670 immed *= 2;
1671 baseaddr = memaddr + 2;
1672 }
1673 else if (use_extend)
1674 baseaddr = memaddr - 2;
1675 else
1676 {
1677 int status;
1678 bfd_byte buffer[2];
1679
1680 baseaddr = memaddr;
1681
1682 /* If this instruction is in the delay slot of a jr
1683 instruction, the base address is the address of the
1684 jr instruction. If it is in the delay slot of jalr
1685 instruction, the base address is the address of the
1686 jalr instruction. This test is unreliable: we have
1687 no way of knowing whether the previous word is
1688 instruction or data. */
1689 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1690 info);
1691 if (status == 0
1692 && (((info->endian == BFD_ENDIAN_BIG
1693 ? bfd_getb16 (buffer)
1694 : bfd_getl16 (buffer))
1695 & 0xf800) == 0x1800))
1696 baseaddr = memaddr - 4;
1697 else
1698 {
1699 status = (*info->read_memory_func) (memaddr - 2, buffer,
1700 2, info);
1701 if (status == 0
1702 && (((info->endian == BFD_ENDIAN_BIG
1703 ? bfd_getb16 (buffer)
1704 : bfd_getl16 (buffer))
1705 & 0xf81f) == 0xe800))
1706 baseaddr = memaddr - 2;
1707 }
1708 }
9bb28706 1709 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
022fac6d
TS		 1710 if (pcrel && branch
1711 && info->flavour == bfd_target_unknown_flavour)
1712 /* For gdb disassembler, maintain odd address. */
1713 info->target |= 1;
9bb28706 1714 (*info->print_address_func) (info->target, info);
252b5132
RH		 1715 }
1716 }
1717 break;
1718
1719 case 'a':
022fac6d
TS		 1720 {
1721 int jalx = l & 0x400;
1722
1723 if (! use_extend)
1724 extend = 0;
1725 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1726 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1727 /* For gdb disassembler, maintain odd address. */
1728 l |= 1;
1729 }
9bb28706
CD		 1730 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1731 (*info->print_address_func) (info->target, info);
252b5132 1732 info->insn_type = dis_jsr;
252b5132
RH		 1733 info->branch_delay_insns = 1;
1734 break;
1735
1736 case 'l':
1737 case 'L':
1738 {
1739 int need_comma, amask, smask;
1740
1741 need_comma = 0;
1742
1743 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1744
1745 amask = (l >> 3) & 7;
1746
1747 if (amask > 0 && amask < 5)
1748 {
640c0ccd 1749 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
252b5132 1750 if (amask > 1)
aa5f19f2 1751 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1752 mips_gpr_names[amask + 3]);
252b5132
RH		 1753 need_comma = 1;
1754 }
1755
1756 smask = (l >> 1) & 3;
1757 if (smask == 3)
1758 {
1759 (*info->fprintf_func) (info->stream, "%s??",
1760 need_comma ? "," : "");
1761 need_comma = 1;
1762 }
1763 else if (smask > 0)
1764 {
aa5f19f2 1765 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1766 need_comma ? "," : "",
640c0ccd 1767 mips_gpr_names[16]);
252b5132 1768 if (smask > 1)
aa5f19f2 1769 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1770 mips_gpr_names[smask + 15]);
252b5132
RH		 1771 need_comma = 1;
1772 }
1773
1774 if (l & 1)
1775 {
aa5f19f2 1776 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1777 need_comma ? "," : "",
640c0ccd 1778 mips_gpr_names[31]);
252b5132
RH		 1779 need_comma = 1;
1780 }
1781
1782 if (amask == 5 || amask == 6)
1783 {
1784 (*info->fprintf_func) (info->stream, "%s$f0",
1785 need_comma ? "," : "");
1786 if (amask == 6)
1787 (*info->fprintf_func) (info->stream, "-$f1");
1788 }
1789 }
1790 break;
1791
0499d65b
TS		 1792 case 'm':
1793 case 'M':
1794 /* MIPS16e save/restore. */
1795 {
1796 int need_comma = 0;
1797 int amask, args, statics;
1798 int nsreg, smask;
1799 int framesz;
1800 int i, j;
1801
1802 l = l & 0x7f;
1803 if (use_extend)
1804 l |= extend << 16;
1805
1806 amask = (l >> 16) & 0xf;
1807 if (amask == MIPS16_ALL_ARGS)
1808 {
1809 args = 4;
1810 statics = 0;
1811 }
1812 else if (amask == MIPS16_ALL_STATICS)
1813 {
1814 args = 0;
1815 statics = 4;
1816 }
1817 else
1818 {
1819 args = amask >> 2;
1820 statics = amask & 3;
1821 }
1822
1823 if (args > 0) {
1824 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1825 if (args > 1)
1826 (*info->fprintf_func) (info->stream, "-%s",
1827 mips_gpr_names[4 + args - 1]);
1828 need_comma = 1;
1829 }
1830
1831 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1832 if (framesz == 0 && !use_extend)
1833 framesz = 128;
1834
1835 (*info->fprintf_func) (info->stream, "%s%d",
1836 need_comma ? "," : "",
1837 framesz);
1838
1839 if (l & 0x40) /* $ra */
1840 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1841
1842 nsreg = (l >> 24) & 0x7;
1843 smask = 0;
1844 if (l & 0x20) /* $s0 */
1845 smask |= 1 << 0;
1846 if (l & 0x10) /* $s1 */
1847 smask |= 1 << 1;
1848 if (nsreg > 0) /* $s2-$s8 */
1849 smask |= ((1 << nsreg) - 1) << 2;
1850
1851 /* Find first set static reg bit. */
1852 for (i = 0; i < 9; i++)
1853 {
1854 if (smask & (1 << i))
1855 {
1856 (*info->fprintf_func) (info->stream, ",%s",
1857 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1858 /* Skip over string of set bits. */
1859 for (j = i; smask & (2 << j); j++)
1860 continue;
1861 if (j > i)
1862 (*info->fprintf_func) (info->stream, "-%s",
1863 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1864 i = j + 1;
1865 }
1866 }
1867
1868 /* Statics $ax - $a3. */
1869 if (statics == 1)
1870 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1871 else if (statics > 0)
1872 (*info->fprintf_func) (info->stream, ",%s-%s",
1873 mips_gpr_names[7 - statics + 1],
1874 mips_gpr_names[7]);
1875 }
1876 break;
1877
252b5132 1878 default:
aa5f19f2
NC		 1879 /* xgettext:c-format */
1880 (*info->fprintf_func)
1881 (info->stream,
1882 _("# internal disassembler error, unrecognised modifier (%c)"),
1883 type);
252b5132
RH		 1884 abort ();
1885 }
1886}
640c0ccd 1887
47b0e7ad
NC		 1888/* Disassemble mips16 instructions. */
1889
1890static int
1891print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1892{
1893 int status;
1894 bfd_byte buffer[2];
1895 int length;
1896 int insn;
1897 bfd_boolean use_extend;
1898 int extend = 0;
1899 const struct mips_opcode *op, *opend;
1900
1901 info->bytes_per_chunk = 2;
1902 info->display_endian = info->endian;
1903 info->insn_info_valid = 1;
1904 info->branch_delay_insns = 0;
1905 info->data_size = 0;
1906 info->insn_type = dis_nonbranch;
1907 info->target = 0;
1908 info->target2 = 0;
1909
1910 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1911 if (status != 0)
1912 {
1913 (*info->memory_error_func) (status, memaddr, info);
1914 return -1;
1915 }
1916
1917 length = 2;
1918
1919 if (info->endian == BFD_ENDIAN_BIG)
1920 insn = bfd_getb16 (buffer);
1921 else
1922 insn = bfd_getl16 (buffer);
1923
1924 /* Handle the extend opcode specially. */
1925 use_extend = FALSE;
1926 if ((insn & 0xf800) == 0xf000)
1927 {
1928 use_extend = TRUE;
1929 extend = insn & 0x7ff;
1930
1931 memaddr += 2;
1932
1933 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1934 if (status != 0)
1935 {
1936 (*info->fprintf_func) (info->stream, "extend 0x%x",
1937 (unsigned int) extend);
1938 (*info->memory_error_func) (status, memaddr, info);
1939 return -1;
1940 }
1941
1942 if (info->endian == BFD_ENDIAN_BIG)
1943 insn = bfd_getb16 (buffer);
1944 else
1945 insn = bfd_getl16 (buffer);
1946
1947 /* Check for an extend opcode followed by an extend opcode. */
1948 if ((insn & 0xf800) == 0xf000)
1949 {
1950 (*info->fprintf_func) (info->stream, "extend 0x%x",
1951 (unsigned int) extend);
1952 info->insn_type = dis_noninsn;
1953 return length;
1954 }
1955
1956 length += 2;
1957 }
1958
1959 /* FIXME: Should probably use a hash table on the major opcode here. */
1960
1961 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1962 for (op = mips16_opcodes; op < opend; op++)
1963 {
1964 if (op->pinfo != INSN_MACRO
1965 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1966 && (insn & op->mask) == op->match)
1967 {
1968 const char *s;
1969
1970 if (strchr (op->args, 'a') != NULL)
1971 {
1972 if (use_extend)
1973 {
1974 (*info->fprintf_func) (info->stream, "extend 0x%x",
1975 (unsigned int) extend);
1976 info->insn_type = dis_noninsn;
1977 return length - 2;
1978 }
1979
1980 use_extend = FALSE;
1981
1982 memaddr += 2;
1983
1984 status = (*info->read_memory_func) (memaddr, buffer, 2,
1985 info);
1986 if (status == 0)
1987 {
1988 use_extend = TRUE;
1989 if (info->endian == BFD_ENDIAN_BIG)
1990 extend = bfd_getb16 (buffer);
1991 else
1992 extend = bfd_getl16 (buffer);
1993 length += 2;
1994 }
1995 }
1996
1997 (*info->fprintf_func) (info->stream, "%s", op->name);
1998 if (op->args[0] != '\0')
1999 (*info->fprintf_func) (info->stream, "\t");
2000
2001 for (s = op->args; *s != '\0'; s++)
2002 {
2003 if (*s == ','
2004 && s[1] == 'w'
2005 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2006 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2007 {
2008 /* Skip the register and the comma. */
2009 ++s;
2010 continue;
2011 }
2012 if (*s == ','
2013 && s[1] == 'v'
2014 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2015 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2016 {
2017 /* Skip the register and the comma. */
2018 ++s;
2019 continue;
2020 }
2021 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2022 info);
2023 }
2024
2025 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2026 {
2027 info->branch_delay_insns = 1;
2028 if (info->insn_type != dis_jsr)
2029 info->insn_type = dis_branch;
2030 }
2031
2032 return length;
2033 }
2034 }
2035
2036 if (use_extend)
2037 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2038 (*info->fprintf_func) (info->stream, "0x%x", insn);
2039 info->insn_type = dis_noninsn;
2040
2041 return length;
2042}
2043
2044/* In an environment where we do not know the symbol type of the
2045 instruction we are forced to assume that the low order bit of the
2046 instructions' address may mark it as a mips16 instruction. If we
2047 are single stepping, or the pc is within the disassembled function,
2048 this works. Otherwise, we need a clue. Sometimes. */
2049
2050static int
2051_print_insn_mips (bfd_vma memaddr,
2052 struct disassemble_info *info,
2053 enum bfd_endian endianness)
2054{
2055 bfd_byte buffer[INSNLEN];
2056 int status;
2057
2058 set_default_mips_dis_options (info);
2059 parse_mips_dis_options (info->disassembler_options);
2060
2061#if 1
2062 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2063 /* Only a few tools will work this way. */
2064 if (memaddr & 0x01)
2065 return print_insn_mips16 (memaddr, info);
2066#endif
2067
2068#if SYMTAB_AVAILABLE
2069 if (info->mach == bfd_mach_mips16
6ba2a415
RS		 2070 || (info->symbols != NULL
2071 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
30c09090
RS		 2072 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2073 ->internal_elf_sym.st_other)))
47b0e7ad
NC		 2074 return print_insn_mips16 (memaddr, info);
2075#endif
2076
2077 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2078 if (status == 0)
2079 {
2080 unsigned long insn;
2081
2082 if (endianness == BFD_ENDIAN_BIG)
2083 insn = (unsigned long) bfd_getb32 (buffer);
2084 else
2085 insn = (unsigned long) bfd_getl32 (buffer);
2086
2087 return print_insn_mips (memaddr, insn, info);
2088 }
2089 else
2090 {
2091 (*info->memory_error_func) (status, memaddr, info);
2092 return -1;
2093 }
2094}
2095
2096int
2097print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2098{
2099 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2100}
2101
2102int
2103print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2104{
2105 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2106}
2107\f
640c0ccd 2108void
47b0e7ad 2109print_mips_disassembler_options (FILE *stream)
640c0ccd 2110{
4a9a3c54 2111 unsigned int i;
640c0ccd
CD		 2112
2113 fprintf (stream, _("\n\
2114The following MIPS specific disassembler options are supported for use\n\
2115with the -M switch (multiple options should be separated by commas):\n"));
2116
2117 fprintf (stream, _("\n\
2118 gpr-names=ABI Print GPR names according to specified ABI.\n\
2119 Default: based on binary being disassembled.\n"));
2120
2121 fprintf (stream, _("\n\
2122 fpr-names=ABI Print FPR names according to specified ABI.\n\
2123 Default: numeric.\n"));
2124
2125 fprintf (stream, _("\n\
2126 cp0-names=ARCH Print CP0 register names according to\n\
2127 specified architecture.\n\
2128 Default: based on binary being disassembled.\n"));
2129
af7ee8bf
CD		 2130 fprintf (stream, _("\n\
2131 hwr-names=ARCH Print HWR names according to specified \n\
2132 architecture.\n\
2133 Default: based on binary being disassembled.\n"));
2134
640c0ccd
CD		 2135 fprintf (stream, _("\n\
2136 reg-names=ABI Print GPR and FPR names according to\n\
2137 specified ABI.\n"));
2138
2139 fprintf (stream, _("\n\
af7ee8bf 2140 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 2141 specified architecture.\n"));
2142
2143 fprintf (stream, _("\n\
2144 For the options above, the following values are supported for \"ABI\":\n\
2145 "));
4a9a3c54 2146 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
640c0ccd
CD		 2147 fprintf (stream, " %s", mips_abi_choices[i].name);
2148 fprintf (stream, _("\n"));
2149
2150 fprintf (stream, _("\n\
2151 For the options above, The following values are supported for \"ARCH\":\n\
2152 "));
4a9a3c54 2153 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
640c0ccd
CD		 2154 if (*mips_arch_choices[i].name != '\0')
2155 fprintf (stream, " %s", mips_arch_choices[i].name);
2156 fprintf (stream, _("\n"));
2157
2158 fprintf (stream, _("\n"));
2159}
GDB Binutils - Deliverables
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