Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print mips instructions for GDB, the GNU debugger, or for objdump. |
060d22b0 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
aa820537 | 3 | 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009 |
73da6b6b | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). |
6 | ||
9b201bb5 | 7 | This file is part of the GNU opcodes library. |
252b5132 | 8 | |
9b201bb5 | 9 | This library is free software; you can redistribute it and/or modify |
47b0e7ad | 10 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
11 | the Free Software Foundation; either version 3, or (at your option) |
12 | any later version. | |
252b5132 | 13 | |
9b201bb5 NC |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
252b5132 | 18 | |
47b0e7ad NC |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, | |
22 | MA 02110-1301, USA. */ | |
252b5132 | 23 | |
252b5132 RH |
24 | #include "sysdep.h" |
25 | #include "dis-asm.h" | |
640c0ccd | 26 | #include "libiberty.h" |
252b5132 RH |
27 | #include "opcode/mips.h" |
28 | #include "opintl.h" | |
29 | ||
30 | /* FIXME: These are needed to figure out if the code is mips16 or | |
31 | not. The low bit of the address is often a good indicator. No | |
32 | symbol table is available when this code runs out in an embedded | |
7f6621cd | 33 | system as when it is used for disassembler support in a monitor. */ |
252b5132 RH |
34 | |
35 | #if !defined(EMBEDDED_ENV) | |
36 | #define SYMTAB_AVAILABLE 1 | |
37 | #include "elf-bfd.h" | |
38 | #include "elf/mips.h" | |
39 | #endif | |
40 | ||
aa5f19f2 NC |
41 | /* Mips instructions are at maximum this many bytes long. */ |
42 | #define INSNLEN 4 | |
43 | ||
252b5132 | 44 | \f |
aa5f19f2 | 45 | /* FIXME: These should be shared with gdb somehow. */ |
252b5132 | 46 | |
47b0e7ad NC |
47 | struct mips_cp0sel_name |
48 | { | |
49 | unsigned int cp0reg; | |
50 | unsigned int sel; | |
51 | const char * const name; | |
bbcc0807 CD |
52 | }; |
53 | ||
654c225a TS |
54 | /* The mips16 registers. */ |
55 | static const unsigned int mips16_to_32_reg_map[] = | |
47b0e7ad | 56 | { |
654c225a | 57 | 16, 17, 2, 3, 4, 5, 6, 7 |
252b5132 | 58 | }; |
fb48caed | 59 | |
654c225a TS |
60 | #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] |
61 | ||
62 | ||
47b0e7ad NC |
63 | static const char * const mips_gpr_names_numeric[32] = |
64 | { | |
640c0ccd CD |
65 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
66 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
67 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
68 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
aa5f19f2 NC |
69 | }; |
70 | ||
47b0e7ad NC |
71 | static const char * const mips_gpr_names_oldabi[32] = |
72 | { | |
640c0ccd CD |
73 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
74 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
75 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
76 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
aa5f19f2 NC |
77 | }; |
78 | ||
47b0e7ad NC |
79 | static const char * const mips_gpr_names_newabi[32] = |
80 | { | |
640c0ccd | 81 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
0b14f26e | 82 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", |
640c0ccd CD |
83 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
84 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
85 | }; | |
86 | ||
47b0e7ad NC |
87 | static const char * const mips_fpr_names_numeric[32] = |
88 | { | |
640c0ccd CD |
89 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", |
90 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", | |
91 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", | |
92 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" | |
93 | }; | |
94 | ||
47b0e7ad NC |
95 | static const char * const mips_fpr_names_32[32] = |
96 | { | |
640c0ccd CD |
97 | "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", |
98 | "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", | |
99 | "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", | |
100 | "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" | |
101 | }; | |
102 | ||
47b0e7ad NC |
103 | static const char * const mips_fpr_names_n32[32] = |
104 | { | |
640c0ccd CD |
105 | "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", |
106 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
107 | "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", | |
108 | "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" | |
109 | }; | |
110 | ||
47b0e7ad NC |
111 | static const char * const mips_fpr_names_64[32] = |
112 | { | |
640c0ccd CD |
113 | "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", |
114 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
115 | "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", | |
116 | "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" | |
117 | }; | |
118 | ||
47b0e7ad NC |
119 | static const char * const mips_cp0_names_numeric[32] = |
120 | { | |
640c0ccd CD |
121 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
122 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
123 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
124 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
125 | }; | |
126 | ||
f409fd1e MR |
127 | static const char * const mips_cp0_names_r3000[32] = |
128 | { | |
129 | "c0_index", "c0_random", "c0_entrylo", "$3", | |
130 | "c0_context", "$5", "$6", "$7", | |
131 | "c0_badvaddr", "$9", "c0_entryhi", "$11", | |
132 | "c0_sr", "c0_cause", "c0_epc", "c0_prid", | |
133 | "$16", "$17", "$18", "$19", | |
134 | "$20", "$21", "$22", "$23", | |
135 | "$24", "$25", "$26", "$27", | |
136 | "$28", "$29", "$30", "$31", | |
137 | }; | |
138 | ||
139 | static const char * const mips_cp0_names_r4000[32] = | |
140 | { | |
141 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", | |
142 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
143 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
144 | "c0_sr", "c0_cause", "c0_epc", "c0_prid", | |
145 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
146 | "c0_xcontext", "$21", "$22", "$23", | |
147 | "$24", "$25", "c0_ecc", "c0_cacheerr", | |
148 | "c0_taglo", "c0_taghi", "c0_errorepc", "$31", | |
149 | }; | |
150 | ||
47b0e7ad NC |
151 | static const char * const mips_cp0_names_mips3264[32] = |
152 | { | |
640c0ccd CD |
153 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
154 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
155 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
156 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
157 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
158 | "c0_xcontext", "$21", "$22", "c0_debug", | |
159 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", | |
160 | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", | |
161 | }; | |
162 | ||
47b0e7ad NC |
163 | static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = |
164 | { | |
bbcc0807 CD |
165 | { 16, 1, "c0_config1" }, |
166 | { 16, 2, "c0_config2" }, | |
167 | { 16, 3, "c0_config3" }, | |
168 | { 18, 1, "c0_watchlo,1" }, | |
169 | { 18, 2, "c0_watchlo,2" }, | |
170 | { 18, 3, "c0_watchlo,3" }, | |
171 | { 18, 4, "c0_watchlo,4" }, | |
172 | { 18, 5, "c0_watchlo,5" }, | |
173 | { 18, 6, "c0_watchlo,6" }, | |
174 | { 18, 7, "c0_watchlo,7" }, | |
175 | { 19, 1, "c0_watchhi,1" }, | |
176 | { 19, 2, "c0_watchhi,2" }, | |
177 | { 19, 3, "c0_watchhi,3" }, | |
178 | { 19, 4, "c0_watchhi,4" }, | |
179 | { 19, 5, "c0_watchhi,5" }, | |
180 | { 19, 6, "c0_watchhi,6" }, | |
181 | { 19, 7, "c0_watchhi,7" }, | |
182 | { 25, 1, "c0_perfcnt,1" }, | |
183 | { 25, 2, "c0_perfcnt,2" }, | |
184 | { 25, 3, "c0_perfcnt,3" }, | |
185 | { 25, 4, "c0_perfcnt,4" }, | |
186 | { 25, 5, "c0_perfcnt,5" }, | |
187 | { 25, 6, "c0_perfcnt,6" }, | |
188 | { 25, 7, "c0_perfcnt,7" }, | |
189 | { 27, 1, "c0_cacheerr,1" }, | |
190 | { 27, 2, "c0_cacheerr,2" }, | |
191 | { 27, 3, "c0_cacheerr,3" }, | |
192 | { 28, 1, "c0_datalo" }, | |
193 | { 29, 1, "c0_datahi" } | |
194 | }; | |
195 | ||
47b0e7ad NC |
196 | static const char * const mips_cp0_names_mips3264r2[32] = |
197 | { | |
af7ee8bf CD |
198 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
199 | "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", | |
200 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
201 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
202 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
203 | "c0_xcontext", "$21", "$22", "c0_debug", | |
204 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", | |
205 | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", | |
206 | }; | |
207 | ||
47b0e7ad NC |
208 | static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = |
209 | { | |
bbcc0807 | 210 | { 4, 1, "c0_contextconfig" }, |
59c455b3 TS |
211 | { 0, 1, "c0_mvpcontrol" }, |
212 | { 0, 2, "c0_mvpconf0" }, | |
213 | { 0, 3, "c0_mvpconf1" }, | |
214 | { 1, 1, "c0_vpecontrol" }, | |
215 | { 1, 2, "c0_vpeconf0" }, | |
216 | { 1, 3, "c0_vpeconf1" }, | |
217 | { 1, 4, "c0_yqmask" }, | |
218 | { 1, 5, "c0_vpeschedule" }, | |
219 | { 1, 6, "c0_vpeschefback" }, | |
220 | { 2, 1, "c0_tcstatus" }, | |
221 | { 2, 2, "c0_tcbind" }, | |
222 | { 2, 3, "c0_tcrestart" }, | |
223 | { 2, 4, "c0_tchalt" }, | |
224 | { 2, 5, "c0_tccontext" }, | |
225 | { 2, 6, "c0_tcschedule" }, | |
226 | { 2, 7, "c0_tcschefback" }, | |
bbcc0807 | 227 | { 5, 1, "c0_pagegrain" }, |
59c455b3 TS |
228 | { 6, 1, "c0_srsconf0" }, |
229 | { 6, 2, "c0_srsconf1" }, | |
230 | { 6, 3, "c0_srsconf2" }, | |
231 | { 6, 4, "c0_srsconf3" }, | |
232 | { 6, 5, "c0_srsconf4" }, | |
bbcc0807 CD |
233 | { 12, 1, "c0_intctl" }, |
234 | { 12, 2, "c0_srsctl" }, | |
235 | { 12, 3, "c0_srsmap" }, | |
236 | { 15, 1, "c0_ebase" }, | |
237 | { 16, 1, "c0_config1" }, | |
238 | { 16, 2, "c0_config2" }, | |
239 | { 16, 3, "c0_config3" }, | |
240 | { 18, 1, "c0_watchlo,1" }, | |
241 | { 18, 2, "c0_watchlo,2" }, | |
242 | { 18, 3, "c0_watchlo,3" }, | |
243 | { 18, 4, "c0_watchlo,4" }, | |
244 | { 18, 5, "c0_watchlo,5" }, | |
245 | { 18, 6, "c0_watchlo,6" }, | |
246 | { 18, 7, "c0_watchlo,7" }, | |
247 | { 19, 1, "c0_watchhi,1" }, | |
248 | { 19, 2, "c0_watchhi,2" }, | |
249 | { 19, 3, "c0_watchhi,3" }, | |
250 | { 19, 4, "c0_watchhi,4" }, | |
251 | { 19, 5, "c0_watchhi,5" }, | |
252 | { 19, 6, "c0_watchhi,6" }, | |
253 | { 19, 7, "c0_watchhi,7" }, | |
254 | { 23, 1, "c0_tracecontrol" }, | |
255 | { 23, 2, "c0_tracecontrol2" }, | |
256 | { 23, 3, "c0_usertracedata" }, | |
257 | { 23, 4, "c0_tracebpc" }, | |
258 | { 25, 1, "c0_perfcnt,1" }, | |
259 | { 25, 2, "c0_perfcnt,2" }, | |
260 | { 25, 3, "c0_perfcnt,3" }, | |
261 | { 25, 4, "c0_perfcnt,4" }, | |
262 | { 25, 5, "c0_perfcnt,5" }, | |
263 | { 25, 6, "c0_perfcnt,6" }, | |
264 | { 25, 7, "c0_perfcnt,7" }, | |
265 | { 27, 1, "c0_cacheerr,1" }, | |
266 | { 27, 2, "c0_cacheerr,2" }, | |
267 | { 27, 3, "c0_cacheerr,3" }, | |
268 | { 28, 1, "c0_datalo" }, | |
269 | { 28, 2, "c0_taglo1" }, | |
270 | { 28, 3, "c0_datalo1" }, | |
271 | { 28, 4, "c0_taglo2" }, | |
272 | { 28, 5, "c0_datalo2" }, | |
273 | { 28, 6, "c0_taglo3" }, | |
274 | { 28, 7, "c0_datalo3" }, | |
275 | { 29, 1, "c0_datahi" }, | |
276 | { 29, 2, "c0_taghi1" }, | |
277 | { 29, 3, "c0_datahi1" }, | |
278 | { 29, 4, "c0_taghi2" }, | |
279 | { 29, 5, "c0_datahi2" }, | |
280 | { 29, 6, "c0_taghi3" }, | |
281 | { 29, 7, "c0_datahi3" }, | |
282 | }; | |
283 | ||
640c0ccd | 284 | /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ |
47b0e7ad NC |
285 | static const char * const mips_cp0_names_sb1[32] = |
286 | { | |
640c0ccd CD |
287 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
288 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
289 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
290 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
291 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
292 | "c0_xcontext", "$21", "$22", "c0_debug", | |
293 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", | |
294 | "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", | |
295 | }; | |
296 | ||
47b0e7ad NC |
297 | static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = |
298 | { | |
bbcc0807 CD |
299 | { 16, 1, "c0_config1" }, |
300 | { 18, 1, "c0_watchlo,1" }, | |
301 | { 19, 1, "c0_watchhi,1" }, | |
302 | { 22, 0, "c0_perftrace" }, | |
303 | { 23, 3, "c0_edebug" }, | |
304 | { 25, 1, "c0_perfcnt,1" }, | |
305 | { 25, 2, "c0_perfcnt,2" }, | |
306 | { 25, 3, "c0_perfcnt,3" }, | |
307 | { 25, 4, "c0_perfcnt,4" }, | |
308 | { 25, 5, "c0_perfcnt,5" }, | |
309 | { 25, 6, "c0_perfcnt,6" }, | |
310 | { 25, 7, "c0_perfcnt,7" }, | |
311 | { 26, 1, "c0_buserr_pa" }, | |
312 | { 27, 1, "c0_cacheerr_d" }, | |
313 | { 27, 3, "c0_cacheerr_d_pa" }, | |
314 | { 28, 1, "c0_datalo_i" }, | |
315 | { 28, 2, "c0_taglo_d" }, | |
316 | { 28, 3, "c0_datalo_d" }, | |
317 | { 29, 1, "c0_datahi_i" }, | |
318 | { 29, 2, "c0_taghi_d" }, | |
319 | { 29, 3, "c0_datahi_d" }, | |
320 | }; | |
321 | ||
52b6b6b9 JM |
322 | /* Xlr cop0 register names. */ |
323 | static const char * const mips_cp0_names_xlr[32] = { | |
324 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", | |
325 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
326 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
327 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
328 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
329 | "c0_xcontext", "$21", "$22", "c0_debug", | |
330 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", | |
331 | "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", | |
332 | }; | |
333 | ||
334 | /* XLR's CP0 Select Registers. */ | |
335 | ||
336 | static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { | |
337 | { 9, 6, "c0_extintreq" }, | |
338 | { 9, 7, "c0_extintmask" }, | |
339 | { 15, 1, "c0_ebase" }, | |
340 | { 16, 1, "c0_config1" }, | |
341 | { 16, 2, "c0_config2" }, | |
342 | { 16, 3, "c0_config3" }, | |
343 | { 16, 7, "c0_procid2" }, | |
344 | { 18, 1, "c0_watchlo,1" }, | |
345 | { 18, 2, "c0_watchlo,2" }, | |
346 | { 18, 3, "c0_watchlo,3" }, | |
347 | { 18, 4, "c0_watchlo,4" }, | |
348 | { 18, 5, "c0_watchlo,5" }, | |
349 | { 18, 6, "c0_watchlo,6" }, | |
350 | { 18, 7, "c0_watchlo,7" }, | |
351 | { 19, 1, "c0_watchhi,1" }, | |
352 | { 19, 2, "c0_watchhi,2" }, | |
353 | { 19, 3, "c0_watchhi,3" }, | |
354 | { 19, 4, "c0_watchhi,4" }, | |
355 | { 19, 5, "c0_watchhi,5" }, | |
356 | { 19, 6, "c0_watchhi,6" }, | |
357 | { 19, 7, "c0_watchhi,7" }, | |
358 | { 25, 1, "c0_perfcnt,1" }, | |
359 | { 25, 2, "c0_perfcnt,2" }, | |
360 | { 25, 3, "c0_perfcnt,3" }, | |
361 | { 25, 4, "c0_perfcnt,4" }, | |
362 | { 25, 5, "c0_perfcnt,5" }, | |
363 | { 25, 6, "c0_perfcnt,6" }, | |
364 | { 25, 7, "c0_perfcnt,7" }, | |
365 | { 27, 1, "c0_cacheerr,1" }, | |
366 | { 27, 2, "c0_cacheerr,2" }, | |
367 | { 27, 3, "c0_cacheerr,3" }, | |
368 | { 28, 1, "c0_datalo" }, | |
369 | { 29, 1, "c0_datahi" } | |
370 | }; | |
371 | ||
47b0e7ad NC |
372 | static const char * const mips_hwr_names_numeric[32] = |
373 | { | |
af7ee8bf CD |
374 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
375 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
376 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
377 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
378 | }; | |
379 | ||
47b0e7ad NC |
380 | static const char * const mips_hwr_names_mips3264r2[32] = |
381 | { | |
af7ee8bf CD |
382 | "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", |
383 | "$4", "$5", "$6", "$7", | |
384 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
385 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
386 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
387 | }; | |
388 | ||
47b0e7ad NC |
389 | struct mips_abi_choice |
390 | { | |
391 | const char * name; | |
640c0ccd CD |
392 | const char * const *gpr_names; |
393 | const char * const *fpr_names; | |
394 | }; | |
395 | ||
47b0e7ad NC |
396 | struct mips_abi_choice mips_abi_choices[] = |
397 | { | |
640c0ccd CD |
398 | { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, |
399 | { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, | |
400 | { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, | |
401 | { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, | |
402 | }; | |
403 | ||
47b0e7ad NC |
404 | struct mips_arch_choice |
405 | { | |
640c0ccd CD |
406 | const char *name; |
407 | int bfd_mach_valid; | |
408 | unsigned long bfd_mach; | |
409 | int processor; | |
410 | int isa; | |
411 | const char * const *cp0_names; | |
bbcc0807 CD |
412 | const struct mips_cp0sel_name *cp0sel_names; |
413 | unsigned int cp0sel_names_len; | |
af7ee8bf | 414 | const char * const *hwr_names; |
640c0ccd CD |
415 | }; |
416 | ||
47b0e7ad NC |
417 | const struct mips_arch_choice mips_arch_choices[] = |
418 | { | |
640c0ccd | 419 | { "numeric", 0, 0, 0, 0, |
bbcc0807 CD |
420 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
421 | ||
640c0ccd | 422 | { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, |
f409fd1e | 423 | mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 424 | { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, |
bbcc0807 | 425 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 426 | { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, |
f409fd1e | 427 | mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 428 | { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, |
bbcc0807 | 429 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 430 | { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, |
bbcc0807 | 431 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 432 | { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, |
bbcc0807 | 433 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 434 | { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, |
bbcc0807 | 435 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 436 | { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, |
bbcc0807 | 437 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 438 | { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, |
f409fd1e | 439 | mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 440 | { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, |
bbcc0807 | 441 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 442 | { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, |
bbcc0807 | 443 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 444 | { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, |
bbcc0807 | 445 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 446 | { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, |
bbcc0807 | 447 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 448 | { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, |
bbcc0807 | 449 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 450 | { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, |
bbcc0807 | 451 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
5a7ea749 RS |
452 | { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, |
453 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
454 | { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, | |
455 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
640c0ccd | 456 | { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, |
bbcc0807 | 457 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 458 | { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, |
bbcc0807 | 459 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd | 460 | { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, |
bbcc0807 | 461 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
3aa3176b TS |
462 | { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, |
463 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
464 | { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, | |
465 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
640c0ccd | 466 | { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, |
bbcc0807 CD |
467 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
468 | ||
640c0ccd CD |
469 | /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. |
470 | Note that MIPS-3D and MDMX are not applicable to MIPS32. (See | |
471 | _MIPS32 Architecture For Programmers Volume I: Introduction to the | |
472 | MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), | |
473 | page 1. */ | |
474 | { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, | |
f79e2745 | 475 | ISA_MIPS32 | INSN_SMARTMIPS, |
bbcc0807 CD |
476 | mips_cp0_names_mips3264, |
477 | mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), | |
478 | mips_hwr_names_numeric }, | |
479 | ||
af7ee8bf | 480 | { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, |
f79e2745 | 481 | (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 |
8b082fb1 | 482 | | INSN_MIPS3D | INSN_MT), |
bbcc0807 CD |
483 | mips_cp0_names_mips3264r2, |
484 | mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), | |
485 | mips_hwr_names_mips3264r2 }, | |
486 | ||
640c0ccd CD |
487 | /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ |
488 | { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, | |
f79e2745 | 489 | ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX, |
bbcc0807 CD |
490 | mips_cp0_names_mips3264, |
491 | mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), | |
492 | mips_hwr_names_numeric }, | |
493 | ||
5f74bc13 | 494 | { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, |
f79e2745 | 495 | (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 |
8b082fb1 | 496 | | INSN_DSP64 | INSN_MT | INSN_MDMX), |
5f74bc13 CD |
497 | mips_cp0_names_mips3264r2, |
498 | mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), | |
499 | mips_hwr_names_mips3264r2 }, | |
500 | ||
640c0ccd CD |
501 | { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, |
502 | ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, | |
bbcc0807 CD |
503 | mips_cp0_names_sb1, |
504 | mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), | |
505 | mips_hwr_names_numeric }, | |
640c0ccd | 506 | |
350cc38d MS |
507 | { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, |
508 | ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, | |
509 | NULL, 0, mips_hwr_names_numeric }, | |
510 | ||
511 | { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, | |
512 | ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, | |
513 | NULL, 0, mips_hwr_names_numeric }, | |
514 | ||
57b592a3 AN |
515 | { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, |
516 | ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0, | |
517 | mips_hwr_names_numeric }, | |
518 | ||
52b6b6b9 JM |
519 | { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, |
520 | ISA_MIPS64 | INSN_XLR, | |
521 | mips_cp0_names_xlr, | |
522 | mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), | |
523 | mips_hwr_names_numeric }, | |
524 | ||
640c0ccd CD |
525 | /* This entry, mips16, is here only for ISA/processor selection; do |
526 | not print its name. */ | |
f79e2745 | 527 | { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, |
bbcc0807 | 528 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
640c0ccd CD |
529 | }; |
530 | ||
531 | /* ISA and processor type to disassemble for, and register names to use. | |
532 | set_default_mips_dis_options and parse_mips_dis_options fill in these | |
533 | values. */ | |
534 | static int mips_processor; | |
535 | static int mips_isa; | |
536 | static const char * const *mips_gpr_names; | |
537 | static const char * const *mips_fpr_names; | |
538 | static const char * const *mips_cp0_names; | |
bbcc0807 CD |
539 | static const struct mips_cp0sel_name *mips_cp0sel_names; |
540 | static int mips_cp0sel_names_len; | |
af7ee8bf | 541 | static const char * const *mips_hwr_names; |
640c0ccd | 542 | |
986e18a5 | 543 | /* Other options */ |
47b0e7ad | 544 | static int no_aliases; /* If set disassemble as most general inst. */ |
640c0ccd CD |
545 | \f |
546 | static const struct mips_abi_choice * | |
47b0e7ad | 547 | choose_abi_by_name (const char *name, unsigned int namelen) |
640c0ccd CD |
548 | { |
549 | const struct mips_abi_choice *c; | |
550 | unsigned int i; | |
551 | ||
552 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) | |
47b0e7ad NC |
553 | if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 |
554 | && strlen (mips_abi_choices[i].name) == namelen) | |
555 | c = &mips_abi_choices[i]; | |
556 | ||
640c0ccd CD |
557 | return c; |
558 | } | |
559 | ||
560 | static const struct mips_arch_choice * | |
47b0e7ad | 561 | choose_arch_by_name (const char *name, unsigned int namelen) |
640c0ccd CD |
562 | { |
563 | const struct mips_arch_choice *c = NULL; | |
564 | unsigned int i; | |
565 | ||
566 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
47b0e7ad NC |
567 | if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 |
568 | && strlen (mips_arch_choices[i].name) == namelen) | |
569 | c = &mips_arch_choices[i]; | |
570 | ||
640c0ccd CD |
571 | return c; |
572 | } | |
573 | ||
574 | static const struct mips_arch_choice * | |
47b0e7ad | 575 | choose_arch_by_number (unsigned long mach) |
640c0ccd CD |
576 | { |
577 | static unsigned long hint_bfd_mach; | |
578 | static const struct mips_arch_choice *hint_arch_choice; | |
579 | const struct mips_arch_choice *c; | |
580 | unsigned int i; | |
581 | ||
582 | /* We optimize this because even if the user specifies no | |
583 | flags, this will be done for every instruction! */ | |
584 | if (hint_bfd_mach == mach | |
585 | && hint_arch_choice != NULL | |
586 | && hint_arch_choice->bfd_mach == hint_bfd_mach) | |
587 | return hint_arch_choice; | |
588 | ||
589 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
590 | { | |
591 | if (mips_arch_choices[i].bfd_mach_valid | |
592 | && mips_arch_choices[i].bfd_mach == mach) | |
593 | { | |
594 | c = &mips_arch_choices[i]; | |
595 | hint_bfd_mach = mach; | |
596 | hint_arch_choice = c; | |
597 | } | |
598 | } | |
599 | return c; | |
600 | } | |
601 | ||
47b0e7ad NC |
602 | /* Check if the object uses NewABI conventions. */ |
603 | ||
604 | static int | |
605 | is_newabi (Elf_Internal_Ehdr *header) | |
606 | { | |
607 | /* There are no old-style ABIs which use 64-bit ELF. */ | |
608 | if (header->e_ident[EI_CLASS] == ELFCLASS64) | |
609 | return 1; | |
610 | ||
611 | /* If a 32-bit ELF file, n32 is a new-style ABI. */ | |
612 | if ((header->e_flags & EF_MIPS_ABI2) != 0) | |
613 | return 1; | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static void | |
619 | set_default_mips_dis_options (struct disassemble_info *info) | |
640c0ccd CD |
620 | { |
621 | const struct mips_arch_choice *chosen_arch; | |
622 | ||
623 | /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, | |
af7ee8bf | 624 | and numeric FPR, CP0 register, and HWR names. */ |
640c0ccd CD |
625 | mips_isa = ISA_MIPS3; |
626 | mips_processor = CPU_R3000; | |
627 | mips_gpr_names = mips_gpr_names_oldabi; | |
628 | mips_fpr_names = mips_fpr_names_numeric; | |
629 | mips_cp0_names = mips_cp0_names_numeric; | |
bbcc0807 CD |
630 | mips_cp0sel_names = NULL; |
631 | mips_cp0sel_names_len = 0; | |
af7ee8bf | 632 | mips_hwr_names = mips_hwr_names_numeric; |
986e18a5 | 633 | no_aliases = 0; |
640c0ccd CD |
634 | |
635 | /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ | |
fec06546 | 636 | if (info->flavour == bfd_target_elf_flavour && info->section != NULL) |
640c0ccd CD |
637 | { |
638 | Elf_Internal_Ehdr *header; | |
639 | ||
fec06546 | 640 | header = elf_elfheader (info->section->owner); |
640c0ccd CD |
641 | if (is_newabi (header)) |
642 | mips_gpr_names = mips_gpr_names_newabi; | |
643 | } | |
644 | ||
645 | /* Set ISA, architecture, and cp0 register names as best we can. */ | |
646 | #if ! SYMTAB_AVAILABLE | |
647 | /* This is running out on a target machine, not in a host tool. | |
648 | FIXME: Where does mips_target_info come from? */ | |
649 | target_processor = mips_target_info.processor; | |
650 | mips_isa = mips_target_info.isa; | |
651 | #else | |
652 | chosen_arch = choose_arch_by_number (info->mach); | |
653 | if (chosen_arch != NULL) | |
654 | { | |
655 | mips_processor = chosen_arch->processor; | |
656 | mips_isa = chosen_arch->isa; | |
bbcc0807 CD |
657 | mips_cp0_names = chosen_arch->cp0_names; |
658 | mips_cp0sel_names = chosen_arch->cp0sel_names; | |
659 | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; | |
660 | mips_hwr_names = chosen_arch->hwr_names; | |
640c0ccd CD |
661 | } |
662 | #endif | |
663 | } | |
664 | ||
47b0e7ad NC |
665 | static void |
666 | parse_mips_dis_option (const char *option, unsigned int len) | |
640c0ccd CD |
667 | { |
668 | unsigned int i, optionlen, vallen; | |
669 | const char *val; | |
670 | const struct mips_abi_choice *chosen_abi; | |
671 | const struct mips_arch_choice *chosen_arch; | |
672 | ||
986e18a5 | 673 | /* Try to match options that are simple flags */ |
0112cd26 | 674 | if (CONST_STRNEQ (option, "no-aliases")) |
986e18a5 FF |
675 | { |
676 | no_aliases = 1; | |
677 | return; | |
678 | } | |
679 | ||
640c0ccd CD |
680 | /* Look for the = that delimits the end of the option name. */ |
681 | for (i = 0; i < len; i++) | |
47b0e7ad NC |
682 | if (option[i] == '=') |
683 | break; | |
684 | ||
640c0ccd CD |
685 | if (i == 0) /* Invalid option: no name before '='. */ |
686 | return; | |
687 | if (i == len) /* Invalid option: no '='. */ | |
688 | return; | |
689 | if (i == (len - 1)) /* Invalid option: no value after '='. */ | |
690 | return; | |
691 | ||
692 | optionlen = i; | |
693 | val = option + (optionlen + 1); | |
694 | vallen = len - (optionlen + 1); | |
695 | ||
47b0e7ad NC |
696 | if (strncmp ("gpr-names", option, optionlen) == 0 |
697 | && strlen ("gpr-names") == optionlen) | |
640c0ccd CD |
698 | { |
699 | chosen_abi = choose_abi_by_name (val, vallen); | |
bbcc0807 | 700 | if (chosen_abi != NULL) |
640c0ccd CD |
701 | mips_gpr_names = chosen_abi->gpr_names; |
702 | return; | |
703 | } | |
704 | ||
47b0e7ad NC |
705 | if (strncmp ("fpr-names", option, optionlen) == 0 |
706 | && strlen ("fpr-names") == optionlen) | |
640c0ccd CD |
707 | { |
708 | chosen_abi = choose_abi_by_name (val, vallen); | |
bbcc0807 | 709 | if (chosen_abi != NULL) |
640c0ccd CD |
710 | mips_fpr_names = chosen_abi->fpr_names; |
711 | return; | |
712 | } | |
713 | ||
47b0e7ad NC |
714 | if (strncmp ("cp0-names", option, optionlen) == 0 |
715 | && strlen ("cp0-names") == optionlen) | |
640c0ccd CD |
716 | { |
717 | chosen_arch = choose_arch_by_name (val, vallen); | |
bbcc0807 CD |
718 | if (chosen_arch != NULL) |
719 | { | |
720 | mips_cp0_names = chosen_arch->cp0_names; | |
721 | mips_cp0sel_names = chosen_arch->cp0sel_names; | |
722 | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; | |
723 | } | |
640c0ccd CD |
724 | return; |
725 | } | |
726 | ||
47b0e7ad NC |
727 | if (strncmp ("hwr-names", option, optionlen) == 0 |
728 | && strlen ("hwr-names") == optionlen) | |
af7ee8bf CD |
729 | { |
730 | chosen_arch = choose_arch_by_name (val, vallen); | |
bbcc0807 | 731 | if (chosen_arch != NULL) |
af7ee8bf CD |
732 | mips_hwr_names = chosen_arch->hwr_names; |
733 | return; | |
734 | } | |
735 | ||
47b0e7ad NC |
736 | if (strncmp ("reg-names", option, optionlen) == 0 |
737 | && strlen ("reg-names") == optionlen) | |
640c0ccd CD |
738 | { |
739 | /* We check both ABI and ARCH here unconditionally, so | |
740 | that "numeric" will do the desirable thing: select | |
741 | numeric register names for all registers. Other than | |
742 | that, a given name probably won't match both. */ | |
743 | chosen_abi = choose_abi_by_name (val, vallen); | |
744 | if (chosen_abi != NULL) | |
745 | { | |
bbcc0807 CD |
746 | mips_gpr_names = chosen_abi->gpr_names; |
747 | mips_fpr_names = chosen_abi->fpr_names; | |
640c0ccd CD |
748 | } |
749 | chosen_arch = choose_arch_by_name (val, vallen); | |
750 | if (chosen_arch != NULL) | |
751 | { | |
bbcc0807 CD |
752 | mips_cp0_names = chosen_arch->cp0_names; |
753 | mips_cp0sel_names = chosen_arch->cp0sel_names; | |
754 | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; | |
755 | mips_hwr_names = chosen_arch->hwr_names; | |
640c0ccd CD |
756 | } |
757 | return; | |
758 | } | |
759 | ||
760 | /* Invalid option. */ | |
761 | } | |
762 | ||
47b0e7ad NC |
763 | static void |
764 | parse_mips_dis_options (const char *options) | |
640c0ccd CD |
765 | { |
766 | const char *option_end; | |
767 | ||
768 | if (options == NULL) | |
769 | return; | |
770 | ||
771 | while (*options != '\0') | |
772 | { | |
773 | /* Skip empty options. */ | |
774 | if (*options == ',') | |
775 | { | |
776 | options++; | |
777 | continue; | |
778 | } | |
779 | ||
780 | /* We know that *options is neither NUL or a comma. */ | |
781 | option_end = options + 1; | |
782 | while (*option_end != ',' && *option_end != '\0') | |
783 | option_end++; | |
784 | ||
785 | parse_mips_dis_option (options, option_end - options); | |
786 | ||
787 | /* Go on to the next one. If option_end points to a comma, it | |
788 | will be skipped above. */ | |
789 | options = option_end; | |
790 | } | |
791 | } | |
792 | ||
bbcc0807 | 793 | static const struct mips_cp0sel_name * |
47b0e7ad NC |
794 | lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, |
795 | unsigned int len, | |
796 | unsigned int cp0reg, | |
797 | unsigned int sel) | |
bbcc0807 CD |
798 | { |
799 | unsigned int i; | |
800 | ||
801 | for (i = 0; i < len; i++) | |
802 | if (names[i].cp0reg == cp0reg && names[i].sel == sel) | |
803 | return &names[i]; | |
804 | return NULL; | |
805 | } | |
252b5132 | 806 | \f |
7f6621cd | 807 | /* Print insn arguments for 32/64-bit code. */ |
aa5f19f2 | 808 | |
794ac9d0 | 809 | static void |
47b0e7ad NC |
810 | print_insn_args (const char *d, |
811 | register unsigned long int l, | |
812 | bfd_vma pc, | |
cc0ca239 TS |
813 | struct disassemble_info *info, |
814 | const struct mips_opcode *opp) | |
252b5132 | 815 | { |
794ac9d0 | 816 | int op, delta; |
440cc0bc CD |
817 | unsigned int lsb, msb, msbd; |
818 | ||
819 | lsb = 0; | |
252b5132 | 820 | |
794ac9d0 | 821 | for (; *d != '\0'; d++) |
252b5132 | 822 | { |
af7ee8bf CD |
823 | switch (*d) |
824 | { | |
794ac9d0 CD |
825 | case ',': |
826 | case '(': | |
827 | case ')': | |
828 | case '[': | |
829 | case ']': | |
830 | (*info->fprintf_func) (info->stream, "%c", *d); | |
831 | break; | |
832 | ||
833 | case '+': | |
834 | /* Extension character; switch for second char. */ | |
835 | d++; | |
836 | switch (*d) | |
837 | { | |
838 | case '\0': | |
839 | /* xgettext:c-format */ | |
840 | (*info->fprintf_func) (info->stream, | |
841 | _("# internal error, incomplete extension sequence (+)")); | |
842 | return; | |
843 | ||
844 | case 'A': | |
440cc0bc CD |
845 | lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; |
846 | (*info->fprintf_func) (info->stream, "0x%x", lsb); | |
794ac9d0 CD |
847 | break; |
848 | ||
849 | case 'B': | |
440cc0bc CD |
850 | msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; |
851 | (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); | |
794ac9d0 CD |
852 | break; |
853 | ||
9bcd4f99 TS |
854 | case '1': |
855 | (*info->fprintf_func) (info->stream, "0x%lx", | |
856 | (l >> OP_SH_UDI1) & OP_MASK_UDI1); | |
857 | break; | |
858 | ||
859 | case '2': | |
860 | (*info->fprintf_func) (info->stream, "0x%lx", | |
861 | (l >> OP_SH_UDI2) & OP_MASK_UDI2); | |
862 | break; | |
863 | ||
864 | case '3': | |
865 | (*info->fprintf_func) (info->stream, "0x%lx", | |
866 | (l >> OP_SH_UDI3) & OP_MASK_UDI3); | |
867 | break; | |
868 | ||
869 | case '4': | |
870 | (*info->fprintf_func) (info->stream, "0x%lx", | |
871 | (l >> OP_SH_UDI4) & OP_MASK_UDI4); | |
872 | break; | |
873 | ||
794ac9d0 | 874 | case 'C': |
5f74bc13 | 875 | case 'H': |
440cc0bc CD |
876 | msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; |
877 | (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); | |
794ac9d0 CD |
878 | break; |
879 | ||
880 | case 'D': | |
881 | { | |
882 | const struct mips_cp0sel_name *n; | |
883 | unsigned int cp0reg, sel; | |
884 | ||
885 | cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; | |
886 | sel = (l >> OP_SH_SEL) & OP_MASK_SEL; | |
887 | ||
888 | /* CP0 register including 'sel' code for mtcN (et al.), to be | |
889 | printed textually if known. If not known, print both | |
890 | CP0 register name and sel numerically since CP0 register | |
891 | with sel 0 may have a name unrelated to register being | |
892 | printed. */ | |
893 | n = lookup_mips_cp0sel_name(mips_cp0sel_names, | |
894 | mips_cp0sel_names_len, cp0reg, sel); | |
895 | if (n != NULL) | |
896 | (*info->fprintf_func) (info->stream, "%s", n->name); | |
897 | else | |
898 | (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); | |
899 | break; | |
900 | } | |
901 | ||
5f74bc13 CD |
902 | case 'E': |
903 | lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; | |
904 | (*info->fprintf_func) (info->stream, "0x%x", lsb); | |
905 | break; | |
906 | ||
907 | case 'F': | |
908 | msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; | |
909 | (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); | |
910 | break; | |
911 | ||
912 | case 'G': | |
913 | msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; | |
914 | (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); | |
915 | break; | |
916 | ||
61cc0267 CF |
917 | case 't': /* Coprocessor 0 reg name */ |
918 | (*info->fprintf_func) (info->stream, "%s", | |
919 | mips_cp0_names[(l >> OP_SH_RT) & | |
920 | OP_MASK_RT]); | |
921 | break; | |
922 | ||
923 | case 'T': /* Coprocessor 0 reg name */ | |
924 | { | |
925 | const struct mips_cp0sel_name *n; | |
926 | unsigned int cp0reg, sel; | |
927 | ||
928 | cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; | |
929 | sel = (l >> OP_SH_SEL) & OP_MASK_SEL; | |
930 | ||
931 | /* CP0 register including 'sel' code for mftc0, to be | |
932 | printed textually if known. If not known, print both | |
933 | CP0 register name and sel numerically since CP0 register | |
934 | with sel 0 may have a name unrelated to register being | |
935 | printed. */ | |
936 | n = lookup_mips_cp0sel_name(mips_cp0sel_names, | |
937 | mips_cp0sel_names_len, cp0reg, sel); | |
938 | if (n != NULL) | |
939 | (*info->fprintf_func) (info->stream, "%s", n->name); | |
940 | else | |
941 | (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); | |
942 | break; | |
943 | } | |
944 | ||
bb35fb24 NC |
945 | case 'x': /* bbit bit index */ |
946 | (*info->fprintf_func) (info->stream, "0x%lx", | |
947 | (l >> OP_SH_BBITIND) & OP_MASK_BBITIND); | |
948 | break; | |
949 | ||
950 | case 'p': /* cins, cins32, exts and exts32 position */ | |
951 | (*info->fprintf_func) (info->stream, "0x%lx", | |
952 | (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS); | |
953 | break; | |
954 | ||
955 | case 's': /* cins and exts length-minus-one */ | |
956 | (*info->fprintf_func) (info->stream, "0x%lx", | |
957 | (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); | |
958 | break; | |
959 | ||
960 | case 'S': /* cins32 and exts32 length-minus-one field */ | |
961 | (*info->fprintf_func) (info->stream, "0x%lx", | |
962 | (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); | |
963 | break; | |
964 | ||
dd3cbb7e NC |
965 | case 'Q': /* seqi/snei immediate field */ |
966 | op = (l >> OP_SH_SEQI) & OP_MASK_SEQI; | |
967 | /* Sign-extend it. */ | |
968 | op = (op ^ 512) - 512; | |
969 | (*info->fprintf_func) (info->stream, "%d", op); | |
970 | break; | |
971 | ||
794ac9d0 CD |
972 | default: |
973 | /* xgettext:c-format */ | |
974 | (*info->fprintf_func) (info->stream, | |
975 | _("# internal error, undefined extension sequence (+%c)"), | |
976 | *d); | |
977 | return; | |
978 | } | |
979 | break; | |
980 | ||
8b082fb1 TS |
981 | case '2': |
982 | (*info->fprintf_func) (info->stream, "0x%lx", | |
983 | (l >> OP_SH_BP) & OP_MASK_BP); | |
984 | break; | |
985 | ||
fd25c5a9 CF |
986 | case '3': |
987 | (*info->fprintf_func) (info->stream, "0x%lx", | |
988 | (l >> OP_SH_SA3) & OP_MASK_SA3); | |
989 | break; | |
990 | ||
991 | case '4': | |
992 | (*info->fprintf_func) (info->stream, "0x%lx", | |
993 | (l >> OP_SH_SA4) & OP_MASK_SA4); | |
994 | break; | |
995 | ||
996 | case '5': | |
997 | (*info->fprintf_func) (info->stream, "0x%lx", | |
998 | (l >> OP_SH_IMM8) & OP_MASK_IMM8); | |
999 | break; | |
1000 | ||
1001 | case '6': | |
1002 | (*info->fprintf_func) (info->stream, "0x%lx", | |
1003 | (l >> OP_SH_RS) & OP_MASK_RS); | |
1004 | break; | |
1005 | ||
1006 | case '7': | |
1007 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
1008 | (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); | |
1009 | break; | |
1010 | ||
1011 | case '8': | |
1012 | (*info->fprintf_func) (info->stream, "0x%lx", | |
1013 | (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); | |
1014 | break; | |
1015 | ||
1016 | case '9': | |
1017 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
1018 | (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); | |
1019 | break; | |
1020 | ||
1021 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
1022 | delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); | |
1023 | if (delta & 0x20) /* test sign bit */ | |
1024 | delta |= ~OP_MASK_DSPSFT; | |
1025 | (*info->fprintf_func) (info->stream, "%d", delta); | |
1026 | break; | |
1027 | ||
1028 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
1029 | delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); | |
1030 | if (delta & 0x40) /* test sign bit */ | |
1031 | delta |= ~OP_MASK_DSPSFT_7; | |
1032 | (*info->fprintf_func) (info->stream, "%d", delta); | |
1033 | break; | |
1034 | ||
1035 | case '\'': | |
1036 | (*info->fprintf_func) (info->stream, "0x%lx", | |
1037 | (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); | |
1038 | break; | |
1039 | ||
1040 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
1041 | delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); | |
1042 | if (delta & 0x200) /* test sign bit */ | |
1043 | delta |= ~OP_MASK_IMM10; | |
1044 | (*info->fprintf_func) (info->stream, "%d", delta); | |
1045 | break; | |
1046 | ||
61cc0267 CF |
1047 | case '!': |
1048 | (*info->fprintf_func) (info->stream, "%ld", | |
1049 | (l >> OP_SH_MT_U) & OP_MASK_MT_U); | |
1050 | break; | |
1051 | ||
1052 | case '$': | |
1053 | (*info->fprintf_func) (info->stream, "%ld", | |
1054 | (l >> OP_SH_MT_H) & OP_MASK_MT_H); | |
1055 | break; | |
1056 | ||
1057 | case '*': | |
1058 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
1059 | (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); | |
1060 | break; | |
1061 | ||
1062 | case '&': | |
1063 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
1064 | (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); | |
1065 | break; | |
1066 | ||
1067 | case 'g': | |
1068 | /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ | |
1069 | (*info->fprintf_func) (info->stream, "$%ld", | |
1070 | (l >> OP_SH_RD) & OP_MASK_RD); | |
1071 | break; | |
1072 | ||
794ac9d0 CD |
1073 | case 's': |
1074 | case 'b': | |
1075 | case 'r': | |
1076 | case 'v': | |
1077 | (*info->fprintf_func) (info->stream, "%s", | |
1078 | mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); | |
1079 | break; | |
1080 | ||
1081 | case 't': | |
1082 | case 'w': | |
1083 | (*info->fprintf_func) (info->stream, "%s", | |
1084 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
1085 | break; | |
1086 | ||
1087 | case 'i': | |
1088 | case 'u': | |
0fd3a477 | 1089 | (*info->fprintf_func) (info->stream, "0x%lx", |
794ac9d0 CD |
1090 | (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); |
1091 | break; | |
1092 | ||
1093 | case 'j': /* Same as i, but sign-extended. */ | |
1094 | case 'o': | |
1095 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; | |
1096 | if (delta & 0x8000) | |
1097 | delta |= ~0xffff; | |
1098 | (*info->fprintf_func) (info->stream, "%d", | |
1099 | delta); | |
1100 | break; | |
1101 | ||
1102 | case 'h': | |
1103 | (*info->fprintf_func) (info->stream, "0x%x", | |
1104 | (unsigned int) ((l >> OP_SH_PREFX) | |
1105 | & OP_MASK_PREFX)); | |
1106 | break; | |
1107 | ||
1108 | case 'k': | |
1109 | (*info->fprintf_func) (info->stream, "0x%x", | |
1110 | (unsigned int) ((l >> OP_SH_CACHE) | |
1111 | & OP_MASK_CACHE)); | |
1112 | break; | |
1113 | ||
1114 | case 'a': | |
1115 | info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) | |
1116 | | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); | |
022fac6d TS |
1117 | /* For gdb disassembler, force odd address on jalx. */ |
1118 | if (info->flavour == bfd_target_unknown_flavour | |
1119 | && strcmp (opp->name, "jalx") == 0) | |
1120 | info->target |= 1; | |
794ac9d0 CD |
1121 | (*info->print_address_func) (info->target, info); |
1122 | break; | |
1123 | ||
1124 | case 'p': | |
1125 | /* Sign extend the displacement. */ | |
1126 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; | |
1127 | if (delta & 0x8000) | |
1128 | delta |= ~0xffff; | |
1129 | info->target = (delta << 2) + pc + INSNLEN; | |
1130 | (*info->print_address_func) (info->target, info); | |
1131 | break; | |
1132 | ||
1133 | case 'd': | |
1134 | (*info->fprintf_func) (info->stream, "%s", | |
1135 | mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
1136 | break; | |
1137 | ||
1138 | case 'U': | |
1139 | { | |
1140 | /* First check for both rd and rt being equal. */ | |
1141 | unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; | |
1142 | if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) | |
1143 | (*info->fprintf_func) (info->stream, "%s", | |
1144 | mips_gpr_names[reg]); | |
1145 | else | |
1146 | { | |
1147 | /* If one is zero use the other. */ | |
1148 | if (reg == 0) | |
1149 | (*info->fprintf_func) (info->stream, "%s", | |
1150 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
1151 | else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) | |
1152 | (*info->fprintf_func) (info->stream, "%s", | |
1153 | mips_gpr_names[reg]); | |
1154 | else /* Bogus, result depends on processor. */ | |
1155 | (*info->fprintf_func) (info->stream, "%s or %s", | |
1156 | mips_gpr_names[reg], | |
1157 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
1158 | } | |
1159 | } | |
1160 | break; | |
1161 | ||
1162 | case 'z': | |
1163 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); | |
1164 | break; | |
1165 | ||
1166 | case '<': | |
4dc48ef6 | 1167 | case '1': |
0fd3a477 | 1168 | (*info->fprintf_func) (info->stream, "0x%lx", |
af7ee8bf CD |
1169 | (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); |
1170 | break; | |
794ac9d0 CD |
1171 | |
1172 | case 'c': | |
0fd3a477 | 1173 | (*info->fprintf_func) (info->stream, "0x%lx", |
794ac9d0 CD |
1174 | (l >> OP_SH_CODE) & OP_MASK_CODE); |
1175 | break; | |
1176 | ||
1177 | case 'q': | |
0fd3a477 | 1178 | (*info->fprintf_func) (info->stream, "0x%lx", |
794ac9d0 | 1179 | (l >> OP_SH_CODE2) & OP_MASK_CODE2); |
af7ee8bf CD |
1180 | break; |
1181 | ||
1182 | case 'C': | |
0fd3a477 | 1183 | (*info->fprintf_func) (info->stream, "0x%lx", |
794ac9d0 CD |
1184 | (l >> OP_SH_COPZ) & OP_MASK_COPZ); |
1185 | break; | |
1186 | ||
1187 | case 'B': | |
0fd3a477 JW |
1188 | (*info->fprintf_func) (info->stream, "0x%lx", |
1189 | ||
794ac9d0 CD |
1190 | (l >> OP_SH_CODE20) & OP_MASK_CODE20); |
1191 | break; | |
1192 | ||
1193 | case 'J': | |
0fd3a477 | 1194 | (*info->fprintf_func) (info->stream, "0x%lx", |
794ac9d0 CD |
1195 | (l >> OP_SH_CODE19) & OP_MASK_CODE19); |
1196 | break; | |
1197 | ||
1198 | case 'S': | |
1199 | case 'V': | |
1200 | (*info->fprintf_func) (info->stream, "%s", | |
1201 | mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); | |
1202 | break; | |
1203 | ||
1204 | case 'T': | |
1205 | case 'W': | |
1206 | (*info->fprintf_func) (info->stream, "%s", | |
1207 | mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); | |
af7ee8bf CD |
1208 | break; |
1209 | ||
bbcc0807 | 1210 | case 'D': |
794ac9d0 CD |
1211 | (*info->fprintf_func) (info->stream, "%s", |
1212 | mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); | |
1213 | break; | |
1214 | ||
1215 | case 'R': | |
1216 | (*info->fprintf_func) (info->stream, "%s", | |
1217 | mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); | |
1218 | break; | |
1219 | ||
1220 | case 'E': | |
1221 | /* Coprocessor register for lwcN instructions, et al. | |
1222 | ||
1223 | Note that there is no load/store cp0 instructions, and | |
1224 | that FPU (cp1) instructions disassemble this field using | |
1225 | 'T' format. Therefore, until we gain understanding of | |
1226 | cp2 register names, we can simply print the register | |
1227 | numbers. */ | |
0fd3a477 | 1228 | (*info->fprintf_func) (info->stream, "$%ld", |
794ac9d0 CD |
1229 | (l >> OP_SH_RT) & OP_MASK_RT); |
1230 | break; | |
1231 | ||
1232 | case 'G': | |
1233 | /* Coprocessor register for mtcN instructions, et al. Note | |
1234 | that FPU (cp1) instructions disassemble this field using | |
1235 | 'S' format. Therefore, we only need to worry about cp0, | |
1236 | cp2, and cp3. */ | |
1237 | op = (l >> OP_SH_OP) & OP_MASK_OP; | |
1238 | if (op == OP_OP_COP0) | |
1239 | (*info->fprintf_func) (info->stream, "%s", | |
1240 | mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
1241 | else | |
0fd3a477 | 1242 | (*info->fprintf_func) (info->stream, "$%ld", |
794ac9d0 CD |
1243 | (l >> OP_SH_RD) & OP_MASK_RD); |
1244 | break; | |
1245 | ||
1246 | case 'K': | |
1247 | (*info->fprintf_func) (info->stream, "%s", | |
1248 | mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
1249 | break; | |
1250 | ||
1251 | case 'N': | |
0d09bfe6 TS |
1252 | (*info->fprintf_func) (info->stream, |
1253 | ((opp->pinfo & (FP_D | FP_S)) != 0 | |
1254 | ? "$fcc%ld" : "$cc%ld"), | |
794ac9d0 CD |
1255 | (l >> OP_SH_BCC) & OP_MASK_BCC); |
1256 | break; | |
1257 | ||
1258 | case 'M': | |
0fd3a477 | 1259 | (*info->fprintf_func) (info->stream, "$fcc%ld", |
794ac9d0 CD |
1260 | (l >> OP_SH_CCC) & OP_MASK_CCC); |
1261 | break; | |
1262 | ||
1263 | case 'P': | |
0fd3a477 | 1264 | (*info->fprintf_func) (info->stream, "%ld", |
794ac9d0 CD |
1265 | (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); |
1266 | break; | |
1267 | ||
1268 | case 'e': | |
0fd3a477 | 1269 | (*info->fprintf_func) (info->stream, "%ld", |
794ac9d0 CD |
1270 | (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); |
1271 | break; | |
1272 | ||
1273 | case '%': | |
0fd3a477 | 1274 | (*info->fprintf_func) (info->stream, "%ld", |
794ac9d0 CD |
1275 | (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); |
1276 | break; | |
1277 | ||
1278 | case 'H': | |
0fd3a477 | 1279 | (*info->fprintf_func) (info->stream, "%ld", |
794ac9d0 CD |
1280 | (l >> OP_SH_SEL) & OP_MASK_SEL); |
1281 | break; | |
1282 | ||
1283 | case 'O': | |
0fd3a477 | 1284 | (*info->fprintf_func) (info->stream, "%ld", |
794ac9d0 CD |
1285 | (l >> OP_SH_ALN) & OP_MASK_ALN); |
1286 | break; | |
1287 | ||
1288 | case 'Q': | |
bbcc0807 | 1289 | { |
794ac9d0 | 1290 | unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; |
47b0e7ad | 1291 | |
794ac9d0 CD |
1292 | if ((vsel & 0x10) == 0) |
1293 | { | |
1294 | int fmt; | |
47b0e7ad | 1295 | |
794ac9d0 CD |
1296 | vsel &= 0x0f; |
1297 | for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) | |
1298 | if ((vsel & 1) == 0) | |
1299 | break; | |
0fd3a477 | 1300 | (*info->fprintf_func) (info->stream, "$v%ld[%d]", |
794ac9d0 CD |
1301 | (l >> OP_SH_FT) & OP_MASK_FT, |
1302 | vsel >> 1); | |
1303 | } | |
1304 | else if ((vsel & 0x08) == 0) | |
1305 | { | |
0fd3a477 | 1306 | (*info->fprintf_func) (info->stream, "$v%ld", |
794ac9d0 CD |
1307 | (l >> OP_SH_FT) & OP_MASK_FT); |
1308 | } | |
bbcc0807 | 1309 | else |
794ac9d0 | 1310 | { |
0fd3a477 | 1311 | (*info->fprintf_func) (info->stream, "0x%lx", |
794ac9d0 CD |
1312 | (l >> OP_SH_FT) & OP_MASK_FT); |
1313 | } | |
bbcc0807 | 1314 | } |
794ac9d0 CD |
1315 | break; |
1316 | ||
1317 | case 'X': | |
0fd3a477 | 1318 | (*info->fprintf_func) (info->stream, "$v%ld", |
794ac9d0 CD |
1319 | (l >> OP_SH_FD) & OP_MASK_FD); |
1320 | break; | |
1321 | ||
1322 | case 'Y': | |
0fd3a477 | 1323 | (*info->fprintf_func) (info->stream, "$v%ld", |
794ac9d0 CD |
1324 | (l >> OP_SH_FS) & OP_MASK_FS); |
1325 | break; | |
1326 | ||
1327 | case 'Z': | |
0fd3a477 | 1328 | (*info->fprintf_func) (info->stream, "$v%ld", |
794ac9d0 CD |
1329 | (l >> OP_SH_FT) & OP_MASK_FT); |
1330 | break; | |
bbcc0807 | 1331 | |
af7ee8bf CD |
1332 | default: |
1333 | /* xgettext:c-format */ | |
1334 | (*info->fprintf_func) (info->stream, | |
168411b1 | 1335 | _("# internal error, undefined modifier (%c)"), |
af7ee8bf | 1336 | *d); |
794ac9d0 | 1337 | return; |
af7ee8bf | 1338 | } |
252b5132 RH |
1339 | } |
1340 | } | |
1341 | \f | |
252b5132 RH |
1342 | /* Print the mips instruction at address MEMADDR in debugged memory, |
1343 | on using INFO. Returns length of the instruction, in bytes, which is | |
aa5f19f2 | 1344 | always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if |
252b5132 RH |
1345 | this is little-endian code. */ |
1346 | ||
1347 | static int | |
47b0e7ad NC |
1348 | print_insn_mips (bfd_vma memaddr, |
1349 | unsigned long int word, | |
1350 | struct disassemble_info *info) | |
252b5132 | 1351 | { |
47b0e7ad | 1352 | const struct mips_opcode *op; |
b34976b6 | 1353 | static bfd_boolean init = 0; |
252b5132 RH |
1354 | static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; |
1355 | ||
1356 | /* Build a hash table to shorten the search time. */ | |
1357 | if (! init) | |
1358 | { | |
1359 | unsigned int i; | |
1360 | ||
1361 | for (i = 0; i <= OP_MASK_OP; i++) | |
1362 | { | |
1363 | for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) | |
1364 | { | |
986e18a5 | 1365 | if (op->pinfo == INSN_MACRO |
9e836e3d | 1366 | || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) |
252b5132 RH |
1367 | continue; |
1368 | if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) | |
1369 | { | |
1370 | mips_hash[i] = op; | |
1371 | break; | |
1372 | } | |
1373 | } | |
7f6621cd | 1374 | } |
252b5132 RH |
1375 | |
1376 | init = 1; | |
1377 | } | |
1378 | ||
aa5f19f2 | 1379 | info->bytes_per_chunk = INSNLEN; |
252b5132 | 1380 | info->display_endian = info->endian; |
9bb28706 CD |
1381 | info->insn_info_valid = 1; |
1382 | info->branch_delay_insns = 0; | |
def7143b | 1383 | info->data_size = 0; |
9bb28706 CD |
1384 | info->insn_type = dis_nonbranch; |
1385 | info->target = 0; | |
1386 | info->target2 = 0; | |
252b5132 RH |
1387 | |
1388 | op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; | |
1389 | if (op != NULL) | |
1390 | { | |
1391 | for (; op < &mips_opcodes[NUMOPCODES]; op++) | |
1392 | { | |
986e18a5 | 1393 | if (op->pinfo != INSN_MACRO |
9e836e3d | 1394 | && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) |
986e18a5 | 1395 | && (word & op->mask) == op->match) |
252b5132 | 1396 | { |
47b0e7ad | 1397 | const char *d; |
2bd7f1f3 | 1398 | |
3396de36 | 1399 | /* We always allow to disassemble the jalx instruction. */ |
640c0ccd | 1400 | if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) |
3396de36 | 1401 | && strcmp (op->name, "jalx")) |
252b5132 RH |
1402 | continue; |
1403 | ||
9bb28706 CD |
1404 | /* Figure out instruction type and branch delay information. */ |
1405 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1406 | { | |
c680e7f6 MR |
1407 | if ((op->pinfo & (INSN_WRITE_GPR_31 |
1408 | | INSN_WRITE_GPR_D)) != 0) | |
9bb28706 CD |
1409 | info->insn_type = dis_jsr; |
1410 | else | |
1411 | info->insn_type = dis_branch; | |
1412 | info->branch_delay_insns = 1; | |
1413 | } | |
1414 | else if ((op->pinfo & (INSN_COND_BRANCH_DELAY | |
1415 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
1416 | { | |
c680e7f6 | 1417 | if ((op->pinfo & INSN_WRITE_GPR_31) != 0) |
9bb28706 CD |
1418 | info->insn_type = dis_condjsr; |
1419 | else | |
1420 | info->insn_type = dis_condbranch; | |
1421 | info->branch_delay_insns = 1; | |
1422 | } | |
1423 | else if ((op->pinfo & (INSN_STORE_MEMORY | |
1424 | | INSN_LOAD_MEMORY_DELAY)) != 0) | |
1425 | info->insn_type = dis_dref; | |
1426 | ||
252b5132 RH |
1427 | (*info->fprintf_func) (info->stream, "%s", op->name); |
1428 | ||
1429 | d = op->args; | |
1430 | if (d != NULL && *d != '\0') | |
1431 | { | |
7f6621cd | 1432 | (*info->fprintf_func) (info->stream, "\t"); |
cc0ca239 | 1433 | print_insn_args (d, word, memaddr, info, op); |
252b5132 RH |
1434 | } |
1435 | ||
aa5f19f2 | 1436 | return INSNLEN; |
252b5132 RH |
1437 | } |
1438 | } | |
1439 | } | |
1440 | ||
1441 | /* Handle undefined instructions. */ | |
9bb28706 | 1442 | info->insn_type = dis_noninsn; |
0fd3a477 | 1443 | (*info->fprintf_func) (info->stream, "0x%lx", word); |
aa5f19f2 | 1444 | return INSNLEN; |
252b5132 | 1445 | } |
aa5f19f2 | 1446 | \f |
252b5132 RH |
1447 | /* Disassemble an operand for a mips16 instruction. */ |
1448 | ||
1449 | static void | |
47b0e7ad NC |
1450 | print_mips16_insn_arg (char type, |
1451 | const struct mips_opcode *op, | |
1452 | int l, | |
1453 | bfd_boolean use_extend, | |
1454 | int extend, | |
1455 | bfd_vma memaddr, | |
1456 | struct disassemble_info *info) | |
252b5132 RH |
1457 | { |
1458 | switch (type) | |
1459 | { | |
1460 | case ',': | |
1461 | case '(': | |
1462 | case ')': | |
1463 | (*info->fprintf_func) (info->stream, "%c", type); | |
1464 | break; | |
1465 | ||
1466 | case 'y': | |
1467 | case 'w': | |
aa5f19f2 | 1468 | (*info->fprintf_func) (info->stream, "%s", |
654c225a TS |
1469 | mips16_reg_names(((l >> MIPS16OP_SH_RY) |
1470 | & MIPS16OP_MASK_RY))); | |
252b5132 RH |
1471 | break; |
1472 | ||
1473 | case 'x': | |
1474 | case 'v': | |
aa5f19f2 | 1475 | (*info->fprintf_func) (info->stream, "%s", |
654c225a TS |
1476 | mips16_reg_names(((l >> MIPS16OP_SH_RX) |
1477 | & MIPS16OP_MASK_RX))); | |
252b5132 RH |
1478 | break; |
1479 | ||
1480 | case 'z': | |
aa5f19f2 | 1481 | (*info->fprintf_func) (info->stream, "%s", |
654c225a TS |
1482 | mips16_reg_names(((l >> MIPS16OP_SH_RZ) |
1483 | & MIPS16OP_MASK_RZ))); | |
252b5132 RH |
1484 | break; |
1485 | ||
1486 | case 'Z': | |
aa5f19f2 | 1487 | (*info->fprintf_func) (info->stream, "%s", |
654c225a TS |
1488 | mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) |
1489 | & MIPS16OP_MASK_MOVE32Z))); | |
252b5132 RH |
1490 | break; |
1491 | ||
1492 | case '0': | |
640c0ccd | 1493 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
252b5132 RH |
1494 | break; |
1495 | ||
1496 | case 'S': | |
640c0ccd | 1497 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); |
252b5132 RH |
1498 | break; |
1499 | ||
1500 | case 'P': | |
1501 | (*info->fprintf_func) (info->stream, "$pc"); | |
1502 | break; | |
1503 | ||
1504 | case 'R': | |
640c0ccd | 1505 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); |
252b5132 RH |
1506 | break; |
1507 | ||
1508 | case 'X': | |
aa5f19f2 | 1509 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd CD |
1510 | mips_gpr_names[((l >> MIPS16OP_SH_REGR32) |
1511 | & MIPS16OP_MASK_REGR32)]); | |
252b5132 RH |
1512 | break; |
1513 | ||
1514 | case 'Y': | |
aa5f19f2 | 1515 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 1516 | mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); |
252b5132 RH |
1517 | break; |
1518 | ||
1519 | case '<': | |
1520 | case '>': | |
1521 | case '[': | |
1522 | case ']': | |
1523 | case '4': | |
1524 | case '5': | |
1525 | case 'H': | |
1526 | case 'W': | |
1527 | case 'D': | |
1528 | case 'j': | |
1529 | case '6': | |
1530 | case '8': | |
1531 | case 'V': | |
1532 | case 'C': | |
1533 | case 'U': | |
1534 | case 'k': | |
1535 | case 'K': | |
1536 | case 'p': | |
1537 | case 'q': | |
1538 | case 'A': | |
1539 | case 'B': | |
1540 | case 'E': | |
1541 | { | |
1542 | int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; | |
1543 | ||
1544 | shift = 0; | |
1545 | signedp = 0; | |
1546 | extbits = 16; | |
1547 | pcrel = 0; | |
1548 | extu = 0; | |
1549 | branch = 0; | |
1550 | switch (type) | |
1551 | { | |
1552 | case '<': | |
1553 | nbits = 3; | |
1554 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
1555 | extbits = 5; | |
1556 | extu = 1; | |
1557 | break; | |
1558 | case '>': | |
1559 | nbits = 3; | |
1560 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
1561 | extbits = 5; | |
1562 | extu = 1; | |
1563 | break; | |
1564 | case '[': | |
1565 | nbits = 3; | |
1566 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
1567 | extbits = 6; | |
1568 | extu = 1; | |
1569 | break; | |
1570 | case ']': | |
1571 | nbits = 3; | |
1572 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
1573 | extbits = 6; | |
1574 | extu = 1; | |
1575 | break; | |
1576 | case '4': | |
1577 | nbits = 4; | |
1578 | immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; | |
1579 | signedp = 1; | |
1580 | extbits = 15; | |
1581 | break; | |
1582 | case '5': | |
1583 | nbits = 5; | |
1584 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1585 | info->insn_type = dis_dref; | |
1586 | info->data_size = 1; | |
1587 | break; | |
1588 | case 'H': | |
1589 | nbits = 5; | |
1590 | shift = 1; | |
1591 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1592 | info->insn_type = dis_dref; | |
1593 | info->data_size = 2; | |
1594 | break; | |
1595 | case 'W': | |
1596 | nbits = 5; | |
1597 | shift = 2; | |
1598 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1599 | if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 | |
1600 | && (op->pinfo & MIPS16_INSN_READ_SP) == 0) | |
1601 | { | |
1602 | info->insn_type = dis_dref; | |
1603 | info->data_size = 4; | |
1604 | } | |
1605 | break; | |
1606 | case 'D': | |
1607 | nbits = 5; | |
1608 | shift = 3; | |
1609 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1610 | info->insn_type = dis_dref; | |
1611 | info->data_size = 8; | |
1612 | break; | |
1613 | case 'j': | |
1614 | nbits = 5; | |
1615 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1616 | signedp = 1; | |
1617 | break; | |
1618 | case '6': | |
1619 | nbits = 6; | |
1620 | immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1621 | break; | |
1622 | case '8': | |
1623 | nbits = 8; | |
1624 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1625 | break; | |
1626 | case 'V': | |
1627 | nbits = 8; | |
1628 | shift = 2; | |
1629 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1630 | /* FIXME: This might be lw, or it might be addiu to $sp or | |
1631 | $pc. We assume it's load. */ | |
1632 | info->insn_type = dis_dref; | |
1633 | info->data_size = 4; | |
1634 | break; | |
1635 | case 'C': | |
1636 | nbits = 8; | |
1637 | shift = 3; | |
1638 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1639 | info->insn_type = dis_dref; | |
1640 | info->data_size = 8; | |
1641 | break; | |
1642 | case 'U': | |
1643 | nbits = 8; | |
1644 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1645 | extu = 1; | |
1646 | break; | |
1647 | case 'k': | |
1648 | nbits = 8; | |
1649 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1650 | signedp = 1; | |
1651 | break; | |
1652 | case 'K': | |
1653 | nbits = 8; | |
1654 | shift = 3; | |
1655 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1656 | signedp = 1; | |
1657 | break; | |
1658 | case 'p': | |
1659 | nbits = 8; | |
1660 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1661 | signedp = 1; | |
1662 | pcrel = 1; | |
1663 | branch = 1; | |
252b5132 RH |
1664 | break; |
1665 | case 'q': | |
1666 | nbits = 11; | |
1667 | immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; | |
1668 | signedp = 1; | |
1669 | pcrel = 1; | |
1670 | branch = 1; | |
252b5132 RH |
1671 | break; |
1672 | case 'A': | |
1673 | nbits = 8; | |
1674 | shift = 2; | |
1675 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1676 | pcrel = 1; | |
1677 | /* FIXME: This can be lw or la. We assume it is lw. */ | |
1678 | info->insn_type = dis_dref; | |
1679 | info->data_size = 4; | |
1680 | break; | |
1681 | case 'B': | |
1682 | nbits = 5; | |
1683 | shift = 3; | |
1684 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1685 | pcrel = 1; | |
1686 | info->insn_type = dis_dref; | |
1687 | info->data_size = 8; | |
1688 | break; | |
1689 | case 'E': | |
1690 | nbits = 5; | |
1691 | shift = 2; | |
1692 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1693 | pcrel = 1; | |
1694 | break; | |
1695 | default: | |
1696 | abort (); | |
1697 | } | |
1698 | ||
1699 | if (! use_extend) | |
1700 | { | |
1701 | if (signedp && immed >= (1 << (nbits - 1))) | |
1702 | immed -= 1 << nbits; | |
1703 | immed <<= shift; | |
1704 | if ((type == '<' || type == '>' || type == '[' || type == ']') | |
1705 | && immed == 0) | |
1706 | immed = 8; | |
1707 | } | |
1708 | else | |
1709 | { | |
1710 | if (extbits == 16) | |
1711 | immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); | |
1712 | else if (extbits == 15) | |
1713 | immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); | |
1714 | else | |
1715 | immed = ((extend >> 6) & 0x1f) | (extend & 0x20); | |
1716 | immed &= (1 << extbits) - 1; | |
1717 | if (! extu && immed >= (1 << (extbits - 1))) | |
1718 | immed -= 1 << extbits; | |
1719 | } | |
1720 | ||
1721 | if (! pcrel) | |
1722 | (*info->fprintf_func) (info->stream, "%d", immed); | |
1723 | else | |
1724 | { | |
1725 | bfd_vma baseaddr; | |
252b5132 RH |
1726 | |
1727 | if (branch) | |
1728 | { | |
1729 | immed *= 2; | |
1730 | baseaddr = memaddr + 2; | |
1731 | } | |
1732 | else if (use_extend) | |
1733 | baseaddr = memaddr - 2; | |
1734 | else | |
1735 | { | |
1736 | int status; | |
1737 | bfd_byte buffer[2]; | |
1738 | ||
1739 | baseaddr = memaddr; | |
1740 | ||
1741 | /* If this instruction is in the delay slot of a jr | |
1742 | instruction, the base address is the address of the | |
1743 | jr instruction. If it is in the delay slot of jalr | |
1744 | instruction, the base address is the address of the | |
1745 | jalr instruction. This test is unreliable: we have | |
1746 | no way of knowing whether the previous word is | |
1747 | instruction or data. */ | |
1748 | status = (*info->read_memory_func) (memaddr - 4, buffer, 2, | |
1749 | info); | |
1750 | if (status == 0 | |
1751 | && (((info->endian == BFD_ENDIAN_BIG | |
1752 | ? bfd_getb16 (buffer) | |
1753 | : bfd_getl16 (buffer)) | |
1754 | & 0xf800) == 0x1800)) | |
1755 | baseaddr = memaddr - 4; | |
1756 | else | |
1757 | { | |
1758 | status = (*info->read_memory_func) (memaddr - 2, buffer, | |
1759 | 2, info); | |
1760 | if (status == 0 | |
1761 | && (((info->endian == BFD_ENDIAN_BIG | |
1762 | ? bfd_getb16 (buffer) | |
1763 | : bfd_getl16 (buffer)) | |
1764 | & 0xf81f) == 0xe800)) | |
1765 | baseaddr = memaddr - 2; | |
1766 | } | |
1767 | } | |
9bb28706 | 1768 | info->target = (baseaddr & ~((1 << shift) - 1)) + immed; |
022fac6d TS |
1769 | if (pcrel && branch |
1770 | && info->flavour == bfd_target_unknown_flavour) | |
1771 | /* For gdb disassembler, maintain odd address. */ | |
1772 | info->target |= 1; | |
9bb28706 | 1773 | (*info->print_address_func) (info->target, info); |
252b5132 RH |
1774 | } |
1775 | } | |
1776 | break; | |
1777 | ||
1778 | case 'a': | |
022fac6d TS |
1779 | { |
1780 | int jalx = l & 0x400; | |
1781 | ||
1782 | if (! use_extend) | |
1783 | extend = 0; | |
1784 | l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); | |
1785 | if (!jalx && info->flavour == bfd_target_unknown_flavour) | |
1786 | /* For gdb disassembler, maintain odd address. */ | |
1787 | l |= 1; | |
1788 | } | |
9bb28706 CD |
1789 | info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; |
1790 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
1791 | break; |
1792 | ||
1793 | case 'l': | |
1794 | case 'L': | |
1795 | { | |
1796 | int need_comma, amask, smask; | |
1797 | ||
1798 | need_comma = 0; | |
1799 | ||
1800 | l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1801 | ||
1802 | amask = (l >> 3) & 7; | |
1803 | ||
1804 | if (amask > 0 && amask < 5) | |
1805 | { | |
640c0ccd | 1806 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); |
252b5132 | 1807 | if (amask > 1) |
aa5f19f2 | 1808 | (*info->fprintf_func) (info->stream, "-%s", |
640c0ccd | 1809 | mips_gpr_names[amask + 3]); |
252b5132 RH |
1810 | need_comma = 1; |
1811 | } | |
1812 | ||
1813 | smask = (l >> 1) & 3; | |
1814 | if (smask == 3) | |
1815 | { | |
1816 | (*info->fprintf_func) (info->stream, "%s??", | |
1817 | need_comma ? "," : ""); | |
1818 | need_comma = 1; | |
1819 | } | |
1820 | else if (smask > 0) | |
1821 | { | |
aa5f19f2 | 1822 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1823 | need_comma ? "," : "", |
640c0ccd | 1824 | mips_gpr_names[16]); |
252b5132 | 1825 | if (smask > 1) |
aa5f19f2 | 1826 | (*info->fprintf_func) (info->stream, "-%s", |
640c0ccd | 1827 | mips_gpr_names[smask + 15]); |
252b5132 RH |
1828 | need_comma = 1; |
1829 | } | |
1830 | ||
1831 | if (l & 1) | |
1832 | { | |
aa5f19f2 | 1833 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1834 | need_comma ? "," : "", |
640c0ccd | 1835 | mips_gpr_names[31]); |
252b5132 RH |
1836 | need_comma = 1; |
1837 | } | |
1838 | ||
1839 | if (amask == 5 || amask == 6) | |
1840 | { | |
1841 | (*info->fprintf_func) (info->stream, "%s$f0", | |
1842 | need_comma ? "," : ""); | |
1843 | if (amask == 6) | |
1844 | (*info->fprintf_func) (info->stream, "-$f1"); | |
1845 | } | |
1846 | } | |
1847 | break; | |
1848 | ||
0499d65b TS |
1849 | case 'm': |
1850 | case 'M': | |
1851 | /* MIPS16e save/restore. */ | |
1852 | { | |
1853 | int need_comma = 0; | |
1854 | int amask, args, statics; | |
1855 | int nsreg, smask; | |
1856 | int framesz; | |
1857 | int i, j; | |
1858 | ||
1859 | l = l & 0x7f; | |
1860 | if (use_extend) | |
1861 | l |= extend << 16; | |
1862 | ||
1863 | amask = (l >> 16) & 0xf; | |
1864 | if (amask == MIPS16_ALL_ARGS) | |
1865 | { | |
1866 | args = 4; | |
1867 | statics = 0; | |
1868 | } | |
1869 | else if (amask == MIPS16_ALL_STATICS) | |
1870 | { | |
1871 | args = 0; | |
1872 | statics = 4; | |
1873 | } | |
1874 | else | |
1875 | { | |
1876 | args = amask >> 2; | |
1877 | statics = amask & 3; | |
1878 | } | |
1879 | ||
1880 | if (args > 0) { | |
1881 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); | |
1882 | if (args > 1) | |
1883 | (*info->fprintf_func) (info->stream, "-%s", | |
1884 | mips_gpr_names[4 + args - 1]); | |
1885 | need_comma = 1; | |
1886 | } | |
1887 | ||
1888 | framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; | |
1889 | if (framesz == 0 && !use_extend) | |
1890 | framesz = 128; | |
1891 | ||
1892 | (*info->fprintf_func) (info->stream, "%s%d", | |
1893 | need_comma ? "," : "", | |
1894 | framesz); | |
1895 | ||
1896 | if (l & 0x40) /* $ra */ | |
1897 | (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); | |
1898 | ||
1899 | nsreg = (l >> 24) & 0x7; | |
1900 | smask = 0; | |
1901 | if (l & 0x20) /* $s0 */ | |
1902 | smask |= 1 << 0; | |
1903 | if (l & 0x10) /* $s1 */ | |
1904 | smask |= 1 << 1; | |
1905 | if (nsreg > 0) /* $s2-$s8 */ | |
1906 | smask |= ((1 << nsreg) - 1) << 2; | |
1907 | ||
1908 | /* Find first set static reg bit. */ | |
1909 | for (i = 0; i < 9; i++) | |
1910 | { | |
1911 | if (smask & (1 << i)) | |
1912 | { | |
1913 | (*info->fprintf_func) (info->stream, ",%s", | |
1914 | mips_gpr_names[i == 8 ? 30 : (16 + i)]); | |
1915 | /* Skip over string of set bits. */ | |
1916 | for (j = i; smask & (2 << j); j++) | |
1917 | continue; | |
1918 | if (j > i) | |
1919 | (*info->fprintf_func) (info->stream, "-%s", | |
1920 | mips_gpr_names[j == 8 ? 30 : (16 + j)]); | |
1921 | i = j + 1; | |
1922 | } | |
1923 | } | |
1924 | ||
1925 | /* Statics $ax - $a3. */ | |
1926 | if (statics == 1) | |
1927 | (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); | |
1928 | else if (statics > 0) | |
1929 | (*info->fprintf_func) (info->stream, ",%s-%s", | |
1930 | mips_gpr_names[7 - statics + 1], | |
1931 | mips_gpr_names[7]); | |
1932 | } | |
1933 | break; | |
1934 | ||
252b5132 | 1935 | default: |
aa5f19f2 NC |
1936 | /* xgettext:c-format */ |
1937 | (*info->fprintf_func) | |
1938 | (info->stream, | |
1939 | _("# internal disassembler error, unrecognised modifier (%c)"), | |
1940 | type); | |
252b5132 RH |
1941 | abort (); |
1942 | } | |
1943 | } | |
640c0ccd | 1944 | |
47b0e7ad NC |
1945 | /* Disassemble mips16 instructions. */ |
1946 | ||
1947 | static int | |
1948 | print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) | |
1949 | { | |
1950 | int status; | |
1951 | bfd_byte buffer[2]; | |
1952 | int length; | |
1953 | int insn; | |
1954 | bfd_boolean use_extend; | |
1955 | int extend = 0; | |
1956 | const struct mips_opcode *op, *opend; | |
1957 | ||
1958 | info->bytes_per_chunk = 2; | |
1959 | info->display_endian = info->endian; | |
1960 | info->insn_info_valid = 1; | |
1961 | info->branch_delay_insns = 0; | |
1962 | info->data_size = 0; | |
1963 | info->insn_type = dis_nonbranch; | |
1964 | info->target = 0; | |
1965 | info->target2 = 0; | |
1966 | ||
1967 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
1968 | if (status != 0) | |
1969 | { | |
1970 | (*info->memory_error_func) (status, memaddr, info); | |
1971 | return -1; | |
1972 | } | |
1973 | ||
1974 | length = 2; | |
1975 | ||
1976 | if (info->endian == BFD_ENDIAN_BIG) | |
1977 | insn = bfd_getb16 (buffer); | |
1978 | else | |
1979 | insn = bfd_getl16 (buffer); | |
1980 | ||
1981 | /* Handle the extend opcode specially. */ | |
1982 | use_extend = FALSE; | |
1983 | if ((insn & 0xf800) == 0xf000) | |
1984 | { | |
1985 | use_extend = TRUE; | |
1986 | extend = insn & 0x7ff; | |
1987 | ||
1988 | memaddr += 2; | |
1989 | ||
1990 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
1991 | if (status != 0) | |
1992 | { | |
1993 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
1994 | (unsigned int) extend); | |
1995 | (*info->memory_error_func) (status, memaddr, info); | |
1996 | return -1; | |
1997 | } | |
1998 | ||
1999 | if (info->endian == BFD_ENDIAN_BIG) | |
2000 | insn = bfd_getb16 (buffer); | |
2001 | else | |
2002 | insn = bfd_getl16 (buffer); | |
2003 | ||
2004 | /* Check for an extend opcode followed by an extend opcode. */ | |
2005 | if ((insn & 0xf800) == 0xf000) | |
2006 | { | |
2007 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
2008 | (unsigned int) extend); | |
2009 | info->insn_type = dis_noninsn; | |
2010 | return length; | |
2011 | } | |
2012 | ||
2013 | length += 2; | |
2014 | } | |
2015 | ||
2016 | /* FIXME: Should probably use a hash table on the major opcode here. */ | |
2017 | ||
2018 | opend = mips16_opcodes + bfd_mips16_num_opcodes; | |
2019 | for (op = mips16_opcodes; op < opend; op++) | |
2020 | { | |
2021 | if (op->pinfo != INSN_MACRO | |
2022 | && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) | |
2023 | && (insn & op->mask) == op->match) | |
2024 | { | |
2025 | const char *s; | |
2026 | ||
2027 | if (strchr (op->args, 'a') != NULL) | |
2028 | { | |
2029 | if (use_extend) | |
2030 | { | |
2031 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
2032 | (unsigned int) extend); | |
2033 | info->insn_type = dis_noninsn; | |
2034 | return length - 2; | |
2035 | } | |
2036 | ||
2037 | use_extend = FALSE; | |
2038 | ||
2039 | memaddr += 2; | |
2040 | ||
2041 | status = (*info->read_memory_func) (memaddr, buffer, 2, | |
2042 | info); | |
2043 | if (status == 0) | |
2044 | { | |
2045 | use_extend = TRUE; | |
2046 | if (info->endian == BFD_ENDIAN_BIG) | |
2047 | extend = bfd_getb16 (buffer); | |
2048 | else | |
2049 | extend = bfd_getl16 (buffer); | |
2050 | length += 2; | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
2055 | if (op->args[0] != '\0') | |
2056 | (*info->fprintf_func) (info->stream, "\t"); | |
2057 | ||
2058 | for (s = op->args; *s != '\0'; s++) | |
2059 | { | |
2060 | if (*s == ',' | |
2061 | && s[1] == 'w' | |
2062 | && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) | |
2063 | == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) | |
2064 | { | |
2065 | /* Skip the register and the comma. */ | |
2066 | ++s; | |
2067 | continue; | |
2068 | } | |
2069 | if (*s == ',' | |
2070 | && s[1] == 'v' | |
2071 | && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) | |
2072 | == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) | |
2073 | { | |
2074 | /* Skip the register and the comma. */ | |
2075 | ++s; | |
2076 | continue; | |
2077 | } | |
2078 | print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, | |
2079 | info); | |
2080 | } | |
2081 | ||
9a2c7088 | 2082 | /* Figure out branch instruction type and delay slot information. */ |
47b0e7ad | 2083 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
9a2c7088 MR |
2084 | info->branch_delay_insns = 1; |
2085 | if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2086 | | MIPS16_INSN_UNCOND_BRANCH)) != 0) | |
47b0e7ad | 2087 | { |
9a2c7088 MR |
2088 | if ((op->pinfo & INSN_WRITE_GPR_31) != 0) |
2089 | info->insn_type = dis_jsr; | |
2090 | else | |
47b0e7ad NC |
2091 | info->insn_type = dis_branch; |
2092 | } | |
9a2c7088 MR |
2093 | else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0) |
2094 | info->insn_type = dis_condbranch; | |
47b0e7ad NC |
2095 | |
2096 | return length; | |
2097 | } | |
2098 | } | |
2099 | ||
2100 | if (use_extend) | |
2101 | (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); | |
2102 | (*info->fprintf_func) (info->stream, "0x%x", insn); | |
2103 | info->insn_type = dis_noninsn; | |
2104 | ||
2105 | return length; | |
2106 | } | |
2107 | ||
2108 | /* In an environment where we do not know the symbol type of the | |
2109 | instruction we are forced to assume that the low order bit of the | |
2110 | instructions' address may mark it as a mips16 instruction. If we | |
2111 | are single stepping, or the pc is within the disassembled function, | |
2112 | this works. Otherwise, we need a clue. Sometimes. */ | |
2113 | ||
2114 | static int | |
2115 | _print_insn_mips (bfd_vma memaddr, | |
2116 | struct disassemble_info *info, | |
2117 | enum bfd_endian endianness) | |
2118 | { | |
2119 | bfd_byte buffer[INSNLEN]; | |
2120 | int status; | |
2121 | ||
2122 | set_default_mips_dis_options (info); | |
2123 | parse_mips_dis_options (info->disassembler_options); | |
2124 | ||
2125 | #if 1 | |
2126 | /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ | |
2127 | /* Only a few tools will work this way. */ | |
2128 | if (memaddr & 0x01) | |
2129 | return print_insn_mips16 (memaddr, info); | |
2130 | #endif | |
2131 | ||
2132 | #if SYMTAB_AVAILABLE | |
2133 | if (info->mach == bfd_mach_mips16 | |
6ba2a415 RS |
2134 | || (info->symbols != NULL |
2135 | && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour | |
30c09090 RS |
2136 | && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols) |
2137 | ->internal_elf_sym.st_other))) | |
47b0e7ad NC |
2138 | return print_insn_mips16 (memaddr, info); |
2139 | #endif | |
2140 | ||
2141 | status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); | |
2142 | if (status == 0) | |
2143 | { | |
2144 | unsigned long insn; | |
2145 | ||
2146 | if (endianness == BFD_ENDIAN_BIG) | |
2147 | insn = (unsigned long) bfd_getb32 (buffer); | |
2148 | else | |
2149 | insn = (unsigned long) bfd_getl32 (buffer); | |
2150 | ||
2151 | return print_insn_mips (memaddr, insn, info); | |
2152 | } | |
2153 | else | |
2154 | { | |
2155 | (*info->memory_error_func) (status, memaddr, info); | |
2156 | return -1; | |
2157 | } | |
2158 | } | |
2159 | ||
2160 | int | |
2161 | print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) | |
2162 | { | |
2163 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); | |
2164 | } | |
2165 | ||
2166 | int | |
2167 | print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) | |
2168 | { | |
2169 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); | |
2170 | } | |
2171 | \f | |
640c0ccd | 2172 | void |
47b0e7ad | 2173 | print_mips_disassembler_options (FILE *stream) |
640c0ccd | 2174 | { |
4a9a3c54 | 2175 | unsigned int i; |
640c0ccd CD |
2176 | |
2177 | fprintf (stream, _("\n\ | |
2178 | The following MIPS specific disassembler options are supported for use\n\ | |
2179 | with the -M switch (multiple options should be separated by commas):\n")); | |
2180 | ||
2181 | fprintf (stream, _("\n\ | |
2182 | gpr-names=ABI Print GPR names according to specified ABI.\n\ | |
2183 | Default: based on binary being disassembled.\n")); | |
2184 | ||
2185 | fprintf (stream, _("\n\ | |
2186 | fpr-names=ABI Print FPR names according to specified ABI.\n\ | |
2187 | Default: numeric.\n")); | |
2188 | ||
2189 | fprintf (stream, _("\n\ | |
2190 | cp0-names=ARCH Print CP0 register names according to\n\ | |
2191 | specified architecture.\n\ | |
2192 | Default: based on binary being disassembled.\n")); | |
2193 | ||
af7ee8bf CD |
2194 | fprintf (stream, _("\n\ |
2195 | hwr-names=ARCH Print HWR names according to specified \n\ | |
2196 | architecture.\n\ | |
2197 | Default: based on binary being disassembled.\n")); | |
2198 | ||
640c0ccd CD |
2199 | fprintf (stream, _("\n\ |
2200 | reg-names=ABI Print GPR and FPR names according to\n\ | |
2201 | specified ABI.\n")); | |
2202 | ||
2203 | fprintf (stream, _("\n\ | |
af7ee8bf | 2204 | reg-names=ARCH Print CP0 register and HWR names according to\n\ |
640c0ccd CD |
2205 | specified architecture.\n")); |
2206 | ||
2207 | fprintf (stream, _("\n\ | |
2208 | For the options above, the following values are supported for \"ABI\":\n\ | |
2209 | ")); | |
4a9a3c54 | 2210 | for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) |
640c0ccd CD |
2211 | fprintf (stream, " %s", mips_abi_choices[i].name); |
2212 | fprintf (stream, _("\n")); | |
2213 | ||
2214 | fprintf (stream, _("\n\ | |
2215 | For the options above, The following values are supported for \"ARCH\":\n\ | |
2216 | ")); | |
4a9a3c54 | 2217 | for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) |
640c0ccd CD |
2218 | if (*mips_arch_choices[i].name != '\0') |
2219 | fprintf (stream, " %s", mips_arch_choices[i].name); | |
2220 | fprintf (stream, _("\n")); | |
2221 | ||
2222 | fprintf (stream, _("\n")); | |
2223 | } |