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* mips-dis.c (print_insn_args): Print $fcc only for FP
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
CommitLineData
252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
060d22b0 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2005
73da6b6b 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
47b0e7ad 7 This file is part of GDB, GAS, and the GNU binutils.
252b5132 8
47b0e7ad
NC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
252b5132 13
47b0e7ad
NC		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
252b5132 18
47b0e7ad
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
252b5132
RH		 24#include "sysdep.h"
25#include "dis-asm.h"
640c0ccd 26#include "libiberty.h"
252b5132
RH		 27#include "opcode/mips.h"
28#include "opintl.h"
29
30/* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
7f6621cd 33 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 34
35#if !defined(EMBEDDED_ENV)
36#define SYMTAB_AVAILABLE 1
37#include "elf-bfd.h"
38#include "elf/mips.h"
39#endif
40
aa5f19f2
NC		 41/* Mips instructions are at maximum this many bytes long. */
42#define INSNLEN 4
43
252b5132 44\f
aa5f19f2 45/* FIXME: These should be shared with gdb somehow. */
252b5132 46
47b0e7ad
NC		 47struct mips_cp0sel_name
48{
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
bbcc0807
CD		 52};
53
654c225a
TS		 54/* The mips16 registers. */
55static const unsigned int mips16_to_32_reg_map[] =
47b0e7ad 56{
654c225a 57 16, 17, 2, 3, 4, 5, 6, 7
252b5132 58};
fb48caed 59
654c225a
TS		 60#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
47b0e7ad
NC		 63static const char * const mips_gpr_names_numeric[32] =
64{
640c0ccd
CD		 65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 69};
70
47b0e7ad
NC		 71static const char * const mips_gpr_names_oldabi[32] =
72{
640c0ccd
CD		 73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 77};
78
47b0e7ad
NC		 79static const char * const mips_gpr_names_newabi[32] =
80{
640c0ccd 81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
0b14f26e 82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
640c0ccd
CD		 83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85};
86
47b0e7ad
NC		 87static const char * const mips_fpr_names_numeric[32] =
88{
640c0ccd
CD		 89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93};
94
47b0e7ad
NC		 95static const char * const mips_fpr_names_32[32] =
96{
640c0ccd
CD		 97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101};
102
47b0e7ad
NC		 103static const char * const mips_fpr_names_n32[32] =
104{
640c0ccd
CD		 105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109};
110
47b0e7ad
NC		 111static const char * const mips_fpr_names_64[32] =
112{
640c0ccd
CD		 113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117};
118
47b0e7ad
NC		 119static const char * const mips_cp0_names_numeric[32] =
120{
640c0ccd
CD		 121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125};
126
47b0e7ad
NC		 127static const char * const mips_cp0_names_mips3264[32] =
128{
640c0ccd
CD		 129 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
130 "c0_context", "c0_pagemask", "c0_wired", "$7",
131 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
132 "c0_status", "c0_cause", "c0_epc", "c0_prid",
133 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
134 "c0_xcontext", "$21", "$22", "c0_debug",
135 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
136 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
137};
138
47b0e7ad
NC		 139static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
140{
bbcc0807
CD		 141 { 16, 1, "c0_config1" },
142 { 16, 2, "c0_config2" },
143 { 16, 3, "c0_config3" },
144 { 18, 1, "c0_watchlo,1" },
145 { 18, 2, "c0_watchlo,2" },
146 { 18, 3, "c0_watchlo,3" },
147 { 18, 4, "c0_watchlo,4" },
148 { 18, 5, "c0_watchlo,5" },
149 { 18, 6, "c0_watchlo,6" },
150 { 18, 7, "c0_watchlo,7" },
151 { 19, 1, "c0_watchhi,1" },
152 { 19, 2, "c0_watchhi,2" },
153 { 19, 3, "c0_watchhi,3" },
154 { 19, 4, "c0_watchhi,4" },
155 { 19, 5, "c0_watchhi,5" },
156 { 19, 6, "c0_watchhi,6" },
157 { 19, 7, "c0_watchhi,7" },
158 { 25, 1, "c0_perfcnt,1" },
159 { 25, 2, "c0_perfcnt,2" },
160 { 25, 3, "c0_perfcnt,3" },
161 { 25, 4, "c0_perfcnt,4" },
162 { 25, 5, "c0_perfcnt,5" },
163 { 25, 6, "c0_perfcnt,6" },
164 { 25, 7, "c0_perfcnt,7" },
165 { 27, 1, "c0_cacheerr,1" },
166 { 27, 2, "c0_cacheerr,2" },
167 { 27, 3, "c0_cacheerr,3" },
168 { 28, 1, "c0_datalo" },
169 { 29, 1, "c0_datahi" }
170};
171
47b0e7ad
NC		 172static const char * const mips_cp0_names_mips3264r2[32] =
173{
af7ee8bf
CD		 174 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
175 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
176 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
177 "c0_status", "c0_cause", "c0_epc", "c0_prid",
178 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
179 "c0_xcontext", "$21", "$22", "c0_debug",
180 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
181 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
182};
183
47b0e7ad
NC		 184static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
185{
bbcc0807
CD		 186 { 4, 1, "c0_contextconfig" },
187 { 5, 1, "c0_pagegrain" },
188 { 12, 1, "c0_intctl" },
189 { 12, 2, "c0_srsctl" },
190 { 12, 3, "c0_srsmap" },
191 { 15, 1, "c0_ebase" },
192 { 16, 1, "c0_config1" },
193 { 16, 2, "c0_config2" },
194 { 16, 3, "c0_config3" },
195 { 18, 1, "c0_watchlo,1" },
196 { 18, 2, "c0_watchlo,2" },
197 { 18, 3, "c0_watchlo,3" },
198 { 18, 4, "c0_watchlo,4" },
199 { 18, 5, "c0_watchlo,5" },
200 { 18, 6, "c0_watchlo,6" },
201 { 18, 7, "c0_watchlo,7" },
202 { 19, 1, "c0_watchhi,1" },
203 { 19, 2, "c0_watchhi,2" },
204 { 19, 3, "c0_watchhi,3" },
205 { 19, 4, "c0_watchhi,4" },
206 { 19, 5, "c0_watchhi,5" },
207 { 19, 6, "c0_watchhi,6" },
208 { 19, 7, "c0_watchhi,7" },
209 { 23, 1, "c0_tracecontrol" },
210 { 23, 2, "c0_tracecontrol2" },
211 { 23, 3, "c0_usertracedata" },
212 { 23, 4, "c0_tracebpc" },
213 { 25, 1, "c0_perfcnt,1" },
214 { 25, 2, "c0_perfcnt,2" },
215 { 25, 3, "c0_perfcnt,3" },
216 { 25, 4, "c0_perfcnt,4" },
217 { 25, 5, "c0_perfcnt,5" },
218 { 25, 6, "c0_perfcnt,6" },
219 { 25, 7, "c0_perfcnt,7" },
220 { 27, 1, "c0_cacheerr,1" },
221 { 27, 2, "c0_cacheerr,2" },
222 { 27, 3, "c0_cacheerr,3" },
223 { 28, 1, "c0_datalo" },
224 { 28, 2, "c0_taglo1" },
225 { 28, 3, "c0_datalo1" },
226 { 28, 4, "c0_taglo2" },
227 { 28, 5, "c0_datalo2" },
228 { 28, 6, "c0_taglo3" },
229 { 28, 7, "c0_datalo3" },
230 { 29, 1, "c0_datahi" },
231 { 29, 2, "c0_taghi1" },
232 { 29, 3, "c0_datahi1" },
233 { 29, 4, "c0_taghi2" },
234 { 29, 5, "c0_datahi2" },
235 { 29, 6, "c0_taghi3" },
236 { 29, 7, "c0_datahi3" },
237};
238
640c0ccd 239/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
47b0e7ad
NC		 240static const char * const mips_cp0_names_sb1[32] =
241{
640c0ccd
CD		 242 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
243 "c0_context", "c0_pagemask", "c0_wired", "$7",
244 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
245 "c0_status", "c0_cause", "c0_epc", "c0_prid",
246 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
247 "c0_xcontext", "$21", "$22", "c0_debug",
248 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
249 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
250};
251
47b0e7ad
NC		 252static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
253{
bbcc0807
CD		 254 { 16, 1, "c0_config1" },
255 { 18, 1, "c0_watchlo,1" },
256 { 19, 1, "c0_watchhi,1" },
257 { 22, 0, "c0_perftrace" },
258 { 23, 3, "c0_edebug" },
259 { 25, 1, "c0_perfcnt,1" },
260 { 25, 2, "c0_perfcnt,2" },
261 { 25, 3, "c0_perfcnt,3" },
262 { 25, 4, "c0_perfcnt,4" },
263 { 25, 5, "c0_perfcnt,5" },
264 { 25, 6, "c0_perfcnt,6" },
265 { 25, 7, "c0_perfcnt,7" },
266 { 26, 1, "c0_buserr_pa" },
267 { 27, 1, "c0_cacheerr_d" },
268 { 27, 3, "c0_cacheerr_d_pa" },
269 { 28, 1, "c0_datalo_i" },
270 { 28, 2, "c0_taglo_d" },
271 { 28, 3, "c0_datalo_d" },
272 { 29, 1, "c0_datahi_i" },
273 { 29, 2, "c0_taghi_d" },
274 { 29, 3, "c0_datahi_d" },
275};
276
47b0e7ad
NC		 277static const char * const mips_hwr_names_numeric[32] =
278{
af7ee8bf
CD		 279 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
280 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
281 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
282 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
283};
284
47b0e7ad
NC		 285static const char * const mips_hwr_names_mips3264r2[32] =
286{
af7ee8bf
CD		 287 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
288 "$4", "$5", "$6", "$7",
289 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
290 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
291 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
292};
293
47b0e7ad
NC		 294struct mips_abi_choice
295{
296 const char * name;
640c0ccd
CD		 297 const char * const *gpr_names;
298 const char * const *fpr_names;
299};
300
47b0e7ad
NC		 301struct mips_abi_choice mips_abi_choices[] =
302{
640c0ccd
CD		 303 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
304 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
305 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
306 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
307};
308
47b0e7ad
NC		 309struct mips_arch_choice
310{
640c0ccd
CD		 311 const char *name;
312 int bfd_mach_valid;
313 unsigned long bfd_mach;
314 int processor;
315 int isa;
316 const char * const *cp0_names;
bbcc0807
CD		 317 const struct mips_cp0sel_name *cp0sel_names;
318 unsigned int cp0sel_names_len;
af7ee8bf 319 const char * const *hwr_names;
640c0ccd
CD		 320};
321
47b0e7ad
NC		 322const struct mips_arch_choice mips_arch_choices[] =
323{
640c0ccd 324 { "numeric", 0, 0, 0, 0,
bbcc0807
CD		 325 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
326
640c0ccd 327 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
bbcc0807 328 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 329 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
bbcc0807 330 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 331 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
bbcc0807 332 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 333 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
bbcc0807 334 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 335 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
bbcc0807 336 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 337 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
bbcc0807 338 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 339 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
bbcc0807 340 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 341 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
bbcc0807 342 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 343 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
bbcc0807 344 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 345 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
bbcc0807 346 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 347 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
bbcc0807 348 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 349 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
bbcc0807 350 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 351 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
bbcc0807 352 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 353 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
bbcc0807 354 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 355 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
bbcc0807 356 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
5a7ea749
RS		 357 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
358 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
359 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
360 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 361 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
bbcc0807 362 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 363 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
bbcc0807 364 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 365 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
bbcc0807 366 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 367 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
bbcc0807
CD		 368 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
369
640c0ccd
CD		 370 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
371 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
372 _MIPS32 Architecture For Programmers Volume I: Introduction to the
373 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
374 page 1. */
375 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
fd25c5a9 376 ISA_MIPS32 | INSN_MIPS16 | INSN_DSP,
bbcc0807
CD		 377 mips_cp0_names_mips3264,
378 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
379 mips_hwr_names_numeric },
380
af7ee8bf 381 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
61cc0267 382 ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
bbcc0807
CD		 383 mips_cp0_names_mips3264r2,
384 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
385 mips_hwr_names_mips3264r2 },
386
640c0ccd
CD		 387 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
388 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
fd25c5a9 389 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
bbcc0807
CD		 390 mips_cp0_names_mips3264,
391 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
392 mips_hwr_names_numeric },
393
5f74bc13 394 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
fd25c5a9 395 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
5f74bc13
CD		 396 mips_cp0_names_mips3264r2,
397 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
398 mips_hwr_names_mips3264r2 },
399
640c0ccd
CD		 400 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
401 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
bbcc0807
CD		 402 mips_cp0_names_sb1,
403 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
404 mips_hwr_names_numeric },
640c0ccd
CD		 405
406 /* This entry, mips16, is here only for ISA/processor selection; do
407 not print its name. */
408 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
bbcc0807 409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd
CD		 410};
411
412/* ISA and processor type to disassemble for, and register names to use.
413 set_default_mips_dis_options and parse_mips_dis_options fill in these
414 values. */
415static int mips_processor;
416static int mips_isa;
417static const char * const *mips_gpr_names;
418static const char * const *mips_fpr_names;
419static const char * const *mips_cp0_names;
bbcc0807
CD		 420static const struct mips_cp0sel_name *mips_cp0sel_names;
421static int mips_cp0sel_names_len;
af7ee8bf 422static const char * const *mips_hwr_names;
640c0ccd 423
986e18a5 424/* Other options */
47b0e7ad 425static int no_aliases; /* If set disassemble as most general inst. */
640c0ccd
CD		 426\f
427static const struct mips_abi_choice *
47b0e7ad 428choose_abi_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 429{
430 const struct mips_abi_choice *c;
431 unsigned int i;
432
433 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
47b0e7ad
NC		 434 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
435 && strlen (mips_abi_choices[i].name) == namelen)
436 c = &mips_abi_choices[i];
437
640c0ccd
CD		 438 return c;
439}
440
441static const struct mips_arch_choice *
47b0e7ad 442choose_arch_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 443{
444 const struct mips_arch_choice *c = NULL;
445 unsigned int i;
446
447 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
47b0e7ad
NC		 448 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
449 && strlen (mips_arch_choices[i].name) == namelen)
450 c = &mips_arch_choices[i];
451
640c0ccd
CD		 452 return c;
453}
454
455static const struct mips_arch_choice *
47b0e7ad 456choose_arch_by_number (unsigned long mach)
640c0ccd
CD		 457{
458 static unsigned long hint_bfd_mach;
459 static const struct mips_arch_choice *hint_arch_choice;
460 const struct mips_arch_choice *c;
461 unsigned int i;
462
463 /* We optimize this because even if the user specifies no
464 flags, this will be done for every instruction! */
465 if (hint_bfd_mach == mach
466 && hint_arch_choice != NULL
467 && hint_arch_choice->bfd_mach == hint_bfd_mach)
468 return hint_arch_choice;
469
470 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
471 {
472 if (mips_arch_choices[i].bfd_mach_valid
473 && mips_arch_choices[i].bfd_mach == mach)
474 {
475 c = &mips_arch_choices[i];
476 hint_bfd_mach = mach;
477 hint_arch_choice = c;
478 }
479 }
480 return c;
481}
482
47b0e7ad
NC		 483/* Check if the object uses NewABI conventions. */
484
485static int
486is_newabi (Elf_Internal_Ehdr *header)
487{
488 /* There are no old-style ABIs which use 64-bit ELF. */
489 if (header->e_ident[EI_CLASS] == ELFCLASS64)
490 return 1;
491
492 /* If a 32-bit ELF file, n32 is a new-style ABI. */
493 if ((header->e_flags & EF_MIPS_ABI2) != 0)
494 return 1;
495
496 return 0;
497}
498
499static void
500set_default_mips_dis_options (struct disassemble_info *info)
640c0ccd
CD		 501{
502 const struct mips_arch_choice *chosen_arch;
503
504 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
af7ee8bf 505 and numeric FPR, CP0 register, and HWR names. */
640c0ccd
CD		 506 mips_isa = ISA_MIPS3;
507 mips_processor = CPU_R3000;
508 mips_gpr_names = mips_gpr_names_oldabi;
509 mips_fpr_names = mips_fpr_names_numeric;
510 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 511 mips_cp0sel_names = NULL;
512 mips_cp0sel_names_len = 0;
af7ee8bf 513 mips_hwr_names = mips_hwr_names_numeric;
986e18a5 514 no_aliases = 0;
640c0ccd
CD		 515
516 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
fec06546 517 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
640c0ccd
CD		 518 {
519 Elf_Internal_Ehdr *header;
520
fec06546 521 header = elf_elfheader (info->section->owner);
640c0ccd
CD		 522 if (is_newabi (header))
523 mips_gpr_names = mips_gpr_names_newabi;
524 }
525
526 /* Set ISA, architecture, and cp0 register names as best we can. */
527#if ! SYMTAB_AVAILABLE
528 /* This is running out on a target machine, not in a host tool.
529 FIXME: Where does mips_target_info come from? */
530 target_processor = mips_target_info.processor;
531 mips_isa = mips_target_info.isa;
532#else
533 chosen_arch = choose_arch_by_number (info->mach);
534 if (chosen_arch != NULL)
535 {
536 mips_processor = chosen_arch->processor;
537 mips_isa = chosen_arch->isa;
bbcc0807
CD		 538 mips_cp0_names = chosen_arch->cp0_names;
539 mips_cp0sel_names = chosen_arch->cp0sel_names;
540 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
541 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 542 }
543#endif
544}
545
47b0e7ad
NC		 546static void
547parse_mips_dis_option (const char *option, unsigned int len)
640c0ccd
CD		 548{
549 unsigned int i, optionlen, vallen;
550 const char *val;
551 const struct mips_abi_choice *chosen_abi;
552 const struct mips_arch_choice *chosen_arch;
553
986e18a5
FF		 554 /* Try to match options that are simple flags */
555 if (strncmp (option, "no-aliases", 10) == 0)
556 {
557 no_aliases = 1;
558 return;
559 }
560
640c0ccd
CD		 561 /* Look for the = that delimits the end of the option name. */
562 for (i = 0; i < len; i++)
47b0e7ad
NC		 563 if (option[i] == '=')
564 break;
565
640c0ccd
CD		 566 if (i == 0) /* Invalid option: no name before '='. */
567 return;
568 if (i == len) /* Invalid option: no '='. */
569 return;
570 if (i == (len - 1)) /* Invalid option: no value after '='. */
571 return;
572
573 optionlen = i;
574 val = option + (optionlen + 1);
575 vallen = len - (optionlen + 1);
576
47b0e7ad
NC		 577 if (strncmp ("gpr-names", option, optionlen) == 0
578 && strlen ("gpr-names") == optionlen)
640c0ccd
CD		 579 {
580 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 581 if (chosen_abi != NULL)
640c0ccd
CD		 582 mips_gpr_names = chosen_abi->gpr_names;
583 return;
584 }
585
47b0e7ad
NC		 586 if (strncmp ("fpr-names", option, optionlen) == 0
587 && strlen ("fpr-names") == optionlen)
640c0ccd
CD		 588 {
589 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 590 if (chosen_abi != NULL)
640c0ccd
CD		 591 mips_fpr_names = chosen_abi->fpr_names;
592 return;
593 }
594
47b0e7ad
NC		 595 if (strncmp ("cp0-names", option, optionlen) == 0
596 && strlen ("cp0-names") == optionlen)
640c0ccd
CD		 597 {
598 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 599 if (chosen_arch != NULL)
600 {
601 mips_cp0_names = chosen_arch->cp0_names;
602 mips_cp0sel_names = chosen_arch->cp0sel_names;
603 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
604 }
640c0ccd
CD		 605 return;
606 }
607
47b0e7ad
NC		 608 if (strncmp ("hwr-names", option, optionlen) == 0
609 && strlen ("hwr-names") == optionlen)
af7ee8bf
CD		 610 {
611 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 612 if (chosen_arch != NULL)
af7ee8bf
CD		 613 mips_hwr_names = chosen_arch->hwr_names;
614 return;
615 }
616
47b0e7ad
NC		 617 if (strncmp ("reg-names", option, optionlen) == 0
618 && strlen ("reg-names") == optionlen)
640c0ccd
CD		 619 {
620 /* We check both ABI and ARCH here unconditionally, so
621 that "numeric" will do the desirable thing: select
622 numeric register names for all registers. Other than
623 that, a given name probably won't match both. */
624 chosen_abi = choose_abi_by_name (val, vallen);
625 if (chosen_abi != NULL)
626 {
bbcc0807
CD		 627 mips_gpr_names = chosen_abi->gpr_names;
628 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 629 }
630 chosen_arch = choose_arch_by_name (val, vallen);
631 if (chosen_arch != NULL)
632 {
bbcc0807
CD		 633 mips_cp0_names = chosen_arch->cp0_names;
634 mips_cp0sel_names = chosen_arch->cp0sel_names;
635 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
636 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 637 }
638 return;
639 }
640
641 /* Invalid option. */
642}
643
47b0e7ad
NC		 644static void
645parse_mips_dis_options (const char *options)
640c0ccd
CD		 646{
647 const char *option_end;
648
649 if (options == NULL)
650 return;
651
652 while (*options != '\0')
653 {
654 /* Skip empty options. */
655 if (*options == ',')
656 {
657 options++;
658 continue;
659 }
660
661 /* We know that *options is neither NUL or a comma. */
662 option_end = options + 1;
663 while (*option_end != ',' && *option_end != '\0')
664 option_end++;
665
666 parse_mips_dis_option (options, option_end - options);
667
668 /* Go on to the next one. If option_end points to a comma, it
669 will be skipped above. */
670 options = option_end;
671 }
672}
673
bbcc0807 674static const struct mips_cp0sel_name *
47b0e7ad
NC		 675lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
676 unsigned int len,
677 unsigned int cp0reg,
678 unsigned int sel)
bbcc0807
CD		 679{
680 unsigned int i;
681
682 for (i = 0; i < len; i++)
683 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
684 return &names[i];
685 return NULL;
686}
252b5132 687\f
7f6621cd 688/* Print insn arguments for 32/64-bit code. */
aa5f19f2 689
794ac9d0 690static void
47b0e7ad
NC		 691print_insn_args (const char *d,
692 register unsigned long int l,
693 bfd_vma pc,
694 struct disassemble_info *info)
252b5132 695{
794ac9d0 696 int op, delta;
440cc0bc
CD		 697 unsigned int lsb, msb, msbd;
698
699 lsb = 0;
252b5132 700
794ac9d0 701 for (; *d != '\0'; d++)
252b5132 702 {
af7ee8bf
CD		 703 switch (*d)
704 {
794ac9d0
CD		 705 case ',':
706 case '(':
707 case ')':
708 case '[':
709 case ']':
710 (*info->fprintf_func) (info->stream, "%c", *d);
711 break;
712
713 case '+':
714 /* Extension character; switch for second char. */
715 d++;
716 switch (*d)
717 {
718 case '\0':
719 /* xgettext:c-format */
720 (*info->fprintf_func) (info->stream,
721 _("# internal error, incomplete extension sequence (+)"));
722 return;
723
724 case 'A':
440cc0bc
CD		 725 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
726 (*info->fprintf_func) (info->stream, "0x%x", lsb);
794ac9d0
CD		 727 break;
728
729 case 'B':
440cc0bc
CD		 730 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
731 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
794ac9d0
CD		 732 break;
733
734 case 'C':
5f74bc13 735 case 'H':
440cc0bc
CD		 736 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
737 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
794ac9d0
CD		 738 break;
739
740 case 'D':
741 {
742 const struct mips_cp0sel_name *n;
743 unsigned int cp0reg, sel;
744
745 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
746 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
747
748 /* CP0 register including 'sel' code for mtcN (et al.), to be
749 printed textually if known. If not known, print both
750 CP0 register name and sel numerically since CP0 register
751 with sel 0 may have a name unrelated to register being
752 printed. */
753 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
754 mips_cp0sel_names_len, cp0reg, sel);
755 if (n != NULL)
756 (*info->fprintf_func) (info->stream, "%s", n->name);
757 else
758 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
759 break;
760 }
761
5f74bc13
CD		 762 case 'E':
763 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
764 (*info->fprintf_func) (info->stream, "0x%x", lsb);
765 break;
766
767 case 'F':
768 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
769 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
770 break;
771
772 case 'G':
773 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
774 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
775 break;
776
61cc0267
CF		 777 case 't': /* Coprocessor 0 reg name */
778 (*info->fprintf_func) (info->stream, "%s",
779 mips_cp0_names[(l >> OP_SH_RT) &
780 OP_MASK_RT]);
781 break;
782
783 case 'T': /* Coprocessor 0 reg name */
784 {
785 const struct mips_cp0sel_name *n;
786 unsigned int cp0reg, sel;
787
788 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
789 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
790
791 /* CP0 register including 'sel' code for mftc0, to be
792 printed textually if known. If not known, print both
793 CP0 register name and sel numerically since CP0 register
794 with sel 0 may have a name unrelated to register being
795 printed. */
796 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
797 mips_cp0sel_names_len, cp0reg, sel);
798 if (n != NULL)
799 (*info->fprintf_func) (info->stream, "%s", n->name);
800 else
801 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
802 break;
803 }
804
794ac9d0
CD		 805 default:
806 /* xgettext:c-format */
807 (*info->fprintf_func) (info->stream,
808 _("# internal error, undefined extension sequence (+%c)"),
809 *d);
810 return;
811 }
812 break;
813
fd25c5a9
CF		 814 case '3':
815 (*info->fprintf_func) (info->stream, "0x%lx",
816 (l >> OP_SH_SA3) & OP_MASK_SA3);
817 break;
818
819 case '4':
820 (*info->fprintf_func) (info->stream, "0x%lx",
821 (l >> OP_SH_SA4) & OP_MASK_SA4);
822 break;
823
824 case '5':
825 (*info->fprintf_func) (info->stream, "0x%lx",
826 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
827 break;
828
829 case '6':
830 (*info->fprintf_func) (info->stream, "0x%lx",
831 (l >> OP_SH_RS) & OP_MASK_RS);
832 break;
833
834 case '7':
835 (*info->fprintf_func) (info->stream, "$ac%ld",
836 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
837 break;
838
839 case '8':
840 (*info->fprintf_func) (info->stream, "0x%lx",
841 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
842 break;
843
844 case '9':
845 (*info->fprintf_func) (info->stream, "$ac%ld",
846 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
847 break;
848
849 case '0': /* dsp 6-bit signed immediate in bit 20 */
850 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
851 if (delta & 0x20) /* test sign bit */
852 delta |= ~OP_MASK_DSPSFT;
853 (*info->fprintf_func) (info->stream, "%d", delta);
854 break;
855
856 case ':': /* dsp 7-bit signed immediate in bit 19 */
857 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
858 if (delta & 0x40) /* test sign bit */
859 delta |= ~OP_MASK_DSPSFT_7;
860 (*info->fprintf_func) (info->stream, "%d", delta);
861 break;
862
863 case '\'':
864 (*info->fprintf_func) (info->stream, "0x%lx",
865 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
866 break;
867
868 case '@': /* dsp 10-bit signed immediate in bit 16 */
869 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
870 if (delta & 0x200) /* test sign bit */
871 delta |= ~OP_MASK_IMM10;
872 (*info->fprintf_func) (info->stream, "%d", delta);
873 break;
874
61cc0267
CF		 875 case '!':
876 (*info->fprintf_func) (info->stream, "%ld",
877 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
878 break;
879
880 case '$':
881 (*info->fprintf_func) (info->stream, "%ld",
882 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
883 break;
884
885 case '*':
886 (*info->fprintf_func) (info->stream, "$ac%ld",
887 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
888 break;
889
890 case '&':
891 (*info->fprintf_func) (info->stream, "$ac%ld",
892 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
893 break;
894
895 case 'g':
896 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
897 (*info->fprintf_func) (info->stream, "$%ld",
898 (l >> OP_SH_RD) & OP_MASK_RD);
899 break;
900
794ac9d0
CD		 901 case 's':
902 case 'b':
903 case 'r':
904 case 'v':
905 (*info->fprintf_func) (info->stream, "%s",
906 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
907 break;
908
909 case 't':
910 case 'w':
911 (*info->fprintf_func) (info->stream, "%s",
912 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
913 break;
914
915 case 'i':
916 case 'u':
0fd3a477 917 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 918 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
919 break;
920
921 case 'j': /* Same as i, but sign-extended. */
922 case 'o':
923 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
924 if (delta & 0x8000)
925 delta |= ~0xffff;
926 (*info->fprintf_func) (info->stream, "%d",
927 delta);
928 break;
929
930 case 'h':
931 (*info->fprintf_func) (info->stream, "0x%x",
932 (unsigned int) ((l >> OP_SH_PREFX)
933 & OP_MASK_PREFX));
934 break;
935
936 case 'k':
937 (*info->fprintf_func) (info->stream, "0x%x",
938 (unsigned int) ((l >> OP_SH_CACHE)
939 & OP_MASK_CACHE));
940 break;
941
942 case 'a':
943 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
944 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
945 (*info->print_address_func) (info->target, info);
946 break;
947
948 case 'p':
949 /* Sign extend the displacement. */
950 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
951 if (delta & 0x8000)
952 delta |= ~0xffff;
953 info->target = (delta << 2) + pc + INSNLEN;
954 (*info->print_address_func) (info->target, info);
955 break;
956
957 case 'd':
958 (*info->fprintf_func) (info->stream, "%s",
959 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
960 break;
961
962 case 'U':
963 {
964 /* First check for both rd and rt being equal. */
965 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
966 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
967 (*info->fprintf_func) (info->stream, "%s",
968 mips_gpr_names[reg]);
969 else
970 {
971 /* If one is zero use the other. */
972 if (reg == 0)
973 (*info->fprintf_func) (info->stream, "%s",
974 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
975 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
976 (*info->fprintf_func) (info->stream, "%s",
977 mips_gpr_names[reg]);
978 else /* Bogus, result depends on processor. */
979 (*info->fprintf_func) (info->stream, "%s or %s",
980 mips_gpr_names[reg],
981 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
982 }
983 }
984 break;
985
986 case 'z':
987 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
988 break;
989
990 case '<':
0fd3a477 991 (*info->fprintf_func) (info->stream, "0x%lx",
af7ee8bf
CD		 992 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
993 break;
794ac9d0
CD		 994
995 case 'c':
0fd3a477 996 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 997 (l >> OP_SH_CODE) & OP_MASK_CODE);
998 break;
999
1000 case 'q':
0fd3a477 1001 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0 1002 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
af7ee8bf
CD		 1003 break;
1004
1005 case 'C':
0fd3a477 1006 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1007 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1008 break;
1009
1010 case 'B':
0fd3a477
JW		 1011 (*info->fprintf_func) (info->stream, "0x%lx",
1012
794ac9d0
CD		 1013 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1014 break;
1015
1016 case 'J':
0fd3a477 1017 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1018 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1019 break;
1020
1021 case 'S':
1022 case 'V':
1023 (*info->fprintf_func) (info->stream, "%s",
1024 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1025 break;
1026
1027 case 'T':
1028 case 'W':
1029 (*info->fprintf_func) (info->stream, "%s",
1030 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
af7ee8bf
CD		 1031 break;
1032
bbcc0807 1033 case 'D':
794ac9d0
CD		 1034 (*info->fprintf_func) (info->stream, "%s",
1035 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1036 break;
1037
1038 case 'R':
1039 (*info->fprintf_func) (info->stream, "%s",
1040 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1041 break;
1042
1043 case 'E':
1044 /* Coprocessor register for lwcN instructions, et al.
1045
1046 Note that there is no load/store cp0 instructions, and
1047 that FPU (cp1) instructions disassemble this field using
1048 'T' format. Therefore, until we gain understanding of
1049 cp2 register names, we can simply print the register
1050 numbers. */
0fd3a477 1051 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1052 (l >> OP_SH_RT) & OP_MASK_RT);
1053 break;
1054
1055 case 'G':
1056 /* Coprocessor register for mtcN instructions, et al. Note
1057 that FPU (cp1) instructions disassemble this field using
1058 'S' format. Therefore, we only need to worry about cp0,
1059 cp2, and cp3. */
1060 op = (l >> OP_SH_OP) & OP_MASK_OP;
1061 if (op == OP_OP_COP0)
1062 (*info->fprintf_func) (info->stream, "%s",
1063 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1064 else
0fd3a477 1065 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1066 (l >> OP_SH_RD) & OP_MASK_RD);
1067 break;
1068
1069 case 'K':
1070 (*info->fprintf_func) (info->stream, "%s",
1071 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1072 break;
1073
1074 case 'N':
0d09bfe6
TS		 1075 (*info->fprintf_func) (info->stream,
1076 ((opp->pinfo & (FP_D | FP_S)) != 0
1077 ? "$fcc%ld" : "$cc%ld"),
794ac9d0
CD		 1078 (l >> OP_SH_BCC) & OP_MASK_BCC);
1079 break;
1080
1081 case 'M':
0fd3a477 1082 (*info->fprintf_func) (info->stream, "$fcc%ld",
794ac9d0
CD		 1083 (l >> OP_SH_CCC) & OP_MASK_CCC);
1084 break;
1085
1086 case 'P':
0fd3a477 1087 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1088 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1089 break;
1090
1091 case 'e':
0fd3a477 1092 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1093 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1094 break;
1095
1096 case '%':
0fd3a477 1097 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1098 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1099 break;
1100
1101 case 'H':
0fd3a477 1102 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1103 (l >> OP_SH_SEL) & OP_MASK_SEL);
1104 break;
1105
1106 case 'O':
0fd3a477 1107 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1108 (l >> OP_SH_ALN) & OP_MASK_ALN);
1109 break;
1110
1111 case 'Q':
bbcc0807 1112 {
794ac9d0 1113 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
47b0e7ad 1114
794ac9d0
CD		 1115 if ((vsel & 0x10) == 0)
1116 {
1117 int fmt;
47b0e7ad 1118
794ac9d0
CD		 1119 vsel &= 0x0f;
1120 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1121 if ((vsel & 1) == 0)
1122 break;
0fd3a477 1123 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
794ac9d0
CD		 1124 (l >> OP_SH_FT) & OP_MASK_FT,
1125 vsel >> 1);
1126 }
1127 else if ((vsel & 0x08) == 0)
1128 {
0fd3a477 1129 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1130 (l >> OP_SH_FT) & OP_MASK_FT);
1131 }
bbcc0807 1132 else
794ac9d0 1133 {
0fd3a477 1134 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1135 (l >> OP_SH_FT) & OP_MASK_FT);
1136 }
bbcc0807 1137 }
794ac9d0
CD		 1138 break;
1139
1140 case 'X':
0fd3a477 1141 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1142 (l >> OP_SH_FD) & OP_MASK_FD);
1143 break;
1144
1145 case 'Y':
0fd3a477 1146 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1147 (l >> OP_SH_FS) & OP_MASK_FS);
1148 break;
1149
1150 case 'Z':
0fd3a477 1151 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1152 (l >> OP_SH_FT) & OP_MASK_FT);
1153 break;
bbcc0807 1154
af7ee8bf
CD		 1155 default:
1156 /* xgettext:c-format */
1157 (*info->fprintf_func) (info->stream,
794ac9d0 1158 _("# internal error, undefined modifier(%c)"),
af7ee8bf 1159 *d);
794ac9d0 1160 return;
af7ee8bf 1161 }
252b5132
RH		 1162 }
1163}
1164\f
252b5132
RH		 1165/* Print the mips instruction at address MEMADDR in debugged memory,
1166 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1167 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1168 this is little-endian code. */
1169
1170static int
47b0e7ad
NC		 1171print_insn_mips (bfd_vma memaddr,
1172 unsigned long int word,
1173 struct disassemble_info *info)
252b5132 1174{
47b0e7ad 1175 const struct mips_opcode *op;
b34976b6 1176 static bfd_boolean init = 0;
252b5132
RH		 1177 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1178
1179 /* Build a hash table to shorten the search time. */
1180 if (! init)
1181 {
1182 unsigned int i;
1183
1184 for (i = 0; i <= OP_MASK_OP; i++)
1185 {
1186 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1187 {
986e18a5 1188 if (op->pinfo == INSN_MACRO
9e836e3d 1189 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
252b5132
RH		 1190 continue;
1191 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1192 {
1193 mips_hash[i] = op;
1194 break;
1195 }
1196 }
7f6621cd 1197 }
252b5132
RH		 1198
1199 init = 1;
1200 }
1201
aa5f19f2 1202 info->bytes_per_chunk = INSNLEN;
252b5132 1203 info->display_endian = info->endian;
9bb28706
CD		 1204 info->insn_info_valid = 1;
1205 info->branch_delay_insns = 0;
def7143b 1206 info->data_size = 0;
9bb28706
CD		 1207 info->insn_type = dis_nonbranch;
1208 info->target = 0;
1209 info->target2 = 0;
252b5132
RH		 1210
1211 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1212 if (op != NULL)
1213 {
1214 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1215 {
986e18a5 1216 if (op->pinfo != INSN_MACRO
9e836e3d 1217 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
986e18a5 1218 && (word & op->mask) == op->match)
252b5132 1219 {
47b0e7ad 1220 const char *d;
2bd7f1f3 1221
3396de36 1222 /* We always allow to disassemble the jalx instruction. */
640c0ccd 1223 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3396de36 1224 && strcmp (op->name, "jalx"))
252b5132
RH		 1225 continue;
1226
9bb28706
CD		 1227 /* Figure out instruction type and branch delay information. */
1228 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1229 {
1230 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1231 info->insn_type = dis_jsr;
1232 else
1233 info->insn_type = dis_branch;
1234 info->branch_delay_insns = 1;
1235 }
1236 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1237 | INSN_COND_BRANCH_LIKELY)) != 0)
1238 {
1239 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1240 info->insn_type = dis_condjsr;
1241 else
1242 info->insn_type = dis_condbranch;
1243 info->branch_delay_insns = 1;
1244 }
1245 else if ((op->pinfo & (INSN_STORE_MEMORY
1246 | INSN_LOAD_MEMORY_DELAY)) != 0)
1247 info->insn_type = dis_dref;
1248
252b5132
RH		 1249 (*info->fprintf_func) (info->stream, "%s", op->name);
1250
1251 d = op->args;
1252 if (d != NULL && *d != '\0')
1253 {
7f6621cd 1254 (*info->fprintf_func) (info->stream, "\t");
794ac9d0 1255 print_insn_args (d, word, memaddr, info);
252b5132
RH		 1256 }
1257
aa5f19f2 1258 return INSNLEN;
252b5132
RH		 1259 }
1260 }
1261 }
1262
1263 /* Handle undefined instructions. */
9bb28706 1264 info->insn_type = dis_noninsn;
0fd3a477 1265 (*info->fprintf_func) (info->stream, "0x%lx", word);
aa5f19f2 1266 return INSNLEN;
252b5132 1267}
aa5f19f2 1268\f
252b5132
RH		 1269/* Disassemble an operand for a mips16 instruction. */
1270
1271static void
47b0e7ad
NC		 1272print_mips16_insn_arg (char type,
1273 const struct mips_opcode *op,
1274 int l,
1275 bfd_boolean use_extend,
1276 int extend,
1277 bfd_vma memaddr,
1278 struct disassemble_info *info)
252b5132
RH		 1279{
1280 switch (type)
1281 {
1282 case ',':
1283 case '(':
1284 case ')':
1285 (*info->fprintf_func) (info->stream, "%c", type);
1286 break;
1287
1288 case 'y':
1289 case 'w':
aa5f19f2 1290 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1291 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1292 & MIPS16OP_MASK_RY)));
252b5132
RH		 1293 break;
1294
1295 case 'x':
1296 case 'v':
aa5f19f2 1297 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1298 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1299 & MIPS16OP_MASK_RX)));
252b5132
RH		 1300 break;
1301
1302 case 'z':
aa5f19f2 1303 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1304 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1305 & MIPS16OP_MASK_RZ)));
252b5132
RH		 1306 break;
1307
1308 case 'Z':
aa5f19f2 1309 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1310 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1311 & MIPS16OP_MASK_MOVE32Z)));
252b5132
RH		 1312 break;
1313
1314 case '0':
640c0ccd 1315 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
252b5132
RH		 1316 break;
1317
1318 case 'S':
640c0ccd 1319 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
252b5132
RH		 1320 break;
1321
1322 case 'P':
1323 (*info->fprintf_func) (info->stream, "$pc");
1324 break;
1325
1326 case 'R':
640c0ccd 1327 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
252b5132
RH		 1328 break;
1329
1330 case 'X':
aa5f19f2 1331 (*info->fprintf_func) (info->stream, "%s",
640c0ccd
CD		 1332 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1333 & MIPS16OP_MASK_REGR32)]);
252b5132
RH		 1334 break;
1335
1336 case 'Y':
aa5f19f2 1337 (*info->fprintf_func) (info->stream, "%s",
640c0ccd 1338 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
252b5132
RH		 1339 break;
1340
1341 case '<':
1342 case '>':
1343 case '[':
1344 case ']':
1345 case '4':
1346 case '5':
1347 case 'H':
1348 case 'W':
1349 case 'D':
1350 case 'j':
1351 case '6':
1352 case '8':
1353 case 'V':
1354 case 'C':
1355 case 'U':
1356 case 'k':
1357 case 'K':
1358 case 'p':
1359 case 'q':
1360 case 'A':
1361 case 'B':
1362 case 'E':
1363 {
1364 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1365
1366 shift = 0;
1367 signedp = 0;
1368 extbits = 16;
1369 pcrel = 0;
1370 extu = 0;
1371 branch = 0;
1372 switch (type)
1373 {
1374 case '<':
1375 nbits = 3;
1376 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1377 extbits = 5;
1378 extu = 1;
1379 break;
1380 case '>':
1381 nbits = 3;
1382 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1383 extbits = 5;
1384 extu = 1;
1385 break;
1386 case '[':
1387 nbits = 3;
1388 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1389 extbits = 6;
1390 extu = 1;
1391 break;
1392 case ']':
1393 nbits = 3;
1394 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1395 extbits = 6;
1396 extu = 1;
1397 break;
1398 case '4':
1399 nbits = 4;
1400 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1401 signedp = 1;
1402 extbits = 15;
1403 break;
1404 case '5':
1405 nbits = 5;
1406 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1407 info->insn_type = dis_dref;
1408 info->data_size = 1;
1409 break;
1410 case 'H':
1411 nbits = 5;
1412 shift = 1;
1413 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1414 info->insn_type = dis_dref;
1415 info->data_size = 2;
1416 break;
1417 case 'W':
1418 nbits = 5;
1419 shift = 2;
1420 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1421 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1422 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1423 {
1424 info->insn_type = dis_dref;
1425 info->data_size = 4;
1426 }
1427 break;
1428 case 'D':
1429 nbits = 5;
1430 shift = 3;
1431 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1432 info->insn_type = dis_dref;
1433 info->data_size = 8;
1434 break;
1435 case 'j':
1436 nbits = 5;
1437 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1438 signedp = 1;
1439 break;
1440 case '6':
1441 nbits = 6;
1442 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1443 break;
1444 case '8':
1445 nbits = 8;
1446 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1447 break;
1448 case 'V':
1449 nbits = 8;
1450 shift = 2;
1451 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1452 /* FIXME: This might be lw, or it might be addiu to $sp or
1453 $pc. We assume it's load. */
1454 info->insn_type = dis_dref;
1455 info->data_size = 4;
1456 break;
1457 case 'C':
1458 nbits = 8;
1459 shift = 3;
1460 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1461 info->insn_type = dis_dref;
1462 info->data_size = 8;
1463 break;
1464 case 'U':
1465 nbits = 8;
1466 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1467 extu = 1;
1468 break;
1469 case 'k':
1470 nbits = 8;
1471 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1472 signedp = 1;
1473 break;
1474 case 'K':
1475 nbits = 8;
1476 shift = 3;
1477 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1478 signedp = 1;
1479 break;
1480 case 'p':
1481 nbits = 8;
1482 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1483 signedp = 1;
1484 pcrel = 1;
1485 branch = 1;
1486 info->insn_type = dis_condbranch;
1487 break;
1488 case 'q':
1489 nbits = 11;
1490 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1491 signedp = 1;
1492 pcrel = 1;
1493 branch = 1;
1494 info->insn_type = dis_branch;
1495 break;
1496 case 'A':
1497 nbits = 8;
1498 shift = 2;
1499 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1500 pcrel = 1;
1501 /* FIXME: This can be lw or la. We assume it is lw. */
1502 info->insn_type = dis_dref;
1503 info->data_size = 4;
1504 break;
1505 case 'B':
1506 nbits = 5;
1507 shift = 3;
1508 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1509 pcrel = 1;
1510 info->insn_type = dis_dref;
1511 info->data_size = 8;
1512 break;
1513 case 'E':
1514 nbits = 5;
1515 shift = 2;
1516 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1517 pcrel = 1;
1518 break;
1519 default:
1520 abort ();
1521 }
1522
1523 if (! use_extend)
1524 {
1525 if (signedp && immed >= (1 << (nbits - 1)))
1526 immed -= 1 << nbits;
1527 immed <<= shift;
1528 if ((type == '<' || type == '>' || type == '[' || type == ']')
1529 && immed == 0)
1530 immed = 8;
1531 }
1532 else
1533 {
1534 if (extbits == 16)
1535 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1536 else if (extbits == 15)
1537 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1538 else
1539 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1540 immed &= (1 << extbits) - 1;
1541 if (! extu && immed >= (1 << (extbits - 1)))
1542 immed -= 1 << extbits;
1543 }
1544
1545 if (! pcrel)
1546 (*info->fprintf_func) (info->stream, "%d", immed);
1547 else
1548 {
1549 bfd_vma baseaddr;
252b5132
RH		 1550
1551 if (branch)
1552 {
1553 immed *= 2;
1554 baseaddr = memaddr + 2;
1555 }
1556 else if (use_extend)
1557 baseaddr = memaddr - 2;
1558 else
1559 {
1560 int status;
1561 bfd_byte buffer[2];
1562
1563 baseaddr = memaddr;
1564
1565 /* If this instruction is in the delay slot of a jr
1566 instruction, the base address is the address of the
1567 jr instruction. If it is in the delay slot of jalr
1568 instruction, the base address is the address of the
1569 jalr instruction. This test is unreliable: we have
1570 no way of knowing whether the previous word is
1571 instruction or data. */
1572 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1573 info);
1574 if (status == 0
1575 && (((info->endian == BFD_ENDIAN_BIG
1576 ? bfd_getb16 (buffer)
1577 : bfd_getl16 (buffer))
1578 & 0xf800) == 0x1800))
1579 baseaddr = memaddr - 4;
1580 else
1581 {
1582 status = (*info->read_memory_func) (memaddr - 2, buffer,
1583 2, info);
1584 if (status == 0
1585 && (((info->endian == BFD_ENDIAN_BIG
1586 ? bfd_getb16 (buffer)
1587 : bfd_getl16 (buffer))
1588 & 0xf81f) == 0xe800))
1589 baseaddr = memaddr - 2;
1590 }
1591 }
9bb28706
CD		 1592 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1593 (*info->print_address_func) (info->target, info);
252b5132
RH		 1594 }
1595 }
1596 break;
1597
1598 case 'a':
1599 if (! use_extend)
1600 extend = 0;
1601 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
9bb28706
CD		 1602 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1603 (*info->print_address_func) (info->target, info);
252b5132 1604 info->insn_type = dis_jsr;
252b5132
RH		 1605 info->branch_delay_insns = 1;
1606 break;
1607
1608 case 'l':
1609 case 'L':
1610 {
1611 int need_comma, amask, smask;
1612
1613 need_comma = 0;
1614
1615 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1616
1617 amask = (l >> 3) & 7;
1618
1619 if (amask > 0 && amask < 5)
1620 {
640c0ccd 1621 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
252b5132 1622 if (amask > 1)
aa5f19f2 1623 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1624 mips_gpr_names[amask + 3]);
252b5132
RH		 1625 need_comma = 1;
1626 }
1627
1628 smask = (l >> 1) & 3;
1629 if (smask == 3)
1630 {
1631 (*info->fprintf_func) (info->stream, "%s??",
1632 need_comma ? "," : "");
1633 need_comma = 1;
1634 }
1635 else if (smask > 0)
1636 {
aa5f19f2 1637 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1638 need_comma ? "," : "",
640c0ccd 1639 mips_gpr_names[16]);
252b5132 1640 if (smask > 1)
aa5f19f2 1641 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1642 mips_gpr_names[smask + 15]);
252b5132
RH		 1643 need_comma = 1;
1644 }
1645
1646 if (l & 1)
1647 {
aa5f19f2 1648 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1649 need_comma ? "," : "",
640c0ccd 1650 mips_gpr_names[31]);
252b5132
RH		 1651 need_comma = 1;
1652 }
1653
1654 if (amask == 5 || amask == 6)
1655 {
1656 (*info->fprintf_func) (info->stream, "%s$f0",
1657 need_comma ? "," : "");
1658 if (amask == 6)
1659 (*info->fprintf_func) (info->stream, "-$f1");
1660 }
1661 }
1662 break;
1663
0499d65b
TS		 1664 case 'm':
1665 case 'M':
1666 /* MIPS16e save/restore. */
1667 {
1668 int need_comma = 0;
1669 int amask, args, statics;
1670 int nsreg, smask;
1671 int framesz;
1672 int i, j;
1673
1674 l = l & 0x7f;
1675 if (use_extend)
1676 l |= extend << 16;
1677
1678 amask = (l >> 16) & 0xf;
1679 if (amask == MIPS16_ALL_ARGS)
1680 {
1681 args = 4;
1682 statics = 0;
1683 }
1684 else if (amask == MIPS16_ALL_STATICS)
1685 {
1686 args = 0;
1687 statics = 4;
1688 }
1689 else
1690 {
1691 args = amask >> 2;
1692 statics = amask & 3;
1693 }
1694
1695 if (args > 0) {
1696 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1697 if (args > 1)
1698 (*info->fprintf_func) (info->stream, "-%s",
1699 mips_gpr_names[4 + args - 1]);
1700 need_comma = 1;
1701 }
1702
1703 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1704 if (framesz == 0 && !use_extend)
1705 framesz = 128;
1706
1707 (*info->fprintf_func) (info->stream, "%s%d",
1708 need_comma ? "," : "",
1709 framesz);
1710
1711 if (l & 0x40) /* $ra */
1712 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1713
1714 nsreg = (l >> 24) & 0x7;
1715 smask = 0;
1716 if (l & 0x20) /* $s0 */
1717 smask |= 1 << 0;
1718 if (l & 0x10) /* $s1 */
1719 smask |= 1 << 1;
1720 if (nsreg > 0) /* $s2-$s8 */
1721 smask |= ((1 << nsreg) - 1) << 2;
1722
1723 /* Find first set static reg bit. */
1724 for (i = 0; i < 9; i++)
1725 {
1726 if (smask & (1 << i))
1727 {
1728 (*info->fprintf_func) (info->stream, ",%s",
1729 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1730 /* Skip over string of set bits. */
1731 for (j = i; smask & (2 << j); j++)
1732 continue;
1733 if (j > i)
1734 (*info->fprintf_func) (info->stream, "-%s",
1735 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1736 i = j + 1;
1737 }
1738 }
1739
1740 /* Statics $ax - $a3. */
1741 if (statics == 1)
1742 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1743 else if (statics > 0)
1744 (*info->fprintf_func) (info->stream, ",%s-%s",
1745 mips_gpr_names[7 - statics + 1],
1746 mips_gpr_names[7]);
1747 }
1748 break;
1749
252b5132 1750 default:
aa5f19f2
NC		 1751 /* xgettext:c-format */
1752 (*info->fprintf_func)
1753 (info->stream,
1754 _("# internal disassembler error, unrecognised modifier (%c)"),
1755 type);
252b5132
RH		 1756 abort ();
1757 }
1758}
640c0ccd 1759
47b0e7ad
NC		 1760/* Disassemble mips16 instructions. */
1761
1762static int
1763print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1764{
1765 int status;
1766 bfd_byte buffer[2];
1767 int length;
1768 int insn;
1769 bfd_boolean use_extend;
1770 int extend = 0;
1771 const struct mips_opcode *op, *opend;
1772
1773 info->bytes_per_chunk = 2;
1774 info->display_endian = info->endian;
1775 info->insn_info_valid = 1;
1776 info->branch_delay_insns = 0;
1777 info->data_size = 0;
1778 info->insn_type = dis_nonbranch;
1779 info->target = 0;
1780 info->target2 = 0;
1781
1782 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1783 if (status != 0)
1784 {
1785 (*info->memory_error_func) (status, memaddr, info);
1786 return -1;
1787 }
1788
1789 length = 2;
1790
1791 if (info->endian == BFD_ENDIAN_BIG)
1792 insn = bfd_getb16 (buffer);
1793 else
1794 insn = bfd_getl16 (buffer);
1795
1796 /* Handle the extend opcode specially. */
1797 use_extend = FALSE;
1798 if ((insn & 0xf800) == 0xf000)
1799 {
1800 use_extend = TRUE;
1801 extend = insn & 0x7ff;
1802
1803 memaddr += 2;
1804
1805 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1806 if (status != 0)
1807 {
1808 (*info->fprintf_func) (info->stream, "extend 0x%x",
1809 (unsigned int) extend);
1810 (*info->memory_error_func) (status, memaddr, info);
1811 return -1;
1812 }
1813
1814 if (info->endian == BFD_ENDIAN_BIG)
1815 insn = bfd_getb16 (buffer);
1816 else
1817 insn = bfd_getl16 (buffer);
1818
1819 /* Check for an extend opcode followed by an extend opcode. */
1820 if ((insn & 0xf800) == 0xf000)
1821 {
1822 (*info->fprintf_func) (info->stream, "extend 0x%x",
1823 (unsigned int) extend);
1824 info->insn_type = dis_noninsn;
1825 return length;
1826 }
1827
1828 length += 2;
1829 }
1830
1831 /* FIXME: Should probably use a hash table on the major opcode here. */
1832
1833 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1834 for (op = mips16_opcodes; op < opend; op++)
1835 {
1836 if (op->pinfo != INSN_MACRO
1837 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1838 && (insn & op->mask) == op->match)
1839 {
1840 const char *s;
1841
1842 if (strchr (op->args, 'a') != NULL)
1843 {
1844 if (use_extend)
1845 {
1846 (*info->fprintf_func) (info->stream, "extend 0x%x",
1847 (unsigned int) extend);
1848 info->insn_type = dis_noninsn;
1849 return length - 2;
1850 }
1851
1852 use_extend = FALSE;
1853
1854 memaddr += 2;
1855
1856 status = (*info->read_memory_func) (memaddr, buffer, 2,
1857 info);
1858 if (status == 0)
1859 {
1860 use_extend = TRUE;
1861 if (info->endian == BFD_ENDIAN_BIG)
1862 extend = bfd_getb16 (buffer);
1863 else
1864 extend = bfd_getl16 (buffer);
1865 length += 2;
1866 }
1867 }
1868
1869 (*info->fprintf_func) (info->stream, "%s", op->name);
1870 if (op->args[0] != '\0')
1871 (*info->fprintf_func) (info->stream, "\t");
1872
1873 for (s = op->args; *s != '\0'; s++)
1874 {
1875 if (*s == ','
1876 && s[1] == 'w'
1877 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1878 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1879 {
1880 /* Skip the register and the comma. */
1881 ++s;
1882 continue;
1883 }
1884 if (*s == ','
1885 && s[1] == 'v'
1886 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1887 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1888 {
1889 /* Skip the register and the comma. */
1890 ++s;
1891 continue;
1892 }
1893 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1894 info);
1895 }
1896
1897 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1898 {
1899 info->branch_delay_insns = 1;
1900 if (info->insn_type != dis_jsr)
1901 info->insn_type = dis_branch;
1902 }
1903
1904 return length;
1905 }
1906 }
1907
1908 if (use_extend)
1909 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1910 (*info->fprintf_func) (info->stream, "0x%x", insn);
1911 info->insn_type = dis_noninsn;
1912
1913 return length;
1914}
1915
1916/* In an environment where we do not know the symbol type of the
1917 instruction we are forced to assume that the low order bit of the
1918 instructions' address may mark it as a mips16 instruction. If we
1919 are single stepping, or the pc is within the disassembled function,
1920 this works. Otherwise, we need a clue. Sometimes. */
1921
1922static int
1923_print_insn_mips (bfd_vma memaddr,
1924 struct disassemble_info *info,
1925 enum bfd_endian endianness)
1926{
1927 bfd_byte buffer[INSNLEN];
1928 int status;
1929
1930 set_default_mips_dis_options (info);
1931 parse_mips_dis_options (info->disassembler_options);
1932
1933#if 1
1934 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1935 /* Only a few tools will work this way. */
1936 if (memaddr & 0x01)
1937 return print_insn_mips16 (memaddr, info);
1938#endif
1939
1940#if SYMTAB_AVAILABLE
1941 if (info->mach == bfd_mach_mips16
1942 || (info->flavour == bfd_target_elf_flavour
1943 && info->symbols != NULL
1944 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1945 == STO_MIPS16)))
1946 return print_insn_mips16 (memaddr, info);
1947#endif
1948
1949 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
1950 if (status == 0)
1951 {
1952 unsigned long insn;
1953
1954 if (endianness == BFD_ENDIAN_BIG)
1955 insn = (unsigned long) bfd_getb32 (buffer);
1956 else
1957 insn = (unsigned long) bfd_getl32 (buffer);
1958
1959 return print_insn_mips (memaddr, insn, info);
1960 }
1961 else
1962 {
1963 (*info->memory_error_func) (status, memaddr, info);
1964 return -1;
1965 }
1966}
1967
1968int
1969print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
1970{
1971 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
1972}
1973
1974int
1975print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
1976{
1977 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
1978}
1979\f
640c0ccd 1980void
47b0e7ad 1981print_mips_disassembler_options (FILE *stream)
640c0ccd 1982{
4a9a3c54 1983 unsigned int i;
640c0ccd
CD		 1984
1985 fprintf (stream, _("\n\
1986The following MIPS specific disassembler options are supported for use\n\
1987with the -M switch (multiple options should be separated by commas):\n"));
1988
1989 fprintf (stream, _("\n\
1990 gpr-names=ABI Print GPR names according to specified ABI.\n\
1991 Default: based on binary being disassembled.\n"));
1992
1993 fprintf (stream, _("\n\
1994 fpr-names=ABI Print FPR names according to specified ABI.\n\
1995 Default: numeric.\n"));
1996
1997 fprintf (stream, _("\n\
1998 cp0-names=ARCH Print CP0 register names according to\n\
1999 specified architecture.\n\
2000 Default: based on binary being disassembled.\n"));
2001
af7ee8bf
CD		 2002 fprintf (stream, _("\n\
2003 hwr-names=ARCH Print HWR names according to specified \n\
2004 architecture.\n\
2005 Default: based on binary being disassembled.\n"));
2006
640c0ccd
CD		 2007 fprintf (stream, _("\n\
2008 reg-names=ABI Print GPR and FPR names according to\n\
2009 specified ABI.\n"));
2010
2011 fprintf (stream, _("\n\
af7ee8bf 2012 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 2013 specified architecture.\n"));
2014
2015 fprintf (stream, _("\n\
2016 For the options above, the following values are supported for \"ABI\":\n\
2017 "));
4a9a3c54 2018 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
640c0ccd
CD		 2019 fprintf (stream, " %s", mips_abi_choices[i].name);
2020 fprintf (stream, _("\n"));
2021
2022 fprintf (stream, _("\n\
2023 For the options above, The following values are supported for \"ARCH\":\n\
2024 "));
4a9a3c54 2025 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
640c0ccd
CD		 2026 if (*mips_arch_choices[i].name != '\0')
2027 fprintf (stream, " %s", mips_arch_choices[i].name);
2028 fprintf (stream, _("\n"));
2029
2030 fprintf (stream, _("\n"));
2031}
GDB Binutils - Deliverables
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