Commit | Line | Data |
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252b5132 | 1 | /* Print mips instructions for GDB, the GNU debugger, or for objdump. |
060d22b0 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
82f6ea4a | 3 | 2000, 2001, 2002 |
73da6b6b | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). |
6 | ||
7 | This file is part of GDB, GAS, and the GNU binutils. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
22 | ||
252b5132 RH |
23 | #include "sysdep.h" |
24 | #include "dis-asm.h" | |
640c0ccd | 25 | #include "libiberty.h" |
252b5132 RH |
26 | #include "opcode/mips.h" |
27 | #include "opintl.h" | |
28 | ||
29 | /* FIXME: These are needed to figure out if the code is mips16 or | |
30 | not. The low bit of the address is often a good indicator. No | |
31 | symbol table is available when this code runs out in an embedded | |
7f6621cd | 32 | system as when it is used for disassembler support in a monitor. */ |
252b5132 RH |
33 | |
34 | #if !defined(EMBEDDED_ENV) | |
35 | #define SYMTAB_AVAILABLE 1 | |
36 | #include "elf-bfd.h" | |
37 | #include "elf/mips.h" | |
38 | #endif | |
39 | ||
aa5f19f2 NC |
40 | /* Mips instructions are at maximum this many bytes long. */ |
41 | #define INSNLEN 4 | |
42 | ||
640c0ccd CD |
43 | static void set_default_mips_dis_options |
44 | PARAMS ((struct disassemble_info *)); | |
45 | static void parse_mips_dis_option | |
46 | PARAMS ((const char *, unsigned int)); | |
47 | static void parse_mips_dis_options | |
48 | PARAMS ((const char *)); | |
aa5f19f2 NC |
49 | static int _print_insn_mips |
50 | PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian)); | |
51 | static int print_insn_mips | |
52 | PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *)); | |
af7ee8bf | 53 | static int print_insn_arg |
aa5f19f2 NC |
54 | PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *)); |
55 | static int print_insn_mips16 | |
56 | PARAMS ((bfd_vma, struct disassemble_info *)); | |
7fa108a4 AJ |
57 | static int is_newabi |
58 | PARAMS ((Elf_Internal_Ehdr *)); | |
252b5132 | 59 | static void print_mips16_insn_arg |
b34976b6 | 60 | PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma, |
252b5132 | 61 | struct disassemble_info *)); |
252b5132 | 62 | \f |
aa5f19f2 | 63 | /* FIXME: These should be shared with gdb somehow. */ |
252b5132 RH |
64 | |
65 | /* The mips16 register names. */ | |
7f6621cd | 66 | static const char * const mips16_reg_names[] = { |
252b5132 RH |
67 | "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" |
68 | }; | |
fb48caed | 69 | |
640c0ccd CD |
70 | static const char * const mips_gpr_names_numeric[32] = { |
71 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", | |
72 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
73 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
74 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
aa5f19f2 NC |
75 | }; |
76 | ||
640c0ccd CD |
77 | static const char * const mips_gpr_names_oldabi[32] = { |
78 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
79 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
80 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
81 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
aa5f19f2 NC |
82 | }; |
83 | ||
640c0ccd CD |
84 | static const char * const mips_gpr_names_newabi[32] = { |
85 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
86 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
87 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
88 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
89 | }; | |
90 | ||
91 | static const char * const mips_fpr_names_numeric[32] = { | |
92 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", | |
93 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", | |
94 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", | |
95 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" | |
96 | }; | |
97 | ||
98 | static const char * const mips_fpr_names_32[32] = { | |
99 | "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", | |
100 | "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", | |
101 | "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", | |
102 | "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" | |
103 | }; | |
104 | ||
105 | static const char * const mips_fpr_names_n32[32] = { | |
106 | "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", | |
107 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
108 | "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", | |
109 | "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" | |
110 | }; | |
111 | ||
112 | static const char * const mips_fpr_names_64[32] = { | |
113 | "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", | |
114 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
115 | "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", | |
116 | "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" | |
117 | }; | |
118 | ||
119 | static const char * const mips_cp0_names_numeric[32] = { | |
120 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", | |
121 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
122 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
123 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
124 | }; | |
125 | ||
126 | static const char * const mips_cp0_names_mips3264[32] = { | |
127 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", | |
128 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
129 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
130 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
131 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
132 | "c0_xcontext", "$21", "$22", "c0_debug", | |
133 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", | |
134 | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", | |
135 | }; | |
136 | ||
af7ee8bf CD |
137 | static const char * const mips_cp0_names_mips3264r2[32] = { |
138 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", | |
139 | "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", | |
140 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
141 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
142 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
143 | "c0_xcontext", "$21", "$22", "c0_debug", | |
144 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", | |
145 | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", | |
146 | }; | |
147 | ||
640c0ccd CD |
148 | /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ |
149 | static const char * const mips_cp0_names_sb1[32] = { | |
150 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", | |
151 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
152 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
153 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
154 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
155 | "c0_xcontext", "$21", "$22", "c0_debug", | |
156 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", | |
157 | "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", | |
158 | }; | |
159 | ||
af7ee8bf CD |
160 | static const char * const mips_hwr_names_numeric[32] = { |
161 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", | |
162 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
163 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
164 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
165 | }; | |
166 | ||
167 | static const char * const mips_hwr_names_mips3264r2[32] = { | |
168 | "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", | |
169 | "$4", "$5", "$6", "$7", | |
170 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
171 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
172 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
173 | }; | |
174 | ||
640c0ccd CD |
175 | struct mips_abi_choice { |
176 | const char *name; | |
177 | const char * const *gpr_names; | |
178 | const char * const *fpr_names; | |
179 | }; | |
180 | ||
181 | struct mips_abi_choice mips_abi_choices[] = { | |
182 | { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, | |
183 | { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, | |
184 | { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, | |
185 | { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, | |
186 | }; | |
187 | ||
188 | struct mips_arch_choice { | |
189 | const char *name; | |
190 | int bfd_mach_valid; | |
191 | unsigned long bfd_mach; | |
192 | int processor; | |
193 | int isa; | |
194 | const char * const *cp0_names; | |
af7ee8bf | 195 | const char * const *hwr_names; |
640c0ccd CD |
196 | }; |
197 | ||
198 | struct mips_arch_choice mips_arch_choices[] = { | |
199 | { "numeric", 0, 0, 0, 0, | |
af7ee8bf | 200 | mips_cp0_names_numeric, mips_hwr_names_numeric }, |
640c0ccd | 201 | { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, |
af7ee8bf | 202 | NULL, NULL }, |
640c0ccd | 203 | { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, |
af7ee8bf | 204 | NULL, NULL }, |
640c0ccd | 205 | { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, |
af7ee8bf | 206 | NULL, NULL }, |
640c0ccd | 207 | { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, |
af7ee8bf | 208 | NULL, NULL }, |
640c0ccd | 209 | { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, |
af7ee8bf | 210 | NULL, NULL }, |
640c0ccd | 211 | { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, |
af7ee8bf | 212 | NULL, NULL }, |
640c0ccd | 213 | { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, |
af7ee8bf | 214 | NULL, NULL }, |
640c0ccd | 215 | { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, |
af7ee8bf | 216 | NULL, NULL }, |
640c0ccd | 217 | { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, |
af7ee8bf | 218 | NULL, NULL }, |
640c0ccd | 219 | { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, |
af7ee8bf | 220 | NULL, NULL }, |
640c0ccd | 221 | { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, |
af7ee8bf | 222 | NULL, NULL }, |
640c0ccd | 223 | { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, |
af7ee8bf | 224 | NULL, NULL }, |
640c0ccd | 225 | { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, |
af7ee8bf | 226 | NULL, NULL }, |
640c0ccd | 227 | { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, |
af7ee8bf | 228 | NULL, NULL }, |
640c0ccd | 229 | { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, |
af7ee8bf | 230 | NULL, NULL }, |
640c0ccd | 231 | { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, |
af7ee8bf | 232 | NULL, NULL }, |
640c0ccd | 233 | { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, |
af7ee8bf | 234 | NULL, NULL }, |
640c0ccd | 235 | { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, |
af7ee8bf | 236 | NULL, NULL }, |
640c0ccd | 237 | { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, |
af7ee8bf | 238 | NULL, NULL }, |
640c0ccd CD |
239 | /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. |
240 | Note that MIPS-3D and MDMX are not applicable to MIPS32. (See | |
241 | _MIPS32 Architecture For Programmers Volume I: Introduction to the | |
242 | MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), | |
243 | page 1. */ | |
244 | { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, | |
245 | ISA_MIPS32 | INSN_MIPS16, | |
af7ee8bf CD |
246 | mips_cp0_names_mips3264, NULL }, |
247 | { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, | |
248 | ISA_MIPS32R2 | INSN_MIPS16, | |
249 | mips_cp0_names_mips3264r2, mips_hwr_names_mips3264r2 }, | |
640c0ccd CD |
250 | /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ |
251 | { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, | |
252 | ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, | |
af7ee8bf | 253 | mips_cp0_names_mips3264, NULL }, |
640c0ccd CD |
254 | { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, |
255 | ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, | |
af7ee8bf | 256 | mips_cp0_names_sb1, NULL }, |
640c0ccd CD |
257 | |
258 | /* This entry, mips16, is here only for ISA/processor selection; do | |
259 | not print its name. */ | |
260 | { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, | |
af7ee8bf | 261 | NULL, NULL }, |
640c0ccd CD |
262 | }; |
263 | ||
264 | /* ISA and processor type to disassemble for, and register names to use. | |
265 | set_default_mips_dis_options and parse_mips_dis_options fill in these | |
266 | values. */ | |
267 | static int mips_processor; | |
268 | static int mips_isa; | |
269 | static const char * const *mips_gpr_names; | |
270 | static const char * const *mips_fpr_names; | |
271 | static const char * const *mips_cp0_names; | |
af7ee8bf | 272 | static const char * const *mips_hwr_names; |
640c0ccd CD |
273 | |
274 | static const struct mips_abi_choice *choose_abi_by_name | |
275 | PARAMS ((const char *, unsigned int)); | |
276 | static const struct mips_arch_choice *choose_arch_by_name | |
277 | PARAMS ((const char *, unsigned int)); | |
278 | static const struct mips_arch_choice *choose_arch_by_number | |
279 | PARAMS ((unsigned long)); | |
280 | \f | |
281 | static const struct mips_abi_choice * | |
282 | choose_abi_by_name (name, namelen) | |
283 | const char *name; | |
284 | unsigned int namelen; | |
285 | { | |
286 | const struct mips_abi_choice *c; | |
287 | unsigned int i; | |
288 | ||
289 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) | |
290 | { | |
291 | if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 | |
292 | && strlen (mips_abi_choices[i].name) == namelen) | |
293 | c = &mips_abi_choices[i]; | |
294 | } | |
295 | return c; | |
296 | } | |
297 | ||
298 | static const struct mips_arch_choice * | |
299 | choose_arch_by_name (name, namelen) | |
300 | const char *name; | |
301 | unsigned int namelen; | |
302 | { | |
303 | const struct mips_arch_choice *c = NULL; | |
304 | unsigned int i; | |
305 | ||
306 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
307 | { | |
308 | if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 | |
309 | && strlen (mips_arch_choices[i].name) == namelen) | |
310 | c = &mips_arch_choices[i]; | |
311 | } | |
312 | return c; | |
313 | } | |
314 | ||
315 | static const struct mips_arch_choice * | |
316 | choose_arch_by_number (mach) | |
317 | unsigned long mach; | |
318 | { | |
319 | static unsigned long hint_bfd_mach; | |
320 | static const struct mips_arch_choice *hint_arch_choice; | |
321 | const struct mips_arch_choice *c; | |
322 | unsigned int i; | |
323 | ||
324 | /* We optimize this because even if the user specifies no | |
325 | flags, this will be done for every instruction! */ | |
326 | if (hint_bfd_mach == mach | |
327 | && hint_arch_choice != NULL | |
328 | && hint_arch_choice->bfd_mach == hint_bfd_mach) | |
329 | return hint_arch_choice; | |
330 | ||
331 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
332 | { | |
333 | if (mips_arch_choices[i].bfd_mach_valid | |
334 | && mips_arch_choices[i].bfd_mach == mach) | |
335 | { | |
336 | c = &mips_arch_choices[i]; | |
337 | hint_bfd_mach = mach; | |
338 | hint_arch_choice = c; | |
339 | } | |
340 | } | |
341 | return c; | |
342 | } | |
343 | ||
344 | void | |
345 | set_default_mips_dis_options (info) | |
346 | struct disassemble_info *info; | |
347 | { | |
348 | const struct mips_arch_choice *chosen_arch; | |
349 | ||
350 | /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, | |
af7ee8bf | 351 | and numeric FPR, CP0 register, and HWR names. */ |
640c0ccd CD |
352 | mips_isa = ISA_MIPS3; |
353 | mips_processor = CPU_R3000; | |
354 | mips_gpr_names = mips_gpr_names_oldabi; | |
355 | mips_fpr_names = mips_fpr_names_numeric; | |
356 | mips_cp0_names = mips_cp0_names_numeric; | |
af7ee8bf | 357 | mips_hwr_names = mips_hwr_names_numeric; |
640c0ccd CD |
358 | |
359 | /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ | |
360 | if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL) | |
361 | { | |
362 | Elf_Internal_Ehdr *header; | |
363 | ||
364 | header = elf_elfheader (bfd_asymbol_bfd (*(info->symbols))); | |
365 | if (is_newabi (header)) | |
366 | mips_gpr_names = mips_gpr_names_newabi; | |
367 | } | |
368 | ||
369 | /* Set ISA, architecture, and cp0 register names as best we can. */ | |
370 | #if ! SYMTAB_AVAILABLE | |
371 | /* This is running out on a target machine, not in a host tool. | |
372 | FIXME: Where does mips_target_info come from? */ | |
373 | target_processor = mips_target_info.processor; | |
374 | mips_isa = mips_target_info.isa; | |
375 | #else | |
376 | chosen_arch = choose_arch_by_number (info->mach); | |
377 | if (chosen_arch != NULL) | |
378 | { | |
379 | mips_processor = chosen_arch->processor; | |
380 | mips_isa = chosen_arch->isa; | |
381 | if (chosen_arch->cp0_names != NULL) | |
382 | mips_cp0_names = chosen_arch->cp0_names; | |
af7ee8bf CD |
383 | if (chosen_arch->hwr_names != NULL) |
384 | mips_hwr_names = chosen_arch->hwr_names; | |
640c0ccd CD |
385 | } |
386 | #endif | |
387 | } | |
388 | ||
389 | void | |
390 | parse_mips_dis_option (option, len) | |
391 | const char *option; | |
392 | unsigned int len; | |
393 | { | |
394 | unsigned int i, optionlen, vallen; | |
395 | const char *val; | |
396 | const struct mips_abi_choice *chosen_abi; | |
397 | const struct mips_arch_choice *chosen_arch; | |
398 | ||
399 | /* Look for the = that delimits the end of the option name. */ | |
400 | for (i = 0; i < len; i++) | |
401 | { | |
402 | if (option[i] == '=') | |
403 | break; | |
404 | } | |
405 | if (i == 0) /* Invalid option: no name before '='. */ | |
406 | return; | |
407 | if (i == len) /* Invalid option: no '='. */ | |
408 | return; | |
409 | if (i == (len - 1)) /* Invalid option: no value after '='. */ | |
410 | return; | |
411 | ||
412 | optionlen = i; | |
413 | val = option + (optionlen + 1); | |
414 | vallen = len - (optionlen + 1); | |
415 | ||
416 | if (strncmp("gpr-names", option, optionlen) == 0 | |
417 | && strlen("gpr-names") == optionlen) | |
418 | { | |
419 | chosen_abi = choose_abi_by_name (val, vallen); | |
420 | if (chosen_abi != NULL && chosen_abi->gpr_names != NULL) | |
421 | mips_gpr_names = chosen_abi->gpr_names; | |
422 | return; | |
423 | } | |
424 | ||
425 | if (strncmp("fpr-names", option, optionlen) == 0 | |
426 | && strlen("fpr-names") == optionlen) | |
427 | { | |
428 | chosen_abi = choose_abi_by_name (val, vallen); | |
429 | if (chosen_abi != NULL && chosen_abi->fpr_names != NULL) | |
430 | mips_fpr_names = chosen_abi->fpr_names; | |
431 | return; | |
432 | } | |
433 | ||
434 | if (strncmp("cp0-names", option, optionlen) == 0 | |
435 | && strlen("cp0-names") == optionlen) | |
436 | { | |
437 | chosen_arch = choose_arch_by_name (val, vallen); | |
438 | if (chosen_arch != NULL && chosen_arch->cp0_names != NULL) | |
439 | mips_cp0_names = chosen_arch->cp0_names; | |
440 | return; | |
441 | } | |
442 | ||
af7ee8bf CD |
443 | if (strncmp("hwr-names", option, optionlen) == 0 |
444 | && strlen("hwr-names") == optionlen) | |
445 | { | |
446 | chosen_arch = choose_arch_by_name (val, vallen); | |
447 | if (chosen_arch != NULL && chosen_arch->hwr_names != NULL) | |
448 | mips_hwr_names = chosen_arch->hwr_names; | |
449 | return; | |
450 | } | |
451 | ||
640c0ccd CD |
452 | if (strncmp("reg-names", option, optionlen) == 0 |
453 | && strlen("reg-names") == optionlen) | |
454 | { | |
455 | /* We check both ABI and ARCH here unconditionally, so | |
456 | that "numeric" will do the desirable thing: select | |
457 | numeric register names for all registers. Other than | |
458 | that, a given name probably won't match both. */ | |
459 | chosen_abi = choose_abi_by_name (val, vallen); | |
460 | if (chosen_abi != NULL) | |
461 | { | |
462 | if (chosen_abi->gpr_names != NULL) | |
463 | mips_gpr_names = chosen_abi->gpr_names; | |
464 | if (chosen_abi->fpr_names != NULL) | |
465 | mips_fpr_names = chosen_abi->fpr_names; | |
466 | } | |
467 | chosen_arch = choose_arch_by_name (val, vallen); | |
468 | if (chosen_arch != NULL) | |
469 | { | |
470 | if (chosen_arch->cp0_names != NULL) | |
471 | mips_cp0_names = chosen_arch->cp0_names; | |
af7ee8bf CD |
472 | if (chosen_arch->hwr_names != NULL) |
473 | mips_hwr_names = chosen_arch->hwr_names; | |
640c0ccd CD |
474 | } |
475 | return; | |
476 | } | |
477 | ||
478 | /* Invalid option. */ | |
479 | } | |
480 | ||
481 | void | |
482 | parse_mips_dis_options (options) | |
483 | const char *options; | |
484 | { | |
485 | const char *option_end; | |
486 | ||
487 | if (options == NULL) | |
488 | return; | |
489 | ||
490 | while (*options != '\0') | |
491 | { | |
492 | /* Skip empty options. */ | |
493 | if (*options == ',') | |
494 | { | |
495 | options++; | |
496 | continue; | |
497 | } | |
498 | ||
499 | /* We know that *options is neither NUL or a comma. */ | |
500 | option_end = options + 1; | |
501 | while (*option_end != ',' && *option_end != '\0') | |
502 | option_end++; | |
503 | ||
504 | parse_mips_dis_option (options, option_end - options); | |
505 | ||
506 | /* Go on to the next one. If option_end points to a comma, it | |
507 | will be skipped above. */ | |
508 | options = option_end; | |
509 | } | |
510 | } | |
511 | ||
252b5132 | 512 | \f |
7f6621cd | 513 | /* Print insn arguments for 32/64-bit code. */ |
aa5f19f2 | 514 | |
af7ee8bf | 515 | static int |
252b5132 RH |
516 | print_insn_arg (d, l, pc, info) |
517 | const char *d; | |
518 | register unsigned long int l; | |
519 | bfd_vma pc; | |
520 | struct disassemble_info *info; | |
521 | { | |
af7ee8bf | 522 | int op, delta, consumed; |
252b5132 | 523 | |
af7ee8bf | 524 | consumed = 1; |
252b5132 RH |
525 | switch (*d) |
526 | { | |
527 | case ',': | |
528 | case '(': | |
529 | case ')': | |
9752cf1b RS |
530 | case '[': |
531 | case ']': | |
252b5132 RH |
532 | (*info->fprintf_func) (info->stream, "%c", *d); |
533 | break; | |
534 | ||
af7ee8bf CD |
535 | case '+': |
536 | /* Extension character; switch for second char. */ | |
537 | d++; | |
538 | consumed++; | |
539 | switch (*d) | |
540 | { | |
541 | case 'A': | |
542 | (*info->fprintf_func) (info->stream, "0x%x", | |
543 | (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); | |
544 | break; | |
545 | ||
546 | case 'B': | |
547 | (*info->fprintf_func) (info->stream, "0x%x", | |
548 | (((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) | |
549 | - ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) | |
550 | + 1)); | |
551 | break; | |
552 | ||
553 | case 'C': | |
554 | (*info->fprintf_func) (info->stream, "0x%x", | |
555 | (((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) | |
556 | + 1)); | |
557 | break; | |
558 | ||
559 | default: | |
560 | /* xgettext:c-format */ | |
561 | (*info->fprintf_func) (info->stream, | |
562 | _("# internal error, undefined extension sequence (+%c)"), | |
563 | *d); | |
564 | /* Do not eat the trailing newline. */ | |
565 | if (*d == '\0') | |
566 | consumed--; | |
567 | break; | |
568 | } | |
569 | break; | |
570 | ||
252b5132 RH |
571 | case 's': |
572 | case 'b': | |
573 | case 'r': | |
574 | case 'v': | |
aa5f19f2 | 575 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 576 | mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); |
252b5132 RH |
577 | break; |
578 | ||
579 | case 't': | |
580 | case 'w': | |
aa5f19f2 | 581 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 582 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
252b5132 RH |
583 | break; |
584 | ||
585 | case 'i': | |
586 | case 'u': | |
587 | (*info->fprintf_func) (info->stream, "0x%x", | |
7f6621cd | 588 | (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); |
252b5132 RH |
589 | break; |
590 | ||
7f6621cd | 591 | case 'j': /* Same as i, but sign-extended. */ |
252b5132 RH |
592 | case 'o': |
593 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; | |
594 | if (delta & 0x8000) | |
595 | delta |= ~0xffff; | |
596 | (*info->fprintf_func) (info->stream, "%d", | |
597 | delta); | |
598 | break; | |
599 | ||
600 | case 'h': | |
601 | (*info->fprintf_func) (info->stream, "0x%x", | |
602 | (unsigned int) ((l >> OP_SH_PREFX) | |
603 | & OP_MASK_PREFX)); | |
604 | break; | |
605 | ||
606 | case 'k': | |
607 | (*info->fprintf_func) (info->stream, "0x%x", | |
608 | (unsigned int) ((l >> OP_SH_CACHE) | |
609 | & OP_MASK_CACHE)); | |
610 | break; | |
611 | ||
612 | case 'a': | |
9bb28706 CD |
613 | info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) |
614 | | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); | |
615 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
616 | break; |
617 | ||
618 | case 'p': | |
7f6621cd | 619 | /* Sign extend the displacement. */ |
252b5132 RH |
620 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; |
621 | if (delta & 0x8000) | |
622 | delta |= ~0xffff; | |
9bb28706 CD |
623 | info->target = (delta << 2) + pc + INSNLEN; |
624 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
625 | break; |
626 | ||
627 | case 'd': | |
aa5f19f2 | 628 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 629 | mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
252b5132 RH |
630 | break; |
631 | ||
4372b673 NC |
632 | case 'U': |
633 | { | |
7f6621cd KH |
634 | /* First check for both rd and rt being equal. */ |
635 | unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; | |
636 | if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) | |
637 | (*info->fprintf_func) (info->stream, "%s", | |
640c0ccd | 638 | mips_gpr_names[reg]); |
7f6621cd KH |
639 | else |
640 | { | |
641 | /* If one is zero use the other. */ | |
642 | if (reg == 0) | |
643 | (*info->fprintf_func) (info->stream, "%s", | |
640c0ccd | 644 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
7f6621cd KH |
645 | else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) |
646 | (*info->fprintf_func) (info->stream, "%s", | |
640c0ccd | 647 | mips_gpr_names[reg]); |
7f6621cd KH |
648 | else /* Bogus, result depends on processor. */ |
649 | (*info->fprintf_func) (info->stream, "%s or %s", | |
640c0ccd CD |
650 | mips_gpr_names[reg], |
651 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
7f6621cd | 652 | } |
4372b673 NC |
653 | } |
654 | break; | |
655 | ||
252b5132 | 656 | case 'z': |
640c0ccd | 657 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
252b5132 RH |
658 | break; |
659 | ||
660 | case '<': | |
661 | (*info->fprintf_func) (info->stream, "0x%x", | |
662 | (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); | |
663 | break; | |
664 | ||
665 | case 'c': | |
666 | (*info->fprintf_func) (info->stream, "0x%x", | |
667 | (l >> OP_SH_CODE) & OP_MASK_CODE); | |
668 | break; | |
669 | ||
252b5132 RH |
670 | case 'q': |
671 | (*info->fprintf_func) (info->stream, "0x%x", | |
672 | (l >> OP_SH_CODE2) & OP_MASK_CODE2); | |
673 | break; | |
674 | ||
675 | case 'C': | |
676 | (*info->fprintf_func) (info->stream, "0x%x", | |
677 | (l >> OP_SH_COPZ) & OP_MASK_COPZ); | |
678 | break; | |
679 | ||
680 | case 'B': | |
681 | (*info->fprintf_func) (info->stream, "0x%x", | |
4372b673 NC |
682 | (l >> OP_SH_CODE20) & OP_MASK_CODE20); |
683 | break; | |
684 | ||
685 | case 'J': | |
686 | (*info->fprintf_func) (info->stream, "0x%x", | |
687 | (l >> OP_SH_CODE19) & OP_MASK_CODE19); | |
252b5132 RH |
688 | break; |
689 | ||
690 | case 'S': | |
691 | case 'V': | |
640c0ccd CD |
692 | (*info->fprintf_func) (info->stream, "%s", |
693 | mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); | |
252b5132 RH |
694 | break; |
695 | ||
252b5132 RH |
696 | case 'T': |
697 | case 'W': | |
640c0ccd CD |
698 | (*info->fprintf_func) (info->stream, "%s", |
699 | mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); | |
252b5132 RH |
700 | break; |
701 | ||
702 | case 'D': | |
640c0ccd CD |
703 | (*info->fprintf_func) (info->stream, "%s", |
704 | mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); | |
252b5132 RH |
705 | break; |
706 | ||
707 | case 'R': | |
640c0ccd CD |
708 | (*info->fprintf_func) (info->stream, "%s", |
709 | mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); | |
252b5132 RH |
710 | break; |
711 | ||
712 | case 'E': | |
640c0ccd CD |
713 | /* Coprocessor register for lwcN instructions, et al. |
714 | ||
715 | Note that there is no load/store cp0 instructions, and | |
716 | that FPU (cp1) instructions disassemble this field using | |
717 | 'T' format. Therefore, until we gain understanding of | |
718 | cp2 register names, | |
719 | we can simply print the register numbers. */ | |
21d34b1c TS |
720 | (*info->fprintf_func) (info->stream, "$%d", |
721 | (l >> OP_SH_RT) & OP_MASK_RT); | |
252b5132 RH |
722 | break; |
723 | ||
724 | case 'G': | |
640c0ccd CD |
725 | /* Coprocessor register for mtcN instructions, et al. |
726 | Note that FPU (cp1) instructions disassemble this field using | |
727 | 'S' format. Therefore, we only need to worry about cp0, cp2, | |
728 | and cp3. */ | |
729 | op = (l >> OP_SH_OP) & OP_MASK_OP; | |
730 | if (op == OP_OP_COP0) | |
731 | (*info->fprintf_func) (info->stream, "%s", | |
732 | mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
733 | else | |
734 | (*info->fprintf_func) (info->stream, "$%d", | |
735 | (l >> OP_SH_RD) & OP_MASK_RD); | |
252b5132 RH |
736 | break; |
737 | ||
af7ee8bf CD |
738 | case 'K': |
739 | (*info->fprintf_func) (info->stream, "%s", | |
740 | mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
741 | break; | |
742 | ||
252b5132 RH |
743 | case 'N': |
744 | (*info->fprintf_func) (info->stream, "$fcc%d", | |
745 | (l >> OP_SH_BCC) & OP_MASK_BCC); | |
746 | break; | |
747 | ||
748 | case 'M': | |
749 | (*info->fprintf_func) (info->stream, "$fcc%d", | |
750 | (l >> OP_SH_CCC) & OP_MASK_CCC); | |
751 | break; | |
752 | ||
753 | case 'P': | |
754 | (*info->fprintf_func) (info->stream, "%d", | |
755 | (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); | |
756 | break; | |
757 | ||
9752cf1b RS |
758 | case 'e': |
759 | (*info->fprintf_func) (info->stream, "%d", | |
760 | (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); | |
761 | break; | |
762 | ||
763 | case '%': | |
764 | (*info->fprintf_func) (info->stream, "%d", | |
765 | (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); | |
766 | break; | |
767 | ||
156c2f8b | 768 | case 'H': |
e93d7199 | 769 | (*info->fprintf_func) (info->stream, "%d", |
156c2f8b NC |
770 | (l >> OP_SH_SEL) & OP_MASK_SEL); |
771 | break; | |
252b5132 | 772 | |
deec1734 CD |
773 | case 'O': |
774 | (*info->fprintf_func) (info->stream, "%d", | |
775 | (l >> OP_SH_ALN) & OP_MASK_ALN); | |
776 | break; | |
777 | ||
778 | case 'Q': | |
779 | { | |
780 | unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; | |
781 | if ((vsel & 0x10) == 0) | |
782 | { | |
783 | int fmt; | |
784 | vsel &= 0x0f; | |
785 | for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) | |
786 | if ((vsel & 1) == 0) | |
787 | break; | |
788 | (*info->fprintf_func) (info->stream, "$v%d[%d]", | |
b34976b6 | 789 | (l >> OP_SH_FT) & OP_MASK_FT, |
deec1734 CD |
790 | vsel >> 1); |
791 | } | |
792 | else if ((vsel & 0x08) == 0) | |
793 | { | |
794 | (*info->fprintf_func) (info->stream, "$v%d", | |
795 | (l >> OP_SH_FT) & OP_MASK_FT); | |
796 | } | |
797 | else | |
798 | { | |
799 | (*info->fprintf_func) (info->stream, "0x%x", | |
800 | (l >> OP_SH_FT) & OP_MASK_FT); | |
801 | } | |
802 | } | |
803 | break; | |
804 | ||
805 | case 'X': | |
806 | (*info->fprintf_func) (info->stream, "$v%d", | |
807 | (l >> OP_SH_FD) & OP_MASK_FD); | |
808 | break; | |
809 | ||
810 | case 'Y': | |
811 | (*info->fprintf_func) (info->stream, "$v%d", | |
812 | (l >> OP_SH_FS) & OP_MASK_FS); | |
813 | break; | |
814 | ||
815 | case 'Z': | |
816 | (*info->fprintf_func) (info->stream, "$v%d", | |
817 | (l >> OP_SH_FT) & OP_MASK_FT); | |
818 | break; | |
819 | ||
252b5132 RH |
820 | default: |
821 | /* xgettext:c-format */ | |
822 | (*info->fprintf_func) (info->stream, | |
823 | _("# internal error, undefined modifier(%c)"), | |
824 | *d); | |
825 | break; | |
826 | } | |
af7ee8bf CD |
827 | |
828 | return consumed; | |
252b5132 RH |
829 | } |
830 | \f | |
21d34b1c | 831 | /* Check if the object uses NewABI conventions. */ |
aa5f19f2 NC |
832 | |
833 | static int | |
7f6621cd | 834 | is_newabi (header) |
21d34b1c | 835 | Elf_Internal_Ehdr *header; |
aa5f19f2 | 836 | { |
4c563ebf CD |
837 | /* There are no old-style ABIs which use 64-bit ELF. */ |
838 | if (header->e_ident[EI_CLASS] == ELFCLASS64) | |
839 | return 1; | |
840 | ||
563773fe TS |
841 | /* If a 32-bit ELF file, n32 is a new-style ABI. */ |
842 | if ((header->e_flags & EF_MIPS_ABI2) != 0) | |
21d34b1c | 843 | return 1; |
252b5132 | 844 | |
21d34b1c | 845 | return 0; |
aa5f19f2 NC |
846 | } |
847 | \f | |
252b5132 RH |
848 | /* Print the mips instruction at address MEMADDR in debugged memory, |
849 | on using INFO. Returns length of the instruction, in bytes, which is | |
aa5f19f2 | 850 | always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if |
252b5132 RH |
851 | this is little-endian code. */ |
852 | ||
853 | static int | |
aa5f19f2 | 854 | print_insn_mips (memaddr, word, info) |
252b5132 RH |
855 | bfd_vma memaddr; |
856 | unsigned long int word; | |
857 | struct disassemble_info *info; | |
858 | { | |
859 | register const struct mips_opcode *op; | |
b34976b6 | 860 | static bfd_boolean init = 0; |
252b5132 RH |
861 | static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; |
862 | ||
863 | /* Build a hash table to shorten the search time. */ | |
864 | if (! init) | |
865 | { | |
866 | unsigned int i; | |
867 | ||
868 | for (i = 0; i <= OP_MASK_OP; i++) | |
869 | { | |
870 | for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) | |
871 | { | |
872 | if (op->pinfo == INSN_MACRO) | |
873 | continue; | |
874 | if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) | |
875 | { | |
876 | mips_hash[i] = op; | |
877 | break; | |
878 | } | |
879 | } | |
7f6621cd | 880 | } |
252b5132 RH |
881 | |
882 | init = 1; | |
883 | } | |
884 | ||
aa5f19f2 | 885 | info->bytes_per_chunk = INSNLEN; |
252b5132 | 886 | info->display_endian = info->endian; |
9bb28706 CD |
887 | info->insn_info_valid = 1; |
888 | info->branch_delay_insns = 0; | |
def7143b | 889 | info->data_size = 0; |
9bb28706 CD |
890 | info->insn_type = dis_nonbranch; |
891 | info->target = 0; | |
892 | info->target2 = 0; | |
252b5132 RH |
893 | |
894 | op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; | |
895 | if (op != NULL) | |
896 | { | |
897 | for (; op < &mips_opcodes[NUMOPCODES]; op++) | |
898 | { | |
899 | if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) | |
900 | { | |
901 | register const char *d; | |
2bd7f1f3 | 902 | |
3396de36 | 903 | /* We always allow to disassemble the jalx instruction. */ |
640c0ccd | 904 | if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) |
3396de36 | 905 | && strcmp (op->name, "jalx")) |
252b5132 RH |
906 | continue; |
907 | ||
9bb28706 CD |
908 | /* Figure out instruction type and branch delay information. */ |
909 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
910 | { | |
911 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
912 | info->insn_type = dis_jsr; | |
913 | else | |
914 | info->insn_type = dis_branch; | |
915 | info->branch_delay_insns = 1; | |
916 | } | |
917 | else if ((op->pinfo & (INSN_COND_BRANCH_DELAY | |
918 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
919 | { | |
920 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
921 | info->insn_type = dis_condjsr; | |
922 | else | |
923 | info->insn_type = dis_condbranch; | |
924 | info->branch_delay_insns = 1; | |
925 | } | |
926 | else if ((op->pinfo & (INSN_STORE_MEMORY | |
927 | | INSN_LOAD_MEMORY_DELAY)) != 0) | |
928 | info->insn_type = dis_dref; | |
929 | ||
252b5132 RH |
930 | (*info->fprintf_func) (info->stream, "%s", op->name); |
931 | ||
932 | d = op->args; | |
933 | if (d != NULL && *d != '\0') | |
934 | { | |
af7ee8bf CD |
935 | int consumed; |
936 | ||
7f6621cd | 937 | (*info->fprintf_func) (info->stream, "\t"); |
af7ee8bf CD |
938 | while (*d != '\0') |
939 | { | |
940 | /* print_insn_arg will not eat the trailing NUL | |
941 | of (erroneous) multi-character strings. */ | |
942 | consumed = print_insn_arg (d, word, memaddr, info); | |
943 | d += consumed; | |
944 | } | |
252b5132 RH |
945 | } |
946 | ||
aa5f19f2 | 947 | return INSNLEN; |
252b5132 RH |
948 | } |
949 | } | |
950 | } | |
951 | ||
952 | /* Handle undefined instructions. */ | |
9bb28706 | 953 | info->insn_type = dis_noninsn; |
252b5132 | 954 | (*info->fprintf_func) (info->stream, "0x%x", word); |
aa5f19f2 | 955 | return INSNLEN; |
252b5132 | 956 | } |
aa5f19f2 | 957 | \f |
252b5132 RH |
958 | /* In an environment where we do not know the symbol type of the |
959 | instruction we are forced to assume that the low order bit of the | |
960 | instructions' address may mark it as a mips16 instruction. If we | |
961 | are single stepping, or the pc is within the disassembled function, | |
962 | this works. Otherwise, we need a clue. Sometimes. */ | |
963 | ||
aa5f19f2 NC |
964 | static int |
965 | _print_insn_mips (memaddr, info, endianness) | |
252b5132 RH |
966 | bfd_vma memaddr; |
967 | struct disassemble_info *info; | |
aa5f19f2 | 968 | enum bfd_endian endianness; |
252b5132 | 969 | { |
aa5f19f2 | 970 | bfd_byte buffer[INSNLEN]; |
252b5132 RH |
971 | int status; |
972 | ||
640c0ccd CD |
973 | set_default_mips_dis_options (info); |
974 | parse_mips_dis_options (info->disassembler_options); | |
975 | ||
252b5132 RH |
976 | #if 1 |
977 | /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ | |
978 | /* Only a few tools will work this way. */ | |
979 | if (memaddr & 0x01) | |
980 | return print_insn_mips16 (memaddr, info); | |
e93d7199 | 981 | #endif |
252b5132 RH |
982 | |
983 | #if SYMTAB_AVAILABLE | |
53f32ea5 | 984 | if (info->mach == bfd_mach_mips16 |
252b5132 RH |
985 | || (info->flavour == bfd_target_elf_flavour |
986 | && info->symbols != NULL | |
987 | && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other | |
988 | == STO_MIPS16))) | |
989 | return print_insn_mips16 (memaddr, info); | |
e93d7199 | 990 | #endif |
252b5132 | 991 | |
aa5f19f2 | 992 | status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); |
252b5132 | 993 | if (status == 0) |
aa5f19f2 NC |
994 | { |
995 | unsigned long insn; | |
996 | ||
997 | if (endianness == BFD_ENDIAN_BIG) | |
7f6621cd | 998 | insn = (unsigned long) bfd_getb32 (buffer); |
aa5f19f2 NC |
999 | else |
1000 | insn = (unsigned long) bfd_getl32 (buffer); | |
1001 | ||
1002 | return print_insn_mips (memaddr, insn, info); | |
1003 | } | |
252b5132 RH |
1004 | else |
1005 | { | |
1006 | (*info->memory_error_func) (status, memaddr, info); | |
1007 | return -1; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | int | |
aa5f19f2 | 1012 | print_insn_big_mips (memaddr, info) |
252b5132 RH |
1013 | bfd_vma memaddr; |
1014 | struct disassemble_info *info; | |
1015 | { | |
aa5f19f2 NC |
1016 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); |
1017 | } | |
252b5132 | 1018 | |
aa5f19f2 NC |
1019 | int |
1020 | print_insn_little_mips (memaddr, info) | |
1021 | bfd_vma memaddr; | |
1022 | struct disassemble_info *info; | |
1023 | { | |
1024 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); | |
252b5132 RH |
1025 | } |
1026 | \f | |
1027 | /* Disassemble mips16 instructions. */ | |
1028 | ||
1029 | static int | |
1030 | print_insn_mips16 (memaddr, info) | |
1031 | bfd_vma memaddr; | |
1032 | struct disassemble_info *info; | |
1033 | { | |
1034 | int status; | |
1035 | bfd_byte buffer[2]; | |
1036 | int length; | |
1037 | int insn; | |
b34976b6 | 1038 | bfd_boolean use_extend; |
252b5132 RH |
1039 | int extend = 0; |
1040 | const struct mips_opcode *op, *opend; | |
1041 | ||
1042 | info->bytes_per_chunk = 2; | |
1043 | info->display_endian = info->endian; | |
252b5132 RH |
1044 | info->insn_info_valid = 1; |
1045 | info->branch_delay_insns = 0; | |
1046 | info->data_size = 0; | |
1047 | info->insn_type = dis_nonbranch; | |
1048 | info->target = 0; | |
1049 | info->target2 = 0; | |
1050 | ||
1051 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
1052 | if (status != 0) | |
1053 | { | |
1054 | (*info->memory_error_func) (status, memaddr, info); | |
1055 | return -1; | |
1056 | } | |
1057 | ||
1058 | length = 2; | |
1059 | ||
1060 | if (info->endian == BFD_ENDIAN_BIG) | |
1061 | insn = bfd_getb16 (buffer); | |
1062 | else | |
1063 | insn = bfd_getl16 (buffer); | |
1064 | ||
1065 | /* Handle the extend opcode specially. */ | |
b34976b6 | 1066 | use_extend = FALSE; |
252b5132 RH |
1067 | if ((insn & 0xf800) == 0xf000) |
1068 | { | |
b34976b6 | 1069 | use_extend = TRUE; |
252b5132 RH |
1070 | extend = insn & 0x7ff; |
1071 | ||
1072 | memaddr += 2; | |
1073 | ||
1074 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
1075 | if (status != 0) | |
1076 | { | |
1077 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
1078 | (unsigned int) extend); | |
1079 | (*info->memory_error_func) (status, memaddr, info); | |
1080 | return -1; | |
1081 | } | |
1082 | ||
1083 | if (info->endian == BFD_ENDIAN_BIG) | |
1084 | insn = bfd_getb16 (buffer); | |
1085 | else | |
1086 | insn = bfd_getl16 (buffer); | |
1087 | ||
1088 | /* Check for an extend opcode followed by an extend opcode. */ | |
1089 | if ((insn & 0xf800) == 0xf000) | |
1090 | { | |
1091 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
1092 | (unsigned int) extend); | |
1093 | info->insn_type = dis_noninsn; | |
1094 | return length; | |
1095 | } | |
1096 | ||
1097 | length += 2; | |
1098 | } | |
1099 | ||
1100 | /* FIXME: Should probably use a hash table on the major opcode here. */ | |
1101 | ||
1102 | opend = mips16_opcodes + bfd_mips16_num_opcodes; | |
1103 | for (op = mips16_opcodes; op < opend; op++) | |
1104 | { | |
1105 | if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match) | |
1106 | { | |
1107 | const char *s; | |
1108 | ||
1109 | if (strchr (op->args, 'a') != NULL) | |
1110 | { | |
1111 | if (use_extend) | |
1112 | { | |
1113 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
1114 | (unsigned int) extend); | |
1115 | info->insn_type = dis_noninsn; | |
1116 | return length - 2; | |
1117 | } | |
1118 | ||
b34976b6 | 1119 | use_extend = FALSE; |
252b5132 RH |
1120 | |
1121 | memaddr += 2; | |
1122 | ||
1123 | status = (*info->read_memory_func) (memaddr, buffer, 2, | |
1124 | info); | |
1125 | if (status == 0) | |
1126 | { | |
b34976b6 | 1127 | use_extend = TRUE; |
252b5132 RH |
1128 | if (info->endian == BFD_ENDIAN_BIG) |
1129 | extend = bfd_getb16 (buffer); | |
1130 | else | |
1131 | extend = bfd_getl16 (buffer); | |
1132 | length += 2; | |
1133 | } | |
1134 | } | |
1135 | ||
1136 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
1137 | if (op->args[0] != '\0') | |
1138 | (*info->fprintf_func) (info->stream, "\t"); | |
1139 | ||
1140 | for (s = op->args; *s != '\0'; s++) | |
1141 | { | |
1142 | if (*s == ',' | |
1143 | && s[1] == 'w' | |
1144 | && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) | |
1145 | == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) | |
1146 | { | |
1147 | /* Skip the register and the comma. */ | |
1148 | ++s; | |
1149 | continue; | |
1150 | } | |
1151 | if (*s == ',' | |
1152 | && s[1] == 'v' | |
1153 | && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) | |
1154 | == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) | |
1155 | { | |
1156 | /* Skip the register and the comma. */ | |
1157 | ++s; | |
1158 | continue; | |
1159 | } | |
1160 | print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, | |
1161 | info); | |
1162 | } | |
1163 | ||
1164 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1165 | { | |
1166 | info->branch_delay_insns = 1; | |
1167 | if (info->insn_type != dis_jsr) | |
1168 | info->insn_type = dis_branch; | |
1169 | } | |
1170 | ||
1171 | return length; | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | if (use_extend) | |
1176 | (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); | |
1177 | (*info->fprintf_func) (info->stream, "0x%x", insn); | |
1178 | info->insn_type = dis_noninsn; | |
1179 | ||
1180 | return length; | |
1181 | } | |
1182 | ||
1183 | /* Disassemble an operand for a mips16 instruction. */ | |
1184 | ||
1185 | static void | |
1186 | print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) | |
aa5f19f2 | 1187 | char type; |
252b5132 RH |
1188 | const struct mips_opcode *op; |
1189 | int l; | |
b34976b6 | 1190 | bfd_boolean use_extend; |
252b5132 RH |
1191 | int extend; |
1192 | bfd_vma memaddr; | |
1193 | struct disassemble_info *info; | |
1194 | { | |
1195 | switch (type) | |
1196 | { | |
1197 | case ',': | |
1198 | case '(': | |
1199 | case ')': | |
1200 | (*info->fprintf_func) (info->stream, "%c", type); | |
1201 | break; | |
1202 | ||
1203 | case 'y': | |
1204 | case 'w': | |
aa5f19f2 | 1205 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1206 | mips16_reg_names[((l >> MIPS16OP_SH_RY) |
1207 | & MIPS16OP_MASK_RY)]); | |
1208 | break; | |
1209 | ||
1210 | case 'x': | |
1211 | case 'v': | |
aa5f19f2 | 1212 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1213 | mips16_reg_names[((l >> MIPS16OP_SH_RX) |
1214 | & MIPS16OP_MASK_RX)]); | |
1215 | break; | |
1216 | ||
1217 | case 'z': | |
aa5f19f2 | 1218 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1219 | mips16_reg_names[((l >> MIPS16OP_SH_RZ) |
1220 | & MIPS16OP_MASK_RZ)]); | |
1221 | break; | |
1222 | ||
1223 | case 'Z': | |
aa5f19f2 | 1224 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1225 | mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) |
1226 | & MIPS16OP_MASK_MOVE32Z)]); | |
1227 | break; | |
1228 | ||
1229 | case '0': | |
640c0ccd | 1230 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
252b5132 RH |
1231 | break; |
1232 | ||
1233 | case 'S': | |
640c0ccd | 1234 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); |
252b5132 RH |
1235 | break; |
1236 | ||
1237 | case 'P': | |
1238 | (*info->fprintf_func) (info->stream, "$pc"); | |
1239 | break; | |
1240 | ||
1241 | case 'R': | |
640c0ccd | 1242 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); |
252b5132 RH |
1243 | break; |
1244 | ||
1245 | case 'X': | |
aa5f19f2 | 1246 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd CD |
1247 | mips_gpr_names[((l >> MIPS16OP_SH_REGR32) |
1248 | & MIPS16OP_MASK_REGR32)]); | |
252b5132 RH |
1249 | break; |
1250 | ||
1251 | case 'Y': | |
aa5f19f2 | 1252 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 1253 | mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); |
252b5132 RH |
1254 | break; |
1255 | ||
1256 | case '<': | |
1257 | case '>': | |
1258 | case '[': | |
1259 | case ']': | |
1260 | case '4': | |
1261 | case '5': | |
1262 | case 'H': | |
1263 | case 'W': | |
1264 | case 'D': | |
1265 | case 'j': | |
1266 | case '6': | |
1267 | case '8': | |
1268 | case 'V': | |
1269 | case 'C': | |
1270 | case 'U': | |
1271 | case 'k': | |
1272 | case 'K': | |
1273 | case 'p': | |
1274 | case 'q': | |
1275 | case 'A': | |
1276 | case 'B': | |
1277 | case 'E': | |
1278 | { | |
1279 | int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; | |
1280 | ||
1281 | shift = 0; | |
1282 | signedp = 0; | |
1283 | extbits = 16; | |
1284 | pcrel = 0; | |
1285 | extu = 0; | |
1286 | branch = 0; | |
1287 | switch (type) | |
1288 | { | |
1289 | case '<': | |
1290 | nbits = 3; | |
1291 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
1292 | extbits = 5; | |
1293 | extu = 1; | |
1294 | break; | |
1295 | case '>': | |
1296 | nbits = 3; | |
1297 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
1298 | extbits = 5; | |
1299 | extu = 1; | |
1300 | break; | |
1301 | case '[': | |
1302 | nbits = 3; | |
1303 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
1304 | extbits = 6; | |
1305 | extu = 1; | |
1306 | break; | |
1307 | case ']': | |
1308 | nbits = 3; | |
1309 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
1310 | extbits = 6; | |
1311 | extu = 1; | |
1312 | break; | |
1313 | case '4': | |
1314 | nbits = 4; | |
1315 | immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; | |
1316 | signedp = 1; | |
1317 | extbits = 15; | |
1318 | break; | |
1319 | case '5': | |
1320 | nbits = 5; | |
1321 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1322 | info->insn_type = dis_dref; | |
1323 | info->data_size = 1; | |
1324 | break; | |
1325 | case 'H': | |
1326 | nbits = 5; | |
1327 | shift = 1; | |
1328 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1329 | info->insn_type = dis_dref; | |
1330 | info->data_size = 2; | |
1331 | break; | |
1332 | case 'W': | |
1333 | nbits = 5; | |
1334 | shift = 2; | |
1335 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1336 | if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 | |
1337 | && (op->pinfo & MIPS16_INSN_READ_SP) == 0) | |
1338 | { | |
1339 | info->insn_type = dis_dref; | |
1340 | info->data_size = 4; | |
1341 | } | |
1342 | break; | |
1343 | case 'D': | |
1344 | nbits = 5; | |
1345 | shift = 3; | |
1346 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1347 | info->insn_type = dis_dref; | |
1348 | info->data_size = 8; | |
1349 | break; | |
1350 | case 'j': | |
1351 | nbits = 5; | |
1352 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1353 | signedp = 1; | |
1354 | break; | |
1355 | case '6': | |
1356 | nbits = 6; | |
1357 | immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1358 | break; | |
1359 | case '8': | |
1360 | nbits = 8; | |
1361 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1362 | break; | |
1363 | case 'V': | |
1364 | nbits = 8; | |
1365 | shift = 2; | |
1366 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1367 | /* FIXME: This might be lw, or it might be addiu to $sp or | |
1368 | $pc. We assume it's load. */ | |
1369 | info->insn_type = dis_dref; | |
1370 | info->data_size = 4; | |
1371 | break; | |
1372 | case 'C': | |
1373 | nbits = 8; | |
1374 | shift = 3; | |
1375 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1376 | info->insn_type = dis_dref; | |
1377 | info->data_size = 8; | |
1378 | break; | |
1379 | case 'U': | |
1380 | nbits = 8; | |
1381 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1382 | extu = 1; | |
1383 | break; | |
1384 | case 'k': | |
1385 | nbits = 8; | |
1386 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1387 | signedp = 1; | |
1388 | break; | |
1389 | case 'K': | |
1390 | nbits = 8; | |
1391 | shift = 3; | |
1392 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1393 | signedp = 1; | |
1394 | break; | |
1395 | case 'p': | |
1396 | nbits = 8; | |
1397 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1398 | signedp = 1; | |
1399 | pcrel = 1; | |
1400 | branch = 1; | |
1401 | info->insn_type = dis_condbranch; | |
1402 | break; | |
1403 | case 'q': | |
1404 | nbits = 11; | |
1405 | immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; | |
1406 | signedp = 1; | |
1407 | pcrel = 1; | |
1408 | branch = 1; | |
1409 | info->insn_type = dis_branch; | |
1410 | break; | |
1411 | case 'A': | |
1412 | nbits = 8; | |
1413 | shift = 2; | |
1414 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1415 | pcrel = 1; | |
1416 | /* FIXME: This can be lw or la. We assume it is lw. */ | |
1417 | info->insn_type = dis_dref; | |
1418 | info->data_size = 4; | |
1419 | break; | |
1420 | case 'B': | |
1421 | nbits = 5; | |
1422 | shift = 3; | |
1423 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1424 | pcrel = 1; | |
1425 | info->insn_type = dis_dref; | |
1426 | info->data_size = 8; | |
1427 | break; | |
1428 | case 'E': | |
1429 | nbits = 5; | |
1430 | shift = 2; | |
1431 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1432 | pcrel = 1; | |
1433 | break; | |
1434 | default: | |
1435 | abort (); | |
1436 | } | |
1437 | ||
1438 | if (! use_extend) | |
1439 | { | |
1440 | if (signedp && immed >= (1 << (nbits - 1))) | |
1441 | immed -= 1 << nbits; | |
1442 | immed <<= shift; | |
1443 | if ((type == '<' || type == '>' || type == '[' || type == ']') | |
1444 | && immed == 0) | |
1445 | immed = 8; | |
1446 | } | |
1447 | else | |
1448 | { | |
1449 | if (extbits == 16) | |
1450 | immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); | |
1451 | else if (extbits == 15) | |
1452 | immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); | |
1453 | else | |
1454 | immed = ((extend >> 6) & 0x1f) | (extend & 0x20); | |
1455 | immed &= (1 << extbits) - 1; | |
1456 | if (! extu && immed >= (1 << (extbits - 1))) | |
1457 | immed -= 1 << extbits; | |
1458 | } | |
1459 | ||
1460 | if (! pcrel) | |
1461 | (*info->fprintf_func) (info->stream, "%d", immed); | |
1462 | else | |
1463 | { | |
1464 | bfd_vma baseaddr; | |
252b5132 RH |
1465 | |
1466 | if (branch) | |
1467 | { | |
1468 | immed *= 2; | |
1469 | baseaddr = memaddr + 2; | |
1470 | } | |
1471 | else if (use_extend) | |
1472 | baseaddr = memaddr - 2; | |
1473 | else | |
1474 | { | |
1475 | int status; | |
1476 | bfd_byte buffer[2]; | |
1477 | ||
1478 | baseaddr = memaddr; | |
1479 | ||
1480 | /* If this instruction is in the delay slot of a jr | |
1481 | instruction, the base address is the address of the | |
1482 | jr instruction. If it is in the delay slot of jalr | |
1483 | instruction, the base address is the address of the | |
1484 | jalr instruction. This test is unreliable: we have | |
1485 | no way of knowing whether the previous word is | |
1486 | instruction or data. */ | |
1487 | status = (*info->read_memory_func) (memaddr - 4, buffer, 2, | |
1488 | info); | |
1489 | if (status == 0 | |
1490 | && (((info->endian == BFD_ENDIAN_BIG | |
1491 | ? bfd_getb16 (buffer) | |
1492 | : bfd_getl16 (buffer)) | |
1493 | & 0xf800) == 0x1800)) | |
1494 | baseaddr = memaddr - 4; | |
1495 | else | |
1496 | { | |
1497 | status = (*info->read_memory_func) (memaddr - 2, buffer, | |
1498 | 2, info); | |
1499 | if (status == 0 | |
1500 | && (((info->endian == BFD_ENDIAN_BIG | |
1501 | ? bfd_getb16 (buffer) | |
1502 | : bfd_getl16 (buffer)) | |
1503 | & 0xf81f) == 0xe800)) | |
1504 | baseaddr = memaddr - 2; | |
1505 | } | |
1506 | } | |
9bb28706 CD |
1507 | info->target = (baseaddr & ~((1 << shift) - 1)) + immed; |
1508 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
1509 | } |
1510 | } | |
1511 | break; | |
1512 | ||
1513 | case 'a': | |
1514 | if (! use_extend) | |
1515 | extend = 0; | |
1516 | l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); | |
9bb28706 CD |
1517 | info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; |
1518 | (*info->print_address_func) (info->target, info); | |
252b5132 | 1519 | info->insn_type = dis_jsr; |
252b5132 RH |
1520 | info->branch_delay_insns = 1; |
1521 | break; | |
1522 | ||
1523 | case 'l': | |
1524 | case 'L': | |
1525 | { | |
1526 | int need_comma, amask, smask; | |
1527 | ||
1528 | need_comma = 0; | |
1529 | ||
1530 | l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1531 | ||
1532 | amask = (l >> 3) & 7; | |
1533 | ||
1534 | if (amask > 0 && amask < 5) | |
1535 | { | |
640c0ccd | 1536 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); |
252b5132 | 1537 | if (amask > 1) |
aa5f19f2 | 1538 | (*info->fprintf_func) (info->stream, "-%s", |
640c0ccd | 1539 | mips_gpr_names[amask + 3]); |
252b5132 RH |
1540 | need_comma = 1; |
1541 | } | |
1542 | ||
1543 | smask = (l >> 1) & 3; | |
1544 | if (smask == 3) | |
1545 | { | |
1546 | (*info->fprintf_func) (info->stream, "%s??", | |
1547 | need_comma ? "," : ""); | |
1548 | need_comma = 1; | |
1549 | } | |
1550 | else if (smask > 0) | |
1551 | { | |
aa5f19f2 | 1552 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1553 | need_comma ? "," : "", |
640c0ccd | 1554 | mips_gpr_names[16]); |
252b5132 | 1555 | if (smask > 1) |
aa5f19f2 | 1556 | (*info->fprintf_func) (info->stream, "-%s", |
640c0ccd | 1557 | mips_gpr_names[smask + 15]); |
252b5132 RH |
1558 | need_comma = 1; |
1559 | } | |
1560 | ||
1561 | if (l & 1) | |
1562 | { | |
aa5f19f2 | 1563 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1564 | need_comma ? "," : "", |
640c0ccd | 1565 | mips_gpr_names[31]); |
252b5132 RH |
1566 | need_comma = 1; |
1567 | } | |
1568 | ||
1569 | if (amask == 5 || amask == 6) | |
1570 | { | |
1571 | (*info->fprintf_func) (info->stream, "%s$f0", | |
1572 | need_comma ? "," : ""); | |
1573 | if (amask == 6) | |
1574 | (*info->fprintf_func) (info->stream, "-$f1"); | |
1575 | } | |
1576 | } | |
1577 | break; | |
1578 | ||
1579 | default: | |
aa5f19f2 NC |
1580 | /* xgettext:c-format */ |
1581 | (*info->fprintf_func) | |
1582 | (info->stream, | |
1583 | _("# internal disassembler error, unrecognised modifier (%c)"), | |
1584 | type); | |
252b5132 RH |
1585 | abort (); |
1586 | } | |
1587 | } | |
640c0ccd CD |
1588 | |
1589 | void | |
1590 | print_mips_disassembler_options (stream) | |
1591 | FILE *stream; | |
1592 | { | |
1593 | int i; | |
1594 | ||
1595 | fprintf (stream, _("\n\ | |
1596 | The following MIPS specific disassembler options are supported for use\n\ | |
1597 | with the -M switch (multiple options should be separated by commas):\n")); | |
1598 | ||
1599 | fprintf (stream, _("\n\ | |
1600 | gpr-names=ABI Print GPR names according to specified ABI.\n\ | |
1601 | Default: based on binary being disassembled.\n")); | |
1602 | ||
1603 | fprintf (stream, _("\n\ | |
1604 | fpr-names=ABI Print FPR names according to specified ABI.\n\ | |
1605 | Default: numeric.\n")); | |
1606 | ||
1607 | fprintf (stream, _("\n\ | |
1608 | cp0-names=ARCH Print CP0 register names according to\n\ | |
1609 | specified architecture.\n\ | |
1610 | Default: based on binary being disassembled.\n")); | |
1611 | ||
af7ee8bf CD |
1612 | fprintf (stream, _("\n\ |
1613 | hwr-names=ARCH Print HWR names according to specified \n\ | |
1614 | architecture.\n\ | |
1615 | Default: based on binary being disassembled.\n")); | |
1616 | ||
640c0ccd CD |
1617 | fprintf (stream, _("\n\ |
1618 | reg-names=ABI Print GPR and FPR names according to\n\ | |
1619 | specified ABI.\n")); | |
1620 | ||
1621 | fprintf (stream, _("\n\ | |
af7ee8bf | 1622 | reg-names=ARCH Print CP0 register and HWR names according to\n\ |
640c0ccd CD |
1623 | specified architecture.\n")); |
1624 | ||
1625 | fprintf (stream, _("\n\ | |
1626 | For the options above, the following values are supported for \"ABI\":\n\ | |
1627 | ")); | |
1628 | for (i = 0; mips_abi_choices[i].name != NULL; i++) | |
1629 | fprintf (stream, " %s", mips_abi_choices[i].name); | |
1630 | fprintf (stream, _("\n")); | |
1631 | ||
1632 | fprintf (stream, _("\n\ | |
1633 | For the options above, The following values are supported for \"ARCH\":\n\ | |
1634 | ")); | |
1635 | for (i = 0; mips_arch_choices[i].name != NULL; i++) | |
1636 | if (*mips_arch_choices[i].name != '\0') | |
1637 | fprintf (stream, " %s", mips_arch_choices[i].name); | |
1638 | fprintf (stream, _("\n")); | |
1639 | ||
1640 | fprintf (stream, _("\n")); | |
1641 | } |