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* gdb.base/printcmds.exp: New test, for printing register before
[deliverable/binutils-gdb.git] / opcodes / mips-opc.c
CommitLineData
45b14705
ILT		 1/* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
111, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22#include <stdio.h>
23#include "ansidecl.h"
24#include "opcode/mips.h"
25
26/* Short hand so the lines aren't too long. */
27
2bef2d3e
ILT		 28#define LDD INSN_LOAD_MEMORY_DELAY
29#define LCD INSN_LOAD_COPROC_DELAY
45b14705
ILT		 30#define UBD INSN_UNCOND_BRANCH_DELAY
31#define CBD INSN_COND_BRANCH_DELAY
2bef2d3e
ILT		 32#define COD INSN_COPROC_MOVE_DELAY
33#define CLD INSN_COPROC_MEMORY_DELAY
34#define CBL INSN_COND_BRANCH_LIKELY
9978cd4d 35#define TRAP INSN_TRAP
942a4965 36#define SM INSN_STORE_MEMORY
45b14705
ILT		 37
38#define WR_d INSN_WRITE_GPR_D
39#define WR_t INSN_WRITE_GPR_T
40#define WR_31 INSN_WRITE_GPR_31
41#define WR_D INSN_WRITE_FPR_D
42#define WR_T INSN_WRITE_FPR_T
2bef2d3e 43#define WR_S INSN_WRITE_FPR_S
45b14705
ILT		 44#define RD_s INSN_READ_GPR_S
45#define RD_b INSN_READ_GPR_S
46#define RD_t INSN_READ_GPR_T
47#define RD_S INSN_READ_FPR_S
48#define RD_T INSN_READ_FPR_T
49#define WR_CC INSN_WRITE_COND_CODE
50#define RD_CC INSN_READ_COND_CODE
51#define RD_C0 INSN_COP
52#define RD_C1 INSN_COP
53#define RD_C2 INSN_COP
54#define RD_C3 INSN_COP
55#define WR_C0 INSN_COP
56#define WR_C1 INSN_COP
57#define WR_C2 INSN_COP
58#define WR_C3 INSN_COP
59#define WR_HI INSN_WRITE_HI
60#define WR_LO INSN_WRITE_LO
61#define RD_HI INSN_READ_HI
62#define RD_LO INSN_READ_LO
63
2bef2d3e
ILT		 64#define I2 INSN_ISA2
65#define I3 INSN_ISA3
66
45b14705
ILT		 67/* The order of overloaded instructions matters. Label arguments and
68 register arguments look the same. Instructions that can have either
69 for arguments must apear in the correct order in this table for the
70 assembler to pick the right one. In other words, entries with
71 immediate operands must apear after the same instruction with
72 registers.
73
74 Many instructions are short hand for other instructions (i.e., The
75 jal <register> instruction is short for jalr <register>). */
76
77const struct mips_opcode mips_opcodes[] = {
78/* These instructions appear first so that the disassembler will find
79 them first. The assemblers uses a hash table based on the
80 instruction name anyhow. */
81{"nop", "", 0x00000000, 0xffffffff, 0 },
82{"li", "t,j", 0x24000000, 0xffe00000, WR_t }, /* addiu */
83{"li", "t,i", 0x34000000, 0xffe00000, WR_t }, /* ori */
84{"li", "t,I", 0, (int) M_LI, INSN_MACRO },
27faaa41
ILT		 85/* dli is used on Irix 6 for a 64 bit load--our li can do that. */
86{"dli", "t,j", 0x24000000, 0xffe00000, WR_t }, /* addiu */
87{"dli", "t,i", 0x34000000, 0xffe00000, WR_t }, /* ori */
88{"dli", "t,I", 0, (int) M_LI, INSN_MACRO },
89{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s },/* or */
90{"b", "p", 0x10000000, 0xffff0000, UBD },/* beq 0,0 */
91{"b", "p", 0x04010000, 0xffff0000, UBD },/* bgez 0 */
92{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31 },/* bgezal 0*/
45b14705
ILT		 93
94{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
95{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S },
96{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S },
45b14705
ILT		 97{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t },
98{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
99{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T },
100{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T },
101{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s },
102{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s },
103{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t },
104{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
105{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t },
106{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
107{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s },
108/* b is at the top of the table. */
109/* bal is at the top of the table. */
110{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 111{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 112{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 113{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 114{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 115{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 116{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 117{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 118{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC },
2bef2d3e 119{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 120{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC },
2bef2d3e 121{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 122{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC },
2bef2d3e 123{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 124{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC },
2bef2d3e
ILT		 125{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC|I2 },
126{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 127{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 128{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t },
129{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
2bef2d3e
ILT		 130{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t|I2},
131{"beql", "s,I,p", 2, (int) M_BEQL_I, INSN_MACRO },
45b14705
ILT		 132{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
133{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
2bef2d3e
ILT		 134{"bgel", "s,t,p", 2, (int) M_BGEL, INSN_MACRO },
135{"bgel", "s,I,p", 2, (int) M_BGEL_I, INSN_MACRO },
45b14705
ILT		 136{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
137{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
2bef2d3e
ILT		 138{"bgeul", "s,t,p", 2, (int) M_BGEUL, INSN_MACRO },
139{"bgeul", "s,I,p", 2, (int) M_BGEUL_I, INSN_MACRO },
45b14705 140{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s },
9978cd4d 141{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s|I2 },
a5ba0d3f 142{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31 },
9978cd4d 143{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 144{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
145{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
2bef2d3e
ILT		 146{"bgtl", "s,t,p", 2, (int) M_BGTL, INSN_MACRO },
147{"bgtl", "s,I,p", 2, (int) M_BGTL_I, INSN_MACRO },
45b14705
ILT		 148{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
149{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
2bef2d3e
ILT		 150{"bgtul", "s,t,p", 2, (int) M_BGTUL, INSN_MACRO },
151{"bgtul", "s,I,p", 2, (int) M_BGTUL_I, INSN_MACRO },
45b14705 152{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 153{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 154{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
155{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
2bef2d3e
ILT		 156{"blel", "s,t,p", 2, (int) M_BLEL, INSN_MACRO },
157{"blel", "s,I,p", 2, (int) M_BLEL_I, INSN_MACRO },
45b14705
ILT		 158{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
159{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
2bef2d3e
ILT		 160{"bleul", "s,t,p", 2, (int) M_BLEUL, INSN_MACRO },
161{"bleul", "s,I,p", 2, (int) M_BLEUL_I, INSN_MACRO },
45b14705 162{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 163{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 164{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
165{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
2bef2d3e
ILT		 166{"bltl", "s,t,p", 2, (int) M_BLTL, INSN_MACRO },
167{"bltl", "s,I,p", 2, (int) M_BLTL_I, INSN_MACRO },
45b14705
ILT		 168{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
169{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
2bef2d3e
ILT		 170{"bltul", "s,t,p", 2, (int) M_BLTUL, INSN_MACRO },
171{"bltul", "s,I,p", 2, (int) M_BLTUL_I, INSN_MACRO },
45b14705 172{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 173{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s|I2 },
a5ba0d3f 174{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31 },
9978cd4d 175{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|I2 },
2bef2d3e 176{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 177{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 178{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t },
179{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
9978cd4d 180{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t|I2},
2bef2d3e 181{"bnel", "s,I,p", 2, (int) M_BNEL_I, INSN_MACRO },
9978cd4d
ILT		 182{"break", "", 0x0000000d, 0xffffffff, TRAP },
183{"break", "c", 0x0000000d, 0xfc00003f, TRAP },
45b14705
ILT		 184{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
185{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
186{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
187{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC },
188{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC },
189{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC },
190{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC },
191{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC },
192{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC },
193{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC },
194{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC },
195{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
196{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
197{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
198{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
199{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
200{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
201{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
202{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
203{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
204{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
205{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
206{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
207{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
208{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
209{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
210{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
211{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
212{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
213{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
214{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
215{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
942a4965 216{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b|I3 },
2bef2d3e
ILT		 217{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|I3 },
218{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|I3 },
219{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|I2 },
220{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|I2 },
221{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0 },
222{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1 },
223{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1 },
224{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2 },
225{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3 },
45b14705
ILT		 226{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC },
227{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC },
228{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC },
229{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC },
230{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC },
2bef2d3e 231{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|I3 },
45b14705
ILT		 232{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S },
233{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S },
2bef2d3e
ILT		 234{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|I3 },
235{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|I3 },
236{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|I3 },
45b14705
ILT		 237{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S },
238{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S },
239{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S },
240{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S },
27faaa41 241{"dabs", "d,v", 3, (int) M_DABS, INSN_MACRO },
2bef2d3e
ILT		 242{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
243{"dadd", "t,r,I", 3, (int) M_DADD_I, INSN_MACRO },
244{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s|I3 },
245{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s|I3 },
246{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
247{"daddu", "t,r,I", 3, (int) M_DADDU_I, INSN_MACRO },
a9c686ad 248/* For ddiv, see the comments about div. */
547998d2 249{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
a9c686ad 250{"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
2bef2d3e 251{"ddiv", "d,v,I", 3, (int) M_DDIV_3I, INSN_MACRO },
a9c686ad 252/* For ddivu, see the comments about div. */
547998d2 253{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
a9c686ad 254{"ddivu", "d,v,t", 3, (int) M_DDIVU_3, INSN_MACRO },
2bef2d3e 255{"ddivu", "d,v,I", 3, (int) M_DDIVU_3I, INSN_MACRO },
a9c686ad
ILT		 256/* The MIPS assembler treats the div opcode with two operands as
257 though the first operand appeared twice (the first operand is both
258 a source and a destination). To get the div machine instruction,
547998d2
ILT		 259 you must use an explicit destination of $0. */
260{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
a9c686ad 261{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO },
45b14705
ILT		 262{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
263{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T },
264{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T },
a9c686ad 265/* For divu, see the comments about div. */
547998d2 266{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
a9c686ad 267{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO },
45b14705 268{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
2bef2d3e
ILT		 269{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
270{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
271{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
272{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|I3 },
273{"dmul", "d,v,t", 3, (int) M_DMUL, INSN_MACRO },
274{"dmul", "d,v,I", 3, (int) M_DMUL_I, INSN_MACRO },
275{"dmulo", "d,v,t", 3, (int) M_DMULO, INSN_MACRO },
276{"dmulo", "d,v,I", 3, (int) M_DMULO_I, INSN_MACRO },
277{"dmulou", "d,v,t", 3, (int) M_DMULOU, INSN_MACRO },
278{"dmulou", "d,v,I", 3, (int) M_DMULOU_I, INSN_MACRO },
279{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
280{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
281{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t|I3 }, /* dsub 0 */
282{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t|I3 }, /* dsubu 0*/
547998d2 283{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
2bef2d3e
ILT		 284{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO },
285{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO },
547998d2 286{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
2bef2d3e
ILT		 287{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO },
288{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO },
289{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
942a4965 290{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 291{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsllv */
942a4965 292{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 }, /* dsll32 */
2bef2d3e 293{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 294{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
942a4965 295{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 296{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrav */
942a4965 297{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 }, /* dsra32 */
2bef2d3e 298{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 299{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
942a4965 300{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 301{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrlv */
942a4965 302{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 }, /* dsrl32 */
2bef2d3e 303{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e
ILT		 304{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
305{"dsub", "d,v,I", 3, (int) M_DSUB_I, INSN_MACRO },
306{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
307{"dsubu", "d,v,I", 3, (int) M_DSUBU_I, INSN_MACRO },
308{"eret", "", 0x42000018, 0xffffffff, I3 },
309{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|I3 },
310{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|I3 },
311{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|I2 },
312{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|I2 },
45b14705 313{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s },
942a4965
ILT		 314{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s }, /* jr */
315/* SVR4 PIC code requires special handling for j, so it must be a
316 macro. */
317{"j", "a", 0, (int) M_J_A, INSN_MACRO },
318/* This form of j is used by the disassembler and internally by the
319 assembler, but will never match user input (because the line above
320 will match first). */
45b14705
ILT		 321{"j", "a", 0x08000000, 0xfc000000, UBD },
322{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d },
323{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d },
942a4965
ILT		 324/* SVR4 PIC code requires special handling for jal, so it must be a
325 macro. */
326{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO },
327{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO },
328{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO },
329/* This form of jal is used by the disassembler and internally by the
330 assembler, but will never match user input (because the line above
331 will match first). */
45b14705 332{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31 },
45b14705
ILT		 333{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
334{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t },
335{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
336{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t },
337{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
2bef2d3e 338{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b|I3 },
45b14705
ILT		 339{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
340{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
2bef2d3e
ILT		 341{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
342{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
343{"ldc1", "T,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
344{"ldc1", "E,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
942a4965
ILT		 345{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2}, /* ldc1 */
346{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
347{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
2bef2d3e
ILT		 348{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
349{"ldc2", "E,A(b)", 2, (int) M_LDC2_AB, INSN_MACRO },
350{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
351{"ldc3", "E,A(b)", 2, (int) M_LDC3_AB, INSN_MACRO },
352{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b|I3},
353{"ldl", "t,A(b)", 3, (int) M_LDL_AB, INSN_MACRO },
354{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b|I3},
355{"ldr", "t,A(b)", 3, (int) M_LDR_AB, INSN_MACRO },
45b14705
ILT		 356{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t },
357{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
358{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t },
359{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
360/* li is at the start of the table. */
361{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
362{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO },
363{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO },
364{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO },
2bef2d3e
ILT		 365{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t|I2},
366{"ll", "t,A(b)", 2, (int) M_LL_AB, INSN_MACRO },
367{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t|I3},
368{"lld", "t,A(b)", 3, (int) M_LLD_AB, INSN_MACRO },
45b14705
ILT		 369{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t },
370{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t },
371{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
2bef2d3e 372{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC },
45b14705 373{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
2bef2d3e
ILT		 374{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T },
375{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T },
45b14705
ILT		 376{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
377{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
2bef2d3e 378{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T }, /* lwc1 */
45b14705 379{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
2bef2d3e 380{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC },
45b14705 381{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
2bef2d3e 382{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC },
45b14705
ILT		 383{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
384{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t },
385{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
2bef2d3e
ILT		 386{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
387{"lcache", "t,A(b)", 2, (int) M_LWL_AB, INSN_MACRO }, /* as lwl */
45b14705
ILT		 388{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t },
389{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
2bef2d3e
ILT		 390{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
391{"flush", "t,A(b)", 2, (int) M_LWR_AB, INSN_MACRO }, /* as lwr */
9978cd4d 392{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t|I3},
2bef2d3e
ILT		 393{"lwu", "t,A(b)", 3, (int) M_LWU_AB, INSN_MACRO },
394{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0 },
395{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
396{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
397{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2 },
398{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3 },
45b14705
ILT		 399{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI },
400{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO },
401{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S },
402{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S },
403/* move is at the top of the table. */
404{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC },
2bef2d3e
ILT		 405{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S },
406{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S },
45b14705
ILT		 407{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC },
408{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC },
409{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI },
410{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO },
411{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T },
412{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T },
413{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
414{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
415{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
416{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
417{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
418{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
419{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
420{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
421{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t }, /* sub 0 */
422{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t }, /* subu 0 */
423{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S },
424{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S },
425/* nop is at the start of the table. */
426{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },
942a4965 427{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
27faaa41 428{"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },/*nor d,s,0*/
45b14705
ILT		 429{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t },
430{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
431{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s },
547998d2 432{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
45b14705
ILT		 433{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
434{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
547998d2 435{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
45b14705
ILT		 436{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
437{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
438{"rfe", "", 0x42000010, 0xffffffff, INSN_RFE },
439{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
440{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
441{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
442{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
2bef2d3e
ILT		 443{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|I3 },
444{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|I3 },
445{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|I2 },
446{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|I2 },
942a4965 447{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 448{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
84909073 449{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I2 },
2bef2d3e 450{"sc", "t,A(b)", 2, (int) M_SC_AB, INSN_MACRO },
84909073 451{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I3 },
2bef2d3e 452{"scd", "t,A(b)", 3, (int) M_SCD_AB, INSN_MACRO },
942a4965 453{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b|I3 },
45b14705
ILT		 454{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
455{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
942a4965
ILT		 456{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
457{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
2bef2d3e
ILT		 458{"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
459{"sdc1", "E,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
942a4965 460{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b|I2 },
2bef2d3e 461{"sdc2", "E,A(b)", 2, (int) M_SDC2_AB, INSN_MACRO },
942a4965 462{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b|I2 },
2bef2d3e 463{"sdc3", "E,A(b)", 2, (int) M_SDC3_AB, INSN_MACRO },
942a4965 464{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
2bef2d3e
ILT		 465{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
466{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
942a4965 467{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b|I3 },
2bef2d3e 468{"sdl", "t,A(b)", 3, (int) M_SDL_AB, INSN_MACRO },
942a4965 469{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b|I3 },
2bef2d3e 470{"sdr", "t,A(b)", 3, (int) M_SDR_AB, INSN_MACRO },
45b14705
ILT		 471{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
472{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
473{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
474{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
475{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
476{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
477{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
478{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
479{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
480{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
942a4965 481{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b },
45b14705
ILT		 482{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
483{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
484{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
485{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
486{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
487{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s },
488{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s }, /* sllv */
489{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t },
490{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t },
491{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
492{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s },
493{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s },
494{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t },
495{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
496{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
497{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
2bef2d3e 498{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|I2 },
942a4965 499{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|I2 },
45b14705
ILT		 500{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s },
501{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srav */
502{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t },
503{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s },
504{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srlv */
505{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t },
506{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t },
507{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
508{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T },
509{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T },
510{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t },
511{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
942a4965 512{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 513{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
942a4965 514{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b },
45b14705 515{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
942a4965
ILT		 516{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
517{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
45b14705
ILT		 518{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
519{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
942a4965 520{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b }, /* swc1 */
45b14705 521{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
942a4965 522{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b },
45b14705 523{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
942a4965 524{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b },
45b14705 525{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
942a4965 526{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 527{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
2bef2d3e
ILT		 528{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
529{"scache", "t,A(b)", 2, (int) M_SWL_AB, INSN_MACRO }, /* as swl */
942a4965 530{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 531{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
2bef2d3e
ILT		 532{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
533{"invalidate", "t,A(b)",2, (int) M_SWR_AB, INSN_MACRO }, /* as swr */
534{"sync", "", 0x0000000f, 0xffffffff, I2 },
9978cd4d
ILT		 535{"syscall", "", 0x0000000c, 0xffffffff, TRAP },
536{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP },
537{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP },
538{"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|I2|TRAP },
539{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP }, /* teqi */
2bef2d3e 540{"teq", "s,I", 2, (int) M_TEQ_I, INSN_MACRO },
9978cd4d
ILT		 541{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP },
542{"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|I2|TRAP },
543{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgei */
2bef2d3e 544{"tge", "s,I", 2, (int) M_TGE_I, INSN_MACRO },
9978cd4d
ILT		 545{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP },
546{"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|I2|TRAP },
547{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgeiu */
2bef2d3e 548{"tgeu", "s,I", 2, (int) M_TGEU_I, INSN_MACRO },
45b14705
ILT		 549{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB },
550{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB },
551{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB },
552{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB },
9978cd4d
ILT		 553{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP },
554{"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|I2|TRAP },
555{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tlti */
2bef2d3e 556{"tlt", "s,I", 2, (int) M_TLT_I, INSN_MACRO },
9978cd4d
ILT		 557{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP },
558{"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|I2|TRAP },
559{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tltiu */
2bef2d3e 560{"tltu", "s,I", 2, (int) M_TLTU_I, INSN_MACRO },
9978cd4d
ILT		 561{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP },
562{"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|I2|TRAP },
563{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tnei */
2bef2d3e
ILT		 564{"tne", "s,I", 2, (int) M_TNE_I, INSN_MACRO },
565{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|I3 },
566{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|I3 },
567{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|I2 },
568{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|I2 },
45b14705 569{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
2bef2d3e
ILT		 570{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
571{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
45b14705
ILT		 572{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
573{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
574{"ulh", "t,A", 0, (int) M_ULH_A, INSN_MACRO },
575{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
576{"ulhu", "t,A", 0, (int) M_ULHU_A, INSN_MACRO },
577{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
578{"ulw", "t,A", 0, (int) M_ULW_A, INSN_MACRO },
579{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
580{"ush", "t,A", 0, (int) M_USH_A, INSN_MACRO },
581{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
582{"usw", "t,A", 0, (int) M_USW_A, INSN_MACRO },
583{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t },
584{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
585{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s },
586/* No hazard protection on coprocessor instructions--they shouldn't
587 change the state of the processor and if they do it's up to the
588 user to put in nops as necessary. These are at the end so that the
589 disasembler recognizes more specific versions first. */
590{"c0", "C", 0x42000000, 0xfe000000, 0 },
591{"c1", "C", 0x46000000, 0xfe000000, 0 },
592{"c2", "C", 0x4a000000, 0xfe000000, 0 },
593{"c3", "C", 0x4e000000, 0xfe000000, 0 },
594};
595
596const int bfd_mips_num_opcodes =
597 ((sizeof mips_opcodes) / (sizeof (mips_opcodes[0])));
GDB Binutils - Deliverables
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