Commit | Line | Data |
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657e7cec | 1 | /* mips-opc.c -- MIPS opcode list. |
1f25f5d3 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
df7b86aa NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2012 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by Ralph Campbell and OSF |
6 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
e70f2590 | 7 | Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. |
af7ee8bf CD |
8 | MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom |
9 | Corporation (SiByte). | |
252b5132 | 10 | |
9b201bb5 | 11 | This file is part of the GNU opcodes library. |
252b5132 | 12 | |
9b201bb5 NC |
13 | This library is free software; you can redistribute it and/or modify |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 3, or (at your option) | |
16 | any later version. | |
252b5132 | 17 | |
9b201bb5 NC |
18 | It is distributed in the hope that it will be useful, but WITHOUT |
19 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
20 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
21 | License for more details. | |
252b5132 | 22 | |
9b201bb5 NC |
23 | You should have received a copy of the GNU General Public License |
24 | along with this file; see the file COPYING. If not, write to the | |
25 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
26 | MA 02110-1301, USA. */ | |
252b5132 | 27 | |
0d8dfecf | 28 | #include "sysdep.h" |
df7b86aa | 29 | #include <stdio.h> |
252b5132 | 30 | #include "opcode/mips.h" |
ab902481 RS |
31 | #include "mips-formats.h" |
32 | ||
33 | static unsigned char reg_0_map[] = { 0 }; | |
34 | ||
35 | /* Return the mips_operand structure for the operand at the beginning of P. */ | |
36 | ||
37 | const struct mips_operand * | |
38 | decode_mips_operand (const char *p) | |
39 | { | |
40 | switch (p[0]) | |
41 | { | |
42 | case '+': | |
43 | switch (p[1]) | |
44 | { | |
45 | case '1': HINT (5, 6); | |
46 | case '2': HINT (10, 6); | |
47 | case '3': HINT (15, 6); | |
48 | case '4': HINT (20, 6); | |
49 | ||
50 | case 'A': BIT (5, 6, 0); /* (0 .. 31) */ | |
51 | case 'B': MSB (5, 11, 1, TRUE, 32); /* (1 .. 32), 32-bit op */ | |
52 | case 'C': MSB (5, 11, 1, FALSE, 32); /* (1 .. 32), 32-bit op */ | |
53 | case 'E': BIT (5, 6, 32); /* (32 .. 63) */ | |
54 | case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */ | |
55 | case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */ | |
56 | case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */ | |
57 | case 'J': HINT (10, 11); | |
58 | case 'P': BIT (5, 6, 32); /* (32 .. 63) */ | |
59 | case 'Q': SINT (10, 6); | |
60 | case 'S': MSB (5, 11, 0, FALSE, 63); /* (0 .. 31), 64-bit op */ | |
61 | case 'X': BIT (5, 16, 32); /* (32 .. 63) */ | |
62 | case 'Z': REG (5, 0, FP); | |
63 | ||
64 | case 'a': SINT (8, 6); | |
65 | case 'b': SINT (8, 3); | |
66 | case 'c': INT_ADJ (9, 6, 255, 4, FALSE); /* (-256 .. 255) << 4 */ | |
67 | case 'i': JALX (26, 0, 2); | |
68 | case 'j': SINT (9, 7); | |
69 | case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */ | |
70 | case 's': MSB (5, 11, 0, FALSE, 31); /* (0 .. 31) */ | |
71 | case 't': REG (5, 16, COPRO); | |
72 | case 'x': BIT (5, 16, 0); /* (0 .. 31) */ | |
73 | case 'z': REG (5, 0, GP); | |
74 | } | |
75 | break; | |
76 | ||
77 | case '<': BIT (5, 6, 0); /* (0 .. 31) */ | |
78 | case '>': BIT (5, 6, 32); /* (32 .. 63) */ | |
79 | case '%': UINT (3, 21); | |
80 | case ':': SINT (7, 19); | |
81 | case '\'': HINT (6, 16); | |
82 | case '@': SINT (10, 16); | |
83 | case '!': UINT (1, 5); | |
84 | case '$': UINT (1, 4); | |
85 | case '*': REG (2, 18, ACC); | |
86 | case '&': REG (2, 13, ACC); | |
87 | case '~': SINT (12, 0); | |
88 | case '\\': BIT (3, 12, 0); /* (0 .. 7) */ | |
89 | ||
90 | case '0': SINT (6, 20); | |
91 | case '1': HINT (5, 6); | |
92 | case '2': HINT (2, 11); | |
93 | case '3': HINT (3, 21); | |
94 | case '4': HINT (4, 21); | |
95 | case '5': HINT (8, 16); | |
96 | case '6': HINT (5, 21); | |
97 | case '7': REG (2, 11, ACC); | |
98 | case '8': HINT (6, 11); | |
99 | case '9': REG (2, 21, ACC); | |
100 | ||
101 | case 'B': HINT (20, 6); | |
102 | case 'C': HINT (25, 0); | |
103 | case 'D': REG (5, 6, FP); | |
104 | case 'E': REG (5, 16, COPRO); | |
105 | case 'G': REG (5, 11, COPRO); | |
106 | case 'H': UINT (3, 0); | |
107 | case 'J': HINT (19, 6); | |
108 | case 'K': REG (5, 11, HW); | |
109 | case 'M': REG (3, 8, CCC); | |
110 | case 'N': REG (3, 18, CCC); | |
111 | case 'O': UINT (3, 21); | |
112 | case 'P': SPECIAL (5, 1, PERF_REG); | |
113 | case 'Q': SPECIAL (10, 16, MDMX_IMM_REG); | |
114 | case 'R': REG (5, 21, FP); | |
115 | case 'S': REG (5, 11, FP); | |
116 | case 'T': REG (5, 16, FP); | |
117 | case 'U': SPECIAL (10, 11, CLO_CLZ_DEST); | |
118 | case 'V': REG (5, 11, FP); | |
119 | case 'W': REG (5, 16, FP); | |
120 | case 'X': REG (5, 6, VEC); | |
121 | case 'Y': REG (5, 11, VEC); | |
122 | case 'Z': REG (5, 16, VEC); | |
123 | ||
124 | case 'a': JUMP (26, 0, 2); | |
125 | case 'b': REG (5, 21, GP); | |
126 | case 'c': HINT (10, 16); | |
127 | case 'd': REG (5, 11, GP); | |
128 | case 'e': UINT (3, 22) | |
129 | case 'g': REG (5, 11, COPRO); | |
130 | case 'h': HINT (5, 11); | |
131 | case 'i': HINT (16, 0); | |
132 | case 'j': SINT (16, 0); | |
133 | case 'k': HINT (5, 16); | |
134 | case 'o': SINT (16, 0); | |
135 | case 'p': BRANCH (16, 0, 2); | |
136 | case 'q': HINT (10, 6); | |
137 | case 'r': REG (5, 21, GP); | |
138 | case 's': REG (5, 21, GP); | |
139 | case 't': REG (5, 16, GP); | |
140 | case 'u': HINT (16, 0); | |
141 | case 'v': REG (5, 21, GP); | |
142 | case 'w': REG (5, 16, GP); | |
143 | case 'x': REG (0, 0, GP); | |
144 | case 'z': MAPPED_REG (0, 0, GP, reg_0_map); | |
145 | } | |
146 | return 0; | |
147 | } | |
252b5132 RH |
148 | |
149 | /* Short hand so the lines aren't too long. */ | |
150 | ||
151 | #define LDD INSN_LOAD_MEMORY_DELAY | |
152 | #define LCD INSN_LOAD_COPROC_DELAY | |
153 | #define UBD INSN_UNCOND_BRANCH_DELAY | |
154 | #define CBD INSN_COND_BRANCH_DELAY | |
155 | #define COD INSN_COPROC_MOVE_DELAY | |
156 | #define CLD INSN_COPROC_MEMORY_DELAY | |
157 | #define CBL INSN_COND_BRANCH_LIKELY | |
bcd530a7 RS |
158 | #define NODS INSN_NO_DELAY_SLOT |
159 | #define TRAP INSN_NO_DELAY_SLOT | |
252b5132 RH |
160 | #define SM INSN_STORE_MEMORY |
161 | ||
162 | #define WR_d INSN_WRITE_GPR_D | |
163 | #define WR_t INSN_WRITE_GPR_T | |
e93d7199 NC |
164 | #define WR_31 INSN_WRITE_GPR_31 |
165 | #define WR_D INSN_WRITE_FPR_D | |
252b5132 RH |
166 | #define WR_T INSN_WRITE_FPR_T |
167 | #define WR_S INSN_WRITE_FPR_S | |
e93d7199 NC |
168 | #define RD_s INSN_READ_GPR_S |
169 | #define RD_b INSN_READ_GPR_S | |
170 | #define RD_t INSN_READ_GPR_T | |
171 | #define RD_S INSN_READ_FPR_S | |
172 | #define RD_T INSN_READ_FPR_T | |
252b5132 RH |
173 | #define RD_R INSN_READ_FPR_R |
174 | #define WR_CC INSN_WRITE_COND_CODE | |
175 | #define RD_CC INSN_READ_COND_CODE | |
176 | #define RD_C0 INSN_COP | |
177 | #define RD_C1 INSN_COP | |
178 | #define RD_C2 INSN_COP | |
179 | #define RD_C3 INSN_COP | |
180 | #define WR_C0 INSN_COP | |
181 | #define WR_C1 INSN_COP | |
182 | #define WR_C2 INSN_COP | |
183 | #define WR_C3 INSN_COP | |
c27e721e | 184 | #define CP INSN_COP |
252b5132 RH |
185 | |
186 | #define WR_HI INSN_WRITE_HI | |
187 | #define RD_HI INSN_READ_HI | |
188 | #define MOD_HI WR_HI|RD_HI | |
189 | ||
190 | #define WR_LO INSN_WRITE_LO | |
191 | #define RD_LO INSN_READ_LO | |
192 | #define MOD_LO WR_LO|RD_LO | |
193 | ||
194 | #define WR_HILO WR_HI|WR_LO | |
195 | #define RD_HILO RD_HI|RD_LO | |
196 | #define MOD_HILO WR_HILO|RD_HILO | |
197 | ||
198 | #define IS_M INSN_MULT | |
199 | ||
9e836e3d FF |
200 | #define WR_MACC INSN2_WRITE_MDMX_ACC |
201 | #define RD_MACC INSN2_READ_MDMX_ACC | |
deec1734 | 202 | |
252b5132 RH |
203 | #define I1 INSN_ISA1 |
204 | #define I2 INSN_ISA2 | |
205 | #define I3 INSN_ISA3 | |
206 | #define I4 INSN_ISA4 | |
5fce5ddf | 207 | #define I5 INSN_ISA5 |
e7af610e | 208 | #define I32 INSN_ISA32 |
84ea6cf2 | 209 | #define I64 INSN_ISA64 |
af7ee8bf | 210 | #define I33 INSN_ISA32R2 |
5f74bc13 | 211 | #define I65 INSN_ISA64R2 |
56950294 MS |
212 | #define I3_32 INSN_ISA3_32 |
213 | #define I3_33 INSN_ISA3_32R2 | |
214 | #define I4_32 INSN_ISA4_32 | |
215 | #define I4_33 INSN_ISA4_32R2 | |
216 | #define I5_33 INSN_ISA5_32R2 | |
e7af610e | 217 | |
44426910 | 218 | /* MIPS64 MIPS-3D ASE support. */ |
d301a56b | 219 | #define M3D ASE_MIPS3D |
1f25f5d3 | 220 | |
39a7806d | 221 | /* MIPS32 SmartMIPS ASE support. */ |
d301a56b | 222 | #define SMT ASE_SMARTMIPS |
39a7806d | 223 | |
deec1734 | 224 | /* MIPS64 MDMX ASE support. */ |
d301a56b | 225 | #define MX ASE_MDMX |
deec1734 | 226 | |
350cc38d MS |
227 | #define IL2E (INSN_LOONGSON_2E) |
228 | #define IL2F (INSN_LOONGSON_2F) | |
fd503541 | 229 | #define IL3A (INSN_LOONGSON_3A) |
350cc38d | 230 | |
252b5132 RH |
231 | #define P3 INSN_4650 |
232 | #define L1 INSN_4010 | |
9752cf1b | 233 | #define V1 (INSN_4100 | INSN_4111 | INSN_4120) |
252b5132 | 234 | #define T3 INSN_3900 |
e407c74b NC |
235 | /* Emotion Engine MIPS r5900. */ |
236 | #define EE INSN_5900 | |
99c14723 | 237 | #define M1 INSN_10000 |
2228315b | 238 | #define SB1 INSN_SB1 |
9752cf1b RS |
239 | #define N411 INSN_4111 |
240 | #define N412 INSN_4120 | |
241 | #define N5 (INSN_5400 | INSN_5500) | |
242 | #define N54 INSN_5400 | |
243 | #define N55 INSN_5500 | |
432233b3 AP |
244 | #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2) |
245 | #define IOCTP (INSN_OCTEONP | INSN_OCTEON2) | |
246 | #define IOCT2 INSN_OCTEON2 | |
52b6b6b9 | 247 | #define XLR INSN_XLR |
d301a56b RS |
248 | #define IVIRT ASE_VIRT |
249 | #define IVIRT64 ASE_VIRT64 | |
252b5132 | 250 | |
e93d7199 | 251 | #define G1 (T3 \ |
e407c74b | 252 | |EE \ |
252b5132 RH |
253 | ) |
254 | ||
99c14723 | 255 | #define G2 (T3 \ |
252b5132 RH |
256 | ) |
257 | ||
99c14723 | 258 | #define G3 (I4 \ |
e407c74b | 259 | |EE \ |
99c14723 | 260 | ) |
252b5132 | 261 | |
e407c74b NC |
262 | /* 64 bit CPU with 32 bit FPU (single float). */ |
263 | #define SF EE | |
264 | ||
265 | /* Support for 128 bit MMI instructions. */ | |
266 | #define MMI EE | |
267 | ||
268 | /* 64 bit CPU with only 32 bit multiplication/division support. */ | |
269 | #define M32 EE | |
270 | ||
fd25c5a9 CF |
271 | /* MIPS DSP ASE support. |
272 | NOTE: | |
273 | 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair | |
274 | of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have | |
275 | the same structure as $ac0 (HI + LO). For DSP instructions that write or | |
276 | read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a | |
39a7806d | 277 | (RD_HILO) attributes, such that HILO dependencies are maintained |
fd25c5a9 CF |
278 | conservatively. |
279 | ||
280 | 2. For some mul. instructions that use integer registers as destinations | |
39a7806d | 281 | but destroy HI+LO as side-effect, we add WR_HILO to their attributes. |
fd25c5a9 CF |
282 | |
283 | 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields | |
284 | (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write | |
285 | certain fields of the DSP control register. For simplicity, we decide not | |
39a7806d | 286 | to track dependencies of these fields. |
fd25c5a9 CF |
287 | However, "bposge32" is a branch instruction that depends on the "pos" |
288 | field. In order to make sure that GAS does not reorder DSP instructions | |
bcd530a7 RS |
289 | that writes the "pos" field and "bposge32", we add DSP_VOLA |
290 | (INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos" | |
291 | field. */ | |
fd25c5a9 CF |
292 | |
293 | #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ | |
294 | #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ | |
295 | #define MOD_a WR_a|RD_a | |
bcd530a7 | 296 | #define DSP_VOLA INSN_NO_DELAY_SLOT |
d301a56b RS |
297 | #define D32 ASE_DSP |
298 | #define D33 ASE_DSPR2 | |
299 | #define D64 ASE_DSP64 | |
fd25c5a9 | 300 | |
61cc0267 | 301 | /* MIPS MT ASE support. */ |
d301a56b | 302 | #define MT32 ASE_MT |
61cc0267 | 303 | |
98675402 RS |
304 | /* Loongson support. */ |
305 | #define WR_z INSN2_WRITE_GPR_Z | |
306 | #define WR_Z INSN2_WRITE_FPR_Z | |
307 | #define RD_z INSN2_READ_GPR_Z | |
308 | #define RD_Z INSN2_READ_FPR_Z | |
309 | #define RD_d INSN2_READ_GPR_D | |
310 | ||
dec0624d | 311 | /* MIPS MCU (MicroController) ASE support. */ |
d301a56b | 312 | #define MC ASE_MCU |
dec0624d | 313 | |
7f3c4072 CM |
314 | /* MIPS Enhanced VA Scheme. */ |
315 | #define EVA ASE_EVA | |
316 | ||
317 | /* TLB invalidate instruction support. */ | |
318 | #define TLBINV ASE_EVA | |
319 | ||
252b5132 RH |
320 | /* The order of overloaded instructions matters. Label arguments and |
321 | register arguments look the same. Instructions that can have either | |
322 | for arguments must apear in the correct order in this table for the | |
323 | assembler to pick the right one. In other words, entries with | |
324 | immediate operands must apear after the same instruction with | |
325 | registers. | |
326 | ||
44426910 CD |
327 | Because of the lookup algorithm used, entries with the same opcode |
328 | name must be contiguous. | |
329 | ||
252b5132 RH |
330 | Many instructions are short hand for other instructions (i.e., The |
331 | jal <register> instruction is short for jalr <register>). */ | |
332 | ||
4372b673 NC |
333 | const struct mips_opcode mips_builtin_opcodes[] = |
334 | { | |
252b5132 RH |
335 | /* These instructions appear first so that the disassembler will find |
336 | them first. The assemblers uses a hash table based on the | |
337 | instruction name anyhow. */ | |
e7ae278d RS |
338 | /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ |
339 | {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3, 0, 0 }, | |
340 | {"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3, 0, 0 }, | |
341 | {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33, 0, 0 }, | |
342 | {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ | |
343 | {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ | |
344 | {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ | |
345 | {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ | |
346 | {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1, 0, 0 }, /* ori */ | |
347 | {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, | |
348 | {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, | |
349 | {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3, 0, 0 },/* daddu */ | |
350 | {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1, 0, 0 },/* addu */ | |
351 | {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1, 0, 0 },/* or */ | |
352 | {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* beq 0,0 */ | |
353 | {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* bgez 0 */ | |
354 | {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1, 0, 0 },/* bgezal 0*/ | |
252b5132 | 355 | |
98675402 RS |
356 | /* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 |
357 | instructions. Put them here so that disassembler will find them first. | |
358 | The assemblers uses a hash table based on the instruction name anyhow. */ | |
e7ae278d RS |
359 | {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_d|RD_s, 0, IL3A, 0, 0 }, |
360 | {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_d|RD_s, 0, IL3A, 0, 0 }, | |
361 | {"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_s|RD_t, RD_d, IL3A, 0, 0 }, | |
362 | {"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_d|RD_s, 0, IL3A, 0, 0 }, | |
363 | {"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_s|RD_t, 0, IL3A, 0, 0 }, | |
364 | {"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_s|RD_t, 0, IL3A, 0, 0 }, | |
365 | {"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
366 | {"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
367 | {"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
368 | {"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
369 | {"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
370 | {"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
371 | {"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
372 | {"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
373 | {"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
374 | {"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
375 | {"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
376 | {"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
377 | {"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
378 | {"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
379 | {"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
380 | {"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
381 | {"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
382 | {"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
383 | {"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
384 | {"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
385 | {"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
386 | {"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
387 | {"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
388 | {"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
389 | {"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A, 0, 0 }, | |
390 | {"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A, 0, 0 }, | |
391 | {"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A, 0, 0 }, | |
392 | {"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A, 0, 0 }, | |
393 | {"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A, 0, 0 }, | |
394 | {"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A, 0, 0 }, | |
395 | {"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A, 0, 0 }, | |
396 | {"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A, 0, 0 }, | |
397 | {"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
398 | {"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
399 | {"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
400 | {"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
401 | {"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
402 | {"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
403 | {"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
404 | {"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
405 | {"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
406 | {"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A, 0, 0 }, | |
407 | {"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
408 | {"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A, 0, 0 }, | |
409 | {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_t|RD_b|LDD, WR_z, IL3A, 0, 0 }, | |
410 | {"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_t|RD_b|SM, RD_z, IL3A, 0, 0 }, | |
411 | {"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_T|RD_b|LDD, WR_Z, IL3A, 0, 0 }, | |
412 | {"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_T|RD_b|SM, RD_Z, IL3A, 0, 0 }, | |
98675402 | 413 | |
e7ae278d RS |
414 | {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, |
415 | {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1, 0, 0 }, | |
416 | {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1, 0, SF }, | |
417 | {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
418 | {"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E, 0, 0 }, | |
419 | {"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC, 0 }, | |
420 | {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, | |
421 | {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
422 | {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, | |
423 | {"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
424 | {"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
425 | {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1, 0, 0 }, | |
426 | {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF }, | |
427 | {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 428 | {"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
429 | {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F, 0, 0 }, |
430 | {"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E, 0, 0 }, | |
431 | {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
432 | {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
433 | {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, | |
434 | {"adda.s", "S,T", 0x46000018, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE, 0, 0 }, | |
435 | {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1, 0, 0 }, | |
436 | {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1, 0, 0 }, | |
437 | {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
438 | {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, | |
439 | {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, M3D, 0 }, | |
440 | {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
441 | {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
442 | {"addu", "D,S,T", 0x45800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
443 | {"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
444 | {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 445 | {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
446 | {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
447 | {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, I5_33, 0, 0 }, | |
448 | {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, SB1, MX, 0 }, | |
449 | {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, 0, MX, 0 }, | |
450 | {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
451 | {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, | |
452 | {"and", "D,S,T", 0x47c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
453 | {"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
454 | {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 455 | {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
456 | {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
457 | {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1, 0, 0 }, | |
458 | {"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC, 0 }, | |
459 | {"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, | |
460 | {"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT, 0, 0 }, | |
252b5132 RH |
461 | /* b is at the top of the table. */ |
462 | /* bal is at the top of the table. */ | |
e7ae278d RS |
463 | {"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT, 0, 0 }, |
464 | {"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT, 0, 0 }, /* bbit032 */ | |
465 | {"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_s|CBD, 0, IOCT, 0, 0 }, | |
466 | {"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT, 0, 0 }, | |
467 | {"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT, 0, 0 }, /* bbit132 */ | |
468 | {"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_s|CBD, 0, IOCT, 0, 0 }, | |
61cc0267 | 469 | /* bc0[tf]l? are at the bottom of the table. */ |
e7ae278d RS |
470 | {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, 0, M3D, 0 }, |
471 | {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, 0, M3D, 0 }, | |
472 | {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, 0, M3D, 0 }, | |
473 | {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, 0, M3D, 0 }, | |
474 | {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1, 0, 0 }, | |
475 | {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
476 | {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3, 0, 0 }, | |
477 | {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
478 | {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1, 0, 0 }, | |
479 | {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
480 | {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3, 0, 0 }, | |
481 | {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
6f14957b | 482 | /* bc2* are at the bottom of the table. */ |
39a7806d | 483 | /* bc3* are at the bottom of the table. */ |
e7ae278d RS |
484 | {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1, 0, 0 }, |
485 | {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3, 0, 0 }, | |
486 | {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1, 0, 0 }, | |
487 | {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, | |
488 | {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3, 0, 0 }, | |
489 | {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
490 | {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, | |
491 | {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
492 | {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
493 | {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
494 | {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, | |
495 | {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
496 | {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
497 | {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
498 | {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1, 0, 0 }, | |
499 | {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3, 0, 0 }, | |
500 | {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1, 0, 0 }, | |
501 | {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3, 0, 0 }, | |
502 | {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, | |
503 | {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
504 | {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
505 | {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
506 | {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, | |
507 | {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
508 | {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
509 | {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
510 | {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1, 0, 0 }, | |
511 | {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3, 0, 0 }, | |
512 | {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, | |
513 | {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
514 | {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
515 | {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
516 | {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, | |
517 | {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
518 | {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
519 | {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
520 | {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1, 0, 0 }, | |
521 | {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3, 0, 0 }, | |
522 | {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, | |
523 | {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
524 | {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
525 | {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
526 | {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, | |
527 | {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
528 | {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
529 | {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
530 | {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1, 0, 0 }, | |
531 | {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3, 0, 0 }, | |
532 | {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1, 0, 0 }, | |
533 | {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3, 0, 0 }, | |
534 | {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1, 0, 0 }, | |
535 | {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3, 0, 0 }, | |
536 | {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1, 0, 0 }, | |
537 | {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
538 | {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3, 0, 0 }, | |
539 | {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
540 | {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 }, | |
541 | {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, | |
542 | {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 }, | |
543 | {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
544 | {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
545 | {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, 0 }, | |
546 | {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
547 | {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
548 | {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
549 | {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
550 | {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
551 | {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
552 | {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
553 | {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
554 | {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
555 | {"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
556 | {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
557 | {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
558 | {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
559 | {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, 0 }, | |
560 | {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
561 | {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 562 | {"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
563 | {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, |
564 | {"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
565 | {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
566 | {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
567 | {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
568 | {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
569 | {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
570 | {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
571 | {"c.ueq.ps", "S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
572 | {"c.ueq.ps", "S,T", 0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
573 | {"c.ueq.ps", "M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
574 | {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
575 | {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
576 | {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
577 | {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
578 | {"c.olt.ps", "S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
579 | {"c.olt.ps", "S,T", 0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
580 | {"c.olt.ps", "M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
581 | {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
582 | {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
583 | {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
584 | {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
585 | {"c.ult.ps", "S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
586 | {"c.ult.ps", "S,T", 0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
587 | {"c.ult.ps", "M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
588 | {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
589 | {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
590 | {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
591 | {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
592 | {"c.ole.ps", "S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
593 | {"c.ole.ps", "S,T", 0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
594 | {"c.ole.ps", "M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
595 | {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
596 | {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
597 | {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
598 | {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
599 | {"c.ule.ps", "S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
600 | {"c.ule.ps", "S,T", 0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
601 | {"c.ule.ps", "M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
602 | {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
603 | {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
604 | {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
605 | {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
606 | {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
607 | {"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
608 | {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
609 | {"c.ngle.d", "S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
610 | {"c.ngle.d", "M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
611 | {"c.ngle.s", "S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
612 | {"c.ngle.s", "M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
613 | {"c.ngle.ps", "S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
614 | {"c.ngle.ps", "S,T", 0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
615 | {"c.ngle.ps", "M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
616 | {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
617 | {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
618 | {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
619 | {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
620 | {"c.seq.ps", "S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
621 | {"c.seq.ps", "S,T", 0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
622 | {"c.seq.ps", "M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
623 | {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
624 | {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
625 | {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
626 | {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
627 | {"c.ngl.ps", "S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
628 | {"c.ngl.ps", "S,T", 0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
629 | {"c.ngl.ps", "M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
630 | {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
631 | {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
632 | {"c.lt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, EE, 0, 0 }, | |
633 | {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
634 | {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
635 | {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 636 | {"c.lt.ob", "S,Q", 0x48000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
637 | {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, |
638 | {"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
639 | {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
640 | {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
641 | {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
642 | {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
643 | {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
644 | {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
645 | {"c.nge.ps", "S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
646 | {"c.nge.ps", "S,T", 0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
647 | {"c.nge.ps", "M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
648 | {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
649 | {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
650 | {"c.le.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, EE, 0, 0 }, | |
651 | {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
652 | {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
653 | {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 654 | {"c.le.ob", "S,Q", 0x48000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
655 | {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, |
656 | {"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
657 | {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
658 | {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
659 | {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, 0, SF }, | |
660 | {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
661 | {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE }, | |
662 | {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
663 | {"c.ngt.ps", "S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
664 | {"c.ngt.ps", "S,T", 0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
665 | {"c.ngt.ps", "M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
666 | {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
667 | {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
668 | {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
669 | {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
670 | {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
671 | {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
672 | {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
673 | {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
674 | {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
675 | {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
676 | {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
677 | {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
678 | {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
679 | {"cabs.nge.ps", "M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
680 | {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
681 | {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
682 | {"cabs.ngl.ps", "M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
683 | {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
684 | {"cabs.ngle.d", "M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
685 | {"cabs.ngle.ps", "M,S,T", 0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
686 | {"cabs.ngle.s", "M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
687 | {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
688 | {"cabs.ngt.ps", "M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
689 | {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
690 | {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
691 | {"cabs.ole.ps", "M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
692 | {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
693 | {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
694 | {"cabs.olt.ps", "M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
695 | {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
696 | {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
697 | {"cabs.seq.ps", "M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
698 | {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
699 | {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
700 | {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
701 | {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
702 | {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
703 | {"cabs.ueq.ps", "M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
704 | {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
705 | {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
706 | {"cabs.ule.ps", "M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
707 | {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
708 | {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
709 | {"cabs.ult.ps", "M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
710 | {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
711 | {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
712 | {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
713 | {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
39a7806d | 714 | /* CW4010 instructions which are aliases for the cache instruction. */ |
e7ae278d RS |
715 | {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1, 0, 0 }, |
716 | {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1, 0, 0 }, | |
717 | {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1, 0, 0 }, | |
718 | {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1, 0, 0 }, | |
719 | {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3, 0, 0}, | |
720 | {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, 0}, | |
721 | {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33, 0, 0 }, | |
722 | {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
723 | {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, 0, SF }, | |
724 | {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE }, | |
725 | {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
726 | {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1, 0, 0 }, | |
727 | {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1, 0, 0 }, | |
6f14957b | 728 | /* cfc2 is at the bottom of the table. */ |
39a7806d | 729 | /* cfc3 is at the bottom of the table. */ |
e7ae278d RS |
730 | {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, 0, MT32, 0 }, |
731 | {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, 0, MT32, 0 }, | |
732 | {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
733 | {"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, | |
734 | {"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, /* cins32 */ | |
735 | {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, | |
736 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55, 0, 0 }, | |
737 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55, 0, 0 }, | |
738 | {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
739 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1, 0, 0 }, | |
740 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1, 0, 0 }, | |
6f14957b | 741 | /* ctc2 is at the bottom of the table. */ |
39a7806d | 742 | /* ctc3 is at the bottom of the table. */ |
e7ae278d RS |
743 | {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, 0, MT32, 0 }, |
744 | {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, 0, MT32, 0 }, | |
745 | {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
746 | {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33, 0, 0 }, | |
747 | {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, 0, SF }, | |
748 | {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, 0, SF }, | |
749 | {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33, 0, 0 }, | |
750 | {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
751 | {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
752 | {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, 0, SF }, | |
753 | {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1, 0, 0 }, | |
754 | {"cvt.s.pl", "D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33, 0, 0 }, | |
755 | {"cvt.s.pu", "D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33, 0, 0 }, | |
756 | {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, 0, SF }, | |
757 | {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1, 0, EE }, | |
758 | {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, 0, M3D, 0 }, | |
759 | {"cvt.ps.s", "D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33, 0, 0 }, | |
760 | {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, 0, M3D, 0 }, | |
761 | {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, | |
762 | {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3, 0, 0 }, | |
763 | {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, | |
764 | {"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
765 | {"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
766 | {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3, 0, 0 }, | |
767 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3, 0, 0 }, | |
768 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3, 0, 0 }, | |
769 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, | |
770 | {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR, 0, 0 }, | |
771 | {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, | |
772 | {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55, 0, 0 }, | |
773 | {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55, 0, 0 }, | |
252b5132 | 774 | /* dctr and dctw are used on the r5000. */ |
e7ae278d RS |
775 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3, 0, 0 }, |
776 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3, 0, 0 }, | |
777 | {"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2, 0, 0 }, | |
778 | {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65, 0, 0 }, | |
779 | {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65, 0, 0 }, | |
780 | {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65, 0, 0 }, | |
781 | {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65, 0, 0 }, | |
252b5132 | 782 | /* For ddiv, see the comments about div. */ |
e7ae278d RS |
783 | {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, 0, M32 }, |
784 | {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, M32 }, | |
785 | {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
252b5132 | 786 | /* For ddivu, see the comments about div. */ |
e7ae278d RS |
787 | {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, 0, M32 }, |
788 | {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32 }, | |
789 | {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
790 | {"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 }, | |
6a819047 | 791 | {"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 }, |
e7ae278d RS |
792 | {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33, 0, 0 }, |
793 | {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65, 0, 0 }, | |
794 | {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65, 0, 0 }, | |
795 | {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65, 0, 0 }, | |
796 | {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65, 0, 0 }, | |
252b5132 RH |
797 | /* The MIPS assembler treats the div opcode with two operands as |
798 | though the first operand appeared twice (the first operand is both | |
799 | a source and a destination). To get the div machine instruction, | |
800 | you must use an explicit destination of $0. */ | |
e7ae278d | 801 | {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 }, |
6a819047 | 802 | {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_t|WR_HILO, 0, I1, 0, 0 }, |
e7ae278d RS |
803 | {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, |
804 | {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
805 | {"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE, 0, 0 }, | |
6a819047 | 806 | {"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_t|WR_HILO, 0, EE, 0, 0 }, |
e7ae278d RS |
807 | {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF }, |
808 | {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1, 0, 0 }, | |
809 | {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, 0, 0 }, | |
252b5132 | 810 | /* For divu, see the comments about div. */ |
e7ae278d | 811 | {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 }, |
6a819047 | 812 | {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_t|WR_HILO, 0, I1, 0, 0 }, |
e7ae278d RS |
813 | {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, |
814 | {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
815 | {"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE, 0, 0 }, | |
6a819047 | 816 | {"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_t|WR_HILO, 0, EE, 0, 0 }, |
e7ae278d RS |
817 | {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 }, |
818 | {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
819 | {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3, 0, 0 }, /* addiu */ | |
820 | {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3, 0, 0 }, /* ori */ | |
821 | {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, | |
822 | {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
823 | {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
824 | {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
825 | {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
826 | {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
827 | {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
828 | {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
829 | {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412, 0, 0 }, | |
830 | {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411, 0, 0 }, | |
831 | {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3, 0, EE }, | |
832 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64, 0, 0 }, | |
833 | {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, LCD|WR_t|RD_C0, 0, 0, IVIRT64, 0 }, | |
834 | {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT64, 0 }, | |
835 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | |
836 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32, 0 }, | |
837 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3, 0, EE }, | |
838 | {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64, 0, 0 }, | |
839 | {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, | |
840 | {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, | |
841 | {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, 0, SF }, | |
842 | {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, 0, SF }, | |
843 | {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3, 0, SF }, | |
844 | {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3, 0, SF }, | |
6f14957b MR |
845 | /* dmfc2 is at the bottom of the table. */ |
846 | /* dmtc2 is at the bottom of the table. */ | |
39a7806d TS |
847 | /* dmfc3 is at the bottom of the table. */ |
848 | /* dmtc3 is at the bottom of the table. */ | |
e7ae278d RS |
849 | {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCT, 0, 0 }, |
850 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32 }, | |
851 | {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32 }, | |
852 | {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, M32 }, | |
853 | {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, M32 }, | |
854 | {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, M32 }, | |
855 | {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, M32 }, | |
856 | {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, 0, M32 }, | |
857 | {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, 0, M32 }, | |
858 | {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3, 0, 0 }, /* dsub 0 */ | |
859 | {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3, 0, 0 }, /* dsubu 0*/ | |
860 | {"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_d|RD_s, 0, IOCT, 0, 0 }, | |
861 | {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, 0, M32 }, | |
862 | {"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, M32 }, | |
863 | {"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
864 | {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, 0, M32 }, | |
865 | {"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, M32 }, | |
866 | {"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
867 | {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5, 0, 0 }, | |
868 | {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, | |
869 | {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, | |
870 | {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, | |
871 | {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, | |
872 | {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65, 0, 0 }, | |
873 | {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65, 0, 0 }, | |
874 | {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65, 0, 0 }, | |
875 | {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65, 0, 0 }, | |
876 | {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65, 0, 0 }, | |
877 | {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65, 0, 0 }, | |
878 | {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65, 0, 0 }, | |
879 | {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65, 0, 0 }, | |
880 | {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65, 0, 0 }, | |
881 | {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65, 0, 0 }, | |
882 | {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65, 0, 0 }, | |
883 | {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3, 0, 0 }, | |
884 | {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, | |
885 | {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3, 0, 0 }, /* dsllv */ | |
886 | {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, /* dsll32 */ | |
887 | {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, | |
888 | {"dsll", "D,S,T", 0x45a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
889 | {"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
890 | {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3, 0, 0 }, | |
891 | {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, | |
892 | {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3, 0, 0 }, /* dsrav */ | |
893 | {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, /* dsra32 */ | |
894 | {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, | |
895 | {"dsra", "D,S,T", 0x45e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
896 | {"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
897 | {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3, 0, 0 }, | |
898 | {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, | |
899 | {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3, 0, 0 }, /* dsrlv */ | |
900 | {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, /* dsrl32 */ | |
901 | {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3, 0, 0 }, | |
902 | {"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
903 | {"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
904 | {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3, 0, 0 }, | |
905 | {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, | |
906 | {"dsub", "D,S,T", 0x45e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
907 | {"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
908 | {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3, 0, 0 }, | |
909 | {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, | |
910 | {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | |
911 | {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32, 0 }, | |
912 | {"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 }, | |
6a819047 | 913 | {"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 }, |
e7ae278d RS |
914 | {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33, 0, 0 }, |
915 | {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | |
916 | {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32, 0 }, | |
917 | {"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 }, | |
918 | {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | |
919 | {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32, 0 }, | |
920 | {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33, 0, 0 }, | |
921 | {"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, | |
922 | {"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, /* exts32 */ | |
923 | {"exts", "t,r,+p,+S", 0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, | |
924 | {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33, 0, 0 }, | |
925 | {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
926 | {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, 0, SF }, | |
927 | {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, 0 }, | |
928 | {"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 }, | |
929 | {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, | |
930 | {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, | |
931 | {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33, 0, 0 }, | |
932 | {"iret", "", 0x42000038, 0xffffffff, NODS, 0, 0, MC, 0 }, | |
933 | {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1, 0, 0 }, | |
39a7806d TS |
934 | /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with |
935 | the same hazard barrier effect. */ | |
e7ae278d RS |
936 | {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32, 0, 0 }, |
937 | {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1, 0, 0 }, /* jr */ | |
252b5132 RH |
938 | /* SVR4 PIC code requires special handling for j, so it must be a |
939 | macro. */ | |
e7ae278d | 940 | {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 }, |
252b5132 RH |
941 | /* This form of j is used by the disassembler and internally by the |
942 | assembler, but will never match user input (because the line above | |
943 | will match first). */ | |
e7ae278d | 944 | {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1, 0, 0 }, |
344c74a6 | 945 | {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_31, 0, I1, 0, 0 }, |
e7ae278d | 946 | {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1, 0, 0 }, |
39a7806d TS |
947 | /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr |
948 | with the same hazard barrier effect. */ | |
344c74a6 | 949 | {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_31, 0, I32, 0, 0 }, |
e7ae278d | 950 | {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32, 0, 0 }, |
252b5132 RH |
951 | /* SVR4 PIC code requires special handling for jal, so it must be a |
952 | macro. */ | |
e7ae278d RS |
953 | {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 }, |
954 | {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1, 0, 0 }, | |
955 | {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1, 0, 0 }, | |
252b5132 RH |
956 | /* This form of jal is used by the disassembler and internally by the |
957 | assembler, but will never match user input (because the line above | |
958 | will match first). */ | |
e7ae278d RS |
959 | {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1, 0, 0 }, |
960 | {"jalx", "+i", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1, 0, 0 }, | |
961 | {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
962 | {"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 }, | |
963 | {"laad", "d,(b),t", 0x700004df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 }, | |
964 | {"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, | |
965 | {"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, | |
6a819047 RS |
966 | {"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, |
967 | {"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, | |
968 | {"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, | |
969 | {"laid", "d,(b)", 0x700000df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, | |
e7ae278d RS |
970 | {"las", "d,(b)", 0x7000029f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, |
971 | {"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 }, | |
972 | {"law", "d,(b),t", 0x7000059f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 }, | |
973 | {"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 }, | |
974 | {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1, 0, 0 }, | |
975 | {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
976 | {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1, 0, 0 }, | |
977 | {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
978 | {"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 }, | |
979 | {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2, D32, 0}, | |
980 | {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2, D64, 0}, | |
981 | {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2, D32, 0}, | |
982 | {"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 }, | |
983 | {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2, D32, 0}, | |
984 | {"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 }, | |
985 | {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
704897fb | 986 | /* The macro has to be first to handle o32 correctly. */ |
e7ae278d RS |
987 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, |
988 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3, 0, 0 }, | |
989 | {"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR, 0, 0 }, | |
990 | {"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR, 0, 0 }, | |
991 | {"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR, 0, 0 }, | |
992 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, 0, SF }, | |
993 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, 0, SF }, | |
994 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | |
995 | {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | |
996 | {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, 0, SF }, /* ldc1 */ | |
997 | {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, | |
998 | {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
999 | {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
1000 | {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
1001 | {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
1002 | {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3, 0, 0 }, | |
1003 | {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1004 | {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3, 0, 0 }, | |
1005 | {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1006 | {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4_33, 0, 0 }, | |
1007 | {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1, 0, 0 }, | |
1008 | {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1009 | {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1, 0, 0 }, | |
1010 | {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
252b5132 | 1011 | /* li is at the start of the table. */ |
e7ae278d RS |
1012 | {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, |
1013 | {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, | |
1014 | {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1015 | {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1016 | {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2, 0, EE }, | |
1017 | {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2, 0, EE }, | |
1018 | {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3, 0, EE }, | |
1019 | {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE }, | |
1020 | {"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, 0, MMI, 0, 0 }, | |
1021 | {"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, | |
1022 | {"lqc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_b|WR_C2, 0, EE, 0, 0 }, | |
1023 | {"lqc2", "E,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, | |
1024 | {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1, 0, 0 }, | |
1025 | {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55, 0, 0}, | |
1026 | {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1, 0, 0 }, | |
1027 | {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1028 | {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
1029 | {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
1030 | {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1, 0, 0 }, | |
1031 | {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1, 0, 0 }, | |
1032 | {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1033 | {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1034 | {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1, 0, 0 }, /* lwc1 */ | |
1035 | {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1036 | {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1037 | {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1038 | {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1039 | {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1040 | {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1, 0, 0 }, | |
1041 | {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1042 | {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2, 0, 0 }, /* same */ | |
1043 | {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as lwl */ | |
1044 | {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1, 0, 0 }, | |
1045 | {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1046 | {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2, 0, 0 }, /* same */ | |
1047 | {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as lwr */ | |
1048 | {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, 0, MT32, 0 }, | |
1049 | {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3, 0, 0 }, | |
1050 | {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1051 | {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0, I4_33, 0, 0 }, | |
1052 | {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, 0, SMT, 0 }, | |
1053 | {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1054 | {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1055 | {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1056 | {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1057 | {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1058 | {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1059 | {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1060 | {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1061 | {"macchius", "d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1062 | {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1063 | {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1064 | {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412, 0, 0 }, | |
1065 | {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3, 0, 0 }, | |
1066 | {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3, 0, 0 }, | |
1067 | {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33, 0, 0 }, | |
1068 | {"madd.d", "D,S,T", 0x46200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1069 | {"madd.d", "D,S,T", 0x72200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, | |
1070 | {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33, 0, 0 }, | |
1071 | {"madd.s", "D,S,T", 0x46000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
1072 | {"madd.s", "D,S,T", 0x72000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F, 0, 0 }, | |
1073 | {"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE, 0, 0 }, | |
1074 | {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 }, | |
1075 | {"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1d2db237 | 1076 | {"madd.ps", "D,S,T", 0x72c00018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, |
e7ae278d RS |
1077 | {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1, 0, 0 }, |
1078 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1079 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1080 | {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1081 | {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1, 0, 0 }, | |
1082 | {"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1083 | {"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE, 0, 0 }, | |
1084 | {"madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE, 0, 0 }, | |
1085 | {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, 0, SMT, 0 }, | |
1086 | {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1, 0, 0 }, | |
1087 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1088 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1089 | {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1090 | {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1, 0, 0 }, | |
1091 | {"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1092 | {"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE, 0, 0 }, | |
1093 | {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411, 0, 0 }, | |
1094 | {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1095 | {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1096 | {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1097 | {"max.s", "D,S,T", 0x46000028, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE, 0, 0 }, | |
1098 | {"mfbpc", "t", 0x4000c000, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE, 0, 0 }, | |
1099 | {"mfdab", "t", 0x4000c004, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE, 0, 0 }, | |
1100 | {"mfdabm", "t", 0x4000c005, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE, 0, 0 }, | |
1101 | {"mfdvb", "t", 0x4000c006, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE, 0, 0 }, | |
1102 | {"mfdvbm", "t", 0x4000c007, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE, 0, 0 }, | |
1103 | {"mfiab", "t", 0x4000c002, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE, 0, 0 }, | |
1104 | {"mfiabm", "t", 0x4000c003, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE, 0, 0 }, | |
1105 | {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5|EE, 0, 0 }, | |
1106 | {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5|EE, 0, 0 }, | |
1107 | {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, 0, MT32, 0 }, | |
1108 | {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, 0, MT32, 0 }, | |
1109 | {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32, 0 }, | |
1110 | {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32, 0 }, | |
1111 | {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, 0, MT32, 0 }, | |
1112 | {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, 0, MT32, 0 }, | |
1113 | {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1114 | {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, 0, MT32, 0 }, | |
1115 | {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, 0, MT32, 0 }, | |
1116 | {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, 0, MT32, 0 }, | |
1117 | {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, 0, MT32, 0 }, | |
1118 | {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1119 | {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, 0, MT32, 0 }, | |
1120 | {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, 0, MT32, 0 }, | |
1121 | {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, 0, MT32, 0 }, | |
1122 | {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, 0, MT32, 0 }, | |
1123 | {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, 0, MT32, 0 }, | |
1124 | {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1, 0, 0 }, | |
1125 | {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32, 0, 0 }, | |
1126 | {"mfgc0", "t,G", 0x40600000, 0xffe007ff, LCD|WR_t|RD_C0, 0, 0, IVIRT, 0 }, | |
1127 | {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT, 0 }, | |
1128 | {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1, 0, 0 }, | |
1129 | {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1, 0, 0 }, | |
1130 | {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33, 0, 0 }, | |
1131 | {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33, 0, 0 }, | |
6f14957b MR |
1132 | /* mfc2 is at the bottom of the table. */ |
1133 | /* mfhc2 is at the bottom of the table. */ | |
39a7806d | 1134 | /* mfc3 is at the bottom of the table. */ |
e7ae278d RS |
1135 | {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5, 0, 0 }, |
1136 | {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1, 0, 0 }, | |
1137 | {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, 0, D32, 0 }, | |
1138 | {"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d|RD_HI, 0, EE, 0, 0 }, | |
1139 | {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1, 0, 0 }, | |
1140 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, 0, D32, 0 }, | |
1141 | {"mflo1", "d", 0x70000012, 0xffff07ff, WR_d|RD_LO, 0, EE, 0, 0 }, | |
1142 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, 0, SMT, 0 }, | |
1143 | {"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR, 0, 0 }, | |
1144 | {"mfsa", "d", 0x00000028, 0xffff07ff, WR_d, 0, EE, 0, 0 }, | |
1145 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1146 | {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1147 | {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1148 | {"min.s", "D,S,T", 0x46000029, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE, 0, 0 }, | |
1149 | {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1, 0, SF }, | |
1150 | {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1, 0, 0 }, | |
1151 | {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
1152 | {"mov.ps", "D,S", 0x45600006, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E, 0, 0 }, | |
1153 | {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32, 0, 0 }, | |
1154 | {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32, 0, 0 }, | |
1155 | {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1156 | {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1157 | {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
1158 | {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33, 0, 0 }, | |
1159 | {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|EE, 0, 0 }, | |
1160 | {"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A, 0, 0 }, | |
1161 | {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1, 0, 0 }, | |
1162 | {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32, 0, 0 }, | |
1163 | {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, SB1, MX, 0 }, | |
1164 | {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, SB1, MX, 0 }, | |
1165 | {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32, 0, 0 }, | |
1166 | {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33, 0, 0 }, | |
1167 | {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32, 0, 0 }, | |
1168 | {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32, 0, 0 }, | |
1169 | {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1170 | {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1171 | {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
1172 | {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33, 0, 0 }, | |
1173 | {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|EE, 0, 0 }, | |
1174 | {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1, 0, 0 }, | |
1175 | {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32, 0, 0 }, | |
1176 | {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, SB1, MX, 0 }, | |
1177 | {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, SB1, MX, 0 }, | |
1178 | {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32, 0, 0 }, | |
1179 | {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33, 0, 0 }, | |
1180 | {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1181 | {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1182 | {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1183 | {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
252b5132 | 1184 | /* move is at the top of the table. */ |
e7ae278d RS |
1185 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1186 | {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, | |
1187 | {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 }, | |
1188 | {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, | |
1189 | {"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, | |
1190 | {"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, | |
1191 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33, 0, 0 }, | |
1192 | {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1193 | {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, | |
1194 | {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33, 0, 0 }, | |
1195 | {"msub.s", "D,S,T", 0x46000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
1196 | {"msub.s", "D,S,T", 0x72000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F, 0, 0 }, | |
1197 | {"msub.s", "D,S,T", 0x4600001d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE, 0, 0 }, | |
1198 | {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 }, | |
1199 | {"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1d2db237 | 1200 | {"msub.ps", "D,S,T", 0x72c00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, |
e7ae278d RS |
1201 | {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1, 0, 0 }, |
1202 | {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1203 | {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1204 | {"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE, 0, 0 }, | |
1205 | {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1, 0, 0 }, | |
1206 | {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1207 | {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1208 | {"mtbpc", "t", 0x4080c000, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE, 0, 0 }, | |
1209 | {"mtdab", "t", 0x4080c004, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE, 0, 0 }, | |
1210 | {"mtdabm", "t", 0x4080c005, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE, 0, 0 }, | |
1211 | {"mtdvb", "t", 0x4080c006, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE, 0, 0 }, | |
1212 | {"mtdvbm", "t", 0x4080c007, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE, 0, 0 }, | |
1213 | {"mtiab", "t", 0x4080c002, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE, 0, 0 }, | |
1214 | {"mtiabm", "t", 0x4080c003, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE, 0, 0 }, | |
1215 | {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE, 0, 0 }, | |
1216 | {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE, 0, 0 }, | |
1217 | {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1, 0, 0 }, | |
1218 | {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32, 0, 0 }, | |
1219 | {"mtgc0", "t,G", 0x40600200, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, | |
1220 | {"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, | |
1221 | {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1, 0, 0 }, | |
1222 | {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1, 0, 0 }, | |
1223 | {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33, 0, 0 }, | |
1224 | {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33, 0, 0 }, | |
6f14957b MR |
1225 | /* mtc2 is at the bottom of the table. */ |
1226 | /* mthc2 is at the bottom of the table. */ | |
39a7806d | 1227 | /* mtc3 is at the bottom of the table. */ |
e7ae278d RS |
1228 | {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5, 0, 0 }, |
1229 | {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1, 0, 0 }, | |
1230 | {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, 0, D32, 0 }, | |
1231 | {"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s|WR_HI, 0, EE, 0, 0 }, | |
1232 | {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1, 0, 0 }, | |
1233 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, 0, D32, 0 }, | |
1234 | {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s|WR_LO, 0, EE, 0, 0 }, | |
1235 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, 0, SMT, 0 }, | |
1236 | {"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR, 0, 0 }, | |
1237 | {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCT, 0, 0 }, | |
1238 | {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCT, 0, 0 }, | |
1239 | {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCT, 0, 0 }, | |
1240 | {"mtp0", "s", 0x70000009, 0xfc1fffff, RD_s, 0, IOCT, 0, 0 }, | |
1241 | {"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_s, 0, IOCT, 0, 0 }, | |
1242 | {"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_s, 0, IOCT, 0, 0 }, | |
1243 | {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_s, 0, EE, 0, 0 }, | |
1244 | {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_s, 0, EE, 0, 0 }, | |
1245 | {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_s, 0, EE, 0, 0 }, | |
1246 | {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32, 0 }, | |
1247 | {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32, 0 }, | |
1248 | {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, 0, MT32, 0 }, | |
1249 | {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, 0, MT32, 0 }, | |
1250 | {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1251 | {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, 0, MT32, 0 }, | |
1252 | {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, 0, MT32, 0 }, | |
1253 | {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, 0, MT32, 0 }, | |
1254 | {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, 0, MT32, 0 }, | |
1255 | {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, 0, MT32, 0 }, | |
1256 | {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, 0, MT32, 0 }, | |
1257 | {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1258 | {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, 0, MT32, 0 }, | |
1259 | {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, 0, MT32, 0 }, | |
1260 | {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, 0, MT32, 0 }, | |
1261 | {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, 0, MT32, 0 }, | |
1262 | {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, 0, MT32, 0 }, | |
1263 | {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF }, | |
1264 | {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1, 0, 0 }, | |
1265 | {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1266 | {"mul.ob", "D,S,Q", 0x48000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1267 | {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F, 0, 0 }, |
1268 | {"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E, 0, 0 }, | |
1269 | {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
1270 | {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55, 0, 0}, | |
1271 | {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54, 0, 0 }, | |
1272 | {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 }, | |
1273 | {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1274 | {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
41989114 | 1275 | {"mula.ob", "S,Q", 0x48000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, N54, 0, 0 }, |
e7ae278d RS |
1276 | {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, |
1277 | {"mula.s", "S,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE, 0, 0 }, | |
1278 | {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1279 | {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1280 | {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
41989114 | 1281 | {"mull.ob", "S,Q", 0x48000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, N54, 0, 0 }, |
e7ae278d RS |
1282 | {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, |
1283 | {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, 0 }, | |
1284 | {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1285 | {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, 0 }, | |
1286 | {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1287 | {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, M3D, 0 }, | |
1288 | {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1289 | {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1290 | {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1291 | {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1292 | {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
41989114 | 1293 | {"muls.ob", "S,Q", 0x48000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, N54, 0, 0 }, |
e7ae278d RS |
1294 | {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, |
1295 | {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
41989114 | 1296 | {"mulsl.ob", "S,Q", 0x48000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, N54, 0, 0 }, |
e7ae278d RS |
1297 | {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, |
1298 | {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1, 0, 0 }, | |
1299 | {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1300 | {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1, 0, 0 }, | |
1301 | {"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1302 | {"mult1", "d,s,t", 0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE, 0, 0 }, | |
1303 | {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, 0, SMT, 0 }, | |
1304 | {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1, 0, 0 }, | |
1305 | {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1306 | {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1, 0, 0 }, | |
1307 | {"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1308 | {"multu1", "d,s,t", 0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE, 0, 0 }, | |
1309 | {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5, 0, 0 }, | |
1310 | {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1, 0, 0 }, /* sub 0 */ | |
1311 | {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1, 0, 0 }, /* subu 0 */ | |
1312 | {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1, 0, SF }, | |
1313 | {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1, 0, 0 }, | |
1314 | {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
1315 | {"neg.ps", "D,V", 0x45600007, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E, 0, 0 }, | |
1316 | {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33, 0, 0 }, | |
1317 | {"nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1318 | {"nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, | |
1319 | {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33, 0, 0 }, | |
1320 | {"nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
1321 | {"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F, 0, 0 }, | |
1322 | {"nmadd.ps", "D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 }, | |
1323 | {"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1d2db237 | 1324 | {"nmadd.ps", "D,S,T", 0x72c0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, |
e7ae278d RS |
1325 | {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33, 0, 0 }, |
1326 | {"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1327 | {"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, | |
1328 | {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33, 0, 0 }, | |
1329 | {"nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
1330 | {"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F, 0, 0 }, | |
1331 | {"nmsub.ps", "D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 }, | |
1332 | {"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1d2db237 | 1333 | {"nmsub.ps", "D,S,T", 0x72c0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 }, |
252b5132 | 1334 | /* nop is at the start of the table. */ |
e7ae278d RS |
1335 | {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, |
1336 | {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1337 | {"nor", "D,S,T", 0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1338 | {"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1339 | {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1340 | {"nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d | 1341 | {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
6a819047 | 1342 | {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s, 0, I1, 0, 0 },/*nor d,s,0*/ |
e7ae278d RS |
1343 | {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, |
1344 | {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1345 | {"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1346 | {"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1347 | {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1348 | {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1349 | {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1350 | {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1, 0, 0 }, | |
1351 | {"pabsdiff.ob", "X,Y,Q", 0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, 0, 0 }, | |
1352 | {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, 0, 0 }, | |
1353 | {"pause", "", 0x00000140, 0xffffffff, TRAP, 0, I33, 0, 0 }, | |
1354 | {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, 0, 0 }, | |
1355 | {"pabsh", "d,t", 0x70000168, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1356 | {"pabsw", "d,t", 0x70000068, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1357 | {"paddsw", "d,s,t", 0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1358 | {"paddub", "d,s,t", 0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1359 | {"padduh", "d,s,t", 0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1360 | {"padduw", "d,s,t", 0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1361 | {"padsbh", "d,s,t", 0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1362 | {"pand", "d,s,t", 0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1363 | {"pceqb", "d,s,t", 0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1364 | {"pceqh", "d,s,t", 0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1365 | {"pceqw", "d,s,t", 0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1366 | {"pcgtb", "d,s,t", 0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1367 | {"pcgth", "d,s,t", 0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1368 | {"pcgtw", "d,s,t", 0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1369 | {"pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1370 | {"pcpyld", "d,s,t", 0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1371 | {"pcpyud", "d,s,t", 0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1372 | {"pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1373 | {"pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1374 | {"pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1375 | {"pexch", "d,t", 0x700006a9, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1376 | {"pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1377 | {"pexeh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1378 | {"pexew", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1379 | {"pext5", "d,t", 0x70000788, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1380 | {"pextlb", "d,s,t", 0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1381 | {"pextlh", "d,s,t", 0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1382 | {"pextlw", "d,s,t", 0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1383 | {"pextub", "d,s,t", 0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1384 | {"pextuh", "d,s,t", 0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1385 | {"pextuw", "d,s,t", 0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1386 | {"phmadh", "d,s,t", 0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1387 | {"phmsbh", "d,s,t", 0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1388 | {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1389 | {"pickf.ob", "D,S,Q", 0x48000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1390 | {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1391 | {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1392 | {"pickt.ob", "D,S,Q", 0x48000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1393 | {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1394 | {"pinteh", "d,s,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1395 | {"pinth", "d,s,t", 0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1396 | {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33, 0, 0 }, | |
1397 | {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33, 0, 0 }, | |
1398 | {"plzcw", "d,s", 0x70000004, 0xfc1f07ff, WR_d|RD_s, 0, MMI, 0, 0 }, | |
1399 | {"pmaddh", "d,s,t", 0x70000409, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1400 | {"pmadduw", "d,s,t", 0x70000029, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI, 0, 0 }, | |
1401 | {"pmaddw", "d,s,t", 0x70000009, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI, 0, 0 }, | |
1402 | {"pmaxh", "d,s,t", 0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1403 | {"pmaxw", "d,s,t", 0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1404 | {"pmfhi", "d", 0x70000209, 0xffff07ff, WR_d|RD_HI, 0, MMI, 0, 0 }, | |
1405 | {"pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_d|RD_HILO, 0, MMI, 0, 0 }, | |
1406 | {"pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_d|RD_HILO, 0, MMI, 0, 0 }, | |
1407 | {"pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_d|RD_HILO, 0, MMI, 0, 0 }, | |
1408 | {"pmfhl.slw", "d", 0x700000b0, 0xffff07ff, WR_d|RD_HILO, 0, MMI, 0, 0 }, | |
1409 | {"pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_d|RD_HILO, 0, MMI, 0, 0 }, | |
1410 | {"pmflo", "d", 0x70000249, 0xffff07ff, WR_d|RD_LO, 0, MMI, 0, 0 }, | |
1411 | {"pminh", "d,s,t", 0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1412 | {"pminw", "d,s,t", 0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1413 | {"pmsubh", "d,s,t", 0x70000509, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI, 0, 0 }, | |
1414 | {"pmsubw", "d,s,t", 0x70000109, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI, 0, 0 }, | |
1415 | {"pmthi", "s", 0x70000229, 0xfc1fffff, RD_s|WR_HI, 0, MMI, 0, 0 }, | |
1416 | {"pmthl.lw", "s", 0x70000031, 0xfc1fffff, RD_s|MOD_HILO, 0, MMI, 0, 0 }, | |
1417 | {"pmtlo", "s", 0x70000269, 0xfc1fffff, RD_s|WR_LO, 0, MMI, 0, 0 }, | |
1418 | {"pmulth", "d,s,t", 0x70000709, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1419 | {"pmultuw", "d,s,t", 0x70000329, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1420 | {"pmultw", "d,s,t", 0x70000309, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI, 0, 0 }, | |
1421 | {"pnor", "d,s,t", 0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1422 | {"pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_d|RD_s, 0, IOCT, 0, 0 }, | |
1423 | {"por", "d,s,t", 0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1424 | {"ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1425 | {"ppacb", "d,s,t", 0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1426 | {"ppach", "d,s,t", 0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1427 | {"ppacw", "d,s,t", 0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1428 | {"prevh", "d,t", 0x700006c9, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1429 | {"prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_d|RD_t, 0, MMI, 0, 0 }, | |
1430 | {"psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1431 | {"psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1432 | {"psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1433 | {"psubsw", "d,s,t", 0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1434 | {"psubub", "d,s,t", 0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1435 | {"psubuh", "d,s,t", 0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1436 | {"psubuw", "d,s,t", 0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1437 | {"pxor", "d,s,t", 0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
564e8ad9 | 1438 | /* pref and prefx are at the start of the table. */ |
e7ae278d RS |
1439 | {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33, 0, 0 }, |
1440 | {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33, 0, 0 }, | |
1441 | {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, 0, SMT, 0 }, | |
1442 | {"qfsrv", "d,s,t", 0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
1443 | {"qmac.00", "s,t", 0x70000412, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1444 | {"qmac.01", "s,t", 0x70000452, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1445 | {"qmac.02", "s,t", 0x70000492, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1446 | {"qmac.03", "s,t", 0x700004d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1447 | {"qmacs.00", "s,t", 0x70000012, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1448 | {"qmacs.01", "s,t", 0x70000052, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1449 | {"qmacs.02", "s,t", 0x70000092, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1450 | {"qmacs.03", "s,t", 0x700000d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2, 0, 0 }, | |
1451 | {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, SB1, MX, 0 }, | |
41989114 | 1452 | {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, N54, 0, 0 }, |
e7ae278d RS |
1453 | {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, 0, MX, 0 }, |
1454 | {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, SB1, MX, 0 }, | |
41989114 | 1455 | {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, N54, 0, 0 }, |
e7ae278d RS |
1456 | {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, 0, MX, 0 }, |
1457 | {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, SB1, MX, 0 }, | |
41989114 | 1458 | {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, N54, 0, 0 }, |
e7ae278d RS |
1459 | {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, 0, MX, 0 }, |
1460 | {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33, 0, 0 }, | |
1461 | {"recip.ps", "D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1, 0, 0 }, | |
1462 | {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33, 0, 0 }, | |
1463 | {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, 0, M3D, 0 }, | |
1464 | {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, 0, M3D, 0 }, | |
1465 | {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, 0, M3D, 0 }, | |
1466 | {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, M3D, 0 }, | |
1467 | {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, 0, M3D, 0 }, | |
1468 | {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, 0, M3D, 0 }, | |
1469 | {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 }, | |
1470 | {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, | |
1471 | {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
1472 | {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 }, | |
1473 | {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, | |
1474 | {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
1475 | {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33, 0, 0 }, | |
1476 | {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33, 0, 0 }, | |
b015e599 | 1477 | /* rfe is moved below as it now conflicts with tlbgp */ |
e7ae278d RS |
1478 | {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX, 0 }, |
1479 | {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, SB1, MX, 0 }, | |
1480 | {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX, 0 }, | |
1481 | {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX, 0 }, | |
1482 | {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, SB1, MX, 0 }, | |
1483 | {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX, 0 }, | |
1484 | {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, | |
1485 | {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1486 | {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, | |
1487 | {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1488 | {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33, SMT, 0 }, | |
1489 | {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33, SMT, 0 }, | |
1490 | {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, | |
1491 | {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, | |
1492 | {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, | |
1493 | {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, | |
1494 | {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33, SMT, 0 }, | |
1495 | {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33, 0, 0 }, | |
1496 | {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
1497 | {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, 0, SF }, | |
1498 | {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, 0 }, | |
1499 | {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33, 0, 0 }, | |
1500 | {"rsqrt.ps", "D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1, 0, 0 }, | |
1501 | {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33, 0, 0 }, | |
1502 | {"rsqrt.s", "D,S,T", 0x46000016, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, EE, 0, 0 }, | |
1503 | {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, 0, M3D, 0 }, | |
1504 | {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, 0, M3D, 0 }, | |
1505 | {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, 0, M3D, 0 }, | |
1506 | {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, M3D, 0 }, | |
1507 | {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, 0, M3D, 0 }, | |
1508 | {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, 0, M3D, 0 }, | |
1509 | {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX, 0 }, | |
1510 | {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, SB1, MX, 0 }, | |
41989114 | 1511 | {"rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, N54, 0, 0 }, |
e7ae278d RS |
1512 | {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX, 0 }, |
1513 | {"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, | |
1514 | {"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP, 0, 0 }, | |
1515 | {"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, | |
1516 | {"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP, 0, 0 }, | |
1517 | {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1, 0, 0 }, | |
1518 | {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1519 | {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2, 0, EE }, | |
1520 | {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2, 0, EE }, | |
1521 | {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3, 0, EE }, | |
1522 | {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE }, | |
704897fb | 1523 | /* The macro has to be first to handle o32 correctly. */ |
e7ae278d RS |
1524 | {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, |
1525 | {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3, 0, 0 }, | |
1526 | {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2, 0, 0 }, | |
1527 | {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2, 0, 0 }, | |
1528 | {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2, 0, 0 }, | |
1529 | {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32, 0, 0 }, | |
1530 | {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32, 0, 0 }, | |
1531 | {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, 0, SF }, | |
1532 | {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, 0, SF }, | |
1533 | {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | |
1534 | {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | |
1535 | {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
1536 | {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
1537 | {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
1538 | {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, | |
1539 | {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, 0, SF }, | |
1540 | {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, | |
1541 | {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3, 0, 0 }, | |
1542 | {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1543 | {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3, 0, 0 }, | |
1544 | {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1545 | {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33, 0, 0 }, | |
1546 | {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33, 0, 0 }, | |
1547 | {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33, 0, 0 }, | |
1548 | {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1, 0, 0 }, | |
1549 | {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1, 0, 0 }, | |
1550 | {"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT, 0, 0 }, | |
1551 | {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 }, | |
1552 | {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1553 | {"seq", "S,T", 0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
1554 | {"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1555 | {"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, | |
1556 | {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 }, | |
1557 | {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1558 | {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1, 0, 0 }, | |
1559 | {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1560 | {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1, 0, 0 }, | |
1561 | {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1562 | {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1, 0, 0 }, | |
1563 | {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1564 | {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1, 0, 0 }, | |
1565 | {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1566 | {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
1567 | {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1568 | {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1569 | {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1570 | {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1571 | {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1572 | {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1573 | {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1574 | {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d | 1575 | {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
41989114 | 1576 | {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1577 | {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1578 | {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
1579 | {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
1580 | {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, | |
1581 | {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1582 | {"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
1583 | {"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1584 | {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 }, | |
1585 | {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1586 | {"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
1587 | {"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1588 | {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1, 0, 0 }, | |
1589 | {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1, 0, 0 }, /* sllv */ | |
1590 | {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1, 0, 0 }, | |
1591 | {"sll", "D,S,T", 0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1592 | {"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1593 | {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1594 | {"sll.ob", "D,S,Q", 0x48000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1595 | {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1596 | {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
1597 | {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1598 | {"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
1599 | {"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1600 | {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1, 0, 0 }, | |
1601 | {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1, 0, 0 }, | |
1602 | {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
1603 | {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1604 | {"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
1605 | {"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1606 | {"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT, 0, 0 }, | |
1607 | {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 }, | |
1608 | {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1609 | {"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, IOCT, 0, 0 }, | |
1610 | {"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, 0, MMI, 0, 0 }, | |
1611 | {"sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, | |
1612 | {"sqc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, EE, 0, 0 }, | |
1613 | {"sqc2", "E,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, | |
1614 | {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2, 0, SF }, | |
1615 | {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, 0 }, | |
1616 | {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1, 0, 0 }, | |
1617 | {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1, 0, 0 }, | |
1618 | {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1, 0, 0 }, /* srav */ | |
1619 | {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1, 0, 0 }, | |
1620 | {"sra", "D,S,T", 0x45c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1621 | {"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1622 | {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
1623 | {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1, 0, 0 }, | |
1624 | {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1, 0, 0 }, /* srlv */ | |
1625 | {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1, 0, 0 }, | |
1626 | {"srl", "D,S,T", 0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1627 | {"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1628 | {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1629 | {"srl.ob", "D,S,Q", 0x48000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d | 1630 | {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
4372b673 | 1631 | /* ssnop is at the start of the table. */ |
e7ae278d RS |
1632 | {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 }, |
1633 | {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
1634 | {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1635 | {"sub", "D,S,T", 0x45c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
1636 | {"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
1637 | {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF }, | |
1638 | {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1, 0, 0 }, | |
1639 | {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1640 | {"sub.ob", "D,S,Q", 0x4800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1641 | {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F, 0, 0 }, |
1642 | {"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E, 0, 0 }, | |
1643 | {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, | |
1644 | {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
1645 | {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, | |
1646 | {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
1647 | {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, | |
1648 | {"suba.s", "S,T", 0x46000019, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE, 0, 0 }, | |
1649 | {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
1650 | {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1651 | {"subu", "D,S,T", 0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E, 0, 0 }, | |
1652 | {"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
1653 | {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 }, | |
1654 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55, 0, 0}, | |
1655 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1, 0, 0 }, | |
1656 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1657 | {"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR, 0, 0 }, | |
1658 | {"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR, 0, 0 }, | |
1659 | {"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR, 0, 0 }, | |
1660 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
1661 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
1662 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1, 0, 0 }, | |
1663 | {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1, 0, 0 }, | |
1664 | {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1665 | {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1666 | {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1, 0, 0 }, /* swc1 */ | |
1667 | {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1668 | {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1669 | {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1670 | {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1671 | {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1672 | {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1, 0, 0 }, | |
1673 | {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1674 | {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2, 0, 0 }, /* same */ | |
1675 | {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as swl */ | |
1676 | {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1, 0, 0 }, | |
1677 | {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1678 | {"invalidate", "t,o(b)", 0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2, 0, 0 }, /* same */ | |
1679 | {"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as swr */ | |
1680 | {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33, 0, 0 }, | |
1681 | {"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, | |
1682 | {"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, | |
1683 | {"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, | |
1684 | {"syncws", "", 0x0000014f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, | |
1685 | {"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1686 | {"sync_mb", "", 0x0000040f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1687 | {"sync_release", "", 0x0000048f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1688 | {"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1689 | {"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1690 | {"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1, 0, 0 }, | |
1691 | {"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32, 0, 0 }, | |
1692 | {"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2, 0, 0 }, | |
1693 | {"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2, 0, 0 }, | |
1694 | {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33, 0, 0 }, | |
1695 | {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, | |
1696 | {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, | |
1697 | {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, | |
1698 | {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1699 | {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1700 | {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, /* teqi */ | |
1701 | {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, | |
1702 | {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, | |
1703 | {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1704 | {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1705 | {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, /* tgei */ | |
1706 | {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, | |
1707 | {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, | |
1708 | {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1709 | {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1710 | {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, /* tgeiu */ | |
1711 | {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, | |
1712 | {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, | |
1713 | {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, | |
1714 | {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1715 | {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1716 | {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1717 | {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1718 | {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1719 | {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1720 | {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1721 | {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1722 | {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1723 | {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1724 | {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, | |
1725 | {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1726 | {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1727 | {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, /* tlti */ | |
1728 | {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, | |
1729 | {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, | |
1730 | {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1731 | {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1732 | {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, /* tltiu */ | |
1733 | {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, | |
1734 | {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, | |
1735 | {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1736 | {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2, 0, 0 }, | |
1737 | {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2, 0, 0 }, /* tnei */ | |
1738 | {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, | |
1739 | {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33, 0, 0 }, | |
1740 | {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
1741 | {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, 0, SF }, | |
1742 | {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, 0, SF }, | |
1743 | {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1, 0, SF }, | |
1744 | {"trunc.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, EE, 0, 0 }, | |
1745 | {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE }, | |
1746 | {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE }, | |
1747 | {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE }, | |
1748 | {"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1749 | {"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1750 | {"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1751 | {"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1752 | {"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1753 | {"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1754 | {"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1755 | {"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT, 0, 0 }, | |
1756 | {"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT, 0, 0 }, | |
1757 | {"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT, 0, 0 }, | |
1758 | {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, SB1, MX, 0 }, | |
41989114 | 1759 | {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, N54, 0, 0 }, |
e7ae278d RS |
1760 | {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, 0, MX, 0 }, |
1761 | {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX, 0 }, | |
41989114 | 1762 | {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, N54, 0, 0 }, |
e7ae278d RS |
1763 | {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX, 0 }, |
1764 | {"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32, 0, 0 }, | |
1765 | {"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55, 0, 0 }, | |
1766 | {"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1, 0, 0 }, | |
1767 | {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33, 0, 0 }, | |
1768 | {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33, 0, 0 }, | |
1769 | {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 }, | |
1770 | {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1771 | {"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
1772 | {"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1773 | {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 }, | |
41989114 | 1774 | {"xor.ob", "D,S,Q", 0x4800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 }, |
e7ae278d RS |
1775 | {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 }, |
1776 | {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1, 0, 0 }, | |
1777 | {"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, 0, MT32, 0 }, | |
1778 | {"yield", "d,s", 0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s, 0, 0, MT32, 0 }, | |
1779 | {"zcb", "(b)", 0x7000071f, 0xfc1fffff, SM|RD_b, 0, IOCT2, 0, 0 }, | |
1780 | {"zcbt", "(b)", 0x7000075f, 0xfc1fffff, SM|RD_b, 0, IOCT2, 0, 0 }, | |
deec1734 | 1781 | |
9bcd4f99 | 1782 | /* User Defined Instruction. */ |
e7ae278d RS |
1783 | {"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, |
1784 | {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1785 | {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1786 | {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1787 | {"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1788 | {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1789 | {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1790 | {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1791 | {"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1792 | {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1793 | {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1794 | {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1795 | {"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1796 | {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1797 | {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1798 | {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1799 | {"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1800 | {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1801 | {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1802 | {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1803 | {"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1804 | {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1805 | {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1806 | {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1807 | {"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1808 | {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1809 | {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1810 | {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1811 | {"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1812 | {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1813 | {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1814 | {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1815 | {"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1816 | {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1817 | {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1818 | {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1819 | {"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1820 | {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1821 | {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1822 | {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1823 | {"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1824 | {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1825 | {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1826 | {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1827 | {"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1828 | {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1829 | {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1830 | {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1831 | {"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1832 | {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1833 | {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1834 | {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1835 | {"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1836 | {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1837 | {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1838 | {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1839 | {"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1840 | {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1841 | {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1842 | {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1843 | {"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1844 | {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1845 | {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
1846 | {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33, 0, 0 }, | |
9bcd4f99 | 1847 | |
6f14957b MR |
1848 | /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format |
1849 | instructions so they are here for the latters to take precedence. */ | |
e7ae278d RS |
1850 | {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
1851 | {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
1852 | {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
1853 | {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
1854 | {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
1855 | {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
1856 | {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
1857 | {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
1858 | {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
1859 | {"cfc2.i", "t,G", 0x48400001, 0xffe007ff, LCD|WR_t|RD_C2, 0, EE, 0, 0 }, | |
1860 | {"cfc2.ni", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, EE, 0, 0 }, | |
1861 | {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
1862 | {"ctc2.i", "t,G", 0x48c00001, 0xffe007ff, COD|RD_t|WR_CC, 0, EE, 0, 0 }, | |
1863 | {"ctc2.ni", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, EE, 0, 0 }, | |
1864 | {"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT, 0, 0 }, | |
1865 | {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
1866 | {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, 0, IOCT|IOCTP|IOCT2 }, | |
1867 | {"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT, 0, 0 }, | |
1868 | {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
1869 | {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64, 0, IOCT|IOCTP|IOCT2 }, | |
1870 | {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1871 | {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
1872 | {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
1873 | {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
1874 | {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
1875 | {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1876 | {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
1877 | {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
1878 | {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
1879 | {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
1880 | {"qmfc2", "t,G", 0x48200000, 0xffe007ff, WR_t|RD_C2, 0, EE, 0, 0 }, | |
1881 | {"qmfc2.i", "t,G", 0x48200001, 0xffe007ff, WR_t|RD_C2, 0, EE, 0, 0 }, | |
1882 | {"qmfc2.ni", "t,G", 0x48200000, 0xffe007ff, WR_t|RD_C2, 0, EE, 0, 0 }, | |
1883 | {"qmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_t|WR_C2, 0, EE, 0, 0 }, | |
1884 | {"qmtc2.i", "t,G", 0x48a00001, 0xffe007ff, RD_t|WR_C2, 0, EE, 0, 0 }, | |
1885 | {"qmtc2.ni", "t,G", 0x48a00000, 0xffe007ff, RD_t|WR_C2, 0, EE, 0, 0 }, | |
39a7806d TS |
1886 | /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X |
1887 | instructions, so they are here for the latters to take precedence. */ | |
e7ae278d RS |
1888 | {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
1889 | {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE }, | |
1890 | {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1891 | {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE }, | |
1892 | {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1893 | {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1894 | {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
1895 | {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
1896 | {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1897 | {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32, 0, IOCT|IOCTP|IOCT2|EE }, | |
1898 | {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
1899 | {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32, 0, IOCT|IOCTP|IOCT2|EE }, | |
39a7806d | 1900 | |
252b5132 RH |
1901 | /* Conflicts with the 4650's "mul" instruction. Nobody's using the |
1902 | 4010 any more, so move this insn out of the way. If the object | |
1903 | format gave us more info, we could do this right. */ | |
e7ae278d | 1904 | {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1, 0, 0 }, |
fd25c5a9 | 1905 | /* MIPS DSP ASE */ |
e7ae278d RS |
1906 | {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, |
1907 | {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
1908 | {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
1909 | {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
1910 | {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1911 | {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1912 | {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1913 | {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1914 | {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1915 | {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1916 | {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1917 | {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1918 | {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1919 | {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1920 | {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1921 | {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1922 | {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1923 | {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
1924 | {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 }, | |
1925 | {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 }, | |
1926 | {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, 0, D32, 0 }, | |
1927 | {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1928 | {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1929 | {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1930 | {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1931 | {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1932 | {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1933 | {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
1934 | {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
1935 | {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, 0, D32, 0 }, | |
1936 | {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1937 | {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1938 | {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, 0, D32, 0 }, | |
1939 | {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1940 | {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1941 | {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1942 | {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, 0, D32, 0 }, | |
1943 | {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1944 | {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, 0, D32, 0 }, | |
1945 | {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, 0, D64, 0 }, | |
1946 | {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, 0, D32, 0 }, | |
1947 | {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, 0, D64, 0 }, | |
1948 | {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, 0, D64, 0 }, | |
1949 | {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1950 | {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1951 | {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1952 | {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1953 | {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1954 | {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1955 | {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1956 | {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1957 | {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1958 | {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1959 | {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1960 | {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1961 | {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1962 | {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1963 | {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D64, 0 }, | |
1964 | {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, 0, D64, 0 }, | |
1965 | {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, 0, D64, 0 }, | |
1966 | {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1967 | {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1968 | {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1969 | {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1970 | {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, 0, D64, 0 }, | |
1971 | {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1972 | {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1973 | {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1974 | {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1975 | {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1976 | {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1977 | {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1978 | {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1979 | {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1980 | {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1981 | {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1982 | {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1983 | {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1984 | {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
1985 | {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1986 | {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
1987 | {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, 0, D64, 0 }, | |
1988 | {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, 0, D64, 0 }, | |
1989 | {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, 0, D32, 0 }, | |
1990 | {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, 0, D32, 0 }, | |
1991 | {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, 0, D32, 0 }, | |
1992 | {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D32, 0 }, | |
1993 | {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, 0, D32, 0 }, | |
1994 | {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, 0, D32, 0 }, | |
1995 | {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, 0, D32, 0 }, | |
1996 | {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D32, 0 }, | |
1997 | {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D32, 0 }, | |
1998 | {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D32, 0 }, | |
1999 | {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, 0, D32, 0 }, | |
2000 | {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, 0, D32, 0 }, | |
2001 | {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32, 0 }, | |
432233b3 | 2002 | /* lbux, ldx, lhx and lwx are the basic instruction section. */ |
e7ae278d RS |
2003 | {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, |
2004 | {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
2005 | {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2006 | {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2007 | {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2008 | {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2009 | {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2010 | {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2011 | {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
2012 | {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
2013 | {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2014 | {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2015 | {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2016 | {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2017 | {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2018 | {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, 0, D32, 0 }, | |
2019 | {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D64, 0 }, | |
2020 | {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D64, 0 }, | |
2021 | {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32, 0 }, | |
2022 | {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32, 0 }, | |
2023 | {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32, 0 }, | |
2024 | {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32, 0 }, | |
2025 | {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D64, 0 }, | |
2026 | {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D64, 0 }, | |
2027 | {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32, 0 }, | |
2028 | {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D64, 0 }, | |
2029 | {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2030 | {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 }, | |
2031 | {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D64, 0 }, | |
2032 | {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2033 | {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2034 | {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2035 | {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2036 | {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2037 | {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2038 | {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2039 | {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2040 | {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2041 | {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2042 | {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2043 | {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2044 | {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2045 | {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2046 | {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2047 | {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2048 | {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2049 | {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2050 | {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2051 | {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2052 | {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2053 | {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2054 | {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2055 | {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2056 | {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2057 | {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2058 | {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2059 | {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2060 | {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2061 | {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2062 | {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2063 | {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2064 | {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2065 | {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2066 | {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2067 | {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2068 | {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2069 | {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2070 | {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2071 | {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2072 | {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, 0, D64, 0 }, | |
2073 | {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, 0, D32, 0 }, | |
2074 | {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, 0, D32, 0 }, | |
2075 | {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, 0, D32, 0 }, | |
2076 | {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, 0, D64, 0 }, | |
2077 | {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, 0, D32, 0 }, | |
2078 | {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, 0, D64, 0 }, | |
2079 | {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, 0, D32, 0 }, | |
2080 | {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, 0, D64, 0 }, | |
2081 | {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2082 | {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2083 | {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2084 | {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2085 | {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2086 | {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, 0, D32, 0 }, | |
2087 | {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, 0, D32, 0 }, | |
2088 | {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2089 | {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2090 | {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2091 | {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2092 | {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2093 | {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2094 | {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2095 | {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2096 | {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2097 | {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2098 | {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2099 | {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2100 | {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2101 | {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2102 | {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2103 | {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2104 | {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2105 | {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2106 | {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2107 | {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2108 | {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2109 | {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2110 | {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2111 | {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2112 | {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2113 | {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2114 | {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2115 | {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2116 | {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2117 | {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2118 | {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2119 | {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2120 | {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, 0, D64, 0 }, | |
2121 | {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, 0, D32, 0 }, | |
2122 | {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2123 | {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2124 | {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2125 | {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2126 | {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2127 | {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2128 | {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2129 | {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2130 | {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2131 | {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2132 | {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2133 | {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D64, 0 }, | |
2134 | {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32, 0 }, | |
2135 | {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, 0, D32, 0 }, | |
2136 | {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, 0, D32, 0 }, | |
8b082fb1 | 2137 | /* MIPS DSP ASE Rev2 */ |
e7ae278d RS |
2138 | {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, 0, D33, 0 }, |
2139 | {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2140 | {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2141 | {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2142 | {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2143 | {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33, 0 }, | |
2144 | {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33, 0 }, | |
2145 | {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, 0, D33, 0 }, | |
2146 | {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2147 | {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2148 | {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2149 | {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2150 | {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2151 | {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33, 0 }, | |
2152 | {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33, 0 }, | |
2153 | {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33, 0 }, | |
2154 | {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33, 0 }, | |
2155 | {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33, 0 }, | |
2156 | {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2157 | {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2158 | {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33, 0 }, | |
2159 | {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33, 0 }, | |
2160 | {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33, 0 }, | |
2161 | {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, 0, D33, 0 }, | |
2162 | {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, 0, D33, 0 }, | |
2163 | {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2164 | {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2165 | {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, 0, D33, 0 }, | |
2166 | {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2167 | {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2168 | {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2169 | {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2170 | {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2171 | {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2172 | {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2173 | {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2174 | {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2175 | {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2176 | {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2177 | {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2178 | {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33, 0 }, | |
2179 | {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2180 | {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2181 | {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2182 | {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2183 | {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
2184 | {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D33, 0 }, | |
61cc0267 | 2185 | /* Move bc0* after mftr and mttr to avoid opcode collision. */ |
e7ae278d RS |
2186 | {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
2187 | {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
2188 | {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2189 | {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
350cc38d | 2190 | /* ST Microelectronics Loongson-2E and -2F. */ |
e7ae278d RS |
2191 | {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, |
2192 | {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2193 | {"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2194 | {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2195 | {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2196 | {"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2197 | {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2198 | {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2199 | {"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2200 | {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2201 | {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2202 | {"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2203 | {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2204 | {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2205 | {"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2206 | {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2207 | {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2208 | {"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2209 | {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2210 | {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2211 | {"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2212 | {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2213 | {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2214 | {"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2215 | {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2216 | {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2217 | {"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2218 | {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2219 | {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2220 | {"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2221 | {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2222 | {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2223 | {"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2224 | {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E, 0, 0 }, | |
2225 | {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F, 0, 0 }, | |
2226 | {"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A, 0, 0 }, | |
2227 | {"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2228 | {"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2229 | {"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2230 | {"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2231 | {"packushb", "D,S,T", 0x47600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2232 | {"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2233 | {"paddb", "D,S,T", 0x47c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2234 | {"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2235 | {"paddb", "d,s,t", 0x70000208, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2236 | {"paddh", "D,S,T", 0x47400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2237 | {"paddh", "d,s,t", 0x70000108, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2238 | {"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2239 | {"paddw", "D,S,T", 0x47600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2240 | {"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2241 | {"paddw", "d,s,t", 0x70000008, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2242 | {"paddd", "D,S,T", 0x47e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2243 | {"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2244 | {"paddsb", "D,S,T", 0x47800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2245 | {"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2246 | {"paddsb", "d,s,t", 0x70000608, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2247 | {"paddsh", "D,S,T", 0x47000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2248 | {"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2249 | {"paddsh", "d,s,t", 0x70000508, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2250 | {"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2251 | {"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2252 | {"paddush", "D,S,T", 0x47200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2253 | {"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2254 | {"pandn", "D,S,T", 0x47e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2255 | {"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2256 | {"pavgb", "D,S,T", 0x46600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2257 | {"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2258 | {"pavgh", "D,S,T", 0x46400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2259 | {"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2260 | {"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2261 | {"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2262 | {"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2263 | {"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2264 | {"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2265 | {"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2266 | {"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2267 | {"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2268 | {"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2269 | {"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2270 | {"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2271 | {"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2272 | {"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2273 | {"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2274 | {"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2275 | {"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2276 | {"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2277 | {"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2278 | {"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2279 | {"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2280 | {"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2281 | {"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2282 | {"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2283 | {"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2284 | {"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2285 | {"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2286 | {"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2287 | {"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2288 | {"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2289 | {"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2290 | {"pminub", "D,S,T", 0x46e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2291 | {"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2292 | {"pmovmskb", "D,S", 0x46a00005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2293 | {"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2294 | {"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2295 | {"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2296 | {"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2297 | {"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2298 | {"pmullh", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2299 | {"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2300 | {"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2301 | {"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2302 | {"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2303 | {"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2304 | {"biadd", "D,S", 0x46800005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2305 | {"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2306 | {"pshufh", "D,S,T", 0x47000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2307 | {"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2308 | {"psllh", "D,S,T", 0x46600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2309 | {"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2310 | {"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_d|RD_t, 0, MMI, 0, 0 }, | |
2311 | {"psllw", "D,S,T", 0x46400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2312 | {"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2313 | {"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_d|RD_t, 0, MMI, 0, 0 }, | |
2314 | {"psrah", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2315 | {"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2316 | {"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_d|RD_t, 0, MMI, 0, 0 }, | |
2317 | {"psraw", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2318 | {"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2319 | {"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_d|RD_t, 0, MMI, 0, 0 }, | |
2320 | {"psrlh", "D,S,T", 0x46600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2321 | {"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2322 | {"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_d|RD_t, 0, MMI, 0, 0 }, | |
2323 | {"psrlw", "D,S,T", 0x46400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2324 | {"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2325 | {"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_d|RD_t, 0, MMI, 0, 0 }, | |
2326 | {"psubb", "D,S,T", 0x47c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2327 | {"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2328 | {"psubb", "d,s,t", 0x70000248, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2329 | {"psubh", "D,S,T", 0x47400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2330 | {"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2331 | {"psubh", "d,s,t", 0x70000148, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2332 | {"psubw", "D,S,T", 0x47600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2333 | {"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2334 | {"psubw", "d,s,t", 0x70000048, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2335 | {"psubd", "D,S,T", 0x47e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2336 | {"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2337 | {"psubsb", "D,S,T", 0x47800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2338 | {"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2339 | {"psubsb", "d,s,t", 0x70000648, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2340 | {"psubsh", "D,S,T", 0x47000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2341 | {"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2342 | {"psubsh", "d,s,t", 0x70000548, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI, 0, 0 }, | |
2343 | {"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2344 | {"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2345 | {"psubush", "D,S,T", 0x47200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2346 | {"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2347 | {"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2348 | {"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2349 | {"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2350 | {"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2351 | {"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2352 | {"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2353 | {"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2354 | {"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2355 | {"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2356 | {"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2357 | {"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 }, | |
2358 | {"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2359 | {"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
2360 | {"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
7f3c4072 | 2361 | /* MIPS Enhanced VA Scheme */ |
e7ae278d RS |
2362 | {"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, |
2363 | {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2364 | {"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, | |
2365 | {"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2366 | {"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, | |
2367 | {"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2368 | {"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, | |
2369 | {"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2370 | {"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, | |
2371 | {"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2372 | {"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, | |
2373 | {"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2374 | {"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, | |
2375 | {"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2376 | {"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA, 0 }, | |
2377 | {"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2378 | {"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA, 0 }, | |
2379 | {"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2380 | {"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, SM|RD_t|WR_t|RD_b, 0, 0, EVA, 0 }, | |
2381 | {"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2382 | {"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA, 0 }, | |
2383 | {"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2384 | {"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA, 0 }, | |
2385 | {"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2386 | {"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA, 0 }, | |
2387 | {"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2388 | {"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA, 0 }, | |
2389 | {"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
2390 | {"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_b, 0, 0, EVA, 0 }, | |
2391 | {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, | |
2392 | {"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_b, 0, 0, EVA, 0 }, | |
2393 | {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, | |
350cc38d MS |
2394 | /* No hazard protection on coprocessor instructions--they shouldn't |
2395 | change the state of the processor and if they do it's up to the | |
2396 | user to put in nops as necessary. These are at the end so that the | |
2397 | disassembler recognizes more specific versions first. */ | |
e7ae278d RS |
2398 | {"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
2399 | {"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1, 0, 0 }, | |
2400 | {"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2401 | {"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2402 | {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2403 | {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
2404 | {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2405 | {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
b015e599 | 2406 | /* RFE conflicts with the new Virt spec instruction tlbgp. */ |
e7ae278d | 2407 | {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 }, |
252b5132 RH |
2408 | }; |
2409 | ||
2410 | #define MIPS_NUM_OPCODES \ | |
2411 | ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) | |
2412 | const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; | |
2413 | ||
564e8ad9 | 2414 | /* const removed from the following to allow for dynamic extensions to the |
252b5132 RH |
2415 | * built-in instruction set. */ |
2416 | struct mips_opcode *mips_opcodes = | |
2417 | (struct mips_opcode *) mips_builtin_opcodes; | |
2418 | int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; | |
2419 | #undef MIPS_NUM_OPCODES |