Commit | Line | Data |
---|---|---|
252b5132 RH |
1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. | |
3 | Contributed by Ralph Campbell and OSF | |
4 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
5 | ||
6 | This file is part of GDB, GAS, and the GNU binutils. | |
7 | ||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
9 | them and/or modify them under the terms of the GNU General Public | |
10 | License as published by the Free Software Foundation; either version | |
11 | 1, or (at your option) any later version. | |
12 | ||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
16 | the GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this file; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include "ansidecl.h" | |
24 | #include "opcode/mips.h" | |
25 | ||
26 | /* Short hand so the lines aren't too long. */ | |
27 | ||
28 | #define LDD INSN_LOAD_MEMORY_DELAY | |
29 | #define LCD INSN_LOAD_COPROC_DELAY | |
30 | #define UBD INSN_UNCOND_BRANCH_DELAY | |
31 | #define CBD INSN_COND_BRANCH_DELAY | |
32 | #define COD INSN_COPROC_MOVE_DELAY | |
33 | #define CLD INSN_COPROC_MEMORY_DELAY | |
34 | #define CBL INSN_COND_BRANCH_LIKELY | |
35 | #define TRAP INSN_TRAP | |
36 | #define SM INSN_STORE_MEMORY | |
37 | ||
38 | #define WR_d INSN_WRITE_GPR_D | |
39 | #define WR_t INSN_WRITE_GPR_T | |
40 | #define WR_31 INSN_WRITE_GPR_31 | |
41 | #define WR_D INSN_WRITE_FPR_D | |
42 | #define WR_T INSN_WRITE_FPR_T | |
43 | #define WR_S INSN_WRITE_FPR_S | |
44 | #define RD_s INSN_READ_GPR_S | |
45 | #define RD_b INSN_READ_GPR_S | |
46 | #define RD_t INSN_READ_GPR_T | |
47 | #define RD_S INSN_READ_FPR_S | |
48 | #define RD_T INSN_READ_FPR_T | |
49 | #define RD_R INSN_READ_FPR_R | |
50 | #define WR_CC INSN_WRITE_COND_CODE | |
51 | #define RD_CC INSN_READ_COND_CODE | |
52 | #define RD_C0 INSN_COP | |
53 | #define RD_C1 INSN_COP | |
54 | #define RD_C2 INSN_COP | |
55 | #define RD_C3 INSN_COP | |
56 | #define WR_C0 INSN_COP | |
57 | #define WR_C1 INSN_COP | |
58 | #define WR_C2 INSN_COP | |
59 | #define WR_C3 INSN_COP | |
60 | ||
61 | #define WR_HI INSN_WRITE_HI | |
62 | #define RD_HI INSN_READ_HI | |
63 | #define MOD_HI WR_HI|RD_HI | |
64 | ||
65 | #define WR_LO INSN_WRITE_LO | |
66 | #define RD_LO INSN_READ_LO | |
67 | #define MOD_LO WR_LO|RD_LO | |
68 | ||
69 | #define WR_HILO WR_HI|WR_LO | |
70 | #define RD_HILO RD_HI|RD_LO | |
71 | #define MOD_HILO WR_HILO|RD_HILO | |
72 | ||
73 | #define IS_M INSN_MULT | |
74 | ||
75 | #define I1 INSN_ISA1 | |
76 | #define I2 INSN_ISA2 | |
77 | #define I3 INSN_ISA3 | |
78 | #define I4 INSN_ISA4 | |
5fce5ddf | 79 | #define I5 INSN_ISA5 |
252b5132 RH |
80 | #define P3 INSN_4650 |
81 | #define L1 INSN_4010 | |
82 | #define V1 INSN_4100 | |
83 | #define T3 INSN_3900 | |
84 | ||
85 | #define G1 (T3 \ | |
86 | ) | |
87 | ||
88 | #define G2 (T3 \ | |
89 | ) | |
90 | ||
91 | #define G3 (I4 \ | |
92 | ) | |
93 | ||
c156a9fd NC |
94 | #define M1 0 |
95 | #define M2 0 | |
96 | ||
252b5132 RH |
97 | /* The order of overloaded instructions matters. Label arguments and |
98 | register arguments look the same. Instructions that can have either | |
99 | for arguments must apear in the correct order in this table for the | |
100 | assembler to pick the right one. In other words, entries with | |
101 | immediate operands must apear after the same instruction with | |
102 | registers. | |
103 | ||
104 | Many instructions are short hand for other instructions (i.e., The | |
105 | jal <register> instruction is short for jalr <register>). */ | |
106 | ||
107 | const struct mips_opcode mips_builtin_opcodes[] = { | |
108 | /* These instructions appear first so that the disassembler will find | |
109 | them first. The assemblers uses a hash table based on the | |
110 | instruction name anyhow. */ | |
111 | /* name, args, mask, match, pinfo */ | |
112 | {"nop", "", 0x00000000, 0xffffffff, 0, I1 }, | |
113 | {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ | |
114 | {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ | |
115 | {"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, | |
116 | {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ | |
117 | {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ | |
118 | {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ | |
119 | {"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ | |
120 | {"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ | |
121 | {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ | |
122 | ||
123 | {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, | |
124 | {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, | |
125 | {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 }, | |
5fce5ddf | 126 | {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 }, |
252b5132 RH |
127 | {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
128 | {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, | |
129 | {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1}, | |
130 | {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1}, | |
5fce5ddf | 131 | {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, |
252b5132 RH |
132 | {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, |
133 | {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, | |
134 | {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, | |
135 | {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, | |
5fce5ddf | 136 | {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5}, |
252b5132 RH |
137 | {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
138 | {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, | |
139 | {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, | |
140 | /* b is at the top of the table. */ | |
141 | /* bal is at the top of the table. */ | |
142 | {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 }, | |
143 | {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 }, | |
c156a9fd NC |
144 | {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1|M1 }, |
145 | {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|M1 }, | |
146 | {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3|M1}, | |
147 | {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|M1 }, | |
252b5132 RH |
148 | {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 }, |
149 | {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 }, | |
150 | {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 }, | |
151 | {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 }, | |
152 | {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, | |
153 | {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, | |
154 | {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, | |
155 | {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, | |
156 | {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, | |
157 | {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, | |
158 | {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 }, | |
159 | {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 }, | |
160 | {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, | |
161 | {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 }, | |
162 | {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 }, | |
163 | {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
164 | {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, | |
165 | {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, | |
166 | {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, | |
167 | {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2 }, | |
168 | {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, | |
169 | {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, | |
170 | {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2 }, | |
171 | {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2 }, | |
172 | {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, | |
173 | {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, | |
174 | {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2 }, | |
175 | {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2 }, | |
176 | {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, | |
177 | {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
178 | {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, | |
179 | {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
180 | {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, | |
181 | {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, | |
182 | {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2 }, | |
183 | {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2 }, | |
184 | {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, | |
185 | {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, | |
186 | {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2 }, | |
187 | {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2 }, | |
188 | {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, | |
189 | {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
190 | {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, | |
191 | {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, | |
192 | {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2 }, | |
193 | {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2 }, | |
194 | {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, | |
195 | {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, | |
196 | {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2 }, | |
197 | {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2 }, | |
198 | {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, | |
199 | {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
200 | {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, | |
201 | {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, | |
202 | {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2 }, | |
203 | {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2 }, | |
204 | {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, | |
205 | {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, | |
206 | {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2 }, | |
207 | {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2 }, | |
208 | {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, | |
209 | {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
210 | {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, | |
211 | {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
212 | {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, | |
213 | {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, | |
214 | {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, | |
215 | {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, | |
216 | {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, | |
217 | {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 }, | |
218 | {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, | |
219 | {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, | |
220 | {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, | |
221 | {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, | |
222 | {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
223 | {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
224 | {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
225 | {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
226 | {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
227 | {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
228 | {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
229 | {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
230 | {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
231 | {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
232 | {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
233 | {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
234 | {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
235 | {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
236 | {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
237 | {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
238 | {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
239 | {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
240 | {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
241 | {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
242 | {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
243 | {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
244 | {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
c156a9fd NC |
245 | {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
246 | {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
252b5132 RH |
247 | {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
248 | {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
249 | {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
250 | {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
251 | {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
252 | {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
253 | {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
254 | {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
255 | {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
256 | {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
257 | {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
258 | {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
c156a9fd NC |
259 | {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
260 | {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
252b5132 RH |
261 | {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
262 | {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
263 | {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
264 | {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
265 | {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
266 | {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
267 | {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
268 | {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
269 | {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
270 | {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
271 | {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
272 | {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
273 | {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
274 | {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
275 | {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
276 | {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
277 | {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
278 | {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
279 | {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
280 | {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
281 | {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
282 | {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
283 | {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
284 | {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
285 | {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
286 | {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
287 | {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
288 | {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
289 | {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
290 | {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
291 | {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
292 | {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
293 | {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
294 | {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
295 | {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
296 | {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
297 | {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
298 | {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
5fce5ddf GRK |
299 | {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
300 | {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
301 | {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
302 | {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
303 | {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
304 | {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
305 | {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
306 | {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
307 | {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
308 | {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
5fce5ddf GRK |
309 | {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
310 | {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
252b5132 RH |
311 | {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
312 | {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, | |
313 | {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, | |
314 | {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, | |
5fce5ddf GRK |
315 | {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
316 | {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, | |
c156a9fd | 317 | {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1 }, |
252b5132 RH |
318 | {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
319 | {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, | |
320 | {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, | |
321 | {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 }, | |
322 | {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, | |
323 | {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, | |
324 | {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, | |
325 | {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, | |
326 | {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, | |
327 | {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, | |
328 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, | |
329 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, | |
330 | {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, | |
331 | {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, | |
332 | {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, | |
333 | {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, | |
334 | {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 }, | |
335 | {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 }, | |
336 | {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 }, | |
337 | {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 }, | |
338 | {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 }, | |
339 | {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 }, | |
5fce5ddf GRK |
340 | {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, |
341 | {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, | |
252b5132 RH |
342 | {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
343 | {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 }, | |
5fce5ddf | 344 | {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, |
252b5132 RH |
345 | {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 }, |
346 | {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, | |
347 | {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 }, | |
348 | {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, | |
349 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, | |
350 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, | |
351 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, | |
352 | /* dctr and dctw are used on the r5000. */ | |
353 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, | |
354 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, | |
c156a9fd | 355 | {"deret", "", 0x4200001f, 0xffffffff, 0, G2|M1 }, |
252b5132 RH |
356 | /* For ddiv, see the comments about div. */ |
357 | {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, | |
358 | {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, | |
359 | {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 }, | |
360 | /* For ddivu, see the comments about div. */ | |
361 | {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, | |
362 | {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 }, | |
363 | {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, | |
364 | /* The MIPS assembler treats the div opcode with two operands as | |
365 | though the first operand appeared twice (the first operand is both | |
366 | a source and a destination). To get the div machine instruction, | |
367 | you must use an explicit destination of $0. */ | |
368 | {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, | |
369 | {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, | |
370 | {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 }, | |
371 | {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, | |
372 | {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, | |
373 | {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, | |
374 | /* For divu, see the comments about div. */ | |
375 | {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, | |
376 | {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, | |
377 | {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, | |
378 | {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, | |
6e3708af | 379 | {"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, /* daddiu */ |
252b5132 RH |
380 | {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, |
381 | {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ | |
382 | {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ | |
383 | {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 }, | |
384 | ||
385 | {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 }, | |
386 | {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, | |
387 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, | |
388 | {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, | |
389 | {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, | |
390 | {"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, | |
391 | {"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, | |
392 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, | |
393 | {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, | |
394 | {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, | |
395 | {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 }, | |
396 | {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 }, | |
397 | {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 }, | |
398 | {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, | |
399 | {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, | |
400 | {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */ | |
401 | {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/ | |
402 | {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, | |
403 | {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 }, | |
404 | {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 }, | |
405 | {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, | |
406 | {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, | |
407 | {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, | |
408 | {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, | |
409 | {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, | |
410 | {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ | |
411 | {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */ | |
412 | {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 }, | |
413 | {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, | |
414 | {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, | |
415 | {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */ | |
416 | {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */ | |
417 | {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 }, | |
418 | {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, | |
419 | {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, | |
420 | {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */ | |
421 | {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */ | |
422 | {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 }, | |
423 | {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, | |
424 | {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 }, | |
425 | {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, | |
426 | {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, | |
c156a9fd | 427 | {"eret", "", 0x42000018, 0xffffffff, 0, I3|M1 }, |
252b5132 RH |
428 | {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
429 | {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, | |
430 | {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 }, | |
431 | {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 }, | |
432 | {"flushi", "", 0xbc010000, 0xffffffff, 0, L1 }, | |
433 | {"flushd", "", 0xbc020000, 0xffffffff, 0, L1 }, | |
434 | {"flushid", "", 0xbc030000, 0xffffffff, 0, L1 }, | |
435 | {"hibernate","", 0x42000023, 0xffffffff, 0, V1 }, | |
436 | {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, | |
437 | {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */ | |
438 | /* SVR4 PIC code requires special handling for j, so it must be a | |
439 | macro. */ | |
440 | {"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 }, | |
441 | /* This form of j is used by the disassembler and internally by the | |
442 | assembler, but will never match user input (because the line above | |
443 | will match first). */ | |
444 | {"j", "a", 0x08000000, 0xfc000000, UBD, I1 }, | |
445 | {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 }, | |
446 | {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 }, | |
447 | /* SVR4 PIC code requires special handling for jal, so it must be a | |
448 | macro. */ | |
449 | {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 }, | |
450 | {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 }, | |
451 | {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 }, | |
452 | /* This form of jal is used by the disassembler and internally by the | |
453 | assembler, but will never match user input (because the line above | |
454 | will match first). */ | |
455 | {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, | |
456 | /* jalx really should only be avaliable if mips16 is available, | |
457 | but for now make it I1. */ | |
458 | {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 }, | |
6e3708af | 459 | {"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */ |
252b5132 RH |
460 | {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, |
461 | {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, | |
462 | {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 }, | |
463 | {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, | |
464 | {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 }, | |
465 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 }, | |
466 | {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 }, | |
467 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 }, | |
468 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, | |
469 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, | |
470 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, | |
471 | {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, | |
472 | {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */ | |
473 | {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 }, | |
474 | {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 }, | |
475 | {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, | |
476 | {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 }, | |
477 | {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, | |
478 | {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 }, | |
479 | {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, | |
480 | {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 }, | |
481 | {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, | |
482 | {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 }, | |
483 | {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, | |
484 | {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, | |
485 | {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 }, | |
486 | {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, | |
487 | {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 }, | |
488 | /* li is at the start of the table. */ | |
489 | {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 }, | |
490 | {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 }, | |
491 | {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 }, | |
492 | {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 }, | |
493 | {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, | |
494 | {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 }, | |
495 | {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, | |
496 | {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 }, | |
497 | {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, | |
5fce5ddf | 498 | {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5 }, |
252b5132 RH |
499 | {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
500 | {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 }, | |
501 | {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, | |
502 | {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 }, | |
503 | {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, | |
504 | {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, | |
505 | {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, | |
506 | {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, | |
507 | {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */ | |
508 | {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, | |
509 | {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, | |
510 | {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 }, | |
511 | {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, | |
512 | {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 }, | |
513 | {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, | |
514 | {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 }, | |
515 | {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ | |
516 | {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */ | |
517 | {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, | |
518 | {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 }, | |
519 | {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ | |
520 | {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */ | |
521 | {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, | |
522 | {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 }, | |
523 | {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, | |
524 | ||
525 | ||
526 | {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, | |
527 | {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, | |
528 | {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, | |
529 | {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, | |
5fce5ddf | 530 | {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, |
252b5132 | 531 | {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, |
c156a9fd | 532 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 }, |
252b5132 RH |
533 | {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 }, |
534 | {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, | |
c156a9fd | 535 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1}, |
252b5132 RH |
536 | {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, |
537 | {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 }, | |
538 | {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, | |
539 | {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, | |
540 | {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, | |
541 | {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, | |
542 | {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, | |
543 | {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, | |
544 | {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, | |
545 | {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, | |
546 | {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 }, | |
5fce5ddf | 547 | {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 }, |
c156a9fd NC |
548 | {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|M1}, |
549 | {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 }, | |
550 | {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 }, | |
5fce5ddf | 551 | {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 }, |
c156a9fd | 552 | {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1 }, |
252b5132 | 553 | {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 }, |
c156a9fd NC |
554 | {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 }, |
555 | {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 }, | |
556 | {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|M1 }, | |
557 | {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 }, | |
558 | {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 }, | |
5fce5ddf | 559 | {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5}, |
c156a9fd | 560 | {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1 }, |
252b5132 | 561 | {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 }, |
c156a9fd NC |
562 | {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 }, |
563 | {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 }, | |
252b5132 RH |
564 | /* move is at the top of the table. */ |
565 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, | |
566 | {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, | |
5fce5ddf | 567 | {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, |
252b5132 RH |
568 | {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, |
569 | {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, | |
570 | {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, | |
571 | {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, | |
572 | {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, | |
573 | {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, | |
574 | {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, | |
575 | {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 }, | |
576 | {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, | |
577 | {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, | |
578 | {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, | |
5fce5ddf | 579 | {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, |
252b5132 RH |
580 | {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3}, |
581 | {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 }, | |
582 | {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 }, | |
583 | {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 }, | |
584 | {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 }, | |
585 | {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 }, | |
586 | {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 }, | |
587 | {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1}, | |
588 | {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, | |
589 | {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1}, | |
590 | {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, | |
591 | {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */ | |
592 | {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */ | |
593 | {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 }, | |
594 | {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 }, | |
5fce5ddf | 595 | {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,I5 }, |
252b5132 RH |
596 | {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, |
597 | {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, | |
5fce5ddf | 598 | {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, |
252b5132 RH |
599 | {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, |
600 | {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, | |
5fce5ddf | 601 | {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, |
252b5132 RH |
602 | /* nop is at the start of the table. */ |
603 | {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, | |
604 | {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 }, | |
605 | {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/ | |
606 | {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, | |
607 | {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 }, | |
608 | {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, | |
609 | ||
5fce5ddf GRK |
610 | {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, |
611 | {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, | |
252b5132 | 612 | |
c156a9fd | 613 | {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1 }, |
252b5132 RH |
614 | {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, |
615 | ||
5fce5ddf GRK |
616 | {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, |
617 | {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, | |
252b5132 RH |
618 | |
619 | {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, | |
620 | {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, | |
621 | {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, | |
622 | {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, | |
623 | {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, | |
624 | {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, | |
625 | {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 }, | |
626 | {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 }, | |
627 | {"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 }, | |
628 | {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 }, | |
629 | {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 }, | |
630 | {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 }, | |
631 | {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 }, | |
632 | {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 }, | |
633 | {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 }, | |
634 | {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 }, | |
635 | {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, | |
636 | {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, | |
637 | {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, | |
638 | {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, | |
639 | {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, | |
640 | {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, | |
641 | {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 }, | |
642 | {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 }, | |
643 | {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 }, | |
644 | {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 }, | |
645 | {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 }, | |
646 | {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 }, | |
c156a9fd NC |
647 | {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 }, |
648 | {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 }, | |
649 | {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 }, | |
252b5132 RH |
650 | {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, |
651 | {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, | |
652 | {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, | |
653 | {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, | |
654 | {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 }, | |
655 | {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 }, | |
656 | {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 }, | |
657 | {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 }, | |
658 | {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, | |
659 | {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 }, | |
660 | {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 }, | |
661 | {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 }, | |
662 | {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 }, | |
663 | {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 }, | |
664 | {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 }, | |
665 | {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, | |
666 | {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, | |
667 | {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, | |
668 | {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 }, | |
669 | {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 }, | |
670 | {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 }, | |
671 | {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 }, | |
672 | {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 }, | |
673 | {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 }, | |
674 | {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 }, | |
675 | {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 }, | |
676 | {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 }, | |
677 | {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 }, | |
678 | {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 }, | |
679 | {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 }, | |
680 | {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, | |
681 | {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, | |
682 | {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, | |
683 | {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 }, | |
684 | {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, | |
685 | {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */ | |
686 | {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 }, | |
687 | {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, | |
688 | {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 }, | |
689 | {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, | |
690 | {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 }, | |
691 | {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, | |
692 | {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 }, | |
693 | {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 }, | |
694 | {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, | |
695 | {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, | |
696 | {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, | |
697 | {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, | |
698 | {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ | |
699 | {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, | |
700 | {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, | |
701 | {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ | |
702 | {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, | |
c156a9fd | 703 | {"ssnop", "", 0x00000040, 0xffffffff, 0, M1 }, |
252b5132 RH |
704 | {"standby", "", 0x42000021, 0xffffffff, 0, V1 }, |
705 | {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, | |
706 | {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, | |
707 | {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, | |
708 | {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, | |
5fce5ddf | 709 | {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, |
252b5132 RH |
710 | {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
711 | {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 }, | |
712 | {"suspend", "", 0x42000022, 0xffffffff, 0, V1 }, | |
5fce5ddf | 713 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I5 }, |
252b5132 RH |
714 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 }, |
715 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 }, | |
716 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 }, | |
717 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 }, | |
718 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, | |
719 | {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, | |
720 | {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, | |
721 | {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, | |
722 | {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ | |
723 | {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, | |
724 | {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, | |
725 | {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 }, | |
726 | {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 }, | |
727 | {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 }, | |
728 | {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, | |
729 | {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 }, | |
730 | {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ | |
731 | {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */ | |
732 | {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, | |
733 | {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 }, | |
734 | {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ | |
735 | {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */ | |
736 | {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, | |
737 | {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 }, | |
738 | {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 }, | |
739 | {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 }, | |
740 | {"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 }, | |
741 | {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 }, | |
742 | {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, | |
743 | {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, | |
744 | {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, | |
745 | {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */ | |
746 | {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 }, | |
747 | {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, | |
748 | {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, | |
749 | {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, | |
750 | {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */ | |
751 | {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 }, | |
752 | {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, | |
753 | {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, | |
754 | {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, | |
755 | {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */ | |
756 | {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 }, | |
c156a9fd NC |
757 | {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1 }, |
758 | {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1 }, | |
759 | {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1 }, | |
760 | {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1 }, | |
252b5132 RH |
761 | {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, |
762 | {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, | |
763 | {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, | |
764 | {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */ | |
765 | {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 }, | |
766 | {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, | |
767 | {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, | |
768 | {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, | |
769 | {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */ | |
770 | {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 }, | |
771 | {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, | |
772 | {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, | |
773 | {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, | |
774 | {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */ | |
775 | {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 }, | |
776 | {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 }, | |
777 | {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 }, | |
778 | {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, | |
779 | {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, | |
780 | {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 }, | |
781 | {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, | |
782 | {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, | |
783 | {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 }, | |
784 | {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 }, | |
785 | {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 }, | |
786 | {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 }, | |
787 | {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 }, | |
788 | {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 }, | |
789 | {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 }, | |
790 | {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 }, | |
791 | {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 }, | |
792 | {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 }, | |
793 | {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 }, | |
794 | {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 }, | |
795 | {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, | |
796 | {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, | |
797 | {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, | |
798 | {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, | |
799 | {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, | |
800 | {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, | |
c156a9fd | 801 | {"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1 }, |
252b5132 RH |
802 | {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, |
803 | {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, | |
804 | /* No hazard protection on coprocessor instructions--they shouldn't | |
805 | change the state of the processor and if they do it's up to the | |
806 | user to put in nops as necessary. These are at the end so that the | |
807 | disasembler recognizes more specific versions first. */ | |
808 | {"c0", "C", 0x42000000, 0xfe000000, 0, I1 }, | |
809 | {"c1", "C", 0x46000000, 0xfe000000, 0, I1 }, | |
810 | {"c2", "C", 0x4a000000, 0xfe000000, 0, I1 }, | |
811 | {"c3", "C", 0x4e000000, 0xfe000000, 0, I1 }, | |
812 | {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 }, | |
813 | {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 }, | |
814 | {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 }, | |
815 | {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 }, | |
816 | ||
817 | /* Conflicts with the 4650's "mul" instruction. Nobody's using the | |
818 | 4010 any more, so move this insn out of the way. If the object | |
819 | format gave us more info, we could do this right. */ | |
820 | {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 }, | |
821 | }; | |
822 | ||
823 | #define MIPS_NUM_OPCODES \ | |
824 | ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) | |
825 | const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; | |
826 | ||
827 | /* const removed from the following to allow for dynamic extensions to the | |
828 | * built-in instruction set. */ | |
829 | struct mips_opcode *mips_opcodes = | |
830 | (struct mips_opcode *) mips_builtin_opcodes; | |
831 | int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; | |
832 | #undef MIPS_NUM_OPCODES | |
833 |