Commit | Line | Data |
---|---|---|
657e7cec | 1 | /* mips-opc.c -- MIPS opcode list. |
1f25f5d3 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
df7b86aa NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2012 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by Ralph Campbell and OSF |
6 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
e70f2590 | 7 | Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. |
af7ee8bf CD |
8 | MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom |
9 | Corporation (SiByte). | |
252b5132 | 10 | |
9b201bb5 | 11 | This file is part of the GNU opcodes library. |
252b5132 | 12 | |
9b201bb5 NC |
13 | This library is free software; you can redistribute it and/or modify |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 3, or (at your option) | |
16 | any later version. | |
252b5132 | 17 | |
9b201bb5 NC |
18 | It is distributed in the hope that it will be useful, but WITHOUT |
19 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
20 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
21 | License for more details. | |
252b5132 | 22 | |
9b201bb5 NC |
23 | You should have received a copy of the GNU General Public License |
24 | along with this file; see the file COPYING. If not, write to the | |
25 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
26 | MA 02110-1301, USA. */ | |
252b5132 | 27 | |
0d8dfecf | 28 | #include "sysdep.h" |
df7b86aa | 29 | #include <stdio.h> |
252b5132 | 30 | #include "opcode/mips.h" |
ab902481 RS |
31 | #include "mips-formats.h" |
32 | ||
14daeee3 RS |
33 | /* The 4-bit XYZW mask used in some VU0 instructions. */ |
34 | const struct mips_operand mips_vu0_channel_mask = { OP_VU0_SUFFIX, 4, 21 }; | |
35 | ||
ab902481 RS |
36 | static unsigned char reg_0_map[] = { 0 }; |
37 | ||
38 | /* Return the mips_operand structure for the operand at the beginning of P. */ | |
39 | ||
40 | const struct mips_operand * | |
41 | decode_mips_operand (const char *p) | |
42 | { | |
43 | switch (p[0]) | |
44 | { | |
45 | case '+': | |
46 | switch (p[1]) | |
47 | { | |
48 | case '1': HINT (5, 6); | |
49 | case '2': HINT (10, 6); | |
50 | case '3': HINT (15, 6); | |
51 | case '4': HINT (20, 6); | |
14daeee3 RS |
52 | case '5': REG (5, 6, VF); |
53 | case '6': REG (5, 11, VF); | |
54 | case '7': REG (5, 16, VF); | |
55 | case '8': REG (5, 6, VI); | |
56 | case '9': REG (5, 11, VI); | |
57 | case '0': REG (5, 16, VI); | |
ab902481 RS |
58 | |
59 | case 'A': BIT (5, 6, 0); /* (0 .. 31) */ | |
60 | case 'B': MSB (5, 11, 1, TRUE, 32); /* (1 .. 32), 32-bit op */ | |
61 | case 'C': MSB (5, 11, 1, FALSE, 32); /* (1 .. 32), 32-bit op */ | |
62 | case 'E': BIT (5, 6, 32); /* (32 .. 63) */ | |
63 | case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */ | |
64 | case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */ | |
65 | case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */ | |
66 | case 'J': HINT (10, 11); | |
14daeee3 RS |
67 | case 'K': SPECIAL (4, 21, VU0_MATCH_SUFFIX); |
68 | case 'L': SPECIAL (2, 21, VU0_SUFFIX); | |
69 | case 'M': SPECIAL (2, 23, VU0_SUFFIX); | |
70 | case 'N': SPECIAL (2, 0, VU0_MATCH_SUFFIX); | |
ab902481 RS |
71 | case 'P': BIT (5, 6, 32); /* (32 .. 63) */ |
72 | case 'Q': SINT (10, 6); | |
73 | case 'S': MSB (5, 11, 0, FALSE, 63); /* (0 .. 31), 64-bit op */ | |
74 | case 'X': BIT (5, 16, 32); /* (32 .. 63) */ | |
75 | case 'Z': REG (5, 0, FP); | |
76 | ||
77 | case 'a': SINT (8, 6); | |
78 | case 'b': SINT (8, 3); | |
79 | case 'c': INT_ADJ (9, 6, 255, 4, FALSE); /* (-256 .. 255) << 4 */ | |
14daeee3 RS |
80 | case 'f': INT_ADJ (15, 6, 32767, 3, TRUE); |
81 | case 'g': SINT (5, 6); | |
ab902481 RS |
82 | case 'i': JALX (26, 0, 2); |
83 | case 'j': SINT (9, 7); | |
14daeee3 | 84 | case 'm': REG (0, 0, R5900_ACC); |
ab902481 | 85 | case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */ |
14daeee3 RS |
86 | case 'q': REG (0, 0, R5900_Q); |
87 | case 'r': REG (0, 0, R5900_R); | |
ab902481 RS |
88 | case 's': MSB (5, 11, 0, FALSE, 31); /* (0 .. 31) */ |
89 | case 't': REG (5, 16, COPRO); | |
90 | case 'x': BIT (5, 16, 0); /* (0 .. 31) */ | |
14daeee3 | 91 | case 'y': REG (0, 0, R5900_I); |
ab902481 RS |
92 | case 'z': REG (5, 0, GP); |
93 | } | |
94 | break; | |
95 | ||
96 | case '<': BIT (5, 6, 0); /* (0 .. 31) */ | |
97 | case '>': BIT (5, 6, 32); /* (32 .. 63) */ | |
98 | case '%': UINT (3, 21); | |
99 | case ':': SINT (7, 19); | |
100 | case '\'': HINT (6, 16); | |
101 | case '@': SINT (10, 16); | |
102 | case '!': UINT (1, 5); | |
103 | case '$': UINT (1, 4); | |
104 | case '*': REG (2, 18, ACC); | |
105 | case '&': REG (2, 13, ACC); | |
106 | case '~': SINT (12, 0); | |
107 | case '\\': BIT (3, 12, 0); /* (0 .. 7) */ | |
108 | ||
109 | case '0': SINT (6, 20); | |
110 | case '1': HINT (5, 6); | |
111 | case '2': HINT (2, 11); | |
112 | case '3': HINT (3, 21); | |
113 | case '4': HINT (4, 21); | |
114 | case '5': HINT (8, 16); | |
115 | case '6': HINT (5, 21); | |
116 | case '7': REG (2, 11, ACC); | |
117 | case '8': HINT (6, 11); | |
118 | case '9': REG (2, 21, ACC); | |
119 | ||
120 | case 'B': HINT (20, 6); | |
121 | case 'C': HINT (25, 0); | |
122 | case 'D': REG (5, 6, FP); | |
123 | case 'E': REG (5, 16, COPRO); | |
124 | case 'G': REG (5, 11, COPRO); | |
125 | case 'H': UINT (3, 0); | |
126 | case 'J': HINT (19, 6); | |
127 | case 'K': REG (5, 11, HW); | |
128 | case 'M': REG (3, 8, CCC); | |
129 | case 'N': REG (3, 18, CCC); | |
130 | case 'O': UINT (3, 21); | |
131 | case 'P': SPECIAL (5, 1, PERF_REG); | |
132 | case 'Q': SPECIAL (10, 16, MDMX_IMM_REG); | |
133 | case 'R': REG (5, 21, FP); | |
134 | case 'S': REG (5, 11, FP); | |
135 | case 'T': REG (5, 16, FP); | |
136 | case 'U': SPECIAL (10, 11, CLO_CLZ_DEST); | |
0f35dbc4 RS |
137 | case 'V': OPTIONAL_REG (5, 11, FP); |
138 | case 'W': OPTIONAL_REG (5, 16, FP); | |
ab902481 RS |
139 | case 'X': REG (5, 6, VEC); |
140 | case 'Y': REG (5, 11, VEC); | |
141 | case 'Z': REG (5, 16, VEC); | |
142 | ||
143 | case 'a': JUMP (26, 0, 2); | |
144 | case 'b': REG (5, 21, GP); | |
145 | case 'c': HINT (10, 16); | |
146 | case 'd': REG (5, 11, GP); | |
147 | case 'e': UINT (3, 22) | |
148 | case 'g': REG (5, 11, COPRO); | |
149 | case 'h': HINT (5, 11); | |
150 | case 'i': HINT (16, 0); | |
151 | case 'j': SINT (16, 0); | |
152 | case 'k': HINT (5, 16); | |
153 | case 'o': SINT (16, 0); | |
154 | case 'p': BRANCH (16, 0, 2); | |
155 | case 'q': HINT (10, 6); | |
0f35dbc4 | 156 | case 'r': OPTIONAL_REG (5, 21, GP); |
ab902481 RS |
157 | case 's': REG (5, 21, GP); |
158 | case 't': REG (5, 16, GP); | |
159 | case 'u': HINT (16, 0); | |
0f35dbc4 RS |
160 | case 'v': OPTIONAL_REG (5, 21, GP); |
161 | case 'w': OPTIONAL_REG (5, 16, GP); | |
ab902481 RS |
162 | case 'x': REG (0, 0, GP); |
163 | case 'z': MAPPED_REG (0, 0, GP, reg_0_map); | |
164 | } | |
165 | return 0; | |
166 | } | |
252b5132 RH |
167 | |
168 | /* Short hand so the lines aren't too long. */ | |
169 | ||
170 | #define LDD INSN_LOAD_MEMORY_DELAY | |
171 | #define LCD INSN_LOAD_COPROC_DELAY | |
172 | #define UBD INSN_UNCOND_BRANCH_DELAY | |
173 | #define CBD INSN_COND_BRANCH_DELAY | |
174 | #define COD INSN_COPROC_MOVE_DELAY | |
175 | #define CLD INSN_COPROC_MEMORY_DELAY | |
176 | #define CBL INSN_COND_BRANCH_LIKELY | |
bcd530a7 RS |
177 | #define NODS INSN_NO_DELAY_SLOT |
178 | #define TRAP INSN_NO_DELAY_SLOT | |
252b5132 RH |
179 | #define SM INSN_STORE_MEMORY |
180 | ||
fc76e730 RS |
181 | #define WR_1 INSN_WRITE_1 |
182 | #define WR_2 INSN_WRITE_2 | |
183 | #define RD_1 INSN_READ_1 | |
184 | #define RD_2 INSN_READ_2 | |
185 | #define RD_3 INSN_READ_3 | |
186 | #define RD_4 INSN_READ_4 | |
187 | #define MOD_1 (WR_1|RD_1) | |
188 | #define MOD_2 (WR_2|RD_2) | |
189 | ||
e93d7199 | 190 | #define WR_31 INSN_WRITE_GPR_31 |
252b5132 RH |
191 | #define WR_CC INSN_WRITE_COND_CODE |
192 | #define RD_CC INSN_READ_COND_CODE | |
193 | #define RD_C0 INSN_COP | |
194 | #define RD_C1 INSN_COP | |
195 | #define RD_C2 INSN_COP | |
196 | #define RD_C3 INSN_COP | |
197 | #define WR_C0 INSN_COP | |
198 | #define WR_C1 INSN_COP | |
199 | #define WR_C2 INSN_COP | |
200 | #define WR_C3 INSN_COP | |
fc76e730 | 201 | #define UDI INSN_UDI |
c27e721e | 202 | #define CP INSN_COP |
252b5132 RH |
203 | |
204 | #define WR_HI INSN_WRITE_HI | |
205 | #define RD_HI INSN_READ_HI | |
206 | #define MOD_HI WR_HI|RD_HI | |
207 | ||
208 | #define WR_LO INSN_WRITE_LO | |
209 | #define RD_LO INSN_READ_LO | |
210 | #define MOD_LO WR_LO|RD_LO | |
211 | ||
212 | #define WR_HILO WR_HI|WR_LO | |
213 | #define RD_HILO RD_HI|RD_LO | |
214 | #define MOD_HILO WR_HILO|RD_HILO | |
215 | ||
216 | #define IS_M INSN_MULT | |
217 | ||
9e836e3d FF |
218 | #define WR_MACC INSN2_WRITE_MDMX_ACC |
219 | #define RD_MACC INSN2_READ_MDMX_ACC | |
deec1734 | 220 | |
252b5132 RH |
221 | #define I1 INSN_ISA1 |
222 | #define I2 INSN_ISA2 | |
223 | #define I3 INSN_ISA3 | |
224 | #define I4 INSN_ISA4 | |
5fce5ddf | 225 | #define I5 INSN_ISA5 |
e7af610e | 226 | #define I32 INSN_ISA32 |
84ea6cf2 | 227 | #define I64 INSN_ISA64 |
af7ee8bf | 228 | #define I33 INSN_ISA32R2 |
5f74bc13 | 229 | #define I65 INSN_ISA64R2 |
56950294 MS |
230 | #define I3_32 INSN_ISA3_32 |
231 | #define I3_33 INSN_ISA3_32R2 | |
232 | #define I4_32 INSN_ISA4_32 | |
233 | #define I4_33 INSN_ISA4_32R2 | |
234 | #define I5_33 INSN_ISA5_32R2 | |
e7af610e | 235 | |
44426910 | 236 | /* MIPS64 MIPS-3D ASE support. */ |
d301a56b | 237 | #define M3D ASE_MIPS3D |
1f25f5d3 | 238 | |
39a7806d | 239 | /* MIPS32 SmartMIPS ASE support. */ |
d301a56b | 240 | #define SMT ASE_SMARTMIPS |
39a7806d | 241 | |
deec1734 | 242 | /* MIPS64 MDMX ASE support. */ |
d301a56b | 243 | #define MX ASE_MDMX |
deec1734 | 244 | |
350cc38d MS |
245 | #define IL2E (INSN_LOONGSON_2E) |
246 | #define IL2F (INSN_LOONGSON_2F) | |
fd503541 | 247 | #define IL3A (INSN_LOONGSON_3A) |
350cc38d | 248 | |
252b5132 RH |
249 | #define P3 INSN_4650 |
250 | #define L1 INSN_4010 | |
9752cf1b | 251 | #define V1 (INSN_4100 | INSN_4111 | INSN_4120) |
252b5132 | 252 | #define T3 INSN_3900 |
e407c74b NC |
253 | /* Emotion Engine MIPS r5900. */ |
254 | #define EE INSN_5900 | |
99c14723 | 255 | #define M1 INSN_10000 |
2228315b | 256 | #define SB1 INSN_SB1 |
9752cf1b RS |
257 | #define N411 INSN_4111 |
258 | #define N412 INSN_4120 | |
259 | #define N5 (INSN_5400 | INSN_5500) | |
260 | #define N54 INSN_5400 | |
261 | #define N55 INSN_5500 | |
432233b3 AP |
262 | #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2) |
263 | #define IOCTP (INSN_OCTEONP | INSN_OCTEON2) | |
264 | #define IOCT2 INSN_OCTEON2 | |
52b6b6b9 | 265 | #define XLR INSN_XLR |
d301a56b RS |
266 | #define IVIRT ASE_VIRT |
267 | #define IVIRT64 ASE_VIRT64 | |
252b5132 | 268 | |
e93d7199 | 269 | #define G1 (T3 \ |
e407c74b | 270 | |EE \ |
252b5132 RH |
271 | ) |
272 | ||
99c14723 | 273 | #define G2 (T3 \ |
252b5132 RH |
274 | ) |
275 | ||
99c14723 | 276 | #define G3 (I4 \ |
e407c74b | 277 | |EE \ |
99c14723 | 278 | ) |
252b5132 | 279 | |
e407c74b NC |
280 | /* 64 bit CPU with 32 bit FPU (single float). */ |
281 | #define SF EE | |
282 | ||
283 | /* Support for 128 bit MMI instructions. */ | |
284 | #define MMI EE | |
285 | ||
286 | /* 64 bit CPU with only 32 bit multiplication/division support. */ | |
287 | #define M32 EE | |
288 | ||
14daeee3 RS |
289 | /* Support for VU0 Coprocessor instructions */ |
290 | #define VU0 EE | |
291 | #define VU0CH INSN2_VU0_CHANNEL_SUFFIX | |
292 | ||
fd25c5a9 CF |
293 | /* MIPS DSP ASE support. |
294 | NOTE: | |
295 | 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair | |
296 | of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have | |
297 | the same structure as $ac0 (HI + LO). For DSP instructions that write or | |
298 | read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a | |
39a7806d | 299 | (RD_HILO) attributes, such that HILO dependencies are maintained |
fd25c5a9 CF |
300 | conservatively. |
301 | ||
302 | 2. For some mul. instructions that use integer registers as destinations | |
39a7806d | 303 | but destroy HI+LO as side-effect, we add WR_HILO to their attributes. |
fd25c5a9 CF |
304 | |
305 | 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields | |
306 | (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write | |
307 | certain fields of the DSP control register. For simplicity, we decide not | |
39a7806d | 308 | to track dependencies of these fields. |
fd25c5a9 CF |
309 | However, "bposge32" is a branch instruction that depends on the "pos" |
310 | field. In order to make sure that GAS does not reorder DSP instructions | |
bcd530a7 RS |
311 | that writes the "pos" field and "bposge32", we add DSP_VOLA |
312 | (INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos" | |
313 | field. */ | |
fd25c5a9 CF |
314 | |
315 | #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ | |
316 | #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ | |
317 | #define MOD_a WR_a|RD_a | |
bcd530a7 | 318 | #define DSP_VOLA INSN_NO_DELAY_SLOT |
d301a56b RS |
319 | #define D32 ASE_DSP |
320 | #define D33 ASE_DSPR2 | |
321 | #define D64 ASE_DSP64 | |
fd25c5a9 | 322 | |
61cc0267 | 323 | /* MIPS MT ASE support. */ |
d301a56b | 324 | #define MT32 ASE_MT |
61cc0267 | 325 | |
dec0624d | 326 | /* MIPS MCU (MicroController) ASE support. */ |
d301a56b | 327 | #define MC ASE_MCU |
dec0624d | 328 | |
7f3c4072 CM |
329 | /* MIPS Enhanced VA Scheme. */ |
330 | #define EVA ASE_EVA | |
331 | ||
332 | /* TLB invalidate instruction support. */ | |
333 | #define TLBINV ASE_EVA | |
334 | ||
252b5132 RH |
335 | /* The order of overloaded instructions matters. Label arguments and |
336 | register arguments look the same. Instructions that can have either | |
337 | for arguments must apear in the correct order in this table for the | |
338 | assembler to pick the right one. In other words, entries with | |
339 | immediate operands must apear after the same instruction with | |
340 | registers. | |
341 | ||
44426910 CD |
342 | Because of the lookup algorithm used, entries with the same opcode |
343 | name must be contiguous. | |
344 | ||
252b5132 RH |
345 | Many instructions are short hand for other instructions (i.e., The |
346 | jal <register> instruction is short for jalr <register>). */ | |
347 | ||
4372b673 NC |
348 | const struct mips_opcode mips_builtin_opcodes[] = |
349 | { | |
252b5132 RH |
350 | /* These instructions appear first so that the disassembler will find |
351 | them first. The assemblers uses a hash table based on the | |
352 | instruction name anyhow. */ | |
e7ae278d | 353 | /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ |
fc76e730 | 354 | {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_3, 0, I4_32|G3, 0, 0 }, |
e7ae278d | 355 | {"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3, 0, 0 }, |
fc76e730 | 356 | {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S, 0, I4_33, 0, 0 }, |
e7ae278d RS |
357 | {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ |
358 | {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ | |
359 | {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ | |
fc76e730 RS |
360 | {"li", "t,j", 0x24000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ |
361 | {"li", "t,i", 0x34000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */ | |
e7ae278d RS |
362 | {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, |
363 | {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
364 | {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 },/* daddu */ |
365 | {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* addu */ | |
366 | {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */ | |
e7ae278d RS |
367 | {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* beq 0,0 */ |
368 | {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* bgez 0 */ | |
fc76e730 | 369 | {"bal", "p", 0x04110000, 0xffff0000, WR_31|UBD, INSN2_ALIAS, I1, 0, 0 },/* bgezal 0*/ |
252b5132 | 370 | |
98675402 RS |
371 | /* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 |
372 | instructions. Put them here so that disassembler will find them first. | |
373 | The assemblers uses a hash table based on the instruction name anyhow. */ | |
fc76e730 RS |
374 | {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, |
375 | {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, | |
376 | {"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
377 | {"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, | |
378 | {"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, | |
379 | {"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, | |
380 | {"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
381 | {"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
382 | {"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
383 | {"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
384 | {"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
385 | {"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
386 | {"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
387 | {"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
388 | {"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
389 | {"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
390 | {"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
391 | {"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
392 | {"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
393 | {"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
394 | {"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
395 | {"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
396 | {"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
397 | {"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
398 | {"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
399 | {"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, | |
400 | {"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
401 | {"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
402 | {"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
403 | {"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, | |
404 | {"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, | |
405 | {"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, | |
406 | {"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, | |
407 | {"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, | |
408 | {"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
409 | {"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
410 | {"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
411 | {"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, | |
412 | {"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, | |
413 | {"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, | |
414 | {"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, | |
415 | {"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, | |
416 | {"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
417 | {"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
418 | {"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
419 | {"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
420 | {"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, | |
421 | {"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, | |
422 | {"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
423 | {"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, | |
424 | {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LDD, 0, IL3A, 0, 0 }, | |
425 | {"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 }, | |
426 | {"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LDD, 0, IL3A, 0, 0 }, | |
427 | {"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 }, | |
98675402 | 428 | |
14daeee3 RS |
429 | /* R5900 VU0 Macromode instructions. */ |
430 | {"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
431 | {"vadd", "+5+K,+6+K,+7+K", 0x4a000028, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
432 | {"vaddi", "+5+K,+6+K,+y", 0x4a000022, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
433 | {"vaddq", "+5+K,+6+K,+q", 0x4a000020, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
434 | {"vaddw", "+5+K,+6+K,+7+N", 0x4a000003, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
435 | {"vaddx", "+5+K,+6+K,+7+N", 0x4a000000, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
436 | {"vaddy", "+5+K,+6+K,+7+N", 0x4a000001, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
437 | {"vaddz", "+5+K,+6+K,+7+N", 0x4a000002, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
438 | {"vadda", "+m+K,+7+K,+6+K", 0x4a0002bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
439 | {"vaddai", "+m+K,+6+K,+y", 0x4a00023e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
440 | {"vaddaq", "+m+K,+6+K,+q", 0x4a00023c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
441 | {"vaddaw", "+m+K,+6+K,+7+N", 0x4a00003f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
442 | {"vaddax", "+m+K,+6+K,+7+N", 0x4a00003c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
443 | {"vadday", "+m+K,+6+K,+7+N", 0x4a00003d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
444 | {"vaddaz", "+m+K,+6+K,+7+N", 0x4a00003e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
445 | {"vcallms", "+f", 0x4a000038, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
446 | {"vcallmsr", "+9", 0x4a000039, 0xffff07ff, CP, 0, VU0, 0, 0 }, | |
447 | {"vclipw.xyz", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
ee5734f0 | 448 | {"vclipw", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, |
14daeee3 RS |
449 | {"vdiv", "+q,+6+L,+7+M", 0x4a0003bc, 0xfe0007ff, CP, 0, VU0, 0, 0 }, |
450 | {"vftoi0", "+7+K,+6+K", 0x4a00017c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
451 | {"vftoi4", "+7+K,+6+K", 0x4a00017d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
452 | {"vftoi12", "+7+K,+6+K", 0x4a00017e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
453 | {"vftoi15", "+7+K,+6+K", 0x4a00017f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
454 | {"viadd", "+8,+9,+0", 0x4a000030, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
455 | {"viaddi", "+0,+9,+g", 0x4a000032, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
456 | {"viand", "+8,+9,+0", 0x4a000034, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
457 | {"vilwr.w", "+0,(+9)", 0x4a2003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
458 | {"vilwr.x", "+0,(+9)", 0x4b0003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
459 | {"vilwr.y", "+0,(+9)", 0x4a8003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
460 | {"vilwr.z", "+0,(+9)", 0x4a4003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
461 | {"vior", "+8,+9,+0", 0x4a000035, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
462 | {"viswr.w", "+0,(+9)", 0x4a2003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
463 | {"viswr.x", "+0,(+9)", 0x4b0003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
464 | {"viswr.y", "+0,(+9)", 0x4a8003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
465 | {"viswr.z", "+0,(+9)", 0x4a4003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
466 | {"visub", "+8,+9,+0", 0x4a000031, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
467 | {"vitof0", "+7+K,+6+K", 0x4a00013c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
468 | {"vitof4", "+7+K,+6+K", 0x4a00013d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
469 | {"vitof12", "+7+K,+6+K", 0x4a00013e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
470 | {"vitof15", "+7+K,+6+K", 0x4a00013f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
471 | {"vlqd", "+7+K,(#-+9)", 0x4a00037e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
472 | {"vlqi", "+7+K,(+9#+)", 0x4a00037c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
473 | {"vmadd", "+5+K,+6+K,+7+K", 0x4a000029, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
474 | {"vmaddi", "+5+K,+6+K,+y", 0x4a000023, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
475 | {"vmaddq", "+5+K,+6+K,+q", 0x4a000021, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
476 | {"vmaddw", "+5+K,+6+K,+7+N", 0x4a00000b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
477 | {"vmaddx", "+5+K,+6+K,+7+N", 0x4a000008, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
478 | {"vmaddy", "+5+K,+6+K,+7+N", 0x4a000009, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
479 | {"vmaddz", "+5+K,+6+K,+7+N", 0x4a00000a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
480 | {"vmadda", "+m+K,+6+K,+7+K", 0x4a0002bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
481 | {"vmaddai", "+m+K,+6+K,+y", 0x4a00023f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
482 | {"vmaddaq", "+m+K,+6+K,+q", 0x4a00023d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
483 | {"vmaddaw", "+m+K,+6+K,+7+N", 0x4a0000bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
484 | {"vmaddax", "+m+K,+6+K,+7+N", 0x4a0000bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
485 | {"vmadday", "+m+K,+6+K,+7+N", 0x4a0000bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
486 | {"vmaddaz", "+m+K,+6+K,+7+N", 0x4a0000be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
487 | {"vmax", "+5+K,+6+K,+7+K", 0x4a00002b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
488 | {"vmaxi", "+5+K,+6+K,+y", 0x4a00001d, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
489 | {"vmaxw", "+5+K,+6+K,+7+N", 0x4a000013, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
490 | {"vmaxx", "+5+K,+6+K,+7+N", 0x4a000010, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
491 | {"vmaxy", "+5+K,+6+K,+7+N", 0x4a000011, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
492 | {"vmaxz", "+5+K,+6+K,+7+N", 0x4a000012, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
493 | {"vmfir", "+7+K,+9", 0x4a0003fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
494 | {"vmini", "+5+K,+6+K,+7+K", 0x4a00002f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
495 | {"vminii", "+5+K,+6+K,+y", 0x4a00001f, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
496 | {"vminiw", "+5+K,+6+K,+7+N", 0x4a000017, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
497 | {"vminix", "+5+K,+6+K,+7+N", 0x4a000014, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
498 | {"vminiy", "+5+K,+6+K,+7+N", 0x4a000015, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
499 | {"vminiz", "+5+K,+6+K,+7+N", 0x4a000016, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
500 | {"vmove", "+7+K,+6+K", 0x4a00033c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
501 | {"vmr32", "+7+K,+6+K", 0x4a00033d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
502 | {"vmsub", "+5+K,+6+K,+7+K", 0x4a00002d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
503 | {"vmsubi", "+5+K,+6+K,+y", 0x4a000027, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
504 | {"vmsubq", "+5+K,+6+K,+q", 0x4a000025, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
505 | {"vmsubw", "+5+K,+6+K,+7+N", 0x4a00000f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
506 | {"vmsubx", "+5+K,+6+K,+7+N", 0x4a00000c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
507 | {"vmsuby", "+5+K,+6+K,+7+N", 0x4a00000d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
508 | {"vmsubz", "+5+K,+6+K,+7+N", 0x4a00000e, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
509 | {"vmsuba", "+m+K,+7+K,+6+K", 0x4a0002fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
510 | {"vmsubai", "+m+K,+6+K,+y", 0x4a00027f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
511 | {"vmsubaq", "+m+K,+6+K,+q", 0x4a00027d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
512 | {"vmsubaw", "+m+K,+6+K,+7+N", 0x4a0000ff, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
513 | {"vmsubax", "+m+K,+6+K,+7+N", 0x4a0000fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
514 | {"vmsubay", "+m+K,+6+K,+7+N", 0x4a0000fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
515 | {"vmsubaz", "+m+K,+6+K,+7+N", 0x4a0000fe, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
516 | {"vmtir", "+0,+6+L", 0x4a0003fc, 0xff8007ff, CP, 0, VU0, 0, 0 }, | |
517 | {"vmul", "+5+K,+6+K,+7+K", 0x4a00002a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
518 | {"vmuli", "+5+K,+6+K,+y", 0x4a00001e, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
519 | {"vmulq", "+5+K,+6+K,+q", 0x4a00001c, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
520 | {"vmulw", "+5+K,+6+K,+7+N", 0x4a00001b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
521 | {"vmulx", "+5+K,+6+K,+7+N", 0x4a000018, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
522 | {"vmuly", "+5+K,+6+K,+7+N", 0x4a000019, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
523 | {"vmulz", "+5+K,+6+K,+7+N", 0x4a00001a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
524 | {"vmula", "+m+K,+6+K,+7+K", 0x4a0002be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
525 | {"vmulai", "+m+K,+6+K,+y", 0x4a0001fe, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
526 | {"vmulaq", "+m+K,+6+K,+q", 0x4a0001fc, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
527 | {"vmulaw", "+m+K,+6+K,+7+N", 0x4a0001bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
528 | {"vmulax", "+m+K,+6+K,+7+N", 0x4a0001bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
529 | {"vmulay", "+m+K,+6+K,+7+N", 0x4a0001bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
530 | {"vmulaz", "+m+K,+6+K,+7+N", 0x4a0001be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
531 | {"vnop", "", 0x4a0002ff, 0xffffffff, CP, 0, VU0, 0, 0 }, | |
532 | {"vopmula.xyz", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
533 | {"vopmula", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, | |
534 | {"vopmsub.xyz", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
535 | {"vopmsub", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 }, | |
536 | {"vrget", "+7+K,+r", 0x4a00043d, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 }, | |
537 | {"vrinit", "+r,+6+L", 0x4a00043e, 0xff9f07ff, CP, 0, VU0, 0, 0 }, | |
538 | {"vrnext", "+7+K,+r", 0x4a00043c, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 }, | |
539 | {"vrsqrt", "+q,+6+L,+7+M", 0x4a0003be, 0xfe0007ff, CP, 0, VU0, 0, 0 }, | |
540 | {"vrxor", "+r,+6+L", 0x4a00043f, 0xff9f07ff, CP, 0, VU0, 0, 0 }, | |
541 | {"vsqd", "+6+K,(#-+0)", 0x4a00037f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
542 | {"vsqi", "+6+K,(+0#+)", 0x4a00037d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
543 | {"vsqrt", "+q,+7+M", 0x4a2003bd, 0xfe60ffff, CP, 0, VU0, 0, 0 }, | |
544 | {"vsub", "+5+K,+6+K,+7+K", 0x4a00002c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
545 | {"vsubi", "+5+K,+6+K,+y", 0x4a000026, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
546 | {"vsubq", "+5+K,+6+K,+q", 0x4a000024, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, | |
547 | {"vsubw", "+5+K,+6+K,+7+N", 0x4a000007, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
548 | {"vsubx", "+5+K,+6+K,+7+N", 0x4a000004, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
549 | {"vsuby", "+5+K,+6+K,+7+N", 0x4a000005, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
550 | {"vsubz", "+5+K,+6+K,+7+N", 0x4a000006, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, | |
551 | {"vsuba", "+m+K,+6+K,+7+K", 0x4a0002fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
552 | {"vsubai", "+m+K,+6+K,+y", 0x4a00027e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
553 | {"vsubaq", "+m+K,+6+K,+q", 0x4a00027c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, | |
554 | {"vsubaw", "+m+K,+6+K,+7+N", 0x4a00007f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
555 | {"vsubax", "+m+K,+6+K,+7+N", 0x4a00007c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
556 | {"vsubay", "+m+K,+6+K,+7+N", 0x4a00007d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
557 | {"vsubaz", "+m+K,+6+K,+7+N", 0x4a00007e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, | |
558 | {"vwaitq", "", 0x4a0003bf, 0xffffffff, CP, 0, VU0, 0, 0 }, | |
559 | ||
e7ae278d | 560 | {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
561 | {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, |
562 | {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, | |
563 | {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
564 | {"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, | |
565 | {"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, RD_3|SM|NODS, 0, 0, MC, 0 }, | |
e7ae278d | 566 | {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, |
fc76e730 | 567 | {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, |
e7ae278d | 568 | {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
569 | {"add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, |
570 | {"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
571 | {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, | |
572 | {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, | |
573 | {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
574 | {"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
575 | {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
576 | {"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
577 | {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
578 | {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
579 | {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
580 | {"adda.s", "S,T", 0x46000018, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, | |
581 | {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
582 | {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
583 | {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
584 | {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
585 | {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, | |
586 | {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
e7ae278d | 587 | {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
588 | {"addu", "D,S,T", 0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, |
589 | {"addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
590 | {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
591 | {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
592 | {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
593 | {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, | |
594 | {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, SB1, MX, 0 }, | |
595 | {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, 0, MX, 0 }, | |
596 | {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
e7ae278d | 597 | {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
598 | {"and", "D,S,T", 0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
599 | {"and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
600 | {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
601 | {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
602 | {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
603 | {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
604 | {"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, RD_3|SM|NODS, 0, 0, MC, 0 }, | |
e7ae278d | 605 | {"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, |
fc76e730 | 606 | {"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, |
252b5132 RH |
607 | /* b is at the top of the table. */ |
608 | /* bal is at the top of the table. */ | |
fc76e730 RS |
609 | {"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, |
610 | {"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit032 */ | |
611 | {"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, | |
612 | {"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, | |
613 | {"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit132 */ | |
614 | {"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, | |
61cc0267 | 615 | /* bc0[tf]l? are at the bottom of the table. */ |
fc76e730 RS |
616 | {"bc1any2f", "N,p", 0x45200000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, |
617 | {"bc1any2t", "N,p", 0x45210000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, | |
618 | {"bc1any4f", "N,p", 0x45400000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, | |
619 | {"bc1any4t", "N,p", 0x45410000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, | |
620 | {"bc1f", "p", 0x45000000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, | |
621 | {"bc1f", "N,p", 0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, 0 }, | |
622 | {"bc1fl", "p", 0x45020000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, 0 }, | |
623 | {"bc1fl", "N,p", 0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, 0 }, | |
624 | {"bc1t", "p", 0x45010000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, | |
625 | {"bc1t", "N,p", 0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, 0 }, | |
626 | {"bc1tl", "p", 0x45030000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, 0 }, | |
627 | {"bc1tl", "N,p", 0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, 0 }, | |
6f14957b | 628 | /* bc2* are at the bottom of the table. */ |
39a7806d | 629 | /* bc3* are at the bottom of the table. */ |
fc76e730 RS |
630 | {"beqz", "s,p", 0x10000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, |
631 | {"beqzl", "s,p", 0x50000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, | |
632 | {"beq", "s,t,p", 0x10000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, | |
e7ae278d | 633 | {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 634 | {"beql", "s,t,p", 0x50000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, 0 }, |
e7ae278d RS |
635 | {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, |
636 | {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, | |
637 | {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
638 | {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
639 | {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
640 | {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, | |
641 | {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
642 | {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
643 | {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
fc76e730 RS |
644 | {"bgez", "s,p", 0x04010000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, |
645 | {"bgezl", "s,p", 0x04030000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, | |
646 | {"bgezal", "s,p", 0x04110000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, 0 }, | |
647 | {"bgezall", "s,p", 0x04130000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, 0 }, | |
e7ae278d RS |
648 | {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, |
649 | {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
650 | {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
651 | {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
652 | {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, | |
653 | {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
654 | {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
655 | {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
fc76e730 RS |
656 | {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, |
657 | {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, | |
e7ae278d RS |
658 | {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, |
659 | {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
660 | {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
661 | {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
662 | {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, | |
663 | {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
664 | {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
665 | {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
fc76e730 RS |
666 | {"blez", "s,p", 0x18000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, |
667 | {"blezl", "s,p", 0x58000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, | |
e7ae278d RS |
668 | {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, |
669 | {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
670 | {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
671 | {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
672 | {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, | |
673 | {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
674 | {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
675 | {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, | |
fc76e730 RS |
676 | {"bltz", "s,p", 0x04000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, |
677 | {"bltzl", "s,p", 0x04020000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, | |
678 | {"bltzal", "s,p", 0x04100000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, 0 }, | |
679 | {"bltzall", "s,p", 0x04120000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, 0 }, | |
680 | {"bnez", "s,p", 0x14000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, | |
681 | {"bnezl", "s,p", 0x54000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, | |
682 | {"bne", "s,t,p", 0x14000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, | |
e7ae278d | 683 | {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 684 | {"bnel", "s,t,p", 0x54000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, 0 }, |
e7ae278d RS |
685 | {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, |
686 | {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 }, | |
687 | {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, | |
688 | {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 }, | |
fc76e730 RS |
689 | {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, |
690 | {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
691 | {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, | |
692 | {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
693 | {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
694 | {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
695 | {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
696 | {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
697 | {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
698 | {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
699 | {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
700 | {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
701 | {"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
702 | {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
703 | {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
704 | {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
705 | {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, | |
706 | {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
707 | {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, | |
708 | {"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, | |
709 | {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
710 | {"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
711 | {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
712 | {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, | |
713 | {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
714 | {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
715 | {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
716 | {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
717 | {"c.ueq.ps", "S,T", 0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
718 | {"c.ueq.ps", "S,T", 0x45600033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
719 | {"c.ueq.ps", "M,S,T", 0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
720 | {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
721 | {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
722 | {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
723 | {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
724 | {"c.olt.ps", "S,T", 0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
725 | {"c.olt.ps", "S,T", 0x45600034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
726 | {"c.olt.ps", "M,S,T", 0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
727 | {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
728 | {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
729 | {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
730 | {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
731 | {"c.ult.ps", "S,T", 0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
732 | {"c.ult.ps", "S,T", 0x45600035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
733 | {"c.ult.ps", "M,S,T", 0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
734 | {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
735 | {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
736 | {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
737 | {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
738 | {"c.ole.ps", "S,T", 0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
739 | {"c.ole.ps", "S,T", 0x45600036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
740 | {"c.ole.ps", "M,S,T", 0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
741 | {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
742 | {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
743 | {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
744 | {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
745 | {"c.ule.ps", "S,T", 0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
746 | {"c.ule.ps", "S,T", 0x45600037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
747 | {"c.ule.ps", "M,S,T", 0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
748 | {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
749 | {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
750 | {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
751 | {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
752 | {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
753 | {"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
754 | {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
755 | {"c.ngle.d", "S,T", 0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
756 | {"c.ngle.d", "M,S,T", 0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
757 | {"c.ngle.s", "S,T", 0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
758 | {"c.ngle.s", "M,S,T", 0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
759 | {"c.ngle.ps", "S,T", 0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
760 | {"c.ngle.ps", "S,T", 0x45600039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
761 | {"c.ngle.ps", "M,S,T", 0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
762 | {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
763 | {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
764 | {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
765 | {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
766 | {"c.seq.ps", "S,T", 0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
767 | {"c.seq.ps", "S,T", 0x4560003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
768 | {"c.seq.ps", "M,S,T", 0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
769 | {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
770 | {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
771 | {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
772 | {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
773 | {"c.ngl.ps", "S,T", 0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
774 | {"c.ngl.ps", "S,T", 0x4560003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
775 | {"c.ngl.ps", "M,S,T", 0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
776 | {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
777 | {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
778 | {"c.lt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, | |
779 | {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
780 | {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
781 | {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, | |
782 | {"c.lt.ob", "S,Q", 0x48000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, | |
783 | {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
784 | {"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
785 | {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
786 | {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, | |
787 | {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
788 | {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
789 | {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
790 | {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
791 | {"c.nge.ps", "S,T", 0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
792 | {"c.nge.ps", "S,T", 0x4560003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
793 | {"c.nge.ps", "M,S,T", 0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
794 | {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
795 | {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
796 | {"c.le.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, | |
797 | {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
798 | {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
799 | {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, | |
800 | {"c.le.ob", "S,Q", 0x48000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, | |
801 | {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
802 | {"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
803 | {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
804 | {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, | |
805 | {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, | |
806 | {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, | |
807 | {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, | |
808 | {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, | |
809 | {"c.ngt.ps", "S,T", 0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
810 | {"c.ngt.ps", "S,T", 0x4560003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
811 | {"c.ngt.ps", "M,S,T", 0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, | |
812 | {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
813 | {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
814 | {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
815 | {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
816 | {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
817 | {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
818 | {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
819 | {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
820 | {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
821 | {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
822 | {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
823 | {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
824 | {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
825 | {"cabs.nge.ps", "M,S,T", 0x46c0007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
826 | {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
827 | {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
828 | {"cabs.ngl.ps", "M,S,T", 0x46c0007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
829 | {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
830 | {"cabs.ngle.d", "M,S,T", 0x46200079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
831 | {"cabs.ngle.ps", "M,S,T", 0x46c00079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
832 | {"cabs.ngle.s", "M,S,T", 0x46000079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
833 | {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
834 | {"cabs.ngt.ps", "M,S,T", 0x46c0007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
835 | {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
836 | {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
837 | {"cabs.ole.ps", "M,S,T", 0x46c00076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
838 | {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
839 | {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
840 | {"cabs.olt.ps", "M,S,T", 0x46c00074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
841 | {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
842 | {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
843 | {"cabs.seq.ps", "M,S,T", 0x46c0007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
844 | {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
845 | {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
846 | {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
847 | {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
848 | {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
849 | {"cabs.ueq.ps", "M,S,T", 0x46c00073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
850 | {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
851 | {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
852 | {"cabs.ule.ps", "M,S,T", 0x46c00077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
853 | {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
854 | {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
855 | {"cabs.ult.ps", "M,S,T", 0x46c00075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
856 | {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
857 | {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
858 | {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, | |
859 | {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, | |
39a7806d | 860 | /* CW4010 instructions which are aliases for the cache instruction. */ |
e7ae278d RS |
861 | {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1, 0, 0 }, |
862 | {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1, 0, 0 }, | |
863 | {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1, 0, 0 }, | |
fc76e730 RS |
864 | {"wb", "o(b)", 0xbc040000, 0xfc1f0000, RD_2|SM, 0, L1, 0, 0 }, |
865 | {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3, 0, 0}, | |
e7ae278d | 866 | {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, 0}, |
fc76e730 RS |
867 | {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, |
868 | {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
869 | {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, | |
870 | {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, | |
871 | {"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
872 | {"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 }, | |
873 | {"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 }, | |
6f14957b | 874 | /* cfc2 is at the bottom of the table. */ |
39a7806d | 875 | /* cfc3 is at the bottom of the table. */ |
fc76e730 RS |
876 | {"cftc1", "d,E", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD|FP_S, 0, 0, MT32, 0 }, |
877 | {"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD|FP_S, 0, 0, MT32, 0 }, | |
878 | {"cftc2", "d,E", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LCD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
879 | {"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
880 | {"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */ | |
881 | {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
882 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, | |
883 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, | |
884 | {"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
885 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, | |
886 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, | |
6f14957b | 887 | /* ctc2 is at the bottom of the table. */ |
39a7806d | 888 | /* ctc3 is at the bottom of the table. */ |
fc76e730 RS |
889 | {"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD|FP_S, 0, 0, MT32, 0 }, |
890 | {"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD|FP_S, 0, 0, MT32, 0 }, | |
891 | {"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|COD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
892 | {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, | |
893 | {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, | |
894 | {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, | |
895 | {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, | |
896 | {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
897 | {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
898 | {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, | |
899 | {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, | |
900 | {"cvt.s.pl", "D,S", 0x46c00028, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 }, | |
901 | {"cvt.s.pu", "D,S", 0x46c00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 }, | |
902 | {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, | |
903 | {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, EE }, | |
904 | {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, | |
905 | {"cvt.ps.s", "D,V,T", 0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I5_33, 0, 0 }, | |
906 | {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, | |
e7ae278d | 907 | {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 | 908 | {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, |
e7ae278d | 909 | {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 RS |
910 | {"dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
911 | {"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
912 | {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, | |
913 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, | |
914 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
e7ae278d | 915 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 | 916 | {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, |
e7ae278d | 917 | {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, |
fc76e730 RS |
918 | {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, |
919 | {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, | |
252b5132 | 920 | /* dctr and dctw are used on the r5000. */ |
fc76e730 RS |
921 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, |
922 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, | |
e7ae278d | 923 | {"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2, 0, 0 }, |
5e0dc5ba RS |
924 | {"dext", "t,r,+A,+H", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, |
925 | {"dext", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextm */ | |
926 | {"dext", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextu */ | |
fc76e730 RS |
927 | {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, |
928 | {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, | |
252b5132 | 929 | /* For ddiv, see the comments about div. */ |
fc76e730 | 930 | {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, |
e7ae278d RS |
931 | {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, M32 }, |
932 | {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
252b5132 | 933 | /* For ddivu, see the comments about div. */ |
fc76e730 | 934 | {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, |
e7ae278d RS |
935 | {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32 }, |
936 | {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
937 | {"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 }, | |
6a819047 | 938 | {"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 }, |
fc76e730 | 939 | {"di", "t", 0x41606000, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, |
fc76e730 | 940 | {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, |
5e0dc5ba RS |
941 | {"dins", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsm */ |
942 | {"dins", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsu */ | |
fc76e730 RS |
943 | {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, |
944 | {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, | |
252b5132 RH |
945 | /* The MIPS assembler treats the div opcode with two operands as |
946 | though the first operand appeared twice (the first operand is both | |
947 | a source and a destination). To get the div machine instruction, | |
948 | you must use an explicit destination of $0. */ | |
fc76e730 RS |
949 | {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, |
950 | {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, 0 }, | |
e7ae278d RS |
951 | {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, |
952 | {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
953 | {"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, |
954 | {"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, | |
955 | {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, | |
956 | {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, | |
957 | {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, | |
252b5132 | 958 | /* For divu, see the comments about div. */ |
fc76e730 RS |
959 | {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, |
960 | {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, 0 }, | |
e7ae278d RS |
961 | {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, |
962 | {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
963 | {"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, |
964 | {"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, | |
e7ae278d RS |
965 | {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 }, |
966 | {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
fc76e730 RS |
967 | {"dli", "t,j", 0x24000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* addiu */ |
968 | {"dli", "t,i", 0x34000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* ori */ | |
e7ae278d | 969 | {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 RS |
970 | {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, |
971 | {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, | |
972 | {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, | |
973 | {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, | |
974 | {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, | |
975 | {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, | |
976 | {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, | |
977 | {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, | |
978 | {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_1|RD_2|MOD_LO, 0, N411, 0, 0 }, | |
979 | {"dmfc0", "t,G", 0x40200000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I3, 0, EE }, | |
980 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I64, 0, 0 }, | |
981 | {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 }, | |
982 | {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 }, | |
e7ae278d | 983 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, |
fc76e730 RS |
984 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, |
985 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I3, 0, EE }, | |
986 | {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I64, 0, 0 }, | |
987 | {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT64, 0 }, | |
988 | {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT64, 0 }, | |
989 | {"dmfc1", "t,S", 0x44200000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I3, 0, SF }, | |
990 | {"dmfc1", "t,G", 0x44200000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I3, 0, SF }, | |
991 | {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I3, 0, SF }, | |
992 | {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I3, 0, SF }, | |
6f14957b MR |
993 | /* dmfc2 is at the bottom of the table. */ |
994 | /* dmtc2 is at the bottom of the table. */ | |
39a7806d TS |
995 | /* dmfc3 is at the bottom of the table. */ |
996 | /* dmtc3 is at the bottom of the table. */ | |
fc76e730 | 997 | {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, |
e7ae278d RS |
998 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32 }, |
999 | {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32 }, | |
1000 | {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, M32 }, | |
1001 | {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, M32 }, | |
1002 | {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, M32 }, | |
1003 | {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, M32 }, | |
fc76e730 RS |
1004 | {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32 }, |
1005 | {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32 }, | |
1006 | {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */ | |
1007 | {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0*/ | |
1008 | {"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
1009 | {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, | |
e7ae278d RS |
1010 | {"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, M32 }, |
1011 | {"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
fc76e730 | 1012 | {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, |
e7ae278d RS |
1013 | {"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, M32 }, |
1014 | {"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, M32 }, | |
1015 | {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5, 0, 0 }, | |
1016 | {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, | |
1017 | {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, | |
1018 | {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, | |
1019 | {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, | |
fc76e730 RS |
1020 | {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 }, |
1021 | {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I65, 0, 0 }, | |
1022 | {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 }, | |
e7ae278d RS |
1023 | {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65, 0, 0 }, |
1024 | {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65, 0, 0 }, | |
1025 | {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65, 0, 0 }, | |
1026 | {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65, 0, 0 }, | |
fc76e730 RS |
1027 | {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I65, 0, 0 }, |
1028 | {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, I65, 0, 0 }, | |
1029 | {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 }, | |
1030 | {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 }, | |
1031 | {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
1032 | {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
1033 | {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsllv */ | |
1034 | {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */ | |
1035 | {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
1036 | {"dsll", "D,S,T", 0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1037 | {"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1038 | {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
1039 | {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
1040 | {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */ | |
1041 | {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */ | |
1042 | {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
1043 | {"dsra", "D,S,T", 0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1044 | {"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1045 | {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
1046 | {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
1047 | {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */ | |
1048 | {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */ | |
1049 | {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, | |
1050 | {"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1051 | {"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1052 | {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
e7ae278d | 1053 | {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 RS |
1054 | {"dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
1055 | {"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1056 | {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | |
e7ae278d RS |
1057 | {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, |
1058 | {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | |
fc76e730 | 1059 | {"dvpe", "t", 0x41600001, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, |
e7ae278d | 1060 | {"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 }, |
6a819047 | 1061 | {"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 }, |
fc76e730 | 1062 | {"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, |
e7ae278d | 1063 | {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, |
fc76e730 | 1064 | {"emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, |
e7ae278d RS |
1065 | {"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 }, |
1066 | {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | |
fc76e730 RS |
1067 | {"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, |
1068 | {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, | |
1069 | {"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
1070 | {"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */ | |
1071 | {"exts", "t,r,+p,+S", 0x7000003a, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
1072 | {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, | |
1073 | {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
1074 | {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, | |
1075 | {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, | |
e7ae278d RS |
1076 | {"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 }, |
1077 | {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, | |
1078 | {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, | |
fc76e730 | 1079 | {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, |
e7ae278d | 1080 | {"iret", "", 0x42000038, 0xffffffff, NODS, 0, 0, MC, 0 }, |
fc76e730 | 1081 | {"jr", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, 0 }, |
39a7806d TS |
1082 | /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with |
1083 | the same hazard barrier effect. */ | |
fc76e730 RS |
1084 | {"jr.hb", "s", 0x00000408, 0xfc1fffff, RD_1|UBD, 0, I32, 0, 0 }, |
1085 | {"j", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, 0 }, /* jr */ | |
252b5132 RH |
1086 | /* SVR4 PIC code requires special handling for j, so it must be a |
1087 | macro. */ | |
e7ae278d | 1088 | {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 }, |
252b5132 RH |
1089 | /* This form of j is used by the disassembler and internally by the |
1090 | assembler, but will never match user input (because the line above | |
1091 | will match first). */ | |
e7ae278d | 1092 | {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1, 0, 0 }, |
fc76e730 RS |
1093 | {"jalr", "s", 0x0000f809, 0xfc1fffff, RD_1|WR_31|UBD, 0, I1, 0, 0 }, |
1094 | {"jalr", "d,s", 0x00000009, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I1, 0, 0 }, | |
39a7806d TS |
1095 | /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr |
1096 | with the same hazard barrier effect. */ | |
fc76e730 RS |
1097 | {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, RD_1|WR_31|UBD, 0, I32, 0, 0 }, |
1098 | {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I32, 0, 0 }, | |
252b5132 RH |
1099 | /* SVR4 PIC code requires special handling for jal, so it must be a |
1100 | macro. */ | |
e7ae278d RS |
1101 | {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 }, |
1102 | {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1, 0, 0 }, | |
1103 | {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1, 0, 0 }, | |
252b5132 RH |
1104 | /* This form of jal is used by the disassembler and internally by the |
1105 | assembler, but will never match user input (because the line above | |
1106 | will match first). */ | |
fc76e730 RS |
1107 | {"jal", "a", 0x0c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, |
1108 | {"jalx", "+i", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, | |
e7ae278d | 1109 | {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1110 | {"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, |
1111 | {"laad", "d,(b),t", 0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, | |
1112 | {"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1113 | {"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1114 | {"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1115 | {"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1116 | {"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1117 | {"laid", "d,(b)", 0x700000df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1118 | {"las", "d,(b)", 0x7000029f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1119 | {"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, | |
1120 | {"law", "d,(b),t", 0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, | |
1121 | {"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, | |
1122 | {"lb", "t,o(b)", 0x80000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, | |
e7ae278d | 1123 | {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1124 | {"lbu", "t,o(b)", 0x90000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, |
e7ae278d | 1125 | {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1126 | {"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, 0, 0 }, |
1127 | {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D32, 0}, | |
1128 | {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D64, 0}, | |
1129 | {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D32, 0}, | |
1130 | {"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, 0, 0 }, | |
1131 | {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D32, 0}, | |
1132 | {"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, 0, 0 }, | |
e7ae278d | 1133 | {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, |
704897fb | 1134 | /* The macro has to be first to handle o32 correctly. */ |
e7ae278d | 1135 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1136 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3, 0, I3, 0, 0 }, |
1137 | {"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, | |
1138 | {"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, | |
1139 | {"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, | |
1140 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, | |
1141 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, | |
e7ae278d RS |
1142 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, |
1143 | {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | |
fc76e730 | 1144 | {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */ |
e7ae278d | 1145 | {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, |
fc76e730 | 1146 | {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1147 | {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1148 | {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1149 | {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1150 | {"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, 0 }, |
e7ae278d | 1151 | {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 | 1152 | {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, 0 }, |
e7ae278d | 1153 | {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 RS |
1154 | {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_D, 0, I4_33, 0, 0 }, |
1155 | {"lh", "t,o(b)", 0x84000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, | |
e7ae278d | 1156 | {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1157 | {"lhu", "t,o(b)", 0x94000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, |
e7ae278d | 1158 | {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, |
252b5132 | 1159 | /* li is at the start of the table. */ |
e7ae278d RS |
1160 | {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, |
1161 | {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, | |
1162 | {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
1163 | {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
fc76e730 | 1164 | {"ll", "t,o(b)", 0xc0000000, 0xfc000000, WR_1|RD_3|LDD, 0, I2, 0, EE }, |
e7ae278d | 1165 | {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2, 0, EE }, |
fc76e730 | 1166 | {"lld", "t,o(b)", 0xd0000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, EE }, |
e7ae278d | 1167 | {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE }, |
fc76e730 | 1168 | {"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3, 0, MMI, 0, 0 }, |
e7ae278d | 1169 | {"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, |
14daeee3 RS |
1170 | {"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2, 0, EE, 0, 0 }, |
1171 | {"lqc2", "+7,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, | |
fc76e730 RS |
1172 | {"lui", "t,u", 0x3c000000, 0xffe00000, WR_1, 0, I1, 0, 0 }, |
1173 | {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_D, 0, I5_33|N55, 0, 0}, | |
1174 | {"lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, | |
e7ae278d | 1175 | {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1176 | {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
e7ae278d | 1177 | {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
fc76e730 RS |
1178 | {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, |
1179 | {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, | |
e7ae278d RS |
1180 | {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, |
1181 | {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
fc76e730 | 1182 | {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, /* lwc1 */ |
e7ae278d | 1183 | {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, |
fc76e730 | 1184 | {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1185 | {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1186 | {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1187 | {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1188 | {"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, |
e7ae278d | 1189 | {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1190 | {"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LDD, 0, I2, 0, 0 }, /* same */ |
e7ae278d | 1191 | {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as lwl */ |
fc76e730 | 1192 | {"lwr", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, |
e7ae278d | 1193 | {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1194 | {"flush", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LDD, 0, I2, 0, 0 }, /* same */ |
e7ae278d | 1195 | {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as lwr */ |
fc76e730 RS |
1196 | {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP, 0, 0, MT32, 0 }, |
1197 | {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, 0 }, | |
e7ae278d | 1198 | {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 RS |
1199 | {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_S, 0, I4_33, 0, 0 }, |
1200 | {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, 0, SMT, 0 }, | |
1201 | {"macc", "d,s,t", 0x00000028, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1202 | {"macc", "d,s,t", 0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1203 | {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1204 | {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1205 | {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1206 | {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1207 | {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1208 | {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1209 | {"macchius", "d,s,t", 0x00000668, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1210 | {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1211 | {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1212 | {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, | |
1213 | {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, | |
1214 | {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, | |
1215 | {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, | |
1216 | {"madd.d", "D,S,T", 0x46200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1217 | {"madd.d", "D,S,T", 0x72200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
1218 | {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, | |
1219 | {"madd.s", "D,S,T", 0x46000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
1220 | {"madd.s", "D,S,T", 0x72000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, | |
1221 | {"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, | |
1222 | {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, | |
1223 | {"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1224 | {"madd.ps", "D,S,T", 0x72c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
1225 | {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, | |
1226 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1227 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1228 | {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
1229 | {"madd", "d,s,t", 0x70000000, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1230 | {"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1231 | {"madd1", "d,s,t", 0x70000020, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1232 | {"madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, | |
1233 | {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, | |
1234 | {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, | |
1235 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1236 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1237 | {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
1238 | {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1239 | {"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1240 | {"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1241 | {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, N411, 0, 0 }, | |
1242 | {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1243 | {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1244 | {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1245 | {"max.s", "D,S,T", 0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, | |
1246 | {"mfbpc", "t", 0x4000c000, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, | |
1247 | {"mfdab", "t", 0x4000c004, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, | |
1248 | {"mfdabm", "t", 0x4000c005, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, | |
1249 | {"mfdvb", "t", 0x4000c006, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, | |
1250 | {"mfdvbm", "t", 0x4000c007, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, | |
1251 | {"mfiab", "t", 0x4000c002, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, | |
1252 | {"mfiabm", "t", 0x4000c003, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, | |
1253 | {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LCD, 0, M1|N5|EE, 0, 0 }, | |
1254 | {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LCD, 0, M1|N5|EE, 0, 0 }, | |
1255 | {"mftacx", "d", 0x41020021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, | |
1256 | {"mftacx", "d,*", 0x41020021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, | |
1257 | {"mftc0", "d,+t", 0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LCD, 0, 0, MT32, 0 }, | |
1258 | {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LCD, 0, 0, MT32, 0 }, | |
1259 | {"mftc1", "d,T", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_S, 0, 0, MT32, 0 }, | |
1260 | {"mftc1", "d,E", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_S, 0, 0, MT32, 0 }, | |
1261 | {"mftc2", "d,E", 0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LCD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1262 | {"mftdsp", "d", 0x41100021, 0xffff07ff, WR_1|TRAP, 0, 0, MT32, 0 }, | |
1263 | {"mftgpr", "d,t", 0x41000020, 0xffe007ff, WR_1|RD_2|TRAP, 0, 0, MT32, 0 }, | |
1264 | {"mfthc1", "d,T", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_D, 0, 0, MT32, 0 }, | |
1265 | {"mfthc1", "d,E", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_D, 0, 0, MT32, 0 }, | |
1266 | {"mfthc2", "d,E", 0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LCD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1267 | {"mfthi", "d", 0x41010021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, | |
1268 | {"mfthi", "d,*", 0x41010021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, | |
1269 | {"mftlo", "d", 0x41000021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, | |
1270 | {"mftlo", "d,*", 0x41000021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, | |
1271 | {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, WR_1|TRAP, 0, 0, MT32, 0 }, | |
1272 | {"mfc0", "t,G", 0x40000000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I1, 0, 0 }, | |
1273 | {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I32, 0, 0 }, | |
1274 | {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1|RD_C0|LCD, 0, 0, IVIRT, 0 }, | |
1275 | {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1|RD_C0|LCD, 0, 0, IVIRT, 0 }, | |
1276 | {"mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S, 0, I1, 0, 0 }, | |
1277 | {"mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S, 0, I1, 0, 0 }, | |
1278 | {"mfhc1", "t,S", 0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I33, 0, 0 }, | |
1279 | {"mfhc1", "t,G", 0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I33, 0, 0 }, | |
6f14957b MR |
1280 | /* mfc2 is at the bottom of the table. */ |
1281 | /* mfhc2 is at the bottom of the table. */ | |
39a7806d | 1282 | /* mfc3 is at the bottom of the table. */ |
fc76e730 RS |
1283 | {"mfdr", "t,G", 0x7000003d, 0xffe007ff, WR_1|RD_C0|LCD, 0, N5, 0, 0 }, |
1284 | {"mfhi", "d", 0x00000010, 0xffff07ff, WR_1|RD_HI, 0, I1, 0, 0 }, | |
1285 | {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_1|RD_HI, 0, 0, D32, 0 }, | |
1286 | {"mfhi1", "d", 0x70000010, 0xffff07ff, WR_1|RD_HI, 0, EE, 0, 0 }, | |
1287 | {"mflo", "d", 0x00000012, 0xffff07ff, WR_1|RD_LO, 0, I1, 0, 0 }, | |
1288 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, | |
1289 | {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, | |
1290 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, | |
1291 | {"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR, 0, 0 }, | |
1292 | {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, | |
1293 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1294 | {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1295 | {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1296 | {"min.s", "D,S,T", 0x46000029, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, | |
1297 | {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, | |
1298 | {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, | |
1299 | {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
1300 | {"mov.ps", "D,S", 0x45600006, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, | |
1301 | {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, 0 }, | |
1302 | {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, 0 }, | |
1303 | {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1304 | {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1305 | {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
1306 | {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, 0 }, | |
1307 | {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, 0 }, | |
1308 | {"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F|IL3A, 0, 0 }, | |
1309 | {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, | |
1310 | {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, 0 }, | |
1311 | {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1312 | {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1313 | {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, 0 }, | |
1314 | {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, | |
1315 | {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, 0 }, | |
1316 | {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, 0 }, | |
1317 | {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1318 | {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, | |
1319 | {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, 0 }, | |
1320 | {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, 0 }, | |
1321 | {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, 0 }, | |
1322 | {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, | |
1323 | {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, 0 }, | |
1324 | {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1325 | {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1326 | {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, 0 }, | |
1327 | {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, | |
1328 | {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1329 | {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1330 | {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1331 | {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
252b5132 | 1332 | /* move is at the top of the table. */ |
fc76e730 | 1333 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, |
e7ae278d RS |
1334 | {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, |
1335 | {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 }, | |
1336 | {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, | |
1337 | {"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, | |
1338 | {"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, | |
fc76e730 RS |
1339 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, |
1340 | {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1341 | {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
1342 | {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, | |
1343 | {"msub.s", "D,S,T", 0x46000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
1344 | {"msub.s", "D,S,T", 0x72000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, | |
1345 | {"msub.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, | |
1346 | {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, | |
1347 | {"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1348 | {"msub.ps", "D,S,T", 0x72c00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
1349 | {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, | |
1350 | {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1351 | {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
1352 | {"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, | |
1353 | {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, | |
1354 | {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, | |
1355 | {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
1356 | {"mtbpc", "t", 0x4080c000, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, | |
1357 | {"mtdab", "t", 0x4080c004, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, | |
1358 | {"mtdabm", "t", 0x4080c005, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, | |
1359 | {"mtdvb", "t", 0x4080c006, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, | |
1360 | {"mtdvbm", "t", 0x4080c007, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, | |
1361 | {"mtiab", "t", 0x4080c002, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, | |
1362 | {"mtiabm", "t", 0x4080c003, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, | |
1363 | {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, RD_1|WR_C0|COD, 0, M1|N5|EE, 0, 0 }, | |
1364 | {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, RD_1|WR_C0|COD, 0, M1|N5|EE, 0, 0 }, | |
1365 | {"mtc0", "t,G", 0x40800000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I1, 0, 0 }, | |
1366 | {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I32, 0, 0 }, | |
1367 | {"mtgc0", "t,G", 0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT, 0 }, | |
1368 | {"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT, 0 }, | |
1369 | {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S, 0, I1, 0, 0 }, | |
1370 | {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S, 0, I1, 0, 0 }, | |
1371 | {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I33, 0, 0 }, | |
1372 | {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I33, 0, 0 }, | |
6f14957b MR |
1373 | /* mtc2 is at the bottom of the table. */ |
1374 | /* mthc2 is at the bottom of the table. */ | |
39a7806d | 1375 | /* mtc3 is at the bottom of the table. */ |
fc76e730 RS |
1376 | {"mtdr", "t,G", 0x7080003d, 0xffe007ff, RD_1|WR_C0|COD, 0, N5, 0, 0 }, |
1377 | {"mthi", "s", 0x00000011, 0xfc1fffff, RD_1|WR_HI, 0, I1, 0, 0 }, | |
1378 | {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_1|WR_HI, 0, 0, D32, 0 }, | |
1379 | {"mthi1", "s", 0x70000011, 0xfc1fffff, RD_1|WR_HI, 0, EE, 0, 0 }, | |
1380 | {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_1|WR_LO, 0, I1, 0, 0 }, | |
1381 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, | |
1382 | {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, | |
1383 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, | |
1384 | {"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR, 0, 0 }, | |
1385 | {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | |
1386 | {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | |
1387 | {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | |
1388 | {"mtp0", "s", 0x70000009, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | |
1389 | {"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | |
1390 | {"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | |
1391 | {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 }, | |
1392 | {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, | |
1393 | {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, | |
1394 | {"mttc0", "t,G", 0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|COD, 0, 0, MT32, 0 }, | |
1395 | {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|COD, 0, 0, MT32, 0 }, | |
1396 | {"mttc1", "t,S", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_S, 0, 0, MT32, 0 }, | |
1397 | {"mttc1", "t,G", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_S, 0, 0, MT32, 0 }, | |
1398 | {"mttc2", "t,g", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|COD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1399 | {"mttacx", "t", 0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, | |
1400 | {"mttacx", "t,&", 0x41801021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, | |
1401 | {"mttdsp", "t", 0x41808021, 0xffe0ffff, RD_1|TRAP, 0, 0, MT32, 0 }, | |
1402 | {"mttgpr", "t,d", 0x41800020, 0xffe007ff, RD_1|WR_2|TRAP, 0, 0, MT32, 0 }, | |
1403 | {"mtthc1", "t,S", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_D, 0, 0, MT32, 0 }, | |
1404 | {"mtthc1", "t,G", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_D, 0, 0, MT32, 0 }, | |
1405 | {"mtthc2", "t,g", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|COD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, | |
1406 | {"mtthi", "t", 0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, | |
1407 | {"mtthi", "t,&", 0x41800821, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, | |
1408 | {"mttlo", "t", 0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, | |
1409 | {"mttlo", "t,&", 0x41800021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, | |
1410 | {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, RD_1|TRAP, 0, 0, MT32, 0 }, | |
1411 | {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, | |
1412 | {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, | |
1413 | {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1414 | {"mul.ob", "D,S,Q", 0x48000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1415 | {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
1416 | {"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1417 | {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1418 | {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I32|P3|N55, 0, 0}, | |
1419 | {"mul", "d,s,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N54, 0, 0 }, | |
e7ae278d RS |
1420 | {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 }, |
1421 | {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1422 | {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, |
1423 | {"mula.ob", "S,Q", 0x48000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, | |
1424 | {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
1425 | {"mula.s", "S,T", 0x4600001a, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, | |
1426 | {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1427 | {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1428 | {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
1429 | {"mull.ob", "S,Q", 0x48000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, | |
1430 | {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
e7ae278d RS |
1431 | {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, 0 }, |
1432 | {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1433 | {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, 0 }, | |
1434 | {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1435 | {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, |
1436 | {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1437 | {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1438 | {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1439 | {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1440 | {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
1441 | {"muls.ob", "S,Q", 0x48000032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, | |
1442 | {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
1443 | {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
1444 | {"mulsl.ob", "S,Q", 0x48000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, | |
1445 | {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
1446 | {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, 0 }, | |
1447 | {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, | |
1448 | {"mult", "d,s,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1449 | {"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1450 | {"mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1451 | {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, | |
1452 | {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, 0 }, | |
1453 | {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, | |
1454 | {"multu", "d,s,t", 0x00000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, | |
1455 | {"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1456 | {"multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, | |
1457 | {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, | |
1458 | {"neg", "d,w", 0x00000022, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* sub 0 */ | |
1459 | {"negu", "d,w", 0x00000023, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* subu 0 */ | |
1460 | {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, | |
1461 | {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, | |
1462 | {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
1463 | {"neg.ps", "D,V", 0x45600007, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, | |
1464 | {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, | |
1465 | {"nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1466 | {"nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
1467 | {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, | |
1468 | {"nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
1469 | {"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, | |
1470 | {"nmadd.ps", "D,R,S,T", 0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, | |
1471 | {"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1472 | {"nmadd.ps", "D,S,T", 0x72c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
1473 | {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, | |
1474 | {"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1475 | {"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
1476 | {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, | |
1477 | {"nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, | |
1478 | {"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, | |
1479 | {"nmsub.ps", "D,R,S,T", 0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, | |
1480 | {"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1481 | {"nmsub.ps", "D,S,T", 0x72c0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | |
252b5132 | 1482 | /* nop is at the start of the table. */ |
fc76e730 | 1483 | {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, |
e7ae278d | 1484 | {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1485 | {"nor", "D,S,T", 0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
1486 | {"nor", "D,S,T", 0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1487 | {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1488 | {"nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1489 | {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1490 | {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 },/*nor d,s,0*/ | |
1491 | {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
e7ae278d | 1492 | {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1493 | {"or", "D,S,T", 0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
1494 | {"or", "D,S,T", 0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1495 | {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1496 | {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1497 | {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1498 | {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
1499 | {"pabsdiff.ob", "X,Y,Q", 0x78000009, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, | |
1500 | {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, 0, 0 }, | |
e7ae278d | 1501 | {"pause", "", 0x00000140, 0xffffffff, TRAP, 0, I33, 0, 0 }, |
fc76e730 RS |
1502 | {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, |
1503 | {"pabsh", "d,t", 0x70000168, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1504 | {"pabsw", "d,t", 0x70000068, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1505 | {"paddsw", "d,s,t", 0x70000408, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1506 | {"paddub", "d,s,t", 0x70000628, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1507 | {"padduh", "d,s,t", 0x70000528, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1508 | {"padduw", "d,s,t", 0x70000428, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1509 | {"padsbh", "d,s,t", 0x70000128, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1510 | {"pand", "d,s,t", 0x70000489, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1511 | {"pceqb", "d,s,t", 0x700002a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1512 | {"pceqh", "d,s,t", 0x700001a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1513 | {"pceqw", "d,s,t", 0x700000a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1514 | {"pcgtb", "d,s,t", 0x70000288, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1515 | {"pcgth", "d,s,t", 0x70000188, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1516 | {"pcgtw", "d,s,t", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1517 | {"pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1518 | {"pcpyld", "d,s,t", 0x70000389, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1519 | {"pcpyud", "d,s,t", 0x700003a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1520 | {"pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, | |
1521 | {"pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, | |
1522 | {"pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, | |
1523 | {"pexch", "d,t", 0x700006a9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1524 | {"pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1525 | {"pexeh", "d,t", 0x70000689, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1526 | {"pexew", "d,t", 0x70000789, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1527 | {"pext5", "d,t", 0x70000788, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1528 | {"pextlb", "d,s,t", 0x70000688, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1529 | {"pextlh", "d,s,t", 0x70000588, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1530 | {"pextlw", "d,s,t", 0x70000488, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1531 | {"pextub", "d,s,t", 0x700006a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1532 | {"pextuh", "d,s,t", 0x700005a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1533 | {"pextuw", "d,s,t", 0x700004a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1534 | {"phmadh", "d,s,t", 0x70000449, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, | |
1535 | {"phmsbh", "d,s,t", 0x70000549, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, | |
1536 | {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1537 | {"pickf.ob", "D,S,Q", 0x48000002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1538 | {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1539 | {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1540 | {"pickt.ob", "D,S,Q", 0x48000003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1541 | {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1542 | {"pinteh", "d,s,t", 0x700002a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1543 | {"pinth", "d,s,t", 0x70000289, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1544 | {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, | |
1545 | {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, | |
1546 | {"plzcw", "d,s", 0x70000004, 0xfc1f07ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1547 | {"pmaddh", "d,s,t", 0x70000409, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, | |
1548 | {"pmadduw", "d,s,t", 0x70000029, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, | |
1549 | {"pmaddw", "d,s,t", 0x70000009, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, | |
1550 | {"pmaxh", "d,s,t", 0x700001c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1551 | {"pmaxw", "d,s,t", 0x700000c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1552 | {"pmfhi", "d", 0x70000209, 0xffff07ff, WR_1|RD_HI, 0, MMI, 0, 0 }, | |
1553 | {"pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, | |
1554 | {"pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, | |
1555 | {"pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, | |
1556 | {"pmfhl.slw", "d", 0x700000b0, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, | |
1557 | {"pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, | |
1558 | {"pmflo", "d", 0x70000249, 0xffff07ff, WR_1|RD_LO, 0, MMI, 0, 0 }, | |
1559 | {"pminh", "d,s,t", 0x700001e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1560 | {"pminw", "d,s,t", 0x700000e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1561 | {"pmsubh", "d,s,t", 0x70000509, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, | |
1562 | {"pmsubw", "d,s,t", 0x70000109, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, | |
1563 | {"pmthi", "s", 0x70000229, 0xfc1fffff, RD_1|WR_HI, 0, MMI, 0, 0 }, | |
1564 | {"pmthl.lw", "s", 0x70000031, 0xfc1fffff, RD_1|MOD_HILO, 0, MMI, 0, 0 }, | |
1565 | {"pmtlo", "s", 0x70000269, 0xfc1fffff, RD_1|WR_LO, 0, MMI, 0, 0 }, | |
1566 | {"pmulth", "d,s,t", 0x70000709, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, | |
1567 | {"pmultuw", "d,s,t", 0x70000329, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, | |
1568 | {"pmultw", "d,s,t", 0x70000309, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, | |
1569 | {"pnor", "d,s,t", 0x700004e9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1570 | {"pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
1571 | {"por", "d,s,t", 0x700004a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1572 | {"ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1573 | {"ppacb", "d,s,t", 0x700006c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1574 | {"ppach", "d,s,t", 0x700005c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1575 | {"ppacw", "d,s,t", 0x700004c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1576 | {"prevh", "d,t", 0x700006c9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1577 | {"prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, | |
1578 | {"psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1579 | {"psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1580 | {"psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1581 | {"psubsw", "d,s,t", 0x70000448, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1582 | {"psubub", "d,s,t", 0x70000668, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1583 | {"psubuh", "d,s,t", 0x70000568, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1584 | {"psubuw", "d,s,t", 0x70000468, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1585 | {"pxor", "d,s,t", 0x700004c9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
564e8ad9 | 1586 | /* pref and prefx are at the start of the table. */ |
fc76e730 RS |
1587 | {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, |
1588 | {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, | |
1589 | {"pperm", "s,t", 0x70000481, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, | |
1590 | {"qfsrv", "d,s,t", 0x700006e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
1591 | {"qmac.00", "s,t", 0x70000412, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1592 | {"qmac.01", "s,t", 0x70000452, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1593 | {"qmac.02", "s,t", 0x70000492, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1594 | {"qmac.03", "s,t", 0x700004d2, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1595 | {"qmacs.00", "s,t", 0x70000012, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1596 | {"qmacs.01", "s,t", 0x70000052, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1597 | {"qmacs.02", "s,t", 0x70000092, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1598 | {"qmacs.03", "s,t", 0x700000d2, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, | |
1599 | {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, | |
1600 | {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, | |
1601 | {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, | |
1602 | {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, | |
1603 | {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, | |
1604 | {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, | |
1605 | {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, | |
1606 | {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, | |
1607 | {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, | |
1608 | {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_1|RD_2|FP_D, 0, I4_33, 0, 0 }, | |
1609 | {"recip.ps", "D,S", 0x46c00015, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, | |
1610 | {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_1|RD_2|FP_S, 0, I4_33, 0, 0 }, | |
1611 | {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, M3D, 0 }, | |
1612 | {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, | |
1613 | {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, | |
1614 | {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, | |
1615 | {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, | |
1616 | {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, | |
1617 | {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, | |
e7ae278d RS |
1618 | {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, |
1619 | {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 | 1620 | {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, |
e7ae278d RS |
1621 | {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, |
1622 | {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1623 | {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 }, |
1624 | {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 }, | |
b015e599 | 1625 | /* rfe is moved below as it now conflicts with tlbgp */ |
fc76e730 RS |
1626 | {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, |
1627 | {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, | |
1628 | {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, | |
1629 | {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, | |
1630 | {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, | |
1631 | {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, | |
e7ae278d RS |
1632 | {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, |
1633 | {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1634 | {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, | |
1635 | {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1636 | {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 }, |
1637 | {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 }, | |
e7ae278d RS |
1638 | {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, |
1639 | {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, | |
1640 | {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, | |
1641 | {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, | |
fc76e730 RS |
1642 | {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 }, |
1643 | {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, | |
1644 | {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
1645 | {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, | |
1646 | {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, | |
1647 | {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_1|RD_2|FP_D, 0, I4_33, 0, 0 }, | |
1648 | {"rsqrt.ps", "D,S", 0x46c00016, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, | |
1649 | {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_1|RD_2|FP_S, 0, I4_33, 0, 0 }, | |
1650 | {"rsqrt.s", "D,S,T", 0x46000016, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, | |
1651 | {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, M3D, 0 }, | |
1652 | {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, | |
1653 | {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, | |
1654 | {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, | |
1655 | {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, | |
1656 | {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, | |
1657 | {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, | |
1658 | {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, | |
1659 | {"rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, N54, 0, 0 }, | |
1660 | {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, | |
e7ae278d | 1661 | {"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, |
fc76e730 | 1662 | {"saa", "t,(b)", 0x70000018, 0xfc00ffff, RD_1|RD_2|SM, 0, IOCTP, 0, 0 }, |
e7ae278d | 1663 | {"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, |
fc76e730 RS |
1664 | {"saad", "t,(b)", 0x70000019, 0xfc00ffff, RD_1|RD_2|SM, 0, IOCTP, 0, 0 }, |
1665 | {"sb", "t,o(b)", 0xa0000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, | |
e7ae278d | 1666 | {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1667 | {"sc", "t,o(b)", 0xe0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I2, 0, EE }, |
e7ae278d | 1668 | {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2, 0, EE }, |
fc76e730 | 1669 | {"scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE }, |
e7ae278d | 1670 | {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE }, |
704897fb | 1671 | /* The macro has to be first to handle o32 correctly. */ |
e7ae278d | 1672 | {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1673 | {"sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, |
e7ae278d RS |
1674 | {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2, 0, 0 }, |
1675 | {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2, 0, 0 }, | |
1676 | {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2, 0, 0 }, | |
1677 | {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32, 0, 0 }, | |
1678 | {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32, 0, 0 }, | |
fc76e730 RS |
1679 | {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, |
1680 | {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, | |
e7ae278d RS |
1681 | {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, |
1682 | {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | |
fc76e730 | 1683 | {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1684 | {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1685 | {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1686 | {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1687 | {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, |
e7ae278d | 1688 | {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, |
fc76e730 | 1689 | {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, |
e7ae278d | 1690 | {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 | 1691 | {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, |
e7ae278d | 1692 | {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, 0 }, |
fc76e730 RS |
1693 | {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I4_33, 0, 0 }, |
1694 | {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, | |
1695 | {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, | |
1696 | {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, | |
1697 | {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, | |
1698 | {"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, | |
e7ae278d RS |
1699 | {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 }, |
1700 | {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1701 | {"seq", "S,T", 0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, |
1702 | {"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1703 | {"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, | |
e7ae278d RS |
1704 | {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 }, |
1705 | {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1706 | {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1, 0, 0 }, | |
1707 | {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1708 | {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1, 0, 0 }, | |
1709 | {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
1710 | {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1, 0, 0 }, | |
1711 | {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 | 1712 | {"sh", "t,o(b)", 0xa4000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, |
e7ae278d | 1713 | {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1714 | {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, |
1715 | {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1716 | {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1717 | {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1718 | {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1719 | {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1720 | {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1721 | {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1722 | {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1723 | {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1724 | {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1725 | {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1726 | {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1727 | {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
e7ae278d RS |
1728 | {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, |
1729 | {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1730 | {"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, |
1731 | {"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
e7ae278d RS |
1732 | {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 }, |
1733 | {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1734 | {"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, |
1735 | {"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1736 | {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
1737 | {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* sllv */ | |
1738 | {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, | |
1739 | {"sll", "D,S,T", 0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1740 | {"sll", "D,S,T", 0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1741 | {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1742 | {"sll.ob", "D,S,Q", 0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1743 | {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1744 | {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
e7ae278d | 1745 | {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1746 | {"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, |
1747 | {"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1748 | {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
1749 | {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
1750 | {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
e7ae278d | 1751 | {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1752 | {"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, |
1753 | {"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1754 | {"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, | |
e7ae278d RS |
1755 | {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 }, |
1756 | {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1757 | {"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, |
1758 | {"sq", "t,o(b)", 0x7c000000, 0xfc000000, RD_1|RD_3|SM, 0, MMI, 0, 0 }, | |
e7ae278d | 1759 | {"sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, |
14daeee3 RS |
1760 | {"sqc2", "+7,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, EE, 0, 0 }, |
1761 | {"sqc2", "+7,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, | |
fc76e730 RS |
1762 | {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_1|RD_2|FP_D, 0, I2, 0, SF }, |
1763 | {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, | |
1764 | {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, | |
1765 | {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
1766 | {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srav */ | |
1767 | {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, | |
1768 | {"sra", "D,S,T", 0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1769 | {"sra", "D,S,T", 0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1770 | {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1771 | {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
1772 | {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srlv */ | |
1773 | {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, | |
1774 | {"srl", "D,S,T", 0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1775 | {"srl", "D,S,T", 0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1776 | {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1777 | {"srl.ob", "D,S,Q", 0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1778 | {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
4372b673 | 1779 | /* ssnop is at the start of the table. */ |
e7ae278d | 1780 | {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 }, |
fc76e730 | 1781 | {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, |
e7ae278d | 1782 | {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1783 | {"sub", "D,S,T", 0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, |
1784 | {"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
1785 | {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, | |
1786 | {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, | |
1787 | {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1788 | {"sub.ob", "D,S,Q", 0x4800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1789 | {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, 0 }, | |
1790 | {"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
1791 | {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1792 | {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
1793 | {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
1794 | {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
1795 | {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
1796 | {"suba.s", "S,T", 0x46000019, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, | |
1797 | {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
e7ae278d | 1798 | {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1799 | {"subu", "D,S,T", 0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, |
1800 | {"subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, | |
e7ae278d | 1801 | {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 }, |
fc76e730 RS |
1802 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, 0}, |
1803 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, | |
e7ae278d | 1804 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1805 | {"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, |
1806 | {"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, | |
1807 | {"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, | |
1808 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
e7ae278d | 1809 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
fc76e730 RS |
1810 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, |
1811 | {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, | |
e7ae278d RS |
1812 | {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, |
1813 | {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
fc76e730 | 1814 | {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ |
e7ae278d | 1815 | {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, |
fc76e730 | 1816 | {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1817 | {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1818 | {"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
e7ae278d | 1819 | {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
fc76e730 | 1820 | {"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, |
e7ae278d | 1821 | {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1822 | {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, 0 }, /* same */ |
e7ae278d | 1823 | {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as swl */ |
fc76e730 | 1824 | {"swr", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, |
e7ae278d | 1825 | {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 | 1826 | {"invalidate", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, 0 }, /* same */ |
e7ae278d | 1827 | {"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as swr */ |
fc76e730 | 1828 | {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I4_33, 0, 0 }, |
e7ae278d RS |
1829 | {"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, |
1830 | {"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, | |
1831 | {"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, | |
1832 | {"syncws", "", 0x0000014f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, | |
1833 | {"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1834 | {"sync_mb", "", 0x0000040f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1835 | {"sync_release", "", 0x0000048f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1836 | {"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1837 | {"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, 0, I33, 0, 0 }, | |
1838 | {"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1, 0, 0 }, | |
1839 | {"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32, 0, 0 }, | |
1840 | {"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2, 0, 0 }, | |
1841 | {"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2, 0, 0 }, | |
fc76e730 | 1842 | {"synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, |
e7ae278d RS |
1843 | {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, |
1844 | {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, | |
fc76e730 RS |
1845 | {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, |
1846 | {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1847 | {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1848 | {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* teqi */ | |
e7ae278d | 1849 | {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, |
fc76e730 RS |
1850 | {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, |
1851 | {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1852 | {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1853 | {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tgei */ | |
e7ae278d | 1854 | {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, |
fc76e730 RS |
1855 | {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, |
1856 | {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1857 | {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1858 | {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tgeiu */ | |
e7ae278d RS |
1859 | {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, |
1860 | {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, | |
1861 | {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, | |
1862 | {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1863 | {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1864 | {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1865 | {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, | |
1866 | {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1867 | {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1868 | {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1869 | {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1870 | {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
1871 | {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, | |
fc76e730 RS |
1872 | {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, |
1873 | {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1874 | {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1875 | {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tlti */ | |
e7ae278d | 1876 | {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, |
fc76e730 RS |
1877 | {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, |
1878 | {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1879 | {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1880 | {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tltiu */ | |
e7ae278d | 1881 | {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, |
fc76e730 RS |
1882 | {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, |
1883 | {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1884 | {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, | |
1885 | {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tnei */ | |
e7ae278d | 1886 | {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, |
fc76e730 RS |
1887 | {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, |
1888 | {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, | |
1889 | {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, | |
1890 | {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, | |
e7ae278d | 1891 | {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1, 0, SF }, |
fc76e730 RS |
1892 | {"trunc.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, EE, 0, 0 }, |
1893 | {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, | |
1894 | {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, | |
e7ae278d RS |
1895 | {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE }, |
1896 | {"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1897 | {"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1898 | {"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1899 | {"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1900 | {"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3, 0, 0 }, | |
1901 | {"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
1902 | {"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 }, | |
fc76e730 RS |
1903 | {"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, |
1904 | {"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, | |
1905 | {"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, | |
1906 | {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_1|FP_D, WR_MACC, SB1, MX, 0 }, | |
1907 | {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_1|FP_D, WR_MACC, N54, 0, 0 }, | |
1908 | {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_1|FP_D, WR_MACC, 0, MX, 0 }, | |
1909 | {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, | |
1910 | {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, | |
1911 | {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, | |
e7ae278d RS |
1912 | {"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32, 0, 0 }, |
1913 | {"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55, 0, 0 }, | |
1914 | {"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1, 0, 0 }, | |
fc76e730 RS |
1915 | {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_2, 0, I33, 0, 0 }, |
1916 | {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, | |
1917 | {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, | |
e7ae278d | 1918 | {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, |
fc76e730 RS |
1919 | {"xor", "D,S,T", 0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
1920 | {"xor", "D,S,T", 0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
1921 | {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | |
1922 | {"xor.ob", "D,S,Q", 0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | |
1923 | {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | |
1924 | {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, | |
1925 | {"yield", "s", 0x7c000009, 0xfc1fffff, RD_1|NODS, 0, 0, MT32, 0 }, | |
1926 | {"yield", "d,s", 0x7c000009, 0xfc1f07ff, WR_1|RD_2|NODS, 0, 0, MT32, 0 }, | |
1927 | {"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, | |
1928 | {"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, | |
deec1734 | 1929 | |
9bcd4f99 | 1930 | /* User Defined Instruction. */ |
fc76e730 RS |
1931 | {"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, |
1932 | {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1933 | {"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1934 | {"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1935 | {"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1936 | {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1937 | {"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1938 | {"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1939 | {"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1940 | {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1941 | {"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1942 | {"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1943 | {"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1944 | {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1945 | {"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1946 | {"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1947 | {"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1948 | {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1949 | {"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1950 | {"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1951 | {"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1952 | {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1953 | {"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1954 | {"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1955 | {"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1956 | {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1957 | {"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1958 | {"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1959 | {"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1960 | {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1961 | {"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1962 | {"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1963 | {"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1964 | {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1965 | {"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1966 | {"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1967 | {"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1968 | {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1969 | {"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1970 | {"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1971 | {"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1972 | {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1973 | {"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1974 | {"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1975 | {"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1976 | {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1977 | {"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1978 | {"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1979 | {"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1980 | {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1981 | {"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1982 | {"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1983 | {"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1984 | {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1985 | {"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1986 | {"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1987 | {"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1988 | {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1989 | {"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1990 | {"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1991 | {"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1992 | {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1993 | {"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
1994 | {"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, | |
9bcd4f99 | 1995 | |
6f14957b MR |
1996 | /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format |
1997 | instructions so they are here for the latters to take precedence. */ | |
fc76e730 RS |
1998 | {"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
1999 | {"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
2000 | {"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
2001 | {"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
2002 | {"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2003 | {"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
2004 | {"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
2005 | {"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
14daeee3 RS |
2006 | {"cfc2", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
2007 | {"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 }, | |
2008 | {"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 }, | |
2009 | {"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 }, | |
2010 | {"ctc2", "t,G", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2011 | {"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 }, | |
2012 | {"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 }, | |
2013 | {"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 }, | |
fc76e730 RS |
2014 | {"dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LCD, 0, IOCT, 0, 0 }, |
2015 | {"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
2016 | {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LCD, 0, I64, 0, IOCT|IOCTP|IOCT2 }, | |
2017 | {"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|COD, 0, IOCT, 0, 0 }, | |
2018 | {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
2019 | {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD, 0, I64, 0, IOCT|IOCTP|IOCT2 }, | |
2020 | {"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2021 | {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, WR_1|RD_C2|LCD, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
2022 | {"mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
2023 | {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LCD, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
2024 | {"mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LCD, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
2025 | {"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2026 | {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD, 0, I32, 0, IOCT|IOCTP|IOCT2 }, | |
2027 | {"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
2028 | {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
2029 | {"mthc2", "t,i", 0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|COD, 0, I33, 0, IOCT|IOCTP|IOCT2 }, | |
14daeee3 RS |
2030 | {"qmfc2", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, |
2031 | {"qmfc2.i", "t,+6", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, | |
2032 | {"qmfc2.ni", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, | |
2033 | {"qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, | |
2034 | {"qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, | |
2035 | {"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, | |
39a7806d TS |
2036 | /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X |
2037 | instructions, so they are here for the latters to take precedence. */ | |
fc76e730 RS |
2038 | {"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, |
2039 | {"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE }, | |
2040 | {"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2041 | {"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE }, | |
2042 | {"cfc3", "t,G", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2043 | {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2044 | {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
2045 | {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, | |
2046 | {"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2047 | {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LCD, 0, I32, 0, IOCT|IOCTP|IOCT2|EE }, | |
2048 | {"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, | |
2049 | {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|COD, 0, I32, 0, IOCT|IOCTP|IOCT2|EE }, | |
39a7806d | 2050 | |
252b5132 RH |
2051 | /* Conflicts with the 4650's "mul" instruction. Nobody's using the |
2052 | 4010 any more, so move this insn out of the way. If the object | |
2053 | format gave us more info, we could do this right. */ | |
fc76e730 | 2054 | {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_1|RD_2, 0, L1, 0, 0 }, |
fd25c5a9 | 2055 | /* MIPS DSP ASE */ |
fc76e730 RS |
2056 | {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, |
2057 | {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2058 | {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2059 | {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2060 | {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2061 | {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2062 | {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2063 | {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2064 | {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2065 | {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2066 | {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2067 | {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2068 | {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2069 | {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2070 | {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2071 | {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2072 | {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2073 | {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
e7ae278d RS |
2074 | {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 }, |
2075 | {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 }, | |
fc76e730 RS |
2076 | {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, |
2077 | {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2078 | {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2079 | {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2080 | {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2081 | {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2082 | {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2083 | {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2084 | {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2085 | {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, | |
2086 | {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2087 | {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2088 | {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, | |
2089 | {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2090 | {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2091 | {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2092 | {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, | |
2093 | {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2094 | {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, | |
2095 | {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, | |
2096 | {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, | |
2097 | {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_1|RD_a|DSP_VOLA, 0, 0, D64, 0 }, | |
2098 | {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D64, 0 }, | |
2099 | {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2100 | {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2101 | {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2102 | {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2103 | {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2104 | {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2105 | {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2106 | {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2107 | {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2108 | {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2109 | {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2110 | {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2111 | {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2112 | {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2113 | {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, | |
2114 | {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, | |
2115 | {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2116 | {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2117 | {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2118 | {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2119 | {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2120 | {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_1|MOD_a|DSP_VOLA, 0, 0, D64, 0 }, | |
2121 | {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2122 | {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2123 | {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2124 | {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2125 | {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2126 | {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2127 | {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2128 | {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2129 | {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2130 | {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2131 | {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2132 | {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2133 | {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2134 | {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2135 | {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2136 | {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
e7ae278d | 2137 | {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, 0, D64, 0 }, |
fc76e730 RS |
2138 | {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, RD_2|MOD_a, 0, 0, D64, 0 }, |
2139 | {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_1|RD_a|DSP_VOLA, 0, 0, D32, 0 }, | |
2140 | {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D32, 0 }, | |
2141 | {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, | |
2142 | {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, | |
2143 | {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, | |
2144 | {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, | |
2145 | {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, | |
2146 | {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, | |
2147 | {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, | |
2148 | {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, | |
2149 | {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, | |
2150 | {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, | |
2151 | {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, | |
432233b3 | 2152 | /* lbux, ldx, lhx and lwx are the basic instruction section. */ |
fc76e730 RS |
2153 | {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, |
2154 | {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2155 | {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2156 | {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2157 | {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2158 | {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2159 | {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2160 | {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2161 | {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2162 | {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2163 | {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2164 | {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2165 | {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2166 | {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2167 | {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2168 | {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_1|MOD_a|DSP_VOLA, 0, 0, D32, 0 }, | |
2169 | {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, | |
2170 | {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, | |
2171 | {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, | |
2172 | {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, | |
2173 | {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, | |
2174 | {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, | |
2175 | {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, | |
2176 | {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, | |
2177 | {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, | |
2178 | {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, | |
2179 | {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2180 | {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, | |
2181 | {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, | |
2182 | {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2183 | {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2184 | {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2185 | {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2186 | {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2187 | {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2188 | {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2189 | {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2190 | {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2191 | {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2192 | {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2193 | {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2194 | {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2195 | {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2196 | {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2197 | {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2198 | {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2199 | {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2200 | {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2201 | {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2202 | {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2203 | {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2204 | {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2205 | {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2206 | {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2207 | {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2208 | {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2209 | {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2210 | {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2211 | {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2212 | {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2213 | {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2214 | {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2215 | {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2216 | {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2217 | {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2218 | {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2219 | {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2220 | {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2221 | {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2222 | {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2223 | {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2224 | {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_1, 0, 0, D32, 0 }, | |
2225 | {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_1, 0, 0, D32, 0 }, | |
2226 | {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_1, 0, 0, D64, 0 }, | |
2227 | {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_1, 0, 0, D32, 0 }, | |
2228 | {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_1, 0, 0, D64, 0 }, | |
2229 | {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_1, 0, 0, D32, 0 }, | |
2230 | {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_1, 0, 0, D64, 0 }, | |
2231 | {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2232 | {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2233 | {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2234 | {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2235 | {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
e7ae278d | 2236 | {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, 0, D32, 0 }, |
fc76e730 RS |
2237 | {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, RD_2|MOD_a, 0, 0, D32, 0 }, |
2238 | {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2239 | {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2240 | {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2241 | {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2242 | {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2243 | {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2244 | {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2245 | {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2246 | {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2247 | {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2248 | {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2249 | {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2250 | {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2251 | {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2252 | {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2253 | {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2254 | {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2255 | {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2256 | {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2257 | {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2258 | {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2259 | {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2260 | {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2261 | {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2262 | {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2263 | {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2264 | {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2265 | {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2266 | {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2267 | {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2268 | {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2269 | {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2270 | {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_1|RD_2, 0, 0, D64, 0 }, | |
2271 | {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_1|RD_2, 0, 0, D32, 0 }, | |
2272 | {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2273 | {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2274 | {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2275 | {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2276 | {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2277 | {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2278 | {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2279 | {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2280 | {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2281 | {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2282 | {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2283 | {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, | |
2284 | {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, | |
2285 | {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, | |
2286 | {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, | |
8b082fb1 | 2287 | /* MIPS DSP ASE Rev2 */ |
fc76e730 RS |
2288 | {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_1|RD_2, 0, 0, D33, 0 }, |
2289 | {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2290 | {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2291 | {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2292 | {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2293 | {"append", "t,s,h", 0x7c000031, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, | |
e7ae278d | 2294 | {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33, 0 }, |
fc76e730 RS |
2295 | {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, MOD_1|RD_2, 0, 0, D33, 0 }, |
2296 | {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2297 | {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2298 | {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2299 | {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2300 | {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2301 | {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, | |
2302 | {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, | |
2303 | {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, | |
2304 | {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, | |
2305 | {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, | |
2306 | {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2307 | {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2308 | {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, | |
2309 | {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, | |
2310 | {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, | |
2311 | {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_1|RD_2, 0, 0, D33, 0 }, | |
2312 | {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_1|RD_2, 0, 0, D33, 0 }, | |
2313 | {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2314 | {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2315 | {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_1|RD_2, 0, 0, D33, 0 }, | |
2316 | {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2317 | {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2318 | {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2319 | {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2320 | {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2321 | {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2322 | {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2323 | {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2324 | {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2325 | {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2326 | {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2327 | {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2328 | {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, | |
2329 | {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2330 | {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2331 | {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2332 | {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2333 | {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
2334 | {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, | |
61cc0267 | 2335 | /* Move bc0* after mftr and mttr to avoid opcode collision. */ |
fc76e730 RS |
2336 | {"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
2337 | {"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
2338 | {"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2339 | {"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, | |
350cc38d | 2340 | /* ST Microelectronics Loongson-2E and -2F. */ |
fc76e730 RS |
2341 | {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, |
2342 | {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2343 | {"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2344 | {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2345 | {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2346 | {"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2347 | {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2348 | {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2349 | {"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2350 | {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2351 | {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2352 | {"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2353 | {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2354 | {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2355 | {"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2356 | {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2357 | {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2358 | {"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2359 | {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2360 | {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2361 | {"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2362 | {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2363 | {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2364 | {"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2365 | {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2366 | {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2367 | {"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2368 | {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2369 | {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2370 | {"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2371 | {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2372 | {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2373 | {"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2374 | {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, | |
2375 | {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, | |
2376 | {"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 }, | |
2377 | {"packsshb", "D,S,T", 0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2378 | {"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2379 | {"packsswh", "D,S,T", 0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2380 | {"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2381 | {"packushb", "D,S,T", 0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2382 | {"packushb", "D,S,T", 0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2383 | {"paddb", "D,S,T", 0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2384 | {"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2385 | {"paddb", "d,s,t", 0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2386 | {"paddh", "D,S,T", 0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2387 | {"paddh", "d,s,t", 0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2388 | {"paddh", "D,S,T", 0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2389 | {"paddw", "D,S,T", 0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2390 | {"paddw", "D,S,T", 0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2391 | {"paddw", "d,s,t", 0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2392 | {"paddd", "D,S,T", 0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2393 | {"paddd", "D,S,T", 0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2394 | {"paddsb", "D,S,T", 0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2395 | {"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2396 | {"paddsb", "d,s,t", 0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2397 | {"paddsh", "D,S,T", 0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2398 | {"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2399 | {"paddsh", "d,s,t", 0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2400 | {"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2401 | {"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2402 | {"paddush", "D,S,T", 0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2403 | {"paddush", "D,S,T", 0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2404 | {"pandn", "D,S,T", 0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2405 | {"pandn", "D,S,T", 0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2406 | {"pavgb", "D,S,T", 0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2407 | {"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2408 | {"pavgh", "D,S,T", 0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2409 | {"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2410 | {"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2411 | {"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2412 | {"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2413 | {"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2414 | {"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2415 | {"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2416 | {"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2417 | {"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2418 | {"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2419 | {"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2420 | {"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2421 | {"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2422 | {"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2423 | {"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2424 | {"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2425 | {"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2426 | {"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2427 | {"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2428 | {"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2429 | {"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2430 | {"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2431 | {"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2432 | {"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2433 | {"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2434 | {"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2435 | {"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2436 | {"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2437 | {"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2438 | {"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2439 | {"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2440 | {"pminub", "D,S,T", 0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2441 | {"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2442 | {"pmovmskb", "D,S", 0x46a00005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, | |
2443 | {"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2444 | {"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2445 | {"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2446 | {"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2447 | {"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2448 | {"pmullh", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2449 | {"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2450 | {"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2451 | {"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2452 | {"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2453 | {"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2454 | {"biadd", "D,S", 0x46800005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, | |
2455 | {"biadd", "D,S", 0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2456 | {"pshufh", "D,S,T", 0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2457 | {"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2458 | {"psllh", "D,S,T", 0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2459 | {"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2460 | {"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
2461 | {"psllw", "D,S,T", 0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2462 | {"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2463 | {"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
2464 | {"psrah", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2465 | {"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2466 | {"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
2467 | {"psraw", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2468 | {"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2469 | {"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
2470 | {"psrlh", "D,S,T", 0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2471 | {"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2472 | {"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
2473 | {"psrlw", "D,S,T", 0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2474 | {"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2475 | {"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, | |
2476 | {"psubb", "D,S,T", 0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2477 | {"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2478 | {"psubb", "d,s,t", 0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2479 | {"psubh", "D,S,T", 0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2480 | {"psubh", "D,S,T", 0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2481 | {"psubh", "d,s,t", 0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2482 | {"psubw", "D,S,T", 0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2483 | {"psubw", "D,S,T", 0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2484 | {"psubw", "d,s,t", 0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2485 | {"psubd", "D,S,T", 0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2486 | {"psubd", "D,S,T", 0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2487 | {"psubsb", "D,S,T", 0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2488 | {"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2489 | {"psubsb", "d,s,t", 0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2490 | {"psubsh", "D,S,T", 0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2491 | {"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2492 | {"psubsh", "d,s,t", 0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, | |
2493 | {"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2494 | {"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2495 | {"psubush", "D,S,T", 0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2496 | {"psubush", "D,S,T", 0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2497 | {"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2498 | {"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2499 | {"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2500 | {"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2501 | {"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2502 | {"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2503 | {"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2504 | {"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2505 | {"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2506 | {"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2507 | {"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | |
2508 | {"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
2509 | {"sequ", "S,T", 0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, | |
2510 | {"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, | |
7f3c4072 | 2511 | /* MIPS Enhanced VA Scheme */ |
fc76e730 | 2512 | {"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2513 | {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2514 | {"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2515 | {"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2516 | {"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2517 | {"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2518 | {"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2519 | {"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2520 | {"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2521 | {"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2522 | {"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2523 | {"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2524 | {"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2525 | {"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2526 | {"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, |
e7ae278d | 2527 | {"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2528 | {"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, |
e7ae278d | 2529 | {"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2530 | {"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM, 0, 0, EVA, 0 }, |
e7ae278d | 2531 | {"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2532 | {"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, |
e7ae278d | 2533 | {"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2534 | {"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, |
e7ae278d | 2535 | {"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2536 | {"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, |
e7ae278d | 2537 | {"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2538 | {"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, |
e7ae278d | 2539 | {"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2540 | {"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, |
e7ae278d | 2541 | {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, |
fc76e730 | 2542 | {"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, |
e7ae278d | 2543 | {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, |
350cc38d MS |
2544 | /* No hazard protection on coprocessor instructions--they shouldn't |
2545 | change the state of the processor and if they do it's up to the | |
2546 | user to put in nops as necessary. These are at the end so that the | |
2547 | disassembler recognizes more specific versions first. */ | |
e7ae278d RS |
2548 | {"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, |
2549 | {"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1, 0, 0 }, | |
2550 | {"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2551 | {"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2552 | {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2553 | {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, | |
2554 | {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
2555 | {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, | |
b015e599 | 2556 | /* RFE conflicts with the new Virt spec instruction tlbgp. */ |
e7ae278d | 2557 | {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 }, |
252b5132 RH |
2558 | }; |
2559 | ||
2560 | #define MIPS_NUM_OPCODES \ | |
2561 | ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) | |
2562 | const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; | |
2563 | ||
564e8ad9 | 2564 | /* const removed from the following to allow for dynamic extensions to the |
252b5132 RH |
2565 | * built-in instruction set. */ |
2566 | struct mips_opcode *mips_opcodes = | |
2567 | (struct mips_opcode *) mips_builtin_opcodes; | |
2568 | int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; | |
2569 | #undef MIPS_NUM_OPCODES |