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ubsan: or1k: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / mips16-opc.c
CommitLineData
252b5132 1/* mips16-opc.c. Mips16 opcode table.
82704155 2 Copyright (C) 1996-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
9b201bb5
NC		 17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132 24#include "opcode/mips.h"
c3c07478
RS		 25#include "mips-formats.h"
26
27static unsigned char reg_0_map[] = { 0 };
28static unsigned char reg_29_map[] = { 29 };
29static unsigned char reg_31_map[] = { 31 };
30static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
31static unsigned char reg32r_map[] = {
32 0, 8, 16, 24,
33 1, 9, 17, 25,
34 2, 10, 18, 26,
35 3, 11, 19, 27,
36 4, 12, 20, 28,
37 5, 13, 21, 29,
38 6, 14, 22, 30,
39 7, 15, 23, 31
40};
41
42/* Return the meaning of operand character TYPE, or null if it isn't
43 recognized. If the operand is affected by the EXTEND instruction,
44 EXTENDED_P selects between the extended and unextended forms.
45 The extended forms all have an lsb of 0. */
46
47const struct mips_operand *
48decode_mips16_operand (char type, bfd_boolean extended_p)
49{
50 switch (type)
51 {
d8722d76 52 case '.': MAPPED_REG (0, 0, GP, reg_0_map);
25499ac7 53 case '>': HINT (5, 22);
d8722d76 54
5284e471
MR		 55 case '0': HINT (5, 0);
56 case '1': HINT (3, 5);
57 case '2': HINT (3, 8);
58 case '3': HINT (5, 16);
59 case '4': HINT (3, 21);
a4f89915 60 case '6': HINT (6, 5);
25499ac7 61 case '9': SINT (9, 0);
c3c07478 62
25499ac7 63 case 'G': SPECIAL (0, 0, REG28);
c3c07478 64 case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
25499ac7
MR		 65 case 'N': REG (5, 0, COPRO);
66 case 'O': UINT (3, 21);
67 case 'Q': REG (5, 16, HW);
c3c07478
RS		 68 case 'P': SPECIAL (0, 0, PC);
69 case 'R': MAPPED_REG (0, 0, GP, reg_31_map);
70 case 'S': MAPPED_REG (0, 0, GP, reg_29_map);
25499ac7 71 case 'T': HINT (5, 16);
c3c07478
RS		 72 case 'X': REG (5, 0, GP);
73 case 'Y': MAPPED_REG (5, 3, GP, reg32r_map);
74 case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map);
75
76 case 'a': JUMP (26, 0, 2);
25499ac7
MR		 77 case 'b': BIT (5, 22, 0); /* (0 .. 31) */
78 case 'c': MSB (5, 16, 1, TRUE, 32); /* (1 .. 32) */
79 case 'd': MSB (5, 16, 1, FALSE, 32); /* (1 .. 32) */
f17ecb4b 80 case 'e': HINT (11, 0);
c3c07478
RS		 81 case 'i': JALX (26, 0, 2);
82 case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
83 case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
38bf472a
MR		 84 case 'n': INT_BIAS (2, 0, 3, 1, 0, FALSE); /* (1 .. 4) */
85 case 'o': INT_ADJ (5, 16, 31, 4, FALSE); /* (0 .. 31) << 4 */
25499ac7 86 case 'r': MAPPED_REG (3, 16, GP, reg_m16_map);
5284e471 87 case 's': HINT (3, 24);
25499ac7 88 case 'u': HINT (16, 0);
0f35dbc4
RS		 89 case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
90 case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
c3c07478
RS		 91 case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
92 case 'y': MAPPED_REG (3, 5, GP, reg_m16_map);
93 case 'z': MAPPED_REG (3, 2, GP, reg_m16_map);
94 }
95
96 if (extended_p)
97 switch (type)
98 {
bdd15286 99 case '<': UINT (5, 22);
c3c07478
RS		 100 case '[': UINT (6, 0);
101 case ']': UINT (6, 0);
102
c3c07478 103 case '5': SINT (16, 0);
c3c07478
RS		 104 case '8': SINT (16, 0);
105
3ccad066
RS		 106 case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
107 case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
c3c07478
RS		 108 case 'C': SINT (16, 0);
109 case 'D': SINT (16, 0);
3ccad066 110 case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
d8722d76 111 case 'F': SINT (15, 0);
c3c07478
RS		 112 case 'H': SINT (16, 0);
113 case 'K': SINT (16, 0);
114 case 'U': UINT (16, 0);
115 case 'V': SINT (16, 0);
116 case 'W': SINT (16, 0);
117
118 case 'j': SINT (16, 0);
119 case 'k': SINT (16, 0);
120 case 'p': BRANCH (16, 0, 1);
121 case 'q': BRANCH (16, 0, 1);
122 }
123 else
124 switch (type)
125 {
126 case '<': INT_ADJ (3, 2, 8, 0, FALSE);
c3c07478
RS		 127 case '[': INT_ADJ (3, 2, 8, 0, FALSE);
128 case ']': INT_ADJ (3, 8, 8, 0, FALSE);
129
c3c07478 130 case '5': UINT (5, 0);
c3c07478
RS		 131 case '8': UINT (8, 0);
132
3ccad066
RS		 133 case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
134 case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
c3c07478
RS		 135 case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
136 case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
3ccad066 137 case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
d8722d76 138 case 'F': SINT (4, 0);
c3c07478
RS		 139 case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
140 case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
141 case 'U': UINT (8, 0);
142 case 'V': INT_ADJ (8, 0, 255, 2, FALSE); /* (0 .. 255) << 2 */
143 case 'W': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
144
145 case 'j': SINT (5, 0);
146 case 'k': SINT (8, 0);
147 case 'p': BRANCH (8, 0, 1);
148 case 'q': BRANCH (11, 0, 1);
149 }
150 return 0;
151}
252b5132
RH		 152
153/* This is the opcodes table for the mips16 processor. The format of
154 this table is intentionally identical to the one in mips-opc.c.
155 However, the special letters that appear in the argument string are
156 different, and the table uses some different flags. */
157
158/* Use some short hand macros to keep down the length of the lines in
159 the opcodes table. */
160
6e3d1f07
MR		 161#define AL INSN2_ALIAS
162
252b5132 163#define UBD INSN_UNCOND_BRANCH_DELAY
252b5132 164
fc76e730
RS		 165#define WR_1 INSN_WRITE_1
166#define WR_2 INSN_WRITE_2
167#define RD_1 INSN_READ_1
168#define RD_2 INSN_READ_2
169#define RD_3 INSN_READ_3
170#define RD_4 INSN_READ_4
171#define MOD_1 (WR_1|RD_1)
172#define MOD_2 (WR_2|RD_2)
252b5132 173
fc76e730
RS		 174#define RD_T INSN_READ_GPR_24
175#define WR_T INSN_WRITE_GPR_24
176#define WR_31 INSN_WRITE_GPR_31
252b5132 177
25499ac7
MR		 178#define RD_C0 INSN_COP
179#define WR_C0 INSN_COP
180
252b5132
RH		 181#define WR_HI INSN_WRITE_HI
182#define WR_LO INSN_WRITE_LO
183#define RD_HI INSN_READ_HI
184#define RD_LO INSN_READ_LO
185
bcd530a7
RS		 186#define NODS INSN_NO_DELAY_SLOT
187#define TRAP INSN_NO_DELAY_SLOT
252b5132 188
fc76e730
RS		 189#define RD_16 INSN2_READ_GPR_16
190#define RD_SP INSN2_READ_SP
191#define WR_SP INSN2_WRITE_SP
192#define MOD_SP (RD_SP|WR_SP)
26545944
RS		 193#define RD_31 INSN2_READ_GPR_31
194#define RD_PC INSN2_READ_PC
195#define UBR INSN2_UNCOND_BRANCH
196#define CBR INSN2_COND_BRANCH
197
0674ee5d
MR		 198#define SH INSN2_SHORT_ONLY
199
9b3f89ee 200#define I1 INSN_ISA1
252b5132 201#define I3 INSN_ISA3
9b3f89ee
TS		 202#define I32 INSN_ISA32
203#define I64 INSN_ISA64
204#define T3 INSN_3900
38bf472a 205#define IAMR2 INSN_INTERAPTIV_MR2
252b5132 206
25499ac7
MR		 207#define E2 ASE_MIPS16E2
208#define E2MT ASE_MIPS16E2_MT
209
b23da31b
NC		 210const struct mips_opcode mips16_opcodes[] =
211{
343fa690 212/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
6e3d1f07
MR		 213{"nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */
214{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
a8d92fc6 215{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 216{"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
fc76e730 217{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 218{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
219{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730 220{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
25499ac7 221{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
fc76e730 222{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
25499ac7
MR		 223{"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
224{"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
0674ee5d 225{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
d8722d76 226{"addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
fc76e730 227{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 228{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
229{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730 230{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
25499ac7 231{"addu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
fc76e730 232{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
25499ac7
MR		 233{"addu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
234{"addu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
0674ee5d 235{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
25499ac7 236{"andi", "x,u", 0xf0006860, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
26545944 237{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
a8d92fc6
RS		 238{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
239{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 240{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
a8d92fc6
RS		 241{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
242{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
243{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
244{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
245{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
246{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
247{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
248{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
249{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
250{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
251{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
252{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
253{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
254{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
255{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
256{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
257{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
258{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 259{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
a4f89915 260{"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
0674ee5d 261{"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
26545944
RS		 262{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
263{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
25499ac7 264{"cache", "T,9(x)", 0xf000d0a0, 0xfe00f8e0, RD_3, 0, 0, E2, 0 },
fc76e730 265{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 266{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730 267{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
6e3d1f07 268{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
d8722d76 269{"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
fc76e730 270{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 271{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
272{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 273{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
274{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
0674ee5d 275{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
d8722d76 276{"daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
fc76e730 277{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 278{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
279{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 280{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
281{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
d8722d76 282{"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 283{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 284{"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 285{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
25499ac7
MR		 286{"di", "", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
287{"di", ".", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
288{"di", "y", 0xf002670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 },
d8722d76 289{"div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 290{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 291{"divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6
RS		 292{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
293{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d
MR		 294{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
295{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
d8722d76 296{"drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 297{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 298{"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 299{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d 300{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 301{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
0674ee5d
MR		 302{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
303{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 304{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
0674ee5d
MR		 305{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
306{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 307{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
0674ee5d
MR		 308{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
309{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
4ebce1a0
MR		 310{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
311{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 },
25499ac7
MR		 312{"ehb", "", 0xf0c03010, 0xffffffff, 0, 0, 0, E2, 0 },
313{"ei", "", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
314{"ei", ".", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
315{"ei", "y", 0xf003670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 },
0674ee5d
MR		 316{"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
317{"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
318{"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
319{"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
320{"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
321{"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
25499ac7
MR		 322{"ext", "y,x,b,d", 0xf0203008, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 },
323{"ins", "y,.,b,c", 0xf0003004, 0xf820ff1f, WR_1, 0, 0, E2, 0 },
324{"ins", "y,x,b,c", 0xf0203004, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 },
0674ee5d
MR		 325{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
326{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
327{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
328{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
7fd53920
MR		 329{"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
330{"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
0674ee5d
MR		 331{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
332{"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
333{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
334{"j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
63e014fc
MR		 335/* MIPS16e compact jumps. We keep them near the ordinary jumps
336 so that we easily find them when converting a normal jump
337 to a compact one. */
0674ee5d
MR		 338{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 },
339{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 },
340{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 },
341{"jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 },
fc76e730 342{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
25499ac7 343{"lb", "x,V(G)", 0xf0009060, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
fc76e730 344{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
25499ac7 345{"lbu", "x,V(G)", 0xf00090a0, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
fc76e730 346{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
6e3d1f07 347{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
fc76e730
RS		 348{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
349{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
350{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
25499ac7 351{"lh", "x,V(G)", 0xf0009040, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
fc76e730 352{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
25499ac7
MR		 353{"lhu", "x,V(G)", 0xf0009080, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
354{"li", "x,U", 0x6800, 0xf800, WR_1, SH, 0, E2, 0 },
fc76e730 355{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
25499ac7
MR		 356{"li", "x,U", 0xf0006800, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
357{"ll", "x,9(r)", 0xf00090c0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
358{"lui", "x,u", 0xf0006820, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
fc76e730 359{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
6e3d1f07 360{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
fc76e730 361{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
25499ac7 362{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
fc76e730 363{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
25499ac7
MR		 364{"lw", "x,V(S)", 0xf0009000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
365{"lw", "x,V(G)", 0xf0009020, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
366{"lwl", "x,9(r)", 0xf00090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
367{"lwr", "x,9(r)", 0xf01090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
fc76e730 368{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
25499ac7
MR		 369{"mfc0", "y,N", 0xf0006700, 0xffffff00, WR_1|RD_C0, 0, 0, E2, 0 },
370{"mfc0", "y,N,O", 0xf0006700, 0xff1fff00, WR_1|RD_C0, 0, 0, E2, 0 },
0674ee5d
MR		 371{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 },
372{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 },
373{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
374{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
25499ac7
MR		 375{"movn", "x,.,w", 0xf000300a, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
376{"movn", "x,r,w", 0xf020300a, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
377{"movtn", "x,.", 0xf000301a, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
378{"movtn", "x,r", 0xf020301a, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
379{"movtz", "x,.", 0xf0003016, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
380{"movtz", "x,r", 0xf0203016, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
381{"movz", "x,.,w", 0xf0003006, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
382{"movz", "x,r,w", 0xf0203006, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
383{"mtc0", "y,N", 0xf0016700, 0xffffff00, RD_1|WR_C0, 0, 0, E2, 0 },
384{"mtc0", "y,N,O", 0xf0016700, 0xff1fff00, RD_1|WR_C0, 0, 0, E2, 0 },
a8d92fc6 385{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
0674ee5d
MR		 386{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
387{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
388{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
389{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
390{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
25499ac7
MR		 391{"ori", "x,u", 0xf0006840, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
392{"pause", "", 0xf1403018, 0xffffffff, 0, 0, 0, E2, 0 },
393{"pref", "T,9(x)", 0xf000d080, 0xfe00f8e0, RD_3, 0, 0, E2, 0 },
394{"rdhwr", "y,Q", 0xf000300c, 0xffe0ff1f, WR_1, 0, 0, E2, 0 },
d8722d76 395{"rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 396{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 397{"remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 398{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 399{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
25499ac7
MR		 400{"sb", "x,V(G)", 0xf000d060, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
401{"sc", "x,9(r)", 0xf000d0c0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
fc76e730 402{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
353abf7c 403{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
c97dda72 404{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
fc76e730 405{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
25499ac7 406{"sh", "x,V(G)", 0xf000d040, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
0674ee5d 407{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
25499ac7 408{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, SH, 0, E2, 0 },
fc76e730 409{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
25499ac7 410{"sll", "x,w,<", 0xf0003000, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 },
0674ee5d 411{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 412{"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 413{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730
RS		 414{"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
415{"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 416{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730 417{"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 418{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 419{"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
0674ee5d
MR		 420{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
421{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
25499ac7 422{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, SH, 0, E2, 0 },
fc76e730 423{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
25499ac7 424{"srl", "x,w,<", 0xf0003002, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 },
0674ee5d
MR		 425{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
426{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
a8d92fc6
RS		 427{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
428{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 429{"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
25499ac7 430{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, SH|RD_SP, 0, E2, 0 },
fc76e730 431{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
25499ac7 432{"sw", "x,V(S)", 0xf000d000, 0xf800f8e0, RD_1, RD_SP, 0, E2, 0 },
fc76e730 433{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
25499ac7
MR		 434{"sw", "x,V(G)", 0xf000d020, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
435{"swl", "x,9(r)", 0xf000d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
436{"swr", "x,9(r)", 0xf010d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
437{"sync_acquire", "", 0xf4403014, 0xffffffff, 0, AL, 0, E2, 0 },
438{"sync_mb", "", 0xf4003014, 0xffffffff, 0, AL, 0, E2, 0 },
439{"sync_release", "", 0xf4803014, 0xffffffff, 0, AL, 0, E2, 0 },
440{"sync_rmb", "", 0xf4c03014, 0xffffffff, 0, AL, 0, E2, 0 },
441{"sync_wmb", "", 0xf1003014, 0xffffffff, 0, AL, 0, E2, 0 },
442{"sync", "", 0xf0003014, 0xffffffff, 0, 0, 0, E2, 0 },
443{"sync", ">", 0xf0003014, 0xf83fffff, 0, 0, 0, E2, 0 },
0674ee5d 444{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
25499ac7 445{"xori", "x,u", 0xf0006880, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
63e014fc 446 /* MIPS16e additions; see above for compact jumps. */
75f31665 447{"restore", "m", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
fc76e730 448{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
a4f89915 449{"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 },
0674ee5d
MR		 450{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 },
451{"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 },
452{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 },
453{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 },
454{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 },
455{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 },
456{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
25499ac7
MR		 457 /* MIPS16e2 MT ASE instructions. */
458{"dmt", "", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
459{"dmt", ".", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
460{"dmt", "y", 0xf0226701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
461{"dvpe", "", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
462{"dvpe", ".", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
463{"dvpe", "y", 0xf0226700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
464{"emt", "", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
465{"emt", ".", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
466{"emt", "y", 0xf0236701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
467{"evpe", "", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
468{"evpe", ".", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
469{"evpe", "y", 0xf0236700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
38bf472a
MR		 470 /* interAptiv MR2 instruction extensions. */
471{"copyw", "x,y,o,n", 0xf020e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 },
472{"ucopyw", "x,y,o,n", 0xf000e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 },
5284e471
MR		 473 /* Place asmacro at the bottom so that it catches any implementation
474 specific macros that didn't match anything. */
475{"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 },
7fd53920
MR		 476 /* Place EXTEND last so that it catches any prefix that didn't match
477 anything. */
0674ee5d 478{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 },
252b5132
RH		 479};
480
481const int bfd_mips16_num_opcodes =
482 ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
GDB Binutils - Deliverables
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