[deliverable/binutils-gdb.git] / opcodes / mn10300-opc.c

/* Assemble Matsushita MN10300 instructions.
   Copyright (C) 1996 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "ansidecl.h"
#include "opcode/mn10300.h"

\f
const struct mn10300_operand mn10300_operands[] = {
#define UNUSED	0
  {0, 0, 0}, 

#define DN0      (UNUSED+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DN1      (DN0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define DN2      (DN1+1)
  {2, 4, MN10300_OPERAND_DREG},

#define DM0      (DN2+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DM1      (DM0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define DM2      (DM1+1)
  {2, 4, MN10300_OPERAND_DREG},

#define AN0      (DM2+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AN1      (AN0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define AN2      (AN1+1)
  {2, 4, MN10300_OPERAND_AREG},

#define AM0      (AN2+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AM1      (AM0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define AM2      (AM1+1)
  {2, 4, MN10300_OPERAND_AREG},

#define IMM8    (AM2+1)
  {8, 0, MN10300_OPERAND_PROMOTE},

#define IMM16    (IMM8+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

/* 32bit immediate, high 16 bits in the main instruction
   word, 16bits in the extension word. 

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32    (IMM16+1)
  {16, 0, MN10300_OPERAND_SPLIT},

/* 32bit immediate, high 16 bits in the main instruction
   word, 16bits in the extension word, low 16bits are left
   shifted 8 places. 

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32_LOWSHIFT8    (IMM32+1)
  {16, 8, MN10300_OPERAND_SPLIT},

/* 32bit immediate, high 24 bits in the main instruction
   word, 8 in the extension word.

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
  {24, 0, MN10300_OPERAND_SPLIT},

/* 32bit immediate, high 24 bits in the main instruction
   word, 8 in the extension word, low 8 bits are left
   shifted 16 places. 

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
  {24, 16, MN10300_OPERAND_SPLIT},

#define SP    (IMM32_HIGH24_LOWSHIFT16+1)
  {8, 0, MN10300_OPERAND_SP},

#define PSW    (SP+1)
  {0, 0, MN10300_OPERAND_PSW},

#define MDR    (PSW+1)
  {0, 0, MN10300_OPERAND_MDR},

#define DI (MDR+1)
  {2, 2, MN10300_OPERAND_DREG},

#define SD8    (DI+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD16    (SD8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD8N    (SD16+1)
  {8, 0, MN10300_OPERAND_SIGNED},

#define SD8N_SHIFT8    (SD8N+1)
  {8, 8, MN10300_OPERAND_SIGNED},

#define SIMM8    (SD8N_SHIFT8+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SIMM16    (SIMM8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define PAREN	(SIMM16+1)
  {0, 0, MN10300_OPERAND_PAREN}, 

#define DN01     (PAREN+1)
  {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},

#define AN01     (DN01+1)
  {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},

#define D16_SHIFT (AN01+1)
  {16, 8, MN10300_OPERAND_PROMOTE},

#define IMM8E    (D16_SHIFT+1)
  {8, 0, MN10300_OPERAND_EXTENDED},

#define IMM8E_SHIFT8    (IMM8E+1)
  {8, 8, MN10300_OPERAND_EXTENDED},

#define IMM8_SHIFT8 (IMM8E_SHIFT8 + 1)
  {8, 8, 0},

#define REGS    (IMM8_SHIFT8+1)
  {8, 0, MN10300_OPERAND_REG_LIST},

} ; 

#define MEM(ADDR) PAREN, ADDR, PAREN 
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov",	0x8000,		0xf000,		FMT_S1, {SIMM8, DN01}},
{ "mov",	0x80,		0xf0,		FMT_S0, {DM1, DN0}},
{ "mov",	0xf1e0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "mov",	0xf1d0,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "mov",	0x9000,		0xf000,		FMT_S1, {IMM8, AN01}},
{ "mov",	0x90,		0xf0,		FMT_S0, {AM1, AN0}},
{ "mov",	0x3c,		0xfc,		FMT_S0, {SP, AN0}},
{ "mov",	0xf2f0,		0xfff3,		FMT_D0, {AM1, SP}},
{ "mov",	0xf2e4,		0xfffc,		FMT_D0, {PSW, DN0}},
{ "mov",	0xf2f3,		0xfff3,		FMT_D0, {DM1, PSW}},
{ "mov",	0xf2e0,		0xfffc,		FMT_D0, {MDR, DN0}},
{ "mov",	0xf2f2,		0xfff3,		FMT_D0, {DM1, MDR}},
{ "mov",	0x70,		0xf0,		FMT_S0, {MEM(AM0), DN1}},
{ "mov",	0xf80000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "mov",	0xfa000000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "mov",	0xfc000000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "mov",	0x5800,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), DN0}},
{ "mov",	0xfab40000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "mov",	0xfcb40000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "mov",	0xf300,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "mov",	0x300000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
{ "mov",	0xfca40000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
{ "mov",	0xf000,		0xfff0,		FMT_D0, {MEM(AM0), AN1}},
{ "mov",	0xf82000,	0xfff000,	FMT_D1, {MEM2(SD8,AM0), AN1}},
{ "mov",	0xfa200000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), AN1}},
{ "mov",	0xfc200000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), AN1}},
{ "mov",	0x5c00,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), AN0}},
{ "mov",	0xfab00000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), AN0}},
{ "mov",	0xfcb00000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), AN0}},
{ "mov",	0xf380,		0xffc0,		FMT_D0, {MEM2(DI, AM0), AN2}},
{ "mov",	0xfaa00000,	0xfffc0000,	FMT_D2, {MEM(IMM16), AN0}},
{ "mov",	0xfca00000,	0xfffc0000,	FMT_D4, {MEM(IMM32), AN0}},
{ "mov",	0xf8f000,	0xfffc00,	FMT_D1, {MEM2(SD8N, AM0), SP}},
{ "mov",	0x60,		0xf0,		FMT_S0, {DM1, MEM(AN0)}},
{ "mov",	0xf81000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa100000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc100000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "mov",	0x4200,		0xf300,		FMT_S1, {DM1, MEM2(IMM8, SP)}},
{ "mov",	0xfa910000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "mov",	0xfc910000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "mov",	0xf340,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "mov",	0x010000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
{ "mov",	0xfc810000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},
{ "mov",	0xf010,		0xfff0,		FMT_D0, {AM1, MEM(AN0)}},
{ "mov",	0xf83000,	0xfff000,	FMT_D1, {AM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa300000,	0xfff00000,	FMT_D2, {AM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc300000,	0xfff00000,	FMT_D4, {AM1, MEM2(IMM32,AN0)}},
{ "mov",	0x4300,		0xf300,		FMT_S1, {AM1, MEM2(IMM8, SP)}},
{ "mov",	0xfa900000,	0xfff30000,	FMT_D2, {AM1, MEM2(IMM16, SP)}},
{ "mov",	0xfc900000,	0xfc930000,	FMT_D4, {AM1, MEM2(IMM32, SP)}},
{ "mov",	0xf3c0,		0xffc0,		FMT_D0, {AM2, MEM2(DI, AN0)}},
{ "mov",	0xfa800000,	0xfff30000,	FMT_D2, {AM1, MEM(IMM16)}},
{ "mov",	0xfc800000,	0xfff30000,	FMT_D4, {AM1, MEM(IMM32)}},
{ "mov",	0xf8f400,	0xfffc00,	FMT_D1, {SP, MEM2(SD8N, AN0)}},
{ "mov",	0x2c0000,	0xfc0000,	FMT_S2, {SIMM16, DN0}},
{ "mov",	0xfccc0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mov",	0x240000,	0xfc0000,	FMT_S2, {IMM16, AN0}},
{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "movbu",	0xf040,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movbu",	0xf84000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movbu",	0xfa400000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movbu",	0xfc400000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "movbu",	0xf8b800,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
{ "movbu",	0xfab80000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "movbu",	0xfcb80000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "movbu",	0xf400,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "movbu",	0x340000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
{ "movbu",	0xfca80000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
{ "movbu",	0xf050,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movbu",	0xf85000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movbu",	0xfa500000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movbu",	0xfc500000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "movbu",	0xf89200,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
{ "movbu",	0xfa920000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "movbu",	0xfc920000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "movbu",	0xf440,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "movbu",	0x020000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
{ "movbu",	0xfc820000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},

{ "movhu",	0xf060,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movhu",	0xf86000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movhu",	0xfa600000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movhu",	0xfc600000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "movhu",	0xf8bc00,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
{ "movhu",	0xfabc0000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "movhu",	0xfcbc0000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "movhu",	0xf480,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "movhu",	0x380000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
{ "movhu",	0xfcac0000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
{ "movhu",	0xf070,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movhu",	0xf87000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movhu",	0xfa700000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movhu",	0xfc700000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "movhu",	0xf89300,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
{ "movhu",	0xfa930000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "movhu",	0xfc930000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "movhu",	0xf4c0,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "movhu",	0x030000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
{ "movhu",	0xfc830000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},

{ "ext",	0xf2d0,		0xfffc,		FMT_D0, {DN0}},
{ "extb",	0x10, 		0xfc,		FMT_S0, {DN0}},
{ "extbu",	0x14,		0xfc,		FMT_S0, {DN0}},
{ "exth",	0x18,		0xfc,		FMT_S0, {DN0}},
{ "exthu",	0x1c,		0xfc,		FMT_S0, {DN0}},

{ "movm",	0xce00,		0xff00,		FMT_S1, {MEM(SP), REGS}},
{ "movm",	0xcf00,		0xff00,		FMT_S1, {REGS, MEM(SP)}},

{ "clr",	0x00,		0xf3,		FMT_S0, {DN1}},

{ "add",	0xe0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "add",	0xf160,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "add",	0xf150,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "add",	0xf170,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "add",	0x2800,		0xfc00,		FMT_S1, {SIMM8, DN0}},
{ "add",	0xfac00000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "add",	0xfcc00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "add",	0x2000,		0xfc00,		FMT_S1, {SIMM8, AN0}},
{ "add",	0xfad00000,	0xfffc0000,	FMT_D2, {SIMM16, AN0}},
{ "add",	0xfcd00000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "add",	0xf8fe00,	0xffff00,	FMT_D1, {SIMM8, SP}},
{ "add",	0xfafe0000,	0xffff0000,	FMT_D2, {SIMM16, SP}},
{ "add",	0xfcfe0000,	0xffff0000,	FMT_D4, {IMM32, SP}},
{ "addc",	0xf140,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "sub",	0xf100,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sub",	0xf120,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "sub",	0xf110,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "sub",	0xf130,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "sub",	0xfcc40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sub",	0xfcd40000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "subc",	0xf180,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "mul",	0xf240,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulu",	0xf250,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "div",	0xf260,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "divu",	0xf270,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "inc",	0x40,		0xf3,		FMT_S0, {DN1}},
{ "inc",	0x41,		0xf3,		FMT_S0, {AN1}},
{ "inc4",	0x50,		0xfc,		FMT_S0, {AN0}},

{ "cmp",	0xa000,		0xf000,		FMT_S1, {SIMM8, DN01}},
{ "cmp",	0xa0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "cmp",	0xf1a0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "cmp",	0xf190,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "cmp",	0xb000,		0xf000,		FMT_S1, {IMM8, AN01}},
{ "cmp",	0xb0,		0xf0,		FMT_S0, {AM1, AN0}},
{ "cmp",	0xfac80000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "cmp",	0xfcc80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "cmp",	0xfad80000,	0xfffc0000,	FMT_D2, {IMM16, AN0}},
{ "cmp",	0xfcd80000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "and",	0xf200,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "and",	0xf8e000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "and",	0xfae00000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "and",	0xfce00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "and",	0xfafc0000,	0xffff0000,	FMT_D2, {IMM16, PSW}},
{ "or",		0xf210,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "or",		0xf8e400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "or",		0xfae40000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "or",		0xfce40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "or",		0xfafd0000,	0xffff0000,	FMT_D2, {IMM16, PSW}},
{ "xor",	0xf220,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "xor",	0xfae80000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "xor",	0xfce80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "not",	0xf230,		0xfffc,		FMT_D0, {DN0}},

{ "btst",	0xf8ec00,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "btst",	0xfaec0000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "btst",	0xfcec0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "btst",	0xfe020000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "btst",	0xfaf80000,	0xfffc0000,	FMT_D2,
					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bset",	0xf080,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bset",	0xfe000000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "bset",	0xfaf00000,	0xfffc0000,	FMT_D2,
					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bclr",	0xf090,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bclr",	0xfe010000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "bclr",	0xfaf40000,	0xfffc0000,	FMT_D2, {IMM8,
						MEM2(SD8N_SHIFT8,AN0)}},

{ "asr",	0xf2b0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asr",	0xf8c800,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "lsr",	0xf2a0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "lsr",	0xf8c400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl",	0xf290,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asl",	0xf8c000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl2",	0x54,		0xfc,		FMT_S0, {DN0}},
{ "ror",	0xf284,		0xfffc,		FMT_D0, {DN0}},
{ "rol",	0xf280,		0xfffc,		FMT_D0, {DN0}},

{ "beq",	0xc800,		0xff00,		FMT_S1, {SD8N}},
{ "bne",	0xc900,		0xff00,		FMT_S1, {SD8N}},
{ "bgt",	0xc100,		0xff00,		FMT_S1, {SD8N}},
{ "bge",	0xc200,		0xff00,		FMT_S1, {SD8N}},
{ "ble",	0xc300,		0xff00,		FMT_S1, {SD8N}},
{ "blt",	0xc000,		0xff00,		FMT_S1, {SD8N}},
{ "bhi",	0xc500,		0xff00,		FMT_S1, {SD8N}},
{ "bcc",	0xc600,		0xff00,		FMT_S1, {SD8N}},
{ "bls",	0xc700,		0xff00,		FMT_S1, {SD8N}},
{ "bcs",	0xc400,		0xff00,		FMT_S1, {SD8N}},
{ "bvc",	0xf8e800,	0xffff00,	FMT_D1, {SD8N}},
{ "bvs",	0xf8e900,	0xffff00,	FMT_D1, {SD8N}},
{ "bnc",	0xf8ea00,	0xffff00,	FMT_D1, {SD8N}},
{ "bns",	0xf8eb00,	0xffff00,	FMT_D1, {SD8N}},
{ "bra",	0xca00,		0xff00,		FMT_S1, {SD8N}},

{ "leq",	0xd8,		0xff,		FMT_S0, {UNUSED}},
{ "lne",	0xd9,		0xff,		FMT_S0, {UNUSED}},
{ "lgt",	0xd1,		0xff,		FMT_S0, {UNUSED}},
{ "lge",	0xd2,		0xff,		FMT_S0, {UNUSED}},
{ "lle",	0xd3,		0xff,		FMT_S0, {UNUSED}},
{ "llt",	0xd0,		0xff,		FMT_S0, {UNUSED}},
{ "lhi",	0xd5,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "lls",	0xd7,		0xff,		FMT_S0, {UNUSED}},
{ "lcs",	0xd4,		0xff,		FMT_S0, {UNUSED}},
{ "lra",	0xda,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "setlb",	0xdb,		0xff,	 	FMT_S0, {UNUSED}},

{ "jmp",	0xf0f4,		0xfffc,		FMT_D0, {PAREN,AN0,PAREN}},
{ "jmp",	0xcc0000,	0xff0000,	FMT_S2, {IMM16}},
{ "jmp",	0xdc000000,	0xff000000,	FMT_S4, {IMM32_HIGH24}},
{ "call",	0xcd000000,	0xff000000,	FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
{ "call",	0xdd000000,	0xff000000,	FMT_S6,
					{IMM32_HIGH24_LOWSHIFT16,IMM8E_SHIFT8,IMM8E}},
{ "calls",	0xf0f0,		0xfffc,		FMT_D0, {PAREN,AN0,PAREN}},
{ "calls",	0xfaff0000,	0xffff0000,	FMT_D2, {IMM16}},
{ "calls",	0xfcff0000,	0xffff0000,	FMT_D4, {IMM32}},

{ "ret",	0xdf0000,	0xff0000,	FMT_S2, {IMM8_SHIFT8, IMM8}},
{ "retf",	0xde0000,	0xff0000,	FMT_S2, {IMM8_SHIFT8, IMM8}},
{ "rets",	0xf0fc,		0xffff,		FMT_D0, {UNUSED}},
{ "rti",	0xf0fd,		0xffff,		FMT_D0, {UNUSED}},
{ "trap",	0xf0fe,		0xffff,		FMT_D0, {UNUSED}},
{ "rtm",	0xf0ff,		0xffff,		FMT_D0, {UNUSED}},
{ "nop",	0xcb,		0xff,		FMT_S0, {UNUSED}},
/* { "udf", 0, 0, {0}},  */

{ "putx",	0xf500,		0xfff0,		FMT_D0, {DN01}},
{ "getx",	0xf6f0,		0xfff0,		FMT_D0, {DN01}},
{ "mulq",	0xf600,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulq",	0xf90000,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulq",	0xfb000000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulq",	0xfd000000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mulqu",	0xf610,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulqu",	0xf91400,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulqu",	0xfb140000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulqu",	0xfd140000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sat16",	0xf640,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sat24",	0xf650,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "bsch",	0xf670,		0xfff0,		FMT_D0, {DM1, DN0}},
{ 0, 0, 0, 0, {0}},

} ;

const int mn10300_num_opcodes =
  sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);

\f
Commit	Line	Data
ae1b99e4	1	/* Assemble Matsushita MN10300 instructions.
e7c50cef JL	2	Copyright (C) 1996 Free Software Foundation, Inc.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	#include "ansidecl.h"
ae1b99e4	19	#include "opcode/mn10300.h"
e7c50cef JL	20
e7c50cef JL	21	\f
ae1b99e4	22	const struct mn10300_operand mn10300_operands[] = {
e7c50cef	23	#define UNUSED 0
5ab7bce6 JL	24	{0, 0, 0},
5ab7bce6 JL	25
36b34aa4	26	#define DN0 (UNUSED+1)
5ab7bce6 JL	27	{2, 0, MN10300_OPERAND_DREG},
5ab7bce6 JL	28
36b34aa4 JL	29	#define DN1 (DN0+1)
	30	{2, 2, MN10300_OPERAND_DREG},
	31
bb5e141a JL	32	#define DN2 (DN1+1)
	33	{2, 4, MN10300_OPERAND_DREG},
	34
	35	#define DM0 (DN2+1)
5ab7bce6 JL	36	{2, 0, MN10300_OPERAND_DREG},
5ab7bce6 JL	37
36b34aa4 JL	38	#define DM1 (DM0+1)
	39	{2, 2, MN10300_OPERAND_DREG},
	40
bb5e141a JL	41	#define DM2 (DM1+1)
	42	{2, 4, MN10300_OPERAND_DREG},
	43
	44	#define AN0 (DM2+1)
5ab7bce6 JL	45	{2, 0, MN10300_OPERAND_AREG},
5ab7bce6 JL	46
36b34aa4 JL	47	#define AN1 (AN0+1)
	48	{2, 2, MN10300_OPERAND_AREG},
	49
bb5e141a JL	50	#define AN2 (AN1+1)
	51	{2, 4, MN10300_OPERAND_AREG},
	52
	53	#define AM0 (AN2+1)
5ab7bce6 JL	54	{2, 0, MN10300_OPERAND_AREG},
5ab7bce6 JL	55
36b34aa4 JL	56	#define AM1 (AM0+1)
	57	{2, 2, MN10300_OPERAND_AREG},
	58
bb5e141a JL	59	#define AM2 (AM1+1)
	60	{2, 4, MN10300_OPERAND_AREG},
	61
	62	#define IMM8 (AM2+1)
5ab7bce6 JL	63	{8, 0, MN10300_OPERAND_PROMOTE},
	64
	65	#define IMM16 (IMM8+1)
	66	{16, 0, MN10300_OPERAND_PROMOTE},
	67
64ce0668	68	/* 32bit immediate, high 16 bits in the main instruction
26433754 JL	69	word, 16bits in the extension word.
	70
	71	The "bits" field indicates how many bits are in the
	72	main instruction word for MN10300_OPERAND_SPLIT! */
5ab7bce6	73	#define IMM32 (IMM16+1)
26433754	74	{16, 0, MN10300_OPERAND_SPLIT},
5ab7bce6	75
64ce0668 JL	76	/* 32bit immediate, high 16 bits in the main instruction
64ce0668 JL	77	word, 16bits in the extension word, low 16bits are left
26433754 JL	78	shifted 8 places.
	79
	80	The "bits" field indicates how many bits are in the
	81	main instruction word for MN10300_OPERAND_SPLIT! */
64ce0668	82	#define IMM32_LOWSHIFT8 (IMM32+1)
26433754 JL	83	{16, 8, MN10300_OPERAND_SPLIT},
	84
	85	/* 32bit immediate, high 24 bits in the main instruction
	86	word, 8 in the extension word.
	87
	88	The "bits" field indicates how many bits are in the
	89	main instruction word for MN10300_OPERAND_SPLIT! */
	90	#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
	91	{24, 0, MN10300_OPERAND_SPLIT},
64ce0668	92
26433754 JL	93	/* 32bit immediate, high 24 bits in the main instruction
	94	word, 8 in the extension word, low 8 bits are left
	95	shifted 16 places.
	96
	97	The "bits" field indicates how many bits are in the
	98	main instruction word for MN10300_OPERAND_SPLIT! */
	99	#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
	100	{24, 16, MN10300_OPERAND_SPLIT},
	101
	102	#define SP (IMM32_HIGH24_LOWSHIFT16+1)
5ab7bce6 JL	103	{8, 0, MN10300_OPERAND_SP},
	104
	105	#define PSW (SP+1)
	106	{0, 0, MN10300_OPERAND_PSW},
	107
	108	#define MDR (PSW+1)
	109	{0, 0, MN10300_OPERAND_MDR},
	110
fdef41f3	111	#define DI (MDR+1)
bb5e141a	112	{2, 2, MN10300_OPERAND_DREG},
5ab7bce6	113
db229054	114	#define SD8 (DI+1)
5ab7bce6 JL	115	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	116
	117	#define SD16 (SD8+1)
	118	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	119
	120	#define SD8N (SD16+1)
	121	{8, 0, MN10300_OPERAND_SIGNED},
	122
bb5e141a JL	123	#define SD8N_SHIFT8 (SD8N+1)
	124	{8, 8, MN10300_OPERAND_SIGNED},
	125
	126	#define SIMM8 (SD8N_SHIFT8+1)
5ab7bce6 JL	127	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	128
	129	#define SIMM16 (SIMM8+1)
	130	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
db229054 JL	131
	132	#define PAREN (SIMM16+1)
	133	{0, 0, MN10300_OPERAND_PAREN},
e85c140a JL	134
	135	#define DN01 (PAREN+1)
	136	{2, 0, MN10300_OPERAND_DREG \| MN10300_OPERAND_REPEATED},
	137
	138	#define AN01 (DN01+1)
	139	{2, 0, MN10300_OPERAND_AREG \| MN10300_OPERAND_REPEATED},
	140
bb5e141a JL	141	#define D16_SHIFT (AN01+1)
	142	{16, 8, MN10300_OPERAND_PROMOTE},
	143
	144	#define IMM8E (D16_SHIFT+1)
	145	{8, 0, MN10300_OPERAND_EXTENDED},
	146
26433754 JL	147	#define IMM8E_SHIFT8 (IMM8E+1)
	148	{8, 8, MN10300_OPERAND_EXTENDED},
	149
	150	#define IMM8_SHIFT8 (IMM8E_SHIFT8 + 1)
bb5e141a JL	151	{8, 8, 0},
bb5e141a JL	152
99246e03 JL	153	#define REGS (IMM8_SHIFT8+1)
	154	{8, 0, MN10300_OPERAND_REG_LIST},
	155
e7c50cef JL	156	} ;
e7c50cef JL	157
db229054 JL	158	#define MEM(ADDR) PAREN, ADDR, PAREN
db229054 JL	159	#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
e7c50cef JL	160	\f
	161	/* The opcode table.
	162
	163	The format of the opcode table is:
	164
	165	NAME OPCODE MASK { OPERANDS }
	166
	167	NAME is the name of the instruction.
	168	OPCODE is the instruction opcode.
	169	MASK is the opcode mask; this is used to tell the disassembler
	170	which bits in the actual opcode must match OPCODE.
	171	OPERANDS is the list of operands.
	172
	173	The disassembler reads the table in order and prints the first
	174	instruction which matches, so this table is sorted to put more
	175	specific instructions before more general instructions. It is also
	176	sorted by major opcode. */
	177
ae1b99e4	178	const struct mn10300_opcode mn10300_opcodes[] = {
e85c140a	179	{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}},
36b34aa4 JL	180	{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}},
	181	{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}},
	182	{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}},
e85c140a	183	{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN01}},
36b34aa4 JL	184	{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}},
	185	{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}},
	186	{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}},
	187	{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}},
	188	{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}},
	189	{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}},
	190	{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}},
	191	{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}},
	192	{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	193	{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
fdef41f3 JL	194	{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	195	{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(IMM8, SP), DN0}},
	196	{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	197	{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
bb5e141a	198	{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
fdef41f3 JL	199	{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(IMM16), DN0}},
fdef41f3 JL	200	{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(IMM32), DN0}},
36b34aa4	201	{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
fdef41f3 JL	202	{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(SD8,AM0), AN1}},
	203	{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), AN1}},
	204	{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), AN1}},
	205	{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(IMM8, SP), AN0}},
	206	{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), AN0}},
	207	{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), AN0}},
bb5e141a	208	{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}},
fdef41f3 JL	209	{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(IMM16), AN0}},
fdef41f3 JL	210	{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(IMM32), AN0}},
36b34aa4 JL	211	{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
	212	{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}},
	213	{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	214	{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
fdef41f3 JL	215	{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	216	{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(IMM8, SP)}},
	217	{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	218	{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
bb5e141a	219	{ "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
fdef41f3 JL	220	{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(IMM16)}},
fdef41f3 JL	221	{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32)}},
36b34aa4 JL	222	{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
	223	{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}},
	224	{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}},
fdef41f3 JL	225	{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(IMM32,AN0)}},
	226	{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(IMM8, SP)}},
	227	{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(IMM16, SP)}},
	228	{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM1, MEM2(IMM32, SP)}},
bb5e141a	229	{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}},
fdef41f3 JL	230	{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(IMM16)}},
fdef41f3 JL	231	{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(IMM32)}},
36b34aa4 JL	232	{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
36b34aa4 JL	233	{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}},
fdef41f3	234	{ "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
36b34aa4 JL	235	{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}},
	236	{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	237
	238	{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
	239	{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	240	{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
fdef41f3 JL	241	{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	242	{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
	243	{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	244	{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
bb5e141a	245	{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
fdef41f3 JL	246	{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(IMM16), DN0}},
fdef41f3 JL	247	{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(IMM32), DN0}},
36b34aa4 JL	248	{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	249	{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	250	{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
fdef41f3 JL	251	{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	252	{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
	253	{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	254	{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
bb5e141a	255	{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
fdef41f3 JL	256	{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(IMM16)}},
fdef41f3 JL	257	{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32)}},
36b34aa4 JL	258
	259	{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
	260	{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	261	{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
fdef41f3 JL	262	{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	263	{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
	264	{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	265	{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
bb5e141a	266	{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
fdef41f3 JL	267	{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(IMM16), DN0}},
fdef41f3 JL	268	{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(IMM32), DN0}},
36b34aa4 JL	269	{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	270	{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	271	{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
fdef41f3 JL	272	{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	273	{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
	274	{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	275	{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
bb5e141a	276	{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
fdef41f3 JL	277	{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(IMM16)}},
fdef41f3 JL	278	{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32)}},
36b34aa4 JL	279
	280	{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}},
	281	{ "extb", 0x10, 0xfc, FMT_S0, {DN0}},
	282	{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}},
	283	{ "exth", 0x18, 0xfc, FMT_S0, {DN0}},
	284	{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}},
db229054	285
99246e03 JL	286	{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), REGS}},
99246e03 JL	287	{ "movm", 0xcf00, 0xff00, FMT_S1, {REGS, MEM(SP)}},
db229054	288
36b34aa4 JL	289	{ "clr", 0x00, 0xf3, FMT_S0, {DN1}},
	290
	291	{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}},
	292	{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}},
	293	{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}},
	294	{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}},
	295	{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}},
	296	{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	297	{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	298	{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}},
	299	{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}},
	300	{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
db229054	301	{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
4aa92185 JL	302	{ "add", 0xfafe0000, 0xffff0000, FMT_D2, {SIMM16, SP}},
4aa92185 JL	303	{ "add", 0xfcfe0000, 0xffff0000, FMT_D4, {IMM32, SP}},
36b34aa4 JL	304	{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}},
	305
	306	{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}},
	307	{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}},
	308	{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}},
	309	{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}},
	310	{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	311	{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	312	{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}},
	313
	314	{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}},
	315	{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}},
	316
	317	{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}},
	318	{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}},
	319
	320	{ "inc", 0x40, 0xf3, FMT_S0, {DN1}},
	321	{ "inc", 0x41, 0xf3, FMT_S0, {AN1}},
	322	{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}},
	323
e85c140a	324	{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN01}},
36b34aa4 JL	325	{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}},
	326	{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}},
	327	{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}},
e85c140a	328	{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN01}},
36b34aa4 JL	329	{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}},
	330	{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	331	{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	332	{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}},
	333	{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	334
	335	{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}},
	336	{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	337	{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	338	{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
4aa92185	339	{ "and", 0xfafc0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
36b34aa4 JL	340	{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}},
	341	{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}},
	342	{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	343	{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
4aa92185	344	{ "or", 0xfafd0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
36b34aa4 JL	345	{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}},
	346	{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	347	{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	348	{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}},
	349
	350	{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
	351	{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	352	{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
64ce0668 JL	353	{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E,
64ce0668 JL	354	MEM(IMM32_LOWSHIFT8)}},
bb5e141a JL	355	{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
bb5e141a JL	356	{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
36b34aa4	357	{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
64ce0668 JL	358	{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E,
64ce0668 JL	359	MEM(IMM32_LOWSHIFT8)}},
bb5e141a JL	360	{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
bb5e141a JL	361	{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
36b34aa4	362	{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
64ce0668 JL	363	{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E,
64ce0668 JL	364	MEM(IMM32_LOWSHIFT8)}},
bb5e141a	365	{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
64ce0668	366	MEM2(SD8N_SHIFT8,AN0)}},
36b34aa4	367
1e5ddd3b	368	{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4	369	{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
1e5ddd3b	370	{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4	371	{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
1e5ddd3b	372	{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4 JL	373	{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	374	{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
	375	{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
	376	{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}},
db229054 JL	377
	378	{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N}},
	379	{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N}},
	380	{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N}},
	381	{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N}},
	382	{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N}},
	383	{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N}},
	384	{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N}},
	385	{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N}},
	386	{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N}},
	387	{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N}},
	388	{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N}},
	389	{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N}},
	390	{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N}},
	391	{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N}},
	392	{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N}},
	393
	394	{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
	395	{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
	396	{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
	397	{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
	398	{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
	399	{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
	400	{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
	401	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	402	{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
	403	{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
	404	{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
	405	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	406	{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
	407
54dfaf0a	408	{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
fdef41f3	409	{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {IMM16}},
26433754	410	{ "jmp", 0xdc000000, 0xff000000, FMT_S4, {IMM32_HIGH24}},
bb5e141a	411	{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
26433754 JL	412	{ "call", 0xdd000000, 0xff000000, FMT_S6,
26433754 JL	413	{IMM32_HIGH24_LOWSHIFT16,IMM8E_SHIFT8,IMM8E}},
54dfaf0a	414	{ "calls", 0xf0f0, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
fdef41f3 JL	415	{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {IMM16}},
fdef41f3 JL	416	{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {IMM32}},
db229054	417
4aa92185 JL	418	{ "ret", 0xdf0000, 0xff0000, FMT_S2, {IMM8_SHIFT8, IMM8}},
4aa92185 JL	419	{ "retf", 0xde0000, 0xff0000, FMT_S2, {IMM8_SHIFT8, IMM8}},
db229054 JL	420	{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
	421	{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
	422	{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
	423	{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
	424	{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
	425	/* { "udf", 0, 0, {0}}, */
344d6417	426
f2ab9a75 JL	427	{ "putx", 0xf500, 0xfff0, FMT_D0, {DN01}},
f2ab9a75 JL	428	{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN01}},
36b34aa4 JL	429	{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}},
	430	{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	431	{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	432	{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	433	{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}},
f2ab9a75 JL	434	{ "mulqu", 0xf91400, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	435	{ "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	436	{ "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
36b34aa4 JL	437	{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}},
	438	{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}},
	439	{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}},
db229054	440	{ 0, 0, 0, 0, {0}},
5ab7bce6	441
cd8a9026	442	} ;
e7c50cef	443
ae1b99e4 JL	444	const int mn10300_num_opcodes =
ae1b99e4 JL	445	sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
e7c50cef JL	446
e7c50cef JL	447	\f