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ubsan: or1k: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / nds32-asm.c
CommitLineData
35c08157 1/* NDS32-specific support for 32-bit ELF.
82704155 2 Copyright (C) 2012-2019 Free Software Foundation, Inc.
35c08157
KLC		 3 Contributed by Andes Technology Corporation.
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
40c7a7cb 20 02110-1301, USA. */
35c08157
KLC		 21
22
a6743a54 23#include "sysdep.h"
35c08157 24
2d5d5a8f 25#include "bfd_stdint.h"
35c08157
KLC		 26#include <assert.h>
27
28#include "safe-ctype.h"
29#include "libiberty.h"
30#include "hashtab.h"
31#include "bfd.h"
a6743a54 32#include "opintl.h"
35c08157 33
fbaf61ad
NC		 34#include <config.h>
35#include <stdlib.h>
36#include <string.h>
37
35c08157
KLC		 38#include "opcode/nds32.h"
39#include "nds32-asm.h"
40
41/* There at at most MAX_LEX_NUM lexical elements in a syntax. */
42#define MAX_LEX_NUM 32
43/* A operand in syntax string should be at most this long. */
40c7a7cb 44#define MAX_LEX_LEN 64
35c08157
KLC		 45/* The max length of a keyword can be. */
46#define MAX_KEYWORD_LEN 32
47/* This LEX is a plain char or operand. */
48#define IS_LEX_CHAR(c) (((c) >> 7) == 0)
fbaf61ad
NC		 49#define LEX_SET_FIELD(k,c) ((c) | (((k) + 1) << 8))
50#define LEX_GET_FIELD(k,c) (nds32_field_table[k])[((c) & 0xff)]
35c08157
KLC		 51/* Get the char in this lexical element. */
52#define LEX_CHAR(c) ((c) & 0xff)
53
54#define USRIDX(group, usr) ((group) | ((usr) << 5))
55#define SRIDX(major, minor, ext) \
40c7a7cb 56 (((major) << 7) | ((minor) << 3) | (ext))
35c08157 57
40c7a7cb
KLC		 58static int parse_re (struct nds32_asm_desc *, struct nds32_asm_insn *,
59 char **, int64_t *);
35c08157
KLC		 60static int parse_re2 (struct nds32_asm_desc *, struct nds32_asm_insn *,
61 char **, int64_t *);
62static int parse_fe5 (struct nds32_asm_desc *, struct nds32_asm_insn *,
63 char **, int64_t *);
64static int parse_pi5 (struct nds32_asm_desc *, struct nds32_asm_insn *,
65 char **, int64_t *);
fbaf61ad
NC		 66static int parse_aext_reg (struct nds32_asm_desc *, char **,
67 int *, int);
40c7a7cb
KLC		 68static int parse_a30b20 (struct nds32_asm_desc *, struct nds32_asm_insn *,
69 char **, int64_t *);
70static int parse_rt21 (struct nds32_asm_desc *, struct nds32_asm_insn *,
71 char **, int64_t *);
72static int parse_rte_start (struct nds32_asm_desc *, struct nds32_asm_insn *,
73 char **, int64_t *);
74static int parse_rte_end (struct nds32_asm_desc *, struct nds32_asm_insn *,
75 char **, int64_t *);
76static int parse_rte69_start (struct nds32_asm_desc *, struct nds32_asm_insn *,
77 char **, int64_t *);
78static int parse_rte69_end (struct nds32_asm_desc *, struct nds32_asm_insn *,
79 char **, int64_t *);
80static int parse_im5_ip (struct nds32_asm_desc *, struct nds32_asm_insn *,
81 char **, int64_t *);
82static int parse_im5_mr (struct nds32_asm_desc *, struct nds32_asm_insn *,
83 char **, int64_t *);
84static int parse_im6_ip (struct nds32_asm_desc *, struct nds32_asm_insn *,
85 char **, int64_t *);
86static int parse_im6_iq (struct nds32_asm_desc *, struct nds32_asm_insn *,
87 char **, int64_t *);
88static int parse_im6_mr (struct nds32_asm_desc *, struct nds32_asm_insn *,
89 char **, int64_t *);
90static int parse_im6_ms (struct nds32_asm_desc *, struct nds32_asm_insn *,
91 char **, int64_t *);
35c08157 92
35c08157
KLC		 93/* These are operand prefixes for input/output semantic.
94
95 % input
96 = output
97 & both
98 {} optional operand
99
100 Field table for operands and bit-fields. */
101
40c7a7cb 102const field_t operand_fields[] =
35c08157
KLC		 103{
104 {"rt", 20, 5, 0, HW_GPR, NULL},
105 {"ra", 15, 5, 0, HW_GPR, NULL},
106 {"rb", 10, 5, 0, HW_GPR, NULL},
107 {"rd", 5, 5, 0, HW_GPR, NULL},
40c7a7cb 108 {"re", 10, 5, 0, HW_GPR, parse_re}, /* lmw smw lmwa smwa. */
35c08157
KLC		 109 {"fst", 20, 5, 0, HW_FSR, NULL},
110 {"fsa", 15, 5, 0, HW_FSR, NULL},
111 {"fsb", 10, 5, 0, HW_FSR, NULL},
112 {"fdt", 20, 5, 0, HW_FDR, NULL},
113 {"fda", 15, 5, 0, HW_FDR, NULL},
114 {"fdb", 10, 5, 0, HW_FDR, NULL},
115 {"cprt", 20, 5, 0, HW_CPR, NULL},
116 {"cp", 13, 2, 0, HW_CP, NULL},
117 {"sh", 5, 5, 0, HW_UINT, NULL}, /* sh in ALU instructions. */
118 {"sv", 8, 2, 0, HW_UINT, NULL}, /* sv in MEM instructions. */
119 {"dt", 21, 1, 0, HW_DXR, NULL},
120 {"usr", 10, 10, 0, HW_USR, NULL}, /* User Special Registers. */
121 {"sr", 10, 10, 0, HW_SR, NULL}, /* System Registers. */
122 {"ridx", 10, 10, 0, HW_UINT, NULL}, /* Raw value for mfusr/mfsr. */
40c7a7cb 123 {"enb4", 6, 4, 0, HW_UINT, NULL}, /* Enable4 for LSMW. */
35c08157
KLC		 124 {"swid", 5, 15, 0, HW_UINT, NULL},
125 {"stdby_st", 5, 2, 0, HW_STANDBY_ST, NULL},
126 {"tlbop_st", 5, 5, 0, HW_TLBOP_ST, NULL},
127 {"tlbop_stx", 5, 5, 0, HW_UINT, NULL},
128 {"cctl_st0", 5, 5, 0, HW_CCTL_ST0, NULL},
129 {"cctl_st1", 5, 5, 0, HW_CCTL_ST1, NULL},
130 {"cctl_st2", 5, 5, 0, HW_CCTL_ST2, NULL},
131 {"cctl_st3", 5, 5, 0, HW_CCTL_ST3, NULL},
132 {"cctl_st4", 5, 5, 0, HW_CCTL_ST4, NULL},
133 {"cctl_st5", 5, 5, 0, HW_CCTL_ST5, NULL},
134 {"cctl_stx", 5, 5, 0, HW_UINT, NULL},
135 {"cctl_lv", 10, 1, 0, HW_CCTL_LV, NULL},
136 {"msync_st", 5, 3, 0, HW_MSYNC_ST, NULL},
137 {"msync_stx", 5, 3, 0, HW_UINT, NULL},
40c7a7cb 138 {"dpref_st", 20, 4, 0, HW_DPREF_ST, NULL},
35c08157
KLC		 139 {"rt5", 5, 5, 0, HW_GPR, NULL},
140 {"ra5", 0, 5, 0, HW_GPR, NULL},
141 {"rt4", 5, 4, 0, HW_GPR, NULL},
142 {"rt3", 6, 3, 0, HW_GPR, NULL},
143 {"rt38", 8, 3, 0, HW_GPR, NULL}, /* rt3 used in 38 form. */
144 {"ra3", 3, 3, 0, HW_GPR, NULL},
145 {"rb3", 0, 3, 0, HW_GPR, NULL},
40c7a7cb
KLC		 146 {"rt5e", 4, 4, 1, HW_GPR, NULL}, /* for movd44. */
147 {"ra5e", 0, 4, 1, HW_GPR, NULL}, /* for movd44. */
35c08157
KLC		 148 {"re2", 5, 2, 0, HW_GPR, parse_re2}, /* re in push25/pop25. */
149 {"fe5", 0, 5, 2, HW_UINT, parse_fe5}, /* imm5u in lwi45.fe. */
150 {"pi5", 0, 5, 0, HW_UINT, parse_pi5}, /* imm5u in movpi45. */
151 {"abdim", 2, 3, 0, HW_ABDIM, NULL}, /* Flags for LSMW. */
152 {"abm", 2, 3, 0, HW_ABM, NULL}, /* Flags for LSMWZB. */
153 {"dtiton", 8, 2, 0, HW_DTITON, NULL},
154 {"dtitoff", 8, 2, 0, HW_DTITOFF, NULL},
155
156 {"i5s", 0, 5, 0, HW_INT, NULL},
157 {"i10s", 0, 10, 0, HW_INT, NULL},
158 {"i15s", 0, 15, 0, HW_INT, NULL},
159 {"i19s", 0, 19, 0, HW_INT, NULL},
160 {"i20s", 0, 20, 0, HW_INT, NULL},
161 {"i8s1", 0, 8, 1, HW_INT, NULL},
162 {"i11br3", 8, 11, 0, HW_INT, NULL},
163 {"i14s1", 0, 14, 1, HW_INT, NULL},
164 {"i15s1", 0, 15, 1, HW_INT, NULL},
165 {"i16s1", 0, 16, 1, HW_INT, NULL},
fbaf61ad 166 {"i16u5", 5, 16, 0, HW_UINT, NULL},
35c08157
KLC		 167 {"i18s1", 0, 18, 1, HW_INT, NULL},
168 {"i24s1", 0, 24, 1, HW_INT, NULL},
169 {"i8s2", 0, 8, 2, HW_INT, NULL},
170 {"i12s2", 0, 12, 2, HW_INT, NULL},
171 {"i15s2", 0, 15, 2, HW_INT, NULL},
172 {"i17s2", 0, 17, 2, HW_INT, NULL},
173 {"i19s2", 0, 19, 2, HW_INT, NULL},
174 {"i3u", 0, 3, 0, HW_UINT, NULL},
175 {"i5u", 0, 5, 0, HW_UINT, NULL},
176 {"ib5u", 10, 5, 0, HW_UINT, NULL}, /* imm5 field in ALU. */
177 {"ib5s", 10, 5, 0, HW_INT, NULL}, /* imm5 field in ALU. */
40c7a7cb 178 {"ia3u", 3, 3, 0, HW_UINT, NULL}, /* for bmski33, fexti33. */
35c08157 179 {"i8u", 0, 8, 0, HW_UINT, NULL},
40c7a7cb 180 {"ib8u", 7, 8, 0, HW_UINT, NULL}, /* for ffbi. */
35c08157
KLC		 181 {"i15u", 0, 15, 0, HW_UINT, NULL},
182 {"i20u", 0, 20, 0, HW_UINT, NULL},
183 {"i3u1", 0, 3, 1, HW_UINT, NULL},
184 {"i9u1", 0, 9, 1, HW_UINT, NULL},
185 {"i3u2", 0, 3, 2, HW_UINT, NULL},
186 {"i6u2", 0, 6, 2, HW_UINT, NULL},
187 {"i7u2", 0, 7, 2, HW_UINT, NULL},
40c7a7cb
KLC		 188 {"i5u3", 0, 5, 3, HW_UINT, NULL}, /* for pop25/pop25. */
189 {"i15s3", 0, 15, 3, HW_INT, NULL}, /* for dprefi.d. */
fbaf61ad
NC		 190 {"ib4u", 10, 4, 0, HW_UINT, NULL}, /* imm5 field in ALU. */
191 {"ib2u", 10, 2, 0, HW_UINT, NULL}, /* imm5 field in ALU. */
40c7a7cb
KLC		 192
193 {"a_rt", 15, 5, 0, HW_GPR, NULL}, /* for audio-extension. */
194 {"a_ru", 10, 5, 0, HW_GPR, NULL}, /* for audio-extension. */
195 {"a_dx", 9, 1, 0, HW_DXR, NULL}, /* for audio-extension. */
196 {"a_a30", 16, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */
197 {"a_b20", 12, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */
198 {"a_rt21", 5, 7, 0, HW_GPR, parse_rt21}, /* for audio-extension. */
199 {"a_rte", 5, 7, 0, HW_GPR, parse_rte_start}, /* for audio-extension. */
200 {"a_rte1", 5, 7, 0, HW_GPR, parse_rte_end}, /* for audio-extension. */
201 {"a_rte69", 6, 4, 0, HW_GPR, parse_rte69_start}, /* for audio-extension. */
202 {"a_rte69_1", 6, 4, 0, HW_GPR, parse_rte69_end}, /* for audio-extension. */
203 {"dhy", 5, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */
204 {"dxh", 15, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */
205 {"aridx", 0, 5, 0, HW_AEXT_ARIDX, NULL}, /* for audio-extension. */
206 {"aridx2", 0, 5, 0, HW_AEXT_ARIDX2, NULL}, /* for audio-extension. */
207 {"aridxi", 16, 4, 0, HW_AEXT_ARIDXI, NULL}, /* for audio-extension. */
fbaf61ad
NC		 208 {"aridxi_mx", 16, 4, 0, HW_AEXT_ARIDXI_MX, NULL}, /* for audio-extension. */
209 {"imm16s", 0, 16, 0, HW_INT, NULL}, /* for audio-extension. */
210 {"imm16u", 0, 16, 0, HW_UINT, NULL}, /* for audio-extension. */
40c7a7cb
KLC		 211 {"im5_i", 0, 5, 0, HW_AEXT_IM_I, parse_im5_ip}, /* for audio-extension. */
212 {"im5_m", 0, 5, 0, HW_AEXT_IM_M, parse_im5_mr}, /* for audio-extension. */
213 {"im6_ip", 0, 2, 0, HW_AEXT_IM_I, parse_im6_ip}, /* for audio-extension. */
214 {"im6_iq", 0, 2, 0, HW_AEXT_IM_I, parse_im6_iq}, /* for audio-extension. */
215 {"im6_mr", 2, 2, 0, HW_AEXT_IM_M, parse_im6_mr}, /* for audio-extension. */
216 {"im6_ms", 4, 2, 0, HW_AEXT_IM_M, parse_im6_ms}, /* for audio-extension. */
217 {"cp45", 4, 2, 0, HW_CP, NULL}, /* for cop-extension. */
218 {"i12u", 8, 12, 0, HW_UINT, NULL}, /* for cop-extension. */
219 {"cpi19", 6, 19, 0, HW_UINT, NULL}, /* for cop-extension. */
35c08157
KLC		 220 {NULL, 0, 0, 0, 0, NULL}
221};
222
4ec521f2
KLC		 223#define DEF_REG(r) (N32_BIT (r))
224#define USE_REG(r) (N32_BIT (r))
35c08157
KLC		 225#define RT(r) (r << 20)
226#define RA(r) (r << 15)
227#define RB(r) (r << 10)
228#define RA5(r) (r)
229
40c7a7cb 230struct nds32_opcode nds32_opcodes[] =
35c08157 231{
40c7a7cb
KLC		 232 /* opc6_encoding table OPC_6. */
233 {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
234 {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
235 {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
236 {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
237 {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
238 {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
239 {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
240 {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
241 {"swi", "%rt,[%ra{+%i15s2}]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
242 {"sbi.bi", "%rt,[%ra],%i15s", OP6 (SBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
243 {"shi.bi", "%rt,[%ra],%i15s1", OP6 (SHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
244 {"swi.bi", "%rt,[%ra],%i15s2", OP6 (SWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
245
246 {"lbsi", "=rt,[%ra{+%i15s}]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
247 {"lhsi", "=rt,[%ra{+%i15s1}]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
248 {"lbsi.bi", "=rt,[%ra],%i15s", OP6 (LBSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
249 {"lhsi.bi", "=rt,[%ra],%i15s1", OP6 (LHSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
250 {"movi", "=rt,%i20s", OP6 (MOVI), 4, ATTR_ALL, 0, NULL, 0, NULL},
251 {"sethi", "=rt,%i20u", OP6 (SETHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
252 {"addi", "=rt,%ra,%i15s", OP6 (ADDI), 4, ATTR_ALL, 0, NULL, 0, NULL},
253 {"subri", "=rt,%ra,%i15s", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
254 {"andi", "=rt,%ra,%i15u", OP6 (ANDI), 4, ATTR_ALL, 0, NULL, 0, NULL},
255 {"xori", "=rt,%ra,%i15u", OP6 (XORI), 4, ATTR_ALL, 0, NULL, 0, NULL},
256 {"ori", "=rt,%ra,%i15u", OP6 (ORI), 4, ATTR_ALL, 0, NULL, 0, NULL},
257 {"slti", "=rt,%ra,%i15s", OP6 (SLTI), 4, ATTR_ALL, 0, NULL, 0, NULL},
258 {"sltsi", "=rt,%ra,%i15s", OP6 (SLTSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
259 {"bitci", "=rt,%ra,%i15u", OP6 (BITCI), 4, ATTR_V3, 0, NULL, 0, NULL},
260
261 /* seg-DPREFI. */
262 {"dprefi.w", "%dpref_st,[%ra{+%i15s2}]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
4ec521f2 263 {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | N32_BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
40c7a7cb
KLC		 264 /* seg-LBGP. */
265 {"lbi.gp", "=rt,[+%i19s]", OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
4ec521f2 266 {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | N32_BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
40c7a7cb
KLC		 267 /* seg-LWC/0. */
268 {"cplwi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (LWC), 4, 0, 0, NULL, 0, NULL},
4ec521f2 269 {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
40c7a7cb
KLC		 270 /* seg-SWC/0. */
271 {"cpswi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (SWC), 4, 0, 0, NULL, 0, NULL},
4ec521f2 272 {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
40c7a7cb
KLC		 273 /* seg-LDC/0. */
274 {"cpldi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (LDC), 4, 0, 0, NULL, 0, NULL},
4ec521f2 275 {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
40c7a7cb
KLC		 276 /* seg-SDC/0. */
277 {"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (SDC), 4, 0, 0, NULL, 0, NULL},
4ec521f2 278 {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
40c7a7cb
KLC		 279 /* seg-LSMW. */
280 {"lmw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL},
281 {"lmwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
282 {"lmwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
4ec521f2
KLC		 283 {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | N32_BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
284 {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | N32_BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
285 {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | N32_BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
40c7a7cb
KLC		 286 /* seg-HWGP. */
287 {"lhi.gp", "=rt,[+%i18s1]", OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
288 {"lhsi.gp", "=rt,[+%i18s1]", OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
289 {"shi.gp", "%rt,[+%i18s1]", OP6 (HWGP) | (4 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
290 {"lwi.gp", "=rt,[+%i17s2]", OP6 (HWGP) | (6 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
291 {"swi.gp", "%rt,[+%i17s2]", OP6 (HWGP) | (7 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
292
293 /* seg-SBGP. */
294 {"sbi.gp", "%rt,[+%i19s]", OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
4ec521f2 295 {"addi.gp", "=rt,%i19s", OP6 (SBGP) | N32_BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
40c7a7cb
KLC		 296 /* seg-JI. */
297 {"j", "%i24s1", OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
4ec521f2 298 {"jal", "%i24s1", OP6 (JI) | N32_BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 299 /* seg-JREG. */
300 {"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
301 {"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
302 {"jrnez", "%rb", JREG (JRNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
303 {"jralnez", "%rt,%rb", JREG (JRALNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
304 {"ret", "%rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 305 {"jral", "%rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
306 {"jralnez", "%rb", JREG (JRALNEZ) | RT (30), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
307 {"ret", "", JREG (JR) | JREG_RET | RB (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
308 {"jr", "%dtitoff %rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL},
309 {"ret", "%dtitoff %rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL},
310 {"jral", "%dtiton %rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
311 {"jral", "%dtiton %rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
312 /* seg-BR1. */
313 {"beq", "%rt,%ra,%i14s1", OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
4ec521f2 314 {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | N32_BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb 315 /* seg-BR2. */
40c7a7cb
KLC		 316 {"beqz", "%rt,%i16s1", BR2 (BEQZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
317 {"bnez", "%rt,%i16s1", BR2 (BNEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
318 {"bgez", "%rt,%i16s1", BR2 (BGEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
319 {"bltz", "%rt,%i16s1", BR2 (BLTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
320 {"bgtz", "%rt,%i16s1", BR2 (BGTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
321 {"blez", "%rt,%i16s1", BR2 (BLEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
322 {"bgezal", "%rt,%i16s1", BR2 (BGEZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
323 {"bltzal", "%rt,%i16s1", BR2 (BLTZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
324 /* seg-BR3. */
325 {"beqc", "%rt,%i11br3,%i8s1", OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
4ec521f2 326 {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | N32_BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
40c7a7cb
KLC		 327 /* seg-SIMD. */
328 {"pbsad", "%rt,%ra,%rb", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
329 {"pbsada", "%rt,%ra,%rb", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
330 /* seg-ALU1. */
331 {"add", "=rt,%ra,%rb", ALU1 (ADD), 4, ATTR_ALL, 0, NULL, 0, NULL},
332 {"sub", "=rt,%ra,%rb", ALU1 (SUB), 4, ATTR_ALL, 0, NULL, 0, NULL},
333 {"and", "=rt,%ra,%rb", ALU1 (AND), 4, ATTR_ALL, 0, NULL, 0, NULL},
334 {"xor", "=rt,%ra,%rb", ALU1 (XOR), 4, ATTR_ALL, 0, NULL, 0, NULL},
335 {"or", "=rt,%ra,%rb", ALU1 (OR), 4, ATTR_ALL, 0, NULL, 0, NULL},
336 {"nor", "=rt,%ra,%rb", ALU1 (NOR), 4, ATTR_ALL, 0, NULL, 0, NULL},
337 {"slt", "=rt,%ra,%rb", ALU1 (SLT), 4, ATTR_ALL, 0, NULL, 0, NULL},
338 {"slts", "=rt,%ra,%rb", ALU1 (SLTS), 4, ATTR_ALL, 0, NULL, 0, NULL},
339 {"slli", "=rt,%ra,%ib5u", ALU1 (SLLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
340 {"srli", "=rt,%ra,%ib5u", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
341 {"srai", "=rt,%ra,%ib5u", ALU1 (SRAI), 4, ATTR_ALL, 0, NULL, 0, NULL},
342 {"rotri", "=rt,%ra,%ib5u", ALU1 (ROTRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
343 {"sll", "=rt,%ra,%rb", ALU1 (SLL), 4, ATTR_ALL, 0, NULL, 0, NULL},
344 {"srl", "=rt,%ra,%rb", ALU1 (SRL), 4, ATTR_ALL, 0, NULL, 0, NULL},
345 {"sra", "=rt,%ra,%rb", ALU1 (SRA), 4, ATTR_ALL, 0, NULL, 0, NULL},
346 {"rotr", "=rt,%ra,%rb", ALU1 (ROTR), 4, ATTR_ALL, 0, NULL, 0, NULL},
347 {"seb", "=rt,%ra", ALU1 (SEB), 4, ATTR_ALL, 0, NULL, 0, NULL},
348 {"seh", "=rt,%ra", ALU1 (SEH), 4, ATTR_ALL, 0, NULL, 0, NULL},
349 {"bitc", "=rt,%ra,%rb", ALU1 (BITC), 4, ATTR_V3, 0, NULL, 0, NULL},
350 {"zeh", "=rt,%ra", ALU1 (ZEH), 4, ATTR_ALL, 0, NULL, 0, NULL},
351 {"wsbh", "=rt,%ra", ALU1 (WSBH), 4, ATTR_ALL, 0, NULL, 0, NULL},
352 {"divsr", "=rt,=rd,%ra,%rb", ALU1 (DIVSR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL},
353 {"divr", "=rt,=rd,%ra,%rb", ALU1 (DIVR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL},
354 {"sva", "=rt,%ra,%rb", ALU1 (SVA), 4, ATTR_ALL, 0, NULL, 0, NULL},
355 {"svs", "=rt,%ra,%rb", ALU1 (SVS), 4, ATTR_ALL, 0, NULL, 0, NULL},
356 {"cmovz", "=rt,%ra,%rb", ALU1 (CMOVZ), 4, ATTR_ALL, 0, NULL, 0, NULL},
357 {"cmovn", "=rt,%ra,%rb", ALU1 (CMOVN), 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157
KLC		 358 {"or_srli", "=rt,%ra,%rb,%sh", ALU1 (OR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
359 {"add_srli", "=rt,%ra,%rb,%sh", ALU1 (ADD_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
360 {"sub_srli", "=rt,%ra,%rb,%sh", ALU1 (SUB_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
361 {"and_srli", "=rt,%ra,%rb,%sh", ALU1 (AND_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
362 {"xor_srli", "=rt,%ra,%rb,%sh", ALU1 (XOR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
40c7a7cb
KLC		 363 {"add_slli", "=rt,%ra,%rb,%sh", ALU1 (ADD), 4, ATTR_V3, 0, NULL, 0, NULL},
364 {"sub_slli", "=rt,%ra,%rb,%sh", ALU1 (SUB), 4, ATTR_V3, 0, NULL, 0, NULL},
365 {"and_slli", "=rt,%ra,%rb,%sh", ALU1 (AND), 4, ATTR_V3, 0, NULL, 0, NULL},
366 {"xor_slli", "=rt,%ra,%rb,%sh", ALU1 (XOR), 4, ATTR_V3, 0, NULL, 0, NULL},
367 {"or_slli", "=rt,%ra,%rb,%sh", ALU1 (OR), 4, ATTR_V3, 0, NULL, 0, NULL},
368 {"nop", "", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
369 /* seg-ALU2. */
35c08157
KLC		 370 {"max", "=rt,%ra,%rb", ALU2 (MAX), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
371 {"min", "=rt,%ra,%rb", ALU2 (MIN), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
372 {"ave", "=rt,%ra,%rb", ALU2 (AVE), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
373 {"abs", "=rt,%ra", ALU2 (ABS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
40c7a7cb 374 {"clips", "=rt,%ra,%ib5u", ALU2 (CLIPS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
35c08157
KLC		 375 {"clip", "=rt,%ra,%ib5u", ALU2 (CLIP), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
376 {"clo", "=rt,%ra", ALU2 (CLO), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
377 {"clz", "=rt,%ra", ALU2 (CLZ), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
378 {"bset", "=rt,%ra,%ib5u", ALU2 (BSET), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
379 {"bclr", "=rt,%ra,%ib5u", ALU2 (BCLR), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
380 {"btgl", "=rt,%ra,%ib5u", ALU2 (BTGL), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
381 {"btst", "=rt,%ra,%ib5u", ALU2 (BTST), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
382 {"bse", "=rt,%ra,=rb", ALU2 (BSE), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
383 {"bsp", "=rt,%ra,=rb", ALU2 (BSP), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
35c08157 384 {"ffzmism", "=rt,%ra,%rb", ALU2 (FFZMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
fbaf61ad
NC		 385 {"mfusr", "=rt,%usr", ALU2 (MFUSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
386 {"mtusr", "%rt,%usr", ALU2 (MTUSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
387 {"mfusr", "=rt,%ridx", ALU2 (MFUSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
388 {"mtusr", "%rt,%ridx", ALU2 (MTUSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157 389 {"mul", "=rt,%ra,%rb", ALU2 (MUL), 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157
KLC		 390 {"madds64", "=dt,%ra,%rb", ALU2 (MADDS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
391 {"madd64", "=dt,%ra,%rb", ALU2 (MADD64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
392 {"msubs64", "=dt,%ra,%rb", ALU2 (MSUBS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
393 {"msub64", "=dt,%ra,%rb", ALU2 (MSUB64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
394 {"divs", "=dt,%ra,%rb", ALU2 (DIVS), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL},
395 {"div", "=dt,%ra,%rb", ALU2 (DIV), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL},
396 {"mult32", "=dt,%ra,%rb", ALU2 (MULT32), 4, ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 397
398 /* seg-ALU2_FFBI. */
399 {"ffb", "=rt,%ra,%rb", ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
4ec521f2 400 {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | N32_BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
40c7a7cb
KLC		 401 /* seg-ALU2_FLMISM. */
402 {"ffmism", "=rt,%ra,%rb", ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
4ec521f2 403 {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | N32_BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
40c7a7cb
KLC		 404 /* seg-ALU2_MULSR64. */
405 {"mults64", "=dt,%ra,%rb", ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL},
4ec521f2 406 {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| N32_BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
40c7a7cb
KLC		 407 /* seg-ALU2_MULR64. */
408 {"mult64", "=dt,%ra,%rb", ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL},
4ec521f2 409 {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | N32_BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
40c7a7cb
KLC		 410 /* seg-ALU2_MADDR32. */
411 {"madd32", "=dt,%ra,%rb", ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
4ec521f2 412 {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | N32_BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
40c7a7cb
KLC		 413 /* seg-ALU2_MSUBR32. */
414 {"msub32", "=dt,%ra,%rb", ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
4ec521f2 415 {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | N32_BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
35c08157 416
40c7a7cb 417 /* seg-MISC. */
35c08157 418 {"standby", "%stdby_st", MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157 419 {"mfsr", "=rt,%sr", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157
KLC		 420 {"iret", "", MISC (IRET), 4, ATTR_ALL, 0, NULL, 0, NULL},
421 {"trap", "%swid", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
e5fe4957
KLC		 422 {"teqz", "%rt{,%swid}", MISC (TEQZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
423 {"tnez", "%rt{,%swid}", MISC (TNEZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
35c08157
KLC		 424 {"dsb", "", MISC (DSB), 4, ATTR_ALL, 0, NULL, 0, NULL},
425 {"isb", "", MISC (ISB), 4, ATTR_ALL, 0, NULL, 0, NULL},
426 {"break", "%swid", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157
KLC		 427 {"syscall", "%swid", MISC (SYSCALL), 4, ATTR_ALL, 0, NULL, 0, NULL},
428 {"msync", "%msync_st", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157 429 {"isync", "%rt", MISC (ISYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 430 /* seg-MISC_MTSR. */
431 {"mtsr", "%rt,%sr", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
432 /* seg-MISC_SETEND. */
4ec521f2
KLC		 433 {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
434 {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5) | N32_BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb 435 /* seg-MISC_SETGIE. */
4ec521f2
KLC		 436 {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
437 {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6) | N32_BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 438 {"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
439 {"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
440 {"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
441 {"break", "", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
442 {"msync", "", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
443 /* seg-MISC_TLBOP. */
444 {"tlbop", "%ra,%tlbop_st", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL},
445 {"tlbop", "%ra,%tlbop_stx", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL},
446 {"tlbop", "%rt,%ra,pb", MISC (TLBOP) | (5 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
fbaf61ad 447 {"tlbop", "%rt,%ra,probe", MISC (TLBOP) | (5 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 448 {"tlbop", "flua", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
449 {"tlbop", "flushall", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
450
451 /* seg-MEM. */
452 {"lb", "=rt,[%ra+(%rb<<%sv)]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL},
453 {"lb", "=rt,[%ra+%rb{<<%sv}]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL},
454 {"lh", "=rt,[%ra+(%rb<<%sv)]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL},
455 {"lh", "=rt,[%ra+%rb{<<%sv}]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL},
456 {"lw", "=rt,[%ra+(%rb<<%sv)]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL},
457 {"lw", "=rt,[%ra+%rb{<<%sv}]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL},
458 {"ld", "=rt,[%ra+(%rb<<%sv)]", MEM (LD), 4, ATTR_ALL, 0, NULL, 0, NULL},
459 {"lb.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
460 {"lb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
461 {"lb.p", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
462 {"lh.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
463 {"lh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
464 {"lh.p", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
465 {"lw.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
466 {"lw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
467 {"lw.p", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
468 {"ld.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
469 {"sb", "=rt,[%ra+(%rb<<%sv)]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL},
470 {"sb", "%rt,[%ra+%rb{<<%sv}]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL},
471 {"sh", "=rt,[%ra+(%rb<<%sv)]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL},
472 {"sh", "%rt,[%ra+%rb{<<%sv}]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL},
473 {"sw", "=rt,[%ra+(%rb<<%sv)]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL},
474 {"sw", "%rt,[%ra+%rb{<<%sv}]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL},
475 {"sd", "=rt,[%ra+(%rb<<%sv)]", MEM (SD), 4, ATTR_ALL, 0, NULL, 0, NULL},
476 {"sb.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
477 {"sb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
478 {"sb.p", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
479 {"sh.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
480 {"sh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
481 {"sh.p", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
482 {"sw.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
483 {"sw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
484 {"sw.p", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
485 {"sd.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
486
487 {"lbs", "=rt,[%ra+(%rb<<%sv)]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL},
488 {"lbs", "=rt,[%ra+%rb{<<%sv}]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL},
489 {"lhs", "=rt,[%ra+(%rb<<%sv)]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL},
490 {"lhs", "=rt,[%ra+%rb{<<%sv}]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL},
491 {"lbs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
492 {"lbs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
493 {"lbs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
494 {"lhs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
495 {"lhs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
496 {"lhs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
497 {"llw", "=rt,[%ra+(%rb<<%sv)]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
498 {"llw", "=rt,[%ra+%rb{<<%sv}]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
499 {"scw", "%rt,[%ra+(%rb<<%sv)]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
500 {"scw", "%rt,[%ra+%rb{<<%sv}]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
501
502 {"lbup", "=rt,[%ra+(%rb<<%sv)]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
503 {"lbup", "=rt,[%ra+%rb{<<%sv}]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
504 {"lwup", "=rt,[%ra+(%rb<<%sv)]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
505 {"lwup", "=rt,[%ra+%rb{<<%sv}]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
506 {"sbup", "%rt,[%ra+(%rb<<%sv)]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
507 {"sbup", "%rt,[%ra+%rb{<<%sv}]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
508 {"swup", "%rt,[%ra+(%rb<<%sv)]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
509 {"swup", "%rt,[%ra+%rb{<<%sv}]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
510
511 {"dpref", "%dpref_st,[%ra]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
35c08157
KLC		 512 {"dpref", "%dpref_st,[%ra+(%rb<<%sv)]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
513 {"dpref", "%dpref_st,[%ra+%rb{<<%sv}]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
514
40c7a7cb
KLC		 515 /* For missing-operand-load/store instructions. */
516 {"lb", "=rt,[%ra]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
517 {"lh", "=rt,[%ra]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
518 {"lw", "=rt,[%ra]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
519 {"lbs", "=rt,[%ra]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
520 {"lhs", "=rt,[%ra]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
521 {"sb", "%rt,[%ra]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
522 {"sh", "%rt,[%ra]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
523 {"sw", "%rt,[%ra]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
524
525 /* seg-LWC0. */
526 {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
527 {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
528 /* seg-SWC0. */
529 {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
530 {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
531 /* seg-LDC0. */
532 {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
533 {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
534 /* seg-SDC0. */
535 {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
536 {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
537
538 /* seg-FPU_FS1. */
539 {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
540 {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
541 {"fcpynss", "=fst,%fsa,%fsb", FS1 (FCPYNSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
542 {"fcpyss", "=fst,%fsa,%fsb", FS1 (FCPYSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
543 {"fmadds", "=fst,%fsa,%fsb", FS1 (FMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
544 {"fmsubs", "=fst,%fsa,%fsb", FS1 (FMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
545 {"fcmovns", "=fst,%fsa,%fsb", FS1 (FCMOVNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
546 {"fcmovzs", "=fst,%fsa,%fsb", FS1 (FCMOVZS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
547 {"fnmadds", "=fst,%fsa,%fsb", FS1 (FNMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
548 {"fnmsubs", "=fst,%fsa,%fsb", FS1 (FNMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
549 {"fmuls", "=fst,%fsa,%fsb", FS1 (FMULS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
550 {"fdivs", "=fst,%fsa,%fsb", FS1 (FDIVS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
551
552 /* seg-FPU_FS1_F2OP. */
553 {"fs2d", "=fdt,%fsa", FS1_F2OP (FS2D), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
554 {"fsqrts", "=fst,%fsa", FS1_F2OP (FSQRTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
555 {"fabss", "=fst,%fsa", FS1_F2OP (FABSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
556 {"fui2s", "=fst,%fsa", FS1_F2OP (FUI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
557 {"fsi2s", "=fst,%fsa", FS1_F2OP (FSI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
558 {"fs2ui", "=fst,%fsa", FS1_F2OP (FS2UI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
35c08157 559 {"fs2ui.z", "=fst,%fsa", FS1_F2OP (FS2UI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
40c7a7cb 560 {"fs2si", "=fst,%fsa", FS1_F2OP (FS2SI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
35c08157 561 {"fs2si.z", "=fst,%fsa", FS1_F2OP (FS2SI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
40c7a7cb
KLC		 562 /* seg-FPU_FS2. */
563 {"fcmpeqs", "=fst,%fsa,%fsb", FS2 (FCMPEQS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
564 {"fcmpeqs.e", "=fst,%fsa,%fsb", FS2 (FCMPEQS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
565 {"fcmplts", "=fst,%fsa,%fsb", FS2 (FCMPLTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
566 {"fcmplts.e", "=fst,%fsa,%fsb", FS2 (FCMPLTS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
567 {"fcmples", "=fst,%fsa,%fsb", FS2 (FCMPLES), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
568 {"fcmples.e", "=fst,%fsa,%fsb", FS2 (FCMPLES_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
569 {"fcmpuns", "=fst,%fsa,%fsb", FS2 (FCMPUNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
570 {"fcmpuns.e", "=fst,%fsa,%fsb", FS2 (FCMPUNS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
571 /* seg-FPU_FD1. */
572 {"faddd", "=fdt,%fda,%fdb", FD1 (FADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
573 {"fsubd", "=fdt,%fda,%fdb", FD1 (FSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
574 {"fcpynsd", "=fdt,%fda,%fdb", FD1 (FCPYNSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
575 {"fcpysd", "=fdt,%fda,%fdb", FD1 (FCPYSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
576 {"fmaddd", "=fdt,%fda,%fdb", FD1 (FMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
577 {"fmsubd", "=fdt,%fda,%fdb", FD1 (FMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
578 {"fcmovnd", "=fdt,%fda,%fsb", FD1 (FCMOVND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
579 {"fcmovzd", "=fdt,%fda,%fsb", FD1 (FCMOVZD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
580 {"fnmaddd", "=fdt,%fda,%fdb", FD1 (FNMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
581 {"fnmsubd", "=fdt,%fda,%fdb", FD1 (FNMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
582 {"fmuld", "=fdt,%fda,%fdb", FD1 (FMULD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
583 {"fdivd", "=fdt,%fda,%fdb", FD1 (FDIVD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
584 /* seg-FPU_FD1_F2OP. */
585 {"fd2s", "=fst,%fda", FD1_F2OP (FD2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
586 {"fsqrtd", "=fdt,%fda", FD1_F2OP (FSQRTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
587 {"fabsd", "=fdt,%fda", FD1_F2OP (FABSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
588 {"fui2d", "=fdt,%fsa", FD1_F2OP (FUI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
589 {"fsi2d", "=fdt,%fsa", FD1_F2OP (FSI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
590 {"fd2ui", "=fst,%fda", FD1_F2OP (FD2UI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
35c08157 591 {"fd2ui.z", "=fst,%fda", FD1_F2OP (FD2UI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
40c7a7cb 592 {"fd2si", "=fst,%fda", FD1_F2OP (FD2SI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
35c08157 593 {"fd2si.z", "=fst,%fda", FD1_F2OP (FD2SI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
40c7a7cb
KLC		 594 /* seg-FPU_FD2. */
595 {"fcmpeqd", "=fst,%fda,%fdb", FD2 (FCMPEQD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
596 {"fcmpeqd.e", "=fst,%fda,%fdb", FD2 (FCMPEQD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
597 {"fcmpltd", "=fst,%fda,%fdb", FD2 (FCMPLTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
598 {"fcmpltd.e", "=fst,%fda,%fdb", FD2 (FCMPLTD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
599 {"fcmpled", "=fst,%fda,%fdb", FD2 (FCMPLED), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
600 {"fcmpled.e", "=fst,%fda,%fdb", FD2 (FCMPLED_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
601 {"fcmpund", "=fst,%fda,%fdb", FD2 (FCMPUND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
602 {"fcmpund.e", "=fst,%fda,%fdb", FD2 (FCMPUND_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
603 /* seg-FPU_MFCP. */
604 {"fmfsr", "=rt,%fsa", MFCP (FMFSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
605 {"fmfdr", "=rt,%fda", MFCP (FMFDR), 4, ATTR (FPU), 0, NULL, 0, NULL},
606 /* seg-FPU_MFCP_XR. */
607 {"fmfcfg", "=rt", MFCP_XR(FMFCFG), 4, ATTR (FPU), 0, NULL, 0, NULL},
608 {"fmfcsr", "=rt", MFCP_XR(FMFCSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
609 /* seg-FPU_MTCP. */
610
611 {"fmtsr", "%rt,=fsa", MTCP (FMTSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
612 {"fmtdr", "%rt,=fda", MTCP (FMTDR), 4, ATTR (FPU), 0, NULL, 0, NULL},
613 /* seg-FPU_MTCP_XR. */
614 {"fmtcsr", "%rt", MTCP_XR(FMTCSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
615 /* seg-FPU_FLS. */
616 {"fls", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
617 {"fls.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
618 /* seg-FPU_FLD. */
619 {"fld", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
620 {"fld.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
621 /* seg-FPU_FSS. */
622 {"fss", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
623 {"fss.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
624 /* seg-FPU_FSD. */
625 {"fsd", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
626 {"fsd.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
627 {"fls", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
628 {"fls.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
629 {"fld", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
630 {"fld.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
631 {"fss", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
632 {"fss.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
633 {"fsd", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
634 {"fsd.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
635 {"cctl", "%ra,%cctl_st0", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
636 {"cctl", "%ra,%cctl_st1{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
637 {"cctl", "=rt,%ra,%cctl_st2", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
638 {"cctl", "%rt,%ra,%cctl_st3", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
639 {"cctl", "%cctl_st4", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
640 {"cctl", "%cctl_st5{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3, 0, NULL, 0, NULL},
641 {"cctl", "=rt,%ra,%cctl_stx,%cctl_lv", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
642 /* seg-Alias instructions. */
643 {"neg", "=rt,%ra", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
644 {"zeb", "=rt,%ra", OP6 (ANDI) | 0xff, 4, ATTR_ALL, 0, NULL, 0, NULL},
645
646 /* seg-COP. */
647 {"cpe1", "%cp45,%cpi19", OP6 (COP) | 0x00, 4, ATTR_ALL, 0, NULL, 0, NULL},
648 {"cpe2", "%cp45,%cpi19", OP6 (COP) | 0x04, 4, ATTR_ALL, 0, NULL, 0, NULL},
649 {"cpe3", "%cp45,%cpi19", OP6 (COP) | 0x08, 4, ATTR_ALL, 0, NULL, 0, NULL},
650 {"cpe4", "%cp45,%cpi19", OP6 (COP) | 0x0C, 4, ATTR_ALL, 0, NULL, 0, NULL},
651 /* seg-COP-MFCPX. */
652 {"mfcpw", "%cp45,=rt,%i12u", OP6 (COP) | 0x01, 4, ATTR_ALL, 0, NULL, 0, NULL},
653 {"mfcpd", "%cp45,=rt,%i12u", OP6 (COP) | 0x41, 4, ATTR_ALL, 0, NULL, 0, NULL},
654 {"mfcppw", "%cp45,=rt,%i12u", OP6 (COP) | 0xc1, 4, ATTR_ALL, 0, NULL, 0, NULL},
655 /* seg-COP-CPLW. */
656 {"cplw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x02, 4, ATTR_ALL, 0, NULL, 0, NULL},
657 {"cplw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x82, 4, ATTR_ALL, 0, NULL, 0, NULL},
658 /* seg-COP-CPLD. */
659 {"cpld", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x03, 4, ATTR_ALL, 0, NULL, 0, NULL},
660 {"cpld.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x83, 4, ATTR_ALL, 0, NULL, 0, NULL},
661 /* seg-COP-MTCPX. */
662 {"mtcpw", "%cp45,%rt,%i12u", OP6 (COP) | 0x09, 4, ATTR_ALL, 0, NULL, 0, NULL},
663 {"mtcpd", "%cp45,%rt,%i12u", OP6 (COP) | 0x49, 4, ATTR_ALL, 0, NULL, 0, NULL},
664 {"mtcppw", "%cp45,%rt,%i12u", OP6 (COP) | 0xc9, 4, ATTR_ALL, 0, NULL, 0, NULL},
665 /* seg-COP-CPSW. */
666 {"cpsw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0a, 4, ATTR_ALL, 0, NULL, 0, NULL},
667 {"cpsw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8a, 4, ATTR_ALL, 0, NULL, 0, NULL},
668 /* seg-COP-CPSD. */
669 {"cpsd", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0b, 4, ATTR_ALL, 0, NULL, 0, NULL},
670 {"cpsd.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8b, 4, ATTR_ALL, 0, NULL, 0, NULL},
35c08157
KLC		 671
672 /* 16-bit instructions. */
40c7a7cb
KLC		 673 /* get bit14~bit11 of 16-bit instruction. */
674 {"beqz38", "%rt38,%i8s1", 0xc000, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
675 {"bnez38", "%rt38,%i8s1", 0xc800, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
676 {"beqs38", "%rt38,%i8s1", 0xd000, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
677 {"bnes38", "%rt38,%i8s1", 0xd800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
678
679 /* SEG00, get bit10. */
680 {"mov55", "=rt5,%ra5", 0x8000, 2, ATTR_ALL, 0, NULL, 0, NULL},
681 {"movi55", "=rt5,%i5s", 0x8400, 2, ATTR_ALL, 0, NULL, 0, NULL},
682 /* SEG01 bit10~bit9. */
683 {"add45", "=rt4,%ra5", 0x8800, 2, ATTR_ALL, 0, NULL, 0, NULL},
684 {"sub45", "=rt4,%ra5", 0x8a00, 2, ATTR_ALL, 0, NULL, 0, NULL},
685 {"addi45", "=rt4,%i5u", 0x8c00, 2, ATTR_ALL, 0, NULL, 0, NULL},
686 {"subi45", "=rt4,%i5u", 0x8e00, 2, ATTR_ALL, 0, NULL, 0, NULL},
687 /* SEG02 bit10~bit9. */
688 {"srai45", "=rt4,%i5u", 0x9000, 2, ATTR_ALL, 0, NULL, 0, NULL},
689 {"srli45", "=rt4,%i5u", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL},
690 {"slli333", "=rt3,%ra3,%i3u", 0x9400, 2, ATTR_ALL, 0, NULL, 0, NULL},
691 /* SEG03 bit10~bit9. */
692 {"add333", "=rt3,%ra3,%rb3", 0x9800, 2, ATTR_ALL, 0, NULL, 0, NULL},
693 {"sub333", "=rt3,%ra3,%rb3", 0x9a00, 2, ATTR_ALL, 0, NULL, 0, NULL},
694 {"addi333", "=rt3,%ra3,%i3u", 0x9c00, 2, ATTR_ALL, 0, NULL, 0, NULL},
695 {"subi333", "=rt3,%ra3,%i3u", 0x9e00, 2, ATTR_ALL, 0, NULL, 0, NULL},
696 /* SEG04 bit10~bit9. */
35c08157
KLC		 697 {"lwi333", "=rt3,[%ra3{+%i3u2}]", 0xa000, 2, ATTR_ALL, 0, NULL, 0, NULL},
698 {"lwi333.bi", "=rt3,[%ra3],%i3u2", 0xa200, 2, ATTR_ALL, 0, NULL, 0, NULL},
699 {"lhi333", "=rt3,[%ra3{+%i3u1}]", 0xa400, 2, ATTR_ALL, 0, NULL, 0, NULL},
700 {"lbi333", "=rt3,[%ra3{+%i3u}]", 0xa600, 2, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb 701 /* SEG05 bit10~bit9. */
35c08157
KLC		 702 {"swi333", "%rt3,[%ra3{+%i3u2}]", 0xa800, 2, ATTR_ALL, 0, NULL, 0, NULL},
703 {"swi333.bi", "%rt3,[%ra3],%i3u2", 0xaa00, 2, ATTR_ALL, 0, NULL, 0, NULL},
704 {"shi333", "%rt3,[%ra3{+%i3u1}]", 0xac00, 2, ATTR_ALL, 0, NULL, 0, NULL},
705 {"sbi333", "%rt3,[%ra3{+%i3u}]", 0xae00, 2, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 706 /* SEG06 bit10~bit9. */
707 {"addri36.sp", "%rt3,%i6u2", 0xb000, 2, ATTR_V3MUP, USE_REG (31), NULL, 0, NULL},
708 {"lwi45.fe", "=rt4,%fe5", 0xb200, 2, ATTR_V3MUP, USE_REG (8), NULL, 0, NULL},
709 {"lwi450", "=rt4,[%ra5]", 0xb400, 2, ATTR_ALL, 0, NULL, 0, NULL},
710 {"swi450", "%rt4,[%ra5]", 0xb600, 2, ATTR_ALL, 0, NULL, 0, NULL},
711 /* SEG07 bit7. */
35c08157
KLC		 712 {"lwi37", "=rt38,[$fp{+%i7u2}]", 0xb800, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL},
713 {"swi37", "%rt38,[$fp{+%i7u2}]", 0xb880, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL},
40c7a7cb
KLC		 714 /* SEG10_1 if Rt3=5. */
715 {"j8", "%i8s1", 0xd500, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
716 /* SEG11_2 bit7~bit5. */
717 {"jr5", "%ra5", 0xdd00, 2, ATTR_ALL, 0, NULL, 0, NULL},
718 {"jral5", "%ra5", 0xdd20, 2, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 719 {"ret5", "%ra5", 0xdd80, 2, ATTR_ALL, 0, NULL, 0, NULL},
720 {"add5.pc", "%ra5", 0xdda0, 2, ATTR_V3, 0, NULL, 0, NULL},
721 /* SEG11_3 if Ra5=30. */
722 {"ret5", "", 0xdd80 | RA5 (30), 2, ATTR_ALL, 0, NULL, 0, NULL},
723 /* SEG12 bit10~bit9. */
724 {"slts45", "%rt4,%ra5", 0xe000, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
725 {"slt45", "%rt4,%ra5", 0xe200, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
726 {"sltsi45", "%rt4,%i5u", 0xe400, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
727 {"slti45", "%rt4,%i5u", 0xe600, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
728 /* SEG13 bit10~bit9. */
729 {"break16", "%i5u", 0xea00, 2, ATTR_ALL, 0, NULL, 0, NULL},
730 {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
731 {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
732 /* SEG13_1 bit8. */
733 {"beqzs8", "%i8s1", 0xe800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL},
734 {"bnezs8", "%i8s1", 0xe900, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL},
40c7a7cb 735 /* SEG14 bit7. */
35c08157
KLC		 736 {"lwi37.sp", "=rt38,[+%i7u2]", 0xf000, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL},
737 {"swi37.sp", "%rt38,[+%i7u2]", 0xf080, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL},
40c7a7cb 738 /* SEG15 bit10~bit9. */
40c7a7cb
KLC		 739 {"movpi45", "=rt4,%pi5", 0xfa00, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
740 /* SEG15_1 bit8. */
741 {"movd44", "=rt5e,%ra5e", 0xfd00, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
742
743 /* SEG-BFMI333 bit2~bit0. */
744 {"zeb33", "=rt3,%ra3", 0x9600, 2, ATTR_ALL, 0, NULL, 0, NULL},
745 {"zeh33", "=rt3,%ra3", 0x9601, 2, ATTR_ALL, 0, NULL, 0, NULL},
746 {"seb33", "=rt3,%ra3", 0x9602, 2, ATTR_ALL, 0, NULL, 0, NULL},
747 {"seh33", "=rt3,%ra3", 0x9603, 2, ATTR_ALL, 0, NULL, 0, NULL},
748 {"xlsb33", "=rt3,%ra3", 0x9604, 2, ATTR_ALL, 0, NULL, 0, NULL},
749 {"x11b33", "=rt3,%ra3", 0x9605, 2, ATTR_ALL, 0, NULL, 0, NULL},
750 {"bmski33", "=rt3,%ia3u", 0x9606, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
751 {"fexti33", "=rt3,%ia3u", 0x9607, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
752 /* SEG-PUSHPOP25 bit8~bit7. */
753 {"push25", "%re2,%i5u3", 0xfc00, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
754 {"pop25", "%re2,%i5u3", 0xfc80, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
755 /* SEG-MISC33 bit2~bit0. */
756 {"neg33", "=rt3,%ra3", 0xfe02, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
757 {"not33", "=rt3,%ra3", 0xfe03, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
758 {"mul33", "=rt3,%ra3", 0xfe04, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
759 {"xor33", "=rt3,%ra3", 0xfe05, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
760 {"and33", "=rt3,%ra3", 0xfe06, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
761 {"or33", "=rt3,%ra3", 0xfe07, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
762 /* SEG-Alias instructions. */
763 {"nop16", "", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL},
40c7a7cb
KLC		 764
765 /* Saturation ext ISA. */
766 {"kaddw", "=rt,%ra,%rb", ALU2 (KADD), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
767 {"ksubw", "=rt,%ra,%rb", ALU2 (KSUB), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
4ec521f2
KLC		 768 {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
769 {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
40c7a7cb 770 {"kdmbb", "=rt,%ra,%rb", ALU2 (KMxy), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
4ec521f2
KLC		 771 {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
772 {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
773 {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (6) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
774 {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
775 {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
776 {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
777 {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (6) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
fbaf61ad
NC		 778 {"kslraw", "=rt,%ra,%rb", ALU2 (KSLRAW), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
779 {"ksll", "=rt,%ra,%rb", ALU2 (KSLRAW), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
780 {"kslraw.u", "=rt,%ra,%rb", ALU2 (KSLRAWu), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
4ec521f2
KLC		 781 {"rdov", "=rt", ALU2 (MFUSR) | N32_BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
782 {"clrov", "", ALU2 (MTUSR) | N32_BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
40c7a7cb
KLC		 783
784 /* Audio ext. instructions. */
785
fbaf61ad
NC		 786 {"amtari", "%aridxi,%imm16u", AUDIO (AMTARI), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
787 {"amtari", "%aridxi_mx,%imm16s", AUDIO (AMTARI), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
40c7a7cb
KLC		 788 /* N32_AEXT_AMADD */
789 {"alr2", "=a_rt,=a_ru,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x1 << 6), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
790 {"amaddl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADD) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
791 {"amaddl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADD) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
792 {"amaddl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
793 {"amaddl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
794 {"amaddsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADD) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
795 {"alr", "=a_rt,[%im5_i],%im5_m", AUDIO (AMADD) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
796 {"amadd", "=a_dx,%ra,%rb", AUDIO (AMADD), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
797 {"amabbs", "=a_dx,%ra,%rb", AUDIO (AMADD) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
798 /* N32_AEXT_AMSUB */
799 {"amsubl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
800 {"amsubl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
801 {"amsubl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
802 {"amsubl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
803 {"amsubsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
804 {"asr", "%ra,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
805 {"amsub", "=a_dx,%ra,%rb", AUDIO (AMSUB), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
806 {"amabts", "=a_dx,%ra,%rb", AUDIO (AMSUB) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
807 /* N32_AEXT_AMULT */
808 {"amultl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULT) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
809 {"amultl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULT) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
810 {"amultl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
811 {"amultl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
812 {"amultsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULT) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
813 {"ala", "=dxh,[%im5_i],%im5_m", AUDIO (AMULT) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
814 {"amult", "=a_dx,%ra,%rb", AUDIO (AMULT), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
815 {"amatbs", "=a_dx,%ra,%rb", AUDIO (AMULT) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
816 {"asats48", "=a_dx", AUDIO (AMULT) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
817 {"awext", "%ra,%a_dx,%i5u", AUDIO (AMULT) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
818 /* N32_AEXT_AMFAR */
819 {"amatts", "=a_dx,%ra,%rb", AUDIO (AMFAR) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
820 {"asa", "=dxh,[%im5_i],%im5_m", AUDIO (AMFAR) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
821 {"amtar", "%ra,%aridx", AUDIO (AMFAR) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
822 {"amtar2", "%ra,%aridx2", AUDIO (AMFAR) | (0x12 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
823 {"amfar", "=ra,%aridx", AUDIO (AMFAR) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
824 {"amfar2", "=ra,%aridx2", AUDIO (AMFAR) | (0x13 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
825 /* N32_AEXT_AMADDS */
826 {"amaddsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
827 {"amaddsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
828 {"amaddsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
829 {"amaddsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
830 {"amaddssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
831 {"aupi", "%im5_i,%im5_m", AUDIO (AMADDS) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
832 {"amadds", "=a_dx,%ra,%rb", AUDIO (AMADDS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
833 {"ambbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
834 {"amawbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
835 /* N32_AEXT_AMSUBS */
836 {"amsubsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
837 {"amsubsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
838 {"amsubsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
839 {"amsubsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
840 {"amsubssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
841 {"amsubs", "=a_dx,%ra,%rb", AUDIO (AMSUBS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
842 {"ambts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
843 {"amawts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
844 /* N32_AEXT_AMULTS */
845 {"amultsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
846 {"amultsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
847 {"amultsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
848 {"amultsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
849 {"amultssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
850 {"amults", "=a_dx,%ra,%rb", AUDIO (AMULTS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
851 {"amtbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
852 {"amwbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
853 /* N32_AEXT_AMNEGS */
854 {"amnegsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
855 {"amnegsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
856 {"amnegsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
857 {"amnegsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
858 {"amnegssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
859 {"amnegs", "=a_dx,%ra,%rb", AUDIO (AMNEGS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
860 {"amtts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
861 {"amwts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
862 /* N32_AEXT_AADDL */
863 {"aaddl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
864 {"asubl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
865 /* N32_AEXT_AMAWBS */
866 {"amawbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
867 {"amawbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
868 {"amawbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
869 {"amawbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
870 {"amawbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
871 /* N32_AEXT_AMAWTS */
872 {"amawtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
873 {"amawtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
874 {"amawtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
875 {"amawtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
876 {"amawtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
877 /* N32_AEXT_AMWBS */
878 {"amwbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
879 {"amwbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
880 {"amwbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
881 {"amwbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
882 {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
883 {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
884 /* N32_AEXT_AMWTS */
885 {"amwtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
886 {"amwtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
887 {"amwtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
888 {"amwtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
889 {"amwtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
890 /* N32_AEXT_AMABBS */
891 {"amabbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
892 {"amabbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
893 {"amabbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
894 {"amabbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
895 {"amabbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
896 /* N32_AEXT_AMABTS */
897 {"amabtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
898 {"amabtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
899 {"amabtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
900 {"amabtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
901 {"amabtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
902 /* N32_AEXT_AMATBS */
903 {"amatbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
904 {"amatbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
905 {"amatbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
906 {"amatbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
907 {"amatbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
908 /* N32_AEXT_AMATTS */
909 {"amattsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
910 {"amattsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
911 {"amattsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
912 {"amattsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
913 {"amattssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
914 /* N32_AEXT_AMBBS */
915 {"ambbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
916 {"ambbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
917 {"ambbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
918 {"ambbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
919 {"ambbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
920 /* N32_AEXT_AMBTS */
921 {"ambtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
922 {"ambtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
923 {"ambtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
924 {"ambtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
925 {"ambtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
926 /* N32_AEXT_AMTBS */
927 {"amtbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
928 {"amtbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
929 {"amtbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
930 {"amtbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
931 {"amtbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
932 /* N32_AEXT_AMTTS */
933 {"amttsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
934 {"amttsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
935 {"amttsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
936 {"amttsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
937 {"amttssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
fbaf61ad
NC		 938
939 /* DSP ISA. */
940 /* ALU2 Bit 9-6 = 0000. */
941 {"add64", "=rt,%ra,%rb", ALU2 (ADD64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
942 {"sub64", "=rt,%ra,%rb", ALU2 (SUB64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
943 {"smal", "=rt,%ra,%rb", ALU2 (SMAL), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
944 {"radd64", "=rt,%ra,%rb", ALU2 (RADD64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
945 {"rsub64", "=rt,%ra,%rb", ALU2 (RSUB64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
946 {"uradd64", "=rt,%ra,%rb", ALU2 (URADD64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
947 {"ursub64", "=rt,%ra,%rb", ALU2 (URSUB64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
948 {"kadd64", "=rt,%ra,%rb", ALU2 (KADD64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
949 {"ksub64", "=rt,%ra,%rb", ALU2 (KSUB64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
950 {"ukadd64", "=rt,%ra,%rb", ALU2 (UKADD64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
951 {"uksub64", "=rt,%ra,%rb", ALU2 (UKSUB64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
952 /* ALU2 Bit 9-6 = 0001. */
953 {"smar64", "=rt,%ra,%rb", ALU2_1 (SMAR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
954 {"umar64", "=rt,%ra,%rb", ALU2_1 (UMAR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
955 {"smsr64", "=rt,%ra,%rb", ALU2_1 (SMSR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
956 {"umsr64", "=rt,%ra,%rb", ALU2_1 (UMSR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
957 {"kmar64", "=rt,%ra,%rb", ALU2_1 (KMAR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
958 {"ukmar64", "=rt,%ra,%rb", ALU2_1 (UKMAR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
959 {"kmsr64", "=rt,%ra,%rb", ALU2_1 (KMSR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
960 {"ukmsr64", "=rt,%ra,%rb", ALU2_1 (UKMSR64), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
961 {"smalda", "=rt,%ra,%rb", ALU2_1 (SMALDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
962 {"smslda", "=rt,%ra,%rb", ALU2_1 (SMSLDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
963 {"smalds", "=rt,%ra,%rb", ALU2_1 (SMALDS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
964 {"smalbb", "=rt,%ra,%rb", ALU2_1 (SMALBB), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
965 {"smalxda", "=rt,%ra,%rb", ALU2_1 (SMALXDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
966 {"smslxda", "=rt,%ra,%rb", ALU2_1 (SMSLXDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
967 {"smalxds", "=rt,%ra,%rb", ALU2_1 (SMALXDS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
968 {"smalbt", "=rt,%ra,%rb", ALU2_1 (SMALBT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
969 {"smalbt", "=rt,%ra,%rb", ALU2_1 (SMALBT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
970 {"smaldrs", "=rt,%ra,%rb", ALU2_1 (SMALDRS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
971 {"smaltt", "=rt,%ra,%rb", ALU2_1 (SMALTT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
972 {"smds", "=rt,%ra,%rb", ALU2_1 (SMDS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
973 {"smxds", "=rt,%ra,%rb", ALU2_1 (SMXDS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
974 {"smdrs", "=rt,%ra,%rb", ALU2_1 (SMDRS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
975 {"kmadrs", "=rt,%ra,%rb", ALU2_1 (KMADRS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
976 {"kmads", "=rt,%ra,%rb", ALU2_1 (KMADS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
977 {"kmaxds", "=rt,%ra,%rb", ALU2_1 (KMAXDS), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
978 /* DSP MISC. */
979 {"bpick", "=rt,%ra,%rb,%rd", MISC (BPICK), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
980 /* ALU_2 KMxy. */
981 {"khm16", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (9) | N32_BIT (8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
982 {"khmx16", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (9) | N32_BIT (8) | N32_BIT (6), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
983 {"smul16", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (9), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
984 {"smulx16", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (9) | N32_BIT (6), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
985 {"umul16", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (9) | N32_BIT (7), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
986 {"umulx16", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (9) | N32_BIT (7) | N32_BIT (6), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
987 /* ALU2 Bit 9-6 = 0010. */
988 {"kadd16", "=rt,%ra,%rb", ALU2_2 (KADD16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
989 {"ksub16", "=rt,%ra,%rb", ALU2_2 (KSUB16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
990 {"kcras16", "=rt,%ra,%rb", ALU2_2 (KCRAS16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
991 {"kcrsa16", "=rt,%ra,%rb", ALU2_2 (KCRSA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
992 {"kadd8", "=rt,%ra,%rb", ALU2_2 (KADD8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
993 {"ksub8", "=rt,%ra,%rb", ALU2_2 (KSUB8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
994 {"wext", "=rt,%ra,%rb", ALU2_2 (WEXT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
995 {"wexti", "=rt,%ra,%ib5u", ALU2_2 (WEXTI), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
996 {"ukadd16", "=rt,%ra,%rb", ALU2_2 (UKADD16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
997 {"uksub16", "=rt,%ra,%rb", ALU2_2 (UKSUB16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
998 {"ukcras16", "=rt,%ra,%rb", ALU2_2 (UKCRAS16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
999 {"ukcrsa16", "=rt,%ra,%rb", ALU2_2 (UKCRSA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1000 {"ukadd8", "=rt,%ra,%rb", ALU2_2 (UKADD8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1001 {"uksub8", "=rt,%ra,%rb", ALU2_2 (UKSUB8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1002 /* ONEOP. */
1003#define DSP_ONEOP(n) ((n) << 10)
1004 {"sunpkd810", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x0), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1005 {"sunpkd820", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x1), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1006 {"sunpkd830", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x2), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1007 {"sunpkd831", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x3), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1008 {"zunpkd810", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x4), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1009 {"zunpkd820", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x5), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1010 {"zunpkd830", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x6), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1011 {"zunpkd831", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x7), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1012 {"kabs", "=rt,%ra", ALU2 (ABS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
1013 {"kabs16", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0x8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1014 {"kabs8", "=rt,%ra", ALU2_2 (ONEOP) | DSP_ONEOP (0xc), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1015 {"insb", "=rt,%ra,%ib2u", ALU2_2 (ONEOP) | DSP_ONEOP (0x10), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1016 {"smbb", "=rt,%ra,%rb", ALU2_2 (SMBB), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1017 {"smbt", "=rt,%ra,%rb", ALU2_2 (SMBT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1018 {"smtt", "=rt,%ra,%rb", ALU2_2 (SMTT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1019 {"kmabb", "=rt,%ra,%rb", ALU2_2 (KMABB), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1020 {"kmabt", "=rt,%ra,%rb", ALU2_2 (KMABT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1021 {"kmatt", "=rt,%ra,%rb", ALU2_2 (KMATT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1022 {"kmda", "=rt,%ra,%rb", ALU2_2 (KMDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1023 {"kmxda", "=rt,%ra,%rb", ALU2_2 (KMXDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1024 {"kmada", "=rt,%ra,%rb", ALU2_2 (KMADA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1025 {"kmaxda", "=rt,%ra,%rb", ALU2_2 (KMAXDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1026 {"kmsda", "=rt,%ra,%rb", ALU2_2 (KMSDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1027 {"kmsxda", "=rt,%ra,%rb", ALU2_2 (KMSXDA), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1028 {"radd16", "=rt,%ra,%rb", ALU2_2 (RADD16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1029 {"rsub16", "=rt,%ra,%rb", ALU2_2 (RSUB16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1030 {"rcras16", "=rt,%ra,%rb", ALU2_2 (RCRAS16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1031 {"rcrsa16", "=rt,%ra,%rb", ALU2_2 (RCRSA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1032 {"radd8", "=rt,%ra,%rb", ALU2_2 (RADD8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1033 {"rsub8", "=rt,%ra,%rb", ALU2_2 (RSUB8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1034 {"raddw", "=rt,%ra,%rb", ALU2_2 (RADDW), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1035 {"rsubw", "=rt,%ra,%rb", ALU2_2 (RSUBW), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1036 {"uradd16", "=rt,%ra,%rb", ALU2_2 (URADD16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1037 {"ursub16", "=rt,%ra,%rb", ALU2_2 (URSUB16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1038 {"urcras16", "=rt,%ra,%rb", ALU2_2 (URCRAS16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1039 {"urcrsa16", "=rt,%ra,%rb", ALU2_2 (URCRSA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1040 {"uradd8", "=rt,%ra,%rb", ALU2_2 (URADD8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1041 {"ursub8", "=rt,%ra,%rb", ALU2_2 (URSUB8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1042 {"uraddw", "=rt,%ra,%rb", ALU2_2 (URADDW), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1043 {"ursubw", "=rt,%ra,%rb", ALU2_2 (URSUBW), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1044 {"add16", "=rt,%ra,%rb", ALU2_2 (ADD16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1045 {"sub16", "=rt,%ra,%rb", ALU2_2 (SUB16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1046 {"cras16", "=rt,%ra,%rb", ALU2_2 (CRAS16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1047 {"crsa16", "=rt,%ra,%rb", ALU2_2 (CRSA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1048 {"add8", "=rt,%ra,%rb", ALU2_2 (ADD8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1049 {"sub8", "=rt,%ra,%rb", ALU2_2 (SUB8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1050 {"bitrev", "=rt,%ra,%rb", ALU2_2 (BITREV), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1051 {"bitrevi", "=rt,%ra,%ib5u", ALU2_2 (BITREVI), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1052 {"smmul", "=rt,%ra,%rb", ALU2_2 (SMMUL), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1053 {"smmul.u", "=rt,%ra,%rb", ALU2_2 (SMMULu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1054 {"kmmac", "=rt,%ra,%rb", ALU2_2 (KMMAC), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1055 {"kmmac.u", "=rt,%ra,%rb", ALU2_2 (KMMACu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1056 {"kmmsb", "=rt,%ra,%rb", ALU2_2 (KMMSB), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1057 {"kmmsb.u", "=rt,%ra,%rb", ALU2_2 (KMMSBu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1058 {"kwmmul", "=rt,%ra,%rb", ALU2_2 (KWMMUL), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1059 {"kwmmul.u", "=rt,%ra,%rb", ALU2_2 (KWMMULu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1060 /* ALU2 Bit 9-6 = 0010. */
1061 {"smmwb", "=rt,%ra,%rb", ALU2_3 (SMMWB), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1062 {"smmwb.u", "=rt,%ra,%rb", ALU2_3 (SMMWBu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1063 {"smmwt", "=rt,%ra,%rb", ALU2_3 (SMMWT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1064 {"smmwt.u", "=rt,%ra,%rb", ALU2_3 (SMMWTu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1065 {"kmmawb", "=rt,%ra,%rb", ALU2_3 (KMMAWB), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1066 {"kmmawb.u", "=rt,%ra,%rb", ALU2_3 (KMMAWBu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1067 {"kmmawt", "=rt,%ra,%rb", ALU2_3 (KMMAWT), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1068 {"kmmawt.u", "=rt,%ra,%rb", ALU2_3 (KMMAWTu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1069 {"pktt16", "=rt,%ra,%rb", ALU2_3 (PKTT16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1070 {"pktb16", "=rt,%ra,%rb", ALU2_3 (PKTB16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1071 {"pkbt16", "=rt,%ra,%rb", ALU2_3 (PKBT16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1072 {"pkbb16", "=rt,%ra,%rb", ALU2_3 (PKBB16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1073 {"sclip32", "=rt,%ra,%ib5u", ALU2 (CLIPS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
1074 {"sclip16", "=rt,%ra,%ib4u", ALU2_3 (SCLIP16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1075 {"smax16", "=rt,%ra,%rb", ALU2_3 (SMAX16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1076 {"smax8", "=rt,%ra,%rb", ALU2_3 (SMAX8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1077 {"uclip32", "=rt,%ra,%ib5u", ALU2 (CLIP), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
1078 {"uclip16", "=rt,%ra,%ib4u", ALU2_3 (UCLIP16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1079 {"umax16", "=rt,%ra,%rb", ALU2_3 (UMAX16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1080 {"umax8", "=rt,%ra,%rb", ALU2_3 (UMAX8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1081 {"sra16", "=rt,%ra,%rb", ALU2_3 (SRA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1082 {"sra16.u", "=rt,%ra,%rb", ALU2_3 (SRA16u), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1083 {"srl16", "=rt,%ra,%rb", ALU2_3 (SRL16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1084 {"srl16.u", "=rt,%ra,%rb", ALU2_3 (SRL16u), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1085 {"sll16", "=rt,%ra,%rb", ALU2_3 (SLL16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1086 {"kslra16", "=rt,%ra,%rb", ALU2_3 (KSLRA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1087 {"ksll16", "=rt,%ra,%rb", ALU2_3 (KSLRA16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1088 {"kslra16.u", "=rt,%ra,%rb", ALU2_3 (KSLRA16u), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1089 {"sra.u", "=rt,%ra,%rb", ALU2_3 (SRAu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1090 {"srai16", "=rt,%ra,%ib4u", ALU2_3 (SRAI16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1091 {"srai16.u", "=rt,%ra,%ib4u", ALU2_3 (SRAI16u), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1092 {"srli16", "=rt,%ra,%ib4u", ALU2_3 (SRLI16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1093 {"srli16.u", "=rt,%ra,%ib4u", ALU2_3 (SRLI16u), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1094 {"slli16", "=rt,%ra,%ib4u", ALU2_3 (SLLI16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1095 {"kslli16", "=rt,%ra,%ib4u", ALU2_3 (KSLLI16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1096 {"kslli", "=rt,%ra,%ib5u", ALU2_3 (KSLLI), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1097 {"srai.u", "=rt,%ra,%ib5u", ALU2_3 (SRAIu), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1098 {"cmpeq16", "=rt,%ra,%rb", ALU2_3 (CMPEQ16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1099 {"scmplt16", "=rt,%ra,%rb", ALU2_3 (SCMPLT16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1100 {"scmple16", "=rt,%ra,%rb", ALU2_3 (SCMPLE16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1101 {"smin16", "=rt,%ra,%rb", ALU2_3 (SMIN16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1102 {"cmpeq8", "=rt,%ra,%rb", ALU2_3 (CMPEQ8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1103 {"scmplt8", "=rt,%ra,%rb", ALU2_3 (SCMPLT8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1104 {"scmple8", "=rt,%ra,%rb", ALU2_3 (SCMPLE8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1105 {"smin8", "=rt,%ra,%rb", ALU2_3 (SMIN8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1106 {"ucmplt16", "=rt,%ra,%rb", ALU2_3 (UCMPLT16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1107 {"ucmple16", "=rt,%ra,%rb", ALU2_3 (UCMPLE16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1108 {"umin16", "=rt,%ra,%rb", ALU2_3 (UMIN16), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1109 {"ucmplt8", "=rt,%ra,%rb", ALU2_3 (UCMPLT8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1110 {"ucmple8", "=rt,%ra,%rb", ALU2_3 (UCMPLE8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1111 {"umin8", "=rt,%ra,%rb", ALU2_3 (UMIN8), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},
1112 {"mtlbi", "%i16s1", BR2 (SOP0) | N32_BIT (20), 4, ATTR (ZOL) | ATTR (DSP_ISAEXT) | ATTR (PCREL), 0, NULL, 0, NULL},
1113 {"mtlei", "%i16s1", BR2 (SOP0) | N32_BIT (21), 4, ATTR (ZOL) | ATTR (DSP_ISAEXT) | ATTR (PCREL), 0, NULL, 0, NULL},
40c7a7cb 1114 {NULL, NULL, 0, 0, 0, 0, NULL, 0, NULL},
35c08157
KLC		 1115};
1116
40c7a7cb 1117const keyword_t keyword_gpr[] =
35c08157 1118{
40c7a7cb 1119 /* Standard names. */
35c08157
KLC		 1120 {"r0", 0, ATTR (RDREG)}, {"r1", 1, ATTR (RDREG)}, {"r2", 2, ATTR (RDREG)},
1121 {"r3", 3, ATTR (RDREG)}, {"r4", 4, ATTR (RDREG)}, {"r5", 5, ATTR (RDREG)},
1122 {"r6", 6, ATTR (RDREG)}, {"r7", 7, ATTR (RDREG)}, {"r8", 8, ATTR (RDREG)},
40c7a7cb
KLC		 1123 {"r9", 9, ATTR (RDREG)}, {"r10", 10, ATTR (RDREG)}, {"r11", 11, 0},
1124 {"r12", 12, 0}, {"r13", 13, 0}, {"r14", 14, 0}, {"r15", 15, ATTR (RDREG)},
1125 {"r16", 16, 0}, {"r17", 17, 0}, {"r18", 18, 0}, {"r19", 19, 0},
1126 {"r20", 20, 0}, {"r21", 21, 0}, {"r22", 22, 0}, {"r23", 23, 0},
1127 {"r24", 24, 0}, {"r25", 25, 0},
1128 {"p0", 26, 0}, {"p1", 27, 0},
1129 {"fp", 28, ATTR (RDREG)}, {"gp", 29, ATTR (RDREG)},
1130 {"lp", 30, ATTR (RDREG)}, {"sp", 31, ATTR (RDREG)},
35c08157
KLC		 1131 {"r26", 26, 0}, {"r27", 27, 0},
1132 {"r28", 28, ATTR (RDREG)}, {"r29", 29, ATTR (RDREG)},
1133 {"r30", 30, ATTR (RDREG)}, {"r31", 31, ATTR (RDREG)},
40c7a7cb
KLC		 1134 /* Names for parameter passing. */
1135 {"a0", 0, ATTR (RDREG)}, {"a1", 1, ATTR (RDREG)},
1136 {"a2", 2, ATTR (RDREG)}, {"a3", 3, ATTR (RDREG)},
1137 {"a4", 4, ATTR (RDREG)}, {"a5", 5, ATTR (RDREG)},
1138 /* Names reserved for 5-bit addressing only. */
1139 {"s0", 6, ATTR (RDREG)}, {"s1", 7, ATTR (RDREG)},
1140 {"s2", 8, ATTR (RDREG)}, {"s3", 9, ATTR (RDREG)},
1141 {"s4", 10, ATTR (RDREG)}, {"s5", 11, 0}, {"s6", 12, 0}, {"s7", 13, 0},
1142 {"s8", 14, 0}, {"s9", 28, ATTR (RDREG)},
1143 {"ta", 15, ATTR (RDREG)},
1144 {"t0", 16, 0}, {"t1", 17, 0}, {"t2", 18, 0}, {"t3", 19, 0},
1145 {"t4", 20, 0}, {"t5", 21, 0}, {"t6", 22, 0}, {"t7", 23, 0},
1146 {"t8", 24, 0}, {"t9", 25, 0},
1147 /* Names reserved for 4-bit addressing only. */
1148 {"h0", 0, ATTR (RDREG)}, {"h1", 1, ATTR (RDREG)},
1149 {"h2", 2, ATTR (RDREG)}, {"h3", 3, ATTR (RDREG)},
1150 {"h4", 4, ATTR (RDREG)}, {"h5", 5, ATTR (RDREG)},
1151 {"h6", 6, ATTR (RDREG)}, {"h7", 7, ATTR (RDREG)},
1152 {"h8", 8, ATTR (RDREG)}, {"h9", 9, ATTR (RDREG)},
1153 {"h10", 10, ATTR (RDREG)}, {"h11", 11, 0},
1154 {"h12", 16, 0}, {"h13", 17, 0}, {"h14", 18, 0}, {"h15", 19, 0},
1155 /* Names reserved for 3-bit addressing only. */
1156 {"o0", 0, ATTR (RDREG)}, {"o1", 1, ATTR (RDREG)},
1157 {"o2", 2, ATTR (RDREG)}, {"o3", 3, ATTR (RDREG)},
1158 {"o4", 4, ATTR (RDREG)}, {"o5", 5, ATTR (RDREG)},
1159 {"o6", 6, ATTR (RDREG)}, {"o7", 7, ATTR (RDREG)},
35c08157
KLC		 1160 {NULL, 0, 0}
1161};
1162
40c7a7cb 1163const keyword_t keyword_usr[] =
35c08157
KLC		 1164{
1165 {"d0.lo", USRIDX (0, 0), 0},
1166 {"d0.hi", USRIDX (0, 1), 0},
1167 {"d1.lo", USRIDX (0, 2), 0},
1168 {"d1.hi", USRIDX (0, 3), 0},
fbaf61ad
NC		 1169 {"lb", USRIDX (0, 25), 0},
1170 {"le", USRIDX (0, 26), 0},
1171 {"lc", USRIDX (0, 27), 0},
35c08157
KLC		 1172 {"itb", USRIDX (0, 28), 0},
1173 {"ifc_lp", USRIDX (0, 29), 0},
1174 {"pc", USRIDX (0, 31), 0},
1175
1176 {"dma_cfg", USRIDX (1, 0), 0},
1177 {"dma_gcsw", USRIDX (1, 1), 0},
1178 {"dma_chnsel", USRIDX (1, 2), 0},
1179 {"dma_act", USRIDX (1, 3), 0},
1180 {"dma_setup", USRIDX (1, 4), 0},
1181 {"dma_isaddr", USRIDX (1, 5), 0},
1182 {"dma_esaddr", USRIDX (1, 6), 0},
1183 {"dma_tcnt", USRIDX (1, 7), 0},
1184 {"dma_status", USRIDX (1, 8), 0},
1185 {"dma_2dset", USRIDX (1, 9), 0},
1186 {"dma_rcnt", USRIDX (1, 23), 0},
1187 {"dma_hstatus", USRIDX (1, 24), 0},
1188 {"dma_2dsctl", USRIDX (1, 25), 0},
1189
1190 {"pfmc0", USRIDX (2, 0), 0},
1191 {"pfmc1", USRIDX (2, 1), 0},
1192 {"pfmc2", USRIDX (2, 2), 0},
1193 {"pfm_ctl", USRIDX (2, 4), 0},
1194
1195 {NULL, 0, 0}
1196};
1197
40c7a7cb 1198const keyword_t keyword_dxr[] =
35c08157
KLC		 1199{
1200 {"d0", 0, 0}, {"d1", 1, 0}, {NULL, 0, 0}
1201};
1202
40c7a7cb 1203const keyword_t keyword_sr[] =
35c08157 1204{
40c7a7cb
KLC		 1205 {"cpu_ver", SRIDX (0, 0, 0), 0}, {"cr0", SRIDX (0, 0, 0), 0},
1206 {"icm_cfg", SRIDX (0, 1, 0), 0}, {"cr1", SRIDX (0, 1, 0), 0},
1207 {"dcm_cfg", SRIDX (0, 2, 0), 0}, {"cr2", SRIDX (0, 2, 0), 0},
1208 {"mmu_cfg", SRIDX (0, 3, 0), 0}, {"cr3", SRIDX (0, 3, 0), 0},
1209 {"msc_cfg", SRIDX (0, 4, 0), 0}, {"cr4", SRIDX (0, 4, 0), 0},
e5fe4957 1210 {"msc_cfg2", SRIDX (0, 4, 1), 0}, {"cr7", SRIDX (0, 4, 1), 0},
40c7a7cb
KLC		 1211 {"core_id", SRIDX (0, 0, 1), 0}, {"cr5", SRIDX (0, 0, 1), 0},
1212 {"fucop_exist", SRIDX (0, 5, 0), 0}, {"cr6", SRIDX (0, 5, 0), 0},
1213
1214 {"psw", SRIDX (1, 0, 0), 0}, {"ir0", SRIDX (1, 0, 0), 0},
1215 {"ipsw", SRIDX (1, 0, 1), 0}, {"ir1", SRIDX (1, 0, 1), 0},
1216 {"p_ipsw", SRIDX (1, 0, 2), 0}, {"ir2", SRIDX (1, 0, 2), 0},
1217 {"ivb", SRIDX (1, 1, 1), 0}, {"ir3", SRIDX (1, 1, 1), 0},
1218 {"eva", SRIDX (1, 2, 1), 0}, {"ir4", SRIDX (1, 2, 1), 0},
1219 {"p_eva", SRIDX (1, 2, 2), 0}, {"ir5", SRIDX (1, 2, 2), 0},
1220 {"itype", SRIDX (1, 3, 1), 0}, {"ir6", SRIDX (1, 3, 1), 0},
1221 {"p_itype", SRIDX (1, 3, 2), 0}, {"ir7", SRIDX (1, 3, 2), 0},
1222 {"merr", SRIDX (1, 4, 1), 0}, {"ir8", SRIDX (1, 4, 1), 0},
1223 {"ipc", SRIDX (1, 5, 1), 0}, {"ir9", SRIDX (1, 5, 1), 0},
1224 {"p_ipc", SRIDX (1, 5, 2), 0}, {"ir10", SRIDX (1, 5, 2), 0},
1225 {"oipc", SRIDX (1, 5, 3), 0}, {"ir11", SRIDX (1, 5, 3), 0},
fbaf61ad 1226 {"dipc", SRIDX (1, 5, 3), 0},
40c7a7cb
KLC		 1227 {"p_p0", SRIDX (1, 6, 2), 0}, {"ir12", SRIDX (1, 6, 2), 0},
1228 {"p_p1", SRIDX (1, 7, 2), 0}, {"ir13", SRIDX (1, 7, 2), 0},
1229 {"int_mask", SRIDX (1, 8, 0), 0}, {"ir14", SRIDX (1, 8, 0), 0},
1230 {"int_pend", SRIDX (1, 9, 0), 0}, {"ir15", SRIDX (1, 9, 0), 0},
1231 {"sp_usr", SRIDX (1, 10, 0), 0}, {"ir16", SRIDX (1, 10, 0), 0},
1232 {"sp_priv", SRIDX (1, 10, 1), 0}, {"ir17", SRIDX (1, 10, 1), 0},
1233 {"int_pri", SRIDX (1, 11, 0), 0}, {"ir18", SRIDX (1, 11, 0), 0},
1234 {"int_ctrl", SRIDX (1, 1, 2), 0}, {"ir19", SRIDX (1, 1, 2), 0},
1235 {"sp_usr1", SRIDX (1, 10, 2), 0}, {"ir20", SRIDX (1, 10, 2), 0},
1236 {"sp_priv1", SRIDX (1, 10, 3), 0}, {"ir21", SRIDX (1, 10, 3), 0},
1237 {"sp_usr2", SRIDX (1, 10, 4), 0}, {"ir22", SRIDX (1, 10, 4), 0},
1238 {"sp_priv2", SRIDX (1, 10, 5), 0}, {"ir23", SRIDX (1, 10, 5), 0},
1239 {"sp_usr3", SRIDX (1, 10, 6), 0}, {"ir24", SRIDX (1, 10, 6), 0},
1240 {"sp_priv3", SRIDX (1, 10, 7), 0}, {"ir25", SRIDX (1, 10, 7), 0},
1241 {"int_mask2", SRIDX (1, 8, 1), 0}, {"ir26", SRIDX (1, 8, 1), 0},
1242 {"int_pend2", SRIDX (1, 9, 1), 0}, {"ir27", SRIDX (1, 9, 1), 0},
1243 {"int_pri2", SRIDX (1, 11, 1), 0}, {"ir28", SRIDX (1, 11, 1), 0},
1244 {"int_trigger", SRIDX (1, 9, 4), 0}, {"ir29", SRIDX (1, 9, 4), 0},
1245 {"int_gpr_push_dis", SRIDX(1, 1, 3), 0}, {"ir30", SRIDX (1, 1, 3), 0},
fbaf61ad
NC		 1246 {"int_mask3", SRIDX(1, 8, 2), 0}, {"ir31", SRIDX (1, 8, 2), 0},
1247 {"int_pend3", SRIDX(1, 9, 2), 0}, {"ir32", SRIDX (1, 9, 2), 0},
1248 {"int_pri3", SRIDX(1, 11, 2), 0}, {"ir33", SRIDX (1, 11, 2), 0},
1249 {"int_pri4", SRIDX(1, 11, 3), 0}, {"ir34", SRIDX (1, 11, 3), 0},
1250 {"int_trigger2", SRIDX(1, 9, 5), 0}, {"ir35", SRIDX (1, 9, 5), 0},
40c7a7cb
KLC		 1251
1252 {"mmu_ctl", SRIDX (2, 0, 0), 0}, {"mr0", SRIDX (2, 0, 0), 0},
1253 {"l1_pptb", SRIDX (2, 1, 0), 0}, {"mr1", SRIDX (2, 1, 0), 0},
1254 {"tlb_vpn", SRIDX (2, 2, 0), 0}, {"mr2", SRIDX (2, 2, 0), 0},
1255 {"tlb_data", SRIDX (2, 3, 0), 0}, {"mr3", SRIDX (2, 3, 0), 0},
1256 {"tlb_misc", SRIDX (2, 4, 0), 0}, {"mr4", SRIDX (2, 4, 0), 0},
1257 {"vlpt_idx", SRIDX (2, 5, 0), 0}, {"mr5", SRIDX (2, 5, 0), 0},
1258 {"ilmb", SRIDX (2, 6, 0), 0}, {"mr6", SRIDX (2, 6, 0), 0},
1259 {"dlmb", SRIDX (2, 7, 0), 0}, {"mr7", SRIDX (2, 7, 0), 0},
1260 {"cache_ctl", SRIDX (2, 8, 0), 0}, {"mr8", SRIDX (2, 8, 0), 0},
1261 {"hsmp_saddr", SRIDX (2, 9, 0), 0}, {"mr9", SRIDX (2, 9, 0), 0},
1262 {"hsmp_eaddr", SRIDX (2, 9, 1), 0}, {"mr10", SRIDX (2, 9, 1), 0},
1263 {"bg_region", SRIDX (2, 0, 1), 0}, {"mr11", SRIDX (2, 0, 1), 0},
1264
1265 {"pfmc0", SRIDX (4, 0, 0), 0}, {"pfr0", SRIDX (4, 0, 0), 0},
1266 {"pfmc1", SRIDX (4, 0, 1), 0}, {"pfr1", SRIDX (4, 0, 1), 0},
1267 {"pfmc2", SRIDX (4, 0, 2), 0}, {"pfr2", SRIDX (4, 0, 2), 0},
1268 {"pfm_ctl", SRIDX (4, 1, 0), 0}, {"pfr3", SRIDX (4, 1, 0), 0},
fbaf61ad 1269 {"pft_ctl", SRIDX (4, 2, 0), 0}, {"pfr4", SRIDX (4, 2, 0), 0},
e5fe4957
KLC		 1270 {"hsp_ctl", SRIDX (4, 6, 0), 0}, {"hspr0", SRIDX (4, 6, 0), 0},
1271 {"sp_bound", SRIDX (4, 6, 1), 0}, {"hspr1", SRIDX (4, 6, 1), 0},
1272 {"sp_bound_priv", SRIDX (4, 6, 2), 0},{"hspr2", SRIDX (4, 6, 2), 0},
fbaf61ad
NC		 1273 {"sp_base", SRIDX (4, 6, 3), 0}, {"hspr3", SRIDX (4, 6, 3), 0},
1274 {"sp_base_priv", SRIDX (4, 6, 4), 0}, {"hspr4", SRIDX (4, 6, 4), 0},
40c7a7cb
KLC		 1275
1276 {"dma_cfg", SRIDX (5, 0, 0), 0}, {"dmar0", SRIDX (5, 0, 0), 0},
1277 {"dma_gcsw", SRIDX (5, 1, 0), 0}, {"dmar1", SRIDX (5, 1, 0), 0},
1278 {"dma_chnsel", SRIDX (5, 2, 0), 0}, {"dmar2", SRIDX (5, 2, 0), 0},
1279 {"dma_act", SRIDX (5, 3, 0), 0}, {"dmar3", SRIDX (5, 3, 0), 0},
1280 {"dma_setup", SRIDX (5, 4, 0), 0}, {"dmar4", SRIDX (5, 4, 0), 0},
1281 {"dma_isaddr", SRIDX (5, 5, 0), 0}, {"dmar5", SRIDX (5, 5, 0), 0},
1282 {"dma_esaddr", SRIDX (5, 6, 0), 0}, {"dmar6", SRIDX (5, 6, 0), 0},
1283 {"dma_tcnt", SRIDX (5, 7, 0), 0}, {"dmar7", SRIDX (5, 7, 0), 0},
1284 {"dma_status", SRIDX (5, 8, 0), 0}, {"dmar8", SRIDX (5, 8, 0), 0},
1285 {"dma_2dset", SRIDX (5, 9, 0), 0}, {"dmar9", SRIDX (5, 9, 0), 0},
1286 {"dma_2dsctl", SRIDX (5, 9, 1), 0}, {"dmar10", SRIDX (5, 9, 1), 0},
1287 {"dma_rcnt", SRIDX (5, 7, 1), 0}, {"dmar11", SRIDX (5, 7, 1), 0},
1288 {"dma_hstatus", SRIDX (5, 8, 1), 0}, {"dmar12", SRIDX (5, 8, 1), 0},
1289
1290 {"sdz_ctl", SRIDX (2, 15, 0), 0}, {"idr0", SRIDX (2, 15, 0), 0},
1291 {"misc_ctl", SRIDX (2, 15, 1), 0}, {"n12misc_ctl", SRIDX (2, 15, 1), 0},
1292 {"idr1", SRIDX (2, 15, 1), 0},
e5fe4957 1293 {"ecc_misc", SRIDX (2, 15, 2), 0}, {"idr2", SRIDX (2, 15, 2), 0},
40c7a7cb
KLC		 1294
1295 {"secur0", SRIDX (6, 0, 0), 0}, {"sfcr", SRIDX (6, 0, 0), 0},
e5fe4957 1296 {"secur1", SRIDX (6, 1, 0), 0}, {"sign", SRIDX (6, 1, 0), 0},
fbaf61ad
NC		 1297 {"secur2", SRIDX (6, 1, 1), 0}, {"isign", SRIDX (6, 1, 1), 0},
1298 {"secur3", SRIDX (6, 1, 2), 0}, {"p_isign", SRIDX (6, 1, 2), 0},
35c08157
KLC		 1299
1300 {"prusr_acc_ctl", SRIDX (4, 4, 0), 0},
40c7a7cb
KLC		 1301 {"fucpr", SRIDX (4, 5, 0), 0}, {"fucop_ctl", SRIDX (4, 5, 0), 0},
1302
1303 {"bpc0", SRIDX (3, 0, 0), 0}, {"dr0", SRIDX (3, 0, 0), 0},
fbaf61ad
NC		 1304 {"bpc1", SRIDX (3, 0, 1), 0}, {"dr5", SRIDX (3, 0, 1), 0},
1305 {"bpc2", SRIDX (3, 0, 2), 0}, {"dr10", SRIDX (3, 0, 2), 0},
1306 {"bpc3", SRIDX (3, 0, 3), 0}, {"dr15", SRIDX (3, 0, 3), 0},
1307 {"bpc4", SRIDX (3, 0, 4), 0}, {"dr20", SRIDX (3, 0, 4), 0},
1308 {"bpc5", SRIDX (3, 0, 5), 0}, {"dr25", SRIDX (3, 0, 5), 0},
1309 {"bpc6", SRIDX (3, 0, 6), 0}, {"dr30", SRIDX (3, 0, 6), 0},
1310 {"bpc7", SRIDX (3, 0, 7), 0}, {"dr35", SRIDX (3, 0, 7), 0},
1311 {"bpa0", SRIDX (3, 1, 0), 0}, {"dr1", SRIDX (3, 1, 0), 0},
1312 {"bpa1", SRIDX (3, 1, 1), 0}, {"dr6", SRIDX (3, 1, 1), 0},
1313 {"bpa2", SRIDX (3, 1, 2), 0}, {"dr11", SRIDX (3, 1, 2), 0},
1314 {"bpa3", SRIDX (3, 1, 3), 0}, {"dr16", SRIDX (3, 1, 3), 0},
1315 {"bpa4", SRIDX (3, 1, 4), 0}, {"dr21", SRIDX (3, 1, 4), 0},
1316 {"bpa5", SRIDX (3, 1, 5), 0}, {"dr26", SRIDX (3, 1, 5), 0},
1317 {"bpa6", SRIDX (3, 1, 6), 0}, {"dr31", SRIDX (3, 1, 6), 0},
1318 {"bpa7", SRIDX (3, 1, 7), 0}, {"dr36", SRIDX (3, 1, 7), 0},
1319 {"bpam0", SRIDX (3, 2, 0), 0}, {"dr2", SRIDX (3, 2, 0), 0},
1320 {"bpam1", SRIDX (3, 2, 1), 0}, {"dr7", SRIDX (3, 2, 1), 0},
1321 {"bpam2", SRIDX (3, 2, 2), 0}, {"dr12", SRIDX (3, 2, 2), 0},
1322 {"bpam3", SRIDX (3, 2, 3), 0}, {"dr17", SRIDX (3, 2, 3), 0},
1323 {"bpam4", SRIDX (3, 2, 4), 0}, {"dr22", SRIDX (3, 2, 4), 0},
1324 {"bpam5", SRIDX (3, 2, 5), 0}, {"dr27", SRIDX (3, 2, 5), 0},
1325 {"bpam6", SRIDX (3, 2, 6), 0}, {"dr32", SRIDX (3, 2, 6), 0},
1326 {"bpam7", SRIDX (3, 2, 7), 0}, {"dr37", SRIDX (3, 2, 7), 0},
1327 {"bpv0", SRIDX (3, 3, 0), 0}, {"dr3", SRIDX (3, 3, 0), 0},
1328 {"bpv1", SRIDX (3, 3, 1), 0}, {"dr8", SRIDX (3, 3, 1), 0},
1329 {"bpv2", SRIDX (3, 3, 2), 0}, {"dr13", SRIDX (3, 3, 2), 0},
1330 {"bpv3", SRIDX (3, 3, 3), 0}, {"dr18", SRIDX (3, 3, 3), 0},
1331 {"bpv4", SRIDX (3, 3, 4), 0}, {"dr23", SRIDX (3, 3, 4), 0},
1332 {"bpv5", SRIDX (3, 3, 5), 0}, {"dr28", SRIDX (3, 3, 5), 0},
1333 {"bpv6", SRIDX (3, 3, 6), 0}, {"dr33", SRIDX (3, 3, 6), 0},
1334 {"bpv7", SRIDX (3, 3, 7), 0}, {"dr38", SRIDX (3, 3, 7), 0},
1335 {"bpcid0", SRIDX (3, 4, 0), 0}, {"dr4", SRIDX (3, 4, 0), 0},
1336 {"bpcid1", SRIDX (3, 4, 1), 0}, {"dr9", SRIDX (3, 4, 1), 0},
1337 {"bpcid2", SRIDX (3, 4, 2), 0}, {"dr14", SRIDX (3, 4, 2), 0},
1338 {"bpcid3", SRIDX (3, 4, 3), 0}, {"dr19", SRIDX (3, 4, 3), 0},
1339 {"bpcid4", SRIDX (3, 4, 4), 0}, {"dr24", SRIDX (3, 4, 4), 0},
1340 {"bpcid5", SRIDX (3, 4, 5), 0}, {"dr29", SRIDX (3, 4, 5), 0},
1341 {"bpcid6", SRIDX (3, 4, 6), 0}, {"dr34", SRIDX (3, 4, 6), 0},
40c7a7cb
KLC		 1342 {"bpcid7", SRIDX (3, 4, 7), 0}, {"dr39", SRIDX (3, 4, 7), 0},
1343 {"edm_cfg", SRIDX (3, 5, 0), 0}, {"dr40", SRIDX (3, 5, 0), 0},
1344 {"edmsw", SRIDX (3, 6, 0), 0}, {"dr41", SRIDX (3, 6, 0), 0},
1345 {"edm_ctl", SRIDX (3, 7, 0), 0}, {"dr42", SRIDX (3, 7, 0), 0},
1346 {"edm_dtr", SRIDX (3, 8, 0), 0}, {"dr43", SRIDX (3, 8, 0), 0},
1347 {"bpmtc", SRIDX (3, 9, 0), 0}, {"dr44", SRIDX (3, 9, 0), 0},
1348 {"dimbr", SRIDX (3, 10, 0), 0}, {"dr45", SRIDX (3, 10, 0), 0},
1349 {"tecr0", SRIDX (3, 14, 0), 0}, {"dr46", SRIDX (3, 14, 0), 0},
1350 {"tecr1", SRIDX (3, 14, 1), 0}, {"dr47", SRIDX (3, 14, 1), 0},
35c08157
KLC		 1351 {NULL,0 ,0}
1352};
1353
40c7a7cb 1354const keyword_t keyword_cp[] =
35c08157
KLC		 1355{
1356 {"cp0", 0, 0}, {"cp1", 1, 0}, {"cp2", 2, 0}, {"cp3", 3, 0}, {NULL, 0, 0}
1357};
1358
40c7a7cb 1359const keyword_t keyword_cpr[] =
35c08157 1360{
40c7a7cb
KLC		 1361 {"cpr0", 0, 0}, {"cpr1", 1, 0}, {"cpr2", 2, 0}, {"cpr3", 3, 0},
1362 {"cpr4", 4, 0}, {"cpr5", 5, 0}, {"cpr6", 6, 0}, {"cpr7", 7, 0},
1363 {"cpr8", 8, 0}, {"cpr9", 9, 0}, {"cpr10", 10, 0}, {"cpr11", 11, 0},
1364 {"cpr12", 12, 0}, {"cpr13", 13, 0}, {"cpr14", 14, 0}, {"cpr15", 15, 0},
1365 {"cpr16", 16, 0}, {"cpr17", 17, 0}, {"cpr18", 18, 0}, {"cpr19", 19, 0},
1366 {"cpr20", 20, 0}, {"cpr21", 21, 0}, {"cpr22", 22, 0}, {"cpr23", 23, 0},
1367 {"cpr24", 24, 0}, {"cpr25", 25, 0}, {"cpr26", 26, 0}, {"cpr27", 27, 0},
1368 {"cpr28", 28, 0}, {"cpr29", 29, 0}, {"cpr30", 30, 0}, {"cpr31", 31, 0},
1369 {NULL, 0, 0}
35c08157
KLC		 1370};
1371
40c7a7cb 1372const keyword_t keyword_fsr[] =
35c08157
KLC		 1373{
1374 {"fs0", 0, 0}, {"fs1", 1, 0}, {"fs2", 2, 0}, {"fs3", 3, 0}, {"fs4", 4, 0},
1375 {"fs5", 5, 0}, {"fs6", 6, 0}, {"fs7", 7, 0}, {"fs8", 8, 0}, {"fs9", 9, 0},
1376 {"fs10", 10, 0}, {"fs11", 11, 0}, {"fs12", 12, 0}, {"fs13", 13, 0},
1377 {"fs14", 14, 0}, {"fs15", 15, 0}, {"fs16", 16, 0}, {"fs17", 17, 0},
1378 {"fs18", 18, 0}, {"fs19", 19, 0}, {"fs20", 20, 0}, {"fs21", 21, 0},
1379 {"fs22", 22, 0}, {"fs23", 23, 0}, {"fs24", 24, 0}, {"fs25", 25, 0},
1380 {"fs26", 26, 0}, {"fs27", 27, 0}, {"fs28", 28, 0}, {"fs29", 29, 0},
1381 {"fs30", 30, 0}, {"fs31", 31, 0}, {NULL, 0 ,0}
1382};
1383
40c7a7cb 1384const keyword_t keyword_fdr[] =
35c08157
KLC		 1385{
1386 {"fd0", 0, 0}, {"fd1", 1, 0}, {"fd2", 2, 0}, {"fd3", 3, 0}, {"fd4", 4, 0},
1387 {"fd5", 5, 0}, {"fd6", 6, 0}, {"fd7", 7, 0}, {"fd8", 8, 0}, {"fd9", 9, 0},
1388 {"fd10", 10, 0}, {"fd11", 11, 0}, {"fd12", 12, 0}, {"fd13", 13, 0},
1389 {"fd14", 14, 0}, {"fd15", 15, 0}, {"fd16", 16, 0}, {"fd17", 17, 0},
1390 {"fd18", 18, 0}, {"fd19", 19, 0}, {"fd20", 20, 0}, {"fd21", 21, 0},
1391 {"fd22", 22, 0}, {"fd23", 23, 0}, {"fd24", 24, 0}, {"fd25", 25, 0},
1392 {"fd26", 26, 0}, {"fd27", 27, 0}, {"fd28", 28, 0}, {"fd29", 29, 0},
1393 {"fd30", 30, 0}, {"fd31", 31, 0}, {NULL, 0, 0}
1394};
1395
40c7a7cb 1396const keyword_t keyword_abdim[] =
35c08157
KLC		 1397{
1398 {"bi", 0, 0}, {"bim", 1, 0}, {"bd", 2, 0}, {"bdm", 3, 0},
1399 {"ai", 4, 0}, {"aim", 5, 0}, {"ad", 6, 0}, {"adm", 7, 0},
1400 {NULL, 0, 0}
1401};
1402
40c7a7cb 1403const keyword_t keyword_abm[] =
35c08157 1404{
40c7a7cb
KLC		 1405 {"b", 0, 0}, {"bm", 1, 0}, {"bx", 2, 0}, {"bmx", 3, 0},
1406 {"a", 4, 0}, {"am", 5, 0}, {"ax", 6, 0}, {"amx", 7, 0},
1407 {NULL, 0, 0}
35c08157
KLC		 1408};
1409
1410static const keyword_t keyword_dtiton[] =
1411{
1412 {"iton", 1, 0}, {"ton", 3, 0}, {NULL, 0, 0}
1413};
1414
1415static const keyword_t keyword_dtitoff[] =
1416{
1417 {"itoff", 1, 0}, {"toff", 3, 0}, {NULL, 0, 0}
1418};
1419
40c7a7cb 1420const keyword_t keyword_dpref_st[] =
35c08157
KLC		 1421{
1422 {"srd", 0, 0}, {"mrd", 1, 0}, {"swr", 2, 0}, {"mwr", 3, 0},
1423 {"pte", 4, 0}, {"clwr", 5, 0}, {NULL, 0, 0}
1424};
1425
40c7a7cb 1426/* CCTL Ra, SubType. */
35c08157
KLC		 1427static const keyword_t keyword_cctl_st0[] =
1428{
1429 {"l1d_ix_inval", 0X0, 0}, {"l1d_ix_wb", 0X1, 0}, {"l1d_ix_wbinval", 0X2, 0},
1430 {"l1d_va_fillck", 0XB, 0}, {"l1d_va_ulck", 0XC, 0}, {"l1i_ix_inval", 0X10, 0},
1431 {"l1i_va_fillck", 0X1B, 0}, {"l1i_va_ulck", 0X1C, 0},
1432 {NULL, 0, 0}
1433};
1434
40c7a7cb 1435/* CCTL Ra, SubType, level. */
35c08157
KLC		 1436static const keyword_t keyword_cctl_st1[] =
1437{
1438 {"l1d_va_inval", 0X8, 0}, {"l1d_va_wb", 0X9, 0},
1439 {"l1d_va_wbinval", 0XA, 0}, {"l1i_va_inval", 0X18, 0},
1440 {NULL, 0, 0}
1441};
1442
40c7a7cb 1443/* CCTL Rt, Ra, SubType. */
35c08157
KLC		 1444static const keyword_t keyword_cctl_st2[] =
1445{
1446 {"l1d_ix_rtag", 0X3, 0}, {"l1d_ix_rwd", 0X4, 0},
1447 {"l1i_ix_rtag", 0X13, 0}, {"l1i_ix_rwd", 0X14, 0},
1448 {NULL, 0, 0}
1449};
1450
40c7a7cb 1451/* CCTL Rb, Ra, SubType. */
35c08157
KLC		 1452static const keyword_t keyword_cctl_st3[] =
1453{
1454 {"l1d_ix_wtag", 0X5, 0}, {"l1d_ix_wwd", 0X6, 0},
1455 {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0},
1456 {NULL, 0, 0}
1457};
1458
40c7a7cb 1459/* CCTL L1D_INVALALL. */
35c08157
KLC		 1460static const keyword_t keyword_cctl_st4[] =
1461{
1462 {"l1d_invalall", 0x7, 0}, {NULL, 0, 0}
1463};
1464
40c7a7cb 1465/* CCTL L1D_WBALL, level. */
35c08157
KLC		 1466static const keyword_t keyword_cctl_st5[] =
1467{
1468 {"l1d_wball", 0xf, 0}, {NULL, 0, 0}
1469};
1470
40c7a7cb 1471const keyword_t keyword_cctl_lv[] =
35c08157
KLC		 1472{
1473 {"1level", 0, 0}, {"alevel", 1, 0}, {"0", 0, 0}, {"1", 1, 0},
1474 {NULL, 0, 0},
1475};
1476
1477static const keyword_t keyword_tlbop_st[] =
1478{
40c7a7cb
KLC		 1479 {"targetread", 0, 0}, {"trd", 0, 0},
1480 {"targetwrite", 1, 0}, {"twr", 1, 0},
1481 {"rwrite", 2, 0}, {"rwr", 2, 0},
1482 {"rwritelock", 3, 0}, {"rwlk", 3, 0},
1483 {"unlock", 4, 0}, {"unlk", 4, 0},
1484 {"invalidate", 6, 0}, {"inv", 6, 0},
35c08157 1485 {NULL, 0, 0},
35c08157
KLC		 1486};
1487
40c7a7cb 1488const keyword_t keyword_standby_st[] =
35c08157
KLC		 1489{
1490 {"no_wake_grant", 0, 0},
1491 {"wake_grant", 1, 0},
1492 {"wait_done", 2, 0},
1493 {"0", 0, 0},
1494 {"1", 1, 0},
1495 {"2", 2, 0},
1496 {"3", 3, 0},
1497 {NULL, 0, 0},
1498};
1499
40c7a7cb 1500const keyword_t keyword_msync_st[] =
35c08157
KLC		 1501{
1502 {"all", 0, 0}, {"store", 1, 0},
1503 {NULL, 0, 0}
1504};
1505
40c7a7cb
KLC		 1506const keyword_t keyword_im5_i[] =
1507{
1508 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0},
1509 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0},
1510 {NULL, 0, 0}
1511};
1512
1513const keyword_t keyword_im5_m[] =
1514{
1515 {"m0", 0, 0}, {"m1", 1, 0}, {"m2", 2, 0}, {"m3", 3, 0},
1516 {"m4", 4, 0}, {"m5", 5, 0}, {"m6", 6, 0}, {"m7", 7, 0},
1517 {NULL, 0, 0}
1518};
1519
1520const keyword_t keyword_accumulator[] =
1521{
1522 {"d0.lo", 0, 0}, {"d0.hi", 1, 0}, {"d1.lo", 2, 0}, {"d1.hi", 3, 0},
1523 {NULL, 0, 0}
1524};
1525
1526const keyword_t keyword_aridx[] =
1527{
1528 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0},
1529 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0},
1530 {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0},
1531 {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0},
1532 {"d0.l24", 16, 0}, {"d1.l24", 17, 0},
1533 {"shft_ctl0", 18, 0}, {"shft_ctl1", 19, 0},
1534 {"lb", 24, 0}, {"le", 25, 0}, {"lc", 26, 0}, {"adm_vbase", 27, 0},
1535 {NULL, 0, 0}
1536};
1537
1538const keyword_t keyword_aridx2[] =
1539{
1540 {"cbb0", 0, 0}, {"cbb1", 1, 0}, {"cbb2", 2, 0}, {"cbb3", 3, 0},
1541 {"cbe0", 4, 0}, {"cbe1", 5, 0}, {"cbe2", 6, 0}, {"cbe3", 7, 0},
1542 {"cb_ctl", 31, 0},
1543 {NULL, 0, 0}
1544};
1545
1546const keyword_t keyword_aridxi[] =
1547{
1548 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0},
1549 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0},
1550 {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0},
1551 {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0},
1552 {NULL, 0, 0}
1553};
1554
fbaf61ad
NC		 1555const keyword_t keyword_aridxi_mx[] =
1556{
1557 {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0},
1558 {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0},
1559 {NULL, 0, 0}
1560};
1561
40c7a7cb
KLC		 1562const keyword_t *keywords[_HW_LAST] =
1563{
1564 keyword_gpr, keyword_usr, keyword_dxr, keyword_sr, keyword_fsr,
1565 keyword_fdr, keyword_cp, keyword_cpr, keyword_abdim, keyword_abm,
1566 keyword_dtiton, keyword_dtitoff, keyword_dpref_st,
1567 keyword_cctl_st0, keyword_cctl_st1, keyword_cctl_st2,
1568 keyword_cctl_st3, keyword_cctl_st4, keyword_cctl_st5,
1569 keyword_cctl_lv, keyword_tlbop_st, keyword_standby_st,
1570 keyword_msync_st,
1571 keyword_im5_i, keyword_im5_m,
fbaf61ad
NC		 1572 keyword_accumulator, keyword_aridx, keyword_aridx2,
1573 keyword_aridxi, keyword_aridxi_mx
40c7a7cb 1574};
fbaf61ad
NC		 1575
1576const keyword_t **nds32_keyword_table[NDS32_CORE_COUNT];
1577static unsigned int nds32_keyword_count_table[NDS32_CORE_COUNT];
1578const field_t *nds32_field_table[NDS32_CORE_COUNT];
1579opcode_t *nds32_opcode_table[NDS32_CORE_COUNT];
35c08157 1580\f
fbaf61ad 1581
35c08157
KLC		 1582/* Hash table for syntax lex. */
1583static htab_t field_htab;
1584/* Hash table for opcodes. */
1585static htab_t opcode_htab;
1586/* Hash table for hardware resources. */
fbaf61ad 1587static htab_t *hw_ktabs;
35c08157
KLC		 1588
1589static hashval_t
1590htab_hash_hash (const void *p)
1591{
1592 struct nds32_hash_entry *h = (struct nds32_hash_entry *) p;
1593
1594 return htab_hash_string (h->name);
1595}
1596
1597static int
1598htab_hash_eq (const void *p, const void *q)
1599{
1600 struct nds32_hash_entry *h = (struct nds32_hash_entry *) p;
1601 const char *name = (const char *) q;
1602
1603 return strcmp (name, h->name) == 0;
1604}
35c08157 1605\f
35c08157 1606
fbaf61ad
NC		 1607static void
1608build_operand_hash_table (void)
35c08157 1609{
fbaf61ad 1610 unsigned k;
35c08157 1611
fbaf61ad
NC		 1612 field_htab = htab_create_alloc (128, htab_hash_hash, htab_hash_eq,
1613 NULL, xcalloc, free);
35c08157 1614
fbaf61ad 1615 for (k = 0; k < NDS32_CORE_COUNT; k++)
35c08157 1616 {
fbaf61ad 1617 const field_t *fld;
35c08157 1618
fbaf61ad
NC		 1619 fld = nds32_field_table[k];
1620 if (fld == NULL)
1621 continue;
35c08157 1622
fbaf61ad
NC		 1623 /* Add op-codes. */
1624 while (fld->name != NULL)
1625 {
1626 hashval_t hash;
1627 const field_t **slot;
35c08157 1628
fbaf61ad
NC		 1629 hash = htab_hash_string (fld->name);
1630 slot = (const field_t **)
1631 htab_find_slot_with_hash (field_htab, fld->name, hash, INSERT);
35c08157 1632
fbaf61ad
NC		 1633 assert (slot != NULL && *slot == NULL);
1634 *slot = fld++;
1635 }
1636 }
1637}
35c08157 1638
fbaf61ad
NC		 1639static void
1640build_keyword_hash_table (void)
1641{
1642 unsigned int i, j, k, n;
35c08157 1643
fbaf61ad
NC		 1644 /* Count total keyword tables. */
1645 for (n = 0, i = 0; i < NDS32_CORE_COUNT; i++)
1646 {
1647 n += nds32_keyword_count_table[i];
35c08157
KLC		 1648 }
1649
fbaf61ad
NC		 1650 /* Allocate space. */
1651 hw_ktabs = (htab_t *) malloc (n * sizeof (struct htab));
1652 for (i = 0; i < n; i++)
1653 {
1654 hw_ktabs[i] = htab_create_alloc (128, htab_hash_hash, htab_hash_eq,
1655 NULL, xcalloc, free);
1656 }
1657
1658 for (n = 0, k = 0; k < NDS32_CORE_COUNT; k++, n += j)
1659 {
1660 const keyword_t **kwd;
1661
1662 if ((j = nds32_keyword_count_table[k]) == 0)
1663 continue;
1664
1665 /* Add keywords. */
1666 kwd = nds32_keyword_table[k];
1667 for (i = 0; i < j; i++)
1668 {
1669 htab_t htab;
1670 const keyword_t *kw;
1671
1672 kw = kwd[i];
1673 htab = hw_ktabs[n + i];
1674 while (kw->name != NULL)
1675 {
1676 hashval_t hash;
1677 const keyword_t **slot;
1678
1679 hash = htab_hash_string (kw->name);
1680 slot = (const keyword_t **)
1681 htab_find_slot_with_hash (htab, kw->name, hash, INSERT);
1682
1683 assert (slot != NULL && *slot == NULL);
1684 *slot = kw++;
1685 }
1686 }
1687 }
35c08157
KLC		 1688}
1689
1690/* Build the syntax for a given opcode OPC. It parses the string
1691 pointed by INSTRUCTION and store the result on SYNTAX, so
1692 when we assemble an instruction, we don't have to parse the syntax
1693 again. */
1694
1695static void
1696build_opcode_syntax (struct nds32_opcode *opc)
1697{
1698 char odstr[MAX_LEX_LEN];
1699 const char *str;
1700 const char *end;
1701 lex_t *plex;
1702 int len;
1703 hashval_t hash;
1704 field_t *fd;
1705 int opt = 0;
1706
1707 /* Check whether it has been initialized. */
1708 if (opc->syntax)
1709 return;
1710
1711 opc->syntax = xmalloc (MAX_LEX_NUM * sizeof (lex_t));
fbaf61ad 1712 memset (opc->syntax, 0, MAX_LEX_NUM * sizeof (lex_t));
35c08157
KLC		 1713
1714 str = opc->instruction;
1715 plex = opc->syntax;
1716 while (*str)
1717 {
fbaf61ad 1718 int fidx, i, k;
35c08157
KLC		 1719
1720 switch (*str)
1721 {
40c7a7cb
KLC		 1722 case '%':
1723 *plex = SYN_INPUT;
1724 break;
1725 case '=':
1726 *plex = SYN_OUTPUT;
1727 break;
1728 case '&':
1729 *plex = SYN_INPUT | SYN_OUTPUT;
1730 break;
35c08157
KLC		 1731 case '{':
1732 *plex++ = SYN_LOPT;
1733 opt++;
1734 str++;
1735 continue;
1736 case '}':
1737 *plex++ = SYN_ROPT;
1738 str++;
1739 continue;
1740 default:
1741 *plex++ = *str++;
1742 continue;
1743 }
1744 str++;
1745
1746 /* Extract operand. */
1747 end = str;
1748 while (ISALNUM (*end) || *end == '_')
1749 end++;
1750 len = end - str;
1751 memcpy (odstr, str, len);
1752 odstr[len] = '\0';
1753
1754 hash = htab_hash_string (odstr);
1755 fd = (field_t *) htab_find_with_hash (field_htab, odstr, hash);
35c08157
KLC		 1756
1757 if (fd == NULL)
1758 {
a6743a54
AM		 1759 /* xgettext: c-format */
1760 opcodes_error_handler (_("internal error: unknown operand, %s"), str);
1761 abort ();
35c08157 1762 }
fbaf61ad
NC		 1763
1764 /* We are not sure how these tables are organized. */
1765 /* Thus, the minimal index should be the right one. */
1766 for (fidx = 256, k = 0, i = 0; i < NDS32_CORE_COUNT; i++)
1767 {
1768 int tmp;
1769
1770 tmp = fd - nds32_field_table[i];
1771 if (tmp >= 0 && tmp < fidx)
1772 {
1773 fidx = tmp;
1774 k = i;
1775 }
1776 }
a6743a54 1777 assert (fidx >= 0 && fidx < (int) ARRAY_SIZE (operand_fields));
fbaf61ad 1778 *plex |= LEX_SET_FIELD (k, fidx);
35c08157
KLC		 1779
1780 str += len;
1781 plex++;
1782 }
1783
1784 *plex = 0;
1785 opc->variant = opt;
1786 return;
35c08157
KLC		 1787}
1788
fbaf61ad
NC		 1789static void
1790build_opcode_hash_table (void)
35c08157 1791{
fbaf61ad 1792 unsigned k;
35c08157 1793
fbaf61ad 1794 opcode_htab = htab_create_alloc (512, htab_hash_hash, htab_hash_eq,
35c08157
KLC		 1795 NULL, xcalloc, free);
1796
fbaf61ad 1797 for (k = 0; k < NDS32_CORE_COUNT; k++)
35c08157 1798 {
fbaf61ad
NC		 1799 opcode_t *opc;
1800
1801 opc = nds32_opcode_table[k];
1802 if (opc == NULL)
1803 continue;
35c08157 1804
fbaf61ad
NC		 1805 /* Add op-codes. */
1806 while ((opc->opcode != NULL) && (opc->instruction != NULL))
40c7a7cb 1807 {
fbaf61ad
NC		 1808 hashval_t hash;
1809 opcode_t **slot;
1810
40c7a7cb 1811 hash = htab_hash_string (opc->opcode);
fbaf61ad
NC		 1812 slot = (opcode_t **)
1813 htab_find_slot_with_hash (opcode_htab, opc->opcode, hash,
1814 INSERT);
35c08157
KLC		 1815
1816#define NDS32_PREINIT_SYNTAX
1817#if defined (NDS32_PREINIT_SYNTAX)
fbaf61ad
NC		 1818 /* Initial SYNTAX when build opcode table, so bug in syntax
1819 can be found when initialized rather than used. */
40c7a7cb 1820 build_opcode_syntax (opc);
35c08157
KLC		 1821#endif
1822
40c7a7cb
KLC		 1823 if (*slot == NULL)
1824 {
1825 /* This is the new one. */
1826 *slot = opc;
1827 }
1828 else
1829 {
fbaf61ad
NC		 1830 opcode_t *ptr;
1831
40c7a7cb 1832 /* Already exists. Append to the list. */
fbaf61ad
NC		 1833 ptr = *slot;
1834 while (ptr->next)
1835 ptr = ptr->next;
1836 ptr->next = opc;
1837 opc->next = NULL;
40c7a7cb 1838 }
fbaf61ad 1839 opc++;
35c08157
KLC		 1840 }
1841 }
1842}
1843
fbaf61ad
NC		 1844/* Initialize the assembler. It must be called before assembling. */
1845
1846void
1847nds32_asm_init (nds32_asm_desc_t *pdesc, int flags)
1848{
1849 pdesc->flags = flags;
1850 pdesc->mach = flags & NASM_OPEN_ARCH_MASK;
1851
1852 /* Setup main core. */
1853 nds32_keyword_table[NDS32_MAIN_CORE] = &keywords[0];
1854 nds32_keyword_count_table[NDS32_MAIN_CORE] = _HW_LAST;
1855 nds32_opcode_table[NDS32_MAIN_CORE] = &nds32_opcodes[0];
1856 nds32_field_table[NDS32_MAIN_CORE] = &operand_fields[0];
1857
1858 /* Build operand hash table. */
1859 build_operand_hash_table ();
1860
1861 /* Build keyword hash tables. */
1862 build_keyword_hash_table ();
1863
1864 /* Build op-code hash table. */
1865 build_opcode_hash_table ();
1866}
1867
35c08157
KLC		 1868/* Parse the input and store operand keyword string in ODSTR.
1869 This function is only used for parsing keywords,
1870 HW_INT/HW_UINT are parsed parse_operand callback handler. */
1871
1872static char *
1873parse_to_delimiter (char *str, char odstr[MAX_KEYWORD_LEN])
1874{
1875 char *outp = odstr;
1876
1877 while (ISALNUM (*str) || *str == '.' || *str == '_')
1878 *outp++ = TOLOWER (*str++);
1879
1880 *outp = '\0';
1881 return str;
1882}
1883
40c7a7cb
KLC		 1884/* Parse the operand of lmw/smw/lmwa/smwa. */
1885
1886static int
1887parse_re (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1888 struct nds32_asm_insn *pinsn, char **pstr, int64_t *value)
1889{
1890 char *end = *pstr;
1891 char odstr[MAX_KEYWORD_LEN];
1892 keyword_t *k;
1893 hashval_t hash;
1894
1895 if (*end == '$')
1896 end++;
1897 end = parse_to_delimiter (end, odstr);
1898
1899 hash = htab_hash_string (odstr);
1900 k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash);
1901
1902 if (k == NULL)
1903 return NASM_ERR_OPERAND;
1904
1905 if (__GF (pinsn->insn, 20, 5) > (unsigned int) k->value)
1906 return NASM_ERR_OPERAND;
1907
fbaf61ad
NC		 1908 /* Register not allowed in reduced register. */
1909 if ((pdesc->flags & NASM_OPEN_REDUCED_REG)
1910 && (k->attr & ATTR (RDREG)) == 0)
1911 return NASM_ERR_REG_REDUCED;
1912
40c7a7cb
KLC		 1913 *value = k->value;
1914 *pstr = end;
1915 return NASM_R_CONST;
1916}
1917
35c08157
KLC		 1918/* Parse the operand of push25/pop25. */
1919
1920static int
1921parse_re2 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1922 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1923 char **pstr, int64_t *value)
1924{
1925 char *end = *pstr;
1926 char odstr[MAX_KEYWORD_LEN];
1927 keyword_t *k;
1928 hashval_t hash;
1929
1930 if (*end == '$')
1931 end++;
1932 end = parse_to_delimiter (end, odstr);
1933
1934 hash = htab_hash_string (odstr);
1935 k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash);
1936
1937 if (k == NULL)
1938 return NASM_ERR_OPERAND;
1939
fbaf61ad
NC		 1940 /* Register not allowed in reduced register. */
1941 if ((pdesc->flags & NASM_OPEN_REDUCED_REG)
1942 && (k->attr & ATTR (RDREG)) == 0)
1943 return NASM_ERR_REG_REDUCED;
1944
35c08157
KLC		 1945 if (k->value == 6)
1946 *value = 0;
1947 else if (k->value == 8)
1948 *value = 1;
1949 else if (k->value == 10)
1950 *value = 2;
1951 else if (k->value == 14)
1952 *value = 3;
1953 else
1954 return NASM_ERR_OPERAND;
1955
1956 *pstr = end;
1957 return NASM_R_CONST;
1958}
1959
1960/* Parse the operand of lwi45.fe. */
1961
1962static int
1963parse_fe5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn,
1964 char **pstr, int64_t *value)
1965{
1966 int r;
1967
1968 r = pdesc->parse_operand (pdesc, pinsn, pstr, value);
1969 if (r != NASM_R_CONST)
40c7a7cb 1970 return NASM_ERR_OPERAND;
35c08157
KLC		 1971
1972 /* 128 == 32 << 2. Leave the shift to parse_opreand,
1973 so it can check whether it is a multiple of 4. */
1974 *value = 128 + *value;
1975 return r;
1976}
1977
1978/* Parse the operand of movpi45. */
1979
1980static int
1981parse_pi5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn,
1982 char **pstr, int64_t *value)
1983{
1984 int r;
1985
1986 r = pdesc->parse_operand (pdesc, pinsn, pstr, value);
1987 if (r != NASM_R_CONST)
40c7a7cb 1988 return NASM_ERR_OPERAND;
35c08157
KLC		 1989
1990 *value -= 16;
1991 return r;
1992}
1993
40c7a7cb
KLC		 1994static int aext_a30b20 = 0;
1995static int aext_rte = 0;
1996static int aext_im5_ip = 0;
1997static int aext_im6_ip = 0;
1998/* Parse the operand of audio ext. */
1999static int
fbaf61ad
NC		 2000parse_aext_reg (struct nds32_asm_desc *pdesc, char **pstr,
2001 int *value, int hw_res)
40c7a7cb
KLC		 2002{
2003 char *end = *pstr;
2004 char odstr[MAX_KEYWORD_LEN];
2005 keyword_t *k;
2006 hashval_t hash;
2007
2008 if (*end == '$')
2009 end++;
2010 end = parse_to_delimiter (end, odstr);
2011
2012 hash = htab_hash_string (odstr);
2013 k = htab_find_with_hash (hw_ktabs[hw_res], odstr, hash);
2014
2015 if (k == NULL)
2016 return NASM_ERR_OPERAND;
2017
fbaf61ad
NC		 2018 if (hw_res == HW_GPR
2019 && (pdesc->flags & NASM_OPEN_REDUCED_REG)
2020 && (k->attr & ATTR (RDREG)) == 0)
2021 return NASM_ERR_REG_REDUCED;
2022
40c7a7cb
KLC		 2023 *value = k->value;
2024 *pstr = end;
2025 return NASM_R_CONST;
2026}
2027
2028static int
fbaf61ad 2029parse_a30b20 (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2030 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2031 char **pstr, int64_t *value)
2032{
2033 int rt_value, ret;
2034
fbaf61ad
NC		 2035 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_GPR);
2036 if (ret == NASM_ERR_REG_REDUCED)
2037 return NASM_ERR_REG_REDUCED;
40c7a7cb
KLC		 2038 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15))
2039 return NASM_ERR_OPERAND;
2040
2041 *value = rt_value;
2042 aext_a30b20 = rt_value;
2043 return NASM_R_CONST;
2044}
2045
2046static int
fbaf61ad 2047parse_rt21 (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2048 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2049 char **pstr, int64_t *value)
2050{
2051 int rt_value, ret, tmp_value, tmp1, tmp2;
2052
fbaf61ad
NC		 2053 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_GPR);
2054 if (ret == NASM_ERR_REG_REDUCED)
2055 return NASM_ERR_REG_REDUCED;
40c7a7cb
KLC		 2056 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15))
2057 return NASM_ERR_OPERAND;
fbaf61ad 2058
40c7a7cb
KLC		 2059 tmp1 = (aext_a30b20 & 0x08);
2060 tmp2 = (rt_value & 0x08);
2061 if (tmp1 != tmp2)
2062 return NASM_ERR_OPERAND;
2063
2064 /* Rt=CONCAT(c, t21, t0), t21:bit11-10, t0:bit5. */
2065 tmp_value = (rt_value & 0x06) << 4;
2066 tmp_value |= (rt_value & 0x01);
2067 *value = tmp_value;
2068 return NASM_R_CONST;
2069}
2070
2071static int
fbaf61ad 2072parse_rte_start (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2073 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2074 char **pstr, int64_t *value)
2075{
2076 int rt_value, ret, tmp1, tmp2;
2077
fbaf61ad
NC		 2078 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_GPR);
2079 if (ret == NASM_ERR_REG_REDUCED)
2080 return NASM_ERR_REG_REDUCED;
40c7a7cb
KLC		 2081 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)
2082 || (rt_value & 0x01))
2083 return NASM_ERR_OPERAND;
fbaf61ad 2084
40c7a7cb
KLC		 2085 tmp1 = (aext_a30b20 & 0x08);
2086 tmp2 = (rt_value & 0x08);
2087 if (tmp1 != tmp2)
2088 return NASM_ERR_OPERAND;
2089
2090 aext_rte = rt_value;
2091 /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */
2092 rt_value = (rt_value & 0x06) << 4;
2093 *value = rt_value;
2094 return NASM_R_CONST;
2095}
2096
2097static int
fbaf61ad 2098parse_rte_end (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2099 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2100 char **pstr, int64_t *value)
2101{
2102 int rt_value, ret, tmp1, tmp2;
2103
fbaf61ad
NC		 2104 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_GPR);
2105 if (ret == NASM_ERR_REG_REDUCED)
2106 return NASM_ERR_REG_REDUCED;
40c7a7cb
KLC		 2107 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)
2108 || ((rt_value & 0x01) == 0)
2109 || (rt_value != (aext_rte + 1)))
2110 return NASM_ERR_OPERAND;
fbaf61ad 2111
40c7a7cb
KLC		 2112 tmp1 = (aext_a30b20 & 0x08);
2113 tmp2 = (rt_value & 0x08);
2114 if (tmp1 != tmp2)
2115 return NASM_ERR_OPERAND;
fbaf61ad 2116
40c7a7cb
KLC		 2117 /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */
2118 rt_value = (rt_value & 0x06) << 4;
2119 *value = rt_value;
2120 return NASM_R_CONST;
2121}
2122
2123static int
fbaf61ad 2124parse_rte69_start (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2125 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2126 char **pstr, int64_t *value)
2127{
2128 int rt_value, ret;
2129
fbaf61ad
NC		 2130 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_GPR);
2131 if (ret == NASM_ERR_REG_REDUCED)
2132 return NASM_ERR_REG_REDUCED;
40c7a7cb
KLC		 2133 if ((ret == NASM_ERR_OPERAND)
2134 || (rt_value & 0x01))
2135 return NASM_ERR_OPERAND;
fbaf61ad 2136
40c7a7cb
KLC		 2137 aext_rte = rt_value;
2138 rt_value = (rt_value >> 1);
2139 *value = rt_value;
2140 return NASM_R_CONST;
2141}
2142
2143static int
fbaf61ad 2144parse_rte69_end (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2145 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2146 char **pstr, int64_t *value)
2147{
2148 int rt_value, ret;
2149
fbaf61ad
NC		 2150 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_GPR);
2151 if (ret == NASM_ERR_REG_REDUCED)
2152 return NASM_ERR_REG_REDUCED;
40c7a7cb
KLC		 2153 if ((ret == NASM_ERR_OPERAND)
2154 || ((rt_value & 0x01) == 0)
2155 || (rt_value != (aext_rte + 1)))
2156 return NASM_ERR_OPERAND;
fbaf61ad 2157
40c7a7cb
KLC		 2158 aext_rte = rt_value;
2159 rt_value = (rt_value >> 1);
2160 *value = rt_value;
2161 return NASM_R_CONST;
2162}
2163
2164static int
fbaf61ad 2165parse_im5_ip (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2166 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2167 char **pstr, int64_t *value)
2168{
2169 int rt_value, ret, new_value;
2170
fbaf61ad 2171 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_AEXT_IM_I);
40c7a7cb
KLC		 2172 if (ret == NASM_ERR_OPERAND)
2173 return NASM_ERR_OPERAND;
fbaf61ad 2174
40c7a7cb
KLC		 2175 /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */
2176 new_value = (rt_value & 0x04) << 2;
2177 new_value |= (rt_value & 0x03);
2178 *value = new_value;
2179 aext_im5_ip = new_value;
2180 return NASM_R_CONST;
2181}
2182
2183static int
fbaf61ad 2184parse_im5_mr (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2185 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2186 char **pstr, int64_t *value)
2187{
2188 int rt_value, ret, new_value, tmp1, tmp2;
2189
fbaf61ad 2190 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_AEXT_IM_M);
40c7a7cb
KLC		 2191 if (ret == NASM_ERR_OPERAND)
2192 return NASM_ERR_OPERAND;
fbaf61ad 2193
40c7a7cb
KLC		 2194 /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */
2195 new_value = (rt_value & 0x07) << 2;
2196 tmp1 = (aext_im5_ip & 0x10);
2197 tmp2 = (new_value & 0x10);
2198 if (tmp1 != tmp2)
2199 return NASM_ERR_OPERAND;
fbaf61ad 2200
40c7a7cb
KLC		 2201 *value = new_value;
2202 return NASM_R_CONST;
2203}
2204
2205static int
fbaf61ad 2206parse_im6_ip (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2207 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2208 char **pstr, int64_t *value)
2209{
2210 int rt_value, ret;
2211
fbaf61ad 2212 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_AEXT_IM_I);
40c7a7cb
KLC		 2213 if ((ret == NASM_ERR_OPERAND) || (rt_value > 3))
2214 return NASM_ERR_OPERAND;
fbaf61ad 2215
40c7a7cb
KLC		 2216 /* p = 0.bit[1:0]. */
2217 aext_im6_ip = rt_value;
2218 *value = aext_im6_ip;
2219 return NASM_R_CONST;
2220}
2221
2222static int
fbaf61ad 2223parse_im6_iq (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2224 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2225 char **pstr, int64_t *value)
2226{
2227 int rt_value, ret;
2228
fbaf61ad 2229 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_AEXT_IM_I);
40c7a7cb
KLC		 2230 if ((ret == NASM_ERR_OPERAND) || (rt_value < 4))
2231 return NASM_ERR_OPERAND;
fbaf61ad 2232
40c7a7cb
KLC		 2233 /* q = 1.bit[1:0]. */
2234 if ((rt_value & 0x03) != aext_im6_ip)
2235 return NASM_ERR_OPERAND;
fbaf61ad 2236
40c7a7cb
KLC		 2237 *value = aext_im6_ip;
2238 return NASM_R_CONST;
2239}
2240
2241static int
fbaf61ad 2242parse_im6_mr (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2243 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2244 char **pstr, int64_t *value)
2245{
2246 int rt_value, ret;
2247
fbaf61ad 2248 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_AEXT_IM_M);
40c7a7cb
KLC		 2249 if ((ret == NASM_ERR_OPERAND) || (rt_value > 3))
2250 return NASM_ERR_OPERAND;
fbaf61ad 2251
40c7a7cb
KLC		 2252 /* r = 0.bit[3:2]. */
2253 *value = (rt_value & 0x03);
2254 return NASM_R_CONST;
2255}
2256
2257static int
fbaf61ad 2258parse_im6_ms (struct nds32_asm_desc *pdesc,
40c7a7cb
KLC		 2259 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
2260 char **pstr, int64_t *value)
2261{
2262 int rt_value, ret;
2263
fbaf61ad 2264 ret = parse_aext_reg (pdesc, pstr, &rt_value, HW_AEXT_IM_M);
40c7a7cb
KLC		 2265 if ((ret == NASM_ERR_OPERAND) || (rt_value < 4))
2266 return NASM_ERR_OPERAND;
fbaf61ad 2267
40c7a7cb
KLC		 2268 /* s = 1.bit[5:4]. */
2269 *value = (rt_value & 0x03);
2270 return NASM_R_CONST;
2271}
2272
35c08157
KLC		 2273/* Generic operand parse base on the information provided by the field. */
2274
2275static int
2276parse_operand (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
2277 char **str, int syn)
2278{
2279 char odstr[MAX_KEYWORD_LEN];
2280 char *end;
2281 hashval_t hash;
fbaf61ad 2282 const field_t *fld = &LEX_GET_FIELD (((syn >> 8) & 0xff) - 1, syn);
35c08157 2283 keyword_t *k;
fbaf61ad 2284 int64_t value = 0; /* 0x100000000; Big enough to overflow. */
35c08157
KLC		 2285 int r;
2286 uint64_t modifier = 0;
2287
2288 end = *str;
2289
2290 if (fld->parse)
2291 {
2292 r = fld->parse (pdesc, pinsn, &end, &value);
fbaf61ad 2293 if (r == NASM_ERR_OPERAND || r == NASM_ERR_REG_REDUCED)
40c7a7cb 2294 {
fbaf61ad 2295 pdesc->result = r;
40c7a7cb
KLC		 2296 return 0;
2297 }
35c08157
KLC		 2298 goto done;
2299 }
2300
fbaf61ad
NC		 2301 /* Check valid keyword group. */
2302 if (fld->hw_res < HW_INT)
35c08157 2303 {
fbaf61ad
NC		 2304 int n = 0, i;
2305
2306 /* Calculate index of keyword hash table. */
2307 for (i = 0; i < (fld->hw_res >> 8); i++)
2308 n += nds32_keyword_count_table[i];
2309
35c08157
KLC		 2310 /* Parse the operand in assembly code. */
2311 if (*end == '$')
2312 end++;
2313 end = parse_to_delimiter (end, odstr);
2314
2315 hash = htab_hash_string (odstr);
fbaf61ad
NC		 2316 k = htab_find_with_hash (hw_ktabs[n + (fld->hw_res & 0xff)], odstr,
2317 hash);
35c08157
KLC		 2318
2319 if (k == NULL)
2320 {
2321 pdesc->result = NASM_ERR_OPERAND;
2322 return 0;
2323 }
2324
2325 if (fld->hw_res == HW_GPR && (pdesc->flags & NASM_OPEN_REDUCED_REG)
2326 && (k->attr & ATTR (RDREG)) == 0)
2327 {
2328 /* Register not allowed in reduced register. */
2329 pdesc->result = NASM_ERR_REG_REDUCED;
2330 return 0;
2331 }
2332
2333 if (fld->hw_res == HW_GPR)
2334 {
2335 if (syn & SYN_INPUT)
2336 pinsn->defuse |= USE_REG (k->value);
2337 if (syn & SYN_OUTPUT)
2338 pinsn->defuse |= DEF_REG (k->value);
2339 }
2340
2341 value = k->value;
2342 if (fld->hw_res == HW_GPR && (fld->bitsize + fld->shift) == 4)
2343 value = nds32_r54map[value];
2344 }
2345 else if (fld->hw_res == HW_INT || fld->hw_res == HW_UINT)
2346 {
2347 if (*end == '#')
2348 end++;
2349
2350 /* Handle modifiers. Do we need to make a table for modifiers?
2351 Do we need to check unknown modifier? */
2352 if (strncasecmp (end, "hi20(", 5) == 0)
2353 {
2354 modifier |= NASM_ATTR_HI20;
2355 end += 5;
2356 }
2357 else if (strncasecmp (end, "lo12(", 5) == 0)
2358 {
2359 modifier |= NASM_ATTR_LO12;
2360 end += 5;
2361 }
2362 else if (strncasecmp (end, "lo20(", 5) == 0)
2363 {
40c7a7cb 2364 /* e.g., movi. */
35c08157
KLC		 2365 modifier |= NASM_ATTR_LO20;
2366 end += 5;
2367 }
2368
2369 r = pdesc->parse_operand (pdesc, pinsn, &end, &value);
2370 if (modifier)
2371 {
2372 /* Consume the ')' of modifier. */
2373 end++;
2374 pinsn->attr |= modifier;
2375 }
2376
2377 switch (r)
2378 {
2379 case NASM_R_ILLEGAL:
2380 pdesc->result = NASM_ERR_OPERAND;
2381 return 0;
2382 case NASM_R_SYMBOL:
2383 /* This field needs special fix-up. */
2384 pinsn->field = fld;
2385 break;
2386 case NASM_R_CONST:
2387 if (modifier & NASM_ATTR_HI20)
2388 value = (value >> 12) & 0xfffff;
2389 else if (modifier & NASM_ATTR_LO12)
2390 value = value & 0xfff;
2391 else if (modifier & NASM_ATTR_LO20)
2392 value = value & 0xfffff;
2393 break;
2394 default:
a6743a54
AM		 2395 /* xgettext: c-format */
2396 opcodes_error_handler (_("internal error: don't know how to handle "
2397 "parsing results"));
35c08157
KLC		 2398 abort ();
2399 }
2400 }
2401 else
2402 {
a6743a54
AM		 2403 /* xgettext: c-format */
2404 opcodes_error_handler (_("internal error: unknown hardware resource"));
35c08157
KLC		 2405 abort ();
2406 }
2407
2408done:
2409 /* Don't silently discarding bits. */
2410 if (value & __MASK (fld->shift))
2411 {
2412 pdesc->result = NASM_ERR_OUT_OF_RANGE;
2413 return 0;
2414 }
2415
2416 /* Check the range of signed or unsigned result. */
40c7a7cb 2417 if (fld->hw_res != HW_INT && ((int32_t) value >> (fld->bitsize + fld->shift)))
35c08157
KLC		 2418 {
2419 pdesc->result = NASM_ERR_OUT_OF_RANGE;
2420 return 0;
2421 }
2422 else if (fld->hw_res == HW_INT)
2423 {
2424 /* Sign-ext the value. */
2425 if (((value >> 32) == 0) && (value & 0x80000000))
b6518b38 2426 value |= (int64_t) -1U << 31;
35c08157
KLC		 2427
2428
2429 /* Shift the value to positive domain. */
2430 if ((value + (1 << (fld->bitsize + fld->shift - 1)))
2431 >> (fld->bitsize + fld->shift))
2432 {
2433 pdesc->result = NASM_ERR_OUT_OF_RANGE;
2434 return 0;
2435 }
2436 }
2437
40c7a7cb
KLC		 2438 pinsn->insn |=
2439 (((value >> fld->shift) & __MASK (fld->bitsize)) << fld->bitpos);
35c08157
KLC		 2440 *str = end;
2441 return 1;
2442}
2443
2444/* Try to parse an instruction string based on opcode syntax. */
2445
2446static int
2447parse_insn (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
2448 char *str, struct nds32_opcode *opc)
2449{
2450 int variant = 0;
2451 char *p = NULL;
2452
2453 /* A syntax may has optional operands, so we have to try each possible
2454 combination to see if the input is accepted. In order to do so,
2455 bit-N represent whether optional-operand-N is used in this combination.
2456 That is, if bit-N is set, optional-operand-N is not used.
2457
2458 For example, there are 2 optional operands in this syntax,
2459
40c7a7cb 2460 "a{,b}{,c}"
35c08157
KLC		 2461
2462 we can try it 4 times (i.e., 1 << 2)
2463
40c7a7cb
KLC		 2464 0 (b00): "a,b,c"
2465 1 (b01): "a,c"
2466 2 (b10): "a,b"
2467 3 (b11): "a"
2468 */
35c08157
KLC		 2469
2470 /* The outer do-while loop is used to try each possible optional
2471 operand combination, and VARIANT is the bit mask. The inner loop
2472 iterates each lexeme in the syntax. */
2473
2474 do
2475 {
2476 /* OPT is the number of optional operands we've seen. */
2477 int opt = 0;
2478 lex_t *plex;
2479
2480 /* PLEX is the syntax iterator and P is the iterator for input
2481 string. */
2482 plex = opc->syntax;
2483 p = str;
2484 /* Initial the base value. */
2485 pinsn->insn = opc->value;
2486
2487 while (*plex)
2488 {
2489 if (IS_LEX_CHAR (*plex))
2490 {
2491 /* If it's a plain char, just compare it. */
40c7a7cb 2492 if (LEX_CHAR (*plex) != TOLOWER (*p))
35c08157 2493 {
40c7a7cb
KLC		 2494 if (LEX_CHAR (*plex) == '+' && TOLOWER (*p) == '-')
2495 {
2496 /* We don't define minus format for some signed
2497 immediate case, so ignoring '+' here to parse
2498 negative value eazily. Besides, the minus format
2499 can not support for instruction with relocation.
2500 Ex: lwi $r0, [$r0 + imm] */
2501 plex++;
2502 continue;
2503 }
35c08157
KLC		 2504 pdesc->result = NASM_ERR_SYNTAX;
2505 goto reject;
2506 }
2507 p++;
2508 }
2509 else if (*plex & SYN_LOPT)
2510 {
2511 /* If it's '{' and it's not used in this iteration,
2512 just skip the whole optional operand. */
2513 if ((1 << (opt++)) & variant)
2514 {
2515 while ((*plex & SYN_ROPT) == 0)
2516 plex++;
2517 }
2518 }
2519 else if (*plex & SYN_ROPT)
2520 {
40c7a7cb 2521 /* ignore. */
35c08157
KLC		 2522 }
2523 else
2524 {
2525 /* If it's a operand, parse the input operand from input. */
2526 if (!parse_operand (pdesc, pinsn, &p, *plex))
2527 goto reject;
2528 }
2529 plex++;
2530 }
2531
2532 /* Check whether this syntax is accepted. */
2533 if (*plex == 0 && (*p == '\0' || *p == '!' || *p == '#'))
2534 return 1;
2535
2536reject:
2537 /* If not accepted, try another combination. */
2538 variant++;
2539 }
2540 while (variant < (1 << opc->variant));
2541
2542 return 0;
2543}
2544
2545void
2546nds32_assemble (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
2547 char *str)
2548{
2549 struct nds32_opcode *opc;
2550 char *s;
2551 char *mnemoic;
2552 char *dot;
2553 hashval_t hash;
2554
2555 /* Duplicate the string, so we can modify it for convenience. */
2556 s = strdup (str);
2557 mnemoic = s;
2558 str = s;
2559
2560 /* Find opcode mnemoic. */
2561 while (*s != ' ' && *s != '\t' && *s != '\0')
2562 s++;
2563 if (*s != '\0')
2564 *s++ = '\0';
2565 dot = strchr (mnemoic, '.');
2566
2567retry_dot:
2568 /* Lookup the opcode syntax. */
2569 hash = htab_hash_string (mnemoic);
2570 opc = (struct nds32_opcode *)
2571 htab_find_with_hash (opcode_htab, mnemoic, hash);
2572
2573 /* If we cannot find a match syntax, try it again without `.'.
2574 For example, try "lmw.adm" first and then try "lmw" again. */
2575 if (opc == NULL && dot != NULL)
2576 {
2577 *dot = '\0';
2578 s[-1] = ' ';
2579 s = dot + 1;
2580 dot = NULL;
2581 goto retry_dot;
2582 }
2583 else if (opc == NULL)
2584 {
2585 pdesc->result = NASM_ERR_UNKNOWN_OP;
2586 goto out;
2587 }
2588
2589 /* There may be multiple syntaxes for a given opcode.
2590 Try each one until a match is found. */
2591 for (; opc; opc = opc->next)
2592 {
2593 /* Build opcode syntax, if it's not been initialized yet. */
2594 if (opc->syntax == NULL)
2595 build_opcode_syntax (opc);
2596
2597 /* Reset status before assemble. */
2598 pinsn->defuse = opc->defuse;
2599 pinsn->insn = 0;
2600 pinsn->field = NULL;
2601 /* Use opcode attributes to initial instruction attributes. */
2602 pinsn->attr = opc->attr;
2603 if (parse_insn (pdesc, pinsn, s, opc))
2604 break;
2605 }
2606
2607 pinsn->opcode = opc;
2608 if (opc == NULL)
2609 {
ea16498d
KLC		 2610 if (pdesc->result == NASM_OK)
2611 pdesc->result = NASM_ERR_SYNTAX;
35c08157
KLC		 2612 goto out;
2613 }
2614
2615 /* A matched opcode is found. Write the result to instruction buffer. */
2616 pdesc->result = NASM_OK;
2617
2618out:
2619 free (str);
2620}
GDB Binutils - Deliverables
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