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87e6d782 NC |
1 | /* CPU data header for openrisc. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
87337981 | 5 | Copyright 1996-2009 Free Software Foundation, Inc. |
87e6d782 NC |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9b201bb5 NC |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
87e6d782 | 13 | |
9b201bb5 NC |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
87e6d782 | 18 | |
9b201bb5 NC |
19 | You should have received a copy of the GNU General Public License along |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
87e6d782 NC |
22 | |
23 | */ | |
24 | ||
25 | #ifndef OPENRISC_CPU_H | |
26 | #define OPENRISC_CPU_H | |
27 | ||
28 | #define CGEN_ARCH openrisc | |
29 | ||
30 | /* Given symbol S, return openrisc_cgen_<S>. */ | |
31 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
32 | #define CGEN_SYM(s) openrisc##_cgen_##s | |
33 | #else | |
34 | #define CGEN_SYM(s) openrisc/**/_cgen_/**/s | |
35 | #endif | |
36 | ||
37 | ||
38 | /* Selected cpu families. */ | |
39 | #define HAVE_CPU_OPENRISCBF | |
40 | ||
41 | #define CGEN_INSN_LSB0_P 1 | |
42 | ||
43 | /* Minimum size of any insn (in bytes). */ | |
44 | #define CGEN_MIN_INSN_SIZE 4 | |
45 | ||
46 | /* Maximum size of any insn (in bytes). */ | |
47 | #define CGEN_MAX_INSN_SIZE 4 | |
48 | ||
49 | #define CGEN_INT_INSN_P 1 | |
50 | ||
51 | /* Maximum number of syntax elements in an instruction. */ | |
52 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14 | |
53 | ||
54 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. | |
55 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands | |
56 | we can't hash on everything up to the space. */ | |
57 | #define CGEN_MNEMONIC_OPERANDS | |
58 | ||
59 | /* Maximum number of fields in an instruction. */ | |
60 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 | |
61 | ||
62 | /* Enums. */ | |
63 | ||
64 | /* Enum declaration for exception vectors. */ | |
65 | typedef enum e_exception { | |
66 | E_RESET, E_BUSERR, E_DPF, E_IPF | |
67 | , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT | |
68 | , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL | |
69 | , E_BREAK, E_RESERVED | |
70 | } E_EXCEPTION; | |
71 | ||
72 | /* Enum declaration for FIXME. */ | |
73 | typedef enum insn_class { | |
74 | OP1_0, OP1_1, OP1_2, OP1_3 | |
75 | } INSN_CLASS; | |
76 | ||
77 | /* Enum declaration for FIXME. */ | |
78 | typedef enum insn_sub { | |
79 | OP2_0, OP2_1, OP2_2, OP2_3 | |
80 | , OP2_4, OP2_5, OP2_6, OP2_7 | |
81 | , OP2_8, OP2_9, OP2_10, OP2_11 | |
82 | , OP2_12, OP2_13, OP2_14, OP2_15 | |
83 | } INSN_SUB; | |
84 | ||
85 | /* Enum declaration for FIXME. */ | |
86 | typedef enum insn_op3 { | |
87 | OP3_0, OP3_1, OP3_2, OP3_3 | |
88 | } INSN_OP3; | |
89 | ||
90 | /* Enum declaration for FIXME. */ | |
91 | typedef enum insn_op4 { | |
92 | OP4_0, OP4_1, OP4_2, OP4_3 | |
93 | , OP4_4, OP4_5, OP4_6, OP4_7 | |
94 | } INSN_OP4; | |
95 | ||
96 | /* Enum declaration for FIXME. */ | |
97 | typedef enum insn_op5 { | |
98 | OP5_0, OP5_1, OP5_2, OP5_3 | |
99 | , OP5_4, OP5_5, OP5_6, OP5_7 | |
100 | , OP5_8, OP5_9, OP5_10, OP5_11 | |
101 | , OP5_12, OP5_13, OP5_14, OP5_15 | |
102 | , OP5_16, OP5_17, OP5_18, OP5_19 | |
103 | , OP5_20, OP5_21, OP5_22, OP5_23 | |
104 | , OP5_24, OP5_25, OP5_26, OP5_27 | |
105 | , OP5_28, OP5_29, OP5_30, OP5_31 | |
106 | } INSN_OP5; | |
107 | ||
108 | /* Enum declaration for FIXME. */ | |
109 | typedef enum insn_op6 { | |
110 | OP6_0, OP6_1, OP6_2, OP6_3 | |
111 | , OP6_4, OP6_5, OP6_6, OP6_7 | |
112 | } INSN_OP6; | |
113 | ||
114 | /* Enum declaration for FIXME. */ | |
115 | typedef enum insn_op7 { | |
116 | OP7_0, OP7_1, OP7_2, OP7_3 | |
117 | , OP7_4, OP7_5, OP7_6, OP7_7 | |
118 | , OP7_8, OP7_9, OP7_10, OP7_11 | |
119 | , OP7_12, OP7_13, OP7_14, OP7_15 | |
120 | } INSN_OP7; | |
121 | ||
122 | /* Attributes. */ | |
123 | ||
124 | /* Enum declaration for machine type selection. */ | |
125 | typedef enum mach_attr { | |
126 | MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX | |
127 | } MACH_ATTR; | |
128 | ||
129 | /* Enum declaration for instruction set selection. */ | |
130 | typedef enum isa_attr { | |
131 | ISA_OR32, ISA_MAX | |
132 | } ISA_ATTR; | |
133 | ||
134 | /* Enum declaration for if this model has caches. */ | |
135 | typedef enum has_cache_attr { | |
136 | HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE | |
137 | } HAS_CACHE_ATTR; | |
138 | ||
139 | /* Number of architecture variants. */ | |
140 | #define MAX_ISAS 1 | |
141 | #define MAX_MACHS ((int) MACH_MAX) | |
142 | ||
143 | /* Ifield support. */ | |
144 | ||
87e6d782 NC |
145 | /* Ifield attribute indices. */ |
146 | ||
147 | /* Enum declaration for cgen_ifld attrs. */ | |
148 | typedef enum cgen_ifld_attr { | |
149 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED | |
150 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 | |
151 | , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS | |
152 | } CGEN_IFLD_ATTR; | |
153 | ||
154 | /* Number of non-boolean elements in cgen_ifld_attr. */ | |
155 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) | |
156 | ||
fb53f5a8 DB |
157 | /* cgen_ifld attribute accessor macros. */ |
158 | #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) | |
159 | #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) | |
160 | #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) | |
161 | #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) | |
162 | #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) | |
163 | #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) | |
164 | #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) | |
165 | ||
87e6d782 NC |
166 | /* Enum declaration for openrisc ifield types. */ |
167 | typedef enum ifield_type { | |
168 | OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB | |
169 | , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16 | |
170 | , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16 | |
171 | , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4 | |
172 | , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1 | |
173 | , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC | |
174 | , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3 | |
175 | , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX | |
176 | } IFIELD_TYPE; | |
177 | ||
178 | #define MAX_IFLD ((int) OPENRISC_F_MAX) | |
179 | ||
180 | /* Hardware attribute indices. */ | |
181 | ||
182 | /* Enum declaration for cgen_hw attrs. */ | |
183 | typedef enum cgen_hw_attr { | |
184 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE | |
185 | , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS | |
186 | } CGEN_HW_ATTR; | |
187 | ||
188 | /* Number of non-boolean elements in cgen_hw_attr. */ | |
189 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) | |
190 | ||
fb53f5a8 DB |
191 | /* cgen_hw attribute accessor macros. */ |
192 | #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) | |
193 | #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) | |
194 | #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) | |
195 | #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) | |
196 | #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) | |
197 | ||
87e6d782 NC |
198 | /* Enum declaration for openrisc hardware types. */ |
199 | typedef enum cgen_hw_type { | |
200 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR | |
201 | , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR | |
202 | , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN | |
203 | , HW_MAX | |
204 | } CGEN_HW_TYPE; | |
205 | ||
206 | #define MAX_HW ((int) HW_MAX) | |
207 | ||
208 | /* Operand attribute indices. */ | |
209 | ||
210 | /* Enum declaration for cgen_operand attrs. */ | |
211 | typedef enum cgen_operand_attr { | |
212 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT | |
213 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY | |
214 | , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS | |
215 | } CGEN_OPERAND_ATTR; | |
216 | ||
217 | /* Number of non-boolean elements in cgen_operand_attr. */ | |
218 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) | |
219 | ||
fb53f5a8 DB |
220 | /* cgen_operand attribute accessor macros. */ |
221 | #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) | |
222 | #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) | |
223 | #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) | |
224 | #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) | |
225 | #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) | |
226 | #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) | |
227 | #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) | |
228 | #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) | |
229 | #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) | |
230 | ||
87e6d782 NC |
231 | /* Enum declaration for openrisc operand types. */ |
232 | typedef enum cgen_operand_type { | |
233 | OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16 | |
234 | , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5 | |
235 | , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23 | |
236 | , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC | |
237 | , OPENRISC_OPERAND_MAX | |
238 | } CGEN_OPERAND_TYPE; | |
239 | ||
240 | /* Number of operands types. */ | |
241 | #define MAX_OPERANDS 16 | |
242 | ||
243 | /* Maximum number of operands referenced by any insn. */ | |
244 | #define MAX_OPERAND_INSTANCES 8 | |
245 | ||
246 | /* Insn attribute indices. */ | |
247 | ||
248 | /* Enum declaration for cgen_insn attrs. */ | |
249 | typedef enum cgen_insn_attr { | |
250 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI | |
b11dcf4e | 251 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED |
87e6d782 NC |
252 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS |
253 | , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS | |
254 | } CGEN_INSN_ATTR; | |
255 | ||
256 | /* Number of non-boolean elements in cgen_insn_attr. */ | |
257 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) | |
258 | ||
fb53f5a8 DB |
259 | /* cgen_insn attribute accessor macros. */ |
260 | #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
261 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) | |
262 | #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) | |
263 | #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) | |
264 | #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) | |
265 | #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) | |
266 | #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) | |
267 | #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) | |
268 | #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) | |
269 | #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) | |
270 | #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) | |
271 | #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) | |
272 | ||
87e6d782 NC |
273 | /* cgen.h uses things we just defined. */ |
274 | #include "opcode/cgen.h" | |
275 | ||
610ad19b AM |
276 | extern const struct cgen_ifld openrisc_cgen_ifld_table[]; |
277 | ||
87e6d782 NC |
278 | /* Attributes. */ |
279 | extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[]; | |
280 | extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[]; | |
281 | extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[]; | |
282 | extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[]; | |
283 | ||
284 | /* Hardware decls. */ | |
285 | ||
286 | extern CGEN_KEYWORD openrisc_cgen_opval_h_gr; | |
287 | ||
bf143b25 | 288 | extern const CGEN_HW_ENTRY openrisc_cgen_hw_table[]; |
87e6d782 NC |
289 | |
290 | ||
291 | ||
292 | #endif /* OPENRISC_CPU_H */ |