Commit | Line | Data |
---|---|---|
87e6d782 NC |
1 | /* Disassembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
47b0e7ad NC |
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
5 | - the resultant file is machine generated, cgen-dis.in isn't | |
87e6d782 | 6 | |
6f2750fe | 7 | Copyright (C) 1996-2016 Free Software Foundation, Inc. |
87e6d782 | 8 | |
9b201bb5 | 9 | This file is part of libopcodes. |
87e6d782 | 10 | |
9b201bb5 | 11 | This library is free software; you can redistribute it and/or modify |
47b0e7ad | 12 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 13 | the Free Software Foundation; either version 3, or (at your option) |
47b0e7ad | 14 | any later version. |
87e6d782 | 15 | |
9b201bb5 NC |
16 | It is distributed in the hope that it will be useful, but WITHOUT |
17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
18 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
19 | License for more details. | |
87e6d782 | 20 | |
47b0e7ad NC |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software Foundation, Inc., | |
23 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ | |
87e6d782 NC |
24 | |
25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
26 | Keep that in mind. */ | |
27 | ||
28 | #include "sysdep.h" | |
29 | #include <stdio.h> | |
30 | #include "ansidecl.h" | |
31 | #include "dis-asm.h" | |
32 | #include "bfd.h" | |
33 | #include "symcat.h" | |
98f70fc4 | 34 | #include "libiberty.h" |
73589c9d CS |
35 | #include "or1k-desc.h" |
36 | #include "or1k-opc.h" | |
87e6d782 NC |
37 | #include "opintl.h" |
38 | ||
39 | /* Default text to print if an instruction isn't recognized. */ | |
40 | #define UNKNOWN_INSN_MSG _("*unknown*") | |
41 | ||
42 | static void print_normal | |
ffead7ae | 43 | (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); |
87e6d782 | 44 | static void print_address |
bf143b25 | 45 | (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; |
87e6d782 | 46 | static void print_keyword |
bf143b25 | 47 | (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; |
87e6d782 | 48 | static void print_insn_normal |
ffead7ae | 49 | (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); |
0e2ee3ca | 50 | static int print_insn |
33b71eeb | 51 | (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); |
87e6d782 | 52 | static int default_print_insn |
bf143b25 | 53 | (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; |
fc05c67f | 54 | static int read_insn |
33b71eeb | 55 | (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, |
ffead7ae | 56 | unsigned long *); |
87e6d782 | 57 | \f |
47b0e7ad | 58 | /* -- disassembler routines inserted here. */ |
87e6d782 NC |
59 | |
60 | ||
73589c9d | 61 | void or1k_cgen_print_operand |
47b0e7ad | 62 | (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); |
0e2ee3ca | 63 | |
87e6d782 NC |
64 | /* Main entry point for printing operands. |
65 | XINFO is a `void *' and not a `disassemble_info *' to not put a requirement | |
66 | of dis-asm.h on cgen.h. | |
67 | ||
68 | This function is basically just a big switch statement. Earlier versions | |
69 | used tables to look up the function to use, but | |
70 | - if the table contains both assembler and disassembler functions then | |
71 | the disassembler contains much of the assembler and vice-versa, | |
72 | - there's a lot of inlining possibilities as things grow, | |
73 | - using a switch statement avoids the function call overhead. | |
74 | ||
75 | This function could be moved into `print_insn_normal', but keeping it | |
76 | separate makes clear the interface between `print_insn_normal' and each of | |
9a2e995d | 77 | the handlers. */ |
87e6d782 NC |
78 | |
79 | void | |
73589c9d | 80 | or1k_cgen_print_operand (CGEN_CPU_DESC cd, |
47b0e7ad NC |
81 | int opindex, |
82 | void * xinfo, | |
83 | CGEN_FIELDS *fields, | |
84 | void const *attrs ATTRIBUTE_UNUSED, | |
85 | bfd_vma pc, | |
86 | int length) | |
87e6d782 | 87 | { |
47b0e7ad | 88 | disassemble_info *info = (disassemble_info *) xinfo; |
87e6d782 NC |
89 | |
90 | switch (opindex) | |
91 | { | |
73589c9d | 92 | case OR1K_OPERAND_DISP26 : |
87e6d782 NC |
93 | print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
94 | break; | |
73589c9d CS |
95 | case OR1K_OPERAND_RA : |
96 | print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r2, 0); | |
97 | break; | |
98 | case OR1K_OPERAND_RADF : | |
99 | print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0); | |
87e6d782 | 100 | break; |
73589c9d CS |
101 | case OR1K_OPERAND_RASF : |
102 | print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r2, 0); | |
87e6d782 | 103 | break; |
73589c9d CS |
104 | case OR1K_OPERAND_RB : |
105 | print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r3, 0); | |
87e6d782 | 106 | break; |
73589c9d CS |
107 | case OR1K_OPERAND_RBDF : |
108 | print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0); | |
87e6d782 | 109 | break; |
73589c9d CS |
110 | case OR1K_OPERAND_RBSF : |
111 | print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r3, 0); | |
87e6d782 | 112 | break; |
73589c9d CS |
113 | case OR1K_OPERAND_RD : |
114 | print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r1, 0); | |
87e6d782 | 115 | break; |
73589c9d CS |
116 | case OR1K_OPERAND_RDDF : |
117 | print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0); | |
87e6d782 | 118 | break; |
73589c9d CS |
119 | case OR1K_OPERAND_RDSF : |
120 | print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r1, 0); | |
87e6d782 | 121 | break; |
73589c9d CS |
122 | case OR1K_OPERAND_SIMM16 : |
123 | print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); | |
124 | break; | |
125 | case OR1K_OPERAND_SIMM16_SPLIT : | |
126 | print_normal (cd, info, fields->f_simm16_split, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); | |
87e6d782 | 127 | break; |
73589c9d | 128 | case OR1K_OPERAND_UIMM16 : |
87e6d782 NC |
129 | print_normal (cd, info, fields->f_uimm16, 0, pc, length); |
130 | break; | |
73589c9d CS |
131 | case OR1K_OPERAND_UIMM16_SPLIT : |
132 | print_normal (cd, info, fields->f_uimm16_split, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); | |
133 | break; | |
134 | case OR1K_OPERAND_UIMM6 : | |
135 | print_normal (cd, info, fields->f_uimm6, 0, pc, length); | |
87e6d782 NC |
136 | break; |
137 | ||
138 | default : | |
139 | /* xgettext:c-format */ | |
140 | fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), | |
141 | opindex); | |
142 | abort (); | |
143 | } | |
144 | } | |
145 | ||
43e65147 | 146 | cgen_print_fn * const or1k_cgen_print_handlers[] = |
87e6d782 NC |
147 | { |
148 | print_insn_normal, | |
149 | }; | |
150 | ||
151 | ||
152 | void | |
73589c9d | 153 | or1k_cgen_init_dis (CGEN_CPU_DESC cd) |
87e6d782 | 154 | { |
73589c9d CS |
155 | or1k_cgen_init_opcode_table (cd); |
156 | or1k_cgen_init_ibld_table (cd); | |
157 | cd->print_handlers = & or1k_cgen_print_handlers[0]; | |
158 | cd->print_operand = or1k_cgen_print_operand; | |
87e6d782 NC |
159 | } |
160 | ||
161 | \f | |
162 | /* Default print handler. */ | |
163 | ||
164 | static void | |
ffead7ae MM |
165 | print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
166 | void *dis_info, | |
167 | long value, | |
168 | unsigned int attrs, | |
169 | bfd_vma pc ATTRIBUTE_UNUSED, | |
170 | int length ATTRIBUTE_UNUSED) | |
87e6d782 NC |
171 | { |
172 | disassemble_info *info = (disassemble_info *) dis_info; | |
173 | ||
87e6d782 NC |
174 | /* Print the operand as directed by the attributes. */ |
175 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
176 | ; /* nothing to do */ | |
177 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
178 | (*info->fprintf_func) (info->stream, "%ld", value); | |
179 | else | |
180 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
181 | } | |
182 | ||
183 | /* Default address handler. */ | |
184 | ||
185 | static void | |
ffead7ae MM |
186 | print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
187 | void *dis_info, | |
188 | bfd_vma value, | |
189 | unsigned int attrs, | |
190 | bfd_vma pc ATTRIBUTE_UNUSED, | |
191 | int length ATTRIBUTE_UNUSED) | |
87e6d782 NC |
192 | { |
193 | disassemble_info *info = (disassemble_info *) dis_info; | |
194 | ||
87e6d782 NC |
195 | /* Print the operand as directed by the attributes. */ |
196 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
47b0e7ad | 197 | ; /* Nothing to do. */ |
87e6d782 NC |
198 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) |
199 | (*info->print_address_func) (value, info); | |
200 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) | |
201 | (*info->print_address_func) (value, info); | |
202 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
203 | (*info->fprintf_func) (info->stream, "%ld", (long) value); | |
204 | else | |
205 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value); | |
206 | } | |
207 | ||
208 | /* Keyword print handler. */ | |
209 | ||
210 | static void | |
ffead7ae MM |
211 | print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
212 | void *dis_info, | |
213 | CGEN_KEYWORD *keyword_table, | |
214 | long value, | |
215 | unsigned int attrs ATTRIBUTE_UNUSED) | |
87e6d782 NC |
216 | { |
217 | disassemble_info *info = (disassemble_info *) dis_info; | |
218 | const CGEN_KEYWORD_ENTRY *ke; | |
219 | ||
220 | ke = cgen_keyword_lookup_value (keyword_table, value); | |
221 | if (ke != NULL) | |
222 | (*info->fprintf_func) (info->stream, "%s", ke->name); | |
223 | else | |
224 | (*info->fprintf_func) (info->stream, "???"); | |
225 | } | |
226 | \f | |
227 | /* Default insn printer. | |
228 | ||
ffead7ae | 229 | DIS_INFO is defined as `void *' so the disassembler needn't know anything |
87e6d782 NC |
230 | about disassemble_info. */ |
231 | ||
232 | static void | |
ffead7ae MM |
233 | print_insn_normal (CGEN_CPU_DESC cd, |
234 | void *dis_info, | |
235 | const CGEN_INSN *insn, | |
236 | CGEN_FIELDS *fields, | |
237 | bfd_vma pc, | |
238 | int length) | |
87e6d782 NC |
239 | { |
240 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
241 | disassemble_info *info = (disassemble_info *) dis_info; | |
242 | const CGEN_SYNTAX_CHAR_TYPE *syn; | |
243 | ||
244 | CGEN_INIT_PRINT (cd); | |
245 | ||
246 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
247 | { | |
248 | if (CGEN_SYNTAX_MNEMONIC_P (*syn)) | |
249 | { | |
250 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); | |
251 | continue; | |
252 | } | |
253 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
254 | { | |
255 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); | |
256 | continue; | |
257 | } | |
258 | ||
259 | /* We have an operand. */ | |
73589c9d | 260 | or1k_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, |
87e6d782 NC |
261 | fields, CGEN_INSN_ATTRS (insn), pc, length); |
262 | } | |
263 | } | |
264 | \f | |
265 | /* Subroutine of print_insn. Reads an insn into the given buffers and updates | |
266 | the extract info. | |
267 | Returns 0 if all is well, non-zero otherwise. */ | |
0e2ee3ca | 268 | |
87e6d782 | 269 | static int |
ffead7ae MM |
270 | read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
271 | bfd_vma pc, | |
272 | disassemble_info *info, | |
33b71eeb | 273 | bfd_byte *buf, |
ffead7ae MM |
274 | int buflen, |
275 | CGEN_EXTRACT_INFO *ex_info, | |
276 | unsigned long *insn_value) | |
87e6d782 NC |
277 | { |
278 | int status = (*info->read_memory_func) (pc, buf, buflen, info); | |
47b0e7ad | 279 | |
87e6d782 NC |
280 | if (status != 0) |
281 | { | |
282 | (*info->memory_error_func) (status, pc, info); | |
283 | return -1; | |
284 | } | |
285 | ||
286 | ex_info->dis_info = info; | |
287 | ex_info->valid = (1 << buflen) - 1; | |
288 | ex_info->insn_bytes = buf; | |
289 | ||
290 | *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); | |
291 | return 0; | |
292 | } | |
293 | ||
294 | /* Utility to print an insn. | |
295 | BUF is the base part of the insn, target byte order, BUFLEN bytes long. | |
296 | The result is the size of the insn in bytes or zero for an unknown insn | |
297 | or -1 if an error occurs fetching data (memory_error_func will have | |
298 | been called). */ | |
299 | ||
300 | static int | |
ffead7ae MM |
301 | print_insn (CGEN_CPU_DESC cd, |
302 | bfd_vma pc, | |
303 | disassemble_info *info, | |
33b71eeb | 304 | bfd_byte *buf, |
ffead7ae | 305 | unsigned int buflen) |
87e6d782 | 306 | { |
fc7bc883 | 307 | CGEN_INSN_INT insn_value; |
87e6d782 NC |
308 | const CGEN_INSN_LIST *insn_list; |
309 | CGEN_EXTRACT_INFO ex_info; | |
3c3bdf30 | 310 | int basesize; |
87e6d782 | 311 | |
fc7bc883 | 312 | /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ |
3c3bdf30 NC |
313 | basesize = cd->base_insn_bitsize < buflen * 8 ? |
314 | cd->base_insn_bitsize : buflen * 8; | |
315 | insn_value = cgen_get_insn_value (cd, buf, basesize); | |
316 | ||
fc7bc883 RH |
317 | |
318 | /* Fill in ex_info fields like read_insn would. Don't actually call | |
319 | read_insn, since the incoming buffer is already read (and possibly | |
320 | modified a la m32r). */ | |
321 | ex_info.valid = (1 << buflen) - 1; | |
322 | ex_info.dis_info = info; | |
323 | ex_info.insn_bytes = buf; | |
87e6d782 NC |
324 | |
325 | /* The instructions are stored in hash lists. | |
326 | Pick the first one and keep trying until we find the right one. */ | |
327 | ||
33b71eeb | 328 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); |
87e6d782 NC |
329 | while (insn_list != NULL) |
330 | { | |
331 | const CGEN_INSN *insn = insn_list->insn; | |
332 | CGEN_FIELDS fields; | |
333 | int length; | |
fc7bc883 | 334 | unsigned long insn_value_cropped; |
87e6d782 | 335 | |
43e65147 | 336 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED |
0e2ee3ca | 337 | /* Not needed as insn shouldn't be in hash lists if not supported. */ |
87e6d782 | 338 | /* Supported by this cpu? */ |
73589c9d | 339 | if (! or1k_cgen_insn_supported (cd, insn)) |
87e6d782 NC |
340 | { |
341 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
342 | continue; | |
343 | } | |
344 | #endif | |
345 | ||
346 | /* Basic bit mask must be correct. */ | |
347 | /* ??? May wish to allow target to defer this check until the extract | |
348 | handler. */ | |
fc7bc883 RH |
349 | |
350 | /* Base size may exceed this instruction's size. Extract the | |
351 | relevant part from the buffer. */ | |
0e2ee3ca NC |
352 | if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && |
353 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
43e65147 | 354 | insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), |
fc7bc883 RH |
355 | info->endian == BFD_ENDIAN_BIG); |
356 | else | |
357 | insn_value_cropped = insn_value; | |
358 | ||
359 | if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) | |
87e6d782 NC |
360 | == CGEN_INSN_BASE_VALUE (insn)) |
361 | { | |
362 | /* Printing is handled in two passes. The first pass parses the | |
363 | machine insn and extracts the fields. The second pass prints | |
364 | them. */ | |
365 | ||
366 | /* Make sure the entire insn is loaded into insn_value, if it | |
367 | can fit. */ | |
0e2ee3ca NC |
368 | if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && |
369 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
87e6d782 NC |
370 | { |
371 | unsigned long full_insn_value; | |
372 | int rc = read_insn (cd, pc, info, buf, | |
373 | CGEN_INSN_BITSIZE (insn) / 8, | |
374 | & ex_info, & full_insn_value); | |
375 | if (rc != 0) | |
376 | return rc; | |
377 | length = CGEN_EXTRACT_FN (cd, insn) | |
378 | (cd, insn, &ex_info, full_insn_value, &fields, pc); | |
379 | } | |
380 | else | |
381 | length = CGEN_EXTRACT_FN (cd, insn) | |
fc7bc883 | 382 | (cd, insn, &ex_info, insn_value_cropped, &fields, pc); |
87e6d782 | 383 | |
47b0e7ad | 384 | /* Length < 0 -> error. */ |
87e6d782 NC |
385 | if (length < 0) |
386 | return length; | |
387 | if (length > 0) | |
388 | { | |
389 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); | |
47b0e7ad | 390 | /* Length is in bits, result is in bytes. */ |
87e6d782 NC |
391 | return length / 8; |
392 | } | |
393 | } | |
394 | ||
395 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | /* Default value for CGEN_PRINT_INSN. | |
402 | The result is the size of the insn in bytes or zero for an unknown insn | |
403 | or -1 if an error occured fetching bytes. */ | |
404 | ||
405 | #ifndef CGEN_PRINT_INSN | |
406 | #define CGEN_PRINT_INSN default_print_insn | |
407 | #endif | |
408 | ||
409 | static int | |
ffead7ae | 410 | default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) |
87e6d782 | 411 | { |
33b71eeb | 412 | bfd_byte buf[CGEN_MAX_INSN_SIZE]; |
fc7bc883 | 413 | int buflen; |
87e6d782 NC |
414 | int status; |
415 | ||
fc7bc883 RH |
416 | /* Attempt to read the base part of the insn. */ |
417 | buflen = cd->base_insn_bitsize / 8; | |
418 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
419 | ||
420 | /* Try again with the minimum part, if min < base. */ | |
421 | if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) | |
422 | { | |
423 | buflen = cd->min_insn_bitsize / 8; | |
424 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
425 | } | |
87e6d782 | 426 | |
87e6d782 NC |
427 | if (status != 0) |
428 | { | |
429 | (*info->memory_error_func) (status, pc, info); | |
430 | return -1; | |
431 | } | |
432 | ||
fc7bc883 | 433 | return print_insn (cd, pc, info, buf, buflen); |
87e6d782 NC |
434 | } |
435 | ||
436 | /* Main entry point. | |
437 | Print one instruction from PC on INFO->STREAM. | |
438 | Return the size of the instruction (in bytes). */ | |
439 | ||
47b0e7ad NC |
440 | typedef struct cpu_desc_list |
441 | { | |
a978a3e5 | 442 | struct cpu_desc_list *next; |
fb53f5a8 | 443 | CGEN_BITSET *isa; |
a978a3e5 NC |
444 | int mach; |
445 | int endian; | |
446 | CGEN_CPU_DESC cd; | |
447 | } cpu_desc_list; | |
448 | ||
87e6d782 | 449 | int |
73589c9d | 450 | print_insn_or1k (bfd_vma pc, disassemble_info *info) |
87e6d782 | 451 | { |
a978a3e5 NC |
452 | static cpu_desc_list *cd_list = 0; |
453 | cpu_desc_list *cl = 0; | |
87e6d782 | 454 | static CGEN_CPU_DESC cd = 0; |
fb53f5a8 | 455 | static CGEN_BITSET *prev_isa; |
87e6d782 NC |
456 | static int prev_mach; |
457 | static int prev_endian; | |
458 | int length; | |
fb53f5a8 DB |
459 | CGEN_BITSET *isa; |
460 | int mach; | |
87e6d782 NC |
461 | int endian = (info->endian == BFD_ENDIAN_BIG |
462 | ? CGEN_ENDIAN_BIG | |
463 | : CGEN_ENDIAN_LITTLE); | |
464 | enum bfd_architecture arch; | |
465 | ||
466 | /* ??? gdb will set mach but leave the architecture as "unknown" */ | |
467 | #ifndef CGEN_BFD_ARCH | |
73589c9d | 468 | #define CGEN_BFD_ARCH bfd_arch_or1k |
87e6d782 NC |
469 | #endif |
470 | arch = info->arch; | |
471 | if (arch == bfd_arch_unknown) | |
472 | arch = CGEN_BFD_ARCH; | |
43e65147 | 473 | |
87e6d782 NC |
474 | /* There's no standard way to compute the machine or isa number |
475 | so we leave it to the target. */ | |
476 | #ifdef CGEN_COMPUTE_MACH | |
477 | mach = CGEN_COMPUTE_MACH (info); | |
478 | #else | |
479 | mach = info->mach; | |
480 | #endif | |
481 | ||
482 | #ifdef CGEN_COMPUTE_ISA | |
fb53f5a8 DB |
483 | { |
484 | static CGEN_BITSET *permanent_isa; | |
485 | ||
486 | if (!permanent_isa) | |
487 | permanent_isa = cgen_bitset_create (MAX_ISAS); | |
488 | isa = permanent_isa; | |
489 | cgen_bitset_clear (isa); | |
490 | cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); | |
491 | } | |
87e6d782 | 492 | #else |
a978a3e5 | 493 | isa = info->insn_sets; |
87e6d782 NC |
494 | #endif |
495 | ||
a978a3e5 | 496 | /* If we've switched cpu's, try to find a handle we've used before */ |
87e6d782 | 497 | if (cd |
fb53f5a8 | 498 | && (cgen_bitset_compare (isa, prev_isa) != 0 |
87e6d782 NC |
499 | || mach != prev_mach |
500 | || endian != prev_endian)) | |
501 | { | |
87e6d782 | 502 | cd = 0; |
a978a3e5 NC |
503 | for (cl = cd_list; cl; cl = cl->next) |
504 | { | |
fb53f5a8 | 505 | if (cgen_bitset_compare (cl->isa, isa) == 0 && |
a978a3e5 NC |
506 | cl->mach == mach && |
507 | cl->endian == endian) | |
508 | { | |
509 | cd = cl->cd; | |
fb53f5a8 | 510 | prev_isa = cd->isas; |
a978a3e5 NC |
511 | break; |
512 | } | |
513 | } | |
43e65147 | 514 | } |
87e6d782 NC |
515 | |
516 | /* If we haven't initialized yet, initialize the opcode table. */ | |
517 | if (! cd) | |
518 | { | |
519 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); | |
520 | const char *mach_name; | |
521 | ||
522 | if (!arch_type) | |
523 | abort (); | |
524 | mach_name = arch_type->printable_name; | |
525 | ||
fb53f5a8 | 526 | prev_isa = cgen_bitset_copy (isa); |
87e6d782 NC |
527 | prev_mach = mach; |
528 | prev_endian = endian; | |
73589c9d | 529 | cd = or1k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, |
87e6d782 NC |
530 | CGEN_CPU_OPEN_BFDMACH, mach_name, |
531 | CGEN_CPU_OPEN_ENDIAN, prev_endian, | |
532 | CGEN_CPU_OPEN_END); | |
533 | if (!cd) | |
534 | abort (); | |
a978a3e5 | 535 | |
47b0e7ad | 536 | /* Save this away for future reference. */ |
a978a3e5 NC |
537 | cl = xmalloc (sizeof (struct cpu_desc_list)); |
538 | cl->cd = cd; | |
fb53f5a8 | 539 | cl->isa = prev_isa; |
a978a3e5 NC |
540 | cl->mach = mach; |
541 | cl->endian = endian; | |
542 | cl->next = cd_list; | |
543 | cd_list = cl; | |
544 | ||
73589c9d | 545 | or1k_cgen_init_dis (cd); |
87e6d782 NC |
546 | } |
547 | ||
548 | /* We try to have as much common code as possible. | |
549 | But at this point some targets need to take over. */ | |
550 | /* ??? Some targets may need a hook elsewhere. Try to avoid this, | |
551 | but if not possible try to move this hook elsewhere rather than | |
552 | have two hooks. */ | |
553 | length = CGEN_PRINT_INSN (cd, pc, info); | |
554 | if (length > 0) | |
555 | return length; | |
556 | if (length < 0) | |
557 | return -1; | |
558 | ||
559 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
560 | return cd->default_insn_bitsize / 8; | |
561 | } |