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252b5132 | 1 | /* ppc-dis.c -- Disassemble PowerPC instructions |
2571583a | 2 | Copyright (C) 1994-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
9b201bb5 NC |
5 | This file is part of the GNU opcodes library. |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING. If not, write to the | |
19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "sysdep.h" |
df7b86aa | 23 | #include <stdio.h> |
88c1242d | 24 | #include "disassemble.h" |
b9c361e0 | 25 | #include "elf-bfd.h" |
94caa966 | 26 | #include "elf/ppc.h" |
69fe9ce5 | 27 | #include "opintl.h" |
252b5132 | 28 | #include "opcode/ppc.h" |
65b48a81 | 29 | #include "libiberty.h" |
252b5132 RH |
30 | |
31 | /* This file provides several disassembler functions, all of which use | |
32 | the disassembler interface defined in dis-asm.h. Several functions | |
33 | are provided because this file handles disassembly for the PowerPC | |
34 | in both big and little endian mode and also for the POWER (RS/6000) | |
35 | chip. */ | |
fa452fa6 PB |
36 | static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, |
37 | ppc_cpu_t); | |
252b5132 | 38 | |
fa452fa6 PB |
39 | struct dis_private |
40 | { | |
41 | /* Stash the result of parsing disassembler_options here. */ | |
42 | ppc_cpu_t dialect; | |
b240011a | 43 | } private; |
fa452fa6 PB |
44 | |
45 | #define POWERPC_DIALECT(INFO) \ | |
46 | (((struct dis_private *) ((INFO)->private_data))->dialect) | |
418c1742 | 47 | |
69fe9ce5 | 48 | struct ppc_mopt { |
9b753937 | 49 | /* Option string, without -m or -M prefix. */ |
69fe9ce5 | 50 | const char *opt; |
9b753937 | 51 | /* CPU option flags. */ |
69fe9ce5 | 52 | ppc_cpu_t cpu; |
9b753937 AM |
53 | /* Flags that should stay on, even when combined with another cpu |
54 | option. This should only be used for generic options like | |
55 | "-many" or "-maltivec" where it is reasonable to add some | |
56 | capability to another cpu selection. The added flags are sticky | |
57 | so that, for example, "-many -me500" and "-me500 -many" result in | |
58 | the same assembler or disassembler behaviour. Do not use | |
59 | "sticky" for specific cpus, as this will prevent that cpu's flags | |
60 | from overriding the defaults set in powerpc_init_dialect or a | |
61 | prior -m option. */ | |
69fe9ce5 AM |
62 | ppc_cpu_t sticky; |
63 | }; | |
64 | ||
65 | struct ppc_mopt ppc_opts[] = { | |
14b57c7c | 66 | { "403", PPC_OPCODE_PPC | PPC_OPCODE_403, |
69fe9ce5 | 67 | 0 }, |
14b57c7c | 68 | { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405, |
69fe9ce5 | 69 | 0 }, |
bdc70b4a AM |
70 | { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
71 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 72 | 0 }, |
bdc70b4a AM |
73 | { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
74 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 75 | 0 }, |
62adc510 AM |
76 | { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476 |
77 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), | |
9fe54b1c | 78 | 0 }, |
14b57c7c | 79 | { "601", PPC_OPCODE_PPC | PPC_OPCODE_601, |
69fe9ce5 | 80 | 0 }, |
14b57c7c | 81 | { "603", PPC_OPCODE_PPC, |
69fe9ce5 | 82 | 0 }, |
14b57c7c | 83 | { "604", PPC_OPCODE_PPC, |
69fe9ce5 | 84 | 0 }, |
14b57c7c | 85 | { "620", PPC_OPCODE_PPC | PPC_OPCODE_64, |
69fe9ce5 | 86 | 0 }, |
14b57c7c | 87 | { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 88 | 0 }, |
14b57c7c | 89 | { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 90 | 0 }, |
14b57c7c | 91 | { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 92 | 0 }, |
14b57c7c | 93 | { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 94 | 0 }, |
14b57c7c | 95 | { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS |
69fe9ce5 | 96 | , 0 }, |
14b57c7c | 97 | { "821", PPC_OPCODE_PPC | PPC_OPCODE_860, |
ef5a96d5 | 98 | 0 }, |
14b57c7c | 99 | { "850", PPC_OPCODE_PPC | PPC_OPCODE_860, |
ef5a96d5 | 100 | 0 }, |
14b57c7c | 101 | { "860", PPC_OPCODE_PPC | PPC_OPCODE_860, |
ef5a96d5 | 102 | 0 }, |
bdc70b4a AM |
103 | { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 |
104 | | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 | |
105 | | PPC_OPCODE_A2), | |
cdc51b07 | 106 | 0 }, |
14b57c7c | 107 | { "altivec", PPC_OPCODE_PPC, |
4b8b687e | 108 | PPC_OPCODE_ALTIVEC }, |
52be03fd | 109 | { "any", PPC_OPCODE_PPC, |
69fe9ce5 | 110 | PPC_OPCODE_ANY }, |
14b57c7c | 111 | { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, |
69fe9ce5 | 112 | 0 }, |
14b57c7c | 113 | { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, |
69fe9ce5 | 114 | 0 }, |
bdc70b4a AM |
115 | { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
116 | | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 117 | 0 }, |
14b57c7c | 118 | { "com", PPC_OPCODE_COMMON, |
69fe9ce5 | 119 | 0 }, |
dfdaec14 AJ |
120 | { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE |
121 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
122 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
74081948 AF |
123 | | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4 |
124 | | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP), | |
9b753937 | 125 | 0 }, |
14b57c7c | 126 | { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300, |
69fe9ce5 AM |
127 | 0 }, |
128 | { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | |
129 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
130 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 131 | | PPC_OPCODE_E500), |
69fe9ce5 AM |
132 | 0 }, |
133 | { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
134 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
135 | | PPC_OPCODE_E500MC), | |
136 | 0 }, | |
0dc93057 AM |
137 | { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
138 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
63d0fa4e AM |
139 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 |
140 | | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), | |
0dc93057 | 141 | 0 }, |
aea77599 AM |
142 | { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
143 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
144 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | |
c03dc33b | 145 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), |
aea77599 AM |
146 | 0 }, |
147 | { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
148 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
149 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC | |
c03dc33b | 150 | | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4 |
aea77599 AM |
151 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), |
152 | 0 }, | |
69fe9ce5 AM |
153 | { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE |
154 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
155 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 156 | | PPC_OPCODE_E500), |
69fe9ce5 | 157 | 0 }, |
14b57c7c | 158 | { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS, |
69fe9ce5 | 159 | 0 }, |
74081948 AF |
160 | { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2, |
161 | 0 }, | |
14b57c7c | 162 | { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, |
69fe9ce5 | 163 | 0 }, |
bdc70b4a AM |
164 | { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
165 | | PPC_OPCODE_POWER5), | |
69fe9ce5 | 166 | 0 }, |
bdc70b4a AM |
167 | { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
168 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 169 | 0 }, |
bdc70b4a AM |
170 | { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
171 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
172 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 173 | 0 }, |
5817ffd1 PB |
174 | { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
175 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
ef85eab0 | 176 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 |
9a85b496 | 177 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), |
5817ffd1 | 178 | 0 }, |
a680de9a PB |
179 | { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
180 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
181 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | |
ef85eab0 | 182 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), |
a680de9a | 183 | 0 }, |
14b57c7c | 184 | { "ppc", PPC_OPCODE_PPC, |
69fe9ce5 | 185 | 0 }, |
14b57c7c | 186 | { "ppc32", PPC_OPCODE_PPC, |
69fe9ce5 | 187 | 0 }, |
65b48a81 PB |
188 | { "32", PPC_OPCODE_PPC, |
189 | 0 }, | |
14b57c7c | 190 | { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64, |
69fe9ce5 | 191 | 0 }, |
65b48a81 PB |
192 | { "64", PPC_OPCODE_PPC | PPC_OPCODE_64, |
193 | 0 }, | |
14b57c7c | 194 | { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE, |
69fe9ce5 | 195 | 0 }, |
14b57c7c | 196 | { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS, |
69fe9ce5 | 197 | 0 }, |
14b57c7c | 198 | { "pwr", PPC_OPCODE_POWER, |
69fe9ce5 | 199 | 0 }, |
14b57c7c | 200 | { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, |
cdc51b07 | 201 | 0 }, |
14b57c7c | 202 | { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, |
cdc51b07 | 203 | 0 }, |
bdc70b4a AM |
204 | { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
205 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 206 | 0 }, |
bdc70b4a AM |
207 | { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
208 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 209 | 0 }, |
bdc70b4a AM |
210 | { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
211 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
cdc51b07 | 212 | 0 }, |
bdc70b4a AM |
213 | { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
214 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
215 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 216 | 0 }, |
5817ffd1 PB |
217 | { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
218 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
ef85eab0 | 219 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 |
9a85b496 | 220 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), |
5817ffd1 | 221 | 0 }, |
a680de9a PB |
222 | { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
223 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
224 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | |
ef85eab0 | 225 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), |
a680de9a | 226 | 0 }, |
14b57c7c | 227 | { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, |
69fe9ce5 | 228 | 0 }, |
52be03fd AM |
229 | { "raw", PPC_OPCODE_PPC, |
230 | PPC_OPCODE_RAW }, | |
14b57c7c | 231 | { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS, |
69fe9ce5 | 232 | PPC_OPCODE_SPE }, |
74081948 AF |
233 | { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE, |
234 | PPC_OPCODE_SPE2 }, | |
bdc70b4a AM |
235 | { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR |
236 | | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), | |
ce3d2015 | 237 | 0 }, |
14b57c7c AM |
238 | { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE |
239 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
240 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
74081948 | 241 | | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2), |
b9c361e0 | 242 | PPC_OPCODE_VLE }, |
14b57c7c | 243 | { "vsx", PPC_OPCODE_PPC, |
4b8b687e | 244 | PPC_OPCODE_VSX }, |
69fe9ce5 AM |
245 | }; |
246 | ||
b9c361e0 JL |
247 | /* Switch between Booke and VLE dialects for interlinked dumps. */ |
248 | static ppc_cpu_t | |
249 | get_powerpc_dialect (struct disassemble_info *info) | |
250 | { | |
251 | ppc_cpu_t dialect = 0; | |
252 | ||
253 | dialect = POWERPC_DIALECT (info); | |
254 | ||
255 | /* Disassemble according to the section headers flags for VLE-mode. */ | |
256 | if (dialect & PPC_OPCODE_VLE | |
3a2488dd | 257 | && info->section != NULL && info->section->owner != NULL |
94caa966 AM |
258 | && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour |
259 | && elf_object_id (info->section->owner) == PPC32_ELF_DATA | |
260 | && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) | |
b9c361e0 JL |
261 | return dialect; |
262 | else | |
263 | return dialect & ~ PPC_OPCODE_VLE; | |
264 | } | |
265 | ||
69fe9ce5 AM |
266 | /* Handle -m and -M options that set cpu type, and .machine arg. */ |
267 | ||
268 | ppc_cpu_t | |
776fc418 | 269 | ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg) |
69fe9ce5 | 270 | { |
69fe9ce5 AM |
271 | unsigned int i; |
272 | ||
65b48a81 PB |
273 | for (i = 0; i < ARRAY_SIZE (ppc_opts); i++) |
274 | if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0) | |
69fe9ce5 AM |
275 | { |
276 | if (ppc_opts[i].sticky) | |
277 | { | |
776fc418 AM |
278 | *sticky |= ppc_opts[i].sticky; |
279 | if ((ppc_cpu & ~*sticky) != 0) | |
69fe9ce5 AM |
280 | break; |
281 | } | |
282 | ppc_cpu = ppc_opts[i].cpu; | |
283 | break; | |
284 | } | |
65b48a81 | 285 | if (i >= ARRAY_SIZE (ppc_opts)) |
69fe9ce5 AM |
286 | return 0; |
287 | ||
776fc418 | 288 | ppc_cpu |= *sticky; |
69fe9ce5 AM |
289 | return ppc_cpu; |
290 | } | |
291 | ||
292 | /* Determine which set of machines to disassemble for. */ | |
418c1742 | 293 | |
b240011a | 294 | static void |
fa452fa6 | 295 | powerpc_init_dialect (struct disassemble_info *info) |
418c1742 | 296 | { |
69fe9ce5 | 297 | ppc_cpu_t dialect = 0; |
776fc418 | 298 | ppc_cpu_t sticky = 0; |
fa452fa6 PB |
299 | struct dis_private *priv = calloc (sizeof (*priv), 1); |
300 | ||
301 | if (priv == NULL) | |
b240011a | 302 | priv = &private; |
418c1742 | 303 | |
776fc418 AM |
304 | switch (info->mach) |
305 | { | |
306 | case bfd_mach_ppc_403: | |
307 | case bfd_mach_ppc_403gc: | |
4f6ffcd3 | 308 | dialect = ppc_parse_cpu (dialect, &sticky, "403"); |
776fc418 AM |
309 | break; |
310 | case bfd_mach_ppc_405: | |
4f6ffcd3 | 311 | dialect = ppc_parse_cpu (dialect, &sticky, "405"); |
776fc418 AM |
312 | break; |
313 | case bfd_mach_ppc_601: | |
4f6ffcd3 | 314 | dialect = ppc_parse_cpu (dialect, &sticky, "601"); |
776fc418 AM |
315 | break; |
316 | case bfd_mach_ppc_a35: | |
317 | case bfd_mach_ppc_rs64ii: | |
318 | case bfd_mach_ppc_rs64iii: | |
4f6ffcd3 | 319 | dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64; |
776fc418 AM |
320 | break; |
321 | case bfd_mach_ppc_e500: | |
4f6ffcd3 | 322 | dialect = ppc_parse_cpu (dialect, &sticky, "e500"); |
776fc418 AM |
323 | break; |
324 | case bfd_mach_ppc_e500mc: | |
4f6ffcd3 | 325 | dialect = ppc_parse_cpu (dialect, &sticky, "e500mc"); |
776fc418 AM |
326 | break; |
327 | case bfd_mach_ppc_e500mc64: | |
4f6ffcd3 | 328 | dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64"); |
776fc418 AM |
329 | break; |
330 | case bfd_mach_ppc_e5500: | |
4f6ffcd3 | 331 | dialect = ppc_parse_cpu (dialect, &sticky, "e5500"); |
776fc418 AM |
332 | break; |
333 | case bfd_mach_ppc_e6500: | |
4f6ffcd3 | 334 | dialect = ppc_parse_cpu (dialect, &sticky, "e6500"); |
776fc418 AM |
335 | break; |
336 | case bfd_mach_ppc_titan: | |
4f6ffcd3 | 337 | dialect = ppc_parse_cpu (dialect, &sticky, "titan"); |
776fc418 AM |
338 | break; |
339 | case bfd_mach_ppc_vle: | |
4f6ffcd3 | 340 | dialect = ppc_parse_cpu (dialect, &sticky, "vle"); |
776fc418 AM |
341 | break; |
342 | default: | |
a680de9a | 343 | dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY; |
65b48a81 | 344 | break; |
776fc418 AM |
345 | } |
346 | ||
f995bbe8 | 347 | const char *opt; |
65b48a81 | 348 | FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options) |
69fe9ce5 AM |
349 | { |
350 | ppc_cpu_t new_cpu = 0; | |
9b4e5766 | 351 | |
65b48a81 | 352 | if (disassembler_options_cmp (opt, "32") == 0) |
7102e95e | 353 | dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; |
65b48a81 | 354 | else if (disassembler_options_cmp (opt, "64") == 0) |
bdc70b4a | 355 | dialect |= PPC_OPCODE_64; |
65b48a81 PB |
356 | else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0) |
357 | dialect = new_cpu; | |
69fe9ce5 | 358 | else |
65b48a81 | 359 | fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), opt); |
69fe9ce5 | 360 | } |
661bd698 | 361 | |
fa452fa6 PB |
362 | info->private_data = priv; |
363 | POWERPC_DIALECT(info) = dialect; | |
b240011a AM |
364 | } |
365 | ||
b9c361e0 JL |
366 | #define PPC_OPCD_SEGS 64 |
367 | static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; | |
368 | #define VLE_OPCD_SEGS 32 | |
369 | static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; | |
74081948 AF |
370 | #define SPE2_OPCD_SEGS 13 |
371 | static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1]; | |
b240011a AM |
372 | |
373 | /* Calculate opcode table indices to speed up disassembly, | |
374 | and init dialect. */ | |
375 | ||
376 | void | |
377 | disassemble_init_powerpc (struct disassemble_info *info) | |
378 | { | |
379 | int i; | |
d6688282 | 380 | unsigned short last; |
fa452fa6 | 381 | |
27c49e9a | 382 | if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0) |
b240011a | 383 | { |
b240011a | 384 | |
27c49e9a AB |
385 | i = powerpc_num_opcodes; |
386 | while (--i >= 0) | |
387 | { | |
388 | unsigned op = PPC_OP (powerpc_opcodes[i].opcode); | |
389 | ||
390 | powerpc_opcd_indices[op] = i; | |
391 | } | |
392 | ||
393 | last = powerpc_num_opcodes; | |
394 | for (i = PPC_OPCD_SEGS; i > 0; --i) | |
395 | { | |
396 | if (powerpc_opcd_indices[i] == 0) | |
397 | powerpc_opcd_indices[i] = last; | |
398 | last = powerpc_opcd_indices[i]; | |
399 | } | |
400 | ||
401 | i = vle_num_opcodes; | |
402 | while (--i >= 0) | |
403 | { | |
404 | unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); | |
405 | unsigned seg = VLE_OP_TO_SEG (op); | |
406 | ||
407 | vle_opcd_indices[seg] = i; | |
408 | } | |
409 | ||
410 | last = vle_num_opcodes; | |
411 | for (i = VLE_OPCD_SEGS; i > 0; --i) | |
412 | { | |
413 | if (vle_opcd_indices[i] == 0) | |
414 | vle_opcd_indices[i] = last; | |
415 | last = vle_opcd_indices[i]; | |
416 | } | |
b9c361e0 JL |
417 | } |
418 | ||
74081948 AF |
419 | /* SPE2 opcodes */ |
420 | i = spe2_num_opcodes; | |
421 | while (--i >= 0) | |
422 | { | |
423 | unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode); | |
424 | unsigned seg = SPE2_XOP_TO_SEG (xop); | |
425 | ||
426 | spe2_opcd_indices[seg] = i; | |
427 | } | |
428 | ||
429 | last = spe2_num_opcodes; | |
430 | for (i = SPE2_OPCD_SEGS; i > 1; --i) | |
431 | { | |
432 | if (spe2_opcd_indices[i] == 0) | |
433 | spe2_opcd_indices[i] = last; | |
434 | last = spe2_opcd_indices[i]; | |
435 | } | |
436 | ||
b240011a AM |
437 | if (info->arch == bfd_arch_powerpc) |
438 | powerpc_init_dialect (info); | |
418c1742 MG |
439 | } |
440 | ||
441 | /* Print a big endian PowerPC instruction. */ | |
252b5132 RH |
442 | |
443 | int | |
823bbe9d | 444 | print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 445 | { |
b9c361e0 | 446 | return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); |
252b5132 RH |
447 | } |
448 | ||
418c1742 | 449 | /* Print a little endian PowerPC instruction. */ |
252b5132 RH |
450 | |
451 | int | |
823bbe9d | 452 | print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 453 | { |
b9c361e0 | 454 | return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); |
252b5132 RH |
455 | } |
456 | ||
457 | /* Print a POWER (RS/6000) instruction. */ | |
458 | ||
459 | int | |
823bbe9d | 460 | print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 RH |
461 | { |
462 | return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); | |
463 | } | |
464 | ||
ea192fa3 PB |
465 | /* Extract the operand value from the PowerPC or POWER instruction. */ |
466 | ||
467 | static long | |
468 | operand_value_powerpc (const struct powerpc_operand *operand, | |
fa452fa6 | 469 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
470 | { |
471 | long value; | |
472 | int invalid; | |
473 | /* Extract the value from the instruction. */ | |
474 | if (operand->extract) | |
475 | value = (*operand->extract) (insn, dialect, &invalid); | |
476 | else | |
477 | { | |
b9c361e0 JL |
478 | if (operand->shift >= 0) |
479 | value = (insn >> operand->shift) & operand->bitm; | |
480 | else | |
481 | value = (insn << -operand->shift) & operand->bitm; | |
ea192fa3 PB |
482 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
483 | { | |
484 | /* BITM is always some number of zeros followed by some | |
b9c361e0 | 485 | number of ones, followed by some number of zeros. */ |
ea192fa3 PB |
486 | unsigned long top = operand->bitm; |
487 | /* top & -top gives the rightmost 1 bit, so this | |
488 | fills in any trailing zeros. */ | |
489 | top |= (top & -top) - 1; | |
490 | top &= ~(top >> 1); | |
491 | value = (value ^ top) - top; | |
492 | } | |
493 | } | |
494 | ||
495 | return value; | |
496 | } | |
497 | ||
498 | /* Determine whether the optional operand(s) should be printed. */ | |
499 | ||
500 | static int | |
501 | skip_optional_operands (const unsigned char *opindex, | |
fa452fa6 | 502 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
503 | { |
504 | const struct powerpc_operand *operand; | |
505 | ||
506 | for (; *opindex != 0; opindex++) | |
507 | { | |
508 | operand = &powerpc_operands[*opindex]; | |
509 | if ((operand->flags & PPC_OPERAND_NEXT) != 0 | |
510 | || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 | |
11a0cf2e PB |
511 | && operand_value_powerpc (operand, insn, dialect) != |
512 | ppc_optional_operand_value (operand))) | |
ea192fa3 PB |
513 | return 0; |
514 | } | |
515 | ||
516 | return 1; | |
517 | } | |
518 | ||
52be03fd | 519 | /* Find a match for INSN in the opcode table, given machine DIALECT. */ |
b9c361e0 | 520 | |
d6688282 AM |
521 | static const struct powerpc_opcode * |
522 | lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) | |
523 | { | |
52be03fd | 524 | const struct powerpc_opcode *opcode, *opcode_end, *last; |
d6688282 AM |
525 | unsigned long op; |
526 | ||
527 | /* Get the major opcode of the instruction. */ | |
528 | op = PPC_OP (insn); | |
529 | ||
530 | /* Find the first match in the opcode table for this major opcode. */ | |
531 | opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; | |
52be03fd | 532 | last = NULL; |
d6688282 AM |
533 | for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; |
534 | opcode < opcode_end; | |
535 | ++opcode) | |
536 | { | |
537 | const unsigned char *opindex; | |
538 | const struct powerpc_operand *operand; | |
539 | int invalid; | |
540 | ||
541 | if ((insn & opcode->mask) != opcode->opcode | |
52be03fd | 542 | || ((dialect & PPC_OPCODE_ANY) == 0 |
d6688282 AM |
543 | && ((opcode->flags & dialect) == 0 |
544 | || (opcode->deprecated & dialect) != 0))) | |
545 | continue; | |
546 | ||
547 | /* Check validity of operands. */ | |
548 | invalid = 0; | |
549 | for (opindex = opcode->operands; *opindex != 0; opindex++) | |
550 | { | |
551 | operand = powerpc_operands + *opindex; | |
552 | if (operand->extract) | |
553 | (*operand->extract) (insn, dialect, &invalid); | |
554 | } | |
555 | if (invalid) | |
556 | continue; | |
557 | ||
52be03fd AM |
558 | if ((dialect & PPC_OPCODE_RAW) == 0) |
559 | return opcode; | |
560 | ||
561 | /* The raw machine insn is one that is not a specialization. */ | |
562 | if (last == NULL | |
563 | || (last->mask & ~opcode->mask) != 0) | |
564 | last = opcode; | |
d6688282 AM |
565 | } |
566 | ||
52be03fd | 567 | return last; |
d6688282 AM |
568 | } |
569 | ||
b9c361e0 JL |
570 | /* Find a match for INSN in the VLE opcode table. */ |
571 | ||
572 | static const struct powerpc_opcode * | |
573 | lookup_vle (unsigned long insn) | |
574 | { | |
575 | const struct powerpc_opcode *opcode; | |
576 | const struct powerpc_opcode *opcode_end; | |
577 | unsigned op, seg; | |
578 | ||
579 | op = PPC_OP (insn); | |
580 | if (op >= 0x20 && op <= 0x37) | |
581 | { | |
582 | /* This insn has a 4-bit opcode. */ | |
583 | op &= 0x3c; | |
584 | } | |
585 | seg = VLE_OP_TO_SEG (op); | |
586 | ||
587 | /* Find the first match in the opcode table for this major opcode. */ | |
588 | opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; | |
589 | for (opcode = vle_opcodes + vle_opcd_indices[seg]; | |
590 | opcode < opcode_end; | |
591 | ++opcode) | |
592 | { | |
593 | unsigned long table_opcd = opcode->opcode; | |
594 | unsigned long table_mask = opcode->mask; | |
595 | bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); | |
596 | unsigned long insn2; | |
597 | const unsigned char *opindex; | |
598 | const struct powerpc_operand *operand; | |
599 | int invalid; | |
600 | ||
601 | insn2 = insn; | |
602 | if (table_op_is_short) | |
603 | insn2 >>= 16; | |
604 | if ((insn2 & table_mask) != table_opcd) | |
605 | continue; | |
606 | ||
607 | /* Check validity of operands. */ | |
608 | invalid = 0; | |
609 | for (opindex = opcode->operands; *opindex != 0; ++opindex) | |
610 | { | |
611 | operand = powerpc_operands + *opindex; | |
612 | if (operand->extract) | |
613 | (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); | |
614 | } | |
615 | if (invalid) | |
616 | continue; | |
617 | ||
618 | return opcode; | |
619 | } | |
620 | ||
621 | return NULL; | |
622 | } | |
623 | ||
74081948 AF |
624 | /* Find a match for INSN in the SPE2 opcode table. */ |
625 | ||
626 | static const struct powerpc_opcode * | |
627 | lookup_spe2 (unsigned long insn) | |
628 | { | |
629 | const struct powerpc_opcode *opcode, *opcode_end; | |
630 | unsigned op, xop, seg; | |
631 | ||
632 | op = PPC_OP (insn); | |
633 | if (op != 0x4) | |
634 | { | |
635 | /* This is not SPE2 insn. | |
636 | * All SPE2 instructions have OP=4 and differs by XOP */ | |
637 | return NULL; | |
638 | } | |
639 | xop = SPE2_XOP (insn); | |
640 | seg = SPE2_XOP_TO_SEG (xop); | |
641 | ||
642 | /* Find the first match in the opcode table for this major opcode. */ | |
643 | opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1]; | |
644 | for (opcode = spe2_opcodes + spe2_opcd_indices[seg]; | |
645 | opcode < opcode_end; | |
646 | ++opcode) | |
647 | { | |
648 | unsigned long table_opcd = opcode->opcode; | |
649 | unsigned long table_mask = opcode->mask; | |
650 | unsigned long insn2; | |
651 | const unsigned char *opindex; | |
652 | const struct powerpc_operand *operand; | |
653 | int invalid; | |
654 | ||
655 | insn2 = insn; | |
656 | if ((insn2 & table_mask) != table_opcd) | |
657 | continue; | |
658 | ||
659 | /* Check validity of operands. */ | |
660 | invalid = 0; | |
661 | for (opindex = opcode->operands; *opindex != 0; ++opindex) | |
662 | { | |
663 | operand = powerpc_operands + *opindex; | |
664 | if (operand->extract) | |
665 | (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); | |
666 | } | |
667 | if (invalid) | |
668 | continue; | |
669 | ||
670 | return opcode; | |
671 | } | |
672 | ||
673 | return NULL; | |
674 | } | |
675 | ||
252b5132 RH |
676 | /* Print a PowerPC or POWER instruction. */ |
677 | ||
678 | static int | |
823bbe9d AM |
679 | print_insn_powerpc (bfd_vma memaddr, |
680 | struct disassemble_info *info, | |
681 | int bigendian, | |
fa452fa6 | 682 | ppc_cpu_t dialect) |
252b5132 RH |
683 | { |
684 | bfd_byte buffer[4]; | |
685 | int status; | |
686 | unsigned long insn; | |
687 | const struct powerpc_opcode *opcode; | |
b9c361e0 | 688 | bfd_boolean insn_is_short; |
252b5132 RH |
689 | |
690 | status = (*info->read_memory_func) (memaddr, buffer, 4, info); | |
691 | if (status != 0) | |
692 | { | |
b9c361e0 JL |
693 | /* The final instruction may be a 2-byte VLE insn. */ |
694 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
695 | { | |
696 | /* Clear buffer so unused bytes will not have garbage in them. */ | |
697 | buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; | |
698 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
699 | if (status != 0) | |
700 | { | |
701 | (*info->memory_error_func) (status, memaddr, info); | |
702 | return -1; | |
703 | } | |
704 | } | |
705 | else | |
706 | { | |
707 | (*info->memory_error_func) (status, memaddr, info); | |
708 | return -1; | |
709 | } | |
252b5132 RH |
710 | } |
711 | ||
712 | if (bigendian) | |
713 | insn = bfd_getb32 (buffer); | |
714 | else | |
715 | insn = bfd_getl32 (buffer); | |
716 | ||
b9c361e0 JL |
717 | /* Get the major opcode of the insn. */ |
718 | opcode = NULL; | |
719 | insn_is_short = FALSE; | |
720 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
721 | { | |
722 | opcode = lookup_vle (insn); | |
723 | if (opcode != NULL) | |
724 | insn_is_short = PPC_OP_SE_VLE(opcode->mask); | |
725 | } | |
74081948 AF |
726 | if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0) |
727 | opcode = lookup_spe2 (insn); | |
b9c361e0 | 728 | if (opcode == NULL) |
52be03fd | 729 | opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY); |
d6688282 | 730 | if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) |
52be03fd | 731 | opcode = lookup_powerpc (insn, dialect); |
252b5132 | 732 | |
d6688282 | 733 | if (opcode != NULL) |
252b5132 | 734 | { |
252b5132 RH |
735 | const unsigned char *opindex; |
736 | const struct powerpc_operand *operand; | |
252b5132 RH |
737 | int need_comma; |
738 | int need_paren; | |
ea192fa3 | 739 | int skip_optional; |
252b5132 | 740 | |
252b5132 | 741 | if (opcode->operands[0] != 0) |
fdd12ef3 AM |
742 | (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); |
743 | else | |
744 | (*info->fprintf_func) (info->stream, "%s", opcode->name); | |
252b5132 | 745 | |
b9c361e0 JL |
746 | if (insn_is_short) |
747 | /* The operands will be fetched out of the 16-bit instruction. */ | |
748 | insn >>= 16; | |
749 | ||
252b5132 RH |
750 | /* Now extract and print the operands. */ |
751 | need_comma = 0; | |
752 | need_paren = 0; | |
ea192fa3 | 753 | skip_optional = -1; |
252b5132 RH |
754 | for (opindex = opcode->operands; *opindex != 0; opindex++) |
755 | { | |
756 | long value; | |
757 | ||
758 | operand = powerpc_operands + *opindex; | |
759 | ||
760 | /* Operands that are marked FAKE are simply ignored. We | |
761 | already made sure that the extract function considered | |
762 | the instruction to be valid. */ | |
763 | if ((operand->flags & PPC_OPERAND_FAKE) != 0) | |
764 | continue; | |
765 | ||
ea192fa3 PB |
766 | /* If all of the optional operands have the value zero, |
767 | then don't print any of them. */ | |
65b650b4 AM |
768 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
769 | { | |
770 | if (skip_optional < 0) | |
771 | skip_optional = skip_optional_operands (opindex, insn, | |
772 | dialect); | |
773 | if (skip_optional) | |
774 | continue; | |
775 | } | |
252b5132 | 776 | |
ea192fa3 PB |
777 | value = operand_value_powerpc (operand, insn, dialect); |
778 | ||
252b5132 RH |
779 | if (need_comma) |
780 | { | |
781 | (*info->fprintf_func) (info->stream, ","); | |
782 | need_comma = 0; | |
783 | } | |
784 | ||
785 | /* Print the operand as directed by the flags. */ | |
fdd12ef3 AM |
786 | if ((operand->flags & PPC_OPERAND_GPR) != 0 |
787 | || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) | |
252b5132 RH |
788 | (*info->fprintf_func) (info->stream, "r%ld", value); |
789 | else if ((operand->flags & PPC_OPERAND_FPR) != 0) | |
790 | (*info->fprintf_func) (info->stream, "f%ld", value); | |
786e2c0f C |
791 | else if ((operand->flags & PPC_OPERAND_VR) != 0) |
792 | (*info->fprintf_func) (info->stream, "v%ld", value); | |
9b4e5766 PB |
793 | else if ((operand->flags & PPC_OPERAND_VSR) != 0) |
794 | (*info->fprintf_func) (info->stream, "vs%ld", value); | |
252b5132 RH |
795 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) |
796 | (*info->print_address_func) (memaddr + value, info); | |
797 | else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
798 | (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); | |
43e65147 | 799 | else if ((operand->flags & PPC_OPERAND_FSL) != 0) |
081ba1b3 AM |
800 | (*info->fprintf_func) (info->stream, "fsl%ld", value); |
801 | else if ((operand->flags & PPC_OPERAND_FCR) != 0) | |
802 | (*info->fprintf_func) (info->stream, "fcr%ld", value); | |
803 | else if ((operand->flags & PPC_OPERAND_UDI) != 0) | |
804 | (*info->fprintf_func) (info->stream, "%ld", value); | |
b9c361e0 JL |
805 | else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 |
806 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
807 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
808 | (*info->fprintf_func) (info->stream, "cr%ld", value); | |
809 | else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
810 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
811 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
252b5132 | 812 | { |
b9c361e0 JL |
813 | static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; |
814 | int cr; | |
815 | int cc; | |
816 | ||
817 | cr = value >> 2; | |
818 | if (cr != 0) | |
819 | (*info->fprintf_func) (info->stream, "4*cr%d+", cr); | |
820 | cc = value & 3; | |
821 | (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); | |
252b5132 | 822 | } |
70dc4e32 | 823 | else |
d908c8af | 824 | (*info->fprintf_func) (info->stream, "%d", (int) value); |
252b5132 RH |
825 | |
826 | if (need_paren) | |
827 | { | |
828 | (*info->fprintf_func) (info->stream, ")"); | |
829 | need_paren = 0; | |
830 | } | |
831 | ||
832 | if ((operand->flags & PPC_OPERAND_PARENS) == 0) | |
833 | need_comma = 1; | |
834 | else | |
835 | { | |
836 | (*info->fprintf_func) (info->stream, "("); | |
837 | need_paren = 1; | |
838 | } | |
839 | } | |
840 | ||
b9c361e0 JL |
841 | /* We have found and printed an instruction. |
842 | If it was a short VLE instruction we have more to do. */ | |
843 | if (insn_is_short) | |
844 | { | |
845 | memaddr += 2; | |
846 | return 2; | |
847 | } | |
848 | else | |
849 | /* Otherwise, return. */ | |
850 | return 4; | |
252b5132 RH |
851 | } |
852 | ||
853 | /* We could not find a match. */ | |
854 | (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); | |
855 | ||
856 | return 4; | |
857 | } | |
07dd56a9 | 858 | |
65b48a81 PB |
859 | const disasm_options_t * |
860 | disassembler_options_powerpc (void) | |
861 | { | |
862 | static disasm_options_t *opts = NULL; | |
863 | ||
864 | if (opts == NULL) | |
865 | { | |
866 | size_t i, num_options = ARRAY_SIZE (ppc_opts); | |
867 | opts = XNEW (disasm_options_t); | |
868 | opts->name = XNEWVEC (const char *, num_options + 1); | |
869 | for (i = 0; i < num_options; i++) | |
870 | opts->name[i] = ppc_opts[i].opt; | |
871 | /* The array we return must be NULL terminated. */ | |
872 | opts->name[i] = NULL; | |
873 | opts->description = NULL; | |
874 | } | |
875 | ||
876 | return opts; | |
877 | } | |
878 | ||
07dd56a9 | 879 | void |
823bbe9d | 880 | print_ppc_disassembler_options (FILE *stream) |
07dd56a9 | 881 | { |
69fe9ce5 AM |
882 | unsigned int i, col; |
883 | ||
884 | fprintf (stream, _("\n\ | |
07dd56a9 | 885 | The following PPC specific disassembler options are supported for use with\n\ |
69fe9ce5 AM |
886 | the -M switch:\n")); |
887 | ||
65b48a81 | 888 | for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++) |
69fe9ce5 AM |
889 | { |
890 | col += fprintf (stream, " %s,", ppc_opts[i].opt); | |
891 | if (col > 66) | |
892 | { | |
893 | fprintf (stream, "\n"); | |
894 | col = 0; | |
895 | } | |
896 | } | |
65b48a81 | 897 | fprintf (stream, "\n"); |
07dd56a9 | 898 | } |