Commit | Line | Data |
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252b5132 | 1 | /* ppc-dis.c -- Disassemble PowerPC instructions |
081ba1b3 | 2 | Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, |
aea77599 | 3 | 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. |
252b5132 RH |
4 | Written by Ian Lance Taylor, Cygnus Support |
5 | ||
9b201bb5 NC |
6 | This file is part of the GNU opcodes library. |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | It is distributed in the hope that it will be useful, but WITHOUT | |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this file; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
21 | MA 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "sysdep.h" |
df7b86aa | 24 | #include <stdio.h> |
252b5132 | 25 | #include "dis-asm.h" |
b9c361e0 | 26 | #include "elf-bfd.h" |
94caa966 | 27 | #include "elf/ppc.h" |
69fe9ce5 | 28 | #include "opintl.h" |
252b5132 RH |
29 | #include "opcode/ppc.h" |
30 | ||
31 | /* This file provides several disassembler functions, all of which use | |
32 | the disassembler interface defined in dis-asm.h. Several functions | |
33 | are provided because this file handles disassembly for the PowerPC | |
34 | in both big and little endian mode and also for the POWER (RS/6000) | |
35 | chip. */ | |
fa452fa6 PB |
36 | static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, |
37 | ppc_cpu_t); | |
252b5132 | 38 | |
fa452fa6 PB |
39 | struct dis_private |
40 | { | |
41 | /* Stash the result of parsing disassembler_options here. */ | |
42 | ppc_cpu_t dialect; | |
b240011a | 43 | } private; |
fa452fa6 PB |
44 | |
45 | #define POWERPC_DIALECT(INFO) \ | |
46 | (((struct dis_private *) ((INFO)->private_data))->dialect) | |
418c1742 | 47 | |
69fe9ce5 AM |
48 | struct ppc_mopt { |
49 | const char *opt; | |
50 | ppc_cpu_t cpu; | |
51 | ppc_cpu_t sticky; | |
52 | }; | |
53 | ||
54 | struct ppc_mopt ppc_opts[] = { | |
bdc70b4a | 55 | { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403), |
69fe9ce5 | 56 | 0 }, |
bdc70b4a | 57 | { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405), |
69fe9ce5 | 58 | 0 }, |
bdc70b4a AM |
59 | { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
60 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 61 | 0 }, |
bdc70b4a AM |
62 | { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
63 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 64 | 0 }, |
bdc70b4a AM |
65 | { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440 |
66 | | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), | |
9fe54b1c | 67 | 0 }, |
bdc70b4a | 68 | { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601), |
69fe9ce5 | 69 | 0 }, |
bdc70b4a | 70 | { "603", (PPC_OPCODE_PPC), |
69fe9ce5 | 71 | 0 }, |
bdc70b4a | 72 | { "604", (PPC_OPCODE_PPC), |
69fe9ce5 | 73 | 0 }, |
bdc70b4a | 74 | { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64), |
69fe9ce5 | 75 | 0 }, |
bdc70b4a | 76 | { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 | 77 | 0 }, |
bdc70b4a | 78 | { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 | 79 | 0 }, |
bdc70b4a | 80 | { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 | 81 | 0 }, |
bdc70b4a | 82 | { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 AM |
83 | 0 }, |
84 | { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS) | |
85 | , 0 }, | |
bdc70b4a AM |
86 | { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 |
87 | | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 | |
88 | | PPC_OPCODE_A2), | |
cdc51b07 | 89 | 0 }, |
bdc70b4a | 90 | { "altivec", (PPC_OPCODE_PPC), |
69fe9ce5 AM |
91 | PPC_OPCODE_ALTIVEC }, |
92 | { "any", 0, | |
93 | PPC_OPCODE_ANY }, | |
bdc70b4a | 94 | { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), |
69fe9ce5 | 95 | 0 }, |
bdc70b4a | 96 | { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), |
69fe9ce5 | 97 | 0 }, |
bdc70b4a AM |
98 | { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
99 | | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 100 | 0 }, |
bdc70b4a | 101 | { "com", (PPC_OPCODE_COMMON), |
69fe9ce5 | 102 | 0 }, |
bdc70b4a | 103 | { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300), |
69fe9ce5 AM |
104 | 0 }, |
105 | { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | |
106 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
107 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 108 | | PPC_OPCODE_E500), |
69fe9ce5 AM |
109 | 0 }, |
110 | { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
111 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
112 | | PPC_OPCODE_E500MC), | |
113 | 0 }, | |
0dc93057 AM |
114 | { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
115 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
63d0fa4e AM |
116 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 |
117 | | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), | |
0dc93057 | 118 | 0 }, |
aea77599 AM |
119 | { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
120 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
121 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | |
122 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
123 | | PPC_OPCODE_POWER7), | |
124 | 0 }, | |
125 | { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
126 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
127 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC | |
128 | | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 | |
129 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), | |
130 | 0 }, | |
69fe9ce5 AM |
131 | { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE |
132 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
133 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 134 | | PPC_OPCODE_E500), |
69fe9ce5 AM |
135 | 0 }, |
136 | { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), | |
137 | 0 }, | |
bdc70b4a | 138 | { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), |
69fe9ce5 | 139 | 0 }, |
bdc70b4a AM |
140 | { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
141 | | PPC_OPCODE_POWER5), | |
69fe9ce5 | 142 | 0 }, |
bdc70b4a AM |
143 | { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
144 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 145 | 0 }, |
bdc70b4a AM |
146 | { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
147 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
148 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 149 | 0 }, |
bdc70b4a | 150 | { "ppc", (PPC_OPCODE_PPC), |
69fe9ce5 | 151 | 0 }, |
bdc70b4a | 152 | { "ppc32", (PPC_OPCODE_PPC), |
69fe9ce5 | 153 | 0 }, |
bdc70b4a | 154 | { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64), |
69fe9ce5 | 155 | 0 }, |
bdc70b4a | 156 | { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE), |
69fe9ce5 AM |
157 | 0 }, |
158 | { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS), | |
159 | 0 }, | |
bdc70b4a | 160 | { "pwr", (PPC_OPCODE_POWER), |
69fe9ce5 | 161 | 0 }, |
bdc70b4a | 162 | { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), |
cdc51b07 | 163 | 0 }, |
bdc70b4a | 164 | { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), |
cdc51b07 | 165 | 0 }, |
bdc70b4a AM |
166 | { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
167 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 168 | 0 }, |
bdc70b4a AM |
169 | { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
170 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 171 | 0 }, |
bdc70b4a AM |
172 | { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
173 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
cdc51b07 | 174 | 0 }, |
bdc70b4a AM |
175 | { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
176 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
177 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 178 | 0 }, |
bdc70b4a | 179 | { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), |
69fe9ce5 AM |
180 | 0 }, |
181 | { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), | |
182 | PPC_OPCODE_SPE }, | |
bdc70b4a AM |
183 | { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR |
184 | | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), | |
ce3d2015 | 185 | 0 }, |
b9c361e0 JL |
186 | { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE), |
187 | PPC_OPCODE_VLE }, | |
bdc70b4a | 188 | { "vsx", (PPC_OPCODE_PPC), |
69fe9ce5 AM |
189 | PPC_OPCODE_VSX }, |
190 | }; | |
191 | ||
b9c361e0 JL |
192 | /* Switch between Booke and VLE dialects for interlinked dumps. */ |
193 | static ppc_cpu_t | |
194 | get_powerpc_dialect (struct disassemble_info *info) | |
195 | { | |
196 | ppc_cpu_t dialect = 0; | |
197 | ||
198 | dialect = POWERPC_DIALECT (info); | |
199 | ||
200 | /* Disassemble according to the section headers flags for VLE-mode. */ | |
201 | if (dialect & PPC_OPCODE_VLE | |
94caa966 AM |
202 | && info->section->owner != NULL |
203 | && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour | |
204 | && elf_object_id (info->section->owner) == PPC32_ELF_DATA | |
205 | && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) | |
b9c361e0 JL |
206 | return dialect; |
207 | else | |
208 | return dialect & ~ PPC_OPCODE_VLE; | |
209 | } | |
210 | ||
69fe9ce5 AM |
211 | /* Handle -m and -M options that set cpu type, and .machine arg. */ |
212 | ||
213 | ppc_cpu_t | |
214 | ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg) | |
215 | { | |
b9c361e0 JL |
216 | const ppc_cpu_t retain_mask = (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX |
217 | | PPC_OPCODE_SPE | PPC_OPCODE_ANY | |
218 | | PPC_OPCODE_VLE | PPC_OPCODE_PMR); | |
69fe9ce5 | 219 | /* Sticky bits. */ |
b9c361e0 | 220 | ppc_cpu_t retain_flags = ppc_cpu & retain_mask; |
69fe9ce5 AM |
221 | unsigned int i; |
222 | ||
223 | for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) | |
224 | if (strcmp (ppc_opts[i].opt, arg) == 0) | |
225 | { | |
226 | if (ppc_opts[i].sticky) | |
227 | { | |
228 | retain_flags |= ppc_opts[i].sticky; | |
b9c361e0 | 229 | if ((ppc_cpu & ~retain_mask) != 0) |
69fe9ce5 AM |
230 | break; |
231 | } | |
232 | ppc_cpu = ppc_opts[i].cpu; | |
233 | break; | |
234 | } | |
235 | if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0])) | |
236 | return 0; | |
237 | ||
238 | ppc_cpu |= retain_flags; | |
239 | return ppc_cpu; | |
240 | } | |
241 | ||
242 | /* Determine which set of machines to disassemble for. */ | |
418c1742 | 243 | |
b240011a | 244 | static void |
fa452fa6 | 245 | powerpc_init_dialect (struct disassemble_info *info) |
418c1742 | 246 | { |
69fe9ce5 AM |
247 | ppc_cpu_t dialect = 0; |
248 | char *arg; | |
fa452fa6 PB |
249 | struct dis_private *priv = calloc (sizeof (*priv), 1); |
250 | ||
251 | if (priv == NULL) | |
b240011a | 252 | priv = &private; |
418c1742 | 253 | |
69fe9ce5 AM |
254 | arg = info->disassembler_options; |
255 | while (arg != NULL) | |
256 | { | |
257 | ppc_cpu_t new_cpu = 0; | |
258 | char *end = strchr (arg, ','); | |
9b4e5766 | 259 | |
69fe9ce5 AM |
260 | if (end != NULL) |
261 | *end = 0; | |
9b4e5766 | 262 | |
69fe9ce5 AM |
263 | if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0) |
264 | dialect = new_cpu; | |
265 | else if (strcmp (arg, "32") == 0) | |
7102e95e | 266 | dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; |
69fe9ce5 | 267 | else if (strcmp (arg, "64") == 0) |
bdc70b4a | 268 | dialect |= PPC_OPCODE_64; |
69fe9ce5 AM |
269 | else |
270 | fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); | |
9622b051 | 271 | |
69fe9ce5 AM |
272 | if (end != NULL) |
273 | *end++ = ','; | |
274 | arg = end; | |
275 | } | |
661bd698 | 276 | |
7102e95e | 277 | if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0) |
802a735e | 278 | { |
70dc4e32 PB |
279 | if (info->mach == bfd_mach_ppc64) |
280 | dialect |= PPC_OPCODE_64; | |
281 | else | |
7102e95e | 282 | dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; |
b9c361e0 JL |
283 | if (info->mach == bfd_mach_ppc_vle) |
284 | dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE; | |
285 | else | |
286 | /* Choose a reasonable default. */ | |
287 | dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601 | |
288 | | PPC_OPCODE_ALTIVEC); | |
802a735e AM |
289 | } |
290 | ||
fa452fa6 PB |
291 | info->private_data = priv; |
292 | POWERPC_DIALECT(info) = dialect; | |
b240011a AM |
293 | } |
294 | ||
b9c361e0 JL |
295 | #define PPC_OPCD_SEGS 64 |
296 | static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; | |
297 | #define VLE_OPCD_SEGS 32 | |
298 | static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; | |
b240011a AM |
299 | |
300 | /* Calculate opcode table indices to speed up disassembly, | |
301 | and init dialect. */ | |
302 | ||
303 | void | |
304 | disassemble_init_powerpc (struct disassemble_info *info) | |
305 | { | |
306 | int i; | |
d6688282 | 307 | unsigned short last; |
fa452fa6 | 308 | |
b240011a AM |
309 | i = powerpc_num_opcodes; |
310 | while (--i >= 0) | |
311 | { | |
312 | unsigned op = PPC_OP (powerpc_opcodes[i].opcode); | |
b240011a | 313 | |
d6688282 AM |
314 | powerpc_opcd_indices[op] = i; |
315 | } | |
316 | ||
317 | last = powerpc_num_opcodes; | |
b9c361e0 | 318 | for (i = PPC_OPCD_SEGS; i > 0; --i) |
d6688282 AM |
319 | { |
320 | if (powerpc_opcd_indices[i] == 0) | |
321 | powerpc_opcd_indices[i] = last; | |
322 | last = powerpc_opcd_indices[i]; | |
b240011a AM |
323 | } |
324 | ||
b9c361e0 JL |
325 | i = vle_num_opcodes; |
326 | while (--i >= 0) | |
327 | { | |
328 | unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); | |
329 | unsigned seg = VLE_OP_TO_SEG (op); | |
330 | ||
331 | vle_opcd_indices[seg] = i; | |
332 | } | |
333 | ||
334 | last = vle_num_opcodes; | |
335 | for (i = VLE_OPCD_SEGS; i > 0; --i) | |
336 | { | |
337 | if (vle_opcd_indices[i] == 0) | |
338 | vle_opcd_indices[i] = last; | |
339 | last = vle_opcd_indices[i]; | |
340 | } | |
341 | ||
b240011a AM |
342 | if (info->arch == bfd_arch_powerpc) |
343 | powerpc_init_dialect (info); | |
418c1742 MG |
344 | } |
345 | ||
346 | /* Print a big endian PowerPC instruction. */ | |
252b5132 RH |
347 | |
348 | int | |
823bbe9d | 349 | print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 350 | { |
b9c361e0 | 351 | return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); |
252b5132 RH |
352 | } |
353 | ||
418c1742 | 354 | /* Print a little endian PowerPC instruction. */ |
252b5132 RH |
355 | |
356 | int | |
823bbe9d | 357 | print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 358 | { |
b9c361e0 | 359 | return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); |
252b5132 RH |
360 | } |
361 | ||
362 | /* Print a POWER (RS/6000) instruction. */ | |
363 | ||
364 | int | |
823bbe9d | 365 | print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 RH |
366 | { |
367 | return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); | |
368 | } | |
369 | ||
ea192fa3 PB |
370 | /* Extract the operand value from the PowerPC or POWER instruction. */ |
371 | ||
372 | static long | |
373 | operand_value_powerpc (const struct powerpc_operand *operand, | |
fa452fa6 | 374 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
375 | { |
376 | long value; | |
377 | int invalid; | |
378 | /* Extract the value from the instruction. */ | |
379 | if (operand->extract) | |
380 | value = (*operand->extract) (insn, dialect, &invalid); | |
381 | else | |
382 | { | |
b9c361e0 JL |
383 | if (operand->shift >= 0) |
384 | value = (insn >> operand->shift) & operand->bitm; | |
385 | else | |
386 | value = (insn << -operand->shift) & operand->bitm; | |
ea192fa3 PB |
387 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
388 | { | |
389 | /* BITM is always some number of zeros followed by some | |
b9c361e0 | 390 | number of ones, followed by some number of zeros. */ |
ea192fa3 PB |
391 | unsigned long top = operand->bitm; |
392 | /* top & -top gives the rightmost 1 bit, so this | |
393 | fills in any trailing zeros. */ | |
394 | top |= (top & -top) - 1; | |
395 | top &= ~(top >> 1); | |
396 | value = (value ^ top) - top; | |
397 | } | |
398 | } | |
399 | ||
400 | return value; | |
401 | } | |
402 | ||
403 | /* Determine whether the optional operand(s) should be printed. */ | |
404 | ||
405 | static int | |
406 | skip_optional_operands (const unsigned char *opindex, | |
fa452fa6 | 407 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
408 | { |
409 | const struct powerpc_operand *operand; | |
410 | ||
411 | for (; *opindex != 0; opindex++) | |
412 | { | |
413 | operand = &powerpc_operands[*opindex]; | |
414 | if ((operand->flags & PPC_OPERAND_NEXT) != 0 | |
415 | || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 | |
416 | && operand_value_powerpc (operand, insn, dialect) != 0)) | |
417 | return 0; | |
418 | } | |
419 | ||
420 | return 1; | |
421 | } | |
422 | ||
d6688282 AM |
423 | /* Find a match for INSN in the opcode table, given machine DIALECT. |
424 | A DIALECT of -1 is special, matching all machine opcode variations. */ | |
b9c361e0 | 425 | |
d6688282 AM |
426 | static const struct powerpc_opcode * |
427 | lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) | |
428 | { | |
429 | const struct powerpc_opcode *opcode; | |
430 | const struct powerpc_opcode *opcode_end; | |
431 | unsigned long op; | |
432 | ||
433 | /* Get the major opcode of the instruction. */ | |
434 | op = PPC_OP (insn); | |
435 | ||
436 | /* Find the first match in the opcode table for this major opcode. */ | |
437 | opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; | |
438 | for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; | |
439 | opcode < opcode_end; | |
440 | ++opcode) | |
441 | { | |
442 | const unsigned char *opindex; | |
443 | const struct powerpc_operand *operand; | |
444 | int invalid; | |
445 | ||
446 | if ((insn & opcode->mask) != opcode->opcode | |
447 | || (dialect != (ppc_cpu_t) -1 | |
448 | && ((opcode->flags & dialect) == 0 | |
449 | || (opcode->deprecated & dialect) != 0))) | |
450 | continue; | |
451 | ||
452 | /* Check validity of operands. */ | |
453 | invalid = 0; | |
454 | for (opindex = opcode->operands; *opindex != 0; opindex++) | |
455 | { | |
456 | operand = powerpc_operands + *opindex; | |
457 | if (operand->extract) | |
458 | (*operand->extract) (insn, dialect, &invalid); | |
459 | } | |
460 | if (invalid) | |
461 | continue; | |
462 | ||
463 | return opcode; | |
464 | } | |
465 | ||
466 | return NULL; | |
467 | } | |
468 | ||
b9c361e0 JL |
469 | /* Find a match for INSN in the VLE opcode table. */ |
470 | ||
471 | static const struct powerpc_opcode * | |
472 | lookup_vle (unsigned long insn) | |
473 | { | |
474 | const struct powerpc_opcode *opcode; | |
475 | const struct powerpc_opcode *opcode_end; | |
476 | unsigned op, seg; | |
477 | ||
478 | op = PPC_OP (insn); | |
479 | if (op >= 0x20 && op <= 0x37) | |
480 | { | |
481 | /* This insn has a 4-bit opcode. */ | |
482 | op &= 0x3c; | |
483 | } | |
484 | seg = VLE_OP_TO_SEG (op); | |
485 | ||
486 | /* Find the first match in the opcode table for this major opcode. */ | |
487 | opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; | |
488 | for (opcode = vle_opcodes + vle_opcd_indices[seg]; | |
489 | opcode < opcode_end; | |
490 | ++opcode) | |
491 | { | |
492 | unsigned long table_opcd = opcode->opcode; | |
493 | unsigned long table_mask = opcode->mask; | |
494 | bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); | |
495 | unsigned long insn2; | |
496 | const unsigned char *opindex; | |
497 | const struct powerpc_operand *operand; | |
498 | int invalid; | |
499 | ||
500 | insn2 = insn; | |
501 | if (table_op_is_short) | |
502 | insn2 >>= 16; | |
503 | if ((insn2 & table_mask) != table_opcd) | |
504 | continue; | |
505 | ||
506 | /* Check validity of operands. */ | |
507 | invalid = 0; | |
508 | for (opindex = opcode->operands; *opindex != 0; ++opindex) | |
509 | { | |
510 | operand = powerpc_operands + *opindex; | |
511 | if (operand->extract) | |
512 | (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); | |
513 | } | |
514 | if (invalid) | |
515 | continue; | |
516 | ||
517 | return opcode; | |
518 | } | |
519 | ||
520 | return NULL; | |
521 | } | |
522 | ||
252b5132 RH |
523 | /* Print a PowerPC or POWER instruction. */ |
524 | ||
525 | static int | |
823bbe9d AM |
526 | print_insn_powerpc (bfd_vma memaddr, |
527 | struct disassemble_info *info, | |
528 | int bigendian, | |
fa452fa6 | 529 | ppc_cpu_t dialect) |
252b5132 RH |
530 | { |
531 | bfd_byte buffer[4]; | |
532 | int status; | |
533 | unsigned long insn; | |
534 | const struct powerpc_opcode *opcode; | |
b9c361e0 | 535 | bfd_boolean insn_is_short; |
252b5132 RH |
536 | |
537 | status = (*info->read_memory_func) (memaddr, buffer, 4, info); | |
538 | if (status != 0) | |
539 | { | |
b9c361e0 JL |
540 | /* The final instruction may be a 2-byte VLE insn. */ |
541 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
542 | { | |
543 | /* Clear buffer so unused bytes will not have garbage in them. */ | |
544 | buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; | |
545 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
546 | if (status != 0) | |
547 | { | |
548 | (*info->memory_error_func) (status, memaddr, info); | |
549 | return -1; | |
550 | } | |
551 | } | |
552 | else | |
553 | { | |
554 | (*info->memory_error_func) (status, memaddr, info); | |
555 | return -1; | |
556 | } | |
252b5132 RH |
557 | } |
558 | ||
559 | if (bigendian) | |
560 | insn = bfd_getb32 (buffer); | |
561 | else | |
562 | insn = bfd_getl32 (buffer); | |
563 | ||
b9c361e0 JL |
564 | /* Get the major opcode of the insn. */ |
565 | opcode = NULL; | |
566 | insn_is_short = FALSE; | |
567 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
568 | { | |
569 | opcode = lookup_vle (insn); | |
570 | if (opcode != NULL) | |
571 | insn_is_short = PPC_OP_SE_VLE(opcode->mask); | |
572 | } | |
573 | if (opcode == NULL) | |
574 | opcode = lookup_powerpc (insn, dialect); | |
d6688282 AM |
575 | if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) |
576 | opcode = lookup_powerpc (insn, (ppc_cpu_t) -1); | |
252b5132 | 577 | |
d6688282 | 578 | if (opcode != NULL) |
252b5132 | 579 | { |
252b5132 RH |
580 | const unsigned char *opindex; |
581 | const struct powerpc_operand *operand; | |
252b5132 RH |
582 | int need_comma; |
583 | int need_paren; | |
ea192fa3 | 584 | int skip_optional; |
252b5132 | 585 | |
252b5132 | 586 | if (opcode->operands[0] != 0) |
fdd12ef3 AM |
587 | (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); |
588 | else | |
589 | (*info->fprintf_func) (info->stream, "%s", opcode->name); | |
252b5132 | 590 | |
b9c361e0 JL |
591 | if (insn_is_short) |
592 | /* The operands will be fetched out of the 16-bit instruction. */ | |
593 | insn >>= 16; | |
594 | ||
252b5132 RH |
595 | /* Now extract and print the operands. */ |
596 | need_comma = 0; | |
597 | need_paren = 0; | |
ea192fa3 | 598 | skip_optional = -1; |
252b5132 RH |
599 | for (opindex = opcode->operands; *opindex != 0; opindex++) |
600 | { | |
601 | long value; | |
602 | ||
603 | operand = powerpc_operands + *opindex; | |
604 | ||
605 | /* Operands that are marked FAKE are simply ignored. We | |
606 | already made sure that the extract function considered | |
607 | the instruction to be valid. */ | |
608 | if ((operand->flags & PPC_OPERAND_FAKE) != 0) | |
609 | continue; | |
610 | ||
ea192fa3 PB |
611 | /* If all of the optional operands have the value zero, |
612 | then don't print any of them. */ | |
65b650b4 AM |
613 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
614 | { | |
615 | if (skip_optional < 0) | |
616 | skip_optional = skip_optional_operands (opindex, insn, | |
617 | dialect); | |
618 | if (skip_optional) | |
619 | continue; | |
620 | } | |
252b5132 | 621 | |
ea192fa3 PB |
622 | value = operand_value_powerpc (operand, insn, dialect); |
623 | ||
252b5132 RH |
624 | if (need_comma) |
625 | { | |
626 | (*info->fprintf_func) (info->stream, ","); | |
627 | need_comma = 0; | |
628 | } | |
629 | ||
630 | /* Print the operand as directed by the flags. */ | |
fdd12ef3 AM |
631 | if ((operand->flags & PPC_OPERAND_GPR) != 0 |
632 | || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) | |
252b5132 RH |
633 | (*info->fprintf_func) (info->stream, "r%ld", value); |
634 | else if ((operand->flags & PPC_OPERAND_FPR) != 0) | |
635 | (*info->fprintf_func) (info->stream, "f%ld", value); | |
786e2c0f C |
636 | else if ((operand->flags & PPC_OPERAND_VR) != 0) |
637 | (*info->fprintf_func) (info->stream, "v%ld", value); | |
9b4e5766 PB |
638 | else if ((operand->flags & PPC_OPERAND_VSR) != 0) |
639 | (*info->fprintf_func) (info->stream, "vs%ld", value); | |
252b5132 RH |
640 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) |
641 | (*info->print_address_func) (memaddr + value, info); | |
642 | else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
643 | (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); | |
081ba1b3 AM |
644 | else if ((operand->flags & PPC_OPERAND_FSL) != 0) |
645 | (*info->fprintf_func) (info->stream, "fsl%ld", value); | |
646 | else if ((operand->flags & PPC_OPERAND_FCR) != 0) | |
647 | (*info->fprintf_func) (info->stream, "fcr%ld", value); | |
648 | else if ((operand->flags & PPC_OPERAND_UDI) != 0) | |
649 | (*info->fprintf_func) (info->stream, "%ld", value); | |
b9c361e0 JL |
650 | else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 |
651 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
652 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
653 | (*info->fprintf_func) (info->stream, "cr%ld", value); | |
654 | else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
655 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
656 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
252b5132 | 657 | { |
b9c361e0 JL |
658 | static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; |
659 | int cr; | |
660 | int cc; | |
661 | ||
662 | cr = value >> 2; | |
663 | if (cr != 0) | |
664 | (*info->fprintf_func) (info->stream, "4*cr%d+", cr); | |
665 | cc = value & 3; | |
666 | (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); | |
252b5132 | 667 | } |
70dc4e32 | 668 | else |
d908c8af | 669 | (*info->fprintf_func) (info->stream, "%d", (int) value); |
252b5132 RH |
670 | |
671 | if (need_paren) | |
672 | { | |
673 | (*info->fprintf_func) (info->stream, ")"); | |
674 | need_paren = 0; | |
675 | } | |
676 | ||
677 | if ((operand->flags & PPC_OPERAND_PARENS) == 0) | |
678 | need_comma = 1; | |
679 | else | |
680 | { | |
681 | (*info->fprintf_func) (info->stream, "("); | |
682 | need_paren = 1; | |
683 | } | |
684 | } | |
685 | ||
b9c361e0 JL |
686 | /* We have found and printed an instruction. |
687 | If it was a short VLE instruction we have more to do. */ | |
688 | if (insn_is_short) | |
689 | { | |
690 | memaddr += 2; | |
691 | return 2; | |
692 | } | |
693 | else | |
694 | /* Otherwise, return. */ | |
695 | return 4; | |
252b5132 RH |
696 | } |
697 | ||
698 | /* We could not find a match. */ | |
699 | (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); | |
700 | ||
701 | return 4; | |
702 | } | |
07dd56a9 NC |
703 | |
704 | void | |
823bbe9d | 705 | print_ppc_disassembler_options (FILE *stream) |
07dd56a9 | 706 | { |
69fe9ce5 AM |
707 | unsigned int i, col; |
708 | ||
709 | fprintf (stream, _("\n\ | |
07dd56a9 | 710 | The following PPC specific disassembler options are supported for use with\n\ |
69fe9ce5 AM |
711 | the -M switch:\n")); |
712 | ||
713 | for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) | |
714 | { | |
715 | col += fprintf (stream, " %s,", ppc_opts[i].opt); | |
716 | if (col > 66) | |
717 | { | |
718 | fprintf (stream, "\n"); | |
719 | col = 0; | |
720 | } | |
721 | } | |
722 | fprintf (stream, " 32, 64\n"); | |
07dd56a9 | 723 | } |