Commit | Line | Data |
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252b5132 | 1 | /* ppc-dis.c -- Disassemble PowerPC instructions |
081ba1b3 | 2 | Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, |
aea77599 | 3 | 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. |
252b5132 RH |
4 | Written by Ian Lance Taylor, Cygnus Support |
5 | ||
9b201bb5 NC |
6 | This file is part of the GNU opcodes library. |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | It is distributed in the hope that it will be useful, but WITHOUT | |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this file; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
21 | MA 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "sysdep.h" |
df7b86aa | 24 | #include <stdio.h> |
252b5132 | 25 | #include "dis-asm.h" |
b9c361e0 | 26 | #include "elf-bfd.h" |
94caa966 | 27 | #include "elf/ppc.h" |
69fe9ce5 | 28 | #include "opintl.h" |
252b5132 RH |
29 | #include "opcode/ppc.h" |
30 | ||
31 | /* This file provides several disassembler functions, all of which use | |
32 | the disassembler interface defined in dis-asm.h. Several functions | |
33 | are provided because this file handles disassembly for the PowerPC | |
34 | in both big and little endian mode and also for the POWER (RS/6000) | |
35 | chip. */ | |
fa452fa6 PB |
36 | static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, |
37 | ppc_cpu_t); | |
252b5132 | 38 | |
fa452fa6 PB |
39 | struct dis_private |
40 | { | |
41 | /* Stash the result of parsing disassembler_options here. */ | |
42 | ppc_cpu_t dialect; | |
b240011a | 43 | } private; |
fa452fa6 PB |
44 | |
45 | #define POWERPC_DIALECT(INFO) \ | |
46 | (((struct dis_private *) ((INFO)->private_data))->dialect) | |
418c1742 | 47 | |
69fe9ce5 AM |
48 | struct ppc_mopt { |
49 | const char *opt; | |
50 | ppc_cpu_t cpu; | |
51 | ppc_cpu_t sticky; | |
52 | }; | |
53 | ||
54 | struct ppc_mopt ppc_opts[] = { | |
bdc70b4a | 55 | { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403), |
69fe9ce5 | 56 | 0 }, |
bdc70b4a | 57 | { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405), |
69fe9ce5 | 58 | 0 }, |
bdc70b4a AM |
59 | { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
60 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 61 | 0 }, |
bdc70b4a AM |
62 | { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
63 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 64 | 0 }, |
bdc70b4a AM |
65 | { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440 |
66 | | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), | |
9fe54b1c | 67 | 0 }, |
bdc70b4a | 68 | { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601), |
69fe9ce5 | 69 | 0 }, |
bdc70b4a | 70 | { "603", (PPC_OPCODE_PPC), |
69fe9ce5 | 71 | 0 }, |
bdc70b4a | 72 | { "604", (PPC_OPCODE_PPC), |
69fe9ce5 | 73 | 0 }, |
bdc70b4a | 74 | { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64), |
69fe9ce5 | 75 | 0 }, |
bdc70b4a | 76 | { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 | 77 | 0 }, |
bdc70b4a | 78 | { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 | 79 | 0 }, |
bdc70b4a | 80 | { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 | 81 | 0 }, |
bdc70b4a | 82 | { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), |
69fe9ce5 AM |
83 | 0 }, |
84 | { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS) | |
85 | , 0 }, | |
bdc70b4a AM |
86 | { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 |
87 | | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 | |
88 | | PPC_OPCODE_A2), | |
cdc51b07 | 89 | 0 }, |
bdc70b4a | 90 | { "altivec", (PPC_OPCODE_PPC), |
c7a5aa9c | 91 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, |
69fe9ce5 AM |
92 | { "any", 0, |
93 | PPC_OPCODE_ANY }, | |
bdc70b4a | 94 | { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), |
69fe9ce5 | 95 | 0 }, |
bdc70b4a | 96 | { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), |
69fe9ce5 | 97 | 0 }, |
bdc70b4a AM |
98 | { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
99 | | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 100 | 0 }, |
bdc70b4a | 101 | { "com", (PPC_OPCODE_COMMON), |
69fe9ce5 | 102 | 0 }, |
bdc70b4a | 103 | { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300), |
69fe9ce5 AM |
104 | 0 }, |
105 | { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | |
106 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
107 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 108 | | PPC_OPCODE_E500), |
69fe9ce5 AM |
109 | 0 }, |
110 | { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
111 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
112 | | PPC_OPCODE_E500MC), | |
113 | 0 }, | |
0dc93057 AM |
114 | { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
115 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
63d0fa4e AM |
116 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 |
117 | | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), | |
0dc93057 | 118 | 0 }, |
aea77599 AM |
119 | { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
120 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
121 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | |
122 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
123 | | PPC_OPCODE_POWER7), | |
124 | 0 }, | |
125 | { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
126 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
127 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC | |
128 | | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 | |
129 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), | |
130 | 0 }, | |
69fe9ce5 AM |
131 | { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE |
132 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
133 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 134 | | PPC_OPCODE_E500), |
69fe9ce5 AM |
135 | 0 }, |
136 | { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), | |
137 | 0 }, | |
bdc70b4a | 138 | { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), |
69fe9ce5 | 139 | 0 }, |
bdc70b4a AM |
140 | { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
141 | | PPC_OPCODE_POWER5), | |
69fe9ce5 | 142 | 0 }, |
bdc70b4a AM |
143 | { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
144 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 145 | 0 }, |
bdc70b4a AM |
146 | { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
147 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
148 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 149 | 0 }, |
5817ffd1 PB |
150 | { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
151 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
152 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM | |
153 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), | |
154 | 0 }, | |
bdc70b4a | 155 | { "ppc", (PPC_OPCODE_PPC), |
69fe9ce5 | 156 | 0 }, |
bdc70b4a | 157 | { "ppc32", (PPC_OPCODE_PPC), |
69fe9ce5 | 158 | 0 }, |
bdc70b4a | 159 | { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64), |
69fe9ce5 | 160 | 0 }, |
bdc70b4a | 161 | { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE), |
69fe9ce5 AM |
162 | 0 }, |
163 | { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS), | |
164 | 0 }, | |
bdc70b4a | 165 | { "pwr", (PPC_OPCODE_POWER), |
69fe9ce5 | 166 | 0 }, |
bdc70b4a | 167 | { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), |
cdc51b07 | 168 | 0 }, |
bdc70b4a | 169 | { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), |
cdc51b07 | 170 | 0 }, |
bdc70b4a AM |
171 | { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
172 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 173 | 0 }, |
bdc70b4a AM |
174 | { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
175 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 176 | 0 }, |
bdc70b4a AM |
177 | { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
178 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
cdc51b07 | 179 | 0 }, |
bdc70b4a AM |
180 | { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
181 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
182 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 183 | 0 }, |
5817ffd1 PB |
184 | { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
185 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
186 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM | |
187 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), | |
188 | 0 }, | |
bdc70b4a | 189 | { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), |
69fe9ce5 AM |
190 | 0 }, |
191 | { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), | |
192 | PPC_OPCODE_SPE }, | |
bdc70b4a AM |
193 | { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR |
194 | | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), | |
ce3d2015 | 195 | 0 }, |
b9c361e0 JL |
196 | { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE), |
197 | PPC_OPCODE_VLE }, | |
bdc70b4a | 198 | { "vsx", (PPC_OPCODE_PPC), |
69fe9ce5 | 199 | PPC_OPCODE_VSX }, |
5817ffd1 PB |
200 | { "htm", (PPC_OPCODE_PPC), |
201 | PPC_OPCODE_HTM }, | |
69fe9ce5 AM |
202 | }; |
203 | ||
b9c361e0 JL |
204 | /* Switch between Booke and VLE dialects for interlinked dumps. */ |
205 | static ppc_cpu_t | |
206 | get_powerpc_dialect (struct disassemble_info *info) | |
207 | { | |
208 | ppc_cpu_t dialect = 0; | |
209 | ||
210 | dialect = POWERPC_DIALECT (info); | |
211 | ||
212 | /* Disassemble according to the section headers flags for VLE-mode. */ | |
213 | if (dialect & PPC_OPCODE_VLE | |
94caa966 AM |
214 | && info->section->owner != NULL |
215 | && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour | |
216 | && elf_object_id (info->section->owner) == PPC32_ELF_DATA | |
217 | && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) | |
b9c361e0 JL |
218 | return dialect; |
219 | else | |
220 | return dialect & ~ PPC_OPCODE_VLE; | |
221 | } | |
222 | ||
69fe9ce5 AM |
223 | /* Handle -m and -M options that set cpu type, and .machine arg. */ |
224 | ||
225 | ppc_cpu_t | |
776fc418 | 226 | ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg) |
69fe9ce5 | 227 | { |
69fe9ce5 AM |
228 | unsigned int i; |
229 | ||
230 | for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) | |
231 | if (strcmp (ppc_opts[i].opt, arg) == 0) | |
232 | { | |
233 | if (ppc_opts[i].sticky) | |
234 | { | |
776fc418 AM |
235 | *sticky |= ppc_opts[i].sticky; |
236 | if ((ppc_cpu & ~*sticky) != 0) | |
69fe9ce5 AM |
237 | break; |
238 | } | |
239 | ppc_cpu = ppc_opts[i].cpu; | |
240 | break; | |
241 | } | |
242 | if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0])) | |
243 | return 0; | |
244 | ||
776fc418 | 245 | ppc_cpu |= *sticky; |
69fe9ce5 AM |
246 | return ppc_cpu; |
247 | } | |
248 | ||
249 | /* Determine which set of machines to disassemble for. */ | |
418c1742 | 250 | |
b240011a | 251 | static void |
fa452fa6 | 252 | powerpc_init_dialect (struct disassemble_info *info) |
418c1742 | 253 | { |
69fe9ce5 | 254 | ppc_cpu_t dialect = 0; |
776fc418 | 255 | ppc_cpu_t sticky = 0; |
69fe9ce5 | 256 | char *arg; |
fa452fa6 PB |
257 | struct dis_private *priv = calloc (sizeof (*priv), 1); |
258 | ||
259 | if (priv == NULL) | |
b240011a | 260 | priv = &private; |
418c1742 | 261 | |
776fc418 AM |
262 | switch (info->mach) |
263 | { | |
264 | case bfd_mach_ppc_403: | |
265 | case bfd_mach_ppc_403gc: | |
266 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403); | |
267 | break; | |
268 | case bfd_mach_ppc_405: | |
269 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405); | |
270 | break; | |
271 | case bfd_mach_ppc_601: | |
272 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601); | |
273 | break; | |
274 | case bfd_mach_ppc_a35: | |
275 | case bfd_mach_ppc_rs64ii: | |
276 | case bfd_mach_ppc_rs64iii: | |
277 | dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64); | |
278 | break; | |
279 | case bfd_mach_ppc_e500: | |
280 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | |
281 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
282 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
283 | | PPC_OPCODE_E500); | |
284 | break; | |
285 | case bfd_mach_ppc_e500mc: | |
286 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
287 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
288 | | PPC_OPCODE_E500MC); | |
289 | break; | |
290 | case bfd_mach_ppc_e500mc64: | |
291 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
292 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
293 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 | |
294 | | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7); | |
295 | break; | |
296 | case bfd_mach_ppc_e5500: | |
297 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
298 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
299 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | |
300 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
301 | | PPC_OPCODE_POWER7); | |
302 | break; | |
303 | case bfd_mach_ppc_e6500: | |
304 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
305 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
306 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC | |
307 | | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 | |
308 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7); | |
309 | break; | |
310 | case bfd_mach_ppc_titan: | |
311 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR | |
312 | | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN); | |
313 | break; | |
314 | case bfd_mach_ppc_vle: | |
315 | dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE); | |
316 | break; | |
317 | default: | |
c0637f3a | 318 | dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY; |
776fc418 AM |
319 | } |
320 | ||
69fe9ce5 AM |
321 | arg = info->disassembler_options; |
322 | while (arg != NULL) | |
323 | { | |
324 | ppc_cpu_t new_cpu = 0; | |
325 | char *end = strchr (arg, ','); | |
9b4e5766 | 326 | |
69fe9ce5 AM |
327 | if (end != NULL) |
328 | *end = 0; | |
9b4e5766 | 329 | |
776fc418 | 330 | if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0) |
69fe9ce5 AM |
331 | dialect = new_cpu; |
332 | else if (strcmp (arg, "32") == 0) | |
7102e95e | 333 | dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; |
69fe9ce5 | 334 | else if (strcmp (arg, "64") == 0) |
bdc70b4a | 335 | dialect |= PPC_OPCODE_64; |
69fe9ce5 AM |
336 | else |
337 | fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); | |
9622b051 | 338 | |
69fe9ce5 AM |
339 | if (end != NULL) |
340 | *end++ = ','; | |
341 | arg = end; | |
342 | } | |
661bd698 | 343 | |
fa452fa6 PB |
344 | info->private_data = priv; |
345 | POWERPC_DIALECT(info) = dialect; | |
b240011a AM |
346 | } |
347 | ||
b9c361e0 JL |
348 | #define PPC_OPCD_SEGS 64 |
349 | static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; | |
350 | #define VLE_OPCD_SEGS 32 | |
351 | static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; | |
b240011a AM |
352 | |
353 | /* Calculate opcode table indices to speed up disassembly, | |
354 | and init dialect. */ | |
355 | ||
356 | void | |
357 | disassemble_init_powerpc (struct disassemble_info *info) | |
358 | { | |
359 | int i; | |
d6688282 | 360 | unsigned short last; |
fa452fa6 | 361 | |
b240011a AM |
362 | i = powerpc_num_opcodes; |
363 | while (--i >= 0) | |
364 | { | |
365 | unsigned op = PPC_OP (powerpc_opcodes[i].opcode); | |
b240011a | 366 | |
d6688282 AM |
367 | powerpc_opcd_indices[op] = i; |
368 | } | |
369 | ||
370 | last = powerpc_num_opcodes; | |
b9c361e0 | 371 | for (i = PPC_OPCD_SEGS; i > 0; --i) |
d6688282 AM |
372 | { |
373 | if (powerpc_opcd_indices[i] == 0) | |
374 | powerpc_opcd_indices[i] = last; | |
375 | last = powerpc_opcd_indices[i]; | |
b240011a AM |
376 | } |
377 | ||
b9c361e0 JL |
378 | i = vle_num_opcodes; |
379 | while (--i >= 0) | |
380 | { | |
381 | unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); | |
382 | unsigned seg = VLE_OP_TO_SEG (op); | |
383 | ||
384 | vle_opcd_indices[seg] = i; | |
385 | } | |
386 | ||
387 | last = vle_num_opcodes; | |
388 | for (i = VLE_OPCD_SEGS; i > 0; --i) | |
389 | { | |
390 | if (vle_opcd_indices[i] == 0) | |
391 | vle_opcd_indices[i] = last; | |
392 | last = vle_opcd_indices[i]; | |
393 | } | |
394 | ||
b240011a AM |
395 | if (info->arch == bfd_arch_powerpc) |
396 | powerpc_init_dialect (info); | |
418c1742 MG |
397 | } |
398 | ||
399 | /* Print a big endian PowerPC instruction. */ | |
252b5132 RH |
400 | |
401 | int | |
823bbe9d | 402 | print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 403 | { |
b9c361e0 | 404 | return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); |
252b5132 RH |
405 | } |
406 | ||
418c1742 | 407 | /* Print a little endian PowerPC instruction. */ |
252b5132 RH |
408 | |
409 | int | |
823bbe9d | 410 | print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 411 | { |
b9c361e0 | 412 | return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); |
252b5132 RH |
413 | } |
414 | ||
415 | /* Print a POWER (RS/6000) instruction. */ | |
416 | ||
417 | int | |
823bbe9d | 418 | print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 RH |
419 | { |
420 | return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); | |
421 | } | |
422 | ||
ea192fa3 PB |
423 | /* Extract the operand value from the PowerPC or POWER instruction. */ |
424 | ||
425 | static long | |
426 | operand_value_powerpc (const struct powerpc_operand *operand, | |
fa452fa6 | 427 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
428 | { |
429 | long value; | |
430 | int invalid; | |
431 | /* Extract the value from the instruction. */ | |
432 | if (operand->extract) | |
433 | value = (*operand->extract) (insn, dialect, &invalid); | |
434 | else | |
435 | { | |
b9c361e0 JL |
436 | if (operand->shift >= 0) |
437 | value = (insn >> operand->shift) & operand->bitm; | |
438 | else | |
439 | value = (insn << -operand->shift) & operand->bitm; | |
ea192fa3 PB |
440 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
441 | { | |
442 | /* BITM is always some number of zeros followed by some | |
b9c361e0 | 443 | number of ones, followed by some number of zeros. */ |
ea192fa3 PB |
444 | unsigned long top = operand->bitm; |
445 | /* top & -top gives the rightmost 1 bit, so this | |
446 | fills in any trailing zeros. */ | |
447 | top |= (top & -top) - 1; | |
448 | top &= ~(top >> 1); | |
449 | value = (value ^ top) - top; | |
450 | } | |
451 | } | |
452 | ||
453 | return value; | |
454 | } | |
455 | ||
456 | /* Determine whether the optional operand(s) should be printed. */ | |
457 | ||
458 | static int | |
459 | skip_optional_operands (const unsigned char *opindex, | |
fa452fa6 | 460 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
461 | { |
462 | const struct powerpc_operand *operand; | |
463 | ||
464 | for (; *opindex != 0; opindex++) | |
465 | { | |
466 | operand = &powerpc_operands[*opindex]; | |
467 | if ((operand->flags & PPC_OPERAND_NEXT) != 0 | |
468 | || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 | |
469 | && operand_value_powerpc (operand, insn, dialect) != 0)) | |
470 | return 0; | |
471 | } | |
472 | ||
473 | return 1; | |
474 | } | |
475 | ||
d6688282 AM |
476 | /* Find a match for INSN in the opcode table, given machine DIALECT. |
477 | A DIALECT of -1 is special, matching all machine opcode variations. */ | |
b9c361e0 | 478 | |
d6688282 AM |
479 | static const struct powerpc_opcode * |
480 | lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) | |
481 | { | |
482 | const struct powerpc_opcode *opcode; | |
483 | const struct powerpc_opcode *opcode_end; | |
484 | unsigned long op; | |
485 | ||
486 | /* Get the major opcode of the instruction. */ | |
487 | op = PPC_OP (insn); | |
488 | ||
489 | /* Find the first match in the opcode table for this major opcode. */ | |
490 | opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; | |
491 | for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; | |
492 | opcode < opcode_end; | |
493 | ++opcode) | |
494 | { | |
495 | const unsigned char *opindex; | |
496 | const struct powerpc_operand *operand; | |
497 | int invalid; | |
498 | ||
499 | if ((insn & opcode->mask) != opcode->opcode | |
500 | || (dialect != (ppc_cpu_t) -1 | |
501 | && ((opcode->flags & dialect) == 0 | |
502 | || (opcode->deprecated & dialect) != 0))) | |
503 | continue; | |
504 | ||
505 | /* Check validity of operands. */ | |
506 | invalid = 0; | |
507 | for (opindex = opcode->operands; *opindex != 0; opindex++) | |
508 | { | |
509 | operand = powerpc_operands + *opindex; | |
510 | if (operand->extract) | |
511 | (*operand->extract) (insn, dialect, &invalid); | |
512 | } | |
513 | if (invalid) | |
514 | continue; | |
515 | ||
516 | return opcode; | |
517 | } | |
518 | ||
519 | return NULL; | |
520 | } | |
521 | ||
b9c361e0 JL |
522 | /* Find a match for INSN in the VLE opcode table. */ |
523 | ||
524 | static const struct powerpc_opcode * | |
525 | lookup_vle (unsigned long insn) | |
526 | { | |
527 | const struct powerpc_opcode *opcode; | |
528 | const struct powerpc_opcode *opcode_end; | |
529 | unsigned op, seg; | |
530 | ||
531 | op = PPC_OP (insn); | |
532 | if (op >= 0x20 && op <= 0x37) | |
533 | { | |
534 | /* This insn has a 4-bit opcode. */ | |
535 | op &= 0x3c; | |
536 | } | |
537 | seg = VLE_OP_TO_SEG (op); | |
538 | ||
539 | /* Find the first match in the opcode table for this major opcode. */ | |
540 | opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; | |
541 | for (opcode = vle_opcodes + vle_opcd_indices[seg]; | |
542 | opcode < opcode_end; | |
543 | ++opcode) | |
544 | { | |
545 | unsigned long table_opcd = opcode->opcode; | |
546 | unsigned long table_mask = opcode->mask; | |
547 | bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); | |
548 | unsigned long insn2; | |
549 | const unsigned char *opindex; | |
550 | const struct powerpc_operand *operand; | |
551 | int invalid; | |
552 | ||
553 | insn2 = insn; | |
554 | if (table_op_is_short) | |
555 | insn2 >>= 16; | |
556 | if ((insn2 & table_mask) != table_opcd) | |
557 | continue; | |
558 | ||
559 | /* Check validity of operands. */ | |
560 | invalid = 0; | |
561 | for (opindex = opcode->operands; *opindex != 0; ++opindex) | |
562 | { | |
563 | operand = powerpc_operands + *opindex; | |
564 | if (operand->extract) | |
565 | (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); | |
566 | } | |
567 | if (invalid) | |
568 | continue; | |
569 | ||
570 | return opcode; | |
571 | } | |
572 | ||
573 | return NULL; | |
574 | } | |
575 | ||
252b5132 RH |
576 | /* Print a PowerPC or POWER instruction. */ |
577 | ||
578 | static int | |
823bbe9d AM |
579 | print_insn_powerpc (bfd_vma memaddr, |
580 | struct disassemble_info *info, | |
581 | int bigendian, | |
fa452fa6 | 582 | ppc_cpu_t dialect) |
252b5132 RH |
583 | { |
584 | bfd_byte buffer[4]; | |
585 | int status; | |
586 | unsigned long insn; | |
587 | const struct powerpc_opcode *opcode; | |
b9c361e0 | 588 | bfd_boolean insn_is_short; |
252b5132 RH |
589 | |
590 | status = (*info->read_memory_func) (memaddr, buffer, 4, info); | |
591 | if (status != 0) | |
592 | { | |
b9c361e0 JL |
593 | /* The final instruction may be a 2-byte VLE insn. */ |
594 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
595 | { | |
596 | /* Clear buffer so unused bytes will not have garbage in them. */ | |
597 | buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; | |
598 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
599 | if (status != 0) | |
600 | { | |
601 | (*info->memory_error_func) (status, memaddr, info); | |
602 | return -1; | |
603 | } | |
604 | } | |
605 | else | |
606 | { | |
607 | (*info->memory_error_func) (status, memaddr, info); | |
608 | return -1; | |
609 | } | |
252b5132 RH |
610 | } |
611 | ||
612 | if (bigendian) | |
613 | insn = bfd_getb32 (buffer); | |
614 | else | |
615 | insn = bfd_getl32 (buffer); | |
616 | ||
b9c361e0 JL |
617 | /* Get the major opcode of the insn. */ |
618 | opcode = NULL; | |
619 | insn_is_short = FALSE; | |
620 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
621 | { | |
622 | opcode = lookup_vle (insn); | |
623 | if (opcode != NULL) | |
624 | insn_is_short = PPC_OP_SE_VLE(opcode->mask); | |
625 | } | |
626 | if (opcode == NULL) | |
627 | opcode = lookup_powerpc (insn, dialect); | |
d6688282 AM |
628 | if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) |
629 | opcode = lookup_powerpc (insn, (ppc_cpu_t) -1); | |
252b5132 | 630 | |
d6688282 | 631 | if (opcode != NULL) |
252b5132 | 632 | { |
252b5132 RH |
633 | const unsigned char *opindex; |
634 | const struct powerpc_operand *operand; | |
252b5132 RH |
635 | int need_comma; |
636 | int need_paren; | |
ea192fa3 | 637 | int skip_optional; |
252b5132 | 638 | |
252b5132 | 639 | if (opcode->operands[0] != 0) |
fdd12ef3 AM |
640 | (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); |
641 | else | |
642 | (*info->fprintf_func) (info->stream, "%s", opcode->name); | |
252b5132 | 643 | |
b9c361e0 JL |
644 | if (insn_is_short) |
645 | /* The operands will be fetched out of the 16-bit instruction. */ | |
646 | insn >>= 16; | |
647 | ||
252b5132 RH |
648 | /* Now extract and print the operands. */ |
649 | need_comma = 0; | |
650 | need_paren = 0; | |
ea192fa3 | 651 | skip_optional = -1; |
252b5132 RH |
652 | for (opindex = opcode->operands; *opindex != 0; opindex++) |
653 | { | |
654 | long value; | |
655 | ||
656 | operand = powerpc_operands + *opindex; | |
657 | ||
658 | /* Operands that are marked FAKE are simply ignored. We | |
659 | already made sure that the extract function considered | |
660 | the instruction to be valid. */ | |
661 | if ((operand->flags & PPC_OPERAND_FAKE) != 0) | |
662 | continue; | |
663 | ||
ea192fa3 PB |
664 | /* If all of the optional operands have the value zero, |
665 | then don't print any of them. */ | |
65b650b4 AM |
666 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
667 | { | |
668 | if (skip_optional < 0) | |
669 | skip_optional = skip_optional_operands (opindex, insn, | |
670 | dialect); | |
671 | if (skip_optional) | |
672 | continue; | |
673 | } | |
252b5132 | 674 | |
ea192fa3 PB |
675 | value = operand_value_powerpc (operand, insn, dialect); |
676 | ||
252b5132 RH |
677 | if (need_comma) |
678 | { | |
679 | (*info->fprintf_func) (info->stream, ","); | |
680 | need_comma = 0; | |
681 | } | |
682 | ||
683 | /* Print the operand as directed by the flags. */ | |
fdd12ef3 AM |
684 | if ((operand->flags & PPC_OPERAND_GPR) != 0 |
685 | || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) | |
252b5132 RH |
686 | (*info->fprintf_func) (info->stream, "r%ld", value); |
687 | else if ((operand->flags & PPC_OPERAND_FPR) != 0) | |
688 | (*info->fprintf_func) (info->stream, "f%ld", value); | |
786e2c0f C |
689 | else if ((operand->flags & PPC_OPERAND_VR) != 0) |
690 | (*info->fprintf_func) (info->stream, "v%ld", value); | |
9b4e5766 PB |
691 | else if ((operand->flags & PPC_OPERAND_VSR) != 0) |
692 | (*info->fprintf_func) (info->stream, "vs%ld", value); | |
252b5132 RH |
693 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) |
694 | (*info->print_address_func) (memaddr + value, info); | |
695 | else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
696 | (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); | |
081ba1b3 AM |
697 | else if ((operand->flags & PPC_OPERAND_FSL) != 0) |
698 | (*info->fprintf_func) (info->stream, "fsl%ld", value); | |
699 | else if ((operand->flags & PPC_OPERAND_FCR) != 0) | |
700 | (*info->fprintf_func) (info->stream, "fcr%ld", value); | |
701 | else if ((operand->flags & PPC_OPERAND_UDI) != 0) | |
702 | (*info->fprintf_func) (info->stream, "%ld", value); | |
b9c361e0 JL |
703 | else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 |
704 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
705 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
706 | (*info->fprintf_func) (info->stream, "cr%ld", value); | |
707 | else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
708 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
709 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
252b5132 | 710 | { |
b9c361e0 JL |
711 | static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; |
712 | int cr; | |
713 | int cc; | |
714 | ||
715 | cr = value >> 2; | |
716 | if (cr != 0) | |
717 | (*info->fprintf_func) (info->stream, "4*cr%d+", cr); | |
718 | cc = value & 3; | |
719 | (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); | |
252b5132 | 720 | } |
70dc4e32 | 721 | else |
d908c8af | 722 | (*info->fprintf_func) (info->stream, "%d", (int) value); |
252b5132 RH |
723 | |
724 | if (need_paren) | |
725 | { | |
726 | (*info->fprintf_func) (info->stream, ")"); | |
727 | need_paren = 0; | |
728 | } | |
729 | ||
730 | if ((operand->flags & PPC_OPERAND_PARENS) == 0) | |
731 | need_comma = 1; | |
732 | else | |
733 | { | |
734 | (*info->fprintf_func) (info->stream, "("); | |
735 | need_paren = 1; | |
736 | } | |
737 | } | |
738 | ||
b9c361e0 JL |
739 | /* We have found and printed an instruction. |
740 | If it was a short VLE instruction we have more to do. */ | |
741 | if (insn_is_short) | |
742 | { | |
743 | memaddr += 2; | |
744 | return 2; | |
745 | } | |
746 | else | |
747 | /* Otherwise, return. */ | |
748 | return 4; | |
252b5132 RH |
749 | } |
750 | ||
751 | /* We could not find a match. */ | |
752 | (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); | |
753 | ||
754 | return 4; | |
755 | } | |
07dd56a9 NC |
756 | |
757 | void | |
823bbe9d | 758 | print_ppc_disassembler_options (FILE *stream) |
07dd56a9 | 759 | { |
69fe9ce5 AM |
760 | unsigned int i, col; |
761 | ||
762 | fprintf (stream, _("\n\ | |
07dd56a9 | 763 | The following PPC specific disassembler options are supported for use with\n\ |
69fe9ce5 AM |
764 | the -M switch:\n")); |
765 | ||
766 | for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) | |
767 | { | |
768 | col += fprintf (stream, " %s,", ppc_opts[i].opt); | |
769 | if (col > 66) | |
770 | { | |
771 | fprintf (stream, "\n"); | |
772 | col = 0; | |
773 | } | |
774 | } | |
775 | fprintf (stream, " 32, 64\n"); | |
07dd56a9 | 776 | } |