[deliverable/binutils-gdb.git] / opcodes / ppc-dis.c

/* ppc-dis.c -- Disassemble PowerPC instructions
   Copyright 1994, 1995, 2000, 2001, 2002 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <stdio.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/ppc.h"

/* This file provides several disassembler functions, all of which use
   the disassembler interface defined in dis-asm.h.  Several functions
   are provided because this file handles disassembly for the PowerPC
   in both big and little endian mode and also for the POWER (RS/6000)
   chip.  */

static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
				       int bigendian, int dialect));

static int powerpc_dialect PARAMS ((struct disassemble_info *));

/* Determine which set of machines to disassemble for.  PPC403/601 or
   BookE.  For convenience, also disassemble instructions supported
   by the AltiVec vector unit.  */

int
powerpc_dialect(info)
     struct disassemble_info *info;
{
  int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;

  if (BFD_DEFAULT_TARGET_SIZE == 64)
    dialect |= PPC_OPCODE_64;

  if (info->disassembler_options
      && (strcmp (info->disassembler_options, "booke") == 0
	  || strcmp (info->disassembler_options, "booke32") == 0
	  || strcmp (info->disassembler_options, "booke64") == 0))
    dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
  else
    if ((info->mach == bfd_mach_ppc_e500)
	|| (info->disassembler_options
	&& (   strcmp (info->disassembler_options, "e500") == 0
	    || strcmp (info->disassembler_options, "e500x2") == 0)))
      {
	dialect |= PPC_OPCODE_BOOKE
	  | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
	  | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
	  | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
	  | PPC_OPCODE_RFMCI;
	/* efs* and AltiVec conflict.  */
	dialect &= ~PPC_OPCODE_ALTIVEC;
      }
  else
    if (info->disassembler_options
	&& (strcmp (info->disassembler_options, "efs") == 0))
      {
	dialect |= PPC_OPCODE_EFS;
	/* efs* and AltiVec conflict.  */
	dialect &= ~PPC_OPCODE_ALTIVEC;
      }
  else
    dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
		| PPC_OPCODE_COMMON);

  if (info->disassembler_options
      && strcmp (info->disassembler_options, "power4") == 0)
    dialect |= PPC_OPCODE_POWER4;

  if (info->disassembler_options)
    {
      if (strstr (info->disassembler_options, "32") != NULL)
	dialect &= ~PPC_OPCODE_64;
      else if (strstr (info->disassembler_options, "64") != NULL)
	dialect |= PPC_OPCODE_64;
    }

  return dialect;
}

/* Print a big endian PowerPC instruction.  */

int
print_insn_big_powerpc (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info));
}

/* Print a little endian PowerPC instruction.  */

int
print_insn_little_powerpc (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info));
}

/* Print a POWER (RS/6000) instruction.  */

int
print_insn_rs6000 (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
}

/* Print a PowerPC or POWER instruction.  */

static int
print_insn_powerpc (memaddr, info, bigendian, dialect)
     bfd_vma memaddr;
     struct disassemble_info *info;
     int bigendian;
     int dialect;
{
  bfd_byte buffer[4];
  int status;
  unsigned long insn;
  const struct powerpc_opcode *opcode;
  const struct powerpc_opcode *opcode_end;
  unsigned long op;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  if (bigendian)
    insn = bfd_getb32 (buffer);
  else
    insn = bfd_getl32 (buffer);

  /* Get the major opcode of the instruction.  */
  op = PPC_OP (insn);

  /* Find the first match in the opcode table.  We could speed this up
     a bit by doing a binary search on the major opcode.  */
  opcode_end = powerpc_opcodes + powerpc_num_opcodes;
  for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
    {
      unsigned long table_op;
      const unsigned char *opindex;
      const struct powerpc_operand *operand;
      int invalid;
      int need_comma;
      int need_paren;

      table_op = PPC_OP (opcode->opcode);
      if (op < table_op)
	break;
      if (op > table_op)
	continue;

      if ((insn & opcode->mask) != opcode->opcode
	  || (opcode->flags & dialect) == 0)
	continue;

      if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC))
	continue;

      /* Make two passes over the operands.  First see if any of them
	 have extraction functions, and, if they do, make sure the
	 instruction is valid.  */
      invalid = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  operand = powerpc_operands + *opindex;
	  if (operand->extract)
	    (*operand->extract) (insn, dialect, &invalid);
	}
      if (invalid)
	continue;

      /* The instruction is valid.  */
      (*info->fprintf_func) (info->stream, "%s", opcode->name);
      if (opcode->operands[0] != 0)
	(*info->fprintf_func) (info->stream, "\t");

      /* Now extract and print the operands.  */
      need_comma = 0;
      need_paren = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  long value;

	  operand = powerpc_operands + *opindex;

	  /* Operands that are marked FAKE are simply ignored.  We
	     already made sure that the extract function considered
	     the instruction to be valid.  */
	  if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	    continue;

	  /* Extract the value from the instruction.  */
	  if (operand->extract)
	    value = (*operand->extract) (insn, dialect, (int *) NULL);
	  else
	    {
	      value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
	      if ((operand->flags & PPC_OPERAND_SIGNED) != 0
		  && (value & (1 << (operand->bits - 1))) != 0)
		value -= 1 << operand->bits;
	    }

	  /* If the operand is optional, and the value is zero, don't
	     print anything.  */
	  if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	      && (operand->flags & PPC_OPERAND_NEXT) == 0
	      && value == 0)
	    continue;

	  if (need_comma)
	    {
	      (*info->fprintf_func) (info->stream, ",");
	      need_comma = 0;
	    }

	  /* Print the operand as directed by the flags.  */
	  if ((operand->flags & PPC_OPERAND_GPR) != 0)
	    (*info->fprintf_func) (info->stream, "r%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	    (*info->fprintf_func) (info->stream, "f%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VR) != 0)
	    (*info->fprintf_func) (info->stream, "v%ld", value);
	  else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	    (*info->print_address_func) (memaddr + value, info);
	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	  else if ((operand->flags & PPC_OPERAND_CR) == 0
		   || (dialect & PPC_OPCODE_PPC) == 0)
	    (*info->fprintf_func) (info->stream, "%ld", value);
	  else
	    {
	      if (operand->bits == 3)
		(*info->fprintf_func) (info->stream, "cr%d", value);
	      else
		{
		  static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
		  int cr;
		  int cc;

		  cr = value >> 2;
		  if (cr != 0)
		    (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
		  cc = value & 3;
		  (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
		}
	    }

	  if (need_paren)
	    {
	      (*info->fprintf_func) (info->stream, ")");
	      need_paren = 0;
	    }

	  if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	    need_comma = 1;
	  else
	    {
	      (*info->fprintf_func) (info->stream, "(");
	      need_paren = 1;
	    }
	}

      /* We have found and printed an instruction; return.  */
      return 4;
    }

  /* We could not find a match.  */
  (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);

  return 4;
}

void
print_ppc_disassembler_options (FILE * stream)
{
  fprintf (stream, "\n\
The following PPC specific disassembler options are supported for use with\n\
the -M switch:\n");

  fprintf (stream, "  booke|booke32|booke64    Disassemble the BookE instructions\n");
  fprintf (stream, "  e500|e500x2              Disassemble the e500 instructions\n");
  fprintf (stream, "  efs                      Disassemble the EFS instructions\n");
  fprintf (stream, "  power4                   Disassemble the Power4 instructions\n");
  fprintf (stream, "  32                       Do not disassemble 64-bit instructions\n");
  fprintf (stream, "  64                       Allow disassembly of 64-bit instructions\n");
}
Commit	Line	Data
252b5132	1	/* ppc-dis.c -- Disassemble PowerPC instructions
94efba12	2	Copyright 1994, 1995, 2000, 2001, 2002 Free Software Foundation, Inc.
252b5132 RH	3	Written by Ian Lance Taylor, Cygnus Support
	4
	5	This file is part of GDB, GAS, and the GNU binutils.
	6
	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version
	10	2, or (at your option) any later version.
	11
	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING. If not, write to the Free
	19	Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#include <stdio.h>
252b5132 RH	22	#include "sysdep.h"
	23	#include "dis-asm.h"
	24	#include "opcode/ppc.h"
	25
	26	/* This file provides several disassembler functions, all of which use
	27	the disassembler interface defined in dis-asm.h. Several functions
	28	are provided because this file handles disassembly for the PowerPC
	29	in both big and little endian mode and also for the POWER (RS/6000)
	30	chip. */
	31
	32	static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
	33	int bigendian, int dialect));
	34
418c1742 MG	35	static int powerpc_dialect PARAMS ((struct disassemble_info *));
	36
	37	/* Determine which set of machines to disassemble for. PPC403/601 or
9a0ccb24 MG	38	BookE. For convenience, also disassemble instructions supported
9a0ccb24 MG	39	by the AltiVec vector unit. */
418c1742 MG	40
	41	int
	42	powerpc_dialect(info)
	43	struct disassemble_info *info;
	44	{
	45	int dialect = PPC_OPCODE_PPC \| PPC_OPCODE_ALTIVEC;
	46
802a735e AM	47	if (BFD_DEFAULT_TARGET_SIZE == 64)
	48	dialect \|= PPC_OPCODE_64;
	49
	50	if (info->disassembler_options
	51	&& (strcmp (info->disassembler_options, "booke") == 0
	52	\|\| strcmp (info->disassembler_options, "booke32") == 0
	53	\|\| strcmp (info->disassembler_options, "booke64") == 0))
418c1742	54	dialect \|= PPC_OPCODE_BOOKE \| PPC_OPCODE_BOOKE64;
8b4fa155	55	else
23976049	56	if ((info->mach == bfd_mach_ppc_e500)
8b4fa155	57	\|\| (info->disassembler_options
23976049 EZ	58	&& ( strcmp (info->disassembler_options, "e500") == 0
	59	\|\| strcmp (info->disassembler_options, "e500x2") == 0)))
	60	{
8b4fa155	61	dialect \|= PPC_OPCODE_BOOKE
23976049 EZ	62	\| PPC_OPCODE_SPE \| PPC_OPCODE_ISEL
	63	\| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
	64	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK
	65	\| PPC_OPCODE_RFMCI;
	66	/* efs* and AltiVec conflict. */
	67	dialect &= ~PPC_OPCODE_ALTIVEC;
	68	}
8b4fa155	69	else
23976049 EZ	70	if (info->disassembler_options
	71	&& (strcmp (info->disassembler_options, "efs") == 0))
	72	{
	73	dialect \|= PPC_OPCODE_EFS;
	74	/* efs* and AltiVec conflict. */
	75	dialect &= ~PPC_OPCODE_ALTIVEC;
	76	}
	77	else
9ec878e3 AM	78	dialect \|= (PPC_OPCODE_403 \| PPC_OPCODE_601 \| PPC_OPCODE_CLASSIC
9ec878e3 AM	79	\| PPC_OPCODE_COMMON);
802a735e	80
94efba12 AM	81	if (info->disassembler_options
	82	&& strcmp (info->disassembler_options, "power4") == 0)
	83	dialect \|= PPC_OPCODE_POWER4;
	84
802a735e AM	85	if (info->disassembler_options)
	86	{
	87	if (strstr (info->disassembler_options, "32") != NULL)
	88	dialect &= ~PPC_OPCODE_64;
	89	else if (strstr (info->disassembler_options, "64") != NULL)
	90	dialect \|= PPC_OPCODE_64;
	91	}
	92
418c1742 MG	93	return dialect;
	94	}
	95
	96	/* Print a big endian PowerPC instruction. */
252b5132 RH	97
	98	int
	99	print_insn_big_powerpc (memaddr, info)
	100	bfd_vma memaddr;
	101	struct disassemble_info *info;
	102	{
418c1742	103	return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info));
252b5132 RH	104	}
252b5132 RH	105
418c1742	106	/* Print a little endian PowerPC instruction. */
252b5132 RH	107
	108	int
	109	print_insn_little_powerpc (memaddr, info)
	110	bfd_vma memaddr;
	111	struct disassemble_info *info;
	112	{
418c1742	113	return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info));
252b5132 RH	114	}
	115
	116	/* Print a POWER (RS/6000) instruction. */
	117
	118	int
	119	print_insn_rs6000 (memaddr, info)
	120	bfd_vma memaddr;
	121	struct disassemble_info *info;
	122	{
	123	return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
	124	}
	125
	126	/* Print a PowerPC or POWER instruction. */
	127
	128	static int
	129	print_insn_powerpc (memaddr, info, bigendian, dialect)
	130	bfd_vma memaddr;
	131	struct disassemble_info *info;
	132	int bigendian;
	133	int dialect;
	134	{
	135	bfd_byte buffer[4];
	136	int status;
	137	unsigned long insn;
	138	const struct powerpc_opcode *opcode;
	139	const struct powerpc_opcode *opcode_end;
	140	unsigned long op;
	141
	142	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	143	if (status != 0)
	144	{
	145	(*info->memory_error_func) (status, memaddr, info);
	146	return -1;
	147	}
	148
	149	if (bigendian)
	150	insn = bfd_getb32 (buffer);
	151	else
	152	insn = bfd_getl32 (buffer);
	153
	154	/* Get the major opcode of the instruction. */
	155	op = PPC_OP (insn);
	156
	157	/* Find the first match in the opcode table. We could speed this up
	158	a bit by doing a binary search on the major opcode. */
	159	opcode_end = powerpc_opcodes + powerpc_num_opcodes;
	160	for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
	161	{
	162	unsigned long table_op;
	163	const unsigned char *opindex;
	164	const struct powerpc_operand *operand;
	165	int invalid;
	166	int need_comma;
	167	int need_paren;
	168
	169	table_op = PPC_OP (opcode->opcode);
	170	if (op < table_op)
	171	break;
	172	if (op > table_op)
	173	continue;
	174
	175	if ((insn & opcode->mask) != opcode->opcode
	176	\|\| (opcode->flags & dialect) == 0)
	177	continue;
178
23976049	179	if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC))
8b4fa155	180	continue;
23976049	181
252b5132 RH	182	/* Make two passes over the operands. First see if any of them
	183	have extraction functions, and, if they do, make sure the
	184	instruction is valid. */
	185	invalid = 0;
	186	for (opindex = opcode->operands; *opindex != 0; opindex++)
	187	{
	188	operand = powerpc_operands + *opindex;
	189	if (operand->extract)
802a735e	190	(*operand->extract) (insn, dialect, &invalid);
252b5132 RH	191	}
	192	if (invalid)
	193	continue;
	194
	195	/* The instruction is valid. */
	196	(*info->fprintf_func) (info->stream, "%s", opcode->name);
	197	if (opcode->operands[0] != 0)
	198	(*info->fprintf_func) (info->stream, "\t");
	199
	200	/* Now extract and print the operands. */
	201	need_comma = 0;
	202	need_paren = 0;
	203	for (opindex = opcode->operands; *opindex != 0; opindex++)
	204	{
	205	long value;
	206
	207	operand = powerpc_operands + *opindex;
	208
	209	/* Operands that are marked FAKE are simply ignored. We
	210	already made sure that the extract function considered
	211	the instruction to be valid. */
	212	if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	213	continue;
	214
	215	/* Extract the value from the instruction. */
	216	if (operand->extract)
802a735e	217	value = (operand->extract) (insn, dialect, (int ) NULL);
252b5132 RH	218	else
	219	{
	220	value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
	221	if ((operand->flags & PPC_OPERAND_SIGNED) != 0
	222	&& (value & (1 << (operand->bits - 1))) != 0)
	223	value -= 1 << operand->bits;
	224	}
	225
	226	/* If the operand is optional, and the value is zero, don't
	227	print anything. */
	228	if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	229	&& (operand->flags & PPC_OPERAND_NEXT) == 0
	230	&& value == 0)
	231	continue;
	232
	233	if (need_comma)
	234	{
	235	(*info->fprintf_func) (info->stream, ",");
	236	need_comma = 0;
	237	}
	238
	239	/* Print the operand as directed by the flags. */
	240	if ((operand->flags & PPC_OPERAND_GPR) != 0)
	241	(*info->fprintf_func) (info->stream, "r%ld", value);
	242	else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	243	(*info->fprintf_func) (info->stream, "f%ld", value);
786e2c0f C	244	else if ((operand->flags & PPC_OPERAND_VR) != 0)
786e2c0f C	245	(*info->fprintf_func) (info->stream, "v%ld", value);
252b5132 RH	246	else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	247	(*info->print_address_func) (memaddr + value, info);
	248	else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	249	(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	250	else if ((operand->flags & PPC_OPERAND_CR) == 0
	251	\|\| (dialect & PPC_OPCODE_PPC) == 0)
	252	(*info->fprintf_func) (info->stream, "%ld", value);
	253	else
	254	{
	255	if (operand->bits == 3)
	256	(*info->fprintf_func) (info->stream, "cr%d", value);
	257	else
	258	{
	259	static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
	260	int cr;
	261	int cc;
	262
	263	cr = value >> 2;
	264	if (cr != 0)
8b4fa155	265	(info->fprintf_func) (info->stream, "4cr%d+", cr);
252b5132	266	cc = value & 3;
8b4fa155	267	(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
252b5132 RH	268	}
	269	}
	270
	271	if (need_paren)
	272	{
	273	(*info->fprintf_func) (info->stream, ")");
	274	need_paren = 0;
	275	}
	276
	277	if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	278	need_comma = 1;
	279	else
	280	{
	281	(*info->fprintf_func) (info->stream, "(");
	282	need_paren = 1;
	283	}
	284	}
	285
	286	/* We have found and printed an instruction; return. */
	287	return 4;
	288	}
	289
	290	/* We could not find a match. */
	291	(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
	292
	293	return 4;
	294	}
07dd56a9 NC	295
	296	void
	297	print_ppc_disassembler_options (FILE * stream)
	298	{
	299	fprintf (stream, "\n\
	300	The following PPC specific disassembler options are supported for use with\n\
	301	the -M switch:\n");
8b4fa155	302
07dd56a9 NC	303	fprintf (stream, " booke\|booke32\|booke64 Disassemble the BookE instructions\n");
	304	fprintf (stream, " e500\|e500x2 Disassemble the e500 instructions\n");
	305	fprintf (stream, " efs Disassemble the EFS instructions\n");
	306	fprintf (stream, " power4 Disassemble the Power4 instructions\n");
	307	fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
	308	fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
	309	}