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252b5132 | 1 | /* ppc-dis.c -- Disassemble PowerPC instructions |
6f2750fe | 2 | Copyright (C) 1994-2016 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
9b201bb5 NC |
5 | This file is part of the GNU opcodes library. |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING. If not, write to the | |
19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "sysdep.h" |
df7b86aa | 23 | #include <stdio.h> |
252b5132 | 24 | #include "dis-asm.h" |
b9c361e0 | 25 | #include "elf-bfd.h" |
94caa966 | 26 | #include "elf/ppc.h" |
69fe9ce5 | 27 | #include "opintl.h" |
252b5132 RH |
28 | #include "opcode/ppc.h" |
29 | ||
30 | /* This file provides several disassembler functions, all of which use | |
31 | the disassembler interface defined in dis-asm.h. Several functions | |
32 | are provided because this file handles disassembly for the PowerPC | |
33 | in both big and little endian mode and also for the POWER (RS/6000) | |
34 | chip. */ | |
fa452fa6 PB |
35 | static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, |
36 | ppc_cpu_t); | |
252b5132 | 37 | |
fa452fa6 PB |
38 | struct dis_private |
39 | { | |
40 | /* Stash the result of parsing disassembler_options here. */ | |
41 | ppc_cpu_t dialect; | |
b240011a | 42 | } private; |
fa452fa6 PB |
43 | |
44 | #define POWERPC_DIALECT(INFO) \ | |
45 | (((struct dis_private *) ((INFO)->private_data))->dialect) | |
418c1742 | 46 | |
69fe9ce5 AM |
47 | struct ppc_mopt { |
48 | const char *opt; | |
49 | ppc_cpu_t cpu; | |
50 | ppc_cpu_t sticky; | |
51 | }; | |
52 | ||
53 | struct ppc_mopt ppc_opts[] = { | |
14b57c7c | 54 | { "403", PPC_OPCODE_PPC | PPC_OPCODE_403, |
69fe9ce5 | 55 | 0 }, |
14b57c7c | 56 | { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405, |
69fe9ce5 | 57 | 0 }, |
bdc70b4a AM |
58 | { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
59 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 60 | 0 }, |
bdc70b4a AM |
61 | { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 |
62 | | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | |
69fe9ce5 | 63 | 0 }, |
bdc70b4a AM |
64 | { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440 |
65 | | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), | |
9fe54b1c | 66 | 0 }, |
14b57c7c | 67 | { "601", PPC_OPCODE_PPC | PPC_OPCODE_601, |
69fe9ce5 | 68 | 0 }, |
14b57c7c | 69 | { "603", PPC_OPCODE_PPC, |
69fe9ce5 | 70 | 0 }, |
14b57c7c | 71 | { "604", PPC_OPCODE_PPC, |
69fe9ce5 | 72 | 0 }, |
14b57c7c | 73 | { "620", PPC_OPCODE_PPC | PPC_OPCODE_64, |
69fe9ce5 | 74 | 0 }, |
14b57c7c | 75 | { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 76 | 0 }, |
14b57c7c | 77 | { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 78 | 0 }, |
14b57c7c | 79 | { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 80 | 0 }, |
14b57c7c | 81 | { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, |
69fe9ce5 | 82 | 0 }, |
14b57c7c | 83 | { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS |
69fe9ce5 | 84 | , 0 }, |
14b57c7c | 85 | { "821", PPC_OPCODE_PPC | PPC_OPCODE_860, |
ef5a96d5 | 86 | 0 }, |
14b57c7c | 87 | { "850", PPC_OPCODE_PPC | PPC_OPCODE_860, |
ef5a96d5 | 88 | 0 }, |
14b57c7c | 89 | { "860", PPC_OPCODE_PPC | PPC_OPCODE_860, |
ef5a96d5 | 90 | 0 }, |
bdc70b4a AM |
91 | { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 |
92 | | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 | |
93 | | PPC_OPCODE_A2), | |
cdc51b07 | 94 | 0 }, |
14b57c7c | 95 | { "altivec", PPC_OPCODE_PPC, |
c7a5aa9c | 96 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, |
69fe9ce5 AM |
97 | { "any", 0, |
98 | PPC_OPCODE_ANY }, | |
14b57c7c | 99 | { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, |
69fe9ce5 | 100 | 0 }, |
14b57c7c | 101 | { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, |
69fe9ce5 | 102 | 0 }, |
bdc70b4a AM |
103 | { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
104 | | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 105 | 0 }, |
14b57c7c | 106 | { "com", PPC_OPCODE_COMMON, |
69fe9ce5 | 107 | 0 }, |
14b57c7c | 108 | { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300, |
69fe9ce5 AM |
109 | 0 }, |
110 | { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | |
111 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
112 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 113 | | PPC_OPCODE_E500), |
69fe9ce5 AM |
114 | 0 }, |
115 | { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
116 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
117 | | PPC_OPCODE_E500MC), | |
118 | 0 }, | |
0dc93057 AM |
119 | { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
120 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
63d0fa4e AM |
121 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 |
122 | | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), | |
0dc93057 | 123 | 0 }, |
aea77599 AM |
124 | { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL |
125 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
126 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | |
127 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
128 | | PPC_OPCODE_POWER7), | |
129 | 0 }, | |
130 | { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | |
131 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
132 | | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC | |
133 | | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 | |
134 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), | |
135 | 0 }, | |
69fe9ce5 AM |
136 | { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE |
137 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
138 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
e01d869a | 139 | | PPC_OPCODE_E500), |
69fe9ce5 | 140 | 0 }, |
14b57c7c | 141 | { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS, |
69fe9ce5 | 142 | 0 }, |
14b57c7c | 143 | { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, |
69fe9ce5 | 144 | 0 }, |
bdc70b4a AM |
145 | { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
146 | | PPC_OPCODE_POWER5), | |
69fe9ce5 | 147 | 0 }, |
bdc70b4a AM |
148 | { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
149 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
69fe9ce5 | 150 | 0 }, |
bdc70b4a AM |
151 | { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
152 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
153 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 154 | 0 }, |
5817ffd1 PB |
155 | { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
156 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
157 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM | |
158 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), | |
159 | 0 }, | |
a680de9a PB |
160 | { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
161 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
162 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | |
163 | | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | |
164 | | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ), | |
165 | 0 }, | |
14b57c7c | 166 | { "ppc", PPC_OPCODE_PPC, |
69fe9ce5 | 167 | 0 }, |
14b57c7c | 168 | { "ppc32", PPC_OPCODE_PPC, |
69fe9ce5 | 169 | 0 }, |
14b57c7c | 170 | { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64, |
69fe9ce5 | 171 | 0 }, |
14b57c7c | 172 | { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE, |
69fe9ce5 | 173 | 0 }, |
14b57c7c | 174 | { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS, |
69fe9ce5 | 175 | 0 }, |
14b57c7c | 176 | { "pwr", PPC_OPCODE_POWER, |
69fe9ce5 | 177 | 0 }, |
14b57c7c | 178 | { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, |
cdc51b07 | 179 | 0 }, |
14b57c7c | 180 | { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, |
cdc51b07 | 181 | 0 }, |
bdc70b4a AM |
182 | { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
183 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 184 | 0 }, |
bdc70b4a AM |
185 | { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
186 | | PPC_OPCODE_POWER5), | |
cdc51b07 | 187 | 0 }, |
bdc70b4a AM |
188 | { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 |
189 | | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), | |
cdc51b07 | 190 | 0 }, |
bdc70b4a AM |
191 | { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
192 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
193 | | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | |
69fe9ce5 | 194 | 0 }, |
5817ffd1 PB |
195 | { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
196 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
197 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM | |
198 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), | |
199 | 0 }, | |
a680de9a PB |
200 | { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 |
201 | | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
202 | | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | |
203 | | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | |
204 | | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ), | |
205 | 0 }, | |
14b57c7c | 206 | { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, |
69fe9ce5 | 207 | 0 }, |
14b57c7c | 208 | { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS, |
69fe9ce5 | 209 | PPC_OPCODE_SPE }, |
bdc70b4a AM |
210 | { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR |
211 | | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), | |
ce3d2015 | 212 | 0 }, |
14b57c7c AM |
213 | { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE |
214 | | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | |
215 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | |
216 | | PPC_OPCODE_E500), | |
b9c361e0 | 217 | PPC_OPCODE_VLE }, |
14b57c7c | 218 | { "vsx", PPC_OPCODE_PPC, |
a680de9a | 219 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 }, |
14b57c7c | 220 | { "htm", PPC_OPCODE_PPC, |
5817ffd1 | 221 | PPC_OPCODE_HTM }, |
69fe9ce5 AM |
222 | }; |
223 | ||
b9c361e0 JL |
224 | /* Switch between Booke and VLE dialects for interlinked dumps. */ |
225 | static ppc_cpu_t | |
226 | get_powerpc_dialect (struct disassemble_info *info) | |
227 | { | |
228 | ppc_cpu_t dialect = 0; | |
229 | ||
230 | dialect = POWERPC_DIALECT (info); | |
231 | ||
232 | /* Disassemble according to the section headers flags for VLE-mode. */ | |
233 | if (dialect & PPC_OPCODE_VLE | |
94caa966 AM |
234 | && info->section->owner != NULL |
235 | && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour | |
236 | && elf_object_id (info->section->owner) == PPC32_ELF_DATA | |
237 | && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) | |
b9c361e0 JL |
238 | return dialect; |
239 | else | |
240 | return dialect & ~ PPC_OPCODE_VLE; | |
241 | } | |
242 | ||
69fe9ce5 AM |
243 | /* Handle -m and -M options that set cpu type, and .machine arg. */ |
244 | ||
245 | ppc_cpu_t | |
776fc418 | 246 | ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg) |
69fe9ce5 | 247 | { |
69fe9ce5 AM |
248 | unsigned int i; |
249 | ||
250 | for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) | |
251 | if (strcmp (ppc_opts[i].opt, arg) == 0) | |
252 | { | |
253 | if (ppc_opts[i].sticky) | |
254 | { | |
776fc418 AM |
255 | *sticky |= ppc_opts[i].sticky; |
256 | if ((ppc_cpu & ~*sticky) != 0) | |
69fe9ce5 AM |
257 | break; |
258 | } | |
259 | ppc_cpu = ppc_opts[i].cpu; | |
260 | break; | |
261 | } | |
262 | if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0])) | |
263 | return 0; | |
264 | ||
776fc418 | 265 | ppc_cpu |= *sticky; |
69fe9ce5 AM |
266 | return ppc_cpu; |
267 | } | |
268 | ||
269 | /* Determine which set of machines to disassemble for. */ | |
418c1742 | 270 | |
b240011a | 271 | static void |
fa452fa6 | 272 | powerpc_init_dialect (struct disassemble_info *info) |
418c1742 | 273 | { |
69fe9ce5 | 274 | ppc_cpu_t dialect = 0; |
776fc418 | 275 | ppc_cpu_t sticky = 0; |
69fe9ce5 | 276 | char *arg; |
fa452fa6 PB |
277 | struct dis_private *priv = calloc (sizeof (*priv), 1); |
278 | ||
279 | if (priv == NULL) | |
b240011a | 280 | priv = &private; |
418c1742 | 281 | |
776fc418 AM |
282 | switch (info->mach) |
283 | { | |
284 | case bfd_mach_ppc_403: | |
285 | case bfd_mach_ppc_403gc: | |
4f6ffcd3 | 286 | dialect = ppc_parse_cpu (dialect, &sticky, "403"); |
776fc418 AM |
287 | break; |
288 | case bfd_mach_ppc_405: | |
4f6ffcd3 | 289 | dialect = ppc_parse_cpu (dialect, &sticky, "405"); |
776fc418 AM |
290 | break; |
291 | case bfd_mach_ppc_601: | |
4f6ffcd3 | 292 | dialect = ppc_parse_cpu (dialect, &sticky, "601"); |
776fc418 AM |
293 | break; |
294 | case bfd_mach_ppc_a35: | |
295 | case bfd_mach_ppc_rs64ii: | |
296 | case bfd_mach_ppc_rs64iii: | |
4f6ffcd3 | 297 | dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64; |
776fc418 AM |
298 | break; |
299 | case bfd_mach_ppc_e500: | |
4f6ffcd3 | 300 | dialect = ppc_parse_cpu (dialect, &sticky, "e500"); |
776fc418 AM |
301 | break; |
302 | case bfd_mach_ppc_e500mc: | |
4f6ffcd3 | 303 | dialect = ppc_parse_cpu (dialect, &sticky, "e500mc"); |
776fc418 AM |
304 | break; |
305 | case bfd_mach_ppc_e500mc64: | |
4f6ffcd3 | 306 | dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64"); |
776fc418 AM |
307 | break; |
308 | case bfd_mach_ppc_e5500: | |
4f6ffcd3 | 309 | dialect = ppc_parse_cpu (dialect, &sticky, "e5500"); |
776fc418 AM |
310 | break; |
311 | case bfd_mach_ppc_e6500: | |
4f6ffcd3 | 312 | dialect = ppc_parse_cpu (dialect, &sticky, "e6500"); |
776fc418 AM |
313 | break; |
314 | case bfd_mach_ppc_titan: | |
4f6ffcd3 | 315 | dialect = ppc_parse_cpu (dialect, &sticky, "titan"); |
776fc418 AM |
316 | break; |
317 | case bfd_mach_ppc_vle: | |
4f6ffcd3 | 318 | dialect = ppc_parse_cpu (dialect, &sticky, "vle"); |
776fc418 AM |
319 | break; |
320 | default: | |
a680de9a | 321 | dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY; |
776fc418 AM |
322 | } |
323 | ||
69fe9ce5 AM |
324 | arg = info->disassembler_options; |
325 | while (arg != NULL) | |
326 | { | |
327 | ppc_cpu_t new_cpu = 0; | |
328 | char *end = strchr (arg, ','); | |
9b4e5766 | 329 | |
69fe9ce5 AM |
330 | if (end != NULL) |
331 | *end = 0; | |
9b4e5766 | 332 | |
776fc418 | 333 | if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0) |
69fe9ce5 AM |
334 | dialect = new_cpu; |
335 | else if (strcmp (arg, "32") == 0) | |
7102e95e | 336 | dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; |
69fe9ce5 | 337 | else if (strcmp (arg, "64") == 0) |
bdc70b4a | 338 | dialect |= PPC_OPCODE_64; |
69fe9ce5 AM |
339 | else |
340 | fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); | |
9622b051 | 341 | |
69fe9ce5 AM |
342 | if (end != NULL) |
343 | *end++ = ','; | |
344 | arg = end; | |
345 | } | |
661bd698 | 346 | |
fa452fa6 PB |
347 | info->private_data = priv; |
348 | POWERPC_DIALECT(info) = dialect; | |
b240011a AM |
349 | } |
350 | ||
b9c361e0 JL |
351 | #define PPC_OPCD_SEGS 64 |
352 | static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; | |
353 | #define VLE_OPCD_SEGS 32 | |
354 | static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; | |
b240011a AM |
355 | |
356 | /* Calculate opcode table indices to speed up disassembly, | |
357 | and init dialect. */ | |
358 | ||
359 | void | |
360 | disassemble_init_powerpc (struct disassemble_info *info) | |
361 | { | |
362 | int i; | |
d6688282 | 363 | unsigned short last; |
fa452fa6 | 364 | |
27c49e9a | 365 | if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0) |
b240011a | 366 | { |
b240011a | 367 | |
27c49e9a AB |
368 | i = powerpc_num_opcodes; |
369 | while (--i >= 0) | |
370 | { | |
371 | unsigned op = PPC_OP (powerpc_opcodes[i].opcode); | |
372 | ||
373 | powerpc_opcd_indices[op] = i; | |
374 | } | |
375 | ||
376 | last = powerpc_num_opcodes; | |
377 | for (i = PPC_OPCD_SEGS; i > 0; --i) | |
378 | { | |
379 | if (powerpc_opcd_indices[i] == 0) | |
380 | powerpc_opcd_indices[i] = last; | |
381 | last = powerpc_opcd_indices[i]; | |
382 | } | |
383 | ||
384 | i = vle_num_opcodes; | |
385 | while (--i >= 0) | |
386 | { | |
387 | unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); | |
388 | unsigned seg = VLE_OP_TO_SEG (op); | |
389 | ||
390 | vle_opcd_indices[seg] = i; | |
391 | } | |
392 | ||
393 | last = vle_num_opcodes; | |
394 | for (i = VLE_OPCD_SEGS; i > 0; --i) | |
395 | { | |
396 | if (vle_opcd_indices[i] == 0) | |
397 | vle_opcd_indices[i] = last; | |
398 | last = vle_opcd_indices[i]; | |
399 | } | |
b9c361e0 JL |
400 | } |
401 | ||
b240011a AM |
402 | if (info->arch == bfd_arch_powerpc) |
403 | powerpc_init_dialect (info); | |
418c1742 MG |
404 | } |
405 | ||
406 | /* Print a big endian PowerPC instruction. */ | |
252b5132 RH |
407 | |
408 | int | |
823bbe9d | 409 | print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 410 | { |
b9c361e0 | 411 | return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); |
252b5132 RH |
412 | } |
413 | ||
418c1742 | 414 | /* Print a little endian PowerPC instruction. */ |
252b5132 RH |
415 | |
416 | int | |
823bbe9d | 417 | print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 | 418 | { |
b9c361e0 | 419 | return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); |
252b5132 RH |
420 | } |
421 | ||
422 | /* Print a POWER (RS/6000) instruction. */ | |
423 | ||
424 | int | |
823bbe9d | 425 | print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) |
252b5132 RH |
426 | { |
427 | return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); | |
428 | } | |
429 | ||
ea192fa3 PB |
430 | /* Extract the operand value from the PowerPC or POWER instruction. */ |
431 | ||
432 | static long | |
433 | operand_value_powerpc (const struct powerpc_operand *operand, | |
fa452fa6 | 434 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
435 | { |
436 | long value; | |
437 | int invalid; | |
438 | /* Extract the value from the instruction. */ | |
439 | if (operand->extract) | |
440 | value = (*operand->extract) (insn, dialect, &invalid); | |
441 | else | |
442 | { | |
b9c361e0 JL |
443 | if (operand->shift >= 0) |
444 | value = (insn >> operand->shift) & operand->bitm; | |
445 | else | |
446 | value = (insn << -operand->shift) & operand->bitm; | |
ea192fa3 PB |
447 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
448 | { | |
449 | /* BITM is always some number of zeros followed by some | |
b9c361e0 | 450 | number of ones, followed by some number of zeros. */ |
ea192fa3 PB |
451 | unsigned long top = operand->bitm; |
452 | /* top & -top gives the rightmost 1 bit, so this | |
453 | fills in any trailing zeros. */ | |
454 | top |= (top & -top) - 1; | |
455 | top &= ~(top >> 1); | |
456 | value = (value ^ top) - top; | |
457 | } | |
458 | } | |
459 | ||
460 | return value; | |
461 | } | |
462 | ||
463 | /* Determine whether the optional operand(s) should be printed. */ | |
464 | ||
465 | static int | |
466 | skip_optional_operands (const unsigned char *opindex, | |
fa452fa6 | 467 | unsigned long insn, ppc_cpu_t dialect) |
ea192fa3 PB |
468 | { |
469 | const struct powerpc_operand *operand; | |
470 | ||
471 | for (; *opindex != 0; opindex++) | |
472 | { | |
473 | operand = &powerpc_operands[*opindex]; | |
474 | if ((operand->flags & PPC_OPERAND_NEXT) != 0 | |
475 | || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 | |
11a0cf2e PB |
476 | && operand_value_powerpc (operand, insn, dialect) != |
477 | ppc_optional_operand_value (operand))) | |
ea192fa3 PB |
478 | return 0; |
479 | } | |
480 | ||
481 | return 1; | |
482 | } | |
483 | ||
d6688282 AM |
484 | /* Find a match for INSN in the opcode table, given machine DIALECT. |
485 | A DIALECT of -1 is special, matching all machine opcode variations. */ | |
b9c361e0 | 486 | |
d6688282 AM |
487 | static const struct powerpc_opcode * |
488 | lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) | |
489 | { | |
490 | const struct powerpc_opcode *opcode; | |
491 | const struct powerpc_opcode *opcode_end; | |
492 | unsigned long op; | |
493 | ||
494 | /* Get the major opcode of the instruction. */ | |
495 | op = PPC_OP (insn); | |
496 | ||
497 | /* Find the first match in the opcode table for this major opcode. */ | |
498 | opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; | |
499 | for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; | |
500 | opcode < opcode_end; | |
501 | ++opcode) | |
502 | { | |
503 | const unsigned char *opindex; | |
504 | const struct powerpc_operand *operand; | |
505 | int invalid; | |
506 | ||
507 | if ((insn & opcode->mask) != opcode->opcode | |
508 | || (dialect != (ppc_cpu_t) -1 | |
509 | && ((opcode->flags & dialect) == 0 | |
510 | || (opcode->deprecated & dialect) != 0))) | |
511 | continue; | |
512 | ||
513 | /* Check validity of operands. */ | |
514 | invalid = 0; | |
515 | for (opindex = opcode->operands; *opindex != 0; opindex++) | |
516 | { | |
517 | operand = powerpc_operands + *opindex; | |
518 | if (operand->extract) | |
519 | (*operand->extract) (insn, dialect, &invalid); | |
520 | } | |
521 | if (invalid) | |
522 | continue; | |
523 | ||
524 | return opcode; | |
525 | } | |
526 | ||
527 | return NULL; | |
528 | } | |
529 | ||
b9c361e0 JL |
530 | /* Find a match for INSN in the VLE opcode table. */ |
531 | ||
532 | static const struct powerpc_opcode * | |
533 | lookup_vle (unsigned long insn) | |
534 | { | |
535 | const struct powerpc_opcode *opcode; | |
536 | const struct powerpc_opcode *opcode_end; | |
537 | unsigned op, seg; | |
538 | ||
539 | op = PPC_OP (insn); | |
540 | if (op >= 0x20 && op <= 0x37) | |
541 | { | |
542 | /* This insn has a 4-bit opcode. */ | |
543 | op &= 0x3c; | |
544 | } | |
545 | seg = VLE_OP_TO_SEG (op); | |
546 | ||
547 | /* Find the first match in the opcode table for this major opcode. */ | |
548 | opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; | |
549 | for (opcode = vle_opcodes + vle_opcd_indices[seg]; | |
550 | opcode < opcode_end; | |
551 | ++opcode) | |
552 | { | |
553 | unsigned long table_opcd = opcode->opcode; | |
554 | unsigned long table_mask = opcode->mask; | |
555 | bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); | |
556 | unsigned long insn2; | |
557 | const unsigned char *opindex; | |
558 | const struct powerpc_operand *operand; | |
559 | int invalid; | |
560 | ||
561 | insn2 = insn; | |
562 | if (table_op_is_short) | |
563 | insn2 >>= 16; | |
564 | if ((insn2 & table_mask) != table_opcd) | |
565 | continue; | |
566 | ||
567 | /* Check validity of operands. */ | |
568 | invalid = 0; | |
569 | for (opindex = opcode->operands; *opindex != 0; ++opindex) | |
570 | { | |
571 | operand = powerpc_operands + *opindex; | |
572 | if (operand->extract) | |
573 | (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); | |
574 | } | |
575 | if (invalid) | |
576 | continue; | |
577 | ||
578 | return opcode; | |
579 | } | |
580 | ||
581 | return NULL; | |
582 | } | |
583 | ||
252b5132 RH |
584 | /* Print a PowerPC or POWER instruction. */ |
585 | ||
586 | static int | |
823bbe9d AM |
587 | print_insn_powerpc (bfd_vma memaddr, |
588 | struct disassemble_info *info, | |
589 | int bigendian, | |
fa452fa6 | 590 | ppc_cpu_t dialect) |
252b5132 RH |
591 | { |
592 | bfd_byte buffer[4]; | |
593 | int status; | |
594 | unsigned long insn; | |
595 | const struct powerpc_opcode *opcode; | |
b9c361e0 | 596 | bfd_boolean insn_is_short; |
252b5132 RH |
597 | |
598 | status = (*info->read_memory_func) (memaddr, buffer, 4, info); | |
599 | if (status != 0) | |
600 | { | |
b9c361e0 JL |
601 | /* The final instruction may be a 2-byte VLE insn. */ |
602 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
603 | { | |
604 | /* Clear buffer so unused bytes will not have garbage in them. */ | |
605 | buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; | |
606 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
607 | if (status != 0) | |
608 | { | |
609 | (*info->memory_error_func) (status, memaddr, info); | |
610 | return -1; | |
611 | } | |
612 | } | |
613 | else | |
614 | { | |
615 | (*info->memory_error_func) (status, memaddr, info); | |
616 | return -1; | |
617 | } | |
252b5132 RH |
618 | } |
619 | ||
620 | if (bigendian) | |
621 | insn = bfd_getb32 (buffer); | |
622 | else | |
623 | insn = bfd_getl32 (buffer); | |
624 | ||
b9c361e0 JL |
625 | /* Get the major opcode of the insn. */ |
626 | opcode = NULL; | |
627 | insn_is_short = FALSE; | |
628 | if ((dialect & PPC_OPCODE_VLE) != 0) | |
629 | { | |
630 | opcode = lookup_vle (insn); | |
631 | if (opcode != NULL) | |
632 | insn_is_short = PPC_OP_SE_VLE(opcode->mask); | |
633 | } | |
634 | if (opcode == NULL) | |
635 | opcode = lookup_powerpc (insn, dialect); | |
d6688282 AM |
636 | if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) |
637 | opcode = lookup_powerpc (insn, (ppc_cpu_t) -1); | |
252b5132 | 638 | |
d6688282 | 639 | if (opcode != NULL) |
252b5132 | 640 | { |
252b5132 RH |
641 | const unsigned char *opindex; |
642 | const struct powerpc_operand *operand; | |
252b5132 RH |
643 | int need_comma; |
644 | int need_paren; | |
ea192fa3 | 645 | int skip_optional; |
252b5132 | 646 | |
252b5132 | 647 | if (opcode->operands[0] != 0) |
fdd12ef3 AM |
648 | (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); |
649 | else | |
650 | (*info->fprintf_func) (info->stream, "%s", opcode->name); | |
252b5132 | 651 | |
b9c361e0 JL |
652 | if (insn_is_short) |
653 | /* The operands will be fetched out of the 16-bit instruction. */ | |
654 | insn >>= 16; | |
655 | ||
252b5132 RH |
656 | /* Now extract and print the operands. */ |
657 | need_comma = 0; | |
658 | need_paren = 0; | |
ea192fa3 | 659 | skip_optional = -1; |
252b5132 RH |
660 | for (opindex = opcode->operands; *opindex != 0; opindex++) |
661 | { | |
662 | long value; | |
663 | ||
664 | operand = powerpc_operands + *opindex; | |
665 | ||
666 | /* Operands that are marked FAKE are simply ignored. We | |
667 | already made sure that the extract function considered | |
668 | the instruction to be valid. */ | |
669 | if ((operand->flags & PPC_OPERAND_FAKE) != 0) | |
670 | continue; | |
671 | ||
ea192fa3 PB |
672 | /* If all of the optional operands have the value zero, |
673 | then don't print any of them. */ | |
65b650b4 AM |
674 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
675 | { | |
676 | if (skip_optional < 0) | |
677 | skip_optional = skip_optional_operands (opindex, insn, | |
678 | dialect); | |
679 | if (skip_optional) | |
680 | continue; | |
681 | } | |
252b5132 | 682 | |
ea192fa3 PB |
683 | value = operand_value_powerpc (operand, insn, dialect); |
684 | ||
252b5132 RH |
685 | if (need_comma) |
686 | { | |
687 | (*info->fprintf_func) (info->stream, ","); | |
688 | need_comma = 0; | |
689 | } | |
690 | ||
691 | /* Print the operand as directed by the flags. */ | |
fdd12ef3 AM |
692 | if ((operand->flags & PPC_OPERAND_GPR) != 0 |
693 | || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) | |
252b5132 RH |
694 | (*info->fprintf_func) (info->stream, "r%ld", value); |
695 | else if ((operand->flags & PPC_OPERAND_FPR) != 0) | |
696 | (*info->fprintf_func) (info->stream, "f%ld", value); | |
786e2c0f C |
697 | else if ((operand->flags & PPC_OPERAND_VR) != 0) |
698 | (*info->fprintf_func) (info->stream, "v%ld", value); | |
9b4e5766 PB |
699 | else if ((operand->flags & PPC_OPERAND_VSR) != 0) |
700 | (*info->fprintf_func) (info->stream, "vs%ld", value); | |
252b5132 RH |
701 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) |
702 | (*info->print_address_func) (memaddr + value, info); | |
703 | else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
704 | (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); | |
43e65147 | 705 | else if ((operand->flags & PPC_OPERAND_FSL) != 0) |
081ba1b3 AM |
706 | (*info->fprintf_func) (info->stream, "fsl%ld", value); |
707 | else if ((operand->flags & PPC_OPERAND_FCR) != 0) | |
708 | (*info->fprintf_func) (info->stream, "fcr%ld", value); | |
709 | else if ((operand->flags & PPC_OPERAND_UDI) != 0) | |
710 | (*info->fprintf_func) (info->stream, "%ld", value); | |
b9c361e0 JL |
711 | else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 |
712 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
713 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
714 | (*info->fprintf_func) (info->stream, "cr%ld", value); | |
715 | else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
716 | && (((dialect & PPC_OPCODE_PPC) != 0) | |
717 | || ((dialect & PPC_OPCODE_VLE) != 0))) | |
252b5132 | 718 | { |
b9c361e0 JL |
719 | static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; |
720 | int cr; | |
721 | int cc; | |
722 | ||
723 | cr = value >> 2; | |
724 | if (cr != 0) | |
725 | (*info->fprintf_func) (info->stream, "4*cr%d+", cr); | |
726 | cc = value & 3; | |
727 | (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); | |
252b5132 | 728 | } |
70dc4e32 | 729 | else |
d908c8af | 730 | (*info->fprintf_func) (info->stream, "%d", (int) value); |
252b5132 RH |
731 | |
732 | if (need_paren) | |
733 | { | |
734 | (*info->fprintf_func) (info->stream, ")"); | |
735 | need_paren = 0; | |
736 | } | |
737 | ||
738 | if ((operand->flags & PPC_OPERAND_PARENS) == 0) | |
739 | need_comma = 1; | |
740 | else | |
741 | { | |
742 | (*info->fprintf_func) (info->stream, "("); | |
743 | need_paren = 1; | |
744 | } | |
745 | } | |
746 | ||
b9c361e0 JL |
747 | /* We have found and printed an instruction. |
748 | If it was a short VLE instruction we have more to do. */ | |
749 | if (insn_is_short) | |
750 | { | |
751 | memaddr += 2; | |
752 | return 2; | |
753 | } | |
754 | else | |
755 | /* Otherwise, return. */ | |
756 | return 4; | |
252b5132 RH |
757 | } |
758 | ||
759 | /* We could not find a match. */ | |
760 | (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); | |
761 | ||
762 | return 4; | |
763 | } | |
07dd56a9 NC |
764 | |
765 | void | |
823bbe9d | 766 | print_ppc_disassembler_options (FILE *stream) |
07dd56a9 | 767 | { |
69fe9ce5 AM |
768 | unsigned int i, col; |
769 | ||
770 | fprintf (stream, _("\n\ | |
07dd56a9 | 771 | The following PPC specific disassembler options are supported for use with\n\ |
69fe9ce5 AM |
772 | the -M switch:\n")); |
773 | ||
774 | for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) | |
775 | { | |
776 | col += fprintf (stream, " %s,", ppc_opts[i].opt); | |
777 | if (col > 66) | |
778 | { | |
779 | fprintf (stream, "\n"); | |
780 | col = 0; | |
781 | } | |
782 | } | |
783 | fprintf (stream, " 32, 64\n"); | |
07dd56a9 | 784 | } |