[deliverable/binutils-gdb.git] / opcodes / ppc-dis.c

/* ppc-dis.c -- Disassemble PowerPC instructions
   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006
   Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#include <stdio.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/ppc.h"

/* This file provides several disassembler functions, all of which use
   the disassembler interface defined in dis-asm.h.  Several functions
   are provided because this file handles disassembly for the PowerPC
   in both big and little endian mode and also for the POWER (RS/6000)
   chip.  */

static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);

/* Determine which set of machines to disassemble for.  PPC403/601 or
   BookE.  For convenience, also disassemble instructions supported
   by the AltiVec vector unit.  */

static int
powerpc_dialect (struct disassemble_info *info)
{
  int dialect = PPC_OPCODE_PPC;

  if (BFD_DEFAULT_TARGET_SIZE == 64)
    dialect |= PPC_OPCODE_64;

  if (info->disassembler_options
      && strstr (info->disassembler_options, "booke") != NULL)
    dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
  else if ((info->mach == bfd_mach_ppc_e500)
	   || (info->disassembler_options
	       && strstr (info->disassembler_options, "e500") != NULL))
    dialect |= (PPC_OPCODE_BOOKE
		| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
		| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
		| PPC_OPCODE_RFMCI);
  else if (info->disassembler_options
	   && strstr (info->disassembler_options, "efs") != NULL)
    dialect |= PPC_OPCODE_EFS;
  else if (info->disassembler_options
	   && strstr (info->disassembler_options, "e300") != NULL)
    dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
  else
    dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
		| PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);

  if (info->disassembler_options
      && strstr (info->disassembler_options, "power4") != NULL)
    dialect |= PPC_OPCODE_POWER4;

  if (info->disassembler_options
      && strstr (info->disassembler_options, "power5") != NULL)
    dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;

  if (info->disassembler_options
      && strstr (info->disassembler_options, "cell") != NULL)
    dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;

  if (info->disassembler_options
      && strstr (info->disassembler_options, "power6") != NULL)
    dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;

  if (info->disassembler_options
      && strstr (info->disassembler_options, "any") != NULL)
    dialect |= PPC_OPCODE_ANY;

  if (info->disassembler_options)
    {
      if (strstr (info->disassembler_options, "32") != NULL)
	dialect &= ~PPC_OPCODE_64;
      else if (strstr (info->disassembler_options, "64") != NULL)
	dialect |= PPC_OPCODE_64;
    }

  info->private_data = (char *) 0 + dialect;
  return dialect;
}

/* Print a big endian PowerPC instruction.  */

int
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  int dialect = (char *) info->private_data - (char *) 0;
  return print_insn_powerpc (memaddr, info, 1, dialect);
}

/* Print a little endian PowerPC instruction.  */

int
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  int dialect = (char *) info->private_data - (char *) 0;
  return print_insn_powerpc (memaddr, info, 0, dialect);
}

/* Print a POWER (RS/6000) instruction.  */

int
print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
{
  return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
}

/* Print a PowerPC or POWER instruction.  */

static int
print_insn_powerpc (bfd_vma memaddr,
		    struct disassemble_info *info,
		    int bigendian,
		    int dialect)
{
  bfd_byte buffer[4];
  int status;
  unsigned long insn;
  const struct powerpc_opcode *opcode;
  const struct powerpc_opcode *opcode_end;
  unsigned long op;

  if (dialect == 0)
    dialect = powerpc_dialect (info);

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  if (bigendian)
    insn = bfd_getb32 (buffer);
  else
    insn = bfd_getl32 (buffer);

  /* Get the major opcode of the instruction.  */
  op = PPC_OP (insn);

  /* Find the first match in the opcode table.  We could speed this up
     a bit by doing a binary search on the major opcode.  */
  opcode_end = powerpc_opcodes + powerpc_num_opcodes;
 again:
  for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
    {
      unsigned long table_op;
      const unsigned char *opindex;
      const struct powerpc_operand *operand;
      int invalid;
      int need_comma;
      int need_paren;

      table_op = PPC_OP (opcode->opcode);
      if (op < table_op)
	break;
      if (op > table_op)
	continue;

      if ((insn & opcode->mask) != opcode->opcode
	  || (opcode->flags & dialect) == 0)
	continue;

      /* Make two passes over the operands.  First see if any of them
	 have extraction functions, and, if they do, make sure the
	 instruction is valid.  */
      invalid = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  operand = powerpc_operands + *opindex;
	  if (operand->extract)
	    (*operand->extract) (insn, dialect, &invalid);
	}
      if (invalid)
	continue;

      /* The instruction is valid.  */
      if (opcode->operands[0] != 0)
	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
      else
	(*info->fprintf_func) (info->stream, "%s", opcode->name);

      /* Now extract and print the operands.  */
      need_comma = 0;
      need_paren = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  long value;

	  operand = powerpc_operands + *opindex;

	  /* Operands that are marked FAKE are simply ignored.  We
	     already made sure that the extract function considered
	     the instruction to be valid.  */
	  if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	    continue;

	  /* Extract the value from the instruction.  */
	  if (operand->extract)
	    value = (*operand->extract) (insn, dialect, &invalid);
	  else
	    {
	      value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
	      if ((operand->flags & PPC_OPERAND_SIGNED) != 0
		  && (value & (1 << (operand->bits - 1))) != 0)
		value -= 1 << operand->bits;
	    }

	  /* If the operand is optional, and the value is zero, don't
	     print anything.  */
	  if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	      && (operand->flags & PPC_OPERAND_NEXT) == 0
	      && value == 0)
	    continue;

	  if (need_comma)
	    {
	      (*info->fprintf_func) (info->stream, ",");
	      need_comma = 0;
	    }

	  /* Print the operand as directed by the flags.  */
	  if ((operand->flags & PPC_OPERAND_GPR) != 0
	      || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
	    (*info->fprintf_func) (info->stream, "r%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	    (*info->fprintf_func) (info->stream, "f%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VR) != 0)
	    (*info->fprintf_func) (info->stream, "v%ld", value);
	  else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	    (*info->print_address_func) (memaddr + value, info);
	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	  else if ((operand->flags & PPC_OPERAND_CR) == 0
		   || (dialect & PPC_OPCODE_PPC) == 0)
	    (*info->fprintf_func) (info->stream, "%ld", value);
	  else
	    {
	      if (operand->bits == 3)
		(*info->fprintf_func) (info->stream, "cr%ld", value);
	      else
		{
		  static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
		  int cr;
		  int cc;

		  cr = value >> 2;
		  if (cr != 0)
		    (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
		  cc = value & 3;
		  (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
		}
	    }

	  if (need_paren)
	    {
	      (*info->fprintf_func) (info->stream, ")");
	      need_paren = 0;
	    }

	  if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	    need_comma = 1;
	  else
	    {
	      (*info->fprintf_func) (info->stream, "(");
	      need_paren = 1;
	    }
	}

      /* We have found and printed an instruction; return.  */
      return 4;
    }

  if ((dialect & PPC_OPCODE_ANY) != 0)
    {
      dialect = ~PPC_OPCODE_ANY;
      goto again;
    }

  /* We could not find a match.  */
  (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);

  return 4;
}

void
print_ppc_disassembler_options (FILE *stream)
{
  fprintf (stream, "\n\
The following PPC specific disassembler options are supported for use with\n\
the -M switch:\n");

  fprintf (stream, "  booke|booke32|booke64    Disassemble the BookE instructions\n");
  fprintf (stream, "  e300                     Disassemble the e300 instructions\n");
  fprintf (stream, "  e500|e500x2              Disassemble the e500 instructions\n");
  fprintf (stream, "  efs                      Disassemble the EFS instructions\n");
  fprintf (stream, "  power4                   Disassemble the Power4 instructions\n");
  fprintf (stream, "  power5                   Disassemble the Power5 instructions\n");
  fprintf (stream, "  power6                   Disassemble the Power6 instructions\n");
  fprintf (stream, "  32                       Do not disassemble 64-bit instructions\n");
  fprintf (stream, "  64                       Allow disassembly of 64-bit instructions\n");
}
Commit	Line	Data
252b5132	1	/* ppc-dis.c -- Disassemble PowerPC instructions
9622b051	2	Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006
8427c424	3	Free Software Foundation, Inc.
252b5132 RH	4	Written by Ian Lance Taylor, Cygnus Support
	5
	6	This file is part of GDB, GAS, and the GNU binutils.
	7
	8	GDB, GAS, and the GNU binutils are free software; you can redistribute
	9	them and/or modify them under the terms of the GNU General Public
	10	License as published by the Free Software Foundation; either version
	11	2, or (at your option) any later version.
	12
	13	GDB, GAS, and the GNU binutils are distributed in the hope that they
	14	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	15	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	16	the GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this file; see the file COPYING. If not, write to the Free
f4321104	20	Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 RH	21
252b5132 RH	22	#include <stdio.h>
252b5132 RH	23	#include "sysdep.h"
	24	#include "dis-asm.h"
	25	#include "opcode/ppc.h"
	26
	27	/* This file provides several disassembler functions, all of which use
	28	the disassembler interface defined in dis-asm.h. Several functions
	29	are provided because this file handles disassembly for the PowerPC
	30	in both big and little endian mode and also for the POWER (RS/6000)
	31	chip. */
	32
823bbe9d	33	static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
418c1742 MG	34
418c1742 MG	35	/* Determine which set of machines to disassemble for. PPC403/601 or
9a0ccb24 MG	36	BookE. For convenience, also disassemble instructions supported
9a0ccb24 MG	37	by the AltiVec vector unit. */
418c1742	38
661bd698	39	static int
823bbe9d	40	powerpc_dialect (struct disassemble_info *info)
418c1742	41	{
4eb30afc	42	int dialect = PPC_OPCODE_PPC;
418c1742	43
802a735e AM	44	if (BFD_DEFAULT_TARGET_SIZE == 64)
	45	dialect \|= PPC_OPCODE_64;
	46
	47	if (info->disassembler_options
661bd698	48	&& strstr (info->disassembler_options, "booke") != NULL)
418c1742	49	dialect \|= PPC_OPCODE_BOOKE \| PPC_OPCODE_BOOKE64;
661bd698 AM	50	else if ((info->mach == bfd_mach_ppc_e500)
	51	\|\| (info->disassembler_options
	52	&& strstr (info->disassembler_options, "e500") != NULL))
4eb30afc AM	53	dialect \|= (PPC_OPCODE_BOOKE
	54	\| PPC_OPCODE_SPE \| PPC_OPCODE_ISEL
	55	\| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
	56	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK
	57	\| PPC_OPCODE_RFMCI);
661bd698 AM	58	else if (info->disassembler_options
661bd698 AM	59	&& strstr (info->disassembler_options, "efs") != NULL)
4eb30afc	60	dialect \|= PPC_OPCODE_EFS;
36ae0db3 DJ	61	else if (info->disassembler_options
	62	&& strstr (info->disassembler_options, "e300") != NULL)
	63	dialect \|= PPC_OPCODE_E300 \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_COMMON;
23976049	64	else
9ec878e3	65	dialect \|= (PPC_OPCODE_403 \| PPC_OPCODE_601 \| PPC_OPCODE_CLASSIC
4eb30afc	66	\| PPC_OPCODE_COMMON \| PPC_OPCODE_ALTIVEC);
802a735e	67
94efba12	68	if (info->disassembler_options
661bd698	69	&& strstr (info->disassembler_options, "power4") != NULL)
94efba12 AM	70	dialect \|= PPC_OPCODE_POWER4;
94efba12 AM	71
1ed8e1e4 AM	72	if (info->disassembler_options
	73	&& strstr (info->disassembler_options, "power5") != NULL)
	74	dialect \|= PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5;
	75
ede602d7 AM	76	if (info->disassembler_options
	77	&& strstr (info->disassembler_options, "cell") != NULL)
	78	dialect \|= PPC_OPCODE_POWER4 \| PPC_OPCODE_CELL \| PPC_OPCODE_ALTIVEC;
	79
9622b051 AM	80	if (info->disassembler_options
	81	&& strstr (info->disassembler_options, "power6") != NULL)
	82	dialect \|= PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6 \| PPC_OPCODE_ALTIVEC;
	83
661bd698 AM	84	if (info->disassembler_options
	85	&& strstr (info->disassembler_options, "any") != NULL)
	86	dialect \|= PPC_OPCODE_ANY;
	87
802a735e AM	88	if (info->disassembler_options)
	89	{
	90	if (strstr (info->disassembler_options, "32") != NULL)
	91	dialect &= ~PPC_OPCODE_64;
	92	else if (strstr (info->disassembler_options, "64") != NULL)
	93	dialect \|= PPC_OPCODE_64;
	94	}
	95
6edfbbad	96	info->private_data = (char *) 0 + dialect;
418c1742 MG	97	return dialect;
	98	}
	99
	100	/* Print a big endian PowerPC instruction. */
252b5132 RH	101
252b5132 RH	102	int
823bbe9d	103	print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	104	{
6edfbbad	105	int dialect = (char ) info->private_data - (char ) 0;
661bd698	106	return print_insn_powerpc (memaddr, info, 1, dialect);
252b5132 RH	107	}
252b5132 RH	108
418c1742	109	/* Print a little endian PowerPC instruction. */
252b5132 RH	110
252b5132 RH	111	int
823bbe9d	112	print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	113	{
6edfbbad	114	int dialect = (char ) info->private_data - (char ) 0;
661bd698	115	return print_insn_powerpc (memaddr, info, 0, dialect);
252b5132 RH	116	}
	117
	118	/* Print a POWER (RS/6000) instruction. */
	119
	120	int
823bbe9d	121	print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
252b5132 RH	122	{
	123	return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
	124	}
	125
	126	/* Print a PowerPC or POWER instruction. */
	127
	128	static int
823bbe9d AM	129	print_insn_powerpc (bfd_vma memaddr,
	130	struct disassemble_info *info,
	131	int bigendian,
	132	int dialect)
252b5132 RH	133	{
	134	bfd_byte buffer[4];
	135	int status;
	136	unsigned long insn;
	137	const struct powerpc_opcode *opcode;
	138	const struct powerpc_opcode *opcode_end;
	139	unsigned long op;
	140
661bd698 AM	141	if (dialect == 0)
	142	dialect = powerpc_dialect (info);
	143
252b5132 RH	144	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	145	if (status != 0)
	146	{
	147	(*info->memory_error_func) (status, memaddr, info);
	148	return -1;
	149	}
	150
	151	if (bigendian)
	152	insn = bfd_getb32 (buffer);
	153	else
	154	insn = bfd_getl32 (buffer);
	155
	156	/* Get the major opcode of the instruction. */
	157	op = PPC_OP (insn);
	158
	159	/* Find the first match in the opcode table. We could speed this up
	160	a bit by doing a binary search on the major opcode. */
	161	opcode_end = powerpc_opcodes + powerpc_num_opcodes;
661bd698	162	again:
252b5132 RH	163	for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
	164	{
	165	unsigned long table_op;
	166	const unsigned char *opindex;
	167	const struct powerpc_operand *operand;
	168	int invalid;
	169	int need_comma;
	170	int need_paren;
	171
	172	table_op = PPC_OP (opcode->opcode);
	173	if (op < table_op)
	174	break;
	175	if (op > table_op)
	176	continue;
	177
	178	if ((insn & opcode->mask) != opcode->opcode
	179	\|\| (opcode->flags & dialect) == 0)
	180	continue;
	181
	182	/* Make two passes over the operands. First see if any of them
	183	have extraction functions, and, if they do, make sure the
	184	instruction is valid. */
	185	invalid = 0;
	186	for (opindex = opcode->operands; *opindex != 0; opindex++)
	187	{
	188	operand = powerpc_operands + *opindex;
	189	if (operand->extract)
802a735e	190	(*operand->extract) (insn, dialect, &invalid);
252b5132 RH	191	}
	192	if (invalid)
	193	continue;
	194
	195	/* The instruction is valid. */
252b5132	196	if (opcode->operands[0] != 0)
fdd12ef3 AM	197	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
	198	else
	199	(*info->fprintf_func) (info->stream, "%s", opcode->name);
252b5132 RH	200
	201	/* Now extract and print the operands. */
	202	need_comma = 0;
	203	need_paren = 0;
	204	for (opindex = opcode->operands; *opindex != 0; opindex++)
	205	{
	206	long value;
	207
	208	operand = powerpc_operands + *opindex;
	209
	210	/* Operands that are marked FAKE are simply ignored. We
	211	already made sure that the extract function considered
	212	the instruction to be valid. */
	213	if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	214	continue;
	215
	216	/* Extract the value from the instruction. */
	217	if (operand->extract)
8427c424	218	value = (*operand->extract) (insn, dialect, &invalid);
252b5132 RH	219	else
	220	{
	221	value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
	222	if ((operand->flags & PPC_OPERAND_SIGNED) != 0
	223	&& (value & (1 << (operand->bits - 1))) != 0)
	224	value -= 1 << operand->bits;
	225	}
	226
	227	/* If the operand is optional, and the value is zero, don't
	228	print anything. */
	229	if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	230	&& (operand->flags & PPC_OPERAND_NEXT) == 0
	231	&& value == 0)
	232	continue;
	233
	234	if (need_comma)
	235	{
	236	(*info->fprintf_func) (info->stream, ",");
	237	need_comma = 0;
	238	}
	239
	240	/* Print the operand as directed by the flags. */
fdd12ef3 AM	241	if ((operand->flags & PPC_OPERAND_GPR) != 0
fdd12ef3 AM	242	\|\| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
252b5132 RH	243	(*info->fprintf_func) (info->stream, "r%ld", value);
	244	else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	245	(*info->fprintf_func) (info->stream, "f%ld", value);
786e2c0f C	246	else if ((operand->flags & PPC_OPERAND_VR) != 0)
786e2c0f C	247	(*info->fprintf_func) (info->stream, "v%ld", value);
252b5132 RH	248	else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	249	(*info->print_address_func) (memaddr + value, info);
	250	else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	251	(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	252	else if ((operand->flags & PPC_OPERAND_CR) == 0
	253	\|\| (dialect & PPC_OPCODE_PPC) == 0)
	254	(*info->fprintf_func) (info->stream, "%ld", value);
	255	else
	256	{
	257	if (operand->bits == 3)
0fd3a477	258	(*info->fprintf_func) (info->stream, "cr%ld", value);
252b5132 RH	259	else
	260	{
	261	static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
	262	int cr;
	263	int cc;
	264
	265	cr = value >> 2;
	266	if (cr != 0)
8b4fa155	267	(info->fprintf_func) (info->stream, "4cr%d+", cr);
252b5132	268	cc = value & 3;
8b4fa155	269	(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
252b5132 RH	270	}
	271	}
	272
	273	if (need_paren)
	274	{
	275	(*info->fprintf_func) (info->stream, ")");
	276	need_paren = 0;
	277	}
	278
	279	if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	280	need_comma = 1;
	281	else
	282	{
	283	(*info->fprintf_func) (info->stream, "(");
	284	need_paren = 1;
	285	}
	286	}
	287
	288	/* We have found and printed an instruction; return. */
	289	return 4;
	290	}
	291
661bd698 AM	292	if ((dialect & PPC_OPCODE_ANY) != 0)
	293	{
	294	dialect = ~PPC_OPCODE_ANY;
	295	goto again;
	296	}
	297
252b5132 RH	298	/* We could not find a match. */
	299	(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
	300
	301	return 4;
	302	}
07dd56a9 NC	303
07dd56a9 NC	304	void
823bbe9d	305	print_ppc_disassembler_options (FILE *stream)
07dd56a9 NC	306	{
	307	fprintf (stream, "\n\
	308	The following PPC specific disassembler options are supported for use with\n\
	309	the -M switch:\n");
8b4fa155	310
07dd56a9	311	fprintf (stream, " booke\|booke32\|booke64 Disassemble the BookE instructions\n");
36ae0db3	312	fprintf (stream, " e300 Disassemble the e300 instructions\n");
07dd56a9 NC	313	fprintf (stream, " e500\|e500x2 Disassemble the e500 instructions\n");
	314	fprintf (stream, " efs Disassemble the EFS instructions\n");
	315	fprintf (stream, " power4 Disassemble the Power4 instructions\n");
1ed8e1e4	316	fprintf (stream, " power5 Disassemble the Power5 instructions\n");
9622b051	317	fprintf (stream, " power6 Disassemble the Power6 instructions\n");
07dd56a9 NC	318	fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
	319	fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
	320	}