Commit | Line | Data |
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252b5132 | 1 | /* ppc-opc.c -- PowerPC opcode list |
b3adc24a | 2 | Copyright (C) 1994-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
9b201bb5 | 5 | This file is part of the GNU opcodes library. |
252b5132 | 6 | |
9b201bb5 NC |
7 | This library is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
252b5132 | 11 | |
9b201bb5 NC |
12 | It is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
252b5132 | 16 | |
112290ab | 17 | You should have received a copy of the GNU General Public License |
9b201bb5 NC |
18 | along with this file; see the file COPYING. If not, write to the |
19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 | 21 | |
0d8dfecf | 22 | #include "sysdep.h" |
df7b86aa | 23 | #include <stdio.h> |
252b5132 RH |
24 | #include "opcode/ppc.h" |
25 | #include "opintl.h" | |
26 | ||
27 | /* This file holds the PowerPC opcode table. The opcode table | |
28 | includes almost all of the extended instruction mnemonics. This | |
29 | permits the disassembler to use them, and simplifies the assembler | |
30 | logic, at the cost of increasing the table size. The table is | |
31 | strictly constant data, so the compiler should be able to put it in | |
b80c7270 | 32 | the text segment. |
252b5132 RH |
33 | |
34 | This file also holds the operand table. All knowledge about | |
35 | inserting operands into instructions and vice-versa is kept in this | |
36 | file. */ | |
252b5132 | 37 | |
b80c7270 | 38 | /* The functions used to insert and extract complicated operands. */ |
252b5132 | 39 | |
b80c7270 | 40 | /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ |
252b5132 | 41 | |
0f873fd5 PB |
42 | static uint64_t |
43 | insert_arx (uint64_t insn, | |
44 | int64_t value, | |
b80c7270 AM |
45 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
46 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 47 | { |
71553718 AM |
48 | value -= 8; |
49 | if (value < 0 || value >= 16) | |
b80c7270 AM |
50 | { |
51 | *errmsg = _("invalid register"); | |
71553718 | 52 | value = 0xf; |
b80c7270 | 53 | } |
71553718 | 54 | return insn | value; |
b80c7270 | 55 | } |
b9c361e0 | 56 | |
0f873fd5 PB |
57 | static int64_t |
58 | extract_arx (uint64_t insn, | |
b80c7270 AM |
59 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
60 | int *invalid ATTRIBUTE_UNUSED) | |
61 | { | |
62 | return (insn & 0xf) + 8; | |
63 | } | |
b9c361e0 | 64 | |
0f873fd5 PB |
65 | static uint64_t |
66 | insert_ary (uint64_t insn, | |
67 | int64_t value, | |
b80c7270 AM |
68 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
69 | const char **errmsg ATTRIBUTE_UNUSED) | |
70 | { | |
71553718 AM |
71 | value -= 8; |
72 | if (value < 0 || value >= 16) | |
b80c7270 AM |
73 | { |
74 | *errmsg = _("invalid register"); | |
71553718 | 75 | value = 0xf; |
b80c7270 | 76 | } |
71553718 | 77 | return insn | (value << 4); |
b80c7270 | 78 | } |
23976049 | 79 | |
0f873fd5 PB |
80 | static int64_t |
81 | extract_ary (uint64_t insn, | |
b80c7270 AM |
82 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
83 | int *invalid ATTRIBUTE_UNUSED) | |
84 | { | |
85 | return ((insn >> 4) & 0xf) + 8; | |
86 | } | |
418c1742 | 87 | |
0f873fd5 PB |
88 | static uint64_t |
89 | insert_rx (uint64_t insn, | |
90 | int64_t value, | |
b80c7270 AM |
91 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
92 | const char **errmsg) | |
93 | { | |
94 | if (value >= 0 && value < 8) | |
71553718 | 95 | ; |
b80c7270 | 96 | else if (value >= 24 && value <= 31) |
71553718 | 97 | value -= 16; |
b80c7270 AM |
98 | else |
99 | { | |
100 | *errmsg = _("invalid register"); | |
71553718 | 101 | value = 0xf; |
b80c7270 | 102 | } |
71553718 | 103 | return insn | value; |
b80c7270 | 104 | } |
252b5132 | 105 | |
0f873fd5 PB |
106 | static int64_t |
107 | extract_rx (uint64_t insn, | |
b80c7270 AM |
108 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
109 | int *invalid ATTRIBUTE_UNUSED) | |
110 | { | |
0f873fd5 | 111 | int64_t value = insn & 0xf; |
b80c7270 AM |
112 | if (value >= 0 && value < 8) |
113 | return value; | |
114 | else | |
115 | return value + 16; | |
116 | } | |
b9c361e0 | 117 | |
0f873fd5 PB |
118 | static uint64_t |
119 | insert_ry (uint64_t insn, | |
120 | int64_t value, | |
b80c7270 AM |
121 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
122 | const char **errmsg) | |
123 | { | |
124 | if (value >= 0 && value < 8) | |
71553718 | 125 | ; |
b80c7270 | 126 | else if (value >= 24 && value <= 31) |
71553718 | 127 | value -= 16; |
b80c7270 AM |
128 | else |
129 | { | |
130 | *errmsg = _("invalid register"); | |
71553718 | 131 | value = 0xf; |
b80c7270 | 132 | } |
71553718 | 133 | return insn | (value << 4); |
b80c7270 | 134 | } |
a680de9a | 135 | |
0f873fd5 PB |
136 | static int64_t |
137 | extract_ry (uint64_t insn, | |
b80c7270 AM |
138 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
139 | int *invalid ATTRIBUTE_UNUSED) | |
140 | { | |
0f873fd5 | 141 | int64_t value = (insn >> 4) & 0xf; |
b80c7270 AM |
142 | if (value >= 0 && value < 8) |
143 | return value; | |
144 | else | |
145 | return value + 16; | |
146 | } | |
a680de9a | 147 | |
98553ad3 PB |
148 | /* The BA and BB fields in an XL form instruction or the RA and RB fields or |
149 | VRA and VRB fields in a VX form instruction when they must be the same. | |
150 | This is used for extended mnemonics like crclr. The extraction function | |
151 | enforces that the fields are the same. */ | |
adadcc0c | 152 | |
0f873fd5 | 153 | static uint64_t |
98553ad3 PB |
154 | insert_bab (uint64_t insn, |
155 | int64_t value, | |
b80c7270 AM |
156 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
157 | const char **errmsg ATTRIBUTE_UNUSED) | |
158 | { | |
98553ad3 PB |
159 | value &= 0x1f; |
160 | return insn | (value << 16) | (value << 11); | |
b80c7270 | 161 | } |
252b5132 | 162 | |
0f873fd5 | 163 | static int64_t |
98553ad3 | 164 | extract_bab (uint64_t insn, |
b80c7270 AM |
165 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
166 | int *invalid) | |
167 | { | |
98553ad3 PB |
168 | int64_t ba = (insn >> 16) & 0x1f; |
169 | int64_t bb = (insn >> 11) & 0x1f; | |
170 | ||
171 | if (ba != bb) | |
b80c7270 | 172 | *invalid = 1; |
98553ad3 | 173 | return ba; |
b80c7270 | 174 | } |
19a6653c | 175 | |
98553ad3 PB |
176 | /* The BT, BA and BB fields in an XL form instruction when they must all be |
177 | the same. This is used for extended mnemonics like crclr. The extraction | |
178 | function enforces that the fields are the same. */ | |
a680de9a | 179 | |
0f873fd5 | 180 | static uint64_t |
98553ad3 PB |
181 | insert_btab (uint64_t insn, |
182 | int64_t value, | |
183 | ppc_cpu_t dialect, | |
184 | const char **errmsg) | |
b80c7270 | 185 | { |
98553ad3 PB |
186 | value &= 0x1f; |
187 | return (value << 21) | insert_bab (insn, value, dialect, errmsg); | |
b80c7270 | 188 | } |
a680de9a | 189 | |
0f873fd5 | 190 | static int64_t |
98553ad3 PB |
191 | extract_btab (uint64_t insn, |
192 | ppc_cpu_t dialect, | |
b80c7270 AM |
193 | int *invalid) |
194 | { | |
98553ad3 PB |
195 | int64_t bt = (insn >> 21) & 0x1f; |
196 | int64_t bab = extract_bab (insn, dialect, invalid); | |
197 | ||
198 | if (bt != bab) | |
b80c7270 | 199 | *invalid = 1; |
98553ad3 | 200 | return bt; |
b80c7270 | 201 | } |
252b5132 | 202 | |
b80c7270 AM |
203 | /* The BD field in a B form instruction when the - modifier is used. |
204 | This modifier means that the branch is not expected to be taken. | |
205 | For chips built to versions of the architecture prior to version 2 | |
206 | (ie. not Power4 compatible), we set the y bit of the BO field to 1 | |
207 | if the offset is negative. When extracting, we require that the y | |
208 | bit be 1 and that the offset be positive, since if the y bit is 0 | |
209 | we just want to print the normal form of the instruction. | |
210 | Power4 compatible targets use two bits, "a", and "t", instead of | |
211 | the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, | |
212 | "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 | |
213 | in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 | |
214 | for branch on CTR. We only handle the taken/not-taken hint here. | |
215 | Note that we don't relax the conditions tested here when | |
216 | disassembling with -Many because insns using extract_bdm and | |
217 | extract_bdp always occur in pairs. One or the other will always | |
218 | be valid. */ | |
252b5132 | 219 | |
b80c7270 | 220 | #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
252b5132 | 221 | |
0f873fd5 PB |
222 | static uint64_t |
223 | insert_bdm (uint64_t insn, | |
224 | int64_t value, | |
b80c7270 AM |
225 | ppc_cpu_t dialect, |
226 | const char **errmsg ATTRIBUTE_UNUSED) | |
227 | { | |
228 | if ((dialect & ISA_V2) == 0) | |
229 | { | |
230 | if ((value & 0x8000) != 0) | |
231 | insn |= 1 << 21; | |
232 | } | |
233 | else | |
234 | { | |
235 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
236 | insn |= 0x02 << 21; | |
237 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
238 | insn |= 0x08 << 21; | |
239 | } | |
240 | return insn | (value & 0xfffc); | |
241 | } | |
252b5132 | 242 | |
0f873fd5 PB |
243 | static int64_t |
244 | extract_bdm (uint64_t insn, | |
b80c7270 AM |
245 | ppc_cpu_t dialect, |
246 | int *invalid) | |
247 | { | |
248 | if ((dialect & ISA_V2) == 0) | |
249 | { | |
250 | if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) | |
251 | *invalid = 1; | |
252 | } | |
253 | else | |
254 | { | |
255 | if ((insn & (0x17 << 21)) != (0x06 << 21) | |
256 | && (insn & (0x1d << 21)) != (0x18 << 21)) | |
257 | *invalid = 1; | |
258 | } | |
252b5132 | 259 | |
b80c7270 AM |
260 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
261 | } | |
989993d8 | 262 | |
b80c7270 AM |
263 | /* The BD field in a B form instruction when the + modifier is used. |
264 | This is like BDM, above, except that the branch is expected to be | |
265 | taken. */ | |
252b5132 | 266 | |
0f873fd5 PB |
267 | static uint64_t |
268 | insert_bdp (uint64_t insn, | |
269 | int64_t value, | |
b80c7270 AM |
270 | ppc_cpu_t dialect, |
271 | const char **errmsg ATTRIBUTE_UNUSED) | |
272 | { | |
273 | if ((dialect & ISA_V2) == 0) | |
274 | { | |
275 | if ((value & 0x8000) == 0) | |
276 | insn |= 1 << 21; | |
277 | } | |
278 | else | |
279 | { | |
280 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
281 | insn |= 0x03 << 21; | |
282 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
283 | insn |= 0x09 << 21; | |
284 | } | |
285 | return insn | (value & 0xfffc); | |
286 | } | |
989993d8 | 287 | |
0f873fd5 PB |
288 | static int64_t |
289 | extract_bdp (uint64_t insn, | |
b80c7270 AM |
290 | ppc_cpu_t dialect, |
291 | int *invalid) | |
292 | { | |
293 | if ((dialect & ISA_V2) == 0) | |
294 | { | |
295 | if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) | |
296 | *invalid = 1; | |
297 | } | |
298 | else | |
299 | { | |
300 | if ((insn & (0x17 << 21)) != (0x07 << 21) | |
301 | && (insn & (0x1d << 21)) != (0x19 << 21)) | |
302 | *invalid = 1; | |
303 | } | |
252b5132 | 304 | |
b80c7270 AM |
305 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
306 | } | |
252b5132 | 307 | |
b80c7270 | 308 | static inline int |
0f873fd5 | 309 | valid_bo_pre_v2 (int64_t value) |
b80c7270 AM |
310 | { |
311 | /* Certain encodings have bits that are required to be zero. | |
312 | These are (z must be zero, y may be anything): | |
313 | 0000y | |
314 | 0001y | |
315 | 001zy | |
316 | 0100y | |
317 | 0101y | |
318 | 011zy | |
319 | 1z00y | |
320 | 1z01y | |
321 | 1z1zz | |
322 | */ | |
323 | if ((value & 0x14) == 0) | |
aae9718e | 324 | /* BO: 0000y, 0001y, 0100y, 0101y. */ |
b80c7270 AM |
325 | return 1; |
326 | else if ((value & 0x14) == 0x4) | |
aae9718e | 327 | /* BO: 001zy, 011zy. */ |
b80c7270 AM |
328 | return (value & 0x2) == 0; |
329 | else if ((value & 0x14) == 0x10) | |
aae9718e | 330 | /* BO: 1z00y, 1z01y. */ |
b80c7270 AM |
331 | return (value & 0x8) == 0; |
332 | else | |
aae9718e | 333 | /* BO: 1z1zz. */ |
b80c7270 AM |
334 | return value == 0x14; |
335 | } | |
989993d8 | 336 | |
b80c7270 | 337 | static inline int |
0f873fd5 | 338 | valid_bo_post_v2 (int64_t value) |
b80c7270 AM |
339 | { |
340 | /* Certain encodings have bits that are required to be zero. | |
341 | These are (z must be zero, a & t may be anything): | |
342 | 0000z | |
343 | 0001z | |
344 | 001at | |
345 | 0100z | |
346 | 0101z | |
347 | 011at | |
348 | 1a00t | |
349 | 1a01t | |
350 | 1z1zz | |
351 | */ | |
352 | if ((value & 0x14) == 0) | |
aae9718e | 353 | /* BO: 0000z, 0001z, 0100z, 0101z. */ |
b80c7270 AM |
354 | return (value & 0x1) == 0; |
355 | else if ((value & 0x14) == 0x14) | |
aae9718e | 356 | /* BO: 1z1zz. */ |
b80c7270 | 357 | return value == 0x14; |
aae9718e PB |
358 | else if ((value & 0x14) == 0x4) |
359 | /* BO: 001at, 011at, with "at" == 0b01 being reserved. */ | |
360 | return (value & 0x3) != 1; | |
361 | else if ((value & 0x14) == 0x10) | |
362 | /* BO: 1a00t, 1a01t, with "at" == 0b01 being reserved. */ | |
363 | return (value & 0x9) != 1; | |
b80c7270 AM |
364 | else |
365 | return 1; | |
366 | } | |
c168870a | 367 | |
b80c7270 | 368 | /* Check for legal values of a BO field. */ |
252b5132 | 369 | |
b80c7270 | 370 | static int |
0f873fd5 | 371 | valid_bo (int64_t value, ppc_cpu_t dialect, int extract) |
b80c7270 AM |
372 | { |
373 | int valid_y = valid_bo_pre_v2 (value); | |
374 | int valid_at = valid_bo_post_v2 (value); | |
b9c361e0 | 375 | |
b80c7270 AM |
376 | /* When disassembling with -Many, accept either encoding on the |
377 | second pass through opcodes. */ | |
378 | if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) | |
379 | return valid_y || valid_at; | |
380 | if ((dialect & ISA_V2) == 0) | |
381 | return valid_y; | |
382 | else | |
383 | return valid_at; | |
384 | } | |
a5721ba2 | 385 | |
b80c7270 AM |
386 | /* The BO field in a B form instruction. Warn about attempts to set |
387 | the field to an illegal value. */ | |
252b5132 | 388 | |
0f873fd5 PB |
389 | static uint64_t |
390 | insert_bo (uint64_t insn, | |
391 | int64_t value, | |
b80c7270 AM |
392 | ppc_cpu_t dialect, |
393 | const char **errmsg) | |
394 | { | |
395 | if (!valid_bo (value, dialect, 0)) | |
396 | *errmsg = _("invalid conditional option"); | |
aae9718e PB |
397 | else if (PPC_OP (insn) == 19 |
398 | && (((insn >> 1) & 0x3ff) == 528) && ! (value & 4)) | |
b80c7270 AM |
399 | *errmsg = _("invalid counter access"); |
400 | return insn | ((value & 0x1f) << 21); | |
401 | } | |
a680de9a | 402 | |
0f873fd5 PB |
403 | static int64_t |
404 | extract_bo (uint64_t insn, | |
b80c7270 AM |
405 | ppc_cpu_t dialect, |
406 | int *invalid) | |
407 | { | |
0f873fd5 | 408 | int64_t value = (insn >> 21) & 0x1f; |
b80c7270 AM |
409 | if (!valid_bo (value, dialect, 1)) |
410 | *invalid = 1; | |
411 | return value; | |
412 | } | |
252b5132 | 413 | |
aae9718e PB |
414 | /* For the given BO value, return a bit mask detailing which bits |
415 | define the branch hints. */ | |
416 | ||
417 | static int64_t | |
418 | get_bo_hint_mask (int64_t bo, ppc_cpu_t dialect) | |
419 | { | |
420 | if ((dialect & ISA_V2) == 0) | |
421 | { | |
422 | if ((bo & 0x14) != 0x14) | |
423 | /* BO: 0000y, 0001y, 001zy, 0100y, 0101y, 011zy, 1z00y, 1z01y . */ | |
424 | return 1; | |
425 | else | |
426 | /* BO: 1z1zz. */ | |
427 | return 0; | |
428 | } | |
429 | else | |
430 | { | |
431 | if ((bo & 0x14) == 0x4) | |
432 | /* BO: 001at, 011at. */ | |
433 | return 0x3; | |
434 | else if ((bo & 0x14) == 0x10) | |
435 | /* BO: 1a00t, 1a01t. */ | |
436 | return 0x9; | |
437 | else | |
438 | /* BO: 0000z, 0001z, 0100z, 0101z, 1z1zz. */ | |
439 | return 0; | |
440 | } | |
441 | } | |
442 | ||
443 | /* The BO field in a B form instruction when the + or - modifier is used. */ | |
1ed8e1e4 | 444 | |
0f873fd5 PB |
445 | static uint64_t |
446 | insert_boe (uint64_t insn, | |
447 | int64_t value, | |
b80c7270 | 448 | ppc_cpu_t dialect, |
aae9718e PB |
449 | const char **errmsg, |
450 | int branch_taken) | |
b80c7270 | 451 | { |
aae9718e PB |
452 | int64_t implied_hint; |
453 | int64_t hint_mask = get_bo_hint_mask (value, dialect); | |
252b5132 | 454 | |
aae9718e PB |
455 | if (branch_taken) |
456 | implied_hint = hint_mask; | |
457 | else | |
458 | implied_hint = hint_mask & ~1; | |
459 | ||
460 | /* The branch hint bit(s) in the BO field must either be zero or exactly | |
461 | match the branch hint bits implied by the '+' or '-' modifier. */ | |
462 | if (implied_hint == 0) | |
463 | *errmsg = _("BO value implies no branch hint, when using + or - modifier"); | |
464 | else if ((value & hint_mask) != 0 | |
465 | && (value & hint_mask) != implied_hint) | |
466 | { | |
467 | if ((dialect & ISA_V2) == 0) | |
468 | *errmsg = _("attempt to set y bit when using + or - modifier"); | |
469 | else | |
470 | *errmsg = _("attempt to set 'at' bits when using + or - modifier"); | |
471 | } | |
472 | ||
473 | value |= implied_hint; | |
474 | ||
475 | return insert_bo (insn, value, dialect, errmsg); | |
b80c7270 | 476 | } |
252b5132 | 477 | |
0f873fd5 PB |
478 | static int64_t |
479 | extract_boe (uint64_t insn, | |
b80c7270 | 480 | ppc_cpu_t dialect, |
aae9718e PB |
481 | int *invalid, |
482 | int branch_taken) | |
b80c7270 | 483 | { |
0f873fd5 | 484 | int64_t value = (insn >> 21) & 0x1f; |
aae9718e PB |
485 | int64_t implied_hint; |
486 | int64_t hint_mask = get_bo_hint_mask (value, dialect); | |
487 | ||
488 | if (branch_taken) | |
489 | implied_hint = hint_mask; | |
490 | else | |
491 | implied_hint = hint_mask & ~1; | |
492 | ||
493 | if (!valid_bo (value, dialect, 1) | |
494 | || implied_hint == 0 | |
495 | || (value & hint_mask) != implied_hint) | |
b80c7270 | 496 | *invalid = 1; |
aae9718e PB |
497 | return value; |
498 | } | |
499 | ||
500 | /* The BO field in a B form instruction when the - modifier is used. */ | |
501 | ||
502 | static uint64_t | |
503 | insert_bom (uint64_t insn, | |
504 | int64_t value, | |
505 | ppc_cpu_t dialect, | |
506 | const char **errmsg) | |
507 | { | |
508 | return insert_boe (insn, value, dialect, errmsg, 0); | |
509 | } | |
510 | ||
511 | static int64_t | |
512 | extract_bom (uint64_t insn, | |
513 | ppc_cpu_t dialect, | |
514 | int *invalid) | |
515 | { | |
516 | return extract_boe (insn, dialect, invalid, 0); | |
517 | } | |
518 | ||
519 | /* The BO field in a B form instruction when the + modifier is used. */ | |
520 | ||
521 | static uint64_t | |
522 | insert_bop (uint64_t insn, | |
523 | int64_t value, | |
524 | ppc_cpu_t dialect, | |
525 | const char **errmsg) | |
526 | { | |
527 | return insert_boe (insn, value, dialect, errmsg, 1); | |
528 | } | |
529 | ||
530 | static int64_t | |
531 | extract_bop (uint64_t insn, | |
532 | ppc_cpu_t dialect, | |
533 | int *invalid) | |
534 | { | |
535 | return extract_boe (insn, dialect, invalid, 1); | |
b80c7270 | 536 | } |
252b5132 | 537 | |
b80c7270 AM |
538 | /* The DCMX field in a X form instruction when the field is split |
539 | into separate DC, DM and DX fields. */ | |
252b5132 | 540 | |
0f873fd5 PB |
541 | static uint64_t |
542 | insert_dcmxs (uint64_t insn, | |
543 | int64_t value, | |
b80c7270 AM |
544 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
545 | const char **errmsg ATTRIBUTE_UNUSED) | |
546 | { | |
547 | return (insn | |
548 | | ((value & 0x1f) << 16) | |
549 | | ((value & 0x20) >> 3) | |
550 | | (value & 0x40)); | |
551 | } | |
252b5132 | 552 | |
0f873fd5 PB |
553 | static int64_t |
554 | extract_dcmxs (uint64_t insn, | |
b80c7270 AM |
555 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
556 | int *invalid ATTRIBUTE_UNUSED) | |
557 | { | |
558 | return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); | |
559 | } | |
252b5132 | 560 | |
b80c7270 AM |
561 | /* The D field in a DX form instruction when the field is split |
562 | into separate D0, D1 and D2 fields. */ | |
989993d8 | 563 | |
0f873fd5 PB |
564 | static uint64_t |
565 | insert_dxd (uint64_t insn, | |
566 | int64_t value, | |
b80c7270 AM |
567 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
568 | const char **errmsg ATTRIBUTE_UNUSED) | |
569 | { | |
570 | return insn | (value & 0xffc1) | ((value & 0x3e) << 15); | |
571 | } | |
e43de63c | 572 | |
0f873fd5 PB |
573 | static int64_t |
574 | extract_dxd (uint64_t insn, | |
b80c7270 AM |
575 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
576 | int *invalid ATTRIBUTE_UNUSED) | |
577 | { | |
0f873fd5 | 578 | uint64_t dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); |
b80c7270 AM |
579 | return (dxd ^ 0x8000) - 0x8000; |
580 | } | |
252b5132 | 581 | |
0f873fd5 PB |
582 | static uint64_t |
583 | insert_dxdn (uint64_t insn, | |
584 | int64_t value, | |
b80c7270 AM |
585 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
586 | const char **errmsg ATTRIBUTE_UNUSED) | |
587 | { | |
588 | return insert_dxd (insn, -value, dialect, errmsg); | |
589 | } | |
252b5132 | 590 | |
0f873fd5 PB |
591 | static int64_t |
592 | extract_dxdn (uint64_t insn, | |
b80c7270 | 593 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
9cf7e568 | 594 | int *invalid) |
b80c7270 AM |
595 | { |
596 | return -extract_dxd (insn, dialect, invalid); | |
597 | } | |
fdd12ef3 | 598 | |
8acf1435 PB |
599 | /* The D field in a 64-bit D form prefix instruction when the field is split |
600 | into separate D0 and D1 fields. */ | |
601 | ||
602 | static uint64_t | |
603 | insert_d34 (uint64_t insn, | |
604 | int64_t value, | |
605 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
606 | const char **errmsg ATTRIBUTE_UNUSED) | |
607 | { | |
608 | return insn | ((value & 0x3ffff0000ULL) << 16) | (value & 0xffff); | |
609 | } | |
610 | ||
611 | static int64_t | |
612 | extract_d34 (uint64_t insn, | |
613 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
614 | int *invalid ATTRIBUTE_UNUSED) | |
615 | { | |
616 | int64_t mask = 1ULL << 33; | |
617 | int64_t value = ((insn >> 16) & 0x3ffff0000ULL) | (insn & 0xffff); | |
618 | value = (value ^ mask) - mask; | |
619 | return value; | |
620 | } | |
621 | ||
622 | /* The NSI34 field in an 8-byte D form prefix instruction. This is the same | |
623 | as the SI34 field, only negated. The extraction function always marks it | |
624 | as invalid, since we never want to recognize an instruction which uses | |
625 | a field of this type. */ | |
626 | ||
627 | static uint64_t | |
628 | insert_nsi34 (uint64_t insn, | |
629 | int64_t value, | |
630 | ppc_cpu_t dialect, | |
631 | const char **errmsg) | |
632 | { | |
633 | return insert_d34 (insn, -value, dialect, errmsg); | |
634 | } | |
635 | ||
636 | static int64_t | |
637 | extract_nsi34 (uint64_t insn, | |
638 | ppc_cpu_t dialect, | |
639 | int *invalid) | |
640 | { | |
641 | int64_t value = extract_d34 (insn, dialect, invalid); | |
642 | *invalid = 1; | |
643 | return -value; | |
644 | } | |
645 | ||
6edbfd3b AM |
646 | /* The split IMM32 field in a vector splat insn. */ |
647 | ||
648 | static uint64_t | |
649 | insert_imm32 (uint64_t insn, | |
650 | int64_t value, | |
651 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
652 | const char **errmsg ATTRIBUTE_UNUSED) | |
653 | { | |
654 | return insn | ((value & 0xffff0000) << 16) | (value & 0xffff); | |
655 | } | |
656 | ||
657 | static int64_t | |
658 | extract_imm32 (uint64_t insn, | |
659 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
660 | int *invalid ATTRIBUTE_UNUSED) | |
661 | { | |
662 | return (insn & 0xffff) | ((insn >> 16) & 0xffff0000); | |
663 | } | |
664 | ||
8acf1435 PB |
665 | /* The R field in an 8-byte prefix instruction when there are restrictions |
666 | between R's value and the RA value (ie, they cannot both be non zero). */ | |
667 | ||
668 | static uint64_t | |
669 | insert_pcrel (uint64_t insn, | |
670 | int64_t value, | |
671 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
672 | const char **errmsg) | |
673 | { | |
674 | value &= 0x1; | |
675 | int64_t ra = (insn >> 16) & 0x1f; | |
676 | if (ra != 0 && value != 0) | |
677 | *errmsg = _("invalid R operand"); | |
678 | ||
679 | return insn | (value << 52); | |
680 | } | |
681 | ||
682 | static int64_t | |
683 | extract_pcrel (uint64_t insn, | |
684 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
685 | int *invalid) | |
686 | { | |
687 | /* If called with *invalid < 0 to return the value for missing | |
688 | operands, *invalid will be the negative count of missing operands | |
689 | including this one. Return a default value of 1 if the PRA0/PRAQ | |
690 | operand was also omitted (ie. *invalid is -2). Return a default | |
691 | value of 0 if the PRA0/PRAQ operand was not omitted | |
692 | (ie. *invalid is -1). */ | |
693 | if (*invalid < 0) | |
694 | return ~ *invalid & 1; | |
695 | ||
696 | int64_t ra = (insn >> 16) & 0x1f; | |
697 | int64_t pcrel = (insn >> 52) & 0x1; | |
698 | if (ra != 0 && pcrel != 0) | |
699 | *invalid = 1; | |
700 | ||
701 | return pcrel; | |
702 | } | |
703 | ||
704 | /* Variant of extract_pcrel that sets invalid for R bit set. The idea | |
705 | is to disassemble "paddi rt,0,offset,1" as "pla rt,offset". */ | |
706 | ||
707 | static int64_t | |
708 | extract_pcrel0 (uint64_t insn, | |
709 | ppc_cpu_t dialect, | |
710 | int *invalid) | |
711 | { | |
712 | int64_t pcrel = extract_pcrel (insn, dialect, invalid); | |
713 | if (pcrel) | |
714 | *invalid = 1; | |
715 | return pcrel; | |
716 | } | |
717 | ||
b80c7270 | 718 | /* FXM mask in mfcr and mtcrf instructions. */ |
adadcc0c | 719 | |
0f873fd5 PB |
720 | static uint64_t |
721 | insert_fxm (uint64_t insn, | |
722 | int64_t value, | |
b80c7270 AM |
723 | ppc_cpu_t dialect, |
724 | const char **errmsg) | |
725 | { | |
726 | /* If we're handling the mfocrf and mtocrf insns ensure that exactly | |
727 | one bit of the mask field is set. */ | |
728 | if ((insn & (1 << 20)) != 0) | |
729 | { | |
730 | if (value == 0 || (value & -value) != value) | |
731 | { | |
732 | *errmsg = _("invalid mask field"); | |
733 | value = 0; | |
734 | } | |
735 | } | |
252b5132 | 736 | |
b80c7270 AM |
737 | /* If only one bit of the FXM field is set, we can use the new form |
738 | of the instruction, which is faster. Unlike the Power4 branch hint | |
739 | encoding, this is not backward compatible. Do not generate the | |
740 | new form unless -mpower4 has been given, or -many and the two | |
741 | operand form of mfcr was used. */ | |
742 | else if (value > 0 | |
743 | && (value & -value) == value | |
744 | && ((dialect & PPC_OPCODE_POWER4) != 0 | |
745 | || ((dialect & PPC_OPCODE_ANY) != 0 | |
746 | && (insn & (0x3ff << 1)) == 19 << 1))) | |
747 | insn |= 1 << 20; | |
252b5132 | 748 | |
b80c7270 AM |
749 | /* Any other value on mfcr is an error. */ |
750 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
751 | { | |
752 | /* A value of -1 means we used the one operand form of | |
753 | mfcr which is valid. */ | |
754 | if (value != -1) | |
755 | *errmsg = _("invalid mfcr mask"); | |
756 | value = 0; | |
757 | } | |
252b5132 | 758 | |
b80c7270 AM |
759 | return insn | ((value & 0xff) << 12); |
760 | } | |
1f6c9eb0 | 761 | |
0f873fd5 PB |
762 | static int64_t |
763 | extract_fxm (uint64_t insn, | |
b80c7270 AM |
764 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
765 | int *invalid) | |
766 | { | |
9cf7e568 AM |
767 | /* Return a value of -1 for a missing optional operand, which is |
768 | used as a flag by insert_fxm. */ | |
769 | if (*invalid < 0) | |
770 | return -1; | |
252b5132 | 771 | |
9cf7e568 | 772 | int64_t mask = (insn >> 12) & 0xff; |
b80c7270 AM |
773 | /* Is this a Power4 insn? */ |
774 | if ((insn & (1 << 20)) != 0) | |
775 | { | |
776 | /* Exactly one bit of MASK should be set. */ | |
777 | if (mask == 0 || (mask & -mask) != mask) | |
778 | *invalid = 1; | |
779 | } | |
252b5132 | 780 | |
b80c7270 AM |
781 | /* Check that non-power4 form of mfcr has a zero MASK. */ |
782 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
783 | { | |
784 | if (mask != 0) | |
785 | *invalid = 1; | |
786 | else | |
787 | mask = -1; | |
788 | } | |
989993d8 | 789 | |
b80c7270 AM |
790 | return mask; |
791 | } | |
cee62821 | 792 | |
afef4fe9 PB |
793 | /* L field in the paste. instruction. */ |
794 | ||
795 | static uint64_t | |
796 | insert_l1opt (uint64_t insn, | |
797 | int64_t value, | |
798 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
799 | const char **errmsg ATTRIBUTE_UNUSED) | |
800 | { | |
801 | return insn | ((value & 1) << 21); | |
802 | } | |
803 | ||
804 | static int64_t | |
805 | extract_l1opt (uint64_t insn, | |
806 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
807 | int *invalid) | |
808 | { | |
809 | /* Return a value of 1 for a missing optional operand. */ | |
810 | if (*invalid < 0) | |
811 | return 1; | |
812 | ||
813 | return (insn >> 21) & 1; | |
814 | } | |
815 | ||
0f873fd5 PB |
816 | static uint64_t |
817 | insert_li20 (uint64_t insn, | |
818 | int64_t value, | |
b80c7270 AM |
819 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
820 | const char **errmsg ATTRIBUTE_UNUSED) | |
821 | { | |
822 | return (insn | |
823 | | ((value & 0xf0000) >> 5) | |
824 | | ((value & 0x0f800) << 5) | |
825 | | (value & 0x7ff)); | |
826 | } | |
a680de9a | 827 | |
0f873fd5 PB |
828 | static int64_t |
829 | extract_li20 (uint64_t insn, | |
b80c7270 AM |
830 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
831 | int *invalid ATTRIBUTE_UNUSED) | |
832 | { | |
f143cb5f AM |
833 | return ((((insn << 5) & 0xf0000) |
834 | | ((insn >> 5) & 0xf800) | |
835 | | (insn & 0x7ff)) ^ 0x80000) - 0x80000; | |
b80c7270 | 836 | } |
e3c2f928 | 837 | |
3d205eb4 | 838 | /* The 2-bit/3-bit L or 2-bit WC field in a SYNC, DCBF or WAIT instruction. |
b80c7270 | 839 | For SYNC, some L values are reserved: |
3d205eb4 PB |
840 | * Values 6 and 7 are reserved on newer server cpus. |
841 | * Value 3 is reserved on all server cpus. | |
842 | * Value 2 is reserved on all other cpus. | |
843 | For DCBF, some L values are reserved: | |
844 | * Values 2, 5 and 7 are reserved on all cpus. | |
845 | For WAIT, some WC values are reserved: | |
846 | * Value 3 is reserved on all server cpus. | |
847 | * Values 1 and 2 are reserved on older server cpus. */ | |
adadcc0c | 848 | |
0f873fd5 PB |
849 | static uint64_t |
850 | insert_ls (uint64_t insn, | |
851 | int64_t value, | |
b80c7270 AM |
852 | ppc_cpu_t dialect, |
853 | const char **errmsg) | |
854 | { | |
3d205eb4 PB |
855 | int64_t mask; |
856 | ||
b80c7270 AM |
857 | if (((insn >> 1) & 0x3ff) == 598) |
858 | { | |
3d205eb4 PB |
859 | /* For SYNC, some L values are illegal. */ |
860 | mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; | |
861 | ||
862 | /* If the value is within range, check for other illegal values. */ | |
863 | if ((value & mask) == value) | |
864 | switch (value) | |
865 | { | |
866 | case 2: | |
867 | if (dialect & PPC_OPCODE_POWER4) | |
868 | break; | |
869 | /* Fall through. */ | |
870 | case 3: | |
871 | case 6: | |
872 | case 7: | |
873 | *errmsg = _("illegal L operand value"); | |
874 | break; | |
875 | default: | |
876 | break; | |
877 | } | |
878 | } | |
879 | else if (((insn >> 1) & 0x3ff) == 86) | |
880 | { | |
881 | /* For DCBF, some L values are illegal. */ | |
882 | mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; | |
883 | ||
884 | /* If the value is within range, check for other illegal values. */ | |
885 | if ((value & mask) == value) | |
886 | switch (value) | |
887 | { | |
888 | case 2: | |
889 | case 5: | |
890 | case 7: | |
891 | *errmsg = _("illegal L operand value"); | |
892 | break; | |
893 | default: | |
894 | break; | |
895 | } | |
896 | } | |
897 | else | |
898 | { | |
899 | /* For WAIT, some WC values are illegal. */ | |
900 | mask = 0x3; | |
901 | ||
902 | /* If the value is within range, check for other illegal values. */ | |
903 | if ((dialect & PPC_OPCODE_A2) == 0 | |
904 | && (dialect & PPC_OPCODE_E500MC) == 0 | |
905 | && (value & mask) == value) | |
906 | switch (value) | |
907 | { | |
908 | case 1: | |
909 | case 2: | |
910 | if (dialect & PPC_OPCODE_POWER10) | |
911 | break; | |
912 | /* Fall through. */ | |
913 | case 3: | |
914 | *errmsg = _("illegal WC operand value"); | |
915 | break; | |
916 | default: | |
917 | break; | |
918 | } | |
b80c7270 | 919 | } |
1f6c9eb0 | 920 | |
3d205eb4 | 921 | return insn | ((value & mask) << 21); |
b80c7270 | 922 | } |
b9c361e0 | 923 | |
0f873fd5 PB |
924 | static int64_t |
925 | extract_ls (uint64_t insn, | |
b80c7270 AM |
926 | ppc_cpu_t dialect, |
927 | int *invalid) | |
928 | { | |
3d205eb4 PB |
929 | uint64_t value; |
930 | ||
9cf7e568 AM |
931 | /* Missing optional operands have a value of zero. */ |
932 | if (*invalid < 0) | |
933 | return 0; | |
b9c361e0 | 934 | |
b80c7270 AM |
935 | if (((insn >> 1) & 0x3ff) == 598) |
936 | { | |
3d205eb4 PB |
937 | /* For SYNC, some L values are illegal. */ |
938 | int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; | |
939 | ||
940 | value = (insn >> 21) & mask; | |
941 | switch (value) | |
942 | { | |
943 | case 2: | |
944 | if (dialect & PPC_OPCODE_POWER4) | |
945 | break; | |
946 | /* Fall through. */ | |
947 | case 3: | |
948 | case 6: | |
949 | case 7: | |
950 | *invalid = 1; | |
951 | break; | |
952 | default: | |
953 | break; | |
954 | } | |
955 | } | |
956 | else if (((insn >> 1) & 0x3ff) == 86) | |
957 | { | |
958 | /* For DCBF, some L values are illegal. */ | |
959 | int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; | |
960 | ||
961 | value = (insn >> 21) & mask; | |
962 | switch (value) | |
963 | { | |
964 | case 2: | |
965 | case 5: | |
966 | case 7: | |
967 | *invalid = 1; | |
968 | break; | |
969 | default: | |
970 | break; | |
971 | } | |
b80c7270 | 972 | } |
3d205eb4 PB |
973 | else |
974 | { | |
975 | /* For WAIT, some WC values are illegal. */ | |
976 | value = (insn >> 21) & 0x3; | |
977 | if ((dialect & PPC_OPCODE_A2) == 0 | |
978 | && (dialect & PPC_OPCODE_E500MC) == 0) | |
979 | switch (value) | |
980 | { | |
981 | case 1: | |
982 | case 2: | |
983 | if (dialect & PPC_OPCODE_POWER10) | |
984 | break; | |
985 | /* Fall through. */ | |
986 | case 3: | |
987 | *invalid = 1; | |
988 | break; | |
989 | default: | |
990 | break; | |
991 | } | |
992 | } | |
993 | ||
994 | return value; | |
b80c7270 | 995 | } |
b9c361e0 | 996 | |
b80c7270 AM |
997 | /* The 4-bit E field in a sync instruction that accepts 2 operands. |
998 | If ESYNC is non-zero, then the L field must be either 0 or 1 and | |
999 | the complement of ESYNC-bit2. */ | |
b9c361e0 | 1000 | |
0f873fd5 PB |
1001 | static uint64_t |
1002 | insert_esync (uint64_t insn, | |
1003 | int64_t value, | |
9cf7e568 | 1004 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 AM |
1005 | const char **errmsg) |
1006 | { | |
0f873fd5 | 1007 | uint64_t ls = (insn >> 21) & 0x03; |
b9c361e0 | 1008 | |
9cf7e568 AM |
1009 | if (value != 0 |
1010 | && ((~value >> 1) & 0x1) != ls) | |
b80c7270 | 1011 | *errmsg = _("incompatible L operand value"); |
b9c361e0 | 1012 | |
b80c7270 AM |
1013 | return insn | ((value & 0xf) << 16); |
1014 | } | |
b9c361e0 | 1015 | |
0f873fd5 PB |
1016 | static int64_t |
1017 | extract_esync (uint64_t insn, | |
9cf7e568 | 1018 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 AM |
1019 | int *invalid) |
1020 | { | |
8acf1435 | 1021 | /* Missing optional operands have a value of zero. */ |
9cf7e568 AM |
1022 | if (*invalid < 0) |
1023 | return 0; | |
b9c361e0 | 1024 | |
9cf7e568 AM |
1025 | uint64_t ls = (insn >> 21) & 0x3; |
1026 | uint64_t value = (insn >> 16) & 0xf; | |
1027 | if (value != 0 | |
1028 | && ((~value >> 1) & 0x1) != ls) | |
b80c7270 | 1029 | *invalid = 1; |
9cf7e568 | 1030 | return value; |
b80c7270 | 1031 | } |
e3c2f928 | 1032 | |
b80c7270 AM |
1033 | /* The MB and ME fields in an M form instruction expressed as a single |
1034 | operand which is itself a bitmask. The extraction function always | |
1035 | marks it as invalid, since we never want to recognize an | |
1036 | instruction which uses a field of this type. */ | |
5817ffd1 | 1037 | |
0f873fd5 PB |
1038 | static uint64_t |
1039 | insert_mbe (uint64_t insn, | |
1040 | int64_t value, | |
b80c7270 AM |
1041 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1042 | const char **errmsg) | |
1043 | { | |
0f873fd5 PB |
1044 | uint64_t uval, mask; |
1045 | long mb, me, mx, count, last; | |
252b5132 | 1046 | |
b80c7270 | 1047 | uval = value; |
1f6c9eb0 | 1048 | |
b80c7270 AM |
1049 | if (uval == 0) |
1050 | { | |
1051 | *errmsg = _("illegal bitmask"); | |
1052 | return insn; | |
1053 | } | |
252b5132 | 1054 | |
b80c7270 AM |
1055 | mb = 0; |
1056 | me = 32; | |
1057 | if ((uval & 1) != 0) | |
1058 | last = 1; | |
1059 | else | |
1060 | last = 0; | |
1061 | count = 0; | |
252b5132 | 1062 | |
b80c7270 AM |
1063 | /* mb: location of last 0->1 transition */ |
1064 | /* me: location of last 1->0 transition */ | |
1065 | /* count: # transitions */ | |
b9c361e0 | 1066 | |
0f873fd5 | 1067 | for (mx = 0, mask = (uint64_t) 1 << 31; mx < 32; ++mx, mask >>= 1) |
b80c7270 AM |
1068 | { |
1069 | if ((uval & mask) && !last) | |
1070 | { | |
1071 | ++count; | |
1072 | mb = mx; | |
1073 | last = 1; | |
1074 | } | |
1075 | else if (!(uval & mask) && last) | |
1076 | { | |
1077 | ++count; | |
1078 | me = mx; | |
1079 | last = 0; | |
1080 | } | |
1081 | } | |
1082 | if (me == 0) | |
1083 | me = 32; | |
252b5132 | 1084 | |
b80c7270 AM |
1085 | if (count != 2 && (count != 0 || ! last)) |
1086 | *errmsg = _("illegal bitmask"); | |
252b5132 | 1087 | |
b80c7270 AM |
1088 | return insn | (mb << 6) | ((me - 1) << 1); |
1089 | } | |
252b5132 | 1090 | |
0f873fd5 PB |
1091 | static int64_t |
1092 | extract_mbe (uint64_t insn, | |
b80c7270 AM |
1093 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1094 | int *invalid) | |
1095 | { | |
0f873fd5 PB |
1096 | int64_t ret; |
1097 | long mb, me; | |
1098 | long i; | |
252b5132 | 1099 | |
b80c7270 | 1100 | *invalid = 1; |
f5c120c5 | 1101 | |
b80c7270 AM |
1102 | mb = (insn >> 6) & 0x1f; |
1103 | me = (insn >> 1) & 0x1f; | |
1104 | if (mb < me + 1) | |
1105 | { | |
1106 | ret = 0; | |
1107 | for (i = mb; i <= me; i++) | |
0f873fd5 | 1108 | ret |= (uint64_t) 1 << (31 - i); |
b80c7270 AM |
1109 | } |
1110 | else if (mb == me + 1) | |
1111 | ret = ~0; | |
1112 | else /* (mb > me + 1) */ | |
1113 | { | |
1114 | ret = ~0; | |
1115 | for (i = me + 1; i < mb; i++) | |
0f873fd5 | 1116 | ret &= ~((uint64_t) 1 << (31 - i)); |
b80c7270 AM |
1117 | } |
1118 | return ret; | |
1119 | } | |
aea77599 | 1120 | |
b80c7270 AM |
1121 | /* The MB or ME field in an MD or MDS form instruction. The high bit |
1122 | is wrapped to the low end. */ | |
252b5132 | 1123 | |
0f873fd5 PB |
1124 | static uint64_t |
1125 | insert_mb6 (uint64_t insn, | |
1126 | int64_t value, | |
b80c7270 AM |
1127 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1128 | const char **errmsg ATTRIBUTE_UNUSED) | |
1129 | { | |
1130 | return insn | ((value & 0x1f) << 6) | (value & 0x20); | |
1131 | } | |
252b5132 | 1132 | |
0f873fd5 PB |
1133 | static int64_t |
1134 | extract_mb6 (uint64_t insn, | |
b80c7270 AM |
1135 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1136 | int *invalid ATTRIBUTE_UNUSED) | |
1137 | { | |
1138 | return ((insn >> 6) & 0x1f) | (insn & 0x20); | |
1139 | } | |
252b5132 | 1140 | |
b80c7270 AM |
1141 | /* The NB field in an X form instruction. The value 32 is stored as |
1142 | 0. */ | |
786e2c0f | 1143 | |
0f873fd5 PB |
1144 | static int64_t |
1145 | extract_nb (uint64_t insn, | |
b80c7270 AM |
1146 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1147 | int *invalid ATTRIBUTE_UNUSED) | |
1148 | { | |
0f873fd5 | 1149 | int64_t ret; |
a47622ac | 1150 | |
b80c7270 AM |
1151 | ret = (insn >> 11) & 0x1f; |
1152 | if (ret == 0) | |
1153 | ret = 32; | |
1154 | return ret; | |
1155 | } | |
b9c361e0 | 1156 | |
b80c7270 AM |
1157 | /* The NB field in an lswi instruction, which has special value |
1158 | restrictions. The value 32 is stored as 0. */ | |
b9c361e0 | 1159 | |
0f873fd5 PB |
1160 | static uint64_t |
1161 | insert_nbi (uint64_t insn, | |
1162 | int64_t value, | |
b80c7270 AM |
1163 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1164 | const char **errmsg ATTRIBUTE_UNUSED) | |
1165 | { | |
0f873fd5 PB |
1166 | int64_t rtvalue = (insn >> 21) & 0x1f; |
1167 | int64_t ravalue = (insn >> 16) & 0x1f; | |
b9c361e0 | 1168 | |
b80c7270 AM |
1169 | if (value == 0) |
1170 | value = 32; | |
1171 | if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 | |
1172 | : ravalue)) | |
1173 | *errmsg = _("address register in load range"); | |
1174 | return insn | ((value & 0x1f) << 11); | |
1175 | } | |
786e2c0f | 1176 | |
b80c7270 AM |
1177 | /* The NSI field in a D form instruction. This is the same as the SI |
1178 | field, only negated. The extraction function always marks it as | |
1179 | invalid, since we never want to recognize an instruction which uses | |
1180 | a field of this type. */ | |
786e2c0f | 1181 | |
0f873fd5 PB |
1182 | static uint64_t |
1183 | insert_nsi (uint64_t insn, | |
1184 | int64_t value, | |
b80c7270 AM |
1185 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1186 | const char **errmsg ATTRIBUTE_UNUSED) | |
1187 | { | |
1188 | return insn | (-value & 0xffff); | |
1189 | } | |
786e2c0f | 1190 | |
0f873fd5 PB |
1191 | static int64_t |
1192 | extract_nsi (uint64_t insn, | |
b80c7270 AM |
1193 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1194 | int *invalid) | |
1195 | { | |
1196 | *invalid = 1; | |
1197 | return -(((insn & 0xffff) ^ 0x8000) - 0x8000); | |
1198 | } | |
786e2c0f | 1199 | |
3d205eb4 PB |
1200 | /* The 2-bit SC field in a SYNC or PL field in a WAIT instruction. |
1201 | For WAIT, some PL values are reserved: | |
1202 | * Values 1, 2 and 3 are reserved. */ | |
1203 | ||
1204 | static uint64_t | |
1205 | insert_pl (uint64_t insn, | |
1206 | int64_t value, | |
1207 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1208 | const char **errmsg) | |
1209 | { | |
1210 | /* For WAIT, some PL values are illegal. */ | |
1211 | if (((insn >> 1) & 0x3ff) == 30 | |
1212 | && value != 0) | |
1213 | *errmsg = _("illegal PL operand value"); | |
1214 | return insn | ((value & 0x3) << 16); | |
1215 | } | |
1216 | ||
1217 | static int64_t | |
1218 | extract_pl (uint64_t insn, | |
1219 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1220 | int *invalid) | |
1221 | { | |
1222 | /* Missing optional operands have a value of zero. */ | |
1223 | if (*invalid < 0) | |
1224 | return 0; | |
1225 | ||
1226 | uint64_t value = (insn >> 16) & 0x3; | |
1227 | ||
1228 | /* For WAIT, some PL values are illegal. */ | |
1229 | if (((insn >> 1) & 0x3ff) == 30 | |
1230 | && value != 0) | |
1231 | *invalid = 1; | |
1232 | return value; | |
1233 | } | |
1234 | ||
b80c7270 AM |
1235 | /* The RA field in a D or X form instruction which is an updating |
1236 | load, which means that the RA field may not be zero and may not | |
1237 | equal the RT field. */ | |
786e2c0f | 1238 | |
0f873fd5 PB |
1239 | static uint64_t |
1240 | insert_ral (uint64_t insn, | |
1241 | int64_t value, | |
b80c7270 AM |
1242 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1243 | const char **errmsg) | |
1244 | { | |
1245 | if (value == 0 | |
0f873fd5 | 1246 | || (uint64_t) value == ((insn >> 21) & 0x1f)) |
b80c7270 AM |
1247 | *errmsg = "invalid register operand when updating"; |
1248 | return insn | ((value & 0x1f) << 16); | |
1249 | } | |
786e2c0f | 1250 | |
0f873fd5 PB |
1251 | static int64_t |
1252 | extract_ral (uint64_t insn, | |
b80c7270 AM |
1253 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1254 | int *invalid) | |
1255 | { | |
0f873fd5 PB |
1256 | int64_t rtvalue = (insn >> 21) & 0x1f; |
1257 | int64_t ravalue = (insn >> 16) & 0x1f; | |
fb048c26 | 1258 | |
b80c7270 AM |
1259 | if (rtvalue == ravalue || ravalue == 0) |
1260 | *invalid = 1; | |
1261 | return ravalue; | |
1262 | } | |
a680de9a | 1263 | |
b80c7270 AM |
1264 | /* The RA field in an lmw instruction, which has special value |
1265 | restrictions. */ | |
c0637f3a | 1266 | |
0f873fd5 PB |
1267 | static uint64_t |
1268 | insert_ram (uint64_t insn, | |
1269 | int64_t value, | |
b80c7270 AM |
1270 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1271 | const char **errmsg) | |
1272 | { | |
0f873fd5 | 1273 | if ((uint64_t) value >= ((insn >> 21) & 0x1f)) |
b80c7270 AM |
1274 | *errmsg = _("index register in load range"); |
1275 | return insn | ((value & 0x1f) << 16); | |
1276 | } | |
c0637f3a | 1277 | |
0f873fd5 PB |
1278 | static int64_t |
1279 | extract_ram (uint64_t insn, | |
b80c7270 AM |
1280 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1281 | int *invalid) | |
1282 | { | |
0f873fd5 PB |
1283 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
1284 | uint64_t ravalue = (insn >> 16) & 0x1f; | |
ff3a6ee3 | 1285 | |
b80c7270 AM |
1286 | if (ravalue >= rtvalue) |
1287 | *invalid = 1; | |
1288 | return ravalue; | |
1289 | } | |
23976049 | 1290 | |
b80c7270 AM |
1291 | /* The RA field in the DQ form lq or an lswx instruction, which have special |
1292 | value restrictions. */ | |
e3c2f928 | 1293 | |
0f873fd5 PB |
1294 | static uint64_t |
1295 | insert_raq (uint64_t insn, | |
1296 | int64_t value, | |
b80c7270 AM |
1297 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1298 | const char **errmsg) | |
1299 | { | |
0f873fd5 | 1300 | int64_t rtvalue = (insn >> 21) & 0x1f; |
23976049 | 1301 | |
b80c7270 AM |
1302 | if (value == rtvalue) |
1303 | *errmsg = _("source and target register operands must be different"); | |
1304 | return insn | ((value & 0x1f) << 16); | |
1305 | } | |
e3c2f928 | 1306 | |
0f873fd5 PB |
1307 | static int64_t |
1308 | extract_raq (uint64_t insn, | |
b80c7270 AM |
1309 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1310 | int *invalid) | |
1311 | { | |
8acf1435 | 1312 | /* Missing optional operands have a value of zero. */ |
9cf7e568 AM |
1313 | if (*invalid < 0) |
1314 | return 0; | |
1315 | ||
0f873fd5 PB |
1316 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
1317 | uint64_t ravalue = (insn >> 16) & 0x1f; | |
b80c7270 AM |
1318 | if (ravalue == rtvalue) |
1319 | *invalid = 1; | |
1320 | return ravalue; | |
1321 | } | |
e3c2f928 | 1322 | |
b80c7270 AM |
1323 | /* The RA field in a D or X form instruction which is an updating |
1324 | store or an updating floating point load, which means that the RA | |
1325 | field may not be zero. */ | |
ff3a6ee3 | 1326 | |
0f873fd5 PB |
1327 | static uint64_t |
1328 | insert_ras (uint64_t insn, | |
1329 | int64_t value, | |
b80c7270 AM |
1330 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1331 | const char **errmsg) | |
1332 | { | |
1333 | if (value == 0) | |
1334 | *errmsg = _("invalid register operand when updating"); | |
1335 | return insn | ((value & 0x1f) << 16); | |
1336 | } | |
c3d65c1c | 1337 | |
0f873fd5 PB |
1338 | static int64_t |
1339 | extract_ras (uint64_t insn, | |
b80c7270 AM |
1340 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1341 | int *invalid) | |
1342 | { | |
0f873fd5 | 1343 | uint64_t ravalue = (insn >> 16) & 0x1f; |
c3d65c1c | 1344 | |
b80c7270 AM |
1345 | if (ravalue == 0) |
1346 | *invalid = 1; | |
1347 | return ravalue; | |
1348 | } | |
c3d65c1c | 1349 | |
98553ad3 PB |
1350 | /* The RS and RB fields in an X form instruction when they must be the same. |
1351 | This is used for extended mnemonics like mr. The extraction function | |
1352 | enforces that the fields are the same. */ | |
c3d65c1c | 1353 | |
0f873fd5 | 1354 | static uint64_t |
98553ad3 PB |
1355 | insert_rsb (uint64_t insn, |
1356 | int64_t value, | |
b80c7270 AM |
1357 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1358 | const char **errmsg ATTRIBUTE_UNUSED) | |
1359 | { | |
98553ad3 PB |
1360 | value &= 0x1f; |
1361 | return insn | (value << 21) | (value << 11); | |
b80c7270 | 1362 | } |
5ae2e65e | 1363 | |
0f873fd5 | 1364 | static int64_t |
98553ad3 | 1365 | extract_rsb (uint64_t insn, |
b80c7270 AM |
1366 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1367 | int *invalid) | |
1368 | { | |
98553ad3 PB |
1369 | int64_t rs = (insn >> 21) & 0x1f; |
1370 | int64_t rb = (insn >> 11) & 0x1f; | |
1371 | ||
1372 | if (rs != rb) | |
b80c7270 | 1373 | *invalid = 1; |
98553ad3 | 1374 | return rs; |
b80c7270 | 1375 | } |
702f0fb4 | 1376 | |
b80c7270 AM |
1377 | /* The RB field in an lswx instruction, which has special value |
1378 | restrictions. */ | |
702f0fb4 | 1379 | |
0f873fd5 PB |
1380 | static uint64_t |
1381 | insert_rbx (uint64_t insn, | |
1382 | int64_t value, | |
b80c7270 AM |
1383 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1384 | const char **errmsg) | |
1385 | { | |
0f873fd5 | 1386 | int64_t rtvalue = (insn >> 21) & 0x1f; |
a680de9a | 1387 | |
b80c7270 AM |
1388 | if (value == rtvalue) |
1389 | *errmsg = _("source and target register operands must be different"); | |
1390 | return insn | ((value & 0x1f) << 11); | |
1391 | } | |
a680de9a | 1392 | |
0f873fd5 PB |
1393 | static int64_t |
1394 | extract_rbx (uint64_t insn, | |
b80c7270 AM |
1395 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1396 | int *invalid) | |
1397 | { | |
0f873fd5 PB |
1398 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
1399 | uint64_t rbvalue = (insn >> 11) & 0x1f; | |
702f0fb4 | 1400 | |
b80c7270 AM |
1401 | if (rbvalue == rtvalue) |
1402 | *invalid = 1; | |
1403 | return rbvalue; | |
1404 | } | |
702f0fb4 | 1405 | |
b80c7270 | 1406 | /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ |
0f873fd5 PB |
1407 | static uint64_t |
1408 | insert_sci8 (uint64_t insn, | |
1409 | int64_t value, | |
b80c7270 AM |
1410 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1411 | const char **errmsg) | |
1412 | { | |
0f873fd5 PB |
1413 | uint64_t fill_scale = 0; |
1414 | uint64_t ui8 = value; | |
c0637f3a | 1415 | |
b80c7270 AM |
1416 | if ((ui8 & 0xffffff00) == 0) |
1417 | ; | |
1418 | else if ((ui8 & 0xffffff00) == 0xffffff00) | |
1419 | fill_scale = 0x400; | |
1420 | else if ((ui8 & 0xffff00ff) == 0) | |
1421 | { | |
1422 | fill_scale = 1 << 8; | |
1423 | ui8 >>= 8; | |
1424 | } | |
1425 | else if ((ui8 & 0xffff00ff) == 0xffff00ff) | |
1426 | { | |
1427 | fill_scale = 0x400 | (1 << 8); | |
1428 | ui8 >>= 8; | |
1429 | } | |
1430 | else if ((ui8 & 0xff00ffff) == 0) | |
1431 | { | |
1432 | fill_scale = 2 << 8; | |
1433 | ui8 >>= 16; | |
1434 | } | |
1435 | else if ((ui8 & 0xff00ffff) == 0xff00ffff) | |
1436 | { | |
1437 | fill_scale = 0x400 | (2 << 8); | |
1438 | ui8 >>= 16; | |
1439 | } | |
1440 | else if ((ui8 & 0x00ffffff) == 0) | |
1441 | { | |
1442 | fill_scale = 3 << 8; | |
1443 | ui8 >>= 24; | |
1444 | } | |
1445 | else if ((ui8 & 0x00ffffff) == 0x00ffffff) | |
1446 | { | |
1447 | fill_scale = 0x400 | (3 << 8); | |
1448 | ui8 >>= 24; | |
1449 | } | |
1450 | else | |
1451 | { | |
1452 | *errmsg = _("illegal immediate value"); | |
1453 | ui8 = 0; | |
1454 | } | |
702f0fb4 | 1455 | |
b80c7270 AM |
1456 | return insn | fill_scale | (ui8 & 0xff); |
1457 | } | |
ea192fa3 | 1458 | |
0f873fd5 PB |
1459 | static int64_t |
1460 | extract_sci8 (uint64_t insn, | |
b80c7270 AM |
1461 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1462 | int *invalid ATTRIBUTE_UNUSED) | |
1463 | { | |
0f873fd5 PB |
1464 | int64_t fill = insn & 0x400; |
1465 | int64_t scale_factor = (insn & 0x300) >> 5; | |
1466 | int64_t value = (insn & 0xff) << scale_factor; | |
081ba1b3 | 1467 | |
b80c7270 | 1468 | if (fill != 0) |
0f873fd5 | 1469 | value |= ~((int64_t) 0xff << scale_factor); |
b80c7270 AM |
1470 | return value; |
1471 | } | |
081ba1b3 | 1472 | |
0f873fd5 PB |
1473 | static uint64_t |
1474 | insert_sci8n (uint64_t insn, | |
1475 | int64_t value, | |
b80c7270 AM |
1476 | ppc_cpu_t dialect, |
1477 | const char **errmsg) | |
1478 | { | |
1479 | return insert_sci8 (insn, -value, dialect, errmsg); | |
1480 | } | |
081ba1b3 | 1481 | |
0f873fd5 PB |
1482 | static int64_t |
1483 | extract_sci8n (uint64_t insn, | |
b80c7270 AM |
1484 | ppc_cpu_t dialect, |
1485 | int *invalid) | |
1486 | { | |
1487 | return -extract_sci8 (insn, dialect, invalid); | |
1488 | } | |
081ba1b3 | 1489 | |
0f873fd5 PB |
1490 | static uint64_t |
1491 | insert_oimm (uint64_t insn, | |
1492 | int64_t value, | |
b80c7270 AM |
1493 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1494 | const char **errmsg ATTRIBUTE_UNUSED) | |
1495 | { | |
1496 | return insn | (((value - 1) & 0x1f) << 4); | |
1497 | } | |
b9c361e0 | 1498 | |
0f873fd5 PB |
1499 | static int64_t |
1500 | extract_oimm (uint64_t insn, | |
b80c7270 AM |
1501 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1502 | int *invalid ATTRIBUTE_UNUSED) | |
1503 | { | |
1504 | return ((insn >> 4) & 0x1f) + 1; | |
1505 | } | |
b9c361e0 | 1506 | |
b80c7270 | 1507 | /* The SH field in an MD form instruction. This is split. */ |
b9c361e0 | 1508 | |
0f873fd5 PB |
1509 | static uint64_t |
1510 | insert_sh6 (uint64_t insn, | |
1511 | int64_t value, | |
b80c7270 AM |
1512 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1513 | const char **errmsg ATTRIBUTE_UNUSED) | |
1514 | { | |
71553718 | 1515 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
b80c7270 | 1516 | } |
9b4e5766 | 1517 | |
0f873fd5 PB |
1518 | static int64_t |
1519 | extract_sh6 (uint64_t insn, | |
b80c7270 AM |
1520 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1521 | int *invalid ATTRIBUTE_UNUSED) | |
1522 | { | |
71553718 | 1523 | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
b80c7270 | 1524 | } |
a680de9a | 1525 | |
b80c7270 AM |
1526 | /* The SPR field in an XFX form instruction. This is flipped--the |
1527 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
9b4e5766 | 1528 | |
0f873fd5 PB |
1529 | static uint64_t |
1530 | insert_spr (uint64_t insn, | |
1531 | int64_t value, | |
b80c7270 AM |
1532 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1533 | const char **errmsg ATTRIBUTE_UNUSED) | |
1534 | { | |
1535 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1536 | } | |
9b4e5766 | 1537 | |
0f873fd5 PB |
1538 | static int64_t |
1539 | extract_spr (uint64_t insn, | |
b80c7270 AM |
1540 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1541 | int *invalid ATTRIBUTE_UNUSED) | |
1542 | { | |
1543 | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); | |
1544 | } | |
9b4e5766 | 1545 | |
fa758a70 AC |
1546 | /* Some dialects have 8 [DI]BAT registers instead of the standard 4. */ |
1547 | #define ALLOW8_BAT (PPC_OPCODE_750) | |
1548 | ||
16065af1 AM |
1549 | static uint64_t |
1550 | insert_sprbat (uint64_t insn, | |
1551 | int64_t value, | |
fa758a70 AC |
1552 | ppc_cpu_t dialect, |
1553 | const char **errmsg) | |
1554 | { | |
71553718 AM |
1555 | if ((uint64_t) value > 7 |
1556 | || ((uint64_t) value > 3 && (dialect & ALLOW8_BAT) == 0)) | |
fa758a70 AC |
1557 | *errmsg = _("invalid bat number"); |
1558 | ||
1559 | /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */ | |
71553718 | 1560 | if ((uint64_t) value > 3) |
fa758a70 AC |
1561 | value = ((value & 3) << 6) | 1; |
1562 | else | |
1563 | value = value << 6; | |
1564 | ||
1565 | return insn | (value << 11); | |
1566 | } | |
1567 | ||
16065af1 AM |
1568 | static int64_t |
1569 | extract_sprbat (uint64_t insn, | |
fa758a70 AC |
1570 | ppc_cpu_t dialect, |
1571 | int *invalid) | |
1572 | { | |
16065af1 | 1573 | uint64_t val = (insn >> 17) & 0x3; |
fa758a70 AC |
1574 | |
1575 | val = val + ((insn >> 9) & 0x4); | |
1576 | if (val > 3 && (dialect & ALLOW8_BAT) == 0) | |
1577 | *invalid = 1; | |
1578 | return val; | |
1579 | } | |
1580 | ||
b80c7270 AM |
1581 | /* Some dialects have 8 SPRG registers instead of the standard 4. */ |
1582 | #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) | |
066be9f7 | 1583 | |
0f873fd5 PB |
1584 | static uint64_t |
1585 | insert_sprg (uint64_t insn, | |
1586 | int64_t value, | |
b80c7270 AM |
1587 | ppc_cpu_t dialect, |
1588 | const char **errmsg) | |
1589 | { | |
71553718 AM |
1590 | if ((uint64_t) value > 7 |
1591 | || ((uint64_t) value > 3 && (dialect & ALLOW8_SPRG) == 0)) | |
b80c7270 | 1592 | *errmsg = _("invalid sprg number"); |
066be9f7 | 1593 | |
b80c7270 AM |
1594 | /* If this is mfsprg4..7 then use spr 260..263 which can be read in |
1595 | user mode. Anything else must use spr 272..279. */ | |
71553718 | 1596 | if ((uint64_t) value <= 3 || (insn & 0x100) != 0) |
b80c7270 | 1597 | value |= 0x10; |
066be9f7 | 1598 | |
b80c7270 AM |
1599 | return insn | ((value & 0x17) << 16); |
1600 | } | |
e0d602ec | 1601 | |
0f873fd5 PB |
1602 | static int64_t |
1603 | extract_sprg (uint64_t insn, | |
b80c7270 AM |
1604 | ppc_cpu_t dialect, |
1605 | int *invalid) | |
1606 | { | |
0f873fd5 | 1607 | uint64_t val = (insn >> 16) & 0x1f; |
4bc0608a | 1608 | |
b80c7270 AM |
1609 | /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 |
1610 | If not BOOKE, 405 or VLE, then both use only 272..275. */ | |
1611 | if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) | |
1612 | || (val - 0x10 > 7 && (insn & 0x100) != 0) | |
1613 | || val <= 3 | |
1614 | || (val & 8) != 0) | |
1615 | *invalid = 1; | |
1616 | return val & 7; | |
1617 | } | |
a680de9a | 1618 | |
b80c7270 AM |
1619 | /* The TBR field in an XFX instruction. This is just like SPR, but it |
1620 | is optional. */ | |
e3c2f928 | 1621 | |
0f873fd5 PB |
1622 | static uint64_t |
1623 | insert_tbr (uint64_t insn, | |
1624 | int64_t value, | |
b80c7270 AM |
1625 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1626 | const char **errmsg) | |
1627 | { | |
1628 | if (value != 268 && value != 269) | |
1629 | *errmsg = _("invalid tbr number"); | |
1630 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1631 | } | |
252b5132 | 1632 | |
0f873fd5 PB |
1633 | static int64_t |
1634 | extract_tbr (uint64_t insn, | |
b80c7270 AM |
1635 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1636 | int *invalid) | |
1637 | { | |
8acf1435 | 1638 | /* Missing optional operands have a value of 268. */ |
9cf7e568 AM |
1639 | if (*invalid < 0) |
1640 | return 268; | |
1641 | ||
0f873fd5 | 1642 | int64_t ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
b80c7270 AM |
1643 | if (ret != 268 && ret != 269) |
1644 | *invalid = 1; | |
1645 | return ret; | |
1646 | } | |
252b5132 | 1647 | |
b80c7270 | 1648 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
b9c361e0 | 1649 | |
0f873fd5 PB |
1650 | static uint64_t |
1651 | insert_xt6 (uint64_t insn, | |
1652 | int64_t value, | |
b9c361e0 JL |
1653 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1654 | const char **errmsg ATTRIBUTE_UNUSED) | |
1655 | { | |
b80c7270 | 1656 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); |
b9c361e0 JL |
1657 | } |
1658 | ||
0f873fd5 PB |
1659 | static int64_t |
1660 | extract_xt6 (uint64_t insn, | |
b9c361e0 JL |
1661 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1662 | int *invalid ATTRIBUTE_UNUSED) | |
43e65147 | 1663 | { |
b80c7270 | 1664 | return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); |
b9c361e0 JL |
1665 | } |
1666 | ||
b80c7270 | 1667 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
0f873fd5 PB |
1668 | static uint64_t |
1669 | insert_xtq6 (uint64_t insn, | |
1670 | int64_t value, | |
b80c7270 AM |
1671 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1672 | const char **errmsg ATTRIBUTE_UNUSED) | |
1673 | { | |
1674 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); | |
1675 | } | |
1676 | ||
0f873fd5 PB |
1677 | static int64_t |
1678 | extract_xtq6 (uint64_t insn, | |
b80c7270 AM |
1679 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1680 | int *invalid ATTRIBUTE_UNUSED) | |
1681 | { | |
1682 | return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); | |
1683 | } | |
1684 | ||
1685 | /* The XA field in an XX3 form instruction. This is split. */ | |
1686 | ||
0f873fd5 PB |
1687 | static uint64_t |
1688 | insert_xa6 (uint64_t insn, | |
1689 | int64_t value, | |
b9c361e0 JL |
1690 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1691 | const char **errmsg ATTRIBUTE_UNUSED) | |
1692 | { | |
b80c7270 | 1693 | return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); |
b9c361e0 JL |
1694 | } |
1695 | ||
0f873fd5 PB |
1696 | static int64_t |
1697 | extract_xa6 (uint64_t insn, | |
b9c361e0 JL |
1698 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1699 | int *invalid ATTRIBUTE_UNUSED) | |
1700 | { | |
b80c7270 | 1701 | return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); |
b9c361e0 JL |
1702 | } |
1703 | ||
aa3c112f AM |
1704 | /* The XA field in an MMA XX3 form instruction. This is split |
1705 | and must not overlap with the ACC operand. */ | |
1706 | ||
1707 | static uint64_t | |
1708 | insert_xa6a (uint64_t insn, | |
1709 | int64_t value, | |
1710 | ppc_cpu_t dialect, | |
1711 | const char **errmsg) | |
1712 | { | |
1713 | int64_t acc = (insn >> 23) & 0x7; | |
1714 | if ((value >> 2) == acc) | |
1715 | *errmsg = _("VSR overlaps ACC operand"); | |
1716 | return insert_xa6 (insn, value, dialect, errmsg); | |
1717 | } | |
1718 | ||
1719 | static int64_t | |
1720 | extract_xa6a (uint64_t insn, | |
1721 | ppc_cpu_t dialect, | |
1722 | int *invalid) | |
1723 | { | |
1724 | int64_t acc = (insn >> 23) & 0x7; | |
1725 | int64_t value = extract_xa6 (insn, dialect, invalid); | |
1726 | if ((value >> 2) == acc) | |
1727 | *invalid = 1; | |
1728 | return value; | |
1729 | } | |
1730 | ||
b80c7270 AM |
1731 | /* The XB field in an XX3 form instruction. This is split. */ |
1732 | ||
0f873fd5 PB |
1733 | static uint64_t |
1734 | insert_xb6 (uint64_t insn, | |
1735 | int64_t value, | |
b80c7270 AM |
1736 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1737 | const char **errmsg ATTRIBUTE_UNUSED) | |
b9c361e0 | 1738 | { |
b80c7270 | 1739 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
b9c361e0 JL |
1740 | } |
1741 | ||
0f873fd5 PB |
1742 | static int64_t |
1743 | extract_xb6 (uint64_t insn, | |
b80c7270 AM |
1744 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1745 | int *invalid ATTRIBUTE_UNUSED) | |
b9c361e0 | 1746 | { |
b80c7270 | 1747 | return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); |
b9c361e0 JL |
1748 | } |
1749 | ||
aa3c112f AM |
1750 | /* The XB field in an MMA XX3 form instruction. This is split |
1751 | and must not overlap with the ACC operand. */ | |
1752 | ||
1753 | static uint64_t | |
1754 | insert_xb6a (uint64_t insn, | |
1755 | int64_t value, | |
1756 | ppc_cpu_t dialect, | |
1757 | const char **errmsg) | |
1758 | { | |
1759 | int64_t acc = (insn >> 23) & 0x7; | |
1760 | if ((value >> 2) == acc) | |
1761 | *errmsg = _("VSR overlaps ACC operand"); | |
1762 | return insert_xb6 (insn, value, dialect, errmsg); | |
1763 | } | |
1764 | ||
1765 | static int64_t | |
1766 | extract_xb6a (uint64_t insn, | |
1767 | ppc_cpu_t dialect, | |
1768 | int *invalid) | |
1769 | { | |
1770 | int64_t acc = (insn >> 23) & 0x7; | |
1771 | int64_t value = extract_xb6 (insn, dialect, invalid); | |
1772 | if ((value >> 2) == acc) | |
1773 | *invalid = 1; | |
1774 | return value; | |
1775 | } | |
1776 | ||
98553ad3 PB |
1777 | /* The XA and XB fields in an XX3 form instruction when they must be the same. |
1778 | This is used for extended mnemonics like xvmovdp. The extraction function | |
1779 | enforces that the fields are the same. */ | |
b80c7270 | 1780 | |
0f873fd5 | 1781 | static uint64_t |
98553ad3 PB |
1782 | insert_xab6 (uint64_t insn, |
1783 | int64_t value, | |
1784 | ppc_cpu_t dialect, | |
1785 | const char **errmsg) | |
b9c361e0 | 1786 | { |
98553ad3 PB |
1787 | return insert_xa6 (insn, value, dialect, errmsg) |
1788 | | insert_xb6 (insn, value, dialect, errmsg); | |
b9c361e0 JL |
1789 | } |
1790 | ||
0f873fd5 | 1791 | static int64_t |
98553ad3 PB |
1792 | extract_xab6 (uint64_t insn, |
1793 | ppc_cpu_t dialect, | |
b80c7270 | 1794 | int *invalid) |
b9c361e0 | 1795 | { |
98553ad3 PB |
1796 | int64_t xa6 = extract_xa6 (insn, dialect, invalid); |
1797 | int64_t xb6 = extract_xb6 (insn, dialect, invalid); | |
1798 | ||
1799 | if (xa6 != xb6) | |
b80c7270 | 1800 | *invalid = 1; |
98553ad3 | 1801 | return xa6; |
b9c361e0 JL |
1802 | } |
1803 | ||
b80c7270 | 1804 | /* The XC field in an XX4 form instruction. This is split. */ |
252b5132 | 1805 | |
0f873fd5 PB |
1806 | static uint64_t |
1807 | insert_xc6 (uint64_t insn, | |
1808 | int64_t value, | |
fa452fa6 | 1809 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1810 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 | 1811 | { |
b80c7270 | 1812 | return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); |
252b5132 RH |
1813 | } |
1814 | ||
0f873fd5 PB |
1815 | static int64_t |
1816 | extract_xc6 (uint64_t insn, | |
fa452fa6 | 1817 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 | 1818 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 | 1819 | { |
b80c7270 AM |
1820 | return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); |
1821 | } | |
1822 | ||
94ba9882 AM |
1823 | /* The split XTp field in a vector paired insn. */ |
1824 | ||
1825 | static uint64_t | |
1826 | insert_xtp (uint64_t insn, | |
1827 | int64_t value, | |
1828 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1829 | const char **errmsg ATTRIBUTE_UNUSED) | |
1830 | { | |
1831 | return insn | ((value & 0x1e) << 21) | ((value & 0x20) << (21 - 5)); | |
1832 | } | |
1833 | ||
1834 | static int64_t | |
1835 | extract_xtp (uint64_t insn, | |
1836 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1837 | int *invalid ATTRIBUTE_UNUSED) | |
1838 | { | |
1839 | return ((insn >> (21 - 5)) & 0x20) | ((insn >> 21) & 0x1e); | |
1840 | } | |
1841 | ||
6edbfd3b AM |
1842 | /* The split XT field in a vector splat insn. */ |
1843 | ||
1844 | static uint64_t | |
1845 | insert_xts (uint64_t insn, | |
1846 | int64_t value, | |
1847 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1848 | const char **errmsg ATTRIBUTE_UNUSED) | |
1849 | { | |
1850 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) << (16 - 5)); | |
1851 | } | |
1852 | ||
1853 | static int64_t | |
1854 | extract_xts (uint64_t insn, | |
1855 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1856 | int *invalid ATTRIBUTE_UNUSED) | |
1857 | { | |
1858 | return ((insn >> (16 - 5)) & 0x20) | ((insn >> 21) & 0x1f); | |
1859 | } | |
1860 | ||
0f873fd5 PB |
1861 | static uint64_t |
1862 | insert_dm (uint64_t insn, | |
1863 | int64_t value, | |
b80c7270 AM |
1864 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1865 | const char **errmsg) | |
1866 | { | |
1867 | if (value != 0 && value != 1) | |
1868 | *errmsg = _("invalid constant"); | |
1869 | return insn | (((value) ? 3 : 0) << 8); | |
1870 | } | |
1871 | ||
0f873fd5 PB |
1872 | static int64_t |
1873 | extract_dm (uint64_t insn, | |
b80c7270 AM |
1874 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1875 | int *invalid) | |
1876 | { | |
0f873fd5 | 1877 | int64_t value = (insn >> 8) & 3; |
b80c7270 | 1878 | if (value != 0 && value != 3) |
252b5132 | 1879 | *invalid = 1; |
b80c7270 | 1880 | return (value) ? 1 : 0; |
252b5132 RH |
1881 | } |
1882 | ||
b80c7270 | 1883 | /* The VLESIMM field in an I16A form instruction. This is split. */ |
252b5132 | 1884 | |
0f873fd5 PB |
1885 | static uint64_t |
1886 | insert_vlesi (uint64_t insn, | |
1887 | int64_t value, | |
b80c7270 AM |
1888 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1889 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1890 | { |
b80c7270 | 1891 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
252b5132 RH |
1892 | } |
1893 | ||
0f873fd5 PB |
1894 | static int64_t |
1895 | extract_vlesi (uint64_t insn, | |
b80c7270 AM |
1896 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1897 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1898 | { |
0f873fd5 | 1899 | int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
b80c7270 AM |
1900 | value = (value ^ 0x8000) - 0x8000; |
1901 | return value; | |
252b5132 RH |
1902 | } |
1903 | ||
0f873fd5 PB |
1904 | static uint64_t |
1905 | insert_vlensi (uint64_t insn, | |
1906 | int64_t value, | |
b80c7270 AM |
1907 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1908 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1909 | { |
b80c7270 AM |
1910 | value = -value; |
1911 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); | |
252b5132 | 1912 | } |
0f873fd5 PB |
1913 | static int64_t |
1914 | extract_vlensi (uint64_t insn, | |
b80c7270 | 1915 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
9cf7e568 | 1916 | int *invalid) |
252b5132 | 1917 | { |
0f873fd5 | 1918 | int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
b80c7270 AM |
1919 | value = (value ^ 0x8000) - 0x8000; |
1920 | /* Don't use for disassembly. */ | |
1921 | *invalid = 1; | |
1922 | return -value; | |
252b5132 RH |
1923 | } |
1924 | ||
b80c7270 | 1925 | /* The VLEUIMM field in an I16A form instruction. This is split. */ |
252b5132 | 1926 | |
0f873fd5 PB |
1927 | static uint64_t |
1928 | insert_vleui (uint64_t insn, | |
1929 | int64_t value, | |
b80c7270 AM |
1930 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1931 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1932 | { |
b80c7270 | 1933 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
252b5132 RH |
1934 | } |
1935 | ||
0f873fd5 PB |
1936 | static int64_t |
1937 | extract_vleui (uint64_t insn, | |
b80c7270 AM |
1938 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1939 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1940 | { |
b80c7270 AM |
1941 | return ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
1942 | } | |
8427c424 | 1943 | |
b80c7270 AM |
1944 | /* The VLEUIMML field in an I16L form instruction. This is split. */ |
1945 | ||
0f873fd5 PB |
1946 | static uint64_t |
1947 | insert_vleil (uint64_t insn, | |
1948 | int64_t value, | |
b80c7270 AM |
1949 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1950 | const char **errmsg ATTRIBUTE_UNUSED) | |
1951 | { | |
1952 | return insn | ((value & 0xf800) << 5) | (value & 0x7ff); | |
252b5132 RH |
1953 | } |
1954 | ||
0f873fd5 PB |
1955 | static int64_t |
1956 | extract_vleil (uint64_t insn, | |
b80c7270 AM |
1957 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1958 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1959 | { |
b80c7270 | 1960 | return ((insn >> 5) & 0xf800) | (insn & 0x7ff); |
8ebac3aa | 1961 | } |
ba4e851b | 1962 | |
0f873fd5 PB |
1963 | static uint64_t |
1964 | insert_evuimm1_ex0 (uint64_t insn, | |
1965 | int64_t value, | |
74081948 AF |
1966 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1967 | const char **errmsg) | |
1968 | { | |
71553718 AM |
1969 | if (value <= 0 || value > 0x1f) |
1970 | *errmsg = _("UIMM = 00000 is illegal"); | |
1971 | return insn | ((value & 0x1f) << 11); | |
74081948 AF |
1972 | } |
1973 | ||
0f873fd5 PB |
1974 | static int64_t |
1975 | extract_evuimm1_ex0 (uint64_t insn, | |
74081948 AF |
1976 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1977 | int *invalid) | |
1978 | { | |
0f873fd5 | 1979 | int64_t value = ((insn >> 11) & 0x1f); |
74081948 AF |
1980 | if (value == 0) |
1981 | *invalid = 1; | |
1982 | ||
1983 | return value; | |
1984 | } | |
1985 | ||
0f873fd5 PB |
1986 | static uint64_t |
1987 | insert_evuimm2_ex0 (uint64_t insn, | |
1988 | int64_t value, | |
b80c7270 AM |
1989 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1990 | const char **errmsg) | |
8ebac3aa | 1991 | { |
71553718 AM |
1992 | if (value <= 0 || value > 0x3e) |
1993 | *errmsg = _("UIMM = 00000 is illegal"); | |
1994 | return insn | ((value & 0x3e) << 10); | |
252b5132 RH |
1995 | } |
1996 | ||
0f873fd5 PB |
1997 | static int64_t |
1998 | extract_evuimm2_ex0 (uint64_t insn, | |
b80c7270 AM |
1999 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2000 | int *invalid) | |
8ebac3aa | 2001 | { |
0f873fd5 | 2002 | int64_t value = ((insn >> 10) & 0x3e); |
b80c7270 AM |
2003 | if (value == 0) |
2004 | *invalid = 1; | |
8ebac3aa | 2005 | |
b80c7270 | 2006 | return value; |
8ebac3aa AM |
2007 | } |
2008 | ||
0f873fd5 PB |
2009 | static uint64_t |
2010 | insert_evuimm4_ex0 (uint64_t insn, | |
2011 | int64_t value, | |
b80c7270 AM |
2012 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2013 | const char **errmsg) | |
252b5132 | 2014 | { |
71553718 AM |
2015 | if (value <= 0 || value > 0x7c) |
2016 | *errmsg = _("UIMM = 00000 is illegal"); | |
2017 | return insn | ((value & 0x7c) << 9); | |
252b5132 RH |
2018 | } |
2019 | ||
0f873fd5 PB |
2020 | static int64_t |
2021 | extract_evuimm4_ex0 (uint64_t insn, | |
b80c7270 AM |
2022 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2023 | int *invalid) | |
252b5132 | 2024 | { |
0f873fd5 | 2025 | int64_t value = ((insn >> 9) & 0x7c); |
b80c7270 | 2026 | if (value == 0) |
252b5132 | 2027 | *invalid = 1; |
b80c7270 | 2028 | |
252b5132 RH |
2029 | return value; |
2030 | } | |
2031 | ||
0f873fd5 PB |
2032 | static uint64_t |
2033 | insert_evuimm8_ex0 (uint64_t insn, | |
2034 | int64_t value, | |
b80c7270 AM |
2035 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2036 | const char **errmsg) | |
2037 | { | |
71553718 AM |
2038 | if (value <= 0 || value > 0xf8) |
2039 | *errmsg = _("UIMM = 00000 is illegal"); | |
2040 | return insn | ((value & 0xf8) << 8); | |
252b5132 RH |
2041 | } |
2042 | ||
0f873fd5 PB |
2043 | static int64_t |
2044 | extract_evuimm8_ex0 (uint64_t insn, | |
b80c7270 AM |
2045 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2046 | int *invalid) | |
252b5132 | 2047 | { |
0f873fd5 | 2048 | int64_t value = ((insn >> 8) & 0xf8); |
b80c7270 | 2049 | if (value == 0) |
252b5132 | 2050 | *invalid = 1; |
252b5132 | 2051 | |
b80c7270 AM |
2052 | return value; |
2053 | } | |
a680de9a | 2054 | |
0f873fd5 PB |
2055 | static uint64_t |
2056 | insert_evuimm_lt8 (uint64_t insn, | |
2057 | int64_t value, | |
74081948 AF |
2058 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2059 | const char **errmsg) | |
2060 | { | |
71553718 AM |
2061 | if (value < 0 || value > 7) |
2062 | *errmsg = _("UIMM values >7 are illegal"); | |
2063 | return insn | ((value & 0x7) << 11); | |
74081948 AF |
2064 | } |
2065 | ||
0f873fd5 PB |
2066 | static int64_t |
2067 | extract_evuimm_lt8 (uint64_t insn, | |
74081948 AF |
2068 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2069 | int *invalid) | |
2070 | { | |
0f873fd5 | 2071 | int64_t value = ((insn >> 11) & 0x1f); |
74081948 AF |
2072 | if (value > 7) |
2073 | *invalid = 1; | |
2074 | ||
2075 | return value; | |
2076 | } | |
2077 | ||
0f873fd5 PB |
2078 | static uint64_t |
2079 | insert_evuimm_lt16 (uint64_t insn, | |
2080 | int64_t value, | |
b80c7270 AM |
2081 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2082 | const char **errmsg) | |
a680de9a | 2083 | { |
71553718 AM |
2084 | if (value < 0 || value > 15) |
2085 | *errmsg = _("UIMM values >15 are illegal"); | |
2086 | return insn | ((value & 0xf) << 11); | |
a680de9a PB |
2087 | } |
2088 | ||
0f873fd5 PB |
2089 | static int64_t |
2090 | extract_evuimm_lt16 (uint64_t insn, | |
b80c7270 AM |
2091 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2092 | int *invalid) | |
a680de9a | 2093 | { |
0f873fd5 | 2094 | int64_t value = ((insn >> 11) & 0x1f); |
b80c7270 AM |
2095 | if (value > 15) |
2096 | *invalid = 1; | |
a680de9a | 2097 | |
b80c7270 AM |
2098 | return value; |
2099 | } | |
a680de9a | 2100 | |
0f873fd5 PB |
2101 | static uint64_t |
2102 | insert_rD_rS_even (uint64_t insn, | |
2103 | int64_t value, | |
b80c7270 AM |
2104 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2105 | const char **errmsg) | |
a680de9a | 2106 | { |
71553718 AM |
2107 | if ((value & 0x1) != 0) |
2108 | *errmsg = _("GPR odd is illegal"); | |
2109 | return insn | ((value & 0x1e) << 21); | |
a680de9a PB |
2110 | } |
2111 | ||
0f873fd5 PB |
2112 | static int64_t |
2113 | extract_rD_rS_even (uint64_t insn, | |
b80c7270 AM |
2114 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2115 | int *invalid) | |
a680de9a | 2116 | { |
0f873fd5 | 2117 | int64_t value = ((insn >> 21) & 0x1f); |
b80c7270 AM |
2118 | if ((value & 0x1) != 0) |
2119 | *invalid = 1; | |
2120 | ||
2121 | return value; | |
a680de9a PB |
2122 | } |
2123 | ||
0f873fd5 PB |
2124 | static uint64_t |
2125 | insert_off_lsp (uint64_t insn, | |
2126 | int64_t value, | |
b80c7270 AM |
2127 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2128 | const char **errmsg) | |
a680de9a | 2129 | { |
71553718 AM |
2130 | if (value <= 0 || value > 0x3) |
2131 | *errmsg = _("invalid offset"); | |
2132 | return insn | (value & 0x3); | |
a680de9a PB |
2133 | } |
2134 | ||
0f873fd5 PB |
2135 | static int64_t |
2136 | extract_off_lsp (uint64_t insn, | |
b80c7270 AM |
2137 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2138 | int *invalid) | |
a680de9a | 2139 | { |
0f873fd5 | 2140 | int64_t value = (insn & 0x3); |
b80c7270 AM |
2141 | if (value == 0) |
2142 | *invalid = 1; | |
2143 | ||
2144 | return value; | |
a680de9a | 2145 | } |
74081948 | 2146 | |
0f873fd5 PB |
2147 | static uint64_t |
2148 | insert_off_spe2 (uint64_t insn, | |
2149 | int64_t value, | |
74081948 AF |
2150 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2151 | const char **errmsg) | |
2152 | { | |
71553718 AM |
2153 | if (value <= 0 || value > 0x7) |
2154 | *errmsg = _("invalid offset"); | |
2155 | return insn | (value & 0x7); | |
74081948 AF |
2156 | } |
2157 | ||
0f873fd5 PB |
2158 | static int64_t |
2159 | extract_off_spe2 (uint64_t insn, | |
74081948 AF |
2160 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2161 | int *invalid) | |
2162 | { | |
0f873fd5 | 2163 | int64_t value = (insn & 0x7); |
74081948 AF |
2164 | if (value == 0) |
2165 | *invalid = 1; | |
2166 | ||
2167 | return value; | |
2168 | } | |
2169 | ||
0f873fd5 PB |
2170 | static uint64_t |
2171 | insert_Ddd (uint64_t insn, | |
2172 | int64_t value, | |
74081948 AF |
2173 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2174 | const char **errmsg) | |
2175 | { | |
71553718 AM |
2176 | if (value < 0 || value > 0x7) |
2177 | *errmsg = _("invalid Ddd value"); | |
2178 | return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2); | |
74081948 AF |
2179 | } |
2180 | ||
0f873fd5 PB |
2181 | static int64_t |
2182 | extract_Ddd (uint64_t insn, | |
74081948 AF |
2183 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2184 | int *invalid ATTRIBUTE_UNUSED) | |
2185 | { | |
2186 | return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4); | |
2187 | } | |
9cf7e568 AM |
2188 | |
2189 | static uint64_t | |
2190 | insert_sxl (uint64_t insn, | |
2191 | int64_t value, | |
2192 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2193 | const char **errmsg ATTRIBUTE_UNUSED) | |
2194 | { | |
2195 | return insn | ((value & 0x1) << 11); | |
2196 | } | |
2197 | ||
2198 | static int64_t | |
2199 | extract_sxl (uint64_t insn, | |
2200 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2201 | int *invalid) | |
2202 | { | |
8acf1435 | 2203 | /* Missing optional operands have a value of one. */ |
9cf7e568 AM |
2204 | if (*invalid < 0) |
2205 | return 1; | |
2206 | return (insn >> 11) & 0x1; | |
2207 | } | |
b80c7270 AM |
2208 | \f |
2209 | /* The operands table. | |
a680de9a | 2210 | |
b80c7270 | 2211 | The fields are bitm, shift, insert, extract, flags. |
2fbfdc41 | 2212 | |
b80c7270 AM |
2213 | We used to put parens around the various additions, like the one |
2214 | for BA just below. However, that caused trouble with feeble | |
2215 | compilers with a limit on depth of a parenthesized expression, like | |
2216 | (reportedly) the compiler in Microsoft Developer Studio 5. So we | |
2217 | omit the parens, since the macros are never used in a context where | |
2218 | the addition will be ambiguous. */ | |
2219 | ||
2220 | const struct powerpc_operand powerpc_operands[] = | |
c168870a | 2221 | { |
b80c7270 AM |
2222 | /* The zero index is used to indicate the end of the list of |
2223 | operands. */ | |
2224 | #define UNUSED 0 | |
2225 | { 0, 0, NULL, NULL, 0 }, | |
2226 | ||
2227 | /* The BA field in an XL form instruction. */ | |
2228 | #define BA UNUSED + 1 | |
2229 | /* The BI field in a B form or XL form instruction. */ | |
2230 | #define BI BA | |
2231 | #define BI_MASK (0x1f << 16) | |
2232 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
2233 | ||
98553ad3 PB |
2234 | /* The BT, BA and BB fields in a XL form instruction when they must all |
2235 | be the same. */ | |
2236 | #define BTAB BA + 1 | |
2237 | { 0x1f, 21, insert_btab, extract_btab, PPC_OPERAND_CR_BIT }, | |
b80c7270 AM |
2238 | |
2239 | /* The BB field in an XL form instruction. */ | |
98553ad3 | 2240 | #define BB BTAB + 1 |
b80c7270 AM |
2241 | #define BB_MASK (0x1f << 11) |
2242 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
2243 | ||
98553ad3 PB |
2244 | /* The BA and BB fields in a XL form instruction when they must be |
2245 | the same. */ | |
2246 | #define BAB BB + 1 | |
2247 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_CR_BIT }, | |
2248 | ||
2249 | /* The VRA and VRB fields in a VX form instruction when they must be the same. | |
2250 | This is used for extended mnemonics like vmr. */ | |
2251 | #define VAB BAB + 1 | |
2252 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_VR }, | |
2253 | ||
2254 | /* The RA and RB fields in a VX form instruction when they must be the same. | |
2255 | This is used for extended mnemonics like evmr. */ | |
2256 | #define RAB VAB + 1 | |
2257 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_GPR }, | |
b80c7270 AM |
2258 | |
2259 | /* The BD field in a B form instruction. The lower two bits are | |
2260 | forced to zero. */ | |
98553ad3 | 2261 | #define BD RAB + 1 |
b80c7270 AM |
2262 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
2263 | ||
2264 | /* The BD field in a B form instruction when absolute addressing is | |
2265 | used. */ | |
2266 | #define BDA BD + 1 | |
2267 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
2268 | ||
2269 | /* The BD field in a B form instruction when the - modifier is used. | |
2270 | This sets the y bit of the BO field appropriately. */ | |
2271 | #define BDM BDA + 1 | |
2272 | { 0xfffc, 0, insert_bdm, extract_bdm, | |
2273 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
2274 | ||
2275 | /* The BD field in a B form instruction when the - modifier is used | |
2276 | and absolute address is used. */ | |
2277 | #define BDMA BDM + 1 | |
2278 | { 0xfffc, 0, insert_bdm, extract_bdm, | |
2279 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
2280 | ||
2281 | /* The BD field in a B form instruction when the + modifier is used. | |
2282 | This sets the y bit of the BO field appropriately. */ | |
2283 | #define BDP BDMA + 1 | |
2284 | { 0xfffc, 0, insert_bdp, extract_bdp, | |
2285 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
2286 | ||
2287 | /* The BD field in a B form instruction when the + modifier is used | |
2288 | and absolute addressing is used. */ | |
2289 | #define BDPA BDP + 1 | |
2290 | { 0xfffc, 0, insert_bdp, extract_bdp, | |
2291 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
2292 | ||
2293 | /* The BF field in an X or XL form instruction. */ | |
2294 | #define BF BDPA + 1 | |
2295 | /* The CRFD field in an X form instruction. */ | |
2296 | #define CRFD BF | |
2297 | /* The CRD field in an XL form instruction. */ | |
2298 | #define CRD BF | |
2299 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, | |
2300 | ||
2301 | /* The BF field in an X or XL form instruction. */ | |
2302 | #define BFF BF + 1 | |
2303 | { 0x7, 23, NULL, NULL, 0 }, | |
2304 | ||
aa3c112f AM |
2305 | /* The ACC field in a VSX ACC 8LS:D-form instruction. */ |
2306 | #define ACC BFF + 1 | |
2307 | { 0x7, 23, NULL, NULL, PPC_OPERAND_ACC }, | |
2308 | ||
b80c7270 AM |
2309 | /* An optional BF field. This is used for comparison instructions, |
2310 | in which an omitted BF field is taken as zero. */ | |
aa3c112f | 2311 | #define OBF ACC + 1 |
b80c7270 AM |
2312 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
2313 | ||
2314 | /* The BFA field in an X or XL form instruction. */ | |
2315 | #define BFA OBF + 1 | |
2316 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, | |
2317 | ||
2318 | /* The BO field in a B form instruction. Certain values are | |
2319 | illegal. */ | |
2320 | #define BO BFA + 1 | |
2321 | #define BO_MASK (0x1f << 21) | |
2322 | { 0x1f, 21, insert_bo, extract_bo, 0 }, | |
2323 | ||
aae9718e PB |
2324 | /* The BO field in a B form instruction when the - modifier is used. */ |
2325 | #define BOM BO + 1 | |
2326 | { 0x1f, 21, insert_bom, extract_bom, 0 }, | |
2327 | ||
2328 | /* The BO field in a B form instruction when the + modifier is used. */ | |
2329 | #define BOP BOM + 1 | |
2330 | { 0x1f, 21, insert_bop, extract_bop, 0 }, | |
b80c7270 AM |
2331 | |
2332 | /* The RM field in an X form instruction. */ | |
aae9718e | 2333 | #define RM BOP + 1 |
74081948 | 2334 | #define DD RM |
b80c7270 AM |
2335 | { 0x3, 11, NULL, NULL, 0 }, |
2336 | ||
2337 | #define BH RM + 1 | |
2338 | { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
2339 | ||
2340 | /* The BT field in an X or XL form instruction. */ | |
2341 | #define BT BH + 1 | |
2342 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
2343 | ||
96a86c01 AM |
2344 | /* The BT field in a mtfsb0 or mtfsb1 instruction. */ |
2345 | #define BTF BT + 1 | |
2346 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG }, | |
2347 | ||
b80c7270 | 2348 | /* The BI16 field in a BD8 form instruction. */ |
96a86c01 | 2349 | #define BI16 BTF + 1 |
b80c7270 AM |
2350 | { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, |
2351 | ||
2352 | /* The BI32 field in a BD15 form instruction. */ | |
2353 | #define BI32 BI16 + 1 | |
2354 | { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
98e69875 | 2355 | |
b80c7270 AM |
2356 | /* The BO32 field in a BD15 form instruction. */ |
2357 | #define BO32 BI32 + 1 | |
2358 | { 0x3, 20, NULL, NULL, 0 }, | |
c168870a | 2359 | |
b80c7270 AM |
2360 | /* The B8 field in a BD8 form instruction. */ |
2361 | #define B8 BO32 + 1 | |
2362 | { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 2363 | |
b80c7270 AM |
2364 | /* The B15 field in a BD15 form instruction. The lowest bit is |
2365 | forced to zero. */ | |
2366 | #define B15 B8 + 1 | |
2367 | { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 2368 | |
b80c7270 AM |
2369 | /* The B24 field in a BD24 form instruction. The lowest bit is |
2370 | forced to zero. */ | |
2371 | #define B24 B15 + 1 | |
2372 | { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 2373 | |
b80c7270 AM |
2374 | /* The condition register number portion of the BI field in a B form |
2375 | or XL form instruction. This is used for the extended | |
2376 | conditional branch mnemonics, which set the lower two bits of the | |
2377 | BI field. This field is optional. */ | |
2378 | #define CR B24 + 1 | |
2379 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
c168870a | 2380 | |
b80c7270 AM |
2381 | /* The CRB field in an X form instruction. */ |
2382 | #define CRB CR + 1 | |
2383 | /* The MB field in an M form instruction. */ | |
2384 | #define MB CRB | |
2385 | #define MB_MASK (0x1f << 6) | |
2386 | { 0x1f, 6, NULL, NULL, 0 }, | |
c168870a | 2387 | |
b80c7270 AM |
2388 | /* The CRD32 field in an XL form instruction. */ |
2389 | #define CRD32 CRB + 1 | |
2390 | { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, | |
c168870a | 2391 | |
b80c7270 AM |
2392 | /* The CRFS field in an X form instruction. */ |
2393 | #define CRFS CRD32 + 1 | |
2394 | { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, | |
b9c361e0 | 2395 | |
b80c7270 AM |
2396 | #define CRS CRFS + 1 |
2397 | { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2398 | |
b80c7270 AM |
2399 | /* The CT field in an X form instruction. */ |
2400 | #define CT CRS + 1 | |
2401 | /* The MO field in an mbar instruction. */ | |
2402 | #define MO CT | |
2403 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2404 | |
b80c7270 AM |
2405 | /* The D field in a D form instruction. This is a displacement off |
2406 | a register, and implies that the next operand is a register in | |
2407 | parentheses. */ | |
2408 | #define D CT + 1 | |
2409 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
aea77599 | 2410 | |
b80c7270 AM |
2411 | /* The D8 field in a D form instruction. This is a displacement off |
2412 | a register, and implies that the next operand is a register in | |
2413 | parentheses. */ | |
2414 | #define D8 D + 1 | |
2415 | { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
7b934113 | 2416 | |
b80c7270 AM |
2417 | /* The DCMX field in an X form instruction. */ |
2418 | #define DCMX D8 + 1 | |
2419 | { 0x7f, 16, NULL, NULL, 0 }, | |
7b934113 | 2420 | |
b80c7270 AM |
2421 | /* The split DCMX field in an X form instruction. */ |
2422 | #define DCMXS DCMX + 1 | |
2423 | { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, | |
73f07bff | 2424 | |
b80c7270 AM |
2425 | /* The DQ field in a DQ form instruction. This is like D, but the |
2426 | lower four bits are forced to zero. */ | |
2427 | #define DQ DCMXS + 1 | |
2428 | { 0xfff0, 0, NULL, NULL, | |
2429 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, | |
73f07bff | 2430 | |
b80c7270 AM |
2431 | /* The DS field in a DS form instruction. This is like D, but the |
2432 | lower two bits are forced to zero. */ | |
2433 | #define DS DQ + 1 | |
2434 | { 0xfffc, 0, NULL, NULL, | |
2435 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, | |
7b934113 | 2436 | |
8acf1435 PB |
2437 | /* The D field in an 8-byte D form prefix instruction. This is a displacement |
2438 | off a register, and implies that the next operand is a register in | |
2439 | parentheses. */ | |
2440 | #define D34 DS + 1 | |
0e62b37a | 2441 | { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, |
8acf1435 PB |
2442 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
2443 | ||
2444 | /* The SI field in an 8-byte D form prefix instruction. */ | |
2445 | #define SI34 D34 + 1 | |
0e62b37a | 2446 | { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, PPC_OPERAND_SIGNED }, |
8acf1435 PB |
2447 | |
2448 | /* The NSI field in an 8-byte D form prefix instruction. This is the | |
2449 | same as the SI34 field, only negated. */ | |
2450 | #define NSI34 SI34 + 1 | |
0e62b37a | 2451 | { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34, |
8acf1435 PB |
2452 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
2453 | ||
6edbfd3b AM |
2454 | /* The IMM32 field in a vector splat immediate prefix instruction. */ |
2455 | #define IMM32 NSI34 + 1 | |
2456 | { 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0}, | |
2457 | ||
2458 | /* The UIM field in a vector permute extended prefix instruction. */ | |
2459 | #define UIM3 IMM32 + 1 | |
2460 | { 0x7, 32, NULL, NULL, 0}, | |
2461 | ||
ec40e91c AM |
2462 | /* The UIM field in a vector eval prefix instruction. */ |
2463 | #define UIM8 UIM3 + 1 | |
2464 | { 0xff, 32, NULL, NULL, 0}, | |
2465 | ||
6edbfd3b | 2466 | /* The IX field in xxsplti32dx. */ |
ec40e91c | 2467 | #define IX UIM8 + 1 |
6edbfd3b AM |
2468 | { 0x1, 17, NULL, NULL, 0 }, |
2469 | ||
aa3c112f AM |
2470 | /* The PMSK field in GER rank 8 prefix instructions. */ |
2471 | #define PMSK8 IX + 1 | |
2472 | { 0xff, 40, NULL, NULL, 0 }, | |
2473 | ||
2474 | /* The PMSK field in GER rank 4 prefix instructions. */ | |
2475 | #define PMSK4 PMSK8 + 1 | |
2476 | { 0xf, 44, NULL, NULL, 0 }, | |
2477 | ||
2478 | /* The PMSK field in GER rank 2 prefix instructions. */ | |
2479 | #define PMSK2 PMSK4 + 1 | |
2480 | { 0x3, 46, NULL, NULL, 0 }, | |
2481 | ||
2482 | /* The XMSK field in GER prefix instructions. */ | |
2483 | #define XMSK PMSK2 + 1 | |
2484 | { 0xf, 36, NULL, NULL, 0 }, | |
2485 | ||
2486 | /* The YMSK field in GER prefix instructions. */ | |
2487 | #define YMSK XMSK + 1 | |
2488 | { 0xf, 32, NULL, NULL, 0 }, | |
2489 | ||
2490 | /* The YMSK field in 64-bit GER prefix instructions. */ | |
2491 | #define YMSK2 YMSK + 1 | |
2492 | { 0x3, 34, NULL, NULL, 0 }, | |
2493 | ||
b80c7270 AM |
2494 | /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits |
2495 | unsigned imediate */ | |
aa3c112f | 2496 | #define DUIS YMSK2 + 1 |
b80c7270 AM |
2497 | #define BHRBE DUIS |
2498 | { 0x3ff, 11, NULL, NULL, 0 }, | |
aea77599 | 2499 | |
b80c7270 AM |
2500 | /* The split D field in a DX form instruction. */ |
2501 | #define DXD DUIS + 1 | |
2502 | { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, | |
2503 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, | |
7b934113 | 2504 | |
b80c7270 AM |
2505 | /* The split ND field in a DX form instruction. |
2506 | This is the same as the DX field, only negated. */ | |
2507 | #define NDXD DXD + 1 | |
2508 | { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, | |
2509 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, | |
7b934113 | 2510 | |
b80c7270 AM |
2511 | /* The E field in a wrteei instruction. */ |
2512 | /* And the W bit in the pair singles instructions. */ | |
2513 | /* And the ST field in a VX form instruction. */ | |
2514 | #define E NDXD + 1 | |
2515 | #define PSW E | |
2516 | #define ST E | |
2517 | { 0x1, 15, NULL, NULL, 0 }, | |
aea77599 | 2518 | |
b80c7270 AM |
2519 | /* The FL1 field in a POWER SC form instruction. */ |
2520 | #define FL1 E + 1 | |
2521 | /* The U field in an X form instruction. */ | |
2522 | #define U FL1 | |
2523 | { 0xf, 12, NULL, NULL, 0 }, | |
73f07bff | 2524 | |
b80c7270 AM |
2525 | /* The FL2 field in a POWER SC form instruction. */ |
2526 | #define FL2 FL1 + 1 | |
2527 | { 0x7, 2, NULL, NULL, 0 }, | |
73f07bff | 2528 | |
b80c7270 AM |
2529 | /* The FLM field in an XFL form instruction. */ |
2530 | #define FLM FL2 + 1 | |
2531 | { 0xff, 17, NULL, NULL, 0 }, | |
73f07bff | 2532 | |
b80c7270 AM |
2533 | /* The FRA field in an X or A form instruction. */ |
2534 | #define FRA FLM + 1 | |
2535 | #define FRA_MASK (0x1f << 16) | |
2536 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2537 | |
b80c7270 AM |
2538 | /* The FRAp field of DFP instructions. */ |
2539 | #define FRAp FRA + 1 | |
2540 | { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2541 | |
b80c7270 AM |
2542 | /* The FRB field in an X or A form instruction. */ |
2543 | #define FRB FRAp + 1 | |
2544 | #define FRB_MASK (0x1f << 11) | |
2545 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, | |
2546 | ||
2547 | /* The FRBp field of DFP instructions. */ | |
2548 | #define FRBp FRB + 1 | |
2549 | { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2550 | |
b80c7270 AM |
2551 | /* The FRC field in an A form instruction. */ |
2552 | #define FRC FRBp + 1 | |
2553 | #define FRC_MASK (0x1f << 6) | |
2554 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2555 | |
b80c7270 AM |
2556 | /* The FRS field in an X form instruction or the FRT field in a D, X |
2557 | or A form instruction. */ | |
2558 | #define FRS FRC + 1 | |
2559 | #define FRT FRS | |
2560 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2561 | |
b80c7270 AM |
2562 | /* The FRSp field of stfdp or the FRTp field of lfdp and DFP |
2563 | instructions. */ | |
2564 | #define FRSp FRS + 1 | |
2565 | #define FRTp FRSp | |
2566 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2567 | |
b80c7270 AM |
2568 | /* The FXM field in an XFX instruction. */ |
2569 | #define FXM FRSp + 1 | |
2570 | { 0xff, 12, insert_fxm, extract_fxm, 0 }, | |
252b5132 | 2571 | |
b80c7270 AM |
2572 | /* Power4 version for mfcr. */ |
2573 | #define FXM4 FXM + 1 | |
9cf7e568 | 2574 | { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, |
252b5132 | 2575 | |
b80c7270 | 2576 | /* The IMM20 field in an LI instruction. */ |
9cf7e568 | 2577 | #define IMM20 FXM4 + 1 |
b80c7270 | 2578 | { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, |
252b5132 | 2579 | |
b80c7270 AM |
2580 | /* The L field in a D or X form instruction. */ |
2581 | #define L IMM20 + 1 | |
2582 | { 0x1, 21, NULL, NULL, 0 }, | |
252b5132 | 2583 | |
b80c7270 AM |
2584 | /* The optional L field in tlbie and tlbiel instructions. */ |
2585 | #define LOPT L + 1 | |
2586 | /* The R field in a HTM X form instruction. */ | |
2587 | #define HTM_R LOPT | |
2588 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2589 | |
afef4fe9 PB |
2590 | /* The optional L field in the paste. instruction. This is similar to LOPT |
2591 | above, but with a default value of 1. */ | |
2592 | #define L1OPT LOPT + 1 | |
2593 | { 0x1, 21, insert_l1opt, extract_l1opt, PPC_OPERAND_OPTIONAL }, | |
2594 | ||
b80c7270 | 2595 | /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ |
afef4fe9 | 2596 | #define L32OPT L1OPT + 1 |
b80c7270 | 2597 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, |
252b5132 | 2598 | |
3d205eb4 | 2599 | /* The 2-bit L or WC field in an X (sync, dcbf or wait) form instruction. */ |
b80c7270 | 2600 | #define L2OPT L32OPT + 1 |
3d205eb4 PB |
2601 | #define LS L2OPT |
2602 | #define WC L2OPT | |
2603 | { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2604 | |
b80c7270 AM |
2605 | /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ |
2606 | #define SVC_LEV L2OPT + 1 | |
2607 | { 0x7f, 5, NULL, NULL, 0 }, | |
252b5132 | 2608 | |
b80c7270 AM |
2609 | /* The LEV field in an SC form instruction. */ |
2610 | #define LEV SVC_LEV + 1 | |
2611 | { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2612 | |
b80c7270 AM |
2613 | /* The LI field in an I form instruction. The lower two bits are |
2614 | forced to zero. */ | |
2615 | #define LI LEV + 1 | |
2616 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2617 | |
b80c7270 AM |
2618 | /* The LI field in an I form instruction when used as an absolute |
2619 | address. */ | |
2620 | #define LIA LI + 1 | |
2621 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2622 | |
3d205eb4 PB |
2623 | /* The 3-bit L field in a sync or dcbf instruction. */ |
2624 | #define LS3 LIA + 1 | |
2625 | #define L3OPT LS3 | |
2626 | { 0x7, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2627 | |
b80c7270 | 2628 | /* The ME field in an M form instruction. */ |
3d205eb4 | 2629 | #define ME LS3 + 1 |
b80c7270 AM |
2630 | #define ME_MASK (0x1f << 1) |
2631 | { 0x1f, 1, NULL, NULL, 0 }, | |
989993d8 | 2632 | |
b80c7270 AM |
2633 | /* The MB and ME fields in an M form instruction expressed a single |
2634 | operand which is a bitmask indicating which bits to select. This | |
2635 | is a two operand form using PPC_OPERAND_NEXT. See the | |
2636 | description in opcode/ppc.h for what this means. */ | |
2637 | #define MBE ME + 1 | |
2638 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, | |
2639 | { -1, 0, insert_mbe, extract_mbe, 0 }, | |
989993d8 | 2640 | |
b80c7270 AM |
2641 | /* The MB or ME field in an MD or MDS form instruction. The high |
2642 | bit is wrapped to the low end. */ | |
2643 | #define MB6 MBE + 2 | |
2644 | #define ME6 MB6 | |
2645 | #define MB6_MASK (0x3f << 5) | |
2646 | { 0x3f, 5, insert_mb6, extract_mb6, 0 }, | |
989993d8 | 2647 | |
b80c7270 AM |
2648 | /* The NB field in an X form instruction. The value 32 is stored as |
2649 | 0. */ | |
2650 | #define NB MB6 + 1 | |
2651 | { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, | |
252b5132 | 2652 | |
b80c7270 AM |
2653 | /* The NBI field in an lswi instruction, which has special value |
2654 | restrictions. The value 32 is stored as 0. */ | |
2655 | #define NBI NB + 1 | |
2656 | { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, | |
252b5132 | 2657 | |
b80c7270 AM |
2658 | /* The NSI field in a D form instruction. This is the same as the |
2659 | SI field, only negated. */ | |
2660 | #define NSI NBI + 1 | |
2661 | { 0xffff, 0, insert_nsi, extract_nsi, | |
2662 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2663 | |
b80c7270 AM |
2664 | /* The NSI field in a D form instruction when we accept a wide range |
2665 | of positive values. */ | |
2666 | #define NSISIGNOPT NSI + 1 | |
2667 | { 0xffff, 0, insert_nsi, extract_nsi, | |
2668 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
252b5132 | 2669 | |
b80c7270 AM |
2670 | /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
2671 | #define RA NSISIGNOPT + 1 | |
2672 | #define RA_MASK (0x1f << 16) | |
2673 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, | |
252b5132 | 2674 | |
b80c7270 AM |
2675 | /* As above, but 0 in the RA field means zero, not r0. */ |
2676 | #define RA0 RA + 1 | |
2677 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2678 | |
8acf1435 PB |
2679 | /* Similar to above, but optional. */ |
2680 | #define PRA0 RA0 + 1 | |
2681 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL }, | |
2682 | ||
b80c7270 AM |
2683 | /* The RA field in the DQ form lq or an lswx instruction, which have |
2684 | special value restrictions. */ | |
8acf1435 | 2685 | #define RAQ PRA0 + 1 |
b80c7270 AM |
2686 | #define RAX RAQ |
2687 | { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2688 | |
8acf1435 PB |
2689 | /* Similar to above, but optional. */ |
2690 | #define PRAQ RAQ + 1 | |
2691 | { 0x1f, 16, insert_raq, extract_raq, | |
2692 | PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL }, | |
2693 | ||
2694 | /* The R field in an 8-byte D, DS, DQ or X form prefix instruction. */ | |
2695 | #define PCREL PRAQ + 1 | |
2696 | #define PCREL_MASK (1ULL << 52) | |
2697 | { 0x1, 52, insert_pcrel, extract_pcrel, PPC_OPERAND_OPTIONAL }, | |
2698 | ||
2699 | #define PCREL0 PCREL + 1 | |
2700 | { 0x1, 52, insert_pcrel, extract_pcrel0, PPC_OPERAND_OPTIONAL }, | |
2701 | ||
b80c7270 AM |
2702 | /* The RA field in a D or X form instruction which is an updating |
2703 | load, which means that the RA field may not be zero and may not | |
2704 | equal the RT field. */ | |
8acf1435 | 2705 | #define RAL PCREL0 + 1 |
b80c7270 | 2706 | { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 }, |
252b5132 | 2707 | |
b80c7270 AM |
2708 | /* The RA field in an lmw instruction, which has special value |
2709 | restrictions. */ | |
2710 | #define RAM RAL + 1 | |
2711 | { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 }, | |
252b5132 | 2712 | |
b80c7270 AM |
2713 | /* The RA field in a D or X form instruction which is an updating |
2714 | store or an updating floating point load, which means that the RA | |
2715 | field may not be zero. */ | |
2716 | #define RAS RAM + 1 | |
2717 | { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2718 | |
b80c7270 AM |
2719 | /* The RA field of the tlbwe, dccci and iccci instructions, |
2720 | which are optional. */ | |
2721 | #define RAOPT RAS + 1 | |
2722 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2723 | |
b80c7270 AM |
2724 | /* The RB field in an X, XO, M, or MDS form instruction. */ |
2725 | #define RB RAOPT + 1 | |
2726 | #define RB_MASK (0x1f << 11) | |
2727 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, | |
adadcc0c | 2728 | |
98553ad3 PB |
2729 | /* The RS and RB fields in an X form instruction when they must be the same. |
2730 | This is used for extended mnemonics like mr. */ | |
2731 | #define RSB RB + 1 | |
2732 | { 0x1f, 11, insert_rsb, extract_rsb, PPC_OPERAND_GPR }, | |
adadcc0c | 2733 | |
b80c7270 AM |
2734 | /* The RB field in an lswx instruction, which has special value |
2735 | restrictions. */ | |
98553ad3 | 2736 | #define RBX RSB + 1 |
b80c7270 | 2737 | { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR }, |
adadcc0c | 2738 | |
b80c7270 AM |
2739 | /* The RB field of the dccci and iccci instructions, which are optional. */ |
2740 | #define RBOPT RBX + 1 | |
2741 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2742 | |
b80c7270 AM |
2743 | /* The RC register field in an maddld, maddhd or maddhdu instruction. */ |
2744 | #define RC RBOPT + 1 | |
2745 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, | |
73f07bff | 2746 | |
b80c7270 AM |
2747 | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
2748 | instruction or the RT field in a D, DS, X, XFX or XO form | |
2749 | instruction. */ | |
2750 | #define RS RC + 1 | |
2751 | #define RT RS | |
2752 | #define RT_MASK (0x1f << 21) | |
2753 | #define RD RS | |
2754 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, | |
252b5132 | 2755 | |
b80c7270 AM |
2756 | #define RD_EVEN RS + 1 |
2757 | #define RS_EVEN RD_EVEN | |
2758 | { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR }, | |
252b5132 | 2759 | |
b80c7270 AM |
2760 | /* The RS and RT fields of the DS form stq and DQ form lq instructions, |
2761 | which have special value restrictions. */ | |
2762 | #define RSQ RS_EVEN + 1 | |
2763 | #define RTQ RSQ | |
2764 | #define Q_MASK (1 << 21) | |
2765 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, | |
73f07bff | 2766 | |
b80c7270 AM |
2767 | /* The RS field of the tlbwe instruction, which is optional. */ |
2768 | #define RSO RSQ + 1 | |
2769 | #define RTO RSO | |
2770 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2771 | |
b80c7270 AM |
2772 | /* The RX field of the SE_RR form instruction. */ |
2773 | #define RX RSO + 1 | |
2774 | { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, | |
252b5132 | 2775 | |
b80c7270 AM |
2776 | /* The ARX field of the SE_RR form instruction. */ |
2777 | #define ARX RX + 1 | |
2778 | { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, | |
252b5132 | 2779 | |
b80c7270 AM |
2780 | /* The RY field of the SE_RR form instruction. */ |
2781 | #define RY ARX + 1 | |
2782 | #define RZ RY | |
2783 | { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, | |
252b5132 | 2784 | |
b80c7270 AM |
2785 | /* The ARY field of the SE_RR form instruction. */ |
2786 | #define ARY RY + 1 | |
2787 | { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, | |
989993d8 | 2788 | |
b80c7270 AM |
2789 | /* The SCLSCI8 field in a D form instruction. */ |
2790 | #define SCLSCI8 ARY + 1 | |
2791 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, | |
989993d8 | 2792 | |
b80c7270 AM |
2793 | /* The SCLSCI8N field in a D form instruction. This is the same as the |
2794 | SCLSCI8 field, only negated. */ | |
2795 | #define SCLSCI8N SCLSCI8 + 1 | |
2796 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, | |
2797 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, | |
989993d8 | 2798 | |
b80c7270 AM |
2799 | /* The SD field of the SD4 form instruction. */ |
2800 | #define SE_SD SCLSCI8N + 1 | |
2801 | { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, | |
73f07bff | 2802 | |
b80c7270 AM |
2803 | /* The SD field of the SD4 form instruction, for halfword. */ |
2804 | #define SE_SDH SE_SD + 1 | |
71553718 | 2805 | { 0x1e, 7, NULL, NULL, PPC_OPERAND_PARENS }, |
73f07bff | 2806 | |
b80c7270 AM |
2807 | /* The SD field of the SD4 form instruction, for word. */ |
2808 | #define SE_SDW SE_SDH + 1 | |
71553718 | 2809 | { 0x3c, 6, NULL, NULL, PPC_OPERAND_PARENS }, |
b9c361e0 | 2810 | |
b80c7270 AM |
2811 | /* The SH field in an X or M form instruction. */ |
2812 | #define SH SE_SDW + 1 | |
2813 | #define SH_MASK (0x1f << 11) | |
2814 | /* The other UIMM field in a EVX form instruction. */ | |
2815 | #define EVUIMM SH | |
2816 | /* The FC field in an atomic X form instruction. */ | |
2817 | #define FC SH | |
6edbfd3b | 2818 | #define UIM5 SH |
b80c7270 | 2819 | { 0x1f, 11, NULL, NULL, 0 }, |
b9c361e0 | 2820 | |
74081948 AF |
2821 | #define EVUIMM_LT8 SH + 1 |
2822 | { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 }, | |
2823 | ||
2824 | #define EVUIMM_LT16 EVUIMM_LT8 + 1 | |
b80c7270 | 2825 | { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 }, |
b9c361e0 | 2826 | |
b80c7270 AM |
2827 | /* The SI field in a HTM X form instruction. */ |
2828 | #define HTM_SI EVUIMM_LT16 + 1 | |
2829 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, | |
943d398f | 2830 | |
b80c7270 AM |
2831 | /* The SH field in an MD form instruction. This is split. */ |
2832 | #define SH6 HTM_SI + 1 | |
2833 | #define SH6_MASK ((0x1f << 11) | (1 << 1)) | |
2834 | { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, | |
b9c361e0 | 2835 | |
b80c7270 AM |
2836 | /* The SH field of some variants of the tlbre and tlbwe |
2837 | instructions, and the ELEV field of the e_sc instruction. */ | |
2838 | #define SHO SH6 + 1 | |
2839 | #define ELEV SHO | |
2840 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2841 | |
b80c7270 AM |
2842 | /* The SI field in a D form instruction. */ |
2843 | #define SI SHO + 1 | |
2844 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, | |
b9c361e0 | 2845 | |
b80c7270 AM |
2846 | /* The SI field in a D form instruction when we accept a wide range |
2847 | of positive values. */ | |
2848 | #define SISIGNOPT SI + 1 | |
2849 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
b9c361e0 | 2850 | |
b80c7270 AM |
2851 | /* The SI8 field in a D form instruction. */ |
2852 | #define SI8 SISIGNOPT + 1 | |
2853 | { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, | |
b9c361e0 | 2854 | |
b80c7270 AM |
2855 | /* The SPR field in an XFX form instruction. This is flipped--the |
2856 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
2857 | #define SPR SI8 + 1 | |
2858 | #define PMR SPR | |
2859 | #define TMR SPR | |
2860 | #define SPR_MASK (0x3ff << 11) | |
2861 | { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR }, | |
b9c361e0 | 2862 | |
b80c7270 AM |
2863 | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ |
2864 | #define SPRBAT SPR + 1 | |
fa758a70 AC |
2865 | #define SPRBAT_MASK (0xc1 << 11) |
2866 | { 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR }, | |
2867 | ||
2868 | /* The GQR index number in an XFX form m[ft]gqr instruction. */ | |
2869 | #define SPRGQR SPRBAT + 1 | |
2870 | #define SPRGQR_MASK (0x7 << 16) | |
2871 | { 0x7, 16, NULL, NULL, PPC_OPERAND_GQR }, | |
b9c361e0 | 2872 | |
b80c7270 | 2873 | /* The SPRG register number in an XFX form m[ft]sprg instruction. */ |
fa758a70 | 2874 | #define SPRG SPRGQR + 1 |
b80c7270 | 2875 | { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, |
b9c361e0 | 2876 | |
b80c7270 AM |
2877 | /* The SR field in an X form instruction. */ |
2878 | #define SR SPRG + 1 | |
2879 | /* The 4-bit UIMM field in a VX form instruction. */ | |
2880 | #define UIMM4 SR | |
2881 | { 0xf, 16, NULL, NULL, 0 }, | |
b9c361e0 | 2882 | |
b80c7270 AM |
2883 | /* The STRM field in an X AltiVec form instruction. */ |
2884 | #define STRM SR + 1 | |
2885 | /* The T field in a tlbilx form instruction. */ | |
2886 | #define T STRM | |
2887 | /* The L field in wclr instructions. */ | |
2888 | #define L2 STRM | |
2889 | { 0x3, 21, NULL, NULL, 0 }, | |
252b5132 | 2890 | |
b80c7270 AM |
2891 | /* The ESYNC field in an X (sync) form instruction. */ |
2892 | #define ESYNC STRM + 1 | |
2893 | { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2894 | |
b80c7270 AM |
2895 | /* The SV field in a POWER SC form instruction. */ |
2896 | #define SV ESYNC + 1 | |
2897 | { 0x3fff, 2, NULL, NULL, 0 }, | |
252b5132 | 2898 | |
b80c7270 AM |
2899 | /* The TBR field in an XFX form instruction. This is like the SPR |
2900 | field, but it is optional. */ | |
2901 | #define TBR SV + 1 | |
2902 | { 0x3ff, 11, insert_tbr, extract_tbr, | |
9cf7e568 | 2903 | PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL }, |
252b5132 | 2904 | |
b80c7270 | 2905 | /* The TO field in a D or X form instruction. */ |
9cf7e568 | 2906 | #define TO TBR + 1 |
b80c7270 AM |
2907 | #define DUI TO |
2908 | #define TO_MASK (0x1f << 21) | |
2909 | { 0x1f, 21, NULL, NULL, 0 }, | |
252b5132 | 2910 | |
b80c7270 AM |
2911 | /* The UI field in a D form instruction. */ |
2912 | #define UI TO + 1 | |
2913 | { 0xffff, 0, NULL, NULL, 0 }, | |
252b5132 | 2914 | |
b80c7270 AM |
2915 | #define UISIGNOPT UI + 1 |
2916 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, | |
da99ee72 | 2917 | |
b80c7270 AM |
2918 | /* The IMM field in an SE_IM5 instruction. */ |
2919 | #define UI5 UISIGNOPT + 1 | |
2920 | { 0x1f, 4, NULL, NULL, 0 }, | |
da99ee72 | 2921 | |
b80c7270 AM |
2922 | /* The OIMM field in an SE_OIM5 instruction. */ |
2923 | #define OIMM5 UI5 + 1 | |
71553718 | 2924 | { 0x1f, 4, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, |
da99ee72 | 2925 | |
b80c7270 AM |
2926 | /* The UI7 field in an SE_LI instruction. */ |
2927 | #define UI7 OIMM5 + 1 | |
2928 | { 0x7f, 4, NULL, NULL, 0 }, | |
da99ee72 | 2929 | |
b80c7270 AM |
2930 | /* The VA field in a VA, VX or VXR form instruction. */ |
2931 | #define VA UI7 + 1 | |
2932 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, | |
da99ee72 | 2933 | |
b80c7270 AM |
2934 | /* The VB field in a VA, VX or VXR form instruction. */ |
2935 | #define VB VA + 1 | |
2936 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, | |
da99ee72 | 2937 | |
b80c7270 AM |
2938 | /* The VC field in a VA form instruction. */ |
2939 | #define VC VB + 1 | |
2940 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, | |
252b5132 | 2941 | |
b80c7270 AM |
2942 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
2943 | #define VD VC + 1 | |
2944 | #define VS VD | |
2945 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, | |
252b5132 | 2946 | |
b80c7270 AM |
2947 | /* The SIMM field in a VX form instruction, and TE in Z form. */ |
2948 | #define SIMM VD + 1 | |
2949 | #define TE SIMM | |
2950 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, | |
252b5132 | 2951 | |
b80c7270 AM |
2952 | /* The UIMM field in a VX form instruction. */ |
2953 | #define UIMM SIMM + 1 | |
2954 | #define DCTL UIMM | |
2955 | { 0x1f, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2956 | |
b80c7270 AM |
2957 | /* The 3-bit UIMM field in a VX form instruction. */ |
2958 | #define UIMM3 UIMM + 1 | |
2959 | { 0x7, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2960 | |
b80c7270 AM |
2961 | /* The 6-bit UIM field in a X form instruction. */ |
2962 | #define UIM6 UIMM3 + 1 | |
2963 | { 0x3f, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2964 | |
b80c7270 AM |
2965 | /* The SIX field in a VX form instruction. */ |
2966 | #define SIX UIM6 + 1 | |
74081948 | 2967 | #define MMMM SIX |
b80c7270 | 2968 | { 0xf, 11, NULL, NULL, 0 }, |
9b4e5766 | 2969 | |
b80c7270 AM |
2970 | /* The PS field in a VX form instruction. */ |
2971 | #define PS SIX + 1 | |
2972 | { 0x1, 9, NULL, NULL, 0 }, | |
a680de9a | 2973 | |
6edbfd3b AM |
2974 | /* The SH field in a vector shift double by bit immediate instruction. */ |
2975 | #define SH3 PS + 1 | |
2976 | { 0x7, 6, NULL, NULL, 0 }, | |
2977 | ||
b80c7270 | 2978 | /* The SHB field in a VA form instruction. */ |
6edbfd3b | 2979 | #define SHB SH3 + 1 |
b80c7270 | 2980 | { 0xf, 6, NULL, NULL, 0 }, |
a680de9a | 2981 | |
b80c7270 | 2982 | /* The other UIMM field in a half word EVX form instruction. */ |
74081948 AF |
2983 | #define EVUIMM_1 SHB + 1 |
2984 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS }, | |
2985 | ||
2986 | #define EVUIMM_1_EX0 EVUIMM_1 + 1 | |
2987 | { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS }, | |
2988 | ||
2989 | #define EVUIMM_2 EVUIMM_1_EX0 + 1 | |
b80c7270 | 2990 | { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
9b4e5766 | 2991 | |
b80c7270 AM |
2992 | #define EVUIMM_2_EX0 EVUIMM_2 + 1 |
2993 | { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2994 | |
b80c7270 AM |
2995 | /* The other UIMM field in a word EVX form instruction. */ |
2996 | #define EVUIMM_4 EVUIMM_2_EX0 + 1 | |
2997 | { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2998 | |
b80c7270 AM |
2999 | #define EVUIMM_4_EX0 EVUIMM_4 + 1 |
3000 | { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 3001 | |
b80c7270 AM |
3002 | /* The other UIMM field in a double EVX form instruction. */ |
3003 | #define EVUIMM_8 EVUIMM_4_EX0 + 1 | |
3004 | { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, | |
9b4e5766 | 3005 | |
b80c7270 AM |
3006 | #define EVUIMM_8_EX0 EVUIMM_8 + 1 |
3007 | { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 3008 | |
b80c7270 AM |
3009 | /* The WS or DRM field in an X form instruction. */ |
3010 | #define WS EVUIMM_8_EX0 + 1 | |
3011 | #define DRM WS | |
74081948 AF |
3012 | /* The NNN field in a VX form instruction for SPE2 */ |
3013 | #define NNN WS | |
b80c7270 | 3014 | { 0x7, 11, NULL, NULL, 0 }, |
9b4e5766 | 3015 | |
b80c7270 AM |
3016 | /* PowerPC paired singles extensions. */ |
3017 | /* W bit in the pair singles instructions for x type instructions. */ | |
3018 | #define PSWM WS + 1 | |
3019 | /* The BO16 field in a BD8 form instruction. */ | |
3020 | #define BO16 PSWM | |
3021 | { 0x1, 10, 0, 0, 0 }, | |
9b4e5766 | 3022 | |
b80c7270 AM |
3023 | /* IDX bits for quantization in the pair singles instructions. */ |
3024 | #define PSQ PSWM + 1 | |
3025 | { 0x7, 12, 0, 0, PPC_OPERAND_GQR }, | |
066be9f7 | 3026 | |
b80c7270 AM |
3027 | /* IDX bits for quantization in the pair singles x-type instructions. */ |
3028 | #define PSQM PSQ + 1 | |
3029 | { 0x7, 7, 0, 0, PPC_OPERAND_GQR }, | |
066be9f7 | 3030 | |
b80c7270 AM |
3031 | /* Smaller D field for quantization in the pair singles instructions. */ |
3032 | #define PSD PSQM + 1 | |
3033 | { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
066be9f7 | 3034 | |
b80c7270 AM |
3035 | /* The L field in an mtmsrd or A form instruction or R or W in an |
3036 | X form. */ | |
3037 | #define A_L PSD + 1 | |
3038 | #define W A_L | |
3039 | #define X_R A_L | |
3040 | { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
066be9f7 | 3041 | |
b80c7270 AM |
3042 | /* The RMC or CY field in a Z23 form instruction. */ |
3043 | #define RMC A_L + 1 | |
3044 | #define CY RMC | |
3045 | { 0x3, 9, NULL, NULL, 0 }, | |
066be9f7 | 3046 | |
b80c7270 | 3047 | #define R RMC + 1 |
fdefed7c | 3048 | #define MP R |
b80c7270 | 3049 | { 0x1, 16, NULL, NULL, 0 }, |
066be9f7 | 3050 | |
b80c7270 AM |
3051 | #define RIC R + 1 |
3052 | { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
7b934113 | 3053 | |
b80c7270 AM |
3054 | #define PRS RIC + 1 |
3055 | { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 3056 | |
b80c7270 AM |
3057 | #define SP PRS + 1 |
3058 | { 0x3, 19, NULL, NULL, 0 }, | |
b9c361e0 | 3059 | |
b80c7270 AM |
3060 | #define S SP + 1 |
3061 | { 0x1, 20, NULL, NULL, 0 }, | |
b9c361e0 | 3062 | |
b80c7270 AM |
3063 | /* The S field in a XL form instruction. */ |
3064 | #define SXL S + 1 | |
9cf7e568 | 3065 | { 0x1, 11, insert_sxl, extract_sxl, PPC_OPERAND_OPTIONAL }, |
b80c7270 AM |
3066 | |
3067 | /* SH field starting at bit position 16. */ | |
9cf7e568 | 3068 | #define SH16 SXL + 1 |
b80c7270 AM |
3069 | /* The DCM and DGM fields in a Z form instruction. */ |
3070 | #define DCM SH16 | |
3071 | #define DGM DCM | |
3072 | { 0x3f, 10, NULL, NULL, 0 }, | |
3073 | ||
3074 | /* The EH field in larx instruction. */ | |
3075 | #define EH SH16 + 1 | |
3076 | { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 3077 | |
b80c7270 AM |
3078 | /* The L field in an mtfsf or XFL form instruction. */ |
3079 | /* The A field in a HTM X form instruction. */ | |
3080 | #define XFL_L EH + 1 | |
3081 | #define HTM_A XFL_L | |
3082 | { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, | |
b9c361e0 | 3083 | |
b80c7270 AM |
3084 | /* Xilinx APU related masks and macros */ |
3085 | #define FCRT XFL_L + 1 | |
3086 | #define FCRT_MASK (0x1f << 21) | |
3087 | { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, | |
b9c361e0 | 3088 | |
b80c7270 AM |
3089 | /* Xilinx FSL related masks and macros */ |
3090 | #define FSL FCRT + 1 | |
3091 | #define FSL_MASK (0x1f << 11) | |
3092 | { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, | |
b9c361e0 | 3093 | |
b80c7270 AM |
3094 | /* Xilinx UDI related masks and macros */ |
3095 | #define URT FSL + 1 | |
3096 | { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 3097 | |
b80c7270 AM |
3098 | #define URA URT + 1 |
3099 | { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 3100 | |
b80c7270 AM |
3101 | #define URB URA + 1 |
3102 | { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 3103 | |
b80c7270 AM |
3104 | #define URC URB + 1 |
3105 | { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, | |
e3c2f928 | 3106 | |
b80c7270 AM |
3107 | /* The VLESIMM field in a D form instruction. */ |
3108 | #define VLESIMM URC + 1 | |
3109 | { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, | |
3110 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 3111 | |
b80c7270 AM |
3112 | /* The VLENSIMM field in a D form instruction. */ |
3113 | #define VLENSIMM VLESIMM + 1 | |
3114 | { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, | |
3115 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 3116 | |
b80c7270 AM |
3117 | /* The VLEUIMM field in a D form instruction. */ |
3118 | #define VLEUIMM VLENSIMM + 1 | |
3119 | { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, | |
e3c2f928 | 3120 | |
b80c7270 AM |
3121 | /* The VLEUIMML field in a D form instruction. */ |
3122 | #define VLEUIMML VLEUIMM + 1 | |
3123 | { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, | |
e3c2f928 | 3124 | |
b80c7270 AM |
3125 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is |
3126 | split. */ | |
3127 | #define XS6 VLEUIMML + 1 | |
3128 | #define XT6 XS6 | |
3129 | { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, | |
e3c2f928 | 3130 | |
b80c7270 AM |
3131 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
3132 | #define XSQ6 XT6 + 1 | |
3133 | #define XTQ6 XSQ6 | |
3134 | { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, | |
e3c2f928 | 3135 | |
94ba9882 AM |
3136 | /* The split XTp field in a vector paired instruction. */ |
3137 | #define XTP XSQ6 + 1 | |
3138 | { 0x3e, PPC_OPSHIFT_INV, insert_xtp, extract_xtp, PPC_OPERAND_VSR }, | |
3139 | ||
6edbfd3b AM |
3140 | #define XTS XTP + 1 |
3141 | { 0x3f, PPC_OPSHIFT_INV, insert_xts, extract_xts, PPC_OPERAND_VSR }, | |
3142 | ||
8acf1435 | 3143 | /* The XT field in a plxv instruction. Runs into the OP field. */ |
6edbfd3b | 3144 | #define XTOP XTS + 1 |
8acf1435 PB |
3145 | { 0x3f, 21, NULL, NULL, PPC_OPERAND_VSR }, |
3146 | ||
b80c7270 | 3147 | /* The XA field in an XX3 form instruction. This is split. */ |
8acf1435 | 3148 | #define XA6 XTOP + 1 |
b80c7270 | 3149 | { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, |
e3c2f928 | 3150 | |
aa3c112f AM |
3151 | /* The XA field in an MMA XX3 form instruction. This is split and |
3152 | must not overlap with the ACC operand. */ | |
3153 | #define XA6a XA6 + 1 | |
3154 | { 0x3f, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR }, | |
3155 | ||
3156 | /* The XAp field in an MMA XX3 form instruction. This is split. | |
3157 | This is like XA6a, but must be even. */ | |
3158 | #define XA6ap XA6a + 1 | |
3159 | { 0x3e, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR }, | |
3160 | ||
b80c7270 | 3161 | /* The XB field in an XX2 or XX3 form instruction. This is split. */ |
aa3c112f | 3162 | #define XB6 XA6ap + 1 |
b80c7270 | 3163 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, |
e3c2f928 | 3164 | |
aa3c112f AM |
3165 | /* The XB field in an XX3 form instruction. This is split and |
3166 | must not overlap with the ACC operand. */ | |
3167 | #define XB6a XB6 + 1 | |
3168 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6a, extract_xb6a, PPC_OPERAND_VSR }, | |
3169 | ||
98553ad3 PB |
3170 | /* The XA and XB fields in an XX3 form instruction when they must be the same. |
3171 | This is used in extended mnemonics like xvmovdp. This is split. */ | |
aa3c112f | 3172 | #define XAB6 XB6a + 1 |
98553ad3 | 3173 | { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR }, |
e3c2f928 | 3174 | |
b80c7270 | 3175 | /* The XC field in an XX4 form instruction. This is split. */ |
98553ad3 | 3176 | #define XC6 XAB6 + 1 |
b80c7270 | 3177 | { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, |
e3c2f928 | 3178 | |
b80c7270 AM |
3179 | /* The DM or SHW field in an XX3 form instruction. */ |
3180 | #define DM XC6 + 1 | |
3181 | #define SHW DM | |
3182 | { 0x3, 8, NULL, NULL, 0 }, | |
e3c2f928 | 3183 | |
b80c7270 AM |
3184 | /* The DM field in an extended mnemonic XX3 form instruction. */ |
3185 | #define DMEX DM + 1 | |
3186 | { 0x3, 8, insert_dm, extract_dm, 0 }, | |
e3c2f928 | 3187 | |
b80c7270 AM |
3188 | /* The UIM field in an XX2 form instruction. */ |
3189 | #define UIM DMEX + 1 | |
3190 | /* The 2-bit UIMM field in a VX form instruction. */ | |
3191 | #define UIMM2 UIM | |
3192 | /* The 2-bit L field in a darn instruction. */ | |
3193 | #define LRAND UIM | |
3194 | { 0x3, 16, NULL, NULL, 0 }, | |
e3c2f928 | 3195 | |
b80c7270 AM |
3196 | #define ERAT_T UIM + 1 |
3197 | { 0x7, 21, NULL, NULL, 0 }, | |
e3c2f928 | 3198 | |
b80c7270 AM |
3199 | #define IH ERAT_T + 1 |
3200 | { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
e3c2f928 | 3201 | |
3d205eb4 PB |
3202 | /* The 2-bit SC or PL field in an X form instruction. */ |
3203 | #define SC2 IH + 1 | |
3204 | #define PL SC2 | |
3205 | { 0x3, 16, insert_pl, extract_pl, PPC_OPERAND_OPTIONAL }, | |
3206 | ||
b80c7270 | 3207 | /* The 8-bit IMM8 field in a XX1 form instruction. */ |
3d205eb4 | 3208 | #define IMM8 SC2 + 1 |
b80c7270 | 3209 | { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, |
e3c2f928 | 3210 | |
b80c7270 AM |
3211 | #define VX_OFF IMM8 + 1 |
3212 | { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 }, | |
74081948 AF |
3213 | |
3214 | #define VX_OFF_SPE2 VX_OFF + 1 | |
3215 | { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 }, | |
3216 | ||
3217 | #define BBB VX_OFF_SPE2 + 1 | |
3218 | { 0x7, 13, NULL, NULL, 0 }, | |
3219 | ||
3220 | #define DDD BBB + 1 | |
3221 | #define VX_MASK_DDD (VX_MASK & ~0x1) | |
3222 | { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, | |
3223 | ||
3224 | #define HH DDD + 1 | |
3225 | { 0x3, 13, NULL, NULL, 0 }, | |
b80c7270 AM |
3226 | }; |
3227 | ||
3228 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | |
3229 | / sizeof (powerpc_operands[0])); | |
252b5132 RH |
3230 | \f |
3231 | /* Macros used to form opcodes. */ | |
3232 | ||
3233 | /* The main opcode. */ | |
0f873fd5 | 3234 | #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26) |
252b5132 RH |
3235 | #define OP_MASK OP (0x3f) |
3236 | ||
dd7efa79 PB |
3237 | /* The prefix opcode. */ |
3238 | #define PREFIX_OP (1ULL << 58) | |
3239 | ||
3240 | /* The 2-bit prefix form. */ | |
3241 | #define PREFIX_FORM(x) ((x & 3ULL) << 56) | |
3242 | ||
3243 | #define SUFFIX_MASK ((1ULL << 32) - 1) | |
3244 | #define PREFIX_MASK (SUFFIX_MASK << 32) | |
3245 | ||
8acf1435 PB |
3246 | /* Prefix insn, eight byte load/store form 8LS. */ |
3247 | #define P8LS (PREFIX_OP | PREFIX_FORM (0)) | |
3248 | ||
6edbfd3b AM |
3249 | /* Prefix insn, eight byte register to register form 8RR. */ |
3250 | #define P8RR (PREFIX_OP | PREFIX_FORM (1)) | |
3251 | ||
8acf1435 PB |
3252 | /* Prefix insn, modified load/store form MLS. */ |
3253 | #define PMLS (PREFIX_OP | PREFIX_FORM (2)) | |
3254 | ||
dd7efa79 PB |
3255 | /* Prefix insn, modified register to register form MRR. */ |
3256 | #define PMRR (PREFIX_OP | PREFIX_FORM (3)) | |
3257 | ||
aa3c112f AM |
3258 | /* Prefix insn, modified masked immediate register to register form MMIRR. */ |
3259 | #define PMMIRR (PREFIX_OP | PREFIX_FORM (3) | (9ULL << 52)) | |
3260 | ||
8acf1435 PB |
3261 | /* An 8-byte D form prefix instruction. */ |
3262 | #define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK) | |
3263 | ||
3264 | /* The same as P_D_MASK, but with the RA and PCREL fields specified. */ | |
3265 | #define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK) | |
3266 | ||
aa3c112f AM |
3267 | /* Mask for prefix X form instructions. */ |
3268 | #define P_X_MASK (PREFIX_MASK | X_MASK) | |
3269 | #define P_XX1_MASK (PREFIX_MASK | XX1_MASK) | |
3270 | ||
6edbfd3b AM |
3271 | /* Mask for prefix vector permute insns. */ |
3272 | #define P_XX4_MASK (PREFIX_MASK | XX4_MASK) | |
3273 | #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32)) | |
ec40e91c | 3274 | #define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32)) |
6edbfd3b | 3275 | |
aa3c112f AM |
3276 | /* MMIRR:XX3-form 8-byte outer product instructions. */ |
3277 | #define P_GER_MASK ((-1ULL << 40) | XX3_MASK | (3 << 21) | 1) | |
3278 | #define P_GER2_MASK (P_GER_MASK & ~(3ULL << 46)) | |
3279 | #define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44)) | |
3280 | #define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40)) | |
3281 | #define P_GER64_MASK (P_GER_MASK | (3ULL << 32)) | |
3282 | ||
6edbfd3b AM |
3283 | /* Vector splat immediate op. */ |
3284 | #define VSOP(op, xop) (OP (op) | (xop << 17)) | |
3285 | #define P_VS_MASK ((-1ULL << 48) | VSOP (0x3f, 0xf)) | |
3286 | #define P_VSI_MASK ((-1ULL << 48) | VSOP (0x3f, 0xe)) | |
3287 | ||
252b5132 RH |
3288 | /* The main opcode combined with a trap code in the TO field of a D |
3289 | form instruction. Used for extended mnemonics for the trap | |
3290 | instructions. */ | |
0f873fd5 | 3291 | #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21)) |
252b5132 RH |
3292 | #define OPTO_MASK (OP_MASK | TO_MASK) |
3293 | ||
3294 | /* The main opcode combined with a comparison size bit in the L field | |
3295 | of a D form or X form instruction. Used for extended mnemonics for | |
3296 | the comparison instructions. */ | |
0f873fd5 | 3297 | #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21)) |
252b5132 RH |
3298 | #define OPL_MASK OPL (0x3f,1) |
3299 | ||
b9c361e0 JL |
3300 | /* The main opcode combined with an update code in D form instruction. |
3301 | Used for extended mnemonics for VLE memory instructions. */ | |
0f873fd5 | 3302 | #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8)) |
b9c361e0 JL |
3303 | #define OPVUP_MASK OPVUP (0x3f, 0xff) |
3304 | ||
b80c7270 AM |
3305 | /* The main opcode combined with an update code and the RT fields |
3306 | specified in D form instruction. Used for VLE volatile context | |
3307 | save/restore instructions. */ | |
3308 | #define OPVUPRT(x,vup,rt) \ | |
3309 | (OPVUP (x, vup) \ | |
0f873fd5 | 3310 | | ((((uint64_t)(rt)) & 0x1f) << 21)) |
dfdaec14 AJ |
3311 | #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) |
3312 | ||
252b5132 | 3313 | /* An A form instruction. */ |
b80c7270 AM |
3314 | #define A(op, xop, rc) \ |
3315 | (OP (op) \ | |
0f873fd5 PB |
3316 | | ((((uint64_t)(xop)) & 0x1f) << 1) \ |
3317 | | (((uint64_t)(rc)) & 1)) | |
252b5132 RH |
3318 | #define A_MASK A (0x3f, 0x1f, 1) |
3319 | ||
3320 | /* An A_MASK with the FRB field fixed. */ | |
3321 | #define AFRB_MASK (A_MASK | FRB_MASK) | |
3322 | ||
3323 | /* An A_MASK with the FRC field fixed. */ | |
3324 | #define AFRC_MASK (A_MASK | FRC_MASK) | |
3325 | ||
3326 | /* An A_MASK with the FRA and FRC fields fixed. */ | |
3327 | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) | |
3328 | ||
702f0fb4 | 3329 | /* An AFRAFRC_MASK, but with L bit clear. */ |
0f873fd5 | 3330 | #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16)) |
702f0fb4 | 3331 | |
252b5132 | 3332 | /* A B form instruction. */ |
b80c7270 AM |
3333 | #define B(op, aa, lk) \ |
3334 | (OP (op) \ | |
0f873fd5 | 3335 | | ((((uint64_t)(aa)) & 1) << 1) \ |
b80c7270 | 3336 | | ((lk) & 1)) |
252b5132 RH |
3337 | #define B_MASK B (0x3f, 1, 1) |
3338 | ||
b9c361e0 | 3339 | /* A BD8 form instruction. This is a 16-bit instruction. */ |
b80c7270 | 3340 | #define BD8(op, aa, lk) \ |
0f873fd5 | 3341 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 AM |
3342 | | (((aa) & 1) << 9) \ |
3343 | | (((lk) & 1) << 8)) | |
b9c361e0 JL |
3344 | #define BD8_MASK BD8 (0x3f, 1, 1) |
3345 | ||
3346 | /* Another BD8 form instruction. This is a 16-bit instruction. */ | |
0f873fd5 | 3347 | #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11) |
b9c361e0 JL |
3348 | #define BD8IO_MASK BD8IO (0x1f) |
3349 | ||
3350 | /* A BD8 form instruction for simplified mnemonics. */ | |
3351 | #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) | |
3352 | /* A mask that excludes BO32 and BI32. */ | |
3353 | #define EBD8IO1_MASK 0xf800 | |
3354 | /* A mask that includes BO32 and excludes BI32. */ | |
3355 | #define EBD8IO2_MASK 0xfc00 | |
3356 | /* A mask that include BO32 AND BI32. */ | |
3357 | #define EBD8IO3_MASK 0xff00 | |
3358 | ||
3359 | /* A BD15 form instruction. */ | |
b80c7270 AM |
3360 | #define BD15(op, aa, lk) \ |
3361 | (OP (op) \ | |
0f873fd5 | 3362 | | ((((uint64_t)(aa)) & 0xf) << 22) \ |
b80c7270 | 3363 | | ((lk) & 1)) |
b9c361e0 JL |
3364 | #define BD15_MASK BD15 (0x3f, 0xf, 1) |
3365 | ||
3366 | /* A BD15 form instruction for extended conditional branch mnemonics. */ | |
b80c7270 | 3367 | #define EBD15(op, aa, bo, lk) \ |
2480b6fa | 3368 | (((op) & 0x3fu) << 26) \ |
b80c7270 AM |
3369 | | (((aa) & 0xf) << 22) \ |
3370 | | (((bo) & 0x3) << 20) \ | |
3371 | | ((lk) & 1) | |
b9c361e0 JL |
3372 | #define EBD15_MASK 0xfff00001 |
3373 | ||
b80c7270 AM |
3374 | /* A BD15 form instruction for extended conditional branch mnemonics |
3375 | with BI. */ | |
3376 | #define EBD15BI(op, aa, bo, bi, lk) \ | |
2480b6fa | 3377 | ((((op) & 0x3fu) << 26) \ |
b80c7270 AM |
3378 | | (((aa) & 0xf) << 22) \ |
3379 | | (((bo) & 0x3) << 20) \ | |
3380 | | (((bi) & 0x3) << 16) \ | |
3381 | | ((lk) & 1)) | |
3382 | ||
b9c361e0 JL |
3383 | #define EBD15BI_MASK 0xfff30001 |
3384 | ||
3385 | /* A BD24 form instruction. */ | |
b80c7270 AM |
3386 | #define BD24(op, aa, lk) \ |
3387 | (OP (op) \ | |
0f873fd5 | 3388 | | ((((uint64_t)(aa)) & 1) << 25) \ |
b80c7270 | 3389 | | ((lk) & 1)) |
b9c361e0 JL |
3390 | #define BD24_MASK BD24 (0x3f, 1, 1) |
3391 | ||
252b5132 | 3392 | /* A B form instruction setting the BO field. */ |
b80c7270 AM |
3393 | #define BBO(op, bo, aa, lk) \ |
3394 | (B ((op), (aa), (lk)) \ | |
0f873fd5 | 3395 | | ((((uint64_t)(bo)) & 0x1f) << 21)) |
252b5132 RH |
3396 | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
3397 | ||
3398 | /* A BBO_MASK with the y bit of the BO field removed. This permits | |
3399 | matching a conditional branch regardless of the setting of the y | |
94efba12 | 3400 | bit. Similarly for the 'at' bits used for power4 branch hints. */ |
0f873fd5 PB |
3401 | #define Y_MASK (((uint64_t) 1) << 21) |
3402 | #define AT1_MASK (((uint64_t) 3) << 21) | |
3403 | #define AT2_MASK (((uint64_t) 9) << 21) | |
802a735e AM |
3404 | #define BBOY_MASK (BBO_MASK &~ Y_MASK) |
3405 | #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) | |
252b5132 RH |
3406 | |
3407 | /* A B form instruction setting the BO field and the condition bits of | |
3408 | the BI field. */ | |
3409 | #define BBOCB(op, bo, cb, aa, lk) \ | |
0f873fd5 | 3410 | (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16)) |
252b5132 RH |
3411 | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
3412 | ||
3413 | /* A BBOCB_MASK with the y bit of the BO field removed. */ | |
3414 | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) | |
802a735e AM |
3415 | #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
3416 | #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) | |
252b5132 RH |
3417 | |
3418 | /* A BBOYCB_MASK in which the BI field is fixed. */ | |
3419 | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) | |
802a735e | 3420 | #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
252b5132 | 3421 | |
b9c361e0 | 3422 | /* A VLE C form instruction. */ |
0f873fd5 | 3423 | #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1)) |
b9c361e0 | 3424 | #define C_LK_MASK C_LK(0x7fff, 1) |
0f873fd5 | 3425 | #define C(x) ((((uint64_t)(x)) & 0xffff)) |
b9c361e0 JL |
3426 | #define C_MASK C(0xffff) |
3427 | ||
23976049 | 3428 | /* An Context form instruction. */ |
0f873fd5 | 3429 | #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7)) |
fdd12ef3 | 3430 | #define CTX_MASK CTX(0x3f, 0x7) |
23976049 EZ |
3431 | |
3432 | /* An User Context form instruction. */ | |
0f873fd5 | 3433 | #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) |
fdd12ef3 | 3434 | #define UCTX_MASK UCTX(0x3f, 0x1f) |
23976049 | 3435 | |
252b5132 RH |
3436 | /* The main opcode mask with the RA field clear. */ |
3437 | #define DRA_MASK (OP_MASK | RA_MASK) | |
3438 | ||
a680de9a PB |
3439 | /* A DQ form VSX instruction. */ |
3440 | #define DQX(op, xop) (OP (op) | ((xop) & 0x7)) | |
3441 | #define DQX_MASK DQX (0x3f, 7) | |
3442 | ||
94ba9882 AM |
3443 | /* A DQ form VSX vector paired instruction. */ |
3444 | #define DQXP(op, xop) (OP (op) | ((xop) & 0xf)) | |
3445 | #define DQXP_MASK DQXP (0x3f, 0xf) | |
3446 | ||
252b5132 RH |
3447 | /* A DS form instruction. */ |
3448 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) | |
3449 | #define DS_MASK DSO (0x3f, 3) | |
3450 | ||
a680de9a | 3451 | /* An DX form instruction. */ |
0f873fd5 | 3452 | #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
a680de9a | 3453 | #define DX_MASK DX (0x3f, 0x1f) |
1437d063 PB |
3454 | /* An DX form instruction with the D bits specified. */ |
3455 | #define NODX_MASK (DX_MASK | 0x1fffc1) | |
a680de9a | 3456 | |
23976049 | 3457 | /* An EVSEL form instruction. */ |
0f873fd5 | 3458 | #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3) |
23976049 EZ |
3459 | #define EVSEL_MASK EVSEL(0x3f, 0xff) |
3460 | ||
b9c361e0 | 3461 | /* An IA16 form instruction. */ |
0f873fd5 | 3462 | #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
3463 | #define IA16_MASK IA16(0x3f, 0x1f) |
3464 | ||
3465 | /* An I16A form instruction. */ | |
0f873fd5 | 3466 | #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
3467 | #define I16A_MASK I16A(0x3f, 0x1f) |
3468 | ||
3469 | /* An I16L form instruction. */ | |
0f873fd5 | 3470 | #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
3471 | #define I16L_MASK I16L(0x3f, 0x1f) |
3472 | ||
3473 | /* An IM7 form instruction. */ | |
0f873fd5 | 3474 | #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11) |
b9c361e0 JL |
3475 | #define IM7_MASK IM7(0x1f) |
3476 | ||
252b5132 RH |
3477 | /* An M form instruction. */ |
3478 | #define M(op, rc) (OP (op) | ((rc) & 1)) | |
3479 | #define M_MASK M (0x3f, 1) | |
3480 | ||
b9c361e0 | 3481 | /* An LI20 form instruction. */ |
0f873fd5 | 3482 | #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15) |
b9c361e0 JL |
3483 | #define LI20_MASK LI20(0x3f, 0x1) |
3484 | ||
252b5132 | 3485 | /* An M form instruction with the ME field specified. */ |
b80c7270 AM |
3486 | #define MME(op, me, rc) \ |
3487 | (M ((op), (rc)) \ | |
0f873fd5 | 3488 | | ((((uint64_t)(me)) & 0x1f) << 1)) |
252b5132 RH |
3489 | |
3490 | /* An M_MASK with the MB and ME fields fixed. */ | |
3491 | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) | |
3492 | ||
3493 | /* An M_MASK with the SH and ME fields fixed. */ | |
3494 | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) | |
3495 | ||
3496 | /* An MD form instruction. */ | |
b80c7270 AM |
3497 | #define MD(op, xop, rc) \ |
3498 | (OP (op) \ | |
0f873fd5 | 3499 | | ((((uint64_t)(xop)) & 0x7) << 2) \ |
b80c7270 | 3500 | | ((rc) & 1)) |
252b5132 RH |
3501 | #define MD_MASK MD (0x3f, 0x7, 1) |
3502 | ||
3503 | /* An MD_MASK with the MB field fixed. */ | |
3504 | #define MDMB_MASK (MD_MASK | MB6_MASK) | |
3505 | ||
3506 | /* An MD_MASK with the SH field fixed. */ | |
3507 | #define MDSH_MASK (MD_MASK | SH6_MASK) | |
3508 | ||
3509 | /* An MDS form instruction. */ | |
b80c7270 AM |
3510 | #define MDS(op, xop, rc) \ |
3511 | (OP (op) \ | |
0f873fd5 | 3512 | | ((((uint64_t)(xop)) & 0xf) << 1) \ |
b80c7270 | 3513 | | ((rc) & 1)) |
252b5132 RH |
3514 | #define MDS_MASK MDS (0x3f, 0xf, 1) |
3515 | ||
3516 | /* An MDS_MASK with the MB field fixed. */ | |
3517 | #define MDSMB_MASK (MDS_MASK | MB6_MASK) | |
3518 | ||
3519 | /* An SC form instruction. */ | |
b80c7270 AM |
3520 | #define SC(op, sa, lk) \ |
3521 | (OP (op) \ | |
0f873fd5 | 3522 | | ((((uint64_t)(sa)) & 1) << 1) \ |
b80c7270 AM |
3523 | | ((lk) & 1)) |
3524 | #define SC_MASK \ | |
3525 | (OP_MASK \ | |
0f873fd5 PB |
3526 | | (((uint64_t) 0x3ff) << 16) \ |
3527 | | (((uint64_t) 1) << 1) \ | |
b80c7270 | 3528 | | 1) |
252b5132 | 3529 | |
b9c361e0 | 3530 | /* An SCI8 form instruction. */ |
0f873fd5 | 3531 | #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11)) |
b9c361e0 JL |
3532 | #define SCI8_MASK SCI8(0x3f, 0x1f) |
3533 | ||
3534 | /* An SCI8 form instruction. */ | |
b80c7270 AM |
3535 | #define SCI8BF(op, fop, xop) \ |
3536 | (OP (op) \ | |
0f873fd5 | 3537 | | ((((uint64_t)(xop)) & 0x1f) << 11) \ |
b80c7270 | 3538 | | (((fop) & 7) << 23)) |
b9c361e0 JL |
3539 | #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) |
3540 | ||
3541 | /* An SD4 form instruction. This is a 16-bit instruction. */ | |
0f873fd5 | 3542 | #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12) |
b9c361e0 JL |
3543 | #define SD4_MASK SD4(0xf) |
3544 | ||
3545 | /* An SE_IM5 form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 3546 | #define SE_IM5(op, xop) \ |
0f873fd5 | 3547 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 3548 | | (((xop) & 0x1) << 9)) |
b9c361e0 JL |
3549 | #define SE_IM5_MASK SE_IM5(0x3f, 1) |
3550 | ||
3551 | /* An SE_R form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 3552 | #define SE_R(op, xop) \ |
0f873fd5 | 3553 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 3554 | | (((xop) & 0x3f) << 4)) |
b9c361e0 JL |
3555 | #define SE_R_MASK SE_R(0x3f, 0x3f) |
3556 | ||
3557 | /* An SE_RR form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 3558 | #define SE_RR(op, xop) \ |
0f873fd5 | 3559 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 3560 | | (((xop) & 0x3) << 8)) |
b9c361e0 JL |
3561 | #define SE_RR_MASK SE_RR(0x3f, 3) |
3562 | ||
3563 | /* A VX form instruction. */ | |
0f873fd5 | 3564 | #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) |
786e2c0f | 3565 | |
112290ab | 3566 | /* The mask for an VX form instruction. */ |
786e2c0f C |
3567 | #define VX_MASK VX(0x3f, 0x7ff) |
3568 | ||
e3c2f928 | 3569 | /* A VX LSP form instruction. */ |
0f873fd5 | 3570 | #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff)) |
e3c2f928 AF |
3571 | |
3572 | /* The mask for an VX LSP form instruction. */ | |
3573 | #define VX_LSP_MASK VX_LSP(0x3f, 0xffff) | |
3574 | #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc) | |
3575 | ||
74081948 AF |
3576 | /* Additional format of VX SPE2 form instruction. */ |
3577 | #define VX_RA_CONST(op, xop, bits11_15) \ | |
3578 | (OP (op) \ | |
0f873fd5 PB |
3579 | | (((uint64_t)(bits11_15) & 0x1f) << 16) \ |
3580 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3581 | #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f) |
3582 | ||
3583 | #define VX_RB_CONST(op, xop, bits16_20) \ | |
3584 | (OP (op) \ | |
0f873fd5 PB |
3585 | | (((uint64_t)(bits16_20) & 0x1f) << 11) \ |
3586 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3587 | #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f) |
3588 | ||
3589 | #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8) | |
3590 | ||
3591 | #define VX_SPE_CRFD(op, xop, bits9_10) \ | |
3592 | (OP (op) \ | |
0f873fd5 PB |
3593 | | (((uint64_t)(bits9_10) & 0x3) << 21) \ |
3594 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3595 | #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3) |
3596 | ||
3597 | #define VX_SPE2_CLR(op, xop, bit16) \ | |
3598 | (OP (op) \ | |
0f873fd5 PB |
3599 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3600 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3601 | #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1) |
3602 | ||
3603 | #define VX_SPE2_SPLATB(op, xop, bits19_20) \ | |
3604 | (OP (op) \ | |
0f873fd5 PB |
3605 | | (((uint64_t)(bits19_20) & 0x3) << 11) \ |
3606 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3607 | #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3) |
3608 | ||
3609 | #define VX_SPE2_OCTET(op, xop, bits16_17) \ | |
3610 | (OP (op) \ | |
0f873fd5 PB |
3611 | | (((uint64_t)(bits16_17) & 0x3) << 14) \ |
3612 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3613 | #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7) |
3614 | ||
3615 | #define VX_SPE2_DDHH(op, xop, bit16) \ | |
3616 | (OP (op) \ | |
0f873fd5 PB |
3617 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3618 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3619 | #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1) |
3620 | ||
3621 | #define VX_SPE2_HH(op, xop, bit16, bits19_20) \ | |
3622 | (OP (op) \ | |
0f873fd5 PB |
3623 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3624 | | (((uint64_t)(bits19_20) & 0x3) << 11) \ | |
3625 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3626 | #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3) |
3627 | ||
3628 | #define VX_SPE2_EVMAR(op, xop) \ | |
3629 | (OP (op) \ | |
0f873fd5 PB |
3630 | | ((uint64_t)(0x1) << 11) \ |
3631 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3632 | #define VX_SPE2_EVMAR_MASK \ |
3633 | (VX_SPE2_EVMAR(0x3f, 0x7ff) \ | |
0f873fd5 | 3634 | | ((uint64_t)(0x1) << 11)) |
74081948 | 3635 | |
fb048c26 PB |
3636 | /* A VX_MASK with the VA field fixed. */ |
3637 | #define VXVA_MASK (VX_MASK | (0x1f << 16)) | |
3638 | ||
3639 | /* A VX_MASK with the VB field fixed. */ | |
3640 | #define VXVB_MASK (VX_MASK | (0x1f << 11)) | |
3641 | ||
3642 | /* A VX_MASK with the VA and VB fields fixed. */ | |
3643 | #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) | |
3644 | ||
3645 | /* A VX_MASK with the VD and VA fields fixed. */ | |
3646 | #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) | |
3647 | ||
3648 | /* A VX_MASK with a UIMM4 field. */ | |
3649 | #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) | |
3650 | ||
3651 | /* A VX_MASK with a UIMM3 field. */ | |
3652 | #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) | |
3653 | ||
3654 | /* A VX_MASK with a UIMM2 field. */ | |
3655 | #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) | |
3656 | ||
c0637f3a PB |
3657 | /* A VX_MASK with a PS field. */ |
3658 | #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) | |
3659 | ||
a680de9a | 3660 | /* A VX_MASK with the VA field fixed with a PS field. */ |
fdefed7c AM |
3661 | #define VXVAPS_MASK (VXVA_MASK & ~(0x1 << 9)) |
3662 | ||
3663 | /* A VX_MASK with the VA field fixed with a MP field. */ | |
3664 | #define VXVAM_MASK (VXVA_MASK & ~(0x1 << 16)) | |
a680de9a | 3665 | |
c7d7aea2 AM |
3666 | /* A VX_MASK for instructions using a BF field. */ |
3667 | #define VXBF_MASK (VX_MASK | (3 << 21)) | |
3668 | ||
6edbfd3b AM |
3669 | /* A VX_MASK for instructions with an RC field. */ |
3670 | #define VXRC_MASK (VX_MASK & ~(0x1f << 6)) | |
3671 | ||
3672 | /* A VX_MASK for instructions with a SH field. */ | |
3673 | #define VXSH_MASK (VX_MASK & ~(0x7 << 6)) | |
3674 | ||
b9c361e0 | 3675 | /* A VA form instruction. */ |
0f873fd5 | 3676 | #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f)) |
786e2c0f | 3677 | |
112290ab | 3678 | /* The mask for an VA form instruction. */ |
2613489e | 3679 | #define VXA_MASK VXA(0x3f, 0x3f) |
786e2c0f | 3680 | |
382c72e9 PB |
3681 | /* A VXA_MASK with a SHB field. */ |
3682 | #define VXASHB_MASK (VXA_MASK | (1 << 10)) | |
3683 | ||
b9c361e0 | 3684 | /* A VXR form instruction. */ |
b80c7270 AM |
3685 | #define VXR(op, xop, rc) \ |
3686 | (OP (op) \ | |
0f873fd5 PB |
3687 | | (((uint64_t)(rc) & 1) << 10) \ |
3688 | | (((uint64_t)(xop)) & 0x3ff)) | |
786e2c0f | 3689 | |
112290ab | 3690 | /* The mask for a VXR form instruction. */ |
786e2c0f C |
3691 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
3692 | ||
a680de9a PB |
3693 | /* A VX form instruction with a VA tertiary opcode. */ |
3694 | #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) | |
3695 | ||
0f873fd5 | 3696 | #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
6fd3a02d PB |
3697 | #define VXASH_MASK VXASH (0x3f, 0x1f) |
3698 | ||
252b5132 | 3699 | /* An X form instruction. */ |
0f873fd5 | 3700 | #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) |
252b5132 | 3701 | |
a680de9a PB |
3702 | /* A X form instruction for Quad-Precision FP Instructions. */ |
3703 | #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) | |
3704 | ||
b9c361e0 | 3705 | /* An EX form instruction. */ |
0f873fd5 | 3706 | #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) |
b9c361e0 JL |
3707 | |
3708 | /* The mask for an EX form instruction. */ | |
3709 | #define EX_MASK EX (0x3f, 0x7ff) | |
3710 | ||
066be9f7 | 3711 | /* An XX2 form instruction. */ |
0f873fd5 | 3712 | #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2)) |
066be9f7 | 3713 | |
a680de9a PB |
3714 | /* A XX2 form instruction with the VA bits specified. */ |
3715 | #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) | |
3716 | ||
9b4e5766 | 3717 | /* An XX3 form instruction. */ |
0f873fd5 | 3718 | #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3)) |
9b4e5766 | 3719 | |
066be9f7 | 3720 | /* An XX3 form instruction with the RC bit specified. */ |
b80c7270 AM |
3721 | #define XX3RC(op, xop, rc) \ |
3722 | (OP (op) \ | |
0f873fd5 PB |
3723 | | (((uint64_t)(rc) & 1) << 10) \ |
3724 | | ((((uint64_t)(xop)) & 0x7f) << 3)) | |
066be9f7 PB |
3725 | |
3726 | /* An XX4 form instruction. */ | |
0f873fd5 | 3727 | #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4)) |
9b4e5766 | 3728 | |
702f0fb4 | 3729 | /* A Z form instruction. */ |
0f873fd5 | 3730 | #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1)) |
702f0fb4 | 3731 | |
252b5132 RH |
3732 | /* An X form instruction with the RC bit specified. */ |
3733 | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) | |
3734 | ||
a680de9a PB |
3735 | /* A X form instruction for Quad-Precision FP Instructions with RC bit. */ |
3736 | #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) | |
3737 | ||
6fd3a02d | 3738 | /* An X form instruction with the RA bits specified as two ops. */ |
b80c7270 AM |
3739 | #define XMMF(op, xop, mop0, mop1) \ |
3740 | (X ((op), (xop)) \ | |
3741 | | ((mop0) & 3) << 19 \ | |
3742 | | ((mop1) & 7) << 16) | |
6fd3a02d | 3743 | |
702f0fb4 PB |
3744 | /* A Z form instruction with the RC bit specified. */ |
3745 | #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) | |
3746 | ||
252b5132 RH |
3747 | /* The mask for an X form instruction. */ |
3748 | #define X_MASK XRC (0x3f, 0x3ff, 1) | |
3749 | ||
a680de9a PB |
3750 | /* The mask for an X form instruction with the BF bits specified. */ |
3751 | #define XBF_MASK (X_MASK | (3 << 21)) | |
3752 | ||
b80c7270 AM |
3753 | /* An X form wait instruction with everything filled in except the WC |
3754 | field. */ | |
e0d602ec BE |
3755 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
3756 | ||
3d205eb4 PB |
3757 | /* An X form wait instruction with everything filled in except the WC |
3758 | and PL fields. */ | |
3759 | #define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK) | |
3760 | ||
9b4e5766 PB |
3761 | /* The mask for an XX1 form instruction. */ |
3762 | #define XX1_MASK X (0x3f, 0x3ff) | |
3763 | ||
c0637f3a PB |
3764 | /* An XX1_MASK with the RB field fixed. */ |
3765 | #define XX1RB_MASK (XX1_MASK | RB_MASK) | |
3766 | ||
066be9f7 PB |
3767 | /* The mask for an XX2 form instruction. */ |
3768 | #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) | |
3769 | ||
3770 | /* The mask for an XX2 form instruction with the UIM bits specified. */ | |
3771 | #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) | |
3772 | ||
a680de9a PB |
3773 | /* The mask for an XX2 form instruction with the 4 UIM bits specified. */ |
3774 | #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) | |
3775 | ||
066be9f7 PB |
3776 | /* The mask for an XX2 form instruction with the BF bits specified. */ |
3777 | #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) | |
3778 | ||
b80c7270 AM |
3779 | /* The mask for an XX2 form instruction with the BF and DCMX bits |
3780 | specified. */ | |
a680de9a PB |
3781 | #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) |
3782 | ||
b80c7270 AM |
3783 | /* The mask for an XX2 form instruction with a split DCMX bits |
3784 | specified. */ | |
a680de9a PB |
3785 | #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) |
3786 | ||
9b4e5766 PB |
3787 | /* The mask for an XX3 form instruction. */ |
3788 | #define XX3_MASK XX3 (0x3f, 0xff) | |
3789 | ||
066be9f7 PB |
3790 | /* The mask for an XX3 form instruction with the BF bits specified. */ |
3791 | #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) | |
3792 | ||
b80c7270 AM |
3793 | /* The mask for an XX3 form instruction with the DM or SHW bits |
3794 | specified. */ | |
9b4e5766 | 3795 | #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) |
066be9f7 PB |
3796 | #define XX3SHW_MASK XX3DM_MASK |
3797 | ||
3798 | /* The mask for an XX4 form instruction. */ | |
3799 | #define XX4_MASK XX4 (0x3f, 0x3) | |
3800 | ||
b80c7270 AM |
3801 | /* An X form wait instruction with everything filled in except the WC |
3802 | field. */ | |
066be9f7 | 3803 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
9b4e5766 | 3804 | |
6fd3a02d PB |
3805 | /* The mask for an XMMF form instruction. */ |
3806 | #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) | |
3807 | ||
702f0fb4 PB |
3808 | /* The mask for a Z form instruction. */ |
3809 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) | |
0bbdef92 | 3810 | #define Z2_MASK ZRC (0x3f, 0xff, 1) |
702f0fb4 | 3811 | |
a680de9a | 3812 | /* An X_MASK with the RA/VA field fixed. */ |
252b5132 | 3813 | #define XRA_MASK (X_MASK | RA_MASK) |
a680de9a | 3814 | #define XVA_MASK XRA_MASK |
252b5132 | 3815 | |
a680de9a | 3816 | /* An XRA_MASK with the A_L/W field clear. */ |
0f873fd5 | 3817 | #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16)) |
a680de9a | 3818 | #define XRLA_MASK XWRA_MASK |
ea192fa3 | 3819 | |
252b5132 RH |
3820 | /* An X_MASK with the RB field fixed. */ |
3821 | #define XRB_MASK (X_MASK | RB_MASK) | |
3822 | ||
3823 | /* An X_MASK with the RT field fixed. */ | |
3824 | #define XRT_MASK (X_MASK | RT_MASK) | |
3825 | ||
3d205eb4 | 3826 | /* An XRT_MASK mask with the 2 L bits clear. */ |
0f873fd5 | 3827 | #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21)) |
702f0fb4 | 3828 | |
3d205eb4 PB |
3829 | /* An XRT_MASK mask with the 3 L bits clear. */ |
3830 | #define XL3RT_MASK (XRT_MASK & ~((uint64_t) 0x7 << 21)) | |
3831 | ||
252b5132 RH |
3832 | /* An X_MASK with the RA and RB fields fixed. */ |
3833 | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) | |
3834 | ||
a680de9a PB |
3835 | /* An XBF_MASK with the RA and RB fields fixed. */ |
3836 | #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) | |
3837 | ||
112290ab | 3838 | /* An XRARB_MASK, but with the L bit clear. */ |
0f873fd5 | 3839 | #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16)) |
5ae2e65e | 3840 | |
a680de9a | 3841 | /* An XRARB_MASK, but with the L bits in a darn instruction clear. */ |
0f873fd5 | 3842 | #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16)) |
a680de9a | 3843 | |
252b5132 RH |
3844 | /* An X_MASK with the RT and RA fields fixed. */ |
3845 | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) | |
3846 | ||
5817ffd1 PB |
3847 | /* An X_MASK with the RT and RB fields fixed. */ |
3848 | #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) | |
3849 | ||
98acc1c5 | 3850 | /* An XRTRA_MASK, but with L bit clear. */ |
0f873fd5 | 3851 | #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21)) |
98acc1c5 | 3852 | |
5817ffd1 PB |
3853 | /* An X_MASK with the RT, RA and RB fields fixed. */ |
3854 | #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) | |
3855 | ||
3856 | /* An XRTRARB_MASK, but with L bit clear. */ | |
0f873fd5 | 3857 | #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21)) |
5817ffd1 PB |
3858 | |
3859 | /* An XRTRARB_MASK, but with A bit clear. */ | |
0f873fd5 | 3860 | #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25)) |
5817ffd1 PB |
3861 | |
3862 | /* An XRTRARB_MASK, but with BF bits clear. */ | |
0f873fd5 | 3863 | #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23)) |
5817ffd1 | 3864 | |
f3806e43 | 3865 | /* An X form instruction with the L bit specified. */ |
b80c7270 AM |
3866 | #define XOPL(op, xop, l) \ |
3867 | (X ((op), (xop)) \ | |
0f873fd5 | 3868 | | ((((uint64_t)(l)) & 1) << 21)) |
252b5132 | 3869 | |
3d205eb4 | 3870 | /* An X form instruction with the 2 L bits specified. */ |
b80c7270 AM |
3871 | #define XOPL2(op, xop, l) \ |
3872 | (X ((op), (xop)) \ | |
0f873fd5 | 3873 | | ((((uint64_t)(l)) & 3) << 21)) |
e0d602ec | 3874 | |
3d205eb4 PB |
3875 | /* An X form instruction with the 3 L bits specified. */ |
3876 | #define XOPL3(op, xop, l) \ | |
3877 | (X ((op), (xop)) \ | |
3878 | | ((((uint64_t)(l)) & 7) << 21)) | |
3879 | ||
3880 | /* An X form instruction with the WC and PL bits specified. */ | |
3881 | #define XWCPL(op, xop, wc, pl) \ | |
3882 | (XOPL3 ((op), (xop), (wc)) \ | |
3883 | | ((((uint64_t)(pl)) & 3) << 16)) | |
3884 | ||
5817ffd1 | 3885 | /* An X form instruction with the L bit and RC bit specified. */ |
b80c7270 AM |
3886 | #define XRCL(op, xop, l, rc) \ |
3887 | (XRC ((op), (xop), (rc)) \ | |
0f873fd5 | 3888 | | ((((uint64_t)(l)) & 1) << 21)) |
5817ffd1 | 3889 | |
19a6653c | 3890 | /* An X form instruction with RT fields specified */ |
b80c7270 AM |
3891 | #define XRT(op, xop, rt) \ |
3892 | (X ((op), (xop)) \ | |
0f873fd5 | 3893 | | ((((uint64_t)(rt)) & 0x1f) << 21)) |
19a6653c AM |
3894 | |
3895 | /* An X form instruction with RT and RA fields specified */ | |
b80c7270 AM |
3896 | #define XRTRA(op, xop, rt, ra) \ |
3897 | (X ((op), (xop)) \ | |
0f873fd5 PB |
3898 | | ((((uint64_t)(rt)) & 0x1f) << 21) \ |
3899 | | ((((uint64_t)(ra)) & 0x1f) << 16)) | |
19a6653c | 3900 | |
252b5132 | 3901 | /* The mask for an X form comparison instruction. */ |
0f873fd5 | 3902 | #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22)) |
252b5132 | 3903 | |
520ceea4 BE |
3904 | /* The mask for an X form comparison instruction with the L field |
3905 | fixed. */ | |
0f873fd5 | 3906 | #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21)) |
252b5132 RH |
3907 | |
3908 | /* An X form trap instruction with the TO field specified. */ | |
b80c7270 AM |
3909 | #define XTO(op, xop, to) \ |
3910 | (X ((op), (xop)) \ | |
0f873fd5 | 3911 | | ((((uint64_t)(to)) & 0x1f) << 21)) |
252b5132 RH |
3912 | #define XTO_MASK (X_MASK | TO_MASK) |
3913 | ||
e0c21649 | 3914 | /* An X form tlb instruction with the SH field specified. */ |
b80c7270 AM |
3915 | #define XTLB(op, xop, sh) \ |
3916 | (X ((op), (xop)) \ | |
0f873fd5 | 3917 | | ((((uint64_t)(sh)) & 0x1f) << 11)) |
e0c21649 GK |
3918 | #define XTLB_MASK (X_MASK | SH_MASK) |
3919 | ||
6ba045b1 | 3920 | /* An X form sync instruction. */ |
b80c7270 AM |
3921 | #define XSYNC(op, xop, l) \ |
3922 | (X ((op), (xop)) \ | |
0f873fd5 | 3923 | | ((((uint64_t)(l)) & 3) << 21)) |
6ba045b1 | 3924 | |
b80c7270 AM |
3925 | /* An X form sync instruction with everything filled in except the LS |
3926 | field. */ | |
6ba045b1 AM |
3927 | #define XSYNC_MASK (0xff9fffff) |
3928 | ||
b80c7270 AM |
3929 | /* An X form sync instruction with everything filled in except the L |
3930 | and E fields. */ | |
aea77599 AM |
3931 | #define XSYNCLE_MASK (0xff90ffff) |
3932 | ||
3d205eb4 PB |
3933 | /* An X form sync instruction. */ |
3934 | #define XSYNCLS(op, xop, l, s) \ | |
3935 | (X ((op), (xop)) \ | |
3936 | | ((((uint64_t)(l)) & 7) << 21) \ | |
3937 | | ((((uint64_t)(s)) & 3) << 16)) | |
3938 | ||
3939 | /* An X form sync instruction with everything filled in except the | |
3940 | L and SC fields. */ | |
3941 | #define XSYNCLS_MASK (0xff1cffff) | |
3942 | ||
702f0fb4 | 3943 | /* An X_MASK, but with the EH bit clear. */ |
0f873fd5 | 3944 | #define XEH_MASK (X_MASK & ~((uint64_t )1)) |
702f0fb4 | 3945 | |
f5c120c5 | 3946 | /* An X form AltiVec dss instruction. */ |
0f873fd5 | 3947 | #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25)) |
f5c120c5 MG |
3948 | #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) |
3949 | ||
252b5132 | 3950 | /* An XFL form instruction. */ |
b80c7270 AM |
3951 | #define XFL(op, xop, rc) \ |
3952 | (OP (op) \ | |
0f873fd5 PB |
3953 | | ((((uint64_t)(xop)) & 0x3ff) << 1) \ |
3954 | | (((uint64_t)(rc)) & 1)) | |
ea192fa3 | 3955 | #define XFL_MASK XFL (0x3f, 0x3ff, 1) |
252b5132 | 3956 | |
23976049 | 3957 | /* An X form isel instruction. */ |
0f873fd5 | 3958 | #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
de866fcc | 3959 | #define XISEL_MASK XISEL(0x3f, 0x1f) |
23976049 | 3960 | |
252b5132 | 3961 | /* An XL form instruction with the LK field set to 0. */ |
0f873fd5 | 3962 | #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) |
252b5132 RH |
3963 | |
3964 | /* An XL form instruction which uses the LK field. */ | |
3965 | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) | |
3966 | ||
3967 | /* The mask for an XL form instruction. */ | |
3968 | #define XL_MASK XLLK (0x3f, 0x3ff, 1) | |
3969 | ||
c0637f3a PB |
3970 | /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ |
3971 | #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) | |
3972 | ||
252b5132 RH |
3973 | /* An XL form instruction which explicitly sets the BO field. */ |
3974 | #define XLO(op, bo, xop, lk) \ | |
0f873fd5 | 3975 | (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21)) |
252b5132 RH |
3976 | #define XLO_MASK (XL_MASK | BO_MASK) |
3977 | ||
252b5132 RH |
3978 | /* An XL form instruction which sets the BO field and the condition |
3979 | bits of the BI field. */ | |
3980 | #define XLOCB(op, bo, cb, xop, lk) \ | |
0f873fd5 | 3981 | (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16)) |
252b5132 RH |
3982 | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
3983 | ||
aae9718e | 3984 | /* An XL_MASK or XLOCB_MASK with the BB field fixed. */ |
252b5132 | 3985 | #define XLBB_MASK (XL_MASK | BB_MASK) |
252b5132 RH |
3986 | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) |
3987 | ||
d0618d1c | 3988 | /* A mask for branch instructions using the BH field. */ |
66e85460 | 3989 | #define XLBH_MASK (XL_MASK | (BB_MASK & ~(3 << 11))) |
d0618d1c | 3990 | |
252b5132 RH |
3991 | /* An XL_MASK with the BO and BB fields fixed. */ |
3992 | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) | |
3993 | ||
3994 | /* An XL_MASK with the BO, BI and BB fields fixed. */ | |
3995 | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) | |
3996 | ||
e01d869a | 3997 | /* An X form mbar instruction with MO field. */ |
b80c7270 AM |
3998 | #define XMBAR(op, xop, mo) \ |
3999 | (X ((op), (xop)) \ | |
0f873fd5 | 4000 | | ((((uint64_t)(mo)) & 1) << 21)) |
e01d869a | 4001 | |
252b5132 | 4002 | /* An XO form instruction. */ |
b80c7270 AM |
4003 | #define XO(op, xop, oe, rc) \ |
4004 | (OP (op) \ | |
0f873fd5 PB |
4005 | | ((((uint64_t)(xop)) & 0x1ff) << 1) \ |
4006 | | ((((uint64_t)(oe)) & 1) << 10) \ | |
b80c7270 | 4007 | | (((unsigned long)(rc)) & 1)) |
252b5132 RH |
4008 | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
4009 | ||
4010 | /* An XO_MASK with the RB field fixed. */ | |
4011 | #define XORB_MASK (XO_MASK | RB_MASK) | |
4012 | ||
c3d65c1c | 4013 | /* An XOPS form instruction for paired singles. */ |
b80c7270 AM |
4014 | #define XOPS(op, xop, rc) \ |
4015 | (OP (op) \ | |
0f873fd5 PB |
4016 | | ((((uint64_t)(xop)) & 0x3ff) << 1) \ |
4017 | | (((uint64_t)(rc)) & 1)) | |
c3d65c1c BE |
4018 | #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) |
4019 | ||
4020 | ||
252b5132 | 4021 | /* An XS form instruction. */ |
b80c7270 AM |
4022 | #define XS(op, xop, rc) \ |
4023 | (OP (op) \ | |
0f873fd5 PB |
4024 | | ((((uint64_t)(xop)) & 0x1ff) << 2) \ |
4025 | | (((uint64_t)(rc)) & 1)) | |
252b5132 RH |
4026 | #define XS_MASK XS (0x3f, 0x1ff, 1) |
4027 | ||
4028 | /* A mask for the FXM version of an XFX form instruction. */ | |
98e69875 | 4029 | #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) |
252b5132 RH |
4030 | |
4031 | /* An XFX form instruction with the FXM field filled in. */ | |
b80c7270 AM |
4032 | #define XFXM(op, xop, fxm, p4) \ |
4033 | (X ((op), (xop)) \ | |
0f873fd5 PB |
4034 | | ((((uint64_t)(fxm)) & 0xff) << 12) \ |
4035 | | ((uint64_t)(p4) << 20)) | |
252b5132 RH |
4036 | |
4037 | /* An XFX form instruction with the SPR field filled in. */ | |
b80c7270 AM |
4038 | #define XSPR(op, xop, spr) \ |
4039 | (X ((op), (xop)) \ | |
0f873fd5 PB |
4040 | | ((((uint64_t)(spr)) & 0x1f) << 16) \ |
4041 | | ((((uint64_t)(spr)) & 0x3e0) << 6)) | |
252b5132 RH |
4042 | #define XSPR_MASK (X_MASK | SPR_MASK) |
4043 | ||
4044 | /* An XFX form instruction with the SPR field filled in except for the | |
4045 | SPRBAT field. */ | |
4046 | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) | |
4047 | ||
fa758a70 AC |
4048 | /* An XFX form instruction with the SPR field filled in except for the |
4049 | SPRGQR field. */ | |
4050 | #define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK) | |
4051 | ||
252b5132 RH |
4052 | /* An XFX form instruction with the SPR field filled in except for the |
4053 | SPRG field. */ | |
b84bf58a | 4054 | #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) |
252b5132 RH |
4055 | |
4056 | /* An X form instruction with everything filled in except the E field. */ | |
4057 | #define XE_MASK (0xffff7fff) | |
4058 | ||
23976049 | 4059 | /* An X form user context instruction. */ |
0f873fd5 | 4060 | #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) |
23976049 EZ |
4061 | #define XUC_MASK XUC(0x3f, 0x1f) |
4062 | ||
c3d65c1c | 4063 | /* An XW form instruction. */ |
b80c7270 AM |
4064 | #define XW(op, xop, rc) \ |
4065 | (OP (op) \ | |
0f873fd5 | 4066 | | ((((uint64_t)(xop)) & 0x3f) << 1) \ |
b80c7270 | 4067 | | ((rc) & 1)) |
c3d65c1c BE |
4068 | /* The mask for a G form instruction. rc not supported at present. */ |
4069 | #define XW_MASK XW (0x3f, 0x3f, 0) | |
4070 | ||
081ba1b3 | 4071 | /* An APU form instruction. */ |
b80c7270 AM |
4072 | #define APU(op, xop, rc) \ |
4073 | (OP (op) \ | |
0f873fd5 | 4074 | | (((uint64_t)(xop)) & 0x3ff) << 1 \ |
b80c7270 | 4075 | | ((rc) & 1)) |
081ba1b3 AM |
4076 | |
4077 | /* The mask for an APU form instruction. */ | |
4078 | #define APU_MASK APU (0x3f, 0x3ff, 1) | |
4079 | #define APU_RT_MASK (APU_MASK | RT_MASK) | |
4080 | #define APU_RA_MASK (APU_MASK | RA_MASK) | |
4081 | ||
252b5132 RH |
4082 | /* The BO encodings used in extended conditional branch mnemonics. */ |
4083 | #define BODNZF (0x0) | |
4084 | #define BODNZFP (0x1) | |
4085 | #define BODZF (0x2) | |
4086 | #define BODZFP (0x3) | |
252b5132 RH |
4087 | #define BODNZT (0x8) |
4088 | #define BODNZTP (0x9) | |
4089 | #define BODZT (0xa) | |
4090 | #define BODZTP (0xb) | |
802a735e AM |
4091 | |
4092 | #define BOF (0x4) | |
4093 | #define BOFP (0x5) | |
94efba12 AM |
4094 | #define BOFM4 (0x6) |
4095 | #define BOFP4 (0x7) | |
252b5132 RH |
4096 | #define BOT (0xc) |
4097 | #define BOTP (0xd) | |
94efba12 AM |
4098 | #define BOTM4 (0xe) |
4099 | #define BOTP4 (0xf) | |
802a735e | 4100 | |
252b5132 RH |
4101 | #define BODNZ (0x10) |
4102 | #define BODNZP (0x11) | |
4103 | #define BODZ (0x12) | |
4104 | #define BODZP (0x13) | |
94efba12 AM |
4105 | #define BODNZM4 (0x18) |
4106 | #define BODNZP4 (0x19) | |
4107 | #define BODZM4 (0x1a) | |
4108 | #define BODZP4 (0x1b) | |
802a735e | 4109 | |
252b5132 RH |
4110 | #define BOU (0x14) |
4111 | ||
b9c361e0 JL |
4112 | /* The BO16 encodings used in extended VLE conditional branch mnemonics. */ |
4113 | #define BO16F (0x0) | |
4114 | #define BO16T (0x1) | |
4115 | ||
4116 | /* The BO32 encodings used in extended VLE conditional branch mnemonics. */ | |
4117 | #define BO32F (0x0) | |
4118 | #define BO32T (0x1) | |
4119 | #define BO32DNZ (0x2) | |
4120 | #define BO32DZ (0x3) | |
4121 | ||
252b5132 RH |
4122 | /* The BI condition bit encodings used in extended conditional branch |
4123 | mnemonics. */ | |
4124 | #define CBLT (0) | |
4125 | #define CBGT (1) | |
4126 | #define CBEQ (2) | |
4127 | #define CBSO (3) | |
4128 | ||
4129 | /* The TO encodings used in extended trap mnemonics. */ | |
4130 | #define TOLGT (0x1) | |
4131 | #define TOLLT (0x2) | |
4132 | #define TOEQ (0x4) | |
4133 | #define TOLGE (0x5) | |
4134 | #define TOLNL (0x5) | |
4135 | #define TOLLE (0x6) | |
4136 | #define TOLNG (0x6) | |
4137 | #define TOGT (0x8) | |
4138 | #define TOGE (0xc) | |
4139 | #define TONL (0xc) | |
4140 | #define TOLT (0x10) | |
4141 | #define TOLE (0x14) | |
4142 | #define TONG (0x14) | |
4143 | #define TONE (0x18) | |
4144 | #define TOU (0x1f) | |
4145 | \f | |
4146 | /* Smaller names for the flags so each entry in the opcodes table will | |
4147 | fit on a single line. */ | |
4148 | #undef PPC | |
de866fcc | 4149 | #define PPC PPC_OPCODE_PPC |
661bd698 | 4150 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
661bd698 | 4151 | #define POWER4 PPC_OPCODE_POWER4 |
1ed8e1e4 | 4152 | #define POWER5 PPC_OPCODE_POWER5 |
702f0fb4 | 4153 | #define POWER6 PPC_OPCODE_POWER6 |
066be9f7 | 4154 | #define POWER7 PPC_OPCODE_POWER7 |
5817ffd1 | 4155 | #define POWER8 PPC_OPCODE_POWER8 |
a680de9a | 4156 | #define POWER9 PPC_OPCODE_POWER9 |
7c1f4227 | 4157 | #define POWER10 PPC_OPCODE_POWER10 |
ede602d7 | 4158 | #define CELL PPC_OPCODE_CELL |
bdc70b4a | 4159 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE |
6b069ee7 | 4160 | #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ |
bdc70b4a | 4161 | | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
418c1742 | 4162 | #define PPC403 PPC_OPCODE_403 |
081ba1b3 | 4163 | #define PPC405 PPC_OPCODE_405 |
7d5b217e | 4164 | #define PPC440 PPC_OPCODE_440 |
c8187e15 | 4165 | #define PPC464 PPC440 |
9fe54b1c | 4166 | #define PPC476 PPC_OPCODE_476 |
ef5a96d5 | 4167 | #define PPC750 PPC_OPCODE_750 |
fa758a70 AC |
4168 | #define GEKKO PPC_OPCODE_750 |
4169 | #define BROADWAY PPC_OPCODE_750 | |
ef5a96d5 AM |
4170 | #define PPC7450 PPC_OPCODE_7450 |
4171 | #define PPC860 PPC_OPCODE_860 | |
c3d65c1c | 4172 | #define PPCPS PPC_OPCODE_PPCPS |
a404d431 | 4173 | #define PPCVEC PPC_OPCODE_ALTIVEC |
9a85b496 AM |
4174 | #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500) |
4175 | #define PPCVEC3 PPC_OPCODE_POWER9 | |
9b4e5766 | 4176 | #define PPCVSX PPC_OPCODE_VSX |
9570835e AM |
4177 | #define PPCVSX2 PPC_OPCODE_POWER8 |
4178 | #define PPCVSX3 PPC_OPCODE_POWER9 | |
aa3c112f | 4179 | #define PPCVSX4 PPC_OPCODE_POWER10 |
de866fcc AM |
4180 | #define POWER PPC_OPCODE_POWER |
4181 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | |
81a0b7e2 | 4182 | #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON |
b80c7270 AM |
4183 | #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \ |
4184 | | PPC_OPCODE_COMMON) | |
de866fcc | 4185 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
de866fcc | 4186 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 |
661bd698 | 4187 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON |
de866fcc | 4188 | #define MFDEC1 PPC_OPCODE_POWER |
b80c7270 AM |
4189 | #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \ |
4190 | | PPC_OPCODE_TITAN) | |
418c1742 | 4191 | #define BOOKE PPC_OPCODE_BOOKE |
14b57c7c | 4192 | #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS |
36ae0db3 | 4193 | #define PPCE300 PPC_OPCODE_E300 |
14b57c7c | 4194 | #define PPCSPE PPC_OPCODE_SPE |
74081948 | 4195 | #define PPCSPE2 PPC_OPCODE_SPE2 |
14b57c7c AM |
4196 | #define PPCISEL PPC_OPCODE_ISEL |
4197 | #define PPCEFS PPC_OPCODE_EFS | |
74081948 | 4198 | #define PPCEFS2 PPC_OPCODE_EFS2 |
de866fcc | 4199 | #define PPCBRLK PPC_OPCODE_BRLOCK |
23976049 | 4200 | #define PPCPMR PPC_OPCODE_PMR |
aea77599 | 4201 | #define PPCTMR PPC_OPCODE_TMR |
de866fcc | 4202 | #define PPCCHLK PPC_OPCODE_CACHELCK |
fa758a70 | 4203 | #define PPCRFMCI PPC_OPCODE_RFMCI |
19a6653c | 4204 | #define E500MC PPC_OPCODE_E500MC |
634b50f2 | 4205 | #define PPCA2 PPC_OPCODE_A2 |
43e65147 | 4206 | #define TITAN PPC_OPCODE_TITAN |
62adc510 | 4207 | #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN |
e01d869a | 4208 | #define E500 PPC_OPCODE_E500 |
aea77599 | 4209 | #define E6500 PPC_OPCODE_E6500 |
b9c361e0 | 4210 | #define PPCVLE PPC_OPCODE_VLE |
ef85eab0 | 4211 | #define PPCHTM PPC_OPCODE_POWER8 |
dfdaec14 | 4212 | #define E200Z4 PPC_OPCODE_E200Z4 |
e3c2f928 | 4213 | #define PPCLSP PPC_OPCODE_LSP |
4fff86c5 PB |
4214 | /* The list of embedded processors that use the embedded operand ordering |
4215 | for the 3 operand dcbt and dcbtst instructions. */ | |
4216 | #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ | |
14b57c7c | 4217 | | PPC_OPCODE_A2) |
4fff86c5 PB |
4218 | |
4219 | ||
252b5132 RH |
4220 | \f |
4221 | /* The opcode table. | |
4222 | ||
4223 | The format of the opcode table is: | |
4224 | ||
8ebac3aa | 4225 | NAME OPCODE MASK FLAGS ANTI {OPERANDS} |
252b5132 RH |
4226 | |
4227 | NAME is the name of the instruction. | |
4228 | OPCODE is the instruction opcode. | |
4229 | MASK is the opcode mask; this is used to tell the disassembler | |
4230 | which bits in the actual opcode must match OPCODE. | |
8ebac3aa AM |
4231 | FLAGS are flags indicating which processors support the instruction. |
4232 | ANTI indicates which processors don't support the instruction. | |
252b5132 RH |
4233 | OPERANDS is the list of operands. |
4234 | ||
4235 | The disassembler reads the table in order and prints the first | |
4236 | instruction which matches, so this table is sorted to put more | |
de866fcc AM |
4237 | specific instructions before more general instructions. |
4238 | ||
4239 | This table must be sorted by major opcode. Please try to keep it | |
4240 | vaguely sorted within major opcode too, except of course where | |
4241 | constrained otherwise by disassembler operation. */ | |
252b5132 RH |
4242 | |
4243 | const struct powerpc_opcode powerpc_opcodes[] = { | |
14b57c7c AM |
4244 | {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, |
4245 | {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4246 | {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4247 | {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4248 | {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4249 | {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4250 | {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4251 | {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4252 | {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4253 | {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4254 | {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4255 | {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4256 | {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4257 | {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4258 | {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4259 | {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4260 | {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, | |
4261 | ||
4262 | {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4263 | {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4264 | {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4265 | {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4266 | {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4267 | {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4268 | {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4269 | {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4270 | {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4271 | {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4272 | {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4273 | {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4274 | {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4275 | {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4276 | {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4277 | {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4278 | {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4279 | {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4280 | {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4281 | {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4282 | {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4283 | {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4284 | {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4285 | {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4286 | {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4287 | {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4288 | {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4289 | {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4290 | {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4291 | {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4292 | {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, | |
4293 | {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, | |
4294 | ||
4295 | {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4296 | {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4297 | {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, | |
4298 | {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4299 | {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4300 | {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4301 | {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4302 | {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4303 | {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4304 | {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4305 | {"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4306 | {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, |
4307 | {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
66ef5847 AM |
4308 | {"vstribl", VXVA(4,13,0), VXVA_MASK, POWER10, 0, {VD, VB}}, |
4309 | {"vstribr", VXVA(4,13,1), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4310 | {"vstrihl", VXVA(4,13,2), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4311 | {"vstrihr", VXVA(4,13,3), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
14b57c7c AM |
4312 | {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, |
4313 | {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4314 | {"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4315 | {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
4316 | {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
fdefed7c | 4317 | {"mtvsrbmi", DX (4,10), DX_MASK, POWER10, 0, {VD, DXD}}, |
14b57c7c AM |
4318 | {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
4319 | {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
6edbfd3b | 4320 | {"vsldbi", VX (4, 22), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}}, |
14b57c7c AM |
4321 | {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
4322 | {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
6edbfd3b | 4323 | {"vextdubvlx", VX (4, 24), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c AM |
4324 | {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
4325 | {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
6edbfd3b | 4326 | {"vextdubvrx", VX (4, 25), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c AM |
4327 | {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
4328 | {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
6edbfd3b | 4329 | {"vextduhvlx", VX (4, 26), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4330 | {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
6edbfd3b | 4331 | {"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4332 | {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
6edbfd3b | 4333 | {"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4334 | {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
6edbfd3b | 4335 | {"vextduwvrx", VX (4, 29), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4336 | {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
6edbfd3b | 4337 | {"vextddvlx", VX (4, 30), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4338 | {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
6edbfd3b | 4339 | {"vextddvrx", VX (4, 31), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c AM |
4340 | {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
4341 | {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4342 | {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4343 | {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4344 | {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, | |
4345 | {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
c7d7aea2 | 4346 | {"vmsumcud", VXA(4, 23), VXA_MASK, POWER10, 0, {VD, VA, VB, VC}}, |
14b57c7c AM |
4347 | {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
4348 | {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4349 | {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4350 | {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4351 | {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4352 | {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4353 | {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4354 | {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4355 | {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4356 | {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4357 | {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4358 | {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4359 | {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4360 | {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, | |
4361 | {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4362 | {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4363 | {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, | |
4364 | {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4365 | {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, | |
4366 | {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4367 | {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
4368 | {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4369 | {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
4370 | {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
4371 | {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
4372 | {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
4373 | {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4374 | {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4375 | {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4376 | {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4377 | {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4378 | {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4379 | {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, | |
4380 | {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4381 | {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4382 | {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4383 | {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4384 | {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4385 | {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4386 | {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4387 | {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4388 | {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4389 | {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4390 | {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4391 | {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4392 | {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4393 | {"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4394 | {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4395 | {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4396 | {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4397 | {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4398 | {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, | |
4399 | {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4400 | {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, | |
4401 | {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4402 | {"vinshvlx", VX (4, 79), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4403 | {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
4404 | {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4405 | {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4406 | {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4407 | {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4408 | {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4409 | {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4410 | {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4411 | {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4412 | {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4413 | {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4414 | {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4415 | {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4416 | {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4417 | {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4418 | {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4419 | {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
f4791f1a | 4420 | {"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4421 | {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4422 | {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4423 | {"vinswvlx", VX (4, 143), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4424 | {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
4425 | {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4426 | {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4427 | {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4428 | {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4429 | {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4430 | {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4431 | {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4432 | {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4433 | {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4434 | {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4435 | {"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
f4791f1a | 4436 | {"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4437 | {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
6edbfd3b | 4438 | {"vinsw", VX (4, 207), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}}, |
14b57c7c AM |
4439 | {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4440 | {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4441 | {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4442 | {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4443 | {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4444 | {"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, |
14b57c7c AM |
4445 | {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4446 | {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4447 | {"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4448 | {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4449 | {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4450 | {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
c7d7aea2 | 4451 | {"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4452 | {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4453 | {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4454 | {"vinsbvrx", VX (4, 271), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4455 | {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
4456 | {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4457 | {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4458 | {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4459 | {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4460 | {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4461 | {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4462 | {"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, |
14b57c7c AM |
4463 | {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4464 | {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4465 | {"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4466 | {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4467 | {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4468 | {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
4469 | {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4470 | {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4471 | {"vinshvrx", VX (4, 335), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4472 | {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
4473 | {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4474 | {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4475 | {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4476 | {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4477 | {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4478 | {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4479 | {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4480 | {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4481 | {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4482 | {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4483 | {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4484 | {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
f4791f1a | 4485 | {"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4486 | {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
66ef5847 | 4487 | {"vclrlb", VX (4, 397), VX_MASK, POWER10, 0, {VD, VA, RB}}, |
14b57c7c | 4488 | {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
6edbfd3b | 4489 | {"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4490 | {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4491 | {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4492 | {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4493 | {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4494 | {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4495 | {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 AM |
4496 | {"vcmpequq", VXR(4, 455,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
4497 | {"vmulosd", VX (4, 456), VX_MASK, POWER10, 0, {VD, VA, VB}}, | |
f4791f1a | 4498 | {"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4499 | {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
f4791f1a | 4500 | {"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
66ef5847 | 4501 | {"vclrrb", VX (4, 461), VX_MASK, POWER10, 0, {VD, VA, RB}}, |
14b57c7c | 4502 | {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
6edbfd3b | 4503 | {"vinsd", VX (4, 463), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}}, |
14b57c7c AM |
4504 | {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4505 | {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4506 | {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4507 | {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4508 | {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4509 | {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4510 | {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, | |
4511 | {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, | |
4512 | {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4513 | {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4514 | {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, | |
4515 | {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4516 | {"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4517 | {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, |
4518 | {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, | |
4519 | {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4520 | {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4521 | {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4522 | {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4523 | {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4524 | {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
c7d7aea2 | 4525 | {"vdiveuq", VX (4, 523), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4526 | {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, |
4527 | {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4528 | {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, | |
4529 | {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4530 | {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4531 | {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4532 | {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4533 | {"vinsblx", VX (4, 527), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4534 | {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4535 | {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4536 | {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4537 | {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4538 | {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
6edbfd3b | 4539 | {"vsrdbi", VX (4, 534), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}}, |
14b57c7c | 4540 | {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
98553ad3 | 4541 | {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RAB}}, |
14b57c7c | 4542 | {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
98553ad3 | 4543 | {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RAB}}, |
14b57c7c | 4544 | {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
4545 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
4546 | {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4547 | {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4548 | {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4549 | {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4550 | {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4551 | {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4552 | {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4553 | {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4554 | {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4555 | {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4556 | {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, | |
4557 | {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4558 | {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, | |
4559 | {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4560 | {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4561 | {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4562 | {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4563 | {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4564 | {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4565 | {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4566 | {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4567 | {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4568 | {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, | |
4569 | {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4570 | {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4571 | {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4572 | {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4573 | {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4574 | {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4575 | {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
4576 | {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, | |
4577 | {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4578 | {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4579 | {"vinshlx", VX (4, 591), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4580 | {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
4581 | {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, | |
4582 | {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, | |
4583 | {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4584 | {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4585 | {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 | 4586 | {"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c | 4587 | {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
74081948 | 4588 | {"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
4589 | {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, |
4590 | {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4591 | {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4592 | {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4593 | {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4594 | {"vcmpgtuq", VXR(4, 647,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4595 | {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, |
14b57c7c AM |
4596 | {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4597 | {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
f4791f1a | 4598 | {"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4599 | {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
74081948 | 4600 | {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c | 4601 | {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
f4791f1a | 4602 | {"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4603 | {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
4604 | {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
4605 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, | |
4606 | {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4607 | {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4608 | {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4609 | {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4610 | {"vinswlx", VX (4, 655), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c | 4611 | {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, |
74081948 | 4612 | {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4613 | {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, |
4614 | {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4615 | {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4616 | {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
74081948 | 4617 | {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4618 | {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, |
4619 | {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4620 | {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4621 | {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4622 | {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, | |
4623 | {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4624 | {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4625 | {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4626 | {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
74081948 AF |
4627 | {"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, |
4628 | {"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4629 | {"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4630 | {"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4631 | {"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4632 | {"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4633 | {"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4634 | {"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4635 | {"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4636 | {"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4637 | {"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4638 | {"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4639 | {"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4640 | {"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4641 | {"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4642 | {"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4643 | {"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4644 | {"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
14b57c7c | 4645 | {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
74081948 | 4646 | {"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, |
14b57c7c AM |
4647 | {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
4648 | {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 | 4649 | {"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c | 4650 | {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4651 | {"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c AM |
4652 | {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, |
4653 | {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4654 | {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
4655 | {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
4656 | {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4657 | {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, |
14b57c7c | 4658 | {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
c7d7aea2 | 4659 | {"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4660 | {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
f4791f1a | 4661 | {"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4662 | {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
74081948 | 4663 | {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c | 4664 | {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
f4791f1a | 4665 | {"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4666 | {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c AM |
4667 | {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4668 | {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4669 | {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4670 | {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4671 | {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4672 | {"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4673 | {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4674 | {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 4675 | {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4676 | {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4677 | {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4678 | {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4679 | {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 4680 | {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4681 | {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4682 | {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4683 | {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4684 | {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4685 | {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, | |
4686 | {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4687 | {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4688 | {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4689 | {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4690 | {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
4691 | {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 AF |
4692 | {"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, |
4693 | {"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
4694 | {"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, | |
4695 | {"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
14b57c7c AM |
4696 | {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, |
4697 | {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
4698 | {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
74081948 | 4699 | {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, |
14b57c7c AM |
4700 | {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
4701 | {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 AF |
4702 | {"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, |
4703 | {"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
4704 | {"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, | |
4705 | {"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
14b57c7c AM |
4706 | {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4707 | {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4708 | {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4709 | {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 AF |
4710 | {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4711 | {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
4712 | {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, | |
4713 | {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
4714 | {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, | |
14b57c7c AM |
4715 | {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4716 | {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4717 | {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 4718 | {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4719 | {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4720 | {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4721 | {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 AF |
4722 | {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4723 | {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
14b57c7c | 4724 | {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
74081948 AF |
4725 | {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4726 | {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
14b57c7c AM |
4727 | {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4728 | {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4729 | {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4730 | {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4731 | {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4732 | {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4733 | {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4734 | {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4735 | {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4736 | {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4737 | {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4738 | {"vsraq", VX (4, 773), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4739 | {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
4740 | {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4741 | {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4742 | {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4743 | {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, | |
4744 | {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4745 | {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
c7d7aea2 | 4746 | {"vdivesq", VX (4, 779), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4747 | {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4748 | {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, | |
4749 | {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4750 | {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, | |
4751 | {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4752 | {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4753 | {"vinsbrx", VX (4, 783), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4754 | {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, |
4755 | {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4756 | {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4757 | {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4758 | {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4759 | {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4760 | {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4761 | {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4762 | {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4763 | {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4764 | {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4765 | {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4766 | {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4767 | {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4768 | {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4769 | {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4770 | {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4771 | {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4772 | {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4773 | {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4774 | {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4775 | {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4776 | {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4777 | {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4778 | {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4779 | {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4780 | {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4781 | {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4782 | {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4783 | {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4784 | {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4785 | {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4786 | {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4787 | {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4788 | {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4789 | {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4790 | {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4791 | {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, | |
4792 | {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4793 | {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4794 | {"vinshrx", VX (4, 847), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4795 | {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
4796 | {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4797 | {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4798 | {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4799 | {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4800 | {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4801 | {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4802 | {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4803 | {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4804 | {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4805 | {"vcmpgtsq", VXR(4, 903,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4806 | {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
f4791f1a | 4807 | {"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4808 | {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
4809 | {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
f4791f1a | 4810 | {"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4811 | {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, |
4812 | {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
6edbfd3b | 4813 | {"vinswrx", VX (4, 911), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4814 | {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4815 | {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4816 | {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4817 | {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4818 | {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4819 | {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4820 | {"vmulesd", VX (4, 968), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
f4791f1a | 4821 | {"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4822 | {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
4823 | {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
f4791f1a | 4824 | {"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4825 | {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
4826 | {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4827 | {"vinsdrx", VX (4, 975), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4828 | {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4829 | {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4830 | {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4831 | {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4832 | {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4833 | {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, | |
4834 | {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4835 | {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4836 | {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4837 | {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4838 | {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4839 | {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
62adc510 AM |
4840 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4841 | {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4842 | {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4843 | {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4844 | {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4845 | {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4846 | {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4847 | {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4848 | {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4849 | {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
66ef5847 AM |
4850 | {"vstribl.", VXVA(4,1037,0), VXVA_MASK, POWER10, 0, {VD, VB}}, |
4851 | {"vstribr.", VXVA(4,1037,1), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4852 | {"vstrihl.", VXVA(4,1037,2), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4853 | {"vstrihr.", VXVA(4,1037,3), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
14b57c7c AM |
4854 | {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4855 | {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4856 | {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4857 | {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4858 | {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4859 | {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4860 | {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4861 | {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4862 | {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4863 | {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4864 | {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4865 | {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4866 | {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4867 | {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4868 | {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4869 | {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, | |
4870 | {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4871 | {"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4872 | {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4873 | {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4874 | {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4875 | {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4876 | {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4877 | {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4878 | {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4879 | {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4880 | {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4881 | {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4882 | {"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4883 | {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4884 | {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4885 | {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4886 | {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4887 | {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4888 | {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4889 | {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4890 | {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4891 | {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4892 | {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4893 | {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4894 | {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4895 | {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4896 | {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4897 | {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
74081948 | 4898 | {"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4899 | {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4900 | {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 | 4901 | {"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4902 | {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4903 | {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4904 | {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4905 | {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4906 | {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4907 | {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4908 | {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4909 | {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4910 | {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4911 | {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4912 | {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
98553ad3 | 4913 | {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VAB}}, |
14b57c7c AM |
4914 | {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4915 | {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4916 | {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4917 | {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4918 | {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4919 | {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4920 | {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4921 | {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4922 | {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4923 | {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4924 | {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4925 | {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4926 | {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4927 | {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4928 | {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4929 | {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4930 | {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4931 | {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4932 | {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4933 | {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 4934 | {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 4935 | {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 4936 | {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
14b57c7c AM |
4937 | {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4938 | {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4939 | {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4940 | {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4941 | {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4942 | {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
ec40e91c | 4943 | {"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}}, |
14b57c7c AM |
4944 | {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4945 | {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4946 | {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4947 | {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4948 | {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4949 | {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4950 | {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4951 | {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4952 | {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4953 | {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4954 | {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4955 | {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4956 | {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4957 | {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
98553ad3 | 4958 | {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VAB}}, |
14b57c7c AM |
4959 | {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4960 | {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
62adc510 AM |
4961 | {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4962 | {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4963 | {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4964 | {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4965 | {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4966 | {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4967 | {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4968 | {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4969 | {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4970 | {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4971 | {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4972 | {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4973 | {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4974 | {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4975 | {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4976 | {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4977 | {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4978 | {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4979 | {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4980 | {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4981 | {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4982 | {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4983 | {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4984 | {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4985 | {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4986 | {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 AF |
4987 | {"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4988 | {"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4989 | {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4990 | {"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
62adc510 AM |
4991 | {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4992 | {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c | 4993 | {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
74081948 | 4994 | {"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4995 | {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4996 | {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4997 | {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4998 | {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4999 | {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
5000 | {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 5001 | {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
ec40e91c | 5002 | {"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 5003 | {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 5004 | {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 5005 | {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
5006 | {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
5007 | {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5008 | {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5009 | {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5010 | {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5011 | {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5012 | {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5013 | {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
74081948 AF |
5014 | {"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
5015 | {"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
5016 | {"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
5017 | {"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c AM |
5018 | {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
5019 | {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5020 | {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5021 | {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5022 | {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
5023 | {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
5024 | {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5025 | {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
5026 | {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
5027 | {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
5028 | {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5029 | {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5030 | {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
5031 | {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5032 | {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
62adc510 AM |
5033 | {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
5034 | {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
5035 | {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
5036 | {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5037 | {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5038 | {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5039 | {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5040 | {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
ec40e91c | 5041 | {"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5042 | {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
5043 | {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5044 | {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5045 | {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5046 | {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5047 | {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5048 | {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5049 | {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5050 | {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5051 | {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5052 | {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5053 | {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
5054 | {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
5055 | {"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
5056 | {"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 5057 | {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 5058 | {"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 5059 | {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
62adc510 AM |
5060 | {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
5061 | {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
c7d7aea2 | 5062 | {"vcmpequq.", VXR(4, 455,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 5063 | {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
5064 | {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, |
5065 | {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5066 | {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
5067 | {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
5068 | {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 5069 | {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
ec40e91c | 5070 | {"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 5071 | {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 5072 | {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 5073 | {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
5074 | {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
5075 | {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5076 | {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5077 | {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5078 | {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
5079 | {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
5080 | {"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
5081 | {"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
5082 | {"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
5083 | {"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c AM |
5084 | {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
5085 | {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5086 | {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5087 | {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, | |
5088 | {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, | |
5089 | {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5090 | {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5091 | {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5092 | {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5093 | {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5094 | {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5095 | {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5096 | {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5097 | {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5098 | {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
c7d7aea2 | 5099 | {"vextsd2q", VXVA(4,1538,27), VXVA_MASK, POWER10, 0, {VD, VB}}, |
14b57c7c AM |
5100 | {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
5101 | {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5102 | {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5103 | {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
5104 | {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, | |
5105 | {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
5106 | {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
5107 | {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c | 5108 | {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
c7d7aea2 | 5109 | {"vmoduq", VX (4,1547), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5110 | {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
5111 | {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
fdefed7c AM |
5112 | |
5113 | {"vexpandbm", VXVA(4,1602,0), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
5114 | {"vexpandhm", VXVA(4,1602,1), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
5115 | {"vexpandwm", VXVA(4,1602,2), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
5116 | {"vexpanddm", VXVA(4,1602,3), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
5117 | {"vexpandqm", VXVA(4,1602,4), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
5118 | {"vextractbm", VXVA(4,1602,8), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
5119 | {"vextracthm", VXVA(4,1602,9), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
5120 | {"vextractwm", VXVA(4,1602,10), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
5121 | {"vextractdm", VXVA(4,1602,11), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
5122 | {"vextractqm", VXVA(4,1602,12), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
5123 | {"mtvsrbm", VXVA(4,1602,16), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
5124 | {"mtvsrhm", VXVA(4,1602,17), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
5125 | {"mtvsrwm", VXVA(4,1602,18), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
5126 | {"mtvsrdm", VXVA(4,1602,19), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
5127 | {"mtvsrqm", VXVA(4,1602,20), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
5128 | {"vcntmbb", VXVA(4,1602,24), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
5129 | {"vcntmbh", VXVA(4,1602,26), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
5130 | {"vcntmbw", VXVA(4,1602,28), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
5131 | {"vcntmbd", VXVA(4,1602,30), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
5132 | ||
14b57c7c AM |
5133 | {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, |
5134 | {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5135 | {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
5136 | {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
5137 | {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
5138 | {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
5139 | {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5140 | {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5141 | {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, | |
5142 | {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
5143 | {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 5144 | {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
c7d7aea2 | 5145 | {"vcmpgtuq.", VXR(4, 647,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
62adc510 | 5146 | {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 5147 | {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
f4791f1a | 5148 | {"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5149 | {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
5150 | {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
5151 | {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, | |
5152 | {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
5153 | {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 5154 | {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 5155 | {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 5156 | {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
f4791f1a | 5157 | {"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5158 | {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
5159 | {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5160 | {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5161 | {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5162 | {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
5163 | {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
5164 | {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
5165 | {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c | 5166 | {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
c7d7aea2 | 5167 | {"vmodsq", VX (4,1803), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5168 | {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
5169 | {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5170 | {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5171 | {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5172 | {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5173 | {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5174 | {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
5175 | {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5176 | {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
62adc510 AM |
5177 | {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
5178 | {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
5179 | {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
5180 | {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5181 | {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5182 | {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5183 | {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
5184 | {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5185 | {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
ec40e91c | 5186 | {"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 5187 | {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
62adc510 | 5188 | {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
c7d7aea2 | 5189 | {"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
62adc510 | 5190 | {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 5191 | {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
f4791f1a | 5192 | {"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5193 | {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
5194 | {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
5195 | {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5196 | {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5197 | {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5198 | {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
ec40e91c | 5199 | {"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 5200 | {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
62adc510 | 5201 | {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 5202 | {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 5203 | {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
f4791f1a | 5204 | {"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5205 | {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
5206 | {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5207 | {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5208 | {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5209 | {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, | |
5210 | ||
94ba9882 AM |
5211 | {"lxvp", DQXP(6,0), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, |
5212 | {"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, | |
5213 | ||
14b57c7c AM |
5214 | {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, |
5215 | {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5216 | ||
5217 | {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
5218 | {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5219 | ||
5220 | {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, | |
5221 | ||
5222 | {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, | |
5223 | {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, | |
a5721ba2 | 5224 | {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, |
14b57c7c AM |
5225 | {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, |
5226 | ||
5227 | {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, | |
5228 | {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, | |
a5721ba2 | 5229 | {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, |
14b57c7c AM |
5230 | {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, |
5231 | ||
5232 | {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
5233 | {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5234 | {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, | |
5235 | ||
5236 | {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
5237 | {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5238 | {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, | |
5239 | ||
5240 | {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, | |
5241 | {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, | |
5242 | {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, | |
5243 | {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
5244 | {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, | |
5245 | {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, | |
5246 | ||
5247 | {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, | |
5248 | {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, | |
5249 | {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, | |
5250 | {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, | |
5251 | {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, | |
5252 | ||
5253 | {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5254 | {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5255 | {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, | |
5256 | {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, | |
5257 | {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5258 | {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5259 | {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, | |
5260 | {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, | |
5261 | {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5262 | {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5263 | {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, | |
5264 | {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, | |
5265 | {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5266 | {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5267 | {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, | |
5268 | {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, | |
5269 | {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5270 | {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5271 | {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}}, | |
5272 | {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5273 | {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5274 | {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}}, | |
5275 | {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5276 | {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5277 | {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}}, | |
5278 | {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5279 | {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5280 | {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}}, | |
5281 | ||
5282 | {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5283 | {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5284 | {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5285 | {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5286 | {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5287 | {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5288 | {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5289 | {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5290 | {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5291 | {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5292 | {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5293 | {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5294 | {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5295 | {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5296 | {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5297 | {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5298 | {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5299 | {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5300 | {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5301 | {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5302 | {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5303 | {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5304 | {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5305 | {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5306 | {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5307 | {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5308 | {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5309 | {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5310 | {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5311 | {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5312 | {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5313 | {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5314 | {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5315 | {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5316 | {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5317 | {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5318 | {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5319 | {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5320 | {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5321 | {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5322 | {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5323 | {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5324 | {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5325 | {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5326 | {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5327 | {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5328 | {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5329 | {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5330 | {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5331 | {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5332 | {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5333 | {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5334 | {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5335 | {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5336 | {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5337 | {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5338 | {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5339 | {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5340 | {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5341 | {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5342 | {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5343 | {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5344 | {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5345 | {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5346 | {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5347 | {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5348 | {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5349 | {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5350 | {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5351 | {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5352 | {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5353 | {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5354 | {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5355 | {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5356 | {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5357 | {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5358 | {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5359 | {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5360 | {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5361 | {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5362 | {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5363 | {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5364 | {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5365 | {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5366 | ||
5367 | {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5368 | {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5369 | {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5370 | {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5371 | {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5372 | {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5373 | {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5374 | {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5375 | {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5376 | {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5377 | {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5378 | {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5379 | {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5380 | {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5381 | {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5382 | {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5383 | {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5384 | {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5385 | {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5386 | {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5387 | {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5388 | {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5389 | {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5390 | {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5391 | {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5392 | {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5393 | {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5394 | {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5395 | {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5396 | {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5397 | {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5398 | {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5399 | {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5400 | {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5401 | {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5402 | {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5403 | {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5404 | {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5405 | {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5406 | {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5407 | {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5408 | {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5409 | {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5410 | {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5411 | {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5412 | {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5413 | {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5414 | {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5415 | {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5416 | {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5417 | {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5418 | {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5419 | {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5420 | {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5421 | {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5422 | {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5423 | {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5424 | {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5425 | {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5426 | {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5427 | ||
5428 | {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5429 | {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5430 | {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5431 | {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5432 | {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5433 | {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5434 | {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5435 | {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5436 | {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5437 | {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5438 | {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5439 | {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5440 | {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5441 | {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5442 | {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5443 | {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5444 | {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5445 | {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5446 | {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5447 | {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5448 | {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5449 | {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5450 | {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5451 | {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5452 | ||
5453 | {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5454 | {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5455 | {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5456 | {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5457 | {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5458 | {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5459 | {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5460 | {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5461 | {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5462 | {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5463 | {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5464 | {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5465 | {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5466 | {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5467 | {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5468 | {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5469 | ||
5470 | {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5471 | {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5472 | {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5473 | {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5474 | {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5475 | {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5476 | {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5477 | {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5478 | {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5479 | {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5480 | {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5481 | {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5482 | {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5483 | {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5484 | {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5485 | {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5486 | {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5487 | {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5488 | {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5489 | {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5490 | {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5491 | {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5492 | {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5493 | {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5494 | ||
5495 | {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5496 | {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5497 | {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5498 | {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5499 | {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5500 | {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5501 | {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5502 | {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5503 | {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5504 | {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5505 | {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5506 | {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5507 | {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5508 | {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5509 | {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5510 | {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5511 | ||
aae9718e PB |
5512 | {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDM}}, |
5513 | {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDP}}, | |
14b57c7c | 5514 | {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, |
aae9718e PB |
5515 | {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDM}}, |
5516 | {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDP}}, | |
14b57c7c | 5517 | {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, |
aae9718e PB |
5518 | {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDMA}}, |
5519 | {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDPA}}, | |
14b57c7c | 5520 | {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, |
aae9718e PB |
5521 | {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDMA}}, |
5522 | {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDPA}}, | |
14b57c7c AM |
5523 | {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, |
5524 | ||
5525 | {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, | |
dce75bf9 | 5526 | {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, |
14b57c7c AM |
5527 | {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, |
5528 | {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, | |
5529 | {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, | |
5530 | {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, | |
5531 | ||
5532 | {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, | |
5533 | {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, | |
5534 | {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, | |
5535 | {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, | |
5536 | ||
5537 | {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, | |
5538 | ||
1437d063 | 5539 | {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, |
14b57c7c AM |
5540 | {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, |
5541 | {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, | |
5542 | ||
14b57c7c | 5543 | {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
14b57c7c | 5544 | {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 AM |
5545 | {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
5546 | {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
14b57c7c | 5547 | {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 | 5548 | {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
14b57c7c | 5549 | {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
14b57c7c | 5550 | {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 AM |
5551 | {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
5552 | {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
14b57c7c | 5553 | {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 | 5554 | {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
14b57c7c AM |
5555 | {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
5556 | {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, | |
5557 | {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
5558 | {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, | |
5559 | {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5560 | {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5561 | {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5562 | {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5563 | {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5564 | {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5565 | {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5566 | {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5567 | ||
14b57c7c | 5568 | {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5569 | {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5570 | {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5571 | {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5572 | {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5573 | {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5574 | {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5575 | {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5576 | {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5577 | {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5578 | {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5579 | {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5580 | {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5581 | {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5582 | {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5583 | {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5584 | {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5585 | {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5586 | {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5587 | {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5588 | {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5589 | {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5590 | {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5591 | {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5592 | {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5593 | {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5594 | {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5595 | {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5596 | {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5597 | {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5598 | {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5599 | {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5600 | {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5601 | {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5602 | {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5603 | {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5604 | {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5605 | {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5606 | {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5607 | {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5608 | {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5609 | {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5610 | {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5611 | {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5612 | {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5613 | {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5614 | {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5615 | {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5616 | {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5617 | {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5618 | {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5619 | {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5620 | {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5621 | {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5622 | {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5623 | {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5624 | {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5625 | {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5626 | {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5627 | {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5628 | {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5629 | {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5630 | {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5631 | {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5632 | {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5633 | {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5634 | {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5635 | {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5636 | {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5637 | {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5638 | {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5639 | {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5640 | {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5641 | {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5642 | {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5643 | {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5644 | {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5645 | {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5646 | {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5647 | {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5648 | {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5649 | {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
14b57c7c | 5650 | {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5651 | {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5652 | {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5653 | {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5654 | {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5655 | {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5656 | {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5657 | {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5658 | {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5659 | {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5660 | {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5661 | {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5662 | {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5663 | {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5664 | {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5665 | {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5666 | {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5667 | {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5668 | {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5669 | {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5670 | {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5671 | {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5672 | {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5673 | {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5674 | {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5675 | {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5676 | {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5677 | {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5678 | {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5679 | {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5680 | {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5681 | {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5682 | {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5683 | {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5684 | {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5685 | {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5686 | {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5687 | {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5688 | {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5689 | {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5690 | {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5691 | {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5692 | {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5693 | {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5694 | {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5695 | {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5696 | {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5697 | {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5698 | {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5699 | {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5700 | {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5701 | {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5702 | {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5703 | {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5704 | {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5705 | {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5706 | {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5707 | {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5708 | ||
14b57c7c | 5709 | {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5710 | {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5711 | {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5712 | {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5713 | {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5714 | {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5715 | {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5716 | {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5717 | {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5718 | {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5719 | {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5720 | {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5721 | {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5722 | {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
5723 | {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
14b57c7c | 5724 | {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
14b57c7c | 5725 | {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5726 | {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5727 | {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5728 | {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
14b57c7c AM |
5729 | {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5730 | {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5731 | {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5732 | {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
14b57c7c | 5733 | {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5734 | {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5735 | {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5736 | {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5737 | {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5738 | {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5739 | {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5740 | {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5741 | {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5742 | {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5743 | {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5744 | {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5745 | {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5746 | {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
5747 | {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
14b57c7c | 5748 | {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
14b57c7c | 5749 | {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5750 | {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5751 | {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5752 | {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
14b57c7c AM |
5753 | {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5754 | {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5755 | {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5756 | {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5757 | ||
66e85460 AM |
5758 | {"bclr-", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, |
5759 | {"bclr+", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5760 | {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 AM |
5761 | {"bcr", XLLK(19,16,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
5762 | {"bclrl-", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, | |
5763 | {"bclrl+", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5764 | {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 | 5765 | {"bcrl", XLLK(19,16,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
14b57c7c AM |
5766 | |
5767 | {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, | |
5768 | ||
98553ad3 | 5769 | {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, |
14b57c7c AM |
5770 | {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5771 | {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, | |
5772 | ||
5773 | {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, | |
5774 | {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, | |
5775 | {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, | |
5776 | ||
dce75bf9 | 5777 | {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, |
14b57c7c AM |
5778 | {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, |
5779 | ||
5780 | {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, | |
5781 | ||
5782 | {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5783 | ||
5784 | {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, | |
5785 | ||
5786 | {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
5787 | {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, | |
5788 | ||
98553ad3 | 5789 | {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, |
14b57c7c AM |
5790 | {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5791 | ||
5792 | {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, | |
5793 | ||
5794 | {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5795 | ||
5796 | {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5797 | ||
5798 | {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, | |
5799 | ||
98553ad3 | 5800 | {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, |
14b57c7c AM |
5801 | {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5802 | ||
5803 | {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, | |
5804 | {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, | |
5805 | ||
5806 | {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5807 | ||
5808 | {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5809 | ||
5810 | {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5811 | ||
98553ad3 | 5812 | {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, |
14b57c7c AM |
5813 | {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5814 | ||
5815 | {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5816 | {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5817 | ||
5818 | {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}}, | |
5819 | {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}}, | |
5820 | ||
14b57c7c | 5821 | {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5822 | {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5823 | {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5824 | {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5825 | {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5826 | {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5827 | {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5828 | {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5829 | {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5830 | {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5831 | {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5832 | {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5833 | {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5834 | {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5835 | {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5836 | {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5837 | {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5838 | {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5839 | {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5840 | {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5841 | {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5842 | {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5843 | {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5844 | {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5845 | {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5846 | {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5847 | {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5848 | {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5849 | {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5850 | {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5851 | {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5852 | {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5853 | {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5854 | {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5855 | {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5856 | {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5857 | {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5858 | {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5859 | {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5860 | {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5861 | {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5862 | {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5863 | {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5864 | {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5865 | {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5866 | {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5867 | {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5868 | {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5869 | {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5870 | {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5871 | {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5872 | {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5873 | {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5874 | {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5875 | {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5876 | {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5877 | {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5878 | {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5879 | {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5880 | {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5881 | {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5882 | {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5883 | {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5884 | {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5885 | {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5886 | {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5887 | {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5888 | {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5889 | {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5890 | {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
14b57c7c | 5891 | {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5892 | {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5893 | {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5894 | {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5895 | {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5896 | {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5897 | {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5898 | {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5899 | {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5900 | {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5901 | {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5902 | {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5903 | {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5904 | {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5905 | {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5906 | {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5907 | {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5908 | {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5909 | {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5910 | {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5911 | {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5912 | {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5913 | {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5914 | {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5915 | {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5916 | {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5917 | {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5918 | {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5919 | {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5920 | {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5921 | {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5922 | {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5923 | {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5924 | {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5925 | {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5926 | {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5927 | {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5928 | {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5929 | {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5930 | {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5931 | {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5932 | {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5933 | {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5934 | {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5935 | {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5936 | {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5937 | {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5938 | {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5939 | {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5940 | {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5941 | ||
14b57c7c | 5942 | {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5943 | {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5944 | {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5945 | {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5946 | {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5947 | {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c AM |
5948 | {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5949 | {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5950 | {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5951 | {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
14b57c7c | 5952 | {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5953 | {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5954 | {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5955 | {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5956 | {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5957 | {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c AM |
5958 | {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5959 | {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5960 | {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5961 | {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5962 | ||
66e85460 AM |
5963 | {"bcctr-", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, |
5964 | {"bcctr+", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5965 | {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 AM |
5966 | {"bcc", XLLK(19,528,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
5967 | {"bcctrl-", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, | |
5968 | {"bcctrl+", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5969 | {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 | 5970 | {"bccl", XLLK(19,528,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
14b57c7c | 5971 | |
aae9718e PB |
5972 | {"bdnztar", XLO(19,BODNZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, |
5973 | {"bdnztarl", XLO(19,BODNZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5974 | {"bdztar", XLO(19,BODZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5975 | {"bdztarl", XLO(19,BODZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5976 | {"btar", XLO(19,BOU,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5977 | {"btarl", XLO(19,BOU,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5978 | {"bdnztar-", XLO(19,BODNZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5979 | {"bdnztarl-", XLO(19,BODNZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5980 | {"bdnztar+", XLO(19,BODNZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5981 | {"bdnztarl+", XLO(19,BODNZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5982 | {"bdztar-", XLO(19,BODZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5983 | {"bdztarl-", XLO(19,BODZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5984 | {"bdztar+", XLO(19,BODZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5985 | {"bdztarl+", XLO(19,BODZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5986 | ||
5987 | {"bgetar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5988 | {"bnltar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5989 | {"bgetarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5990 | {"bnltarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5991 | {"bletar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5992 | {"bngtar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5993 | {"bletarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5994 | {"bngtarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5995 | {"bnetar", XLOCB(19,BOF,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5996 | {"bnetarl", XLOCB(19,BOF,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5997 | {"bnstar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5998 | {"bnutar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5999 | {"bnstarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6000 | {"bnutarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6001 | {"bgetar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6002 | {"bnltar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6003 | {"bgetarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6004 | {"bnltarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6005 | {"bletar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6006 | {"bngtar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6007 | {"bletarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6008 | {"bngtarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6009 | {"bnetar-", XLOCB(19,BOFM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6010 | {"bnetarl-",XLOCB(19,BOFM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6011 | {"bnstar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6012 | {"bnutar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6013 | {"bnstarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6014 | {"bnutarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6015 | {"bgetar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6016 | {"bnltar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6017 | {"bgetarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6018 | {"bnltarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6019 | {"bletar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6020 | {"bngtar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6021 | {"bletarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6022 | {"bngtarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6023 | {"bnetar+", XLOCB(19,BOFP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6024 | {"bnetarl+",XLOCB(19,BOFP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6025 | {"bnstar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6026 | {"bnutar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6027 | {"bnstarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6028 | {"bnutarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6029 | {"blttar", XLOCB(19,BOT,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6030 | {"blttarl", XLOCB(19,BOT,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6031 | {"bgttar", XLOCB(19,BOT,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6032 | {"bgttarl", XLOCB(19,BOT,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6033 | {"beqtar", XLOCB(19,BOT,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6034 | {"beqtarl", XLOCB(19,BOT,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6035 | {"bsotar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6036 | {"buntar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6037 | {"bsotarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6038 | {"buntarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6039 | {"blttar-", XLOCB(19,BOTM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6040 | {"blttarl-",XLOCB(19,BOTM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6041 | {"bgttar-", XLOCB(19,BOTM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6042 | {"bgttarl-",XLOCB(19,BOTM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6043 | {"beqtar-", XLOCB(19,BOTM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6044 | {"beqtarl-",XLOCB(19,BOTM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6045 | {"bsotar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6046 | {"buntar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6047 | {"bsotarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6048 | {"buntarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6049 | {"blttar+", XLOCB(19,BOTP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6050 | {"blttarl+",XLOCB(19,BOTP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6051 | {"bgttar+", XLOCB(19,BOTP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6052 | {"bgttarl+",XLOCB(19,BOTP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6053 | {"beqtar+", XLOCB(19,BOTP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6054 | {"beqtarl+",XLOCB(19,BOTP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6055 | {"bsotar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6056 | {"buntar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6057 | {"bsotarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6058 | {"buntarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
6059 | ||
6060 | {"bdnzftar", XLO(19,BODNZF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6061 | {"bdnzftarl", XLO(19,BODNZF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6062 | {"bdzftar", XLO(19,BODZF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6063 | {"bdzftarl", XLO(19,BODZF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6064 | ||
6065 | {"bftar", XLO(19,BOF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6066 | {"bftarl", XLO(19,BOF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6067 | {"bftar-", XLO(19,BOFM4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6068 | {"bftarl-", XLO(19,BOFM4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6069 | {"bftar+", XLO(19,BOFP4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6070 | {"bftarl+", XLO(19,BOFP4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6071 | ||
6072 | {"bdnzttar", XLO(19,BODNZT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6073 | {"bdnzttarl", XLO(19,BODNZT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6074 | {"bdzttar", XLO(19,BODZT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6075 | {"bdzttarl", XLO(19,BODZT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6076 | ||
6077 | {"bttar", XLO(19,BOT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6078 | {"bttarl", XLO(19,BOT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6079 | {"bttar-", XLO(19,BOTM4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6080 | {"bttarl-", XLO(19,BOTM4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6081 | {"bttar+", XLO(19,BOTP4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6082 | {"bttarl+", XLO(19,BOTP4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
6083 | ||
66e85460 AM |
6084 | {"bctar-", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BOM, BI, BH}}, |
6085 | {"bctar+", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 6086 | {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, |
66e85460 AM |
6087 | {"bctarl-", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BOM, BI, BH}}, |
6088 | {"bctarl+", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c AM |
6089 | {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, |
6090 | ||
6091 | {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6092 | {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6093 | ||
6094 | {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6095 | {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6096 | ||
6097 | {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, | |
6098 | {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, | |
6099 | {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6100 | {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6101 | {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, | |
6102 | {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, | |
6103 | {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6104 | {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
6105 | ||
6106 | {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
6107 | {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
6108 | ||
6109 | {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, | |
6110 | {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
6111 | {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
6112 | {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, | |
6113 | {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
6114 | {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
6115 | ||
6116 | {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
6117 | {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
6118 | {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
6119 | ||
6120 | {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
6121 | {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
6122 | ||
6123 | {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
6124 | {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
6125 | {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
6126 | ||
6127 | {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
6128 | {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
6129 | ||
6130 | {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
6131 | {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
6132 | ||
6133 | {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
6134 | {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
6135 | ||
6136 | {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, | |
6137 | {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, | |
6138 | {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
6139 | {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, | |
6140 | {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, | |
6141 | {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
6142 | ||
6143 | {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, | |
6144 | {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, | |
6145 | ||
6146 | {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
6147 | {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
6148 | ||
6149 | {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
6150 | {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
6151 | ||
6152 | {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, | |
6153 | {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, | |
6154 | {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, | |
6155 | {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, | |
6156 | ||
6157 | {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, | |
6158 | {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, | |
6159 | ||
6160 | {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, | |
6161 | {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, | |
a5721ba2 | 6162 | {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
bdc70b4a | 6163 | {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
1cb0a767 | 6164 | |
14b57c7c AM |
6165 | {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
6166 | {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6167 | {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6168 | {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6169 | {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6170 | {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6171 | {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6172 | {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6173 | {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6174 | {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6175 | {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6176 | {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6177 | {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6178 | {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6179 | {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6180 | {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6181 | {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6182 | {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6183 | {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6184 | {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6185 | {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6186 | {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6187 | {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6188 | {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6189 | {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6190 | {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6191 | {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6192 | {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6193 | {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, | |
6194 | {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6195 | {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6196 | {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, | |
6197 | {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, | |
6198 | ||
6199 | {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6200 | {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6201 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
6202 | ||
6203 | {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6204 | {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6205 | {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
6206 | {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6207 | {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6208 | {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
6209 | ||
6210 | {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6211 | {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6212 | ||
6213 | {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6214 | {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6215 | {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6216 | {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6217 | ||
6218 | {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6219 | {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6220 | ||
6221 | {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, | |
6222 | ||
9cc4ce88 AM |
6223 | {"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6224 | ||
14b57c7c AM |
6225 | {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
6226 | ||
6227 | {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, | |
6228 | {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, | |
6229 | {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, | |
6230 | {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, | |
6231 | ||
6232 | {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, | |
6233 | {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, | |
6234 | ||
6235 | {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, | |
6236 | ||
6237 | {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, | |
6238 | ||
6239 | {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, | |
6240 | ||
6241 | {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, | |
6242 | {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6243 | ||
6244 | {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
6245 | {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
6246 | {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
6247 | {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
6248 | ||
6249 | {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
6250 | {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
6251 | {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
6252 | {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
6253 | ||
6254 | {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
6255 | {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
6256 | ||
6257 | {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, | |
6258 | {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
6259 | ||
6260 | {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, | |
6261 | {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, | |
6262 | ||
6263 | {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | |
6264 | ||
6265 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, | |
3d205eb4 PB |
6266 | {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, 0, {0}}, |
6267 | {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, 0, {0}}, | |
6268 | {"wait", X(31,30), XWCPL_MASK, POWER10, 0, {WC, PL}}, | |
6269 | {"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}}, | |
14b57c7c AM |
6270 | |
6271 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | |
6272 | ||
6273 | {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, | |
6274 | {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, | |
a5721ba2 | 6275 | {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
bdc70b4a | 6276 | {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
de866fcc | 6277 | |
14b57c7c AM |
6278 | {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
6279 | {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6280 | {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6281 | |
9cc4ce88 AM |
6282 | {"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6283 | ||
ac8f0f72 | 6284 | {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, |
e67ed0e8 | 6285 | |
14b57c7c | 6286 | {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
de866fcc | 6287 | |
14b57c7c | 6288 | {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
de866fcc | 6289 | |
14b57c7c | 6290 | {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, |
066be9f7 | 6291 | |
14b57c7c | 6292 | {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
c0637f3a | 6293 | |
9cc4ce88 AM |
6294 | {"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6295 | ||
14b57c7c | 6296 | {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
de866fcc | 6297 | |
14b57c7c | 6298 | {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, |
de866fcc | 6299 | |
14b57c7c AM |
6300 | {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6301 | {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
6302 | {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6303 | {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
de866fcc | 6304 | |
14b57c7c AM |
6305 | {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, |
6306 | {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, | |
6307 | {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, | |
6308 | {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, | |
e0d602ec | 6309 | |
14b57c7c | 6310 | {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
066be9f7 | 6311 | |
14b57c7c | 6312 | {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
43e65147 | 6313 | |
14b57c7c | 6314 | {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, |
43e65147 | 6315 | |
14b57c7c AM |
6316 | {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, |
6317 | {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 6318 | |
14b57c7c AM |
6319 | {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
6320 | {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, | |
de866fcc | 6321 | |
ec40e91c AM |
6322 | {"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}}, |
6323 | ||
14b57c7c AM |
6324 | {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6325 | {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
de866fcc | 6326 | |
14b57c7c AM |
6327 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
6328 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, | |
6329 | {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, | |
43e65147 | 6330 | |
14b57c7c | 6331 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
19a6653c | 6332 | |
14b57c7c AM |
6333 | {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, |
6334 | {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6335 | {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6336 | {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6337 | {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6338 | {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6339 | {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6340 | {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6341 | {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6342 | {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6343 | {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6344 | {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6345 | {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6346 | {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6347 | {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6348 | {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, | |
de866fcc | 6349 | |
14b57c7c AM |
6350 | {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
6351 | {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6352 | {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 6353 | |
14b57c7c AM |
6354 | {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6355 | {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
de866fcc | 6356 | |
62adc510 AM |
6357 | {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, |
6358 | {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, | |
de866fcc | 6359 | |
14b57c7c | 6360 | {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, |
de866fcc | 6361 | |
14b57c7c | 6362 | {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, |
43e65147 | 6363 | |
14b57c7c | 6364 | {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, |
de866fcc | 6365 | |
c7a8dbf9 | 6366 | {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, |
3d205eb4 PB |
6367 | {"dcbflp", XOPL2(31,86,3), XRT_MASK, POWER9, PPC476, {RA0, RB}}, |
6368 | {"dcbfps", XOPL3(31,86,4), XRT_MASK, POWER10, PPC476, {RA0, RB}}, | |
6369 | {"dcbstps", XOPL3(31,86,6), XRT_MASK, POWER10, PPC476, {RA0, RB}}, | |
6370 | {"dcbf", X(31,86), XL3RT_MASK, POWER10, PPC476, {RA0, RB, L3OPT}}, | |
6371 | {"dcbf", X(31,86), XLRT_MASK, PPC, POWER10, {RA0, RB, L2OPT}}, | |
de866fcc | 6372 | |
14b57c7c | 6373 | {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, |
43e65147 | 6374 | |
14b57c7c | 6375 | {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
de866fcc | 6376 | |
14b57c7c | 6377 | {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, |
aea77599 | 6378 | |
14b57c7c AM |
6379 | {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
6380 | {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6381 | |
14b57c7c AM |
6382 | {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, |
6383 | {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, | |
de866fcc | 6384 | |
14b57c7c AM |
6385 | {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6386 | {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
de866fcc | 6387 | |
9cc4ce88 AM |
6388 | {"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6389 | ||
ac8f0f72 | 6390 | {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}}, |
aea77599 | 6391 | |
14b57c7c | 6392 | {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, |
de866fcc | 6393 | |
14b57c7c AM |
6394 | {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, |
6395 | {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, | |
6396 | {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, | |
c0637f3a | 6397 | |
14b57c7c | 6398 | {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
066be9f7 | 6399 | |
14b57c7c | 6400 | {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, |
de866fcc | 6401 | |
14b57c7c | 6402 | {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, |
43e65147 | 6403 | |
14b57c7c | 6404 | {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, |
de866fcc | 6405 | |
98553ad3 | 6406 | {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 6407 | {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, |
98553ad3 | 6408 | {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 6409 | {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, |
19a6653c | 6410 | |
14b57c7c | 6411 | {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
43e65147 | 6412 | |
fd486b63 | 6413 | {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
a680de9a | 6414 | |
14b57c7c | 6415 | {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, |
43e65147 | 6416 | |
14b57c7c | 6417 | {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
de866fcc | 6418 | |
14b57c7c AM |
6419 | {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6420 | {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6421 | |
14b57c7c AM |
6422 | {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6423 | {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6424 | {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6425 | {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 6426 | |
14b57c7c AM |
6427 | {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6428 | {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6429 | {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6430 | {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 6431 | |
14b57c7c | 6432 | {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
c0637f3a | 6433 | |
9cc4ce88 AM |
6434 | {"stxvrbx", X(31,141), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6435 | ||
14b57c7c AM |
6436 | {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
6437 | {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, | |
de866fcc | 6438 | |
14b57c7c AM |
6439 | {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, |
6440 | {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, | |
6441 | {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, | |
de866fcc | 6442 | |
14b57c7c | 6443 | {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, |
de866fcc | 6444 | |
14b57c7c | 6445 | {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, |
c0637f3a | 6446 | |
14b57c7c AM |
6447 | {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
6448 | {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, | |
e0d602ec | 6449 | |
14b57c7c | 6450 | {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
43e65147 | 6451 | |
14b57c7c | 6452 | {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, |
43e65147 | 6453 | |
14b57c7c AM |
6454 | {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
6455 | {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, | |
de866fcc | 6456 | |
14b57c7c AM |
6457 | {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6458 | {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
de866fcc | 6459 | |
14b57c7c AM |
6460 | {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6461 | {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
de866fcc | 6462 | |
14b57c7c | 6463 | {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, |
de866fcc | 6464 | |
3ff0a5ba | 6465 | {"brw", X(31,155), XRB_MASK, POWER10, 0, {RA, RS}}, |
ec40e91c | 6466 | {"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}}, |
3ff0a5ba | 6467 | |
14b57c7c | 6468 | {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 6469 | |
14b57c7c | 6470 | {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 6471 | |
14b57c7c | 6472 | {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, |
43e65147 | 6473 | |
14b57c7c | 6474 | {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
de866fcc | 6475 | |
14b57c7c AM |
6476 | {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6477 | {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6478 | |
14b57c7c | 6479 | {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, |
19dfcc89 | 6480 | |
9cc4ce88 AM |
6481 | {"stxvrhx", X(31,173), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6482 | ||
14b57c7c AM |
6483 | {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
6484 | {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, | |
de866fcc | 6485 | |
aa3c112f AM |
6486 | {"xxmfacc", XVA(31,177,0), XRARB_MASK|3<<21, POWER10, 0, {ACC}}, |
6487 | {"xxmtacc", XVA(31,177,1), XRARB_MASK|3<<21, POWER10, 0, {ACC}}, | |
6488 | {"xxsetaccz", XVA(31,177,3), XRARB_MASK|3<<21, POWER10, 0, {ACC}}, | |
6489 | ||
14b57c7c | 6490 | {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, |
de866fcc | 6491 | |
14b57c7c AM |
6492 | {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, |
6493 | {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, | |
6494 | {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
6495 | {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, | |
e0d602ec | 6496 | |
14b57c7c | 6497 | {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, |
de866fcc | 6498 | |
73f07bff | 6499 | {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, |
14b57c7c | 6500 | {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, |
e0d602ec | 6501 | |
14b57c7c AM |
6502 | {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, |
6503 | {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
de866fcc | 6504 | |
14b57c7c AM |
6505 | {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6506 | {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
de866fcc | 6507 | |
14b57c7c | 6508 | {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, |
252b5132 | 6509 | |
3ff0a5ba | 6510 | {"brd", X(31,187), XRB_MASK, POWER10, 0, {RA, RS}}, |
ec40e91c | 6511 | {"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}}, |
3ff0a5ba | 6512 | |
14b57c7c | 6513 | {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, |
a680de9a | 6514 | |
14b57c7c | 6515 | {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
aea77599 | 6516 | |
14b57c7c AM |
6517 | {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6518 | {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 6519 | |
14b57c7c AM |
6520 | {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6521 | {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6522 | {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6523 | {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 6524 | |
14b57c7c AM |
6525 | {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6526 | {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6527 | {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6528 | {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 6529 | |
9cc4ce88 AM |
6530 | {"stxvrwx", X(31,205), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6531 | ||
14b57c7c | 6532 | {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, |
19a6653c | 6533 | |
14b57c7c | 6534 | {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, |
418c1742 | 6535 | |
14b57c7c AM |
6536 | {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
6537 | {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
6538 | {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, | |
6539 | {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, | |
e0d602ec | 6540 | |
14b57c7c | 6541 | {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
e0d602ec | 6542 | |
14b57c7c | 6543 | {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
43e65147 | 6544 | |
14b57c7c | 6545 | {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, |
252b5132 | 6546 | |
14b57c7c AM |
6547 | {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6548 | {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6549 | |
14b57c7c AM |
6550 | {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6551 | {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6552 | |
3ff0a5ba | 6553 | {"brh", X(31,219), XRB_MASK, POWER10, 0, {RA, RS}}, |
ec40e91c | 6554 | {"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}}, |
3ff0a5ba | 6555 | |
14b57c7c | 6556 | {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 6557 | |
14b57c7c | 6558 | {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, |
a680de9a | 6559 | |
14b57c7c | 6560 | {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
7d5b217e | 6561 | |
14b57c7c AM |
6562 | {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6563 | {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
f509565f | 6564 | |
14b57c7c AM |
6565 | {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6566 | {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6567 | {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6568 | {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 6569 | |
14b57c7c AM |
6570 | {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6571 | {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 6572 | |
14b57c7c AM |
6573 | {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6574 | {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6575 | {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6576 | {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 6577 | |
14b57c7c AM |
6578 | {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6579 | {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6580 | {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6581 | {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6582 | |
9cc4ce88 AM |
6583 | {"stxvrdx", X(31,237), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6584 | ||
14b57c7c AM |
6585 | {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, |
6586 | {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, | |
6587 | {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, | |
bdc70b4a | 6588 | {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, |
418c1742 | 6589 | |
14b57c7c AM |
6590 | {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
6591 | {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
6592 | {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, | |
c0637f3a | 6593 | |
14b57c7c AM |
6594 | {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
6595 | {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, | |
6596 | {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, | |
6597 | {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, | |
4fff86c5 | 6598 | |
14b57c7c | 6599 | {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, |
252b5132 | 6600 | |
14b57c7c AM |
6601 | {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6602 | {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 6603 | |
14b57c7c | 6604 | {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, |
066be9f7 | 6605 | |
14b57c7c | 6606 | {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
19a6653c | 6607 | |
14b57c7c AM |
6608 | {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, |
6609 | {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, | |
252b5132 | 6610 | |
ac8f0f72 | 6611 | {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6612 | |
14b57c7c | 6613 | {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, |
1ed8e1e4 | 6614 | |
ac8f0f72 | 6615 | {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6616 | |
14b57c7c AM |
6617 | {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
6618 | {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6619 | {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 6620 | |
14b57c7c | 6621 | {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, |
a680de9a | 6622 | |
14b57c7c AM |
6623 | {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6624 | {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6625 | {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6626 | {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
418c1742 | 6627 | |
14b57c7c | 6628 | {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, |
a680de9a | 6629 | |
14b57c7c AM |
6630 | {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, |
6631 | {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
a680de9a | 6632 | |
14b57c7c | 6633 | {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
19a6653c | 6634 | |
62adc510 | 6635 | {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}}, |
a5721ba2 | 6636 | {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, |
418c1742 | 6637 | |
14b57c7c | 6638 | {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, |
1cb0a767 | 6639 | |
73f07bff | 6640 | {"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, |
c0637f3a | 6641 | |
14b57c7c AM |
6642 | {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, |
6643 | {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, | |
1cb0a767 | 6644 | |
14b57c7c AM |
6645 | {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
6646 | {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, | |
6647 | {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, | |
6648 | {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, | |
4fff86c5 | 6649 | |
14b57c7c | 6650 | {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, |
1cb0a767 | 6651 | |
14b57c7c | 6652 | {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, |
066be9f7 | 6653 | |
14b57c7c AM |
6654 | {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6655 | {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 6656 | |
14b57c7c | 6657 | {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
1cb0a767 | 6658 | |
62adc510 | 6659 | {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}}, |
1cb0a767 | 6660 | |
ac8f0f72 AM |
6661 | {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}}, |
6662 | {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}}, | |
aea77599 | 6663 | |
14b57c7c | 6664 | {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 6665 | |
14b57c7c | 6666 | {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, |
c0637f3a | 6667 | |
14b57c7c AM |
6668 | {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, |
6669 | {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, | |
a5721ba2 | 6670 | {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, |
14b57c7c | 6671 | {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, |
1cb0a767 | 6672 | |
14b57c7c | 6673 | {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, |
a680de9a | 6674 | |
14b57c7c | 6675 | {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
1cb0a767 | 6676 | |
14b57c7c | 6677 | {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, |
1cb0a767 | 6678 | |
14b57c7c | 6679 | {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, |
066be9f7 | 6680 | |
14b57c7c AM |
6681 | {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6682 | {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 6683 | |
14b57c7c | 6684 | {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
1cb0a767 | 6685 | |
14b57c7c AM |
6686 | {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, |
6687 | {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, | |
6688 | {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, | |
6689 | {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, | |
6690 | {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, | |
6691 | {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, | |
6692 | {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, | |
6693 | {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, | |
6694 | {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, | |
6695 | {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, | |
6696 | {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, | |
6697 | {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, | |
6698 | {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, | |
6699 | {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, | |
6700 | {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, | |
6701 | {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, | |
6702 | {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, | |
6703 | {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, | |
6704 | {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, | |
6705 | {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, | |
6706 | {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, | |
6707 | {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, | |
6708 | {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, | |
6709 | {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, | |
6710 | {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, | |
6711 | {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, | |
6712 | {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, | |
6713 | {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, | |
6714 | {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, | |
6715 | {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, | |
6716 | {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, | |
6717 | {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, | |
6718 | {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, | |
6719 | {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, | |
6720 | {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, | |
6721 | {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, | |
1cb0a767 | 6722 | |
ac8f0f72 | 6723 | {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6724 | |
14b57c7c | 6725 | {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, |
9fe54b1c | 6726 | |
14b57c7c AM |
6727 | {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6728 | {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
1cb0a767 | 6729 | |
14b57c7c | 6730 | {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
066be9f7 | 6731 | |
94ba9882 AM |
6732 | {"lxvpx", X(31,333), XX1_MASK, POWER10, 0, {XTP, RA0, RB}}, |
6733 | ||
14b57c7c | 6734 | {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, |
c03dc33b | 6735 | {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}}, |
1cb0a767 | 6736 | |
14b57c7c AM |
6737 | {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}}, |
6738 | ||
6739 | {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, | |
6740 | {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, | |
6741 | {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, | |
6742 | {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, | |
6743 | {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, | |
6744 | {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, | |
6745 | {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, | |
6746 | {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, | |
6747 | {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, | |
6748 | {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, | |
6749 | {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, | |
bdc70b4a | 6750 | {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, |
14b57c7c AM |
6751 | {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, |
6752 | {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, | |
6753 | {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, | |
6754 | {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, | |
6755 | {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, | |
6756 | {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, | |
6757 | {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, | |
6758 | {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, | |
6759 | {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, | |
6760 | {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, | |
6761 | {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, | |
6762 | {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, | |
6763 | {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, | |
6764 | {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, | |
6765 | {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, | |
6766 | {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, | |
6767 | {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, | |
6768 | {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, | |
6769 | {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, | |
6770 | {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, | |
6771 | {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, | |
6772 | {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, | |
6773 | {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, | |
6774 | {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, | |
6775 | {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, | |
6776 | {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, | |
6777 | {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, | |
6778 | {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, | |
6779 | {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, | |
6780 | {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, | |
6781 | {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, | |
6782 | {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6783 | {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6784 | {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6785 | {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6786 | {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, | |
6787 | {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, | |
6788 | {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, | |
6789 | {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, | |
6790 | {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, | |
6791 | {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, | |
6792 | {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, | |
6793 | {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, | |
6794 | {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, | |
6795 | {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, | |
6796 | {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, | |
6797 | {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, | |
6798 | {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, | |
6799 | {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, | |
6800 | {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, | |
6801 | {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, | |
6802 | {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, | |
6803 | {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, | |
6804 | {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, | |
6805 | {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, | |
6806 | {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, | |
6807 | {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, | |
6808 | {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, | |
6809 | {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, | |
6810 | {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, | |
6811 | {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, | |
6812 | {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, | |
6813 | {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, | |
6814 | {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, | |
6815 | {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, | |
6816 | {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, | |
6817 | {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, | |
6818 | {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, | |
6819 | {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, | |
6820 | {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, | |
6821 | {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, | |
6822 | {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, | |
6823 | {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, | |
6824 | {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, | |
6825 | {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, | |
6826 | {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, | |
6827 | {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, | |
6828 | {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, | |
6829 | {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, | |
4b94dd2d AM |
6830 | {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, |
6831 | {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, | |
14b57c7c AM |
6832 | {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, |
6833 | {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, | |
4b94dd2d AM |
6834 | {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
6835 | {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, | |
14b57c7c AM |
6836 | {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
6837 | {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, | |
6838 | {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, | |
6839 | {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, | |
6840 | {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, | |
6841 | {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, | |
6842 | {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, | |
6843 | {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, | |
6844 | {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
6845 | {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
6846 | {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
6847 | {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, | |
6848 | {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, | |
6849 | {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, | |
6850 | {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, | |
bb71536f AM |
6851 | {"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, |
6852 | {"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, | |
6853 | {"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, | |
6854 | {"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, | |
6855 | {"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, | |
6856 | {"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, | |
6857 | {"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, | |
6858 | {"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, | |
6859 | {"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, | |
6860 | {"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, | |
6861 | {"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, | |
6862 | {"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, | |
14b57c7c AM |
6863 | {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, |
6864 | {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, | |
6865 | {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, | |
6866 | {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, | |
6867 | {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, | |
6868 | {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, | |
6869 | {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, | |
6870 | {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, | |
6871 | {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, | |
6872 | {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, | |
6873 | {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, | |
6874 | {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, | |
6875 | {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, | |
6876 | {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, | |
6877 | {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, | |
6878 | {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, | |
6879 | {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, | |
6880 | {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, | |
6881 | {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, | |
6882 | {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, | |
6883 | {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, | |
6884 | {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, | |
6885 | {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, | |
6886 | {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, | |
6887 | {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, | |
6888 | {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, | |
6889 | {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, | |
fa758a70 AC |
6890 | {"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, 0, {RT, SPRGQR}}, |
6891 | {"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, 0, {RT}}, | |
6892 | {"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, 0, {RT}}, | |
6893 | {"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, 0, {RT}}, | |
6894 | {"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, 0, {RT}}, | |
14b57c7c AM |
6895 | {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, |
6896 | {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, | |
6897 | {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, | |
6898 | {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, | |
6899 | {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, | |
6900 | {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, | |
6901 | {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, | |
6902 | {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, | |
6903 | {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, | |
6904 | {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, | |
6905 | {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, | |
6906 | {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, | |
6907 | {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, | |
6908 | {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, | |
6909 | {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, | |
6910 | {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, | |
6911 | {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, | |
6912 | {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, | |
6913 | {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, | |
6914 | {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, | |
6915 | {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, | |
6916 | {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, | |
6917 | {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, | |
6918 | {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, | |
6919 | {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, | |
6920 | {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, | |
6921 | {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, | |
6922 | {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, | |
6923 | {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, | |
6924 | {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, | |
6925 | {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, | |
6926 | {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, | |
6927 | {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, | |
6928 | {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, | |
6929 | {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, | |
6930 | {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, | |
6931 | {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, | |
6932 | {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, | |
6933 | {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, | |
6934 | {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, | |
6935 | {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, | |
6936 | {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, | |
6937 | {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, | |
6938 | {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, | |
fa758a70 AC |
6939 | {"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, 0, {RT}}, |
6940 | {"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, 0, {RT}}, | |
14b57c7c | 6941 | {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, |
fa758a70 AC |
6942 | {"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, 0, {RT}}, |
6943 | {"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, 0, {RT}}, | |
14b57c7c AM |
6944 | {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, |
6945 | {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, | |
6946 | {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, | |
fa758a70 | 6947 | {"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, 0, {RT}}, |
14b57c7c AM |
6948 | {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, |
6949 | {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, | |
6950 | {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, | |
6951 | {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, | |
6952 | {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, | |
6953 | {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, | |
6954 | {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, | |
6955 | {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, | |
6956 | {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, | |
6957 | {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, | |
6958 | {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, | |
6959 | {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, | |
6960 | {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, | |
6961 | {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, | |
6962 | ||
6963 | {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, | |
6964 | ||
6965 | {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, | |
6966 | ||
6967 | {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, | |
6968 | ||
6969 | {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6970 | ||
6971 | {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, | |
6972 | {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, | |
6973 | ||
6974 | {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6975 | {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6976 | ||
6977 | {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
6978 | ||
6979 | {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, | |
1cb0a767 | 6980 | |
db76a700 | 6981 | {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
14b57c7c | 6982 | {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, |
db76a700 | 6983 | {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
1cb0a767 | 6984 | |
14b57c7c | 6985 | {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
1cb0a767 | 6986 | |
14b57c7c | 6987 | {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
1cb0a767 | 6988 | |
14b57c7c | 6989 | {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, |
1cb0a767 | 6990 | |
14b57c7c | 6991 | {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
066be9f7 | 6992 | |
4f3e9537 PB |
6993 | {"setbc", X(31,384), XRB_MASK, POWER10, 0, {RT, BI}}, |
6994 | ||
14b57c7c AM |
6995 | {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, |
6996 | {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, | |
1cb0a767 | 6997 | |
ac8f0f72 | 6998 | {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6999 | |
14b57c7c AM |
7000 | {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
7001 | {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
1cb0a767 | 7002 | |
14b57c7c AM |
7003 | {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
7004 | {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7005 | {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7006 | {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 7007 | |
14b57c7c AM |
7008 | {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
7009 | {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
a680de9a | 7010 | |
14b57c7c | 7011 | {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
1cb0a767 | 7012 | |
14b57c7c | 7013 | {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, |
1cb0a767 | 7014 | |
14b57c7c | 7015 | {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, |
a680de9a | 7016 | |
14b57c7c | 7017 | {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, |
c0637f3a | 7018 | |
14b57c7c AM |
7019 | {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, |
7020 | {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, | |
e0d602ec | 7021 | |
14b57c7c | 7022 | {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, |
1cb0a767 | 7023 | |
14b57c7c AM |
7024 | {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, |
7025 | {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 7026 | |
14b57c7c | 7027 | {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
1cb0a767 | 7028 | |
4f3e9537 PB |
7029 | {"setbcr", X(31,416), XRB_MASK, POWER10, 0, {RT, BI}}, |
7030 | ||
62adc510 | 7031 | {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}}, |
1cb0a767 | 7032 | |
ac8f0f72 | 7033 | {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7034 | |
14b57c7c | 7035 | {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
aea77599 | 7036 | |
14b57c7c AM |
7037 | {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
7038 | {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7039 | {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7040 | {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 7041 | |
14b57c7c | 7042 | {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
a680de9a | 7043 | |
14b57c7c | 7044 | {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}}, |
c0637f3a | 7045 | |
14b57c7c | 7046 | {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, |
1cb0a767 | 7047 | |
14b57c7c | 7048 | {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 7049 | |
14b57c7c | 7050 | {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
1cb0a767 | 7051 | |
14b57c7c | 7052 | {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, |
1cb0a767 | 7053 | |
14b57c7c | 7054 | {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}}, |
1cb0a767 | 7055 | |
14b57c7c | 7056 | {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}}, |
aea77599 | 7057 | |
9f6a6cc0 | 7058 | /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for |
14b57c7c AM |
7059 | "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ |
7060 | {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}}, | |
7061 | {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}}, | |
7062 | {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}}, | |
98553ad3 | 7063 | {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 7064 | {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, |
98553ad3 | 7065 | {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c AM |
7066 | {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, |
7067 | ||
4f3e9537 PB |
7068 | {"setnbc", X(31,448), XRB_MASK, POWER10, 0, {RT, BI}}, |
7069 | ||
14b57c7c AM |
7070 | {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, |
7071 | {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, | |
7072 | {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, | |
7073 | {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, | |
7074 | {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, | |
7075 | {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, | |
7076 | {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, | |
7077 | {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, | |
7078 | {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, | |
7079 | {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, | |
7080 | {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, | |
7081 | {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, | |
7082 | {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, | |
7083 | {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, | |
7084 | {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, | |
7085 | {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, | |
7086 | {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, | |
7087 | {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, | |
7088 | {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, | |
7089 | {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, | |
7090 | {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, | |
7091 | {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, | |
7092 | {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, | |
7093 | {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, | |
7094 | {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, | |
7095 | {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, | |
7096 | {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, | |
7097 | {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, | |
7098 | {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, | |
7099 | {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, | |
7100 | {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, | |
7101 | {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, | |
7102 | {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, | |
7103 | {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, | |
7104 | {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, | |
7105 | {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, | |
7106 | ||
ac8f0f72 | 7107 | {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}}, |
14b57c7c | 7108 | |
62adc510 | 7109 | {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
14b57c7c AM |
7110 | {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
7111 | ||
7112 | {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
7113 | {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
7114 | ||
7115 | {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7116 | {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7117 | ||
94ba9882 AM |
7118 | {"stxvpx", X(31,461), XX1_MASK, POWER10, 0, {XTP, RA0, RB}}, |
7119 | ||
14b57c7c | 7120 | {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, |
c03dc33b | 7121 | {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}}, |
14b57c7c AM |
7122 | |
7123 | {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, | |
7124 | ||
7125 | {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, | |
7126 | {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, | |
7127 | {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, | |
7128 | {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, | |
7129 | {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, | |
7130 | {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, | |
7131 | {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, | |
7132 | {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, | |
7133 | {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, | |
7134 | {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, | |
7135 | {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, | |
7136 | {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, | |
7137 | {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, | |
7138 | {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, | |
7139 | {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, | |
7140 | {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, | |
7141 | {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, | |
7142 | {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, | |
7143 | {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, | |
7144 | {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, | |
7145 | {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, | |
7146 | {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, | |
7147 | {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, | |
7148 | {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, | |
7149 | {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, | |
7150 | {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, | |
7151 | {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, | |
7152 | {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, | |
7153 | {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, | |
7154 | {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, | |
7155 | {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, | |
7156 | {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, | |
7157 | {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, | |
7158 | {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, | |
7159 | {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, | |
7160 | {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, | |
7161 | {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, | |
7162 | {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, | |
7163 | {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, | |
7164 | {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, | |
7165 | {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, | |
7166 | {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, | |
7167 | {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, | |
7168 | {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, | |
7169 | {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, | |
7170 | {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, | |
7171 | {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, | |
7172 | {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
7173 | {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
7174 | {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
7175 | {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
7176 | {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, | |
7177 | {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, | |
7178 | {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, | |
7179 | {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, | |
7180 | {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, | |
7181 | {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, | |
7182 | {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, | |
7183 | {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, | |
7184 | {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, | |
7185 | {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, | |
7186 | {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, | |
7187 | {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, | |
7188 | {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, | |
7189 | {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, | |
7190 | {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, | |
7191 | {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, | |
7192 | {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, | |
7193 | {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, | |
7194 | {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, | |
7195 | {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, | |
7196 | {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, | |
7197 | {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, | |
7198 | {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, | |
7199 | {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, | |
7200 | {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, | |
7201 | {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, | |
7202 | {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, | |
7203 | {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, | |
7204 | {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, | |
7205 | {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, | |
7206 | {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, | |
7207 | {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, | |
7208 | {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, | |
7209 | {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, | |
7210 | {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, | |
7211 | {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, | |
7212 | {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, | |
4b94dd2d AM |
7213 | {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, |
7214 | {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, | |
14b57c7c AM |
7215 | {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, |
7216 | {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, | |
4b94dd2d AM |
7217 | {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
7218 | {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, | |
14b57c7c AM |
7219 | {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
7220 | {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, | |
7221 | {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
7222 | {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
7223 | {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
bb71536f AM |
7224 | {"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}}, |
7225 | {"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}}, | |
7226 | {"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}}, | |
7227 | {"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}}, | |
7228 | {"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}}, | |
7229 | {"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}}, | |
14b57c7c AM |
7230 | {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, |
7231 | {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, | |
7232 | {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, | |
7233 | {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, | |
7234 | {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, | |
7235 | {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, | |
7236 | {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, | |
7237 | {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, | |
fa758a70 AC |
7238 | {"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, 0, {SPRGQR, RS}}, |
7239 | {"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, 0, {RS}}, | |
7240 | {"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, 0, {RS}}, | |
7241 | {"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, 0, {RS}}, | |
7242 | {"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, 0, {RS}}, | |
14b57c7c AM |
7243 | {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, |
7244 | {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, | |
7245 | {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, | |
7246 | {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, | |
7247 | {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, | |
7248 | {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, | |
7249 | {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, | |
7250 | {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, | |
7251 | {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, | |
7252 | {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, | |
7253 | {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, | |
7254 | {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, | |
7255 | {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, | |
7256 | {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, | |
7257 | {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, | |
7258 | {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, | |
7259 | {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, | |
7260 | {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, | |
7261 | {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, | |
7262 | {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, | |
7263 | {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, | |
7264 | {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, | |
7265 | {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, | |
7266 | {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, | |
7267 | {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, | |
7268 | {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, | |
7269 | {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, | |
7270 | {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, | |
7271 | {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, | |
7272 | {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, | |
7273 | {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, | |
7274 | {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, | |
7275 | {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, | |
7276 | {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, | |
7277 | {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, | |
7278 | {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, | |
7279 | {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, | |
7280 | {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, | |
7281 | {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, | |
7282 | {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, | |
fa758a70 AC |
7283 | {"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, 0, {RS}}, |
7284 | {"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, 0, {RS}}, | |
14b57c7c | 7285 | {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, |
fa758a70 AC |
7286 | {"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, 0, {RS}}, |
7287 | {"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, 0, {RS}}, | |
7288 | {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, | |
14b57c7c AM |
7289 | {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, |
7290 | {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, | |
fa758a70 | 7291 | {"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, 0, {RS}}, |
14b57c7c AM |
7292 | {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, |
7293 | {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, | |
7294 | {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, | |
7295 | {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, | |
7296 | {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, | |
7297 | {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, | |
7298 | {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, | |
7299 | {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, | |
7300 | {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, | |
7301 | {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, | |
7302 | {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, | |
7303 | {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, | |
7304 | {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, | |
7305 | {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, | |
7306 | ||
7307 | {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, | |
7308 | ||
7309 | {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, | |
7310 | {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
7311 | ||
4f3e9537 PB |
7312 | {"setnbcr", X(31,480), XRB_MASK, POWER10, 0, {RT, BI}}, |
7313 | ||
14b57c7c AM |
7314 | {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, |
7315 | ||
62adc510 | 7316 | {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}}, |
14b57c7c AM |
7317 | |
7318 | {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, | |
7319 | ||
7320 | {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, | |
7321 | ||
7322 | {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, | |
7323 | {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, | |
7324 | ||
7325 | {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
7326 | {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
7327 | ||
7328 | {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7329 | {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7330 | ||
7331 | {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, | |
7332 | ||
7333 | {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}}, | |
4bc0608a | 7334 | {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, |
1cb0a767 | 7335 | |
14b57c7c | 7336 | {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, |
1cb0a767 | 7337 | |
14b57c7c | 7338 | {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
066be9f7 | 7339 | |
14b57c7c | 7340 | {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, |
1cb0a767 | 7341 | |
14b57c7c | 7342 | {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, |
252b5132 | 7343 | |
dfdaec14 | 7344 | {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 7345 | {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 7346 | |
14b57c7c | 7347 | {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}}, |
252b5132 | 7348 | |
14b57c7c AM |
7349 | {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, |
7350 | {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7351 | |
14b57c7c AM |
7352 | {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7353 | {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7354 | {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
7355 | {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7356 | {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7357 | {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
43e65147 | 7358 | |
14b57c7c AM |
7359 | {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7360 | {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7361 | {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7362 | {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7363 | |
14b57c7c | 7364 | {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
c0637f3a | 7365 | |
14b57c7c | 7366 | {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, |
418c1742 | 7367 | |
14b57c7c | 7368 | {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, |
418c1742 | 7369 | |
14b57c7c AM |
7370 | {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, |
7371 | {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7372 | |
14b57c7c AM |
7373 | {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, |
7374 | {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7375 | |
14b57c7c | 7376 | {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
702f0fb4 | 7377 | |
14b57c7c AM |
7378 | {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
7379 | {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
7380 | {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
7381 | {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
252b5132 | 7382 | |
14b57c7c AM |
7383 | {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7384 | {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
23976049 | 7385 | |
14b57c7c AM |
7386 | {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
7387 | {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, | |
a680de9a | 7388 | |
14b57c7c AM |
7389 | {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
7390 | {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
f509565f | 7391 | |
14b57c7c AM |
7392 | {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7393 | {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7394 | |
dfdaec14 | 7395 | {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 7396 | {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 7397 | |
ac8f0f72 | 7398 | {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7399 | |
14b57c7c | 7400 | {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, |
418c1742 | 7401 | |
14b57c7c AM |
7402 | {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, |
7403 | {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7404 | |
14b57c7c AM |
7405 | {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
7406 | {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
7407 | {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7408 | {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
252b5132 | 7409 | |
14b57c7c | 7410 | {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, |
252b5132 | 7411 | |
14b57c7c | 7412 | {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 7413 | |
14b57c7c AM |
7414 | {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
7415 | {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, | |
a680de9a | 7416 | |
ec40e91c AM |
7417 | {"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}}, |
7418 | ||
14b57c7c | 7419 | {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, |
a680de9a | 7420 | |
dfdaec14 | 7421 | {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 7422 | {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 7423 | |
ac8f0f72 | 7424 | {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7425 | |
14b57c7c | 7426 | {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
a680de9a | 7427 | |
14b57c7c | 7428 | {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7429 | |
14b57c7c | 7430 | {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
066be9f7 | 7431 | |
14b57c7c | 7432 | {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, |
252b5132 | 7433 | |
14b57c7c AM |
7434 | {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, |
7435 | {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, | |
252b5132 | 7436 | |
dc302c00 | 7437 | {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, |
e01d869a | 7438 | {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, |
14b57c7c | 7439 | {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, |
3d205eb4 PB |
7440 | {"phwsync", XSYNCLS(31,598,4,0), 0xffffffff, POWER10, 0, {0}}, |
7441 | {"plwsync", XSYNCLS(31,598,5,0), 0xffffffff, POWER10, 0, {0}}, | |
7442 | {"stncisync", XSYNCLS(31,598,1,1), 0xffffffff, POWER10, 0, {0}}, | |
7443 | {"stcisync", XSYNCLS(31,598,0,2), 0xffffffff, POWER10, 0, {0}}, | |
7444 | {"stsync", XSYNCLS(31,598,0,3), 0xffffffff, POWER10, 0, {0}}, | |
7445 | {"sync", X(31,598), XSYNCLS_MASK, POWER10, BOOKE|PPC476, {LS3, SC2}}, | |
fd486b63 | 7446 | {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, |
3d205eb4 | 7447 | {"sync", X(31,598), XSYNC_MASK, PPCCOM, POWER10|BOOKE|PPC476, {LS}}, |
14b57c7c AM |
7448 | {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, |
7449 | {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, | |
7450 | {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, | |
7451 | {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}}, | |
418c1742 | 7452 | |
14b57c7c | 7453 | {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
23976049 | 7454 | |
066be9f7 | 7455 | {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, |
14b57c7c | 7456 | {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, |
252b5132 | 7457 | |
14b57c7c | 7458 | {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, |
19a6653c | 7459 | |
ac8f0f72 | 7460 | {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7461 | |
14b57c7c | 7462 | {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
a680de9a | 7463 | |
14b57c7c | 7464 | {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7465 | |
14b57c7c AM |
7466 | {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, |
7467 | {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, | |
252b5132 | 7468 | |
14b57c7c AM |
7469 | {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7470 | {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7471 | |
14b57c7c | 7472 | {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, |
252b5132 | 7473 | |
14b57c7c | 7474 | {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, |
252b5132 | 7475 | |
14b57c7c | 7476 | {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 7477 | |
dfdaec14 | 7478 | {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 7479 | {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 7480 | |
14b57c7c AM |
7481 | {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, |
7482 | {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
23976049 | 7483 | |
14b57c7c | 7484 | {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
c0637f3a | 7485 | |
14b57c7c | 7486 | {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, |
5817ffd1 | 7487 | |
14b57c7c AM |
7488 | {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7489 | {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7490 | {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7491 | {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7492 | |
14b57c7c AM |
7493 | {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7494 | {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7495 | {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7496 | {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7497 | |
14b57c7c | 7498 | {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, |
418c1742 | 7499 | |
14b57c7c | 7500 | {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, |
252b5132 | 7501 | |
14b57c7c AM |
7502 | {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, |
7503 | {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
418c1742 | 7504 | |
14b57c7c AM |
7505 | {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
7506 | {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
252b5132 | 7507 | |
14b57c7c | 7508 | {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
ede602d7 | 7509 | |
14b57c7c AM |
7510 | {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7511 | {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7512 | |
14b57c7c AM |
7513 | {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7514 | {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7515 | |
dfdaec14 | 7516 | {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 7517 | {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 7518 | |
ac8f0f72 | 7519 | {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7520 | |
14b57c7c AM |
7521 | {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, |
7522 | {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7523 | |
14b57c7c AM |
7524 | {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, |
7525 | {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, | |
5817ffd1 | 7526 | |
14b57c7c | 7527 | {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
066be9f7 | 7528 | |
14b57c7c | 7529 | {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 7530 | |
14b57c7c AM |
7531 | {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, |
7532 | {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 7533 | |
dfdaec14 | 7534 | {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 7535 | {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 7536 | |
ac8f0f72 | 7537 | {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7538 | |
14b57c7c | 7539 | {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
a680de9a | 7540 | |
14b57c7c | 7541 | {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7542 | |
14b57c7c | 7543 | {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
066be9f7 | 7544 | |
14b57c7c | 7545 | {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, |
5817ffd1 | 7546 | |
14b57c7c AM |
7547 | {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7548 | {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7549 | {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7550 | {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 7551 | |
14b57c7c AM |
7552 | {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7553 | {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7554 | {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7555 | {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
fdd12ef3 | 7556 | |
14b57c7c AM |
7557 | {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, |
7558 | {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, | |
252b5132 | 7559 | |
14b57c7c | 7560 | {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
066be9f7 | 7561 | |
14b57c7c | 7562 | {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
252b5132 | 7563 | |
14b57c7c AM |
7564 | {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7565 | {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
418c1742 | 7566 | |
14b57c7c AM |
7567 | {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7568 | {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7569 | |
066be9f7 | 7570 | {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, |
14b57c7c | 7571 | {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, |
252b5132 | 7572 | |
14b57c7c | 7573 | {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, |
19a6653c | 7574 | |
ac8f0f72 | 7575 | {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7576 | |
14b57c7c | 7577 | {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
a680de9a | 7578 | |
14b57c7c | 7579 | {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7580 | |
14b57c7c AM |
7581 | {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7582 | {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7583 | {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7584 | {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 7585 | |
14b57c7c AM |
7586 | {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
7587 | {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
252b5132 | 7588 | |
14b57c7c AM |
7589 | {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7590 | {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7591 | {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7592 | {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 7593 | |
14b57c7c AM |
7594 | {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7595 | {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7596 | {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7597 | {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
702f0fb4 | 7598 | |
14b57c7c AM |
7599 | {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
7600 | {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}}, | |
7601 | {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, | |
5817ffd1 | 7602 | |
14b57c7c | 7603 | {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, |
a680de9a | 7604 | |
14b57c7c AM |
7605 | {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
7606 | {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, | |
252b5132 | 7607 | |
14b57c7c | 7608 | {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 7609 | |
14b57c7c AM |
7610 | {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, |
7611 | {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 7612 | |
ac8f0f72 | 7613 | {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}}, |
a680de9a | 7614 | |
fd486b63 | 7615 | {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, |
a680de9a | 7616 | |
ac8f0f72 | 7617 | {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}}, |
14b57c7c AM |
7618 | {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, |
7619 | {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
ede602d7 | 7620 | |
14b57c7c AM |
7621 | {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7622 | {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7623 | |
14b57c7c AM |
7624 | {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7625 | {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7626 | {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7627 | {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7628 | |
14b57c7c AM |
7629 | {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, |
7630 | {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, | |
a680de9a | 7631 | |
14b57c7c AM |
7632 | {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
7633 | {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
066be9f7 | 7634 | |
14b57c7c | 7635 | {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
5817ffd1 | 7636 | |
14b57c7c | 7637 | {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
252b5132 | 7638 | |
14b57c7c | 7639 | {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 7640 | |
14b57c7c | 7641 | {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, |
252b5132 | 7642 | |
73f07bff | 7643 | {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, |
14b57c7c | 7644 | {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
418c1742 | 7645 | |
14b57c7c AM |
7646 | {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
7647 | {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
7648 | {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
7649 | {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
fdd12ef3 | 7650 | |
14b57c7c AM |
7651 | {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
7652 | {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
252b5132 | 7653 | |
74081948 | 7654 | {"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, |
14b57c7c | 7655 | {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, |
19a6653c | 7656 | |
ac8f0f72 AM |
7657 | {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, |
7658 | {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}}, | |
14b57c7c | 7659 | {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, |
252b5132 | 7660 | |
14b57c7c AM |
7661 | {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
7662 | {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
a680de9a | 7663 | |
14b57c7c | 7664 | {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
5817ffd1 | 7665 | |
14b57c7c | 7666 | {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, |
252b5132 | 7667 | |
14b57c7c | 7668 | {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, |
e0d602ec | 7669 | |
14b57c7c | 7670 | {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 7671 | |
14b57c7c | 7672 | {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, |
252b5132 | 7673 | |
14b57c7c | 7674 | {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
fdd12ef3 | 7675 | |
14b57c7c AM |
7676 | {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, |
7677 | {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, | |
7678 | {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, | |
7679 | {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, | |
702f0fb4 | 7680 | |
14b57c7c AM |
7681 | {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, |
7682 | {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, | |
e0c21649 | 7683 | |
ac8f0f72 | 7684 | {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7685 | |
fd486b63 | 7686 | {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, |
a680de9a | 7687 | |
14b57c7c AM |
7688 | {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7689 | {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7690 | |
14b57c7c | 7691 | {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
a680de9a | 7692 | {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, |
9b4e5766 | 7693 | |
14b57c7c | 7694 | {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
5817ffd1 | 7695 | |
14b57c7c | 7696 | {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, |
e0d602ec | 7697 | |
1224c05d PB |
7698 | {"slbiag", X(31,850), XRLARB_MASK, POWER10, 0, {RS, A_L}}, |
7699 | {"slbiag", X(31,850), XRARB_MASK, POWER9, POWER10, {RS}}, | |
7700 | ||
14b57c7c | 7701 | {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
a680de9a | 7702 | {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
252b5132 | 7703 | |
14b57c7c | 7704 | {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
418c1742 | 7705 | |
9fe54b1c | 7706 | {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, |
14b57c7c AM |
7707 | {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, |
7708 | {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, | |
7709 | {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, | |
418c1742 | 7710 | |
14b57c7c | 7711 | {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, |
418c1742 | 7712 | |
ac8f0f72 | 7713 | {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7714 | |
14b57c7c AM |
7715 | {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
7716 | {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, | |
702f0fb4 | 7717 | |
14b57c7c AM |
7718 | {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7719 | {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7720 | |
14b57c7c | 7721 | {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 7722 | |
14b57c7c | 7723 | {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
5817ffd1 | 7724 | |
14b57c7c | 7725 | {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, |
a680de9a | 7726 | |
14b57c7c | 7727 | {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 7728 | |
14b57c7c | 7729 | {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}}, |
a680de9a | 7730 | |
14b57c7c | 7731 | {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, |
066be9f7 | 7732 | |
14b57c7c AM |
7733 | {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, |
7734 | {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, | |
a680de9a | 7735 | |
afef4fe9 PB |
7736 | {"paste.", XRC(31,902,1), XLRT_MASK, POWER10, 0, {RA0, RB, L1OPT}}, |
7737 | {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, POWER10, {RA0, RB}}, | |
a680de9a | 7738 | |
14b57c7c AM |
7739 | {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, |
7740 | {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7741 | |
14b57c7c AM |
7742 | {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
7743 | {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7744 | {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7745 | {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 7746 | |
14b57c7c AM |
7747 | {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
7748 | {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
066be9f7 | 7749 | |
14b57c7c | 7750 | {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
5817ffd1 | 7751 | |
14b57c7c AM |
7752 | {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, |
7753 | {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, | |
252b5132 | 7754 | |
14b57c7c | 7755 | {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
a680de9a | 7756 | {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
702f0fb4 | 7757 | |
14b57c7c | 7758 | {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
f5c120c5 | 7759 | |
14b57c7c | 7760 | {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, |
252b5132 | 7761 | |
73f07bff | 7762 | {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, |
14b57c7c | 7763 | {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, |
6ba045b1 | 7764 | |
14b57c7c AM |
7765 | {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7766 | {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
702f0fb4 | 7767 | |
14b57c7c AM |
7768 | {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7769 | {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7770 | |
14b57c7c AM |
7771 | {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, |
7772 | {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
7773 | {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
7774 | {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
702f0fb4 | 7775 | |
74081948 | 7776 | {"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, |
14b57c7c | 7777 | {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, |
19a6653c | 7778 | |
ac8f0f72 | 7779 | {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7780 | |
14b57c7c | 7781 | {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, |
a5721ba2 AM |
7782 | {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}}, |
7783 | {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, | |
85d4ac0b | 7784 | |
14b57c7c | 7785 | {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6ba045b1 | 7786 | |
14b57c7c AM |
7787 | {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
7788 | {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7789 | {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7790 | {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 7791 | |
14b57c7c AM |
7792 | {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
7793 | {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
a680de9a | 7794 | |
14b57c7c | 7795 | {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
5817ffd1 | 7796 | |
e0d602ec BE |
7797 | {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, |
7798 | {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, | |
14b57c7c | 7799 | {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, |
702f0fb4 | 7800 | |
14b57c7c | 7801 | {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
252b5132 | 7802 | |
14b57c7c AM |
7803 | {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, |
7804 | {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, | |
51b5d4a8 | 7805 | |
14b57c7c | 7806 | {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, |
252b5132 | 7807 | |
14b57c7c AM |
7808 | {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, |
7809 | {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 7810 | |
14b57c7c AM |
7811 | {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, |
7812 | {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, | |
252b5132 | 7813 | |
ac8f0f72 | 7814 | {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7815 | |
62adc510 | 7816 | {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
14b57c7c | 7817 | {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
43e65147 | 7818 | |
14b57c7c AM |
7819 | {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
7820 | {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 7821 | |
14b57c7c AM |
7822 | {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
7823 | {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
252b5132 | 7824 | |
14b57c7c | 7825 | {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
a680de9a | 7826 | {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, |
9b4e5766 | 7827 | |
9fe54b1c | 7828 | {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, |
14b57c7c AM |
7829 | {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, |
7830 | {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, | |
7831 | {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, | |
418c1742 | 7832 | |
14b57c7c | 7833 | {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, |
c4e676f1 | 7834 | |
14b57c7c | 7835 | {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
252b5132 | 7836 | |
14b57c7c | 7837 | {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, |
252b5132 | 7838 | |
14b57c7c | 7839 | {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, |
702f0fb4 | 7840 | |
14b57c7c AM |
7841 | {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
7842 | {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, | |
252b5132 | 7843 | |
14b57c7c | 7844 | {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
19a6653c | 7845 | |
ac8f0f72 | 7846 | {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7847 | |
14b57c7c | 7848 | {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, |
252b5132 | 7849 | |
14b57c7c AM |
7850 | {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
7851 | {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, | |
252b5132 | 7852 | |
14b57c7c AM |
7853 | {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
7854 | {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 7855 | |
14b57c7c AM |
7856 | {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
7857 | {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
418c1742 | 7858 | |
14b57c7c | 7859 | {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
a680de9a | 7860 | |
14b57c7c | 7861 | {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
702f0fb4 | 7862 | |
14b57c7c | 7863 | {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, |
252b5132 | 7864 | |
14b57c7c | 7865 | {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
418c1742 | 7866 | |
14b57c7c AM |
7867 | {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, |
7868 | {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, | |
786e2c0f | 7869 | |
14b57c7c | 7870 | {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
ede602d7 | 7871 | |
14b57c7c | 7872 | {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, |
252b5132 | 7873 | |
14b57c7c AM |
7874 | {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}}, |
7875 | {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}}, | |
7876 | {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}}, | |
252b5132 | 7877 | |
14b57c7c AM |
7878 | {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
7879 | {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, | |
7880 | {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, | |
252b5132 | 7881 | |
14b57c7c AM |
7882 | {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}}, |
7883 | {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}}, | |
7884 | {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}}, | |
7885 | {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}}, | |
252b5132 | 7886 | |
14b57c7c AM |
7887 | {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, |
7888 | {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 7889 | |
14b57c7c AM |
7890 | {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, |
7891 | {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 7892 | |
14b57c7c | 7893 | {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 7894 | |
14b57c7c | 7895 | {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 7896 | |
14b57c7c AM |
7897 | {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
7898 | {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 7899 | |
14b57c7c AM |
7900 | {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, |
7901 | {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 7902 | |
14b57c7c | 7903 | {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
252b5132 | 7904 | |
14b57c7c | 7905 | {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
252b5132 | 7906 | |
14b57c7c | 7907 | {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 7908 | |
14b57c7c | 7909 | {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 7910 | |
14b57c7c | 7911 | {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 7912 | |
14b57c7c | 7913 | {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 7914 | |
14b57c7c | 7915 | {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
252b5132 | 7916 | |
14b57c7c | 7917 | {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
252b5132 | 7918 | |
14b57c7c AM |
7919 | {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, |
7920 | {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 7921 | |
14b57c7c AM |
7922 | {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
7923 | {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 7924 | |
14b57c7c | 7925 | {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
252b5132 | 7926 | |
14b57c7c | 7927 | {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
252b5132 | 7928 | |
14b57c7c | 7929 | {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
252b5132 | 7930 | |
14b57c7c | 7931 | {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
252b5132 | 7932 | |
14b57c7c | 7933 | {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
adadcc0c | 7934 | |
14b57c7c | 7935 | {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
252b5132 | 7936 | |
14b57c7c | 7937 | {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
c3d65c1c | 7938 | |
14b57c7c | 7939 | {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
252b5132 | 7940 | |
73f07bff | 7941 | {"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, |
14b57c7c AM |
7942 | {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
7943 | {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, | |
418c1742 | 7944 | |
14b57c7c AM |
7945 | {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, |
7946 | {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, | |
73f07bff | 7947 | {"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, |
14b57c7c AM |
7948 | {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
7949 | {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, | |
802a735e | 7950 | |
14b57c7c AM |
7951 | {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, |
7952 | {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, | |
7953 | {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, | |
702f0fb4 | 7954 | |
14b57c7c AM |
7955 | {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
7956 | {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7957 | |
14b57c7c AM |
7958 | {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, |
7959 | {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, | |
252b5132 | 7960 | |
aa3c112f AM |
7961 | {"xvi8ger4pp", XX3(59,2), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7962 | {"xvi8ger4", XX3(59,3), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7963 | ||
14b57c7c AM |
7964 | {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7965 | {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7966 | |
14b57c7c AM |
7967 | {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7968 | {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7969 | |
14b57c7c AM |
7970 | {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7971 | {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7972 | |
14b57c7c AM |
7973 | {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, |
7974 | {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, | |
252b5132 | 7975 | |
14b57c7c AM |
7976 | {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7977 | {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7978 | {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7979 | {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
1ed8e1e4 | 7980 | |
14b57c7c AM |
7981 | {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
7982 | {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, | |
252b5132 | 7983 | |
14b57c7c AM |
7984 | {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7985 | {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7986 | {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7987 | {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
252b5132 | 7988 | |
14b57c7c AM |
7989 | {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7990 | {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7991 | |
14b57c7c AM |
7992 | {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7993 | {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7994 | |
14b57c7c AM |
7995 | {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7996 | {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 7997 | |
14b57c7c AM |
7998 | {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7999 | {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 8000 | |
14b57c7c AM |
8001 | {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
8002 | {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
702f0fb4 | 8003 | |
14b57c7c AM |
8004 | {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, |
8005 | {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, | |
702f0fb4 | 8006 | |
14b57c7c AM |
8007 | {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
8008 | {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, | |
702f0fb4 | 8009 | |
14b57c7c AM |
8010 | {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, |
8011 | {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, | |
702f0fb4 | 8012 | |
aa3c112f AM |
8013 | {"xvf16ger2pp", XX3(59,18), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8014 | {"xvf16ger2", XX3(59,19), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8015 | ||
14b57c7c AM |
8016 | {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
8017 | {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, | |
702f0fb4 | 8018 | |
14b57c7c AM |
8019 | {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, |
8020 | {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
702f0fb4 | 8021 | |
aa3c112f AM |
8022 | {"xvf32gerpp", XX3(59,26), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8023 | {"xvf32ger", XX3(59,27), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8024 | ||
14b57c7c | 8025 | {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
702f0fb4 | 8026 | |
aa3c112f AM |
8027 | {"xvi4ger8pp", XX3(59,34), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8028 | {"xvi4ger8", XX3(59,35), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8029 | ||
14b57c7c | 8030 | {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
aa3c112f AM |
8031 | |
8032 | {"xvi16ger2spp", XX3(59,42), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8033 | {"xvi16ger2s", XX3(59,43), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8034 | ||
14b57c7c | 8035 | {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, |
aa3c112f AM |
8036 | |
8037 | {"xvbf16ger2pp",XX3(59,50), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8038 | {"xvbf16ger2", XX3(59,51), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8039 | ||
14b57c7c AM |
8040 | {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, |
8041 | ||
8042 | {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
8043 | {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
8044 | ||
aa3c112f AM |
8045 | {"xvf64gerpp", XX3(59,58), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, |
8046 | {"xvf64ger", XX3(59,59), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, | |
8047 | ||
14b57c7c AM |
8048 | {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
8049 | {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
8050 | ||
8051 | {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
8052 | {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
8053 | ||
8054 | {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, | |
8055 | {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, | |
8056 | ||
aa3c112f AM |
8057 | {"xvi16ger2", XX3(59,75), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8058 | ||
8059 | {"xvf16ger2np", XX3(59,82), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8060 | ||
14b57c7c AM |
8061 | {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
8062 | {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
8063 | ||
aa3c112f AM |
8064 | {"xvf32gernp", XX3(59,90), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8065 | ||
8066 | {"xvi8ger4spp", XX3(59,99), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8067 | ||
8068 | {"xvi16ger2pp", XX3(59,107), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8069 | ||
8070 | {"xvbf16ger2np",XX3(59,114), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8071 | ||
8072 | {"xvf64gernp", XX3(59,122), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, | |
8073 | ||
14b57c7c AM |
8074 | {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
8075 | {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
8076 | ||
8077 | {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
8078 | {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
8079 | ||
aa3c112f AM |
8080 | {"xvf16ger2pn", XX3(59,146), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8081 | ||
8082 | {"xvf32gerpn", XX3(59,154), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8083 | ||
14b57c7c AM |
8084 | {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
8085 | ||
8086 | {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, | |
8087 | {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, | |
8088 | ||
aa3c112f AM |
8089 | {"xvbf16ger2pn",XX3(59,178), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8090 | ||
8091 | {"xvf64gerpn", XX3(59,186), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, | |
8092 | ||
14b57c7c AM |
8093 | {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
8094 | {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
8095 | ||
8096 | {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8097 | {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8098 | ||
8099 | {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, | |
8100 | {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, | |
8101 | ||
aa3c112f AM |
8102 | {"xvf16ger2nn", XX3(59,210), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8103 | ||
14b57c7c AM |
8104 | {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8105 | {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
8106 | ||
8107 | {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
8108 | {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
8109 | ||
aa3c112f AM |
8110 | {"xvf32gernn", XX3(59,218), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
8111 | ||
8112 | {"xvbf16ger2nn",XX3(59,242), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
8113 | ||
14b57c7c AM |
8114 | {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8115 | {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
8116 | ||
aa3c112f AM |
8117 | {"xvf64gernn", XX3(59,250), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, |
8118 | ||
14b57c7c AM |
8119 | {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
8120 | {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8121 | {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, | |
8122 | {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8123 | {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8124 | {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8125 | {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, | |
8126 | {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8127 | {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
98553ad3 | 8128 | {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XAB6, DMEX}}, |
14b57c7c | 8129 | {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
98553ad3 | 8130 | {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
8131 | {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
8132 | {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, | |
8133 | {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8134 | {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8135 | {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8136 | {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8137 | {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8138 | {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8139 | {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8140 | {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8141 | {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8142 | {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8143 | {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8144 | {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
8145 | {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8146 | {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8147 | {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8148 | {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8149 | {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8150 | {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8151 | {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
8152 | {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8153 | {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8154 | {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8155 | {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8156 | {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8157 | {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8158 | {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8159 | {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
8160 | {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8161 | {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8162 | {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8163 | {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8164 | {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, | |
8165 | {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8166 | {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
8167 | {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8168 | {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8169 | {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8170 | {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8171 | {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8172 | {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8173 | {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8174 | {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8175 | {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8176 | {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8177 | {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8178 | {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8179 | {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8180 | {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8181 | {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8182 | {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8183 | {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8184 | {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, | |
8185 | {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, | |
8186 | {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8187 | {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8188 | {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8189 | {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8190 | {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
8191 | {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8192 | {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8193 | {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8194 | {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, | |
6edbfd3b | 8195 | {"lxvkq", XVA(60,360,31), XVA_MASK&~1, POWER10, PPCVLE, {XT6, UIM5}}, |
14b57c7c AM |
8196 | {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, |
8197 | {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8198 | {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8199 | {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
8200 | {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8201 | {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8202 | {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8203 | {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8204 | {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8205 | {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8206 | {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8207 | {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8208 | {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8209 | {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8210 | {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8211 | {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8212 | {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8213 | {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8214 | {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8215 | {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8216 | {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8217 | {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8218 | {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8219 | {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8220 | {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8221 | {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
8222 | {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8223 | {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8224 | {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8225 | {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8226 | {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8227 | {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
8228 | {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8229 | {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8230 | {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8231 | {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8232 | {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8233 | {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8234 | {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8235 | {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8236 | {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8237 | {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8238 | {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8239 | {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8240 | {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8241 | {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, | |
8242 | {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8243 | {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8244 | {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8245 | {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8246 | {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8247 | {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8248 | {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8249 | {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8250 | {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8251 | {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8252 | {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8253 | {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8254 | {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8255 | {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8256 | {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8257 | {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, | |
8258 | {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, | |
8259 | {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8260 | {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8261 | {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8262 | {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8263 | {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8264 | {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8265 | {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8266 | {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, | |
8267 | {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8268 | {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8269 | {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8270 | {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8271 | {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8272 | {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8273 | {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8274 | {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8275 | {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8276 | {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8277 | {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8278 | {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
98553ad3 | 8279 | {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
8280 | {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
8281 | {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8282 | {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8283 | {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8284 | {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, | |
8285 | {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8286 | {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8287 | {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8288 | {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8289 | {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8290 | {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8291 | {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8292 | {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
d7e97a76 AM |
8293 | {"xxgenpcvbm", X(60,916), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, |
8294 | {"xxgenpcvhm", X(60,917), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, | |
14b57c7c AM |
8295 | {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, |
8296 | {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8297 | {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8298 | {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8299 | {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
d7e97a76 AM |
8300 | {"xxgenpcvwm", X(60,948), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, |
8301 | {"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, | |
14b57c7c AM |
8302 | {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
8303 | {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
5d57bc3f | 8304 | {"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {OBF, XB6}}, |
14b57c7c AM |
8305 | {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
8306 | {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8307 | {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8308 | {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
aa3c112f AM |
8309 | {"xvcvbf16sp", XX2VA(60,475,16),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}}, |
8310 | {"xvcvspbf16", XX2VA(60,475,17),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}}, | |
14b57c7c AM |
8311 | {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
8312 | {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8313 | {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8314 | {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
98553ad3 | 8315 | {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
8316 | {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
8317 | {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8318 | {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8319 | {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8320 | {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, | |
8321 | {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8322 | {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8323 | {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8324 | {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8325 | ||
8326 | {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, | |
8327 | {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, | |
8328 | ||
8329 | {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, | |
8330 | {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, | |
8331 | {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, | |
8332 | {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, | |
73f07bff | 8333 | {"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, |
14b57c7c AM |
8334 | {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, |
8335 | {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, | |
8336 | ||
8337 | {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, | |
8338 | {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, | |
73f07bff | 8339 | {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, |
14b57c7c AM |
8340 | |
8341 | {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, | |
8342 | ||
73f07bff AM |
8343 | {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8344 | {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
14b57c7c | 8345 | |
73f07bff AM |
8346 | {"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, |
8347 | {"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, | |
14b57c7c AM |
8348 | |
8349 | {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
8350 | {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
8351 | ||
8352 | {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, | |
8353 | {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, | |
8354 | ||
8355 | {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, | |
8356 | {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, | |
8357 | ||
8358 | {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8359 | {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8360 | ||
8361 | {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8362 | {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8363 | {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8364 | {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8365 | ||
8366 | {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8367 | {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8368 | {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8369 | {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8370 | ||
8371 | {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8372 | {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8373 | {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8374 | {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8375 | ||
8376 | {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8377 | {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8378 | {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8379 | {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8380 | ||
8381 | {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8382 | {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8383 | {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8384 | {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8385 | ||
8386 | {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, | |
8387 | {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, | |
8388 | ||
8389 | {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8390 | {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8391 | ||
8392 | {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8393 | {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
8394 | {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8395 | {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
1ed8e1e4 | 8396 | |
14b57c7c AM |
8397 | {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
8398 | {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, | |
8399 | {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, | |
8400 | {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, | |
252b5132 | 8401 | |
14b57c7c AM |
8402 | {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
8403 | {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
8404 | {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8405 | {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
252b5132 | 8406 | |
14b57c7c AM |
8407 | {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8408 | {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8409 | {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8410 | {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8411 | |
14b57c7c AM |
8412 | {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8413 | {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8414 | {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8415 | {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8416 | |
14b57c7c AM |
8417 | {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8418 | {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8419 | {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8420 | {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8421 | |
14b57c7c AM |
8422 | {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8423 | {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8424 | {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8425 | {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8426 | |
14b57c7c | 8427 | {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, |
252b5132 | 8428 | |
73f07bff AM |
8429 | {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8430 | {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 8431 | |
73f07bff AM |
8432 | {"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, |
8433 | {"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, | |
702f0fb4 | 8434 | |
14b57c7c AM |
8435 | {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8436 | {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8437 | |
14b57c7c | 8438 | {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, |
a680de9a | 8439 | |
96a86c01 AM |
8440 | {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BTF}}, |
8441 | {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BTF}}, | |
252b5132 | 8442 | |
14b57c7c AM |
8443 | {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8444 | {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8445 | |
14b57c7c | 8446 | {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, |
252b5132 | 8447 | |
73f07bff AM |
8448 | {"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
8449 | {"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 8450 | |
73f07bff AM |
8451 | {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, |
8452 | {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, | |
702f0fb4 | 8453 | |
3b646889 AM |
8454 | {"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8455 | ||
96a86c01 AM |
8456 | {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BTF}}, |
8457 | {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BTF}}, | |
252b5132 | 8458 | |
14b57c7c AM |
8459 | {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8460 | {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8461 | |
73f07bff AM |
8462 | {"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
8463 | {"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 8464 | |
73f07bff AM |
8465 | {"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
8466 | {"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 8467 | |
14b57c7c | 8468 | {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
a680de9a | 8469 | |
14b57c7c | 8470 | {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, |
066be9f7 | 8471 | |
14b57c7c | 8472 | {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
702f0fb4 | 8473 | |
14b57c7c | 8474 | {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 8475 | |
14b57c7c AM |
8476 | {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, |
8477 | {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, | |
8478 | {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, | |
8479 | {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, | |
252b5132 | 8480 | |
14b57c7c AM |
8481 | {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8482 | {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8483 | |
14b57c7c AM |
8484 | {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
8485 | {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8486 | {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8487 | {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 8488 | |
14b57c7c | 8489 | {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, |
066be9f7 | 8490 | |
14b57c7c | 8491 | {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
a680de9a | 8492 | |
14b57c7c | 8493 | {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 8494 | |
14b57c7c | 8495 | {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, |
3b646889 AM |
8496 | |
8497 | {"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, | |
8498 | ||
14b57c7c | 8499 | {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, |
702f0fb4 | 8500 | |
73f07bff AM |
8501 | {"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
8502 | {"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 8503 | |
3b646889 AM |
8504 | {"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8505 | ||
73f07bff AM |
8506 | {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
8507 | {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, | |
702f0fb4 | 8508 | |
14b57c7c AM |
8509 | {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8510 | {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8511 | |
14b57c7c AM |
8512 | {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
8513 | {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, | |
702f0fb4 | 8514 | |
73f07bff AM |
8515 | {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, |
8516 | {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, | |
702f0fb4 | 8517 | |
14b57c7c AM |
8518 | {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
8519 | {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, | |
702f0fb4 | 8520 | |
14b57c7c AM |
8521 | {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8522 | {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8523 | |
14b57c7c AM |
8524 | {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8525 | {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 8526 | |
14b57c7c AM |
8527 | {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8528 | {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8529 | |
14b57c7c AM |
8530 | {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8531 | {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 8532 | |
14b57c7c AM |
8533 | {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8534 | {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8535 | |
14b57c7c AM |
8536 | {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8537 | {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 8538 | |
14b57c7c AM |
8539 | {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8540 | {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8541 | |
14b57c7c AM |
8542 | {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8543 | {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
ce7a772b | 8544 | |
73f07bff AM |
8545 | {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8546 | {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 8547 | |
14b57c7c AM |
8548 | {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8549 | {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8550 | |
73f07bff AM |
8551 | {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8552 | {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 8553 | |
14b57c7c AM |
8554 | {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8555 | {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8556 | |
14b57c7c AM |
8557 | {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, |
8558 | {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, | |
252b5132 | 8559 | |
6fd3a02d PB |
8560 | {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, |
8561 | {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, | |
8562 | {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, | |
8563 | {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, | |
8564 | {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, | |
8565 | {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, | |
8566 | ||
14b57c7c | 8567 | {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
702f0fb4 | 8568 | |
14b57c7c | 8569 | {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 8570 | |
14b57c7c AM |
8571 | {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, |
8572 | {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, | |
a680de9a | 8573 | |
3b646889 AM |
8574 | {"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8575 | ||
14b57c7c | 8576 | {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, |
702f0fb4 | 8577 | |
14b57c7c AM |
8578 | {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, |
8579 | {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, | |
8580 | {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, | |
8581 | {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, | |
252b5132 | 8582 | |
3b646889 AM |
8583 | {"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8584 | ||
73f07bff AM |
8585 | {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, |
8586 | {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, | |
702f0fb4 | 8587 | |
73f07bff AM |
8588 | {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
8589 | {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, | |
702f0fb4 | 8590 | |
14b57c7c AM |
8591 | {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8592 | {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8593 | {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8594 | {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8595 | {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8596 | {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8597 | {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
a680de9a | 8598 | |
14b57c7c AM |
8599 | {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
8600 | {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
8601 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
8602 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 8603 | |
14b57c7c AM |
8604 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
8605 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
8606 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
8607 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 8608 | |
73f07bff AM |
8609 | {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, |
8610 | {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, | |
702f0fb4 | 8611 | |
c7d7aea2 | 8612 | {"xscvqpuqz", XVA(63,836,0), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, |
14b57c7c AM |
8613 | {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8614 | {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
c7d7aea2 AM |
8615 | {"xscvuqqp", XVA(63,836,3), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, |
8616 | {"xscvqpsqz", XVA(63,836,8), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, | |
14b57c7c AM |
8617 | {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8618 | {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
c7d7aea2 | 8619 | {"xscvsqqp", XVA(63,836,11), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, |
14b57c7c AM |
8620 | {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8621 | {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8622 | {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8623 | {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8624 | {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
a680de9a | 8625 | |
14b57c7c | 8626 | {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
c0637f3a | 8627 | |
14b57c7c AM |
8628 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
8629 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
8630 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
8631 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 8632 | |
73f07bff AM |
8633 | {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, |
8634 | {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, | |
702f0fb4 | 8635 | |
14b57c7c | 8636 | {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
a680de9a | 8637 | |
14b57c7c AM |
8638 | {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8639 | {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 8640 | |
14b57c7c AM |
8641 | {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8642 | {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 8643 | |
14b57c7c | 8644 | {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
c0637f3a | 8645 | |
14b57c7c AM |
8646 | {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8647 | {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
c7d7aea2 AM |
8648 | |
8649 | {"dcffixqq", XVA(63,994,0), XVA_MASK, POWER10, PPCVLE, {FRTp, VB}}, | |
8650 | {"dctfixqq", XVA(63,994,1), XVA_MASK, POWER10, PPCVLE, {VD, FRBp}}, | |
252b5132 RH |
8651 | }; |
8652 | ||
2ceb7719 | 8653 | const unsigned int powerpc_num_opcodes = |
252b5132 RH |
8654 | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
8655 | \f | |
dd7efa79 PB |
8656 | /* The opcode table for 8-byte prefix instructions. |
8657 | ||
8658 | The format of this opcode table is the same as the main opcode table. */ | |
8659 | ||
8660 | const struct powerpc_opcode prefix_opcodes[] = { | |
7c1f4227 AM |
8661 | {"pnop", PMRR, PREFIX_MASK, POWER10, 0, {0}}, |
8662 | {"pli", PMLS|OP(14), P_DRAPCREL_MASK, POWER10, 0, {RT, SI34}}, | |
8663 | {"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL0}}, | |
8664 | {"psubi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, NSI34, PCREL0}}, | |
8665 | {"pla", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
6edbfd3b AM |
8666 | {"xxsplti32dx", P8RR|VSOP(32,0), P_VSI_MASK, POWER10, 0, {XTS, IX, IMM32}}, |
8667 | {"xxspltidp", P8RR|VSOP(32,2), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, | |
8668 | {"xxspltiw", P8RR|VSOP(32,3), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, | |
7c1f4227 | 8669 | {"plwz", PMLS|OP(32), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, |
6edbfd3b AM |
8670 | {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, |
8671 | {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, | |
8672 | {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, | |
8673 | {"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, | |
8674 | {"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}}, | |
ec40e91c | 8675 | {"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}}, |
7c1f4227 AM |
8676 | {"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, |
8677 | {"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
8678 | {"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
8679 | {"plhz", PMLS|OP(40), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
8680 | {"plwa", P8LS|OP(41), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
8681 | {"plxsd", P8LS|OP(42), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}}, | |
8682 | {"plha", PMLS|OP(42), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
8683 | {"plxssp", P8LS|OP(43), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}}, | |
8684 | {"psth", PMLS|OP(44), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
8685 | {"pstxsd", P8LS|OP(46), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}}, | |
8686 | {"pstxssp", P8LS|OP(47), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}}, | |
8687 | {"plfs", PMLS|OP(48), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}}, | |
8688 | {"plxv", P8LS|OP(50), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}}, | |
8689 | {"plfd", PMLS|OP(50), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}}, | |
8690 | {"pstfs", PMLS|OP(52), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}}, | |
8691 | {"pstxv", P8LS|OP(54), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}}, | |
8692 | {"pstfd", PMLS|OP(54), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}}, | |
8693 | {"plq", P8LS|OP(56), P_D_MASK, POWER10, 0, {RTQ, D34, PRAQ, PCREL}}, | |
8694 | {"pld", P8LS|OP(57), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
94ba9882 | 8695 | {"plxvp", P8LS|OP(58), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}}, |
aa3c112f AM |
8696 | {"pmxvi8ger4pp", PMMIRR|XX3(59,2), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, |
8697 | {"pmxvi8ger4", PMMIRR|XX3(59,3), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, | |
8698 | {"pmxvf16ger2pp", PMMIRR|XX3(59,18), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8699 | {"pmxvf16ger2", PMMIRR|XX3(59,19), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8700 | {"pmxvf32gerpp", PMMIRR|XX3(59,26), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8701 | {"pmxvf32ger", PMMIRR|XX3(59,27), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8702 | {"pmxvi4ger8pp", PMMIRR|XX3(59,34), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}}, | |
8703 | {"pmxvi4ger8", PMMIRR|XX3(59,35), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}}, | |
8704 | {"pmxvi16ger2spp",PMMIRR|XX3(59,42), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8705 | {"pmxvi16ger2s", PMMIRR|XX3(59,43), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8706 | {"pmxvbf16ger2pp",PMMIRR|XX3(59,50), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8707 | {"pmxvbf16ger2", PMMIRR|XX3(59,51), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8708 | {"pmxvf64gerpp", PMMIRR|XX3(59,58), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8709 | {"pmxvf64ger", PMMIRR|XX3(59,59), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8710 | {"pmxvi16ger2", PMMIRR|XX3(59,75), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8711 | {"pmxvf16ger2np", PMMIRR|XX3(59,82), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8712 | {"pmxvf32gernp", PMMIRR|XX3(59,90), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8713 | {"pmxvi8ger4spp", PMMIRR|XX3(59,99), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, | |
8714 | {"pmxvi16ger2pp", PMMIRR|XX3(59,107), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8715 | {"pmxvbf16ger2np",PMMIRR|XX3(59,114), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8716 | {"pmxvf64gernp", PMMIRR|XX3(59,122), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8717 | {"pmxvf16ger2pn", PMMIRR|XX3(59,146), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8718 | {"pmxvf32gerpn", PMMIRR|XX3(59,154), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8719 | {"pmxvbf16ger2pn",PMMIRR|XX3(59,178), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8720 | {"pmxvf64gerpn", PMMIRR|XX3(59,186), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8721 | {"pmxvf16ger2nn", PMMIRR|XX3(59,210), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8722 | {"pmxvf32gernn", PMMIRR|XX3(59,218), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8723 | {"pmxvbf16ger2nn",PMMIRR|XX3(59,242), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8724 | {"pmxvf64gernn", PMMIRR|XX3(59,250), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
7c1f4227 AM |
8725 | {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}}, |
8726 | {"pstd", P8LS|OP(61), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
94ba9882 | 8727 | {"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}}, |
dd7efa79 PB |
8728 | }; |
8729 | ||
8730 | const unsigned int prefix_num_opcodes = | |
8731 | sizeof (prefix_opcodes) / sizeof (prefix_opcodes[0]); | |
8732 | \f | |
b9c361e0 JL |
8733 | /* The VLE opcode table. |
8734 | ||
8735 | The format of this opcode table is the same as the main opcode table. */ | |
8736 | ||
8737 | const struct powerpc_opcode vle_opcodes[] = { | |
14b57c7c AM |
8738 | {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, |
8739 | {"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, | |
8740 | {"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, | |
8741 | {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, | |
8742 | {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, | |
8743 | {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, | |
8744 | {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, | |
8745 | {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, | |
8746 | {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, | |
8747 | {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, | |
8748 | {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, | |
a8cc8a54 | 8749 | {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}}, |
14b57c7c AM |
8750 | {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, |
8751 | {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8752 | {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8753 | {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8754 | {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8755 | {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8756 | {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8757 | {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8758 | {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8759 | {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8760 | {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8761 | {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, | |
8762 | {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, | |
8763 | {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8764 | {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8765 | {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8766 | {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8767 | {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8768 | {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8769 | {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8770 | {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8771 | ||
e3c2f928 AF |
8772 | /* by major opcode */ |
8773 | {"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8774 | {"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8775 | {"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8776 | {"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8777 | {"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8778 | {"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8779 | {"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8780 | {"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8781 | {"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8782 | {"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8783 | {"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8784 | {"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8785 | {"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8786 | {"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8787 | {"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8788 | {"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8789 | {"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8790 | {"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8791 | {"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8792 | {"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8793 | {"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8794 | {"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8795 | {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8796 | {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8797 | {"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8798 | {"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8799 | {"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8800 | {"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8801 | {"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8802 | {"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8803 | {"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8804 | {"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8805 | {"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8806 | {"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8807 | {"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8808 | {"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8809 | {"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8810 | {"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8811 | {"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8812 | {"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8813 | {"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8814 | {"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8815 | {"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8816 | {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8817 | {"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8818 | {"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8819 | {"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8820 | {"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8821 | {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, | |
8822 | {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, | |
8823 | {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8824 | {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8825 | {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8826 | {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8827 | {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8828 | {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8829 | {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8830 | {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8831 | {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8832 | {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8833 | {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8834 | {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8835 | {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8836 | {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8837 | {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8838 | {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8839 | {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8840 | {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8841 | {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8842 | {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8843 | {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8844 | {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8845 | {"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8846 | {"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8847 | {"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8848 | {"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8849 | {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}}, | |
8850 | {"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8851 | {"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8852 | {"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8853 | {"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8854 | {"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8855 | {"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8856 | {"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8857 | {"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8858 | {"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8859 | {"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8860 | {"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8861 | {"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8862 | {"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8863 | {"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8864 | {"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8865 | {"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8866 | {"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8867 | {"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8868 | {"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8869 | {"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8870 | {"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8871 | {"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8872 | {"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8873 | {"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8874 | {"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8875 | {"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8876 | {"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8877 | {"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8878 | {"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8879 | {"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8880 | {"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8881 | {"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8882 | {"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8883 | {"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8884 | {"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8885 | {"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8886 | {"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8887 | {"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8888 | {"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8889 | {"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8890 | {"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8891 | {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8892 | {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8893 | {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8894 | {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8895 | {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8896 | {"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8897 | {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8898 | {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8899 | {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8900 | {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8901 | {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8902 | {"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8903 | {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8904 | {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8905 | {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8906 | {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8907 | {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8908 | {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8909 | {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8910 | {"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8911 | {"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8912 | {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8913 | {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8914 | {"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8915 | {"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8916 | {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8917 | {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8918 | {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8919 | {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8920 | {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8921 | {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8922 | {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8923 | {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8924 | {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8925 | {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8926 | {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8927 | {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8928 | {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8929 | {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8930 | {"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8931 | {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8932 | {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8933 | {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8934 | {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8935 | {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8936 | {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8937 | {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8938 | {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8939 | {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8940 | {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8941 | {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8942 | {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8943 | {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8944 | {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8945 | {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8946 | {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8947 | {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8948 | {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8949 | {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8950 | {"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8951 | {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8952 | {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8953 | {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8954 | {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8955 | {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8956 | {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8957 | {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8958 | {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8959 | {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8960 | {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8961 | {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8962 | {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8963 | {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8964 | {"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8965 | {"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8966 | {"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8967 | {"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8968 | {"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8969 | {"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8970 | {"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8971 | {"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8972 | {"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8973 | {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8974 | {"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8975 | {"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8976 | {"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8977 | {"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8978 | {"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8979 | {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8980 | {"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8981 | {"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8982 | {"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8983 | {"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8984 | {"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8985 | {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8986 | {"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8987 | {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8988 | {"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8989 | {"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8990 | {"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8991 | {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8992 | {"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8993 | {"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8994 | {"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8995 | {"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8996 | {"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8997 | {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8998 | {"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8999 | {"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9000 | {"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9001 | {"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9002 | {"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9003 | {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9004 | {"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9005 | {"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9006 | {"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9007 | {"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9008 | {"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9009 | {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9010 | {"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9011 | {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9012 | {"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9013 | {"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9014 | {"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9015 | {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9016 | {"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9017 | {"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9018 | {"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9019 | {"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9020 | {"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9021 | {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9022 | {"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9023 | {"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9024 | {"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9025 | {"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9026 | {"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9027 | {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9028 | {"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9029 | {"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9030 | {"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9031 | {"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9032 | {"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9033 | {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9034 | {"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9035 | {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9036 | {"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9037 | {"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9038 | {"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9039 | {"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9040 | {"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9041 | {"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9042 | {"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9043 | {"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9044 | {"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9045 | {"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9046 | {"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9047 | {"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9048 | {"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9049 | {"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9050 | {"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9051 | {"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9052 | {"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9053 | {"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9054 | {"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9055 | {"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9056 | {"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9057 | {"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9058 | {"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9059 | {"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9060 | {"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9061 | {"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9062 | {"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9063 | {"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9064 | {"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9065 | {"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9066 | {"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9067 | {"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9068 | {"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9069 | {"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9070 | {"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9071 | {"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9072 | {"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9073 | {"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9074 | {"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9075 | {"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9076 | {"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9077 | {"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9078 | {"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9079 | {"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9080 | {"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9081 | {"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9082 | {"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9083 | {"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9084 | {"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9085 | {"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9086 | {"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9087 | {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9088 | {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9089 | {"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9090 | {"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9091 | {"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9092 | {"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9093 | {"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9094 | {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9095 | {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9096 | {"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9097 | {"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9098 | {"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9099 | {"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9100 | {"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9101 | {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9102 | {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9103 | {"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9104 | {"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9105 | {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9106 | {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9107 | {"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9108 | {"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9109 | {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9110 | {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9111 | {"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9112 | {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9113 | {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9114 | {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9115 | {"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9116 | {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9117 | {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9118 | {"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9119 | {"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9120 | {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9121 | {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9122 | {"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9123 | {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9124 | {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9125 | {"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9126 | {"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9127 | {"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9128 | {"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9129 | {"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9130 | {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9131 | {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9132 | {"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9133 | {"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9134 | {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9135 | {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9136 | {"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9137 | {"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9138 | {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9139 | {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9140 | {"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9141 | {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9142 | {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9143 | {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9144 | {"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9145 | {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9146 | {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9147 | {"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9148 | {"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9149 | {"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9150 | {"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9151 | {"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9152 | {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9153 | {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9154 | {"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9155 | {"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9156 | {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9157 | {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9158 | {"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9159 | {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9160 | {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9161 | {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9162 | {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9163 | {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9164 | {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9165 | {"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9166 | {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9167 | {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9168 | {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9169 | {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9170 | {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9171 | {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9172 | {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9173 | {"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9174 | {"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9175 | {"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9176 | {"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9177 | {"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9178 | {"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9179 | {"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9180 | {"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9181 | {"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9182 | {"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9183 | {"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9184 | {"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9185 | {"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9186 | {"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9187 | {"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9188 | {"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9189 | {"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9190 | {"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9191 | {"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9192 | {"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9193 | {"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9194 | {"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9195 | {"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9196 | {"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9197 | {"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9198 | {"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9199 | {"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9200 | {"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9201 | {"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9202 | {"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9203 | {"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9204 | {"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9205 | {"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9206 | {"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9207 | {"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9208 | {"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9209 | {"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9210 | {"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9211 | {"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9212 | {"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9213 | {"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9214 | {"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9215 | {"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9216 | {"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9217 | {"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9218 | {"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9219 | {"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9220 | {"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9221 | {"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9222 | {"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9223 | {"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9224 | {"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9225 | {"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9226 | {"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9227 | {"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9228 | {"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9229 | {"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9230 | {"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9231 | {"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9232 | {"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9233 | {"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9234 | {"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9235 | {"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9236 | {"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9237 | {"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9238 | {"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9239 | {"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9240 | {"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9241 | {"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9242 | {"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9243 | {"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9244 | {"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9245 | {"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9246 | {"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9247 | {"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9248 | {"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9249 | {"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9250 | {"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9251 | {"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9252 | {"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9253 | {"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9254 | {"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9255 | {"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9256 | {"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9257 | {"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9258 | {"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9259 | {"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9260 | {"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9261 | {"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9262 | {"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9263 | {"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9264 | {"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9265 | {"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9266 | {"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9267 | {"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9268 | {"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9269 | {"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9270 | {"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9271 | {"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9272 | {"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9273 | {"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9274 | {"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9275 | {"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9276 | {"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9277 | {"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9278 | {"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9279 | {"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9280 | {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9281 | {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9282 | {"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9283 | {"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9284 | {"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9285 | {"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9286 | {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9287 | {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9288 | {"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9289 | {"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9290 | {"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9291 | {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9292 | {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9293 | {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9294 | {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9295 | {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9296 | {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9297 | {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9298 | {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9299 | {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9300 | {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9301 | {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9302 | {"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9303 | {"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9304 | {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9305 | {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9306 | {"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9307 | {"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9308 | {"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9309 | {"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9310 | {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9311 | {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9312 | {"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9313 | {"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9314 | {"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9315 | {"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9316 | {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9317 | {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9318 | {"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9319 | {"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9320 | {"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9321 | {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9322 | {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9323 | {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9324 | {"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9325 | {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9326 | {"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9327 | {"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9328 | {"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9329 | {"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9330 | {"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9331 | {"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9332 | {"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9333 | {"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9334 | {"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9335 | {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9336 | {"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9337 | {"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9338 | {"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9339 | {"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9340 | {"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9341 | {"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9342 | {"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9343 | {"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9344 | {"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
9345 | {"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9346 | {"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
9347 | {"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9348 | {"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
9349 | {"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9350 | {"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9351 | {"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9352 | {"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9353 | {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9354 | {"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9355 | {"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9356 | {"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9357 | {"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9358 | {"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9359 | {"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9360 | {"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9361 | {"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9362 | {"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9363 | {"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9364 | {"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9365 | {"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9366 | {"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, | |
9367 | {"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9368 | {"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, | |
9369 | {"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9370 | {"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9371 | {"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9372 | {"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9373 | {"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9374 | {"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
9375 | {"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9376 | {"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
9377 | {"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9378 | {"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
9379 | {"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9380 | {"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, | |
9381 | {"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9382 | {"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, | |
9383 | {"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9384 | {"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9385 | {"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9386 | {"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9387 | {"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9388 | {"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9389 | {"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9390 | {"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, | |
9391 | {"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9392 | {"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, | |
9393 | {"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9394 | {"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, | |
9395 | {"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9396 | {"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, | |
9397 | {"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9398 | {"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
9399 | {"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9400 | {"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
9401 | {"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9402 | {"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
9403 | {"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9404 | {"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9405 | {"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9406 | {"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9407 | {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9408 | {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9409 | {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9410 | {"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9411 | {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9412 | {"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9413 | {"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9414 | {"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9415 | {"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9416 | {"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9417 | {"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9418 | {"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9419 | {"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9420 | {"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9421 | {"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9422 | {"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9423 | {"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9424 | {"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9425 | {"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9426 | {"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9427 | {"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9428 | {"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}}, | |
9429 | {"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9430 | {"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, | |
9431 | {"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9432 | {"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, | |
9433 | {"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9434 | {"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, | |
9435 | {"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9436 | {"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, | |
9437 | {"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9438 | {"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9439 | {"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9440 | {"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9441 | {"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9442 | {"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9443 | {"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9444 | {"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, | |
9445 | {"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9446 | {"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, | |
9447 | {"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9448 | {"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9449 | {"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9450 | {"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9451 | ||
14b57c7c | 9452 | {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
dfdaec14 | 9453 | {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
14b57c7c | 9454 | {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
dfdaec14 | 9455 | {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
14b57c7c AM |
9456 | {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
9457 | {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
9458 | {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9459 | {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9460 | {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
9461 | {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9462 | {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
9463 | {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9464 | {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9465 | {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9466 | {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9467 | {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9468 | {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}}, | |
9469 | {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9470 | {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9471 | {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9472 | {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9473 | {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9474 | {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9475 | {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9476 | {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9477 | {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9478 | {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9479 | {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9480 | {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9481 | {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
d2e6c9a3 | 9482 | {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9483 | {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9484 | {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9485 | {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9486 | {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9487 | {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9488 | {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9489 | {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9490 | {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9491 | {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9492 | {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9493 | {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9494 | {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9495 | {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9496 | {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 AF |
9497 | {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9498 | {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
14b57c7c AM |
9499 | {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, |
9500 | {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9501 | {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, | |
9502 | ||
9503 | {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9504 | {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9505 | {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9506 | {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9507 | {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9508 | {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9509 | {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9510 | ||
9511 | {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9512 | {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9513 | {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9514 | ||
9515 | {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9516 | {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9517 | {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9518 | {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, | |
9519 | {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9520 | {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9521 | {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9522 | {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9523 | {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, | |
9524 | ||
9525 | {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9526 | {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9527 | {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9528 | {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9529 | ||
9530 | {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9531 | {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9532 | {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9533 | {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9534 | {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9535 | {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9536 | {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9537 | ||
9538 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9539 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9540 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9541 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9542 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9543 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, | |
9544 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
9545 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, | |
14b57c7c AM |
9546 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
9547 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
14b57c7c AM |
9548 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, |
9549 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
9550 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, | |
9551 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
9552 | {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, | |
9553 | {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, | |
9554 | {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, | |
9555 | {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, | |
9556 | {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, | |
9557 | {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9558 | {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9559 | {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9560 | {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9561 | {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9562 | {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9563 | {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9564 | {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9565 | {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9566 | {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9567 | {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9568 | {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9569 | {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9570 | {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9571 | {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9572 | {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9573 | {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9574 | {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9575 | {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9576 | {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9577 | {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9578 | {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9579 | {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9580 | {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9581 | {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9582 | {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9583 | {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9584 | {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9585 | {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, | |
9586 | {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, | |
9587 | ||
9588 | {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9589 | {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9590 | {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9591 | {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9592 | ||
9593 | {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, | |
a8cc8a54 | 9594 | {"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}}, |
14b57c7c AM |
9595 | {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, |
9596 | {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
9597 | {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
98553ad3 | 9598 | {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BAB}}, |
14b57c7c | 9599 | {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
98553ad3 | 9600 | {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BTAB}}, |
14b57c7c AM |
9601 | {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
9602 | {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, | |
9603 | {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9604 | {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9605 | ||
9606 | {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
9607 | ||
9608 | {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, | |
9609 | {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, | |
9610 | ||
98553ad3 | 9611 | {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BTAB}}, |
14b57c7c AM |
9612 | {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
9613 | ||
9614 | {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9615 | {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9616 | ||
9617 | {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
9618 | ||
98553ad3 | 9619 | {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BAB}}, |
14b57c7c AM |
9620 | {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
9621 | ||
9622 | {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, | |
9623 | ||
9624 | {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9625 | {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9626 | ||
9627 | {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, | |
9628 | ||
9629 | {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, | |
9630 | ||
9631 | {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, | |
9632 | ||
9633 | {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, | |
9634 | ||
9635 | {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, | |
9636 | ||
9637 | {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, | |
9638 | ||
9639 | {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9640 | {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9641 | {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9642 | {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9643 | {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9644 | {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9645 | {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9646 | {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, | |
9647 | {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9648 | {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9649 | {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9650 | {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9651 | {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9652 | {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, | |
9653 | {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, | |
9654 | {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, | |
9655 | {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, | |
b9c361e0 JL |
9656 | }; |
9657 | ||
2ceb7719 | 9658 | const unsigned int vle_num_opcodes = |
b9c361e0 JL |
9659 | sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); |
9660 | \f | |
252b5132 RH |
9661 | /* The macro table. This is only used by the assembler. */ |
9662 | ||
9663 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 | |
9664 | when x=0; 32-x when x is between 1 and 31; are negative if x is | |
9665 | negative; and are 32 or more otherwise. This is what you want | |
9666 | when, for instance, you are emulating a right shift by a | |
9667 | rotate-left-and-mask, because the underlying instructions support | |
9668 | shifts of size 0 but not shifts of size 32. By comparison, when | |
9669 | extracting x bits from some word you want to use just 32-x, because | |
9670 | the underlying instructions don't support extracting 0 bits but do | |
9671 | support extracting the whole word (32 bits in this case). */ | |
9672 | ||
9673 | const struct powerpc_macro powerpc_macros[] = { | |
de866fcc AM |
9674 | {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, |
9675 | {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, | |
bdc7fcfe AM |
9676 | {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, |
9677 | {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, | |
de866fcc AM |
9678 | {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, |
9679 | {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, | |
9680 | {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
9681 | {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
9682 | {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, | |
9683 | {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, | |
9684 | {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
9685 | {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
9686 | {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, | |
9687 | {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, | |
9688 | {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, | |
14b57c7c | 9689 | {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, |
de866fcc AM |
9690 | |
9691 | {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, | |
9692 | {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, | |
9693 | {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
9694 | {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
9695 | {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
9696 | {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
9697 | {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
9698 | {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
9699 | {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
9700 | {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
9701 | {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, | |
9702 | {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, | |
9703 | {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, | |
9704 | {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, | |
9705 | {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9706 | {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9707 | {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9708 | {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9709 | {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, | |
9710 | {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, | |
9711 | {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
9712 | {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
a4ebc835 AM |
9713 | |
9714 | {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, | |
9715 | {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
9716 | {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
9717 | {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
9718 | {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, | |
9719 | {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
9720 | {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, | |
9721 | {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9722 | {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, | |
9723 | {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, | |
9724 | {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
74081948 AF |
9725 | |
9726 | /* old SPE instructions have new names with the same opcodes */ | |
9727 | {"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"}, | |
9728 | {"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"}, | |
9729 | {"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"}, | |
9730 | {"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"}, | |
9731 | {"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"}, | |
9732 | {"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"}, | |
9733 | {"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"}, | |
9734 | {"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"}, | |
9735 | {"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"}, | |
9736 | {"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"}, | |
9737 | {"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"}, | |
9738 | {"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"}, | |
9739 | {"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"}, | |
9740 | {"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"}, | |
9741 | {"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"}, | |
9742 | {"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"}, | |
9743 | {"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"}, | |
9744 | {"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"}, | |
9745 | {"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"}, | |
9746 | {"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"}, | |
9747 | {"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"}, | |
9748 | {"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"}, | |
9749 | {"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"}, | |
9750 | ||
9751 | /* SPE2 instructions which just are mapped to SPE2 */ | |
9752 | {"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"}, | |
9753 | {"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"}, | |
9754 | {"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"}, | |
9755 | {"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"} | |
252b5132 RH |
9756 | }; |
9757 | ||
9758 | const int powerpc_num_macros = | |
9759 | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); | |
74081948 AF |
9760 | |
9761 | /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */ | |
9762 | const struct powerpc_opcode spe2_opcodes[] = { | |
9763 | {"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9764 | {"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9765 | {"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9766 | {"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9767 | {"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9768 | {"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9769 | {"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9770 | {"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9771 | {"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9772 | {"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9773 | {"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9774 | {"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9775 | {"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9776 | {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9777 | {"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9778 | {"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9779 | {"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9780 | {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9781 | {"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9782 | {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9783 | {"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9784 | {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9785 | {"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9786 | {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9787 | {"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9788 | {"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9789 | {"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9790 | {"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9791 | {"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9792 | {"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9793 | {"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9794 | {"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9795 | {"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9796 | {"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9797 | {"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9798 | {"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9799 | {"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9800 | {"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9801 | {"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9802 | {"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9803 | {"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9804 | {"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9805 | {"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9806 | {"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9807 | {"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9808 | {"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9809 | {"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9810 | {"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9811 | {"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9812 | {"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9813 | {"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9814 | {"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9815 | {"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9816 | {"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9817 | {"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9818 | {"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9819 | {"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9820 | {"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9821 | {"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9822 | {"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9823 | {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9824 | {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9825 | {"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9826 | {"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9827 | {"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9828 | {"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9829 | {"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9830 | {"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9831 | {"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9832 | {"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9833 | {"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9834 | {"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9835 | {"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9836 | {"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9837 | {"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9838 | {"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9839 | {"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9840 | {"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9841 | {"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9842 | {"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9843 | {"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9844 | {"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9845 | {"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9846 | {"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9847 | {"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9848 | {"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9849 | {"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9850 | {"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9851 | {"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9852 | {"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9853 | {"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9854 | {"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9855 | {"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9856 | {"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9857 | {"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9858 | {"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9859 | {"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9860 | {"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9861 | {"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9862 | {"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9863 | {"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9864 | {"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9865 | {"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9866 | {"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9867 | {"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9868 | {"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9869 | {"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9870 | {"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9871 | {"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9872 | {"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9873 | {"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9874 | {"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9875 | {"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9876 | {"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9877 | {"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9878 | {"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9879 | {"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9880 | {"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9881 | {"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9882 | {"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9883 | {"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9884 | {"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9885 | {"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9886 | {"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9887 | {"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9888 | {"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9889 | {"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9890 | {"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9891 | {"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9892 | {"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9893 | {"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9894 | {"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9895 | {"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9896 | {"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9897 | {"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9898 | {"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9899 | {"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9900 | {"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9901 | {"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9902 | {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9903 | {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9904 | {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9905 | {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9906 | {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9907 | {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9908 | {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9909 | {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9910 | {"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9911 | {"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9912 | {"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9913 | {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9914 | {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9915 | {"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9916 | {"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9917 | {"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9918 | {"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9919 | {"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9920 | {"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9921 | {"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9922 | {"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9923 | {"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9924 | {"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9925 | {"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9926 | {"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9927 | {"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9928 | {"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9929 | {"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9930 | {"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9931 | {"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9932 | {"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9933 | {"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9934 | {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9935 | {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9936 | {"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9937 | {"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9938 | {"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9939 | {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9940 | {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9941 | {"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9942 | {"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9943 | {"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9944 | {"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9945 | {"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9946 | {"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9947 | {"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9948 | {"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9949 | {"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9950 | {"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9951 | {"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9952 | {"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9953 | {"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9954 | {"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9955 | {"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9956 | {"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9957 | {"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9958 | {"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9959 | {"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9960 | {"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9961 | {"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9962 | {"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9963 | {"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9964 | {"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9965 | {"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9966 | {"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9967 | {"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9968 | {"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9969 | {"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9970 | {"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9971 | {"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, | |
9972 | {"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, | |
9973 | {"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, | |
9974 | {"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, | |
9975 | {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9976 | {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9977 | {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9978 | {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9979 | {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9980 | {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9981 | {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9982 | {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9983 | {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9984 | {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9985 | {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9986 | {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9987 | {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9988 | {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9989 | {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9990 | {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9991 | {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9992 | {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9993 | {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9994 | {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9995 | {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9996 | {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9997 | {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9998 | {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9999 | {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10000 | {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10001 | {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10002 | {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10003 | {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10004 | {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10005 | {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10006 | {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10007 | {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10008 | {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10009 | {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10010 | {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10011 | {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10012 | {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10013 | {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10014 | {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10015 | {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10016 | {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10017 | {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10018 | {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10019 | {"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10020 | {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10021 | {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10022 | {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10023 | {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10024 | {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10025 | {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10026 | {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10027 | {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10028 | {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10029 | {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10030 | {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10031 | {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10032 | {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10033 | {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10034 | {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10035 | {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10036 | {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10037 | {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10038 | {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10039 | {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10040 | {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10041 | {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10042 | {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10043 | {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10044 | {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10045 | {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10046 | {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10047 | {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10048 | {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10049 | {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10050 | {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10051 | {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10052 | {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10053 | {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10054 | {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10055 | {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10056 | {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10057 | {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10058 | {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10059 | {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10060 | {"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10061 | {"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10062 | {"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
10063 | {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10064 | {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10065 | {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10066 | {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10067 | {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10068 | {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10069 | {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10070 | {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10071 | {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10072 | {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10073 | {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10074 | {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10075 | {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10076 | {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10077 | {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10078 | {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10079 | {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10080 | {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10081 | {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10082 | {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10083 | {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10084 | {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10085 | {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10086 | {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10087 | {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10088 | {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
10089 | {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
10090 | {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
10091 | {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
10092 | {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
10093 | {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
10094 | {"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10095 | {"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10096 | {"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10097 | {"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10098 | {"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10099 | {"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10100 | {"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10101 | {"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10102 | {"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, | |
10103 | {"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, | |
10104 | {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}}, | |
10105 | {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}}, | |
10106 | {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, | |
10107 | {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
10108 | {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
10109 | {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
10110 | {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, | |
10111 | {"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10112 | {"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10113 | {"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10114 | {"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10115 | {"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10116 | {"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10117 | {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}}, | |
10118 | {"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10119 | {"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10120 | {"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
10121 | {"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
10122 | {"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10123 | {"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10124 | {"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
10125 | {"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
10126 | {"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10127 | {"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10128 | {"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
10129 | {"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
10130 | {"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10131 | {"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10132 | {"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
10133 | {"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
10134 | {"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10135 | {"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10136 | {"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
10137 | {"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
10138 | {"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10139 | {"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10140 | {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
10141 | {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
10142 | {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
10143 | {"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10144 | {"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}}, | |
10145 | {"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10146 | {"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}}, | |
10147 | {"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10148 | {"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
10149 | {"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10150 | {"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
10151 | {"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10152 | {"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}}, | |
10153 | {"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10154 | {"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}}, | |
10155 | {"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10156 | {"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
10157 | {"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10158 | {"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
10159 | {"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10160 | {"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
10161 | {"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10162 | {"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
10163 | {"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10164 | {"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
10165 | {"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10166 | {"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
10167 | {"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10168 | {"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}}, | |
10169 | {"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10170 | {"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
10171 | {"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10172 | {"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
10173 | {"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10174 | {"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
10175 | {"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10176 | {"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
10177 | {"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10178 | {"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
10179 | {"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10180 | {"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
10181 | {"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10182 | {"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
10183 | {"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10184 | {"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
10185 | {"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10186 | {"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10187 | {"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10188 | {"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10189 | {"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10190 | {"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10191 | {"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10192 | {"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10193 | {"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10194 | {"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10195 | {"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10196 | {"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10197 | {"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10198 | {"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10199 | {"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10200 | {"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}}, | |
10201 | {"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10202 | {"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10203 | {"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10204 | {"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10205 | {"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10206 | {"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10207 | {"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10208 | {"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10209 | {"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10210 | {"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10211 | {"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10212 | {"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10213 | {"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10214 | {"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10215 | {"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10216 | {"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10217 | {"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10218 | {"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10219 | {"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10220 | {"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10221 | {"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10222 | {"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10223 | {"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10224 | {"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10225 | {"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10226 | {"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10227 | {"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10228 | {"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10229 | {"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10230 | {"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}}, | |
10231 | {"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10232 | {"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10233 | {"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10234 | {"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10235 | {"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10236 | {"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10237 | {"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10238 | {"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10239 | {"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10240 | {"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10241 | {"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10242 | {"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10243 | {"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10244 | {"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10245 | {"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10246 | {"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10247 | {"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10248 | {"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10249 | {"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10250 | {"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10251 | {"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10252 | {"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10253 | {"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10254 | {"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10255 | {"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10256 | {"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10257 | {"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10258 | {"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10259 | {"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10260 | {"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10261 | {"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10262 | {"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10263 | {"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10264 | {"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10265 | {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10266 | {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10267 | {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10268 | {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10269 | {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10270 | {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10271 | {"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10272 | {"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10273 | {"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10274 | {"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10275 | {"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10276 | {"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10277 | {"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10278 | {"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10279 | {"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10280 | {"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10281 | {"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10282 | {"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10283 | {"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10284 | {"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10285 | {"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10286 | {"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10287 | {"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10288 | {"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10289 | {"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10290 | {"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10291 | {"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10292 | {"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10293 | {"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10294 | {"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10295 | {"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10296 | {"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10297 | {"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10298 | {"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10299 | {"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10300 | {"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10301 | {"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10302 | {"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10303 | {"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10304 | {"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10305 | {"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10306 | {"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10307 | {"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10308 | {"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10309 | {"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10310 | {"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10311 | {"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10312 | {"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10313 | {"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10314 | {"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10315 | {"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10316 | {"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10317 | {"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10318 | {"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10319 | {"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10320 | {"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10321 | {"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10322 | {"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10323 | {"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10324 | {"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10325 | {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}}, | |
10326 | {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10327 | {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10328 | {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10329 | {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10330 | {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10331 | {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10332 | {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10333 | {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10334 | {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10335 | {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10336 | {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10337 | {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10338 | {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10339 | {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10340 | {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10341 | {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10342 | {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10343 | {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10344 | {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10345 | {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10346 | {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10347 | {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10348 | {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10349 | {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10350 | {"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10351 | {"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10352 | {"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10353 | {"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10354 | {"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10355 | {"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10356 | {"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10357 | {"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10358 | {"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10359 | {"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10360 | {"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10361 | {"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10362 | {"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10363 | {"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10364 | {"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10365 | {"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10366 | {"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10367 | {"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10368 | {"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10369 | {"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10370 | {"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10371 | {"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10372 | {"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10373 | {"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10374 | {"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10375 | {"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10376 | {"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10377 | {"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10378 | {"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10379 | {"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10380 | {"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10381 | {"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10382 | {"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10383 | {"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10384 | {"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10385 | {"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10386 | {"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10387 | {"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10388 | {"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10389 | {"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10390 | {"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10391 | {"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10392 | {"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10393 | {"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10394 | {"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10395 | {"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10396 | {"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10397 | {"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10398 | {"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10399 | {"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10400 | {"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10401 | {"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10402 | {"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10403 | {"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10404 | {"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10405 | {"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10406 | {"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10407 | {"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10408 | {"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10409 | {"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10410 | {"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10411 | {"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10412 | {"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10413 | {"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10414 | {"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10415 | {"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10416 | {"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10417 | {"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10418 | {"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10419 | {"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10420 | {"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10421 | {"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10422 | {"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10423 | {"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10424 | {"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10425 | {"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10426 | {"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10427 | {"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10428 | {"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10429 | {"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10430 | {"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10431 | {"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10432 | {"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10433 | {"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10434 | {"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10435 | {"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10436 | {"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10437 | {"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10438 | {"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10439 | {"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10440 | {"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10441 | {"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10442 | {"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10443 | {"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10444 | {"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10445 | {"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10446 | {"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10447 | {"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10448 | {"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10449 | {"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10450 | {"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10451 | {"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10452 | {"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10453 | {"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10454 | {"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10455 | {"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10456 | {"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10457 | {"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10458 | {"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10459 | {"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10460 | {"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10461 | {"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10462 | {"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10463 | {"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10464 | {"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10465 | {"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10466 | {"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10467 | {"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10468 | {"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10469 | {"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10470 | {"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10471 | {"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10472 | {"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10473 | {"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10474 | {"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10475 | {"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10476 | {"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10477 | {"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10478 | {"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10479 | {"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10480 | {"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10481 | {"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10482 | {"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10483 | {"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10484 | {"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10485 | {"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10486 | {"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10487 | {"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10488 | {"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10489 | {"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10490 | {"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10491 | {"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10492 | {"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10493 | {"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10494 | {"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10495 | {"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10496 | {"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10497 | {"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10498 | {"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10499 | {"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10500 | {"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10501 | {"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10502 | {"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10503 | {"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10504 | {"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10505 | {"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10506 | {"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10507 | {"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10508 | {"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10509 | {"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10510 | {"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10511 | {"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10512 | {"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10513 | {"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10514 | {"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10515 | {"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10516 | {"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10517 | {"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10518 | {"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10519 | {"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10520 | {"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10521 | {"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10522 | {"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10523 | {"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10524 | {"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10525 | {"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10526 | {"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10527 | {"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10528 | {"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10529 | {"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10530 | {"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10531 | {"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10532 | {"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10533 | {"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10534 | {"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10535 | {"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10536 | {"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10537 | {"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10538 | {"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10539 | {"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10540 | {"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10541 | {"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10542 | {"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10543 | {"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10544 | {"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10545 | {"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10546 | {"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10547 | }; | |
10548 | ||
2ceb7719 | 10549 | const unsigned int spe2_num_opcodes = |
74081948 | 10550 | sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]); |