Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* ppc-opc.c -- PowerPC opcode list |
5e8cb021 | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, |
aea77599 | 3 | 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
6b069ee7 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Written by Ian Lance Taylor, Cygnus Support |
6 | ||
9b201bb5 | 7 | This file is part of the GNU opcodes library. |
252b5132 | 8 | |
9b201bb5 NC |
9 | This library is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
252b5132 | 13 | |
9b201bb5 NC |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
252b5132 | 18 | |
112290ab | 19 | You should have received a copy of the GNU General Public License |
9b201bb5 NC |
20 | along with this file; see the file COPYING. If not, write to the |
21 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
22 | MA 02110-1301, USA. */ | |
252b5132 | 23 | |
0d8dfecf | 24 | #include "sysdep.h" |
df7b86aa | 25 | #include <stdio.h> |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | #include "opintl.h" | |
28 | ||
29 | /* This file holds the PowerPC opcode table. The opcode table | |
30 | includes almost all of the extended instruction mnemonics. This | |
31 | permits the disassembler to use them, and simplifies the assembler | |
32 | logic, at the cost of increasing the table size. The table is | |
33 | strictly constant data, so the compiler should be able to put it in | |
34 | the .text section. | |
35 | ||
36 | This file also holds the operand table. All knowledge about | |
37 | inserting operands into instructions and vice-versa is kept in this | |
38 | file. */ | |
39 | \f | |
40 | /* Local insertion and extraction functions. */ | |
41 | ||
b9c361e0 JL |
42 | static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **); |
43 | static long extract_arx (unsigned long, ppc_cpu_t, int *); | |
44 | static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **); | |
45 | static long extract_ary (unsigned long, ppc_cpu_t, int *); | |
fa452fa6 PB |
46 | static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); |
47 | static long extract_bat (unsigned long, ppc_cpu_t, int *); | |
48 | static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); | |
49 | static long extract_bba (unsigned long, ppc_cpu_t, int *); | |
50 | static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **); | |
51 | static long extract_bdm (unsigned long, ppc_cpu_t, int *); | |
52 | static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **); | |
53 | static long extract_bdp (unsigned long, ppc_cpu_t, int *); | |
54 | static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **); | |
55 | static long extract_bo (unsigned long, ppc_cpu_t, int *); | |
56 | static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); | |
57 | static long extract_boe (unsigned long, ppc_cpu_t, int *); | |
58 | static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); | |
59 | static long extract_fxm (unsigned long, ppc_cpu_t, int *); | |
b9c361e0 JL |
60 | static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **); |
61 | static long extract_li20 (unsigned long, ppc_cpu_t, int *); | |
aea77599 | 62 | static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); |
fa452fa6 PB |
63 | static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); |
64 | static long extract_mbe (unsigned long, ppc_cpu_t, int *); | |
65 | static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); | |
66 | static long extract_mb6 (unsigned long, ppc_cpu_t, int *); | |
67 | static long extract_nb (unsigned long, ppc_cpu_t, int *); | |
989993d8 | 68 | static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **); |
fa452fa6 PB |
69 | static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); |
70 | static long extract_nsi (unsigned long, ppc_cpu_t, int *); | |
b9c361e0 JL |
71 | static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **); |
72 | static long extract_oimm (unsigned long, ppc_cpu_t, int *); | |
fa452fa6 PB |
73 | static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); |
74 | static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); | |
75 | static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); | |
76 | static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **); | |
77 | static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); | |
78 | static long extract_rbs (unsigned long, ppc_cpu_t, int *); | |
989993d8 | 79 | static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **); |
b9c361e0 JL |
80 | static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **); |
81 | static long extract_rx (unsigned long, ppc_cpu_t, int *); | |
82 | static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **); | |
83 | static long extract_ry (unsigned long, ppc_cpu_t, int *); | |
fa452fa6 PB |
84 | static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); |
85 | static long extract_sh6 (unsigned long, ppc_cpu_t, int *); | |
b9c361e0 JL |
86 | static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **); |
87 | static long extract_sci8 (unsigned long, ppc_cpu_t, int *); | |
88 | static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **); | |
89 | static long extract_sci8n (unsigned long, ppc_cpu_t, int *); | |
90 | static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **); | |
91 | static long extract_sd4h (unsigned long, ppc_cpu_t, int *); | |
92 | static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **); | |
93 | static long extract_sd4w (unsigned long, ppc_cpu_t, int *); | |
fa452fa6 PB |
94 | static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); |
95 | static long extract_spr (unsigned long, ppc_cpu_t, int *); | |
96 | static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); | |
97 | static long extract_sprg (unsigned long, ppc_cpu_t, int *); | |
98 | static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); | |
99 | static long extract_tbr (unsigned long, ppc_cpu_t, int *); | |
9b4e5766 PB |
100 | static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); |
101 | static long extract_xt6 (unsigned long, ppc_cpu_t, int *); | |
102 | static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); | |
103 | static long extract_xa6 (unsigned long, ppc_cpu_t, int *); | |
104 | static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); | |
105 | static long extract_xb6 (unsigned long, ppc_cpu_t, int *); | |
106 | static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); | |
107 | static long extract_xb6s (unsigned long, ppc_cpu_t, int *); | |
066be9f7 PB |
108 | static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); |
109 | static long extract_xc6 (unsigned long, ppc_cpu_t, int *); | |
110 | static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); | |
111 | static long extract_dm (unsigned long, ppc_cpu_t, int *); | |
b9c361e0 JL |
112 | static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **); |
113 | static long extract_vlesi (unsigned long, ppc_cpu_t, int *); | |
114 | static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **); | |
115 | static long extract_vlensi (unsigned long, ppc_cpu_t, int *); | |
116 | static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **); | |
117 | static long extract_vleui (unsigned long, ppc_cpu_t, int *); | |
118 | static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **); | |
119 | static long extract_vleil (unsigned long, ppc_cpu_t, int *); | |
252b5132 RH |
120 | \f |
121 | /* The operands table. | |
122 | ||
717bbdf1 | 123 | The fields are bitm, shift, insert, extract, flags. |
252b5132 RH |
124 | |
125 | We used to put parens around the various additions, like the one | |
126 | for BA just below. However, that caused trouble with feeble | |
127 | compilers with a limit on depth of a parenthesized expression, like | |
128 | (reportedly) the compiler in Microsoft Developer Studio 5. So we | |
129 | omit the parens, since the macros are never used in a context where | |
130 | the addition will be ambiguous. */ | |
131 | ||
132 | const struct powerpc_operand powerpc_operands[] = | |
133 | { | |
134 | /* The zero index is used to indicate the end of the list of | |
135 | operands. */ | |
136 | #define UNUSED 0 | |
bbac1f2a | 137 | { 0, 0, NULL, NULL, 0 }, |
252b5132 RH |
138 | |
139 | /* The BA field in an XL form instruction. */ | |
140 | #define BA UNUSED + 1 | |
717bbdf1 AM |
141 | /* The BI field in a B form or XL form instruction. */ |
142 | #define BI BA | |
143 | #define BI_MASK (0x1f << 16) | |
b9c361e0 | 144 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, |
252b5132 RH |
145 | |
146 | /* The BA field in an XL form instruction when it must be the same | |
147 | as the BT field in the same instruction. */ | |
148 | #define BAT BA + 1 | |
b84bf58a | 149 | { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, |
252b5132 RH |
150 | |
151 | /* The BB field in an XL form instruction. */ | |
152 | #define BB BAT + 1 | |
153 | #define BB_MASK (0x1f << 11) | |
b9c361e0 | 154 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, |
252b5132 RH |
155 | |
156 | /* The BB field in an XL form instruction when it must be the same | |
157 | as the BA field in the same instruction. */ | |
158 | #define BBA BB + 1 | |
c7a5aa9c PB |
159 | /* The VB field in a VX form instruction when it must be the same |
160 | as the VA field in the same instruction. */ | |
161 | #define VBA BBA | |
b84bf58a | 162 | { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, |
252b5132 RH |
163 | |
164 | /* The BD field in a B form instruction. The lower two bits are | |
165 | forced to zero. */ | |
166 | #define BD BBA + 1 | |
b84bf58a | 167 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
252b5132 RH |
168 | |
169 | /* The BD field in a B form instruction when absolute addressing is | |
170 | used. */ | |
171 | #define BDA BD + 1 | |
b84bf58a | 172 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
252b5132 RH |
173 | |
174 | /* The BD field in a B form instruction when the - modifier is used. | |
175 | This sets the y bit of the BO field appropriately. */ | |
176 | #define BDM BDA + 1 | |
b84bf58a | 177 | { 0xfffc, 0, insert_bdm, extract_bdm, |
11b37b7b | 178 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
252b5132 RH |
179 | |
180 | /* The BD field in a B form instruction when the - modifier is used | |
181 | and absolute address is used. */ | |
182 | #define BDMA BDM + 1 | |
b84bf58a | 183 | { 0xfffc, 0, insert_bdm, extract_bdm, |
11b37b7b | 184 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
252b5132 RH |
185 | |
186 | /* The BD field in a B form instruction when the + modifier is used. | |
187 | This sets the y bit of the BO field appropriately. */ | |
188 | #define BDP BDMA + 1 | |
b84bf58a | 189 | { 0xfffc, 0, insert_bdp, extract_bdp, |
11b37b7b | 190 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
252b5132 RH |
191 | |
192 | /* The BD field in a B form instruction when the + modifier is used | |
193 | and absolute addressing is used. */ | |
194 | #define BDPA BDP + 1 | |
b84bf58a | 195 | { 0xfffc, 0, insert_bdp, extract_bdp, |
11b37b7b | 196 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
252b5132 RH |
197 | |
198 | /* The BF field in an X or XL form instruction. */ | |
199 | #define BF BDPA + 1 | |
717bbdf1 AM |
200 | /* The CRFD field in an X form instruction. */ |
201 | #define CRFD BF | |
b9c361e0 JL |
202 | /* The CRD field in an XL form instruction. */ |
203 | #define CRD BF | |
204 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, | |
252b5132 | 205 | |
ea192fa3 PB |
206 | /* The BF field in an X or XL form instruction. */ |
207 | #define BFF BF + 1 | |
208 | { 0x7, 23, NULL, NULL, 0 }, | |
209 | ||
252b5132 RH |
210 | /* An optional BF field. This is used for comparison instructions, |
211 | in which an omitted BF field is taken as zero. */ | |
ea192fa3 | 212 | #define OBF BFF + 1 |
b9c361e0 | 213 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
252b5132 RH |
214 | |
215 | /* The BFA field in an X or XL form instruction. */ | |
216 | #define BFA OBF + 1 | |
b9c361e0 | 217 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, |
252b5132 | 218 | |
252b5132 RH |
219 | /* The BO field in a B form instruction. Certain values are |
220 | illegal. */ | |
717bbdf1 | 221 | #define BO BFA + 1 |
252b5132 | 222 | #define BO_MASK (0x1f << 21) |
b84bf58a | 223 | { 0x1f, 21, insert_bo, extract_bo, 0 }, |
252b5132 RH |
224 | |
225 | /* The BO field in a B form instruction when the + or - modifier is | |
226 | used. This is like the BO field, but it must be even. */ | |
227 | #define BOE BO + 1 | |
b84bf58a | 228 | { 0x1e, 21, insert_boe, extract_boe, 0 }, |
252b5132 | 229 | |
d0618d1c | 230 | #define BH BOE + 1 |
b84bf58a | 231 | { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
d0618d1c | 232 | |
252b5132 | 233 | /* The BT field in an X or XL form instruction. */ |
d0618d1c | 234 | #define BT BH + 1 |
b9c361e0 JL |
235 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, |
236 | ||
237 | /* The BI16 field in a BD8 form instruction. */ | |
238 | #define BI16 BT + 1 | |
239 | { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
240 | ||
241 | /* The BI32 field in a BD15 form instruction. */ | |
242 | #define BI32 BI16 + 1 | |
243 | { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
244 | ||
245 | /* The BO32 field in a BD15 form instruction. */ | |
246 | #define BO32 BI32 + 1 | |
247 | { 0x3, 20, NULL, NULL, 0 }, | |
248 | ||
249 | /* The B8 field in a BD8 form instruction. */ | |
250 | #define B8 BO32 + 1 | |
251 | { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
252 | ||
253 | /* The B15 field in a BD15 form instruction. The lowest bit is | |
254 | forced to zero. */ | |
255 | #define B15 B8 + 1 | |
256 | { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
257 | ||
258 | /* The B24 field in a BD24 form instruction. The lowest bit is | |
259 | forced to zero. */ | |
260 | #define B24 B15 + 1 | |
261 | { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
252b5132 RH |
262 | |
263 | /* The condition register number portion of the BI field in a B form | |
264 | or XL form instruction. This is used for the extended | |
265 | conditional branch mnemonics, which set the lower two bits of the | |
266 | BI field. This field is optional. */ | |
b9c361e0 JL |
267 | #define CR B24 + 1 |
268 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
252b5132 | 269 | |
23976049 EZ |
270 | /* The CRB field in an X form instruction. */ |
271 | #define CRB CR + 1 | |
717bbdf1 AM |
272 | /* The MB field in an M form instruction. */ |
273 | #define MB CRB | |
274 | #define MB_MASK (0x1f << 6) | |
b84bf58a | 275 | { 0x1f, 6, NULL, NULL, 0 }, |
23976049 | 276 | |
b9c361e0 JL |
277 | /* The CRD32 field in an XL form instruction. */ |
278 | #define CRD32 CRB + 1 | |
279 | { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, | |
280 | ||
23976049 | 281 | /* The CRFS field in an X form instruction. */ |
b9c361e0 JL |
282 | #define CRFS CRD32 + 1 |
283 | { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, | |
284 | ||
285 | #define CRS CRFS + 1 | |
286 | { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
23976049 | 287 | |
418c1742 | 288 | /* The CT field in an X form instruction. */ |
b9c361e0 | 289 | #define CT CRS + 1 |
717bbdf1 AM |
290 | /* The MO field in an mbar instruction. */ |
291 | #define MO CT | |
b84bf58a | 292 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
418c1742 | 293 | |
252b5132 RH |
294 | /* The D field in a D form instruction. This is a displacement off |
295 | a register, and implies that the next operand is a register in | |
296 | parentheses. */ | |
418c1742 | 297 | #define D CT + 1 |
b84bf58a | 298 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
252b5132 | 299 | |
b9c361e0 JL |
300 | /* The D8 field in a D form instruction. This is a displacement off |
301 | a register, and implies that the next operand is a register in | |
302 | parentheses. */ | |
303 | #define D8 D + 1 | |
304 | { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
305 | ||
adadcc0c AM |
306 | /* The DQ field in a DQ form instruction. This is like D, but the |
307 | lower four bits are forced to zero. */ | |
b9c361e0 | 308 | #define DQ D8 + 1 |
b84bf58a AM |
309 | { 0xfff0, 0, NULL, NULL, |
310 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, | |
adadcc0c | 311 | |
252b5132 RH |
312 | /* The DS field in a DS form instruction. This is like D, but the |
313 | lower two bits are forced to zero. */ | |
adadcc0c | 314 | #define DS DQ + 1 |
b84bf58a AM |
315 | { 0xfffc, 0, NULL, NULL, |
316 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, | |
252b5132 | 317 | |
19a6653c AM |
318 | /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */ |
319 | #define DUIS DS + 1 | |
320 | { 0x3ff, 11, NULL, NULL, 0 }, | |
321 | ||
252b5132 | 322 | /* The E field in a wrteei instruction. */ |
c3d65c1c | 323 | /* And the W bit in the pair singles instructions. */ |
19a6653c | 324 | #define E DUIS + 1 |
c3d65c1c | 325 | #define PSW E |
b84bf58a | 326 | { 0x1, 15, NULL, NULL, 0 }, |
252b5132 RH |
327 | |
328 | /* The FL1 field in a POWER SC form instruction. */ | |
329 | #define FL1 E + 1 | |
717bbdf1 AM |
330 | /* The U field in an X form instruction. */ |
331 | #define U FL1 | |
b84bf58a | 332 | { 0xf, 12, NULL, NULL, 0 }, |
252b5132 RH |
333 | |
334 | /* The FL2 field in a POWER SC form instruction. */ | |
335 | #define FL2 FL1 + 1 | |
b84bf58a | 336 | { 0x7, 2, NULL, NULL, 0 }, |
252b5132 RH |
337 | |
338 | /* The FLM field in an XFL form instruction. */ | |
339 | #define FLM FL2 + 1 | |
b84bf58a | 340 | { 0xff, 17, NULL, NULL, 0 }, |
252b5132 RH |
341 | |
342 | /* The FRA field in an X or A form instruction. */ | |
343 | #define FRA FLM + 1 | |
344 | #define FRA_MASK (0x1f << 16) | |
b84bf58a | 345 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, |
252b5132 | 346 | |
989993d8 JB |
347 | /* The FRAp field of DFP instructions. */ |
348 | #define FRAp FRA + 1 | |
349 | { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, | |
350 | ||
252b5132 | 351 | /* The FRB field in an X or A form instruction. */ |
989993d8 | 352 | #define FRB FRAp + 1 |
252b5132 | 353 | #define FRB_MASK (0x1f << 11) |
b84bf58a | 354 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, |
252b5132 | 355 | |
989993d8 JB |
356 | /* The FRBp field of DFP instructions. */ |
357 | #define FRBp FRB + 1 | |
358 | { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, | |
359 | ||
252b5132 | 360 | /* The FRC field in an A form instruction. */ |
989993d8 | 361 | #define FRC FRBp + 1 |
252b5132 | 362 | #define FRC_MASK (0x1f << 6) |
b84bf58a | 363 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, |
252b5132 RH |
364 | |
365 | /* The FRS field in an X form instruction or the FRT field in a D, X | |
366 | or A form instruction. */ | |
367 | #define FRS FRC + 1 | |
368 | #define FRT FRS | |
b84bf58a | 369 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, |
252b5132 | 370 | |
989993d8 JB |
371 | /* The FRSp field of stfdp or the FRTp field of lfdp and DFP |
372 | instructions. */ | |
373 | #define FRSp FRS + 1 | |
374 | #define FRTp FRSp | |
375 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, | |
376 | ||
252b5132 | 377 | /* The FXM field in an XFX instruction. */ |
989993d8 | 378 | #define FXM FRSp + 1 |
b84bf58a | 379 | { 0xff, 12, insert_fxm, extract_fxm, 0 }, |
c168870a AM |
380 | |
381 | /* Power4 version for mfcr. */ | |
382 | #define FXM4 FXM + 1 | |
b84bf58a | 383 | { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, |
252b5132 | 384 | |
b9c361e0 JL |
385 | /* The IMM20 field in an LI instruction. */ |
386 | #define IMM20 FXM4 + 1 | |
387 | { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, | |
388 | ||
252b5132 | 389 | /* The L field in a D or X form instruction. */ |
b9c361e0 | 390 | #define L IMM20 + 1 |
5817ffd1 PB |
391 | /* The R field in a HTM X form instruction. */ |
392 | #define HTM_R L | |
b84bf58a | 393 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
252b5132 | 394 | |
1ed8e1e4 AM |
395 | /* The LEV field in a POWER SVC form instruction. */ |
396 | #define SVC_LEV L + 1 | |
b84bf58a | 397 | { 0x7f, 5, NULL, NULL, 0 }, |
252b5132 | 398 | |
1ed8e1e4 AM |
399 | /* The LEV field in an SC form instruction. */ |
400 | #define LEV SVC_LEV + 1 | |
b84bf58a | 401 | { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
1ed8e1e4 | 402 | |
252b5132 RH |
403 | /* The LI field in an I form instruction. The lower two bits are |
404 | forced to zero. */ | |
405 | #define LI LEV + 1 | |
b84bf58a | 406 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
252b5132 RH |
407 | |
408 | /* The LI field in an I form instruction when used as an absolute | |
409 | address. */ | |
410 | #define LIA LI + 1 | |
b84bf58a | 411 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
252b5132 | 412 | |
066be9f7 | 413 | /* The LS or WC field in an X (sync or wait) form instruction. */ |
6ba045b1 | 414 | #define LS LIA + 1 |
066be9f7 | 415 | #define WC LS |
b84bf58a | 416 | { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
6ba045b1 | 417 | |
252b5132 | 418 | /* The ME field in an M form instruction. */ |
717bbdf1 | 419 | #define ME LS + 1 |
252b5132 | 420 | #define ME_MASK (0x1f << 1) |
b84bf58a | 421 | { 0x1f, 1, NULL, NULL, 0 }, |
252b5132 RH |
422 | |
423 | /* The MB and ME fields in an M form instruction expressed a single | |
424 | operand which is a bitmask indicating which bits to select. This | |
425 | is a two operand form using PPC_OPERAND_NEXT. See the | |
426 | description in opcode/ppc.h for what this means. */ | |
427 | #define MBE ME + 1 | |
b84bf58a | 428 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
eb42fac1 | 429 | { -1, 0, insert_mbe, extract_mbe, 0 }, |
252b5132 RH |
430 | |
431 | /* The MB or ME field in an MD or MDS form instruction. The high | |
432 | bit is wrapped to the low end. */ | |
433 | #define MB6 MBE + 2 | |
434 | #define ME6 MB6 | |
435 | #define MB6_MASK (0x3f << 5) | |
b84bf58a | 436 | { 0x3f, 5, insert_mb6, extract_mb6, 0 }, |
252b5132 RH |
437 | |
438 | /* The NB field in an X form instruction. The value 32 is stored as | |
439 | 0. */ | |
717bbdf1 | 440 | #define NB MB6 + 1 |
b84bf58a | 441 | { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, |
252b5132 | 442 | |
989993d8 JB |
443 | /* The NBI field in an lswi instruction, which has special value |
444 | restrictions. The value 32 is stored as 0. */ | |
445 | #define NBI NB + 1 | |
446 | { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, | |
447 | ||
252b5132 RH |
448 | /* The NSI field in a D form instruction. This is the same as the |
449 | SI field, only negated. */ | |
989993d8 | 450 | #define NSI NBI + 1 |
b84bf58a | 451 | { 0xffff, 0, insert_nsi, extract_nsi, |
11b37b7b | 452 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
252b5132 | 453 | |
adadcc0c | 454 | /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
914749f6 | 455 | #define RA NSI + 1 |
252b5132 | 456 | #define RA_MASK (0x1f << 16) |
b84bf58a | 457 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, |
252b5132 | 458 | |
fdd12ef3 AM |
459 | /* As above, but 0 in the RA field means zero, not r0. */ |
460 | #define RA0 RA + 1 | |
b84bf58a | 461 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, |
fdd12ef3 | 462 | |
989993d8 | 463 | /* The RA field in the DQ form lq or an lswx instruction, which have special |
adadcc0c | 464 | value restrictions. */ |
fdd12ef3 | 465 | #define RAQ RA0 + 1 |
989993d8 | 466 | #define RAX RAQ |
b84bf58a | 467 | { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, |
adadcc0c | 468 | |
252b5132 RH |
469 | /* The RA field in a D or X form instruction which is an updating |
470 | load, which means that the RA field may not be zero and may not | |
471 | equal the RT field. */ | |
adadcc0c | 472 | #define RAL RAQ + 1 |
b84bf58a | 473 | { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, |
252b5132 RH |
474 | |
475 | /* The RA field in an lmw instruction, which has special value | |
476 | restrictions. */ | |
477 | #define RAM RAL + 1 | |
b84bf58a | 478 | { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, |
252b5132 RH |
479 | |
480 | /* The RA field in a D or X form instruction which is an updating | |
481 | store or an updating floating point load, which means that the RA | |
482 | field may not be zero. */ | |
483 | #define RAS RAM + 1 | |
b84bf58a | 484 | { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, |
252b5132 | 485 | |
cee62821 PB |
486 | /* The RA field of the tlbwe, dccci and iccci instructions, |
487 | which are optional. */ | |
fdd12ef3 | 488 | #define RAOPT RAS + 1 |
b84bf58a | 489 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
1f6c9eb0 | 490 | |
252b5132 | 491 | /* The RB field in an X, XO, M, or MDS form instruction. */ |
fdd12ef3 | 492 | #define RB RAOPT + 1 |
252b5132 | 493 | #define RB_MASK (0x1f << 11) |
b84bf58a | 494 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, |
252b5132 RH |
495 | |
496 | /* The RB field in an X form instruction when it must be the same as | |
497 | the RS field in the instruction. This is used for extended | |
498 | mnemonics like mr. */ | |
499 | #define RBS RB + 1 | |
b84bf58a | 500 | { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, |
252b5132 | 501 | |
989993d8 JB |
502 | /* The RB field in an lswx instruction, which has special value |
503 | restrictions. */ | |
504 | #define RBX RBS + 1 | |
505 | { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR }, | |
506 | ||
cee62821 | 507 | /* The RB field of the dccci and iccci instructions, which are optional. */ |
989993d8 | 508 | #define RBOPT RBX + 1 |
cee62821 PB |
509 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
510 | ||
252b5132 RH |
511 | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
512 | instruction or the RT field in a D, DS, X, XFX or XO form | |
513 | instruction. */ | |
cee62821 | 514 | #define RS RBOPT + 1 |
252b5132 RH |
515 | #define RT RS |
516 | #define RT_MASK (0x1f << 21) | |
b9c361e0 | 517 | #define RD RS |
b84bf58a | 518 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, |
252b5132 | 519 | |
588925d0 PB |
520 | /* The RS and RT fields of the DS form stq and DQ form lq instructions, |
521 | which have special value restrictions. */ | |
adadcc0c | 522 | #define RSQ RS + 1 |
717bbdf1 | 523 | #define RTQ RSQ |
588925d0 | 524 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, |
adadcc0c | 525 | |
1f6c9eb0 | 526 | /* The RS field of the tlbwe instruction, which is optional. */ |
717bbdf1 | 527 | #define RSO RSQ + 1 |
eed0d89a | 528 | #define RTO RSO |
b84bf58a | 529 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
1f6c9eb0 | 530 | |
b9c361e0 JL |
531 | /* The RX field of the SE_RR form instruction. */ |
532 | #define RX RSO + 1 | |
533 | { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, | |
534 | ||
535 | /* The ARX field of the SE_RR form instruction. */ | |
536 | #define ARX RX + 1 | |
537 | { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, | |
538 | ||
539 | /* The RY field of the SE_RR form instruction. */ | |
540 | #define RY ARX + 1 | |
541 | #define RZ RY | |
542 | { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, | |
543 | ||
544 | /* The ARY field of the SE_RR form instruction. */ | |
545 | #define ARY RY + 1 | |
546 | { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, | |
547 | ||
548 | /* The SCLSCI8 field in a D form instruction. */ | |
549 | #define SCLSCI8 ARY + 1 | |
550 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, | |
551 | ||
552 | /* The SCLSCI8N field in a D form instruction. This is the same as the | |
553 | SCLSCI8 field, only negated. */ | |
554 | #define SCLSCI8N SCLSCI8 + 1 | |
555 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, | |
556 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, | |
557 | ||
558 | /* The SD field of the SD4 form instruction. */ | |
559 | #define SE_SD SCLSCI8N + 1 | |
560 | { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, | |
561 | ||
562 | /* The SD field of the SD4 form instruction, for halfword. */ | |
563 | #define SE_SDH SE_SD + 1 | |
564 | { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, | |
565 | ||
566 | /* The SD field of the SD4 form instruction, for word. */ | |
567 | #define SE_SDW SE_SDH + 1 | |
568 | { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, | |
569 | ||
252b5132 | 570 | /* The SH field in an X or M form instruction. */ |
b9c361e0 | 571 | #define SH SE_SDW + 1 |
252b5132 | 572 | #define SH_MASK (0x1f << 11) |
717bbdf1 AM |
573 | /* The other UIMM field in a EVX form instruction. */ |
574 | #define EVUIMM SH | |
b84bf58a | 575 | { 0x1f, 11, NULL, NULL, 0 }, |
252b5132 | 576 | |
5817ffd1 PB |
577 | /* The SI field in a HTM X form instruction. */ |
578 | #define HTM_SI SH + 1 | |
579 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, | |
580 | ||
252b5132 | 581 | /* The SH field in an MD form instruction. This is split. */ |
5817ffd1 | 582 | #define SH6 HTM_SI + 1 |
252b5132 | 583 | #define SH6_MASK ((0x1f << 11) | (1 << 1)) |
b9c361e0 | 584 | { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, |
252b5132 | 585 | |
1f6c9eb0 ZW |
586 | /* The SH field of the tlbwe instruction, which is optional. */ |
587 | #define SHO SH6 + 1 | |
b84bf58a | 588 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
1f6c9eb0 | 589 | |
252b5132 | 590 | /* The SI field in a D form instruction. */ |
1f6c9eb0 | 591 | #define SI SHO + 1 |
b84bf58a | 592 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, |
252b5132 RH |
593 | |
594 | /* The SI field in a D form instruction when we accept a wide range | |
595 | of positive values. */ | |
596 | #define SISIGNOPT SI + 1 | |
b84bf58a | 597 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
252b5132 | 598 | |
b9c361e0 JL |
599 | /* The SI8 field in a D form instruction. */ |
600 | #define SI8 SISIGNOPT + 1 | |
601 | { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, | |
602 | ||
252b5132 RH |
603 | /* The SPR field in an XFX form instruction. This is flipped--the |
604 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
b9c361e0 | 605 | #define SPR SI8 + 1 |
914749f6 | 606 | #define PMR SPR |
aea77599 | 607 | #define TMR SPR |
252b5132 | 608 | #define SPR_MASK (0x3ff << 11) |
b84bf58a | 609 | { 0x3ff, 11, insert_spr, extract_spr, 0 }, |
252b5132 RH |
610 | |
611 | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ | |
612 | #define SPRBAT SPR + 1 | |
613 | #define SPRBAT_MASK (0x3 << 17) | |
b84bf58a | 614 | { 0x3, 17, NULL, NULL, 0 }, |
252b5132 RH |
615 | |
616 | /* The SPRG register number in an XFX form m[ft]sprg instruction. */ | |
617 | #define SPRG SPRBAT + 1 | |
b84bf58a | 618 | { 0x1f, 16, insert_sprg, extract_sprg, 0 }, |
252b5132 RH |
619 | |
620 | /* The SR field in an X form instruction. */ | |
621 | #define SR SPRG + 1 | |
fb048c26 PB |
622 | /* The 4-bit UIMM field in a VX form instruction. */ |
623 | #define UIMM4 SR | |
b84bf58a | 624 | { 0xf, 16, NULL, NULL, 0 }, |
252b5132 | 625 | |
f5c120c5 MG |
626 | /* The STRM field in an X AltiVec form instruction. */ |
627 | #define STRM SR + 1 | |
19a6653c AM |
628 | /* The T field in a tlbilx form instruction. */ |
629 | #define T STRM | |
b84bf58a | 630 | { 0x3, 21, NULL, NULL, 0 }, |
f5c120c5 | 631 | |
aea77599 AM |
632 | /* The ESYNC field in an X (sync) form instruction. */ |
633 | #define ESYNC STRM + 1 | |
634 | { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL }, | |
635 | ||
252b5132 | 636 | /* The SV field in a POWER SC form instruction. */ |
aea77599 | 637 | #define SV ESYNC + 1 |
b84bf58a | 638 | { 0x3fff, 2, NULL, NULL, 0 }, |
252b5132 RH |
639 | |
640 | /* The TBR field in an XFX form instruction. This is like the SPR | |
641 | field, but it is optional. */ | |
642 | #define TBR SV + 1 | |
b84bf58a | 643 | { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, |
252b5132 RH |
644 | |
645 | /* The TO field in a D or X form instruction. */ | |
646 | #define TO TBR + 1 | |
19a6653c | 647 | #define DUI TO |
252b5132 | 648 | #define TO_MASK (0x1f << 21) |
b84bf58a | 649 | { 0x1f, 21, NULL, NULL, 0 }, |
252b5132 | 650 | |
252b5132 | 651 | /* The UI field in a D form instruction. */ |
717bbdf1 | 652 | #define UI TO + 1 |
b84bf58a | 653 | { 0xffff, 0, NULL, NULL, 0 }, |
786e2c0f | 654 | |
b9c361e0 JL |
655 | /* The IMM field in an SE_IM5 instruction. */ |
656 | #define UI5 UI + 1 | |
657 | { 0x1f, 4, NULL, NULL, 0 }, | |
658 | ||
659 | /* The OIMM field in an SE_OIM5 instruction. */ | |
660 | #define OIMM5 UI5 + 1 | |
661 | { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, | |
662 | ||
663 | /* The UI7 field in an SE_LI instruction. */ | |
664 | #define UI7 OIMM5 + 1 | |
665 | { 0x7f, 4, NULL, NULL, 0 }, | |
666 | ||
112290ab | 667 | /* The VA field in a VA, VX or VXR form instruction. */ |
b9c361e0 | 668 | #define VA UI7 + 1 |
b84bf58a | 669 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, |
786e2c0f | 670 | |
112290ab | 671 | /* The VB field in a VA, VX or VXR form instruction. */ |
786e2c0f | 672 | #define VB VA + 1 |
b84bf58a | 673 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, |
786e2c0f | 674 | |
112290ab | 675 | /* The VC field in a VA form instruction. */ |
786e2c0f | 676 | #define VC VB + 1 |
b84bf58a | 677 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, |
786e2c0f | 678 | |
112290ab | 679 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
786e2c0f C |
680 | #define VD VC + 1 |
681 | #define VS VD | |
b84bf58a | 682 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, |
786e2c0f | 683 | |
8dbcd839 | 684 | /* The SIMM field in a VX form instruction, and TE in Z form. */ |
786e2c0f | 685 | #define SIMM VD + 1 |
8dbcd839 | 686 | #define TE SIMM |
b84bf58a | 687 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, |
786e2c0f | 688 | |
8dbcd839 | 689 | /* The UIMM field in a VX form instruction. */ |
786e2c0f | 690 | #define UIMM SIMM + 1 |
aea77599 | 691 | #define DCTL UIMM |
b84bf58a | 692 | { 0x1f, 16, NULL, NULL, 0 }, |
786e2c0f | 693 | |
fb048c26 PB |
694 | /* The 3-bit UIMM field in a VX form instruction. */ |
695 | #define UIMM3 UIMM + 1 | |
696 | { 0x7, 16, NULL, NULL, 0 }, | |
697 | ||
112290ab | 698 | /* The SHB field in a VA form instruction. */ |
fb048c26 | 699 | #define SHB UIMM3 + 1 |
b84bf58a | 700 | { 0xf, 6, NULL, NULL, 0 }, |
ff3a6ee3 | 701 | |
112290ab | 702 | /* The other UIMM field in a half word EVX form instruction. */ |
717bbdf1 | 703 | #define EVUIMM_2 SHB + 1 |
b84bf58a | 704 | { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
23976049 | 705 | |
112290ab | 706 | /* The other UIMM field in a word EVX form instruction. */ |
23976049 | 707 | #define EVUIMM_4 EVUIMM_2 + 1 |
b84bf58a | 708 | { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, |
23976049 | 709 | |
112290ab | 710 | /* The other UIMM field in a double EVX form instruction. */ |
23976049 | 711 | #define EVUIMM_8 EVUIMM_4 + 1 |
b84bf58a | 712 | { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
23976049 | 713 | |
ff3a6ee3 | 714 | /* The WS field. */ |
23976049 | 715 | #define WS EVUIMM_8 + 1 |
b84bf58a | 716 | { 0x7, 11, NULL, NULL, 0 }, |
ff3a6ee3 | 717 | |
c3d65c1c BE |
718 | /* PowerPC paired singles extensions. */ |
719 | /* W bit in the pair singles instructions for x type instructions. */ | |
720 | #define PSWM WS + 1 | |
b9c361e0 JL |
721 | /* The BO16 field in a BD8 form instruction. */ |
722 | #define BO16 PSWM | |
c3d65c1c BE |
723 | { 0x1, 10, 0, 0, 0 }, |
724 | ||
725 | /* IDX bits for quantization in the pair singles instructions. */ | |
726 | #define PSQ PSWM + 1 | |
727 | { 0x7, 12, 0, 0, 0 }, | |
728 | ||
729 | /* IDX bits for quantization in the pair singles x-type instructions. */ | |
730 | #define PSQM PSQ + 1 | |
731 | { 0x7, 7, 0, 0, 0 }, | |
732 | ||
733 | /* Smaller D field for quantization in the pair singles instructions. */ | |
734 | #define PSD PSQM + 1 | |
735 | { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
736 | ||
737 | #define A_L PSD + 1 | |
ea192fa3 | 738 | #define W A_L |
c3d65c1c | 739 | #define MTMSRD_L W |
b84bf58a | 740 | { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
5ae2e65e | 741 | |
c3d65c1c | 742 | #define RMC MTMSRD_L + 1 |
b84bf58a | 743 | { 0x3, 9, NULL, NULL, 0 }, |
702f0fb4 PB |
744 | |
745 | #define R RMC + 1 | |
b84bf58a | 746 | { 0x1, 16, NULL, NULL, 0 }, |
702f0fb4 PB |
747 | |
748 | #define SP R + 1 | |
b84bf58a | 749 | { 0x3, 19, NULL, NULL, 0 }, |
702f0fb4 PB |
750 | |
751 | #define S SP + 1 | |
b84bf58a | 752 | { 0x1, 20, NULL, NULL, 0 }, |
702f0fb4 PB |
753 | |
754 | /* SH field starting at bit position 16. */ | |
755 | #define SH16 S + 1 | |
0bbdef92 AM |
756 | /* The DCM and DGM fields in a Z form instruction. */ |
757 | #define DCM SH16 | |
758 | #define DGM DCM | |
b84bf58a | 759 | { 0x3f, 10, NULL, NULL, 0 }, |
702f0fb4 | 760 | |
702f0fb4 | 761 | /* The EH field in larx instruction. */ |
717bbdf1 | 762 | #define EH SH16 + 1 |
b84bf58a | 763 | { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
ea192fa3 PB |
764 | |
765 | /* The L field in an mtfsf or XFL form instruction. */ | |
5817ffd1 | 766 | /* The A field in a HTM X form instruction. */ |
ea192fa3 | 767 | #define XFL_L EH + 1 |
5817ffd1 | 768 | #define HTM_A XFL_L |
ea192fa3 | 769 | { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, |
081ba1b3 AM |
770 | |
771 | /* Xilinx APU related masks and macros */ | |
772 | #define FCRT XFL_L + 1 | |
773 | #define FCRT_MASK (0x1f << 21) | |
774 | { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, | |
775 | ||
776 | /* Xilinx FSL related masks and macros */ | |
777 | #define FSL FCRT + 1 | |
778 | #define FSL_MASK (0x1f << 11) | |
779 | { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, | |
780 | ||
781 | /* Xilinx UDI related masks and macros */ | |
782 | #define URT FSL + 1 | |
783 | { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, | |
784 | ||
785 | #define URA URT + 1 | |
786 | { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, | |
787 | ||
788 | #define URB URA + 1 | |
789 | { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, | |
790 | ||
791 | #define URC URB + 1 | |
792 | { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, | |
793 | ||
b9c361e0 JL |
794 | /* The VLESIMM field in a D form instruction. */ |
795 | #define VLESIMM URC + 1 | |
796 | { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, | |
797 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
798 | ||
799 | /* The VLENSIMM field in a D form instruction. */ | |
800 | #define VLENSIMM VLESIMM + 1 | |
801 | { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, | |
802 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
803 | ||
804 | /* The VLEUIMM field in a D form instruction. */ | |
805 | #define VLEUIMM VLENSIMM + 1 | |
806 | { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, | |
807 | ||
808 | /* The VLEUIMML field in a D form instruction. */ | |
809 | #define VLEUIMML VLEUIMM + 1 | |
810 | { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, | |
811 | ||
9b4e5766 | 812 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
b9c361e0 | 813 | #define XS6 VLEUIMML + 1 |
9b4e5766 | 814 | #define XT6 XS6 |
b9c361e0 | 815 | { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, |
9b4e5766 PB |
816 | |
817 | /* The XA field in an XX3 form instruction. This is split. */ | |
818 | #define XA6 XT6 + 1 | |
b9c361e0 | 819 | { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, |
9b4e5766 | 820 | |
066be9f7 | 821 | /* The XB field in an XX2 or XX3 form instruction. This is split. */ |
9b4e5766 | 822 | #define XB6 XA6 + 1 |
b9c361e0 | 823 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, |
9b4e5766 PB |
824 | |
825 | /* The XB field in an XX3 form instruction when it must be the same as | |
826 | the XA field in the instruction. This is used in extended mnemonics | |
827 | like xvmovdp. This is split. */ | |
828 | #define XB6S XB6 + 1 | |
b9c361e0 | 829 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, |
9b4e5766 | 830 | |
066be9f7 PB |
831 | /* The XC field in an XX4 form instruction. This is split. */ |
832 | #define XC6 XB6S + 1 | |
b9c361e0 | 833 | { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, |
066be9f7 PB |
834 | |
835 | /* The DM or SHW field in an XX3 form instruction. */ | |
836 | #define DM XC6 + 1 | |
837 | #define SHW DM | |
9b4e5766 | 838 | { 0x3, 8, NULL, NULL, 0 }, |
066be9f7 PB |
839 | |
840 | /* The DM field in an extended mnemonic XX3 form instruction. */ | |
841 | #define DMEX DM + 1 | |
842 | { 0x3, 8, insert_dm, extract_dm, 0 }, | |
843 | ||
844 | /* The UIM field in an XX2 form instruction. */ | |
845 | #define UIM DMEX + 1 | |
fb048c26 PB |
846 | /* The 2-bit UIMM field in a VX form instruction. */ |
847 | #define UIMM2 UIM | |
066be9f7 | 848 | { 0x3, 16, NULL, NULL, 0 }, |
e0d602ec BE |
849 | |
850 | #define ERAT_T UIM + 1 | |
851 | { 0x7, 21, NULL, NULL, 0 }, | |
252b5132 RH |
852 | }; |
853 | ||
b84bf58a AM |
854 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) |
855 | / sizeof (powerpc_operands[0])); | |
856 | ||
252b5132 RH |
857 | /* The functions used to insert and extract complicated operands. */ |
858 | ||
b9c361e0 JL |
859 | /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ |
860 | ||
861 | static unsigned long | |
862 | insert_arx (unsigned long insn, | |
863 | long value, | |
864 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
865 | const char **errmsg ATTRIBUTE_UNUSED) | |
866 | { | |
867 | if (value >= 8 && value < 24) | |
868 | return insn | ((value - 8) & 0xf); | |
869 | else | |
870 | { | |
871 | *errmsg = _("invalid register"); | |
872 | return 0; | |
873 | } | |
874 | } | |
875 | ||
876 | static long | |
877 | extract_arx (unsigned long insn, | |
878 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
879 | int *invalid ATTRIBUTE_UNUSED) | |
880 | { | |
881 | return (insn & 0xf) + 8; | |
882 | } | |
883 | ||
884 | static unsigned long | |
885 | insert_ary (unsigned long insn, | |
886 | long value, | |
887 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
888 | const char **errmsg ATTRIBUTE_UNUSED) | |
889 | { | |
890 | if (value >= 8 && value < 24) | |
891 | return insn | (((value - 8) & 0xf) << 4); | |
892 | else | |
893 | { | |
894 | *errmsg = _("invalid register"); | |
895 | return 0; | |
896 | } | |
897 | } | |
898 | ||
899 | static long | |
900 | extract_ary (unsigned long insn, | |
901 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
902 | int *invalid ATTRIBUTE_UNUSED) | |
903 | { | |
904 | return ((insn >> 4) & 0xf) + 8; | |
905 | } | |
906 | ||
907 | static unsigned long | |
908 | insert_rx (unsigned long insn, | |
909 | long value, | |
910 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
911 | const char **errmsg) | |
912 | { | |
913 | if (value >= 0 && value < 8) | |
914 | return insn | value; | |
915 | else if (value >= 24 && value <= 31) | |
916 | return insn | (value - 16); | |
917 | else | |
918 | { | |
919 | *errmsg = _("invalid register"); | |
920 | return 0; | |
921 | } | |
922 | } | |
923 | ||
924 | static long | |
925 | extract_rx (unsigned long insn, | |
926 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
927 | int *invalid ATTRIBUTE_UNUSED) | |
928 | { | |
929 | int value = insn & 0xf; | |
930 | if (value >= 0 && value < 8) | |
931 | return value; | |
932 | else | |
933 | return value + 16; | |
934 | } | |
935 | ||
936 | static unsigned long | |
937 | insert_ry (unsigned long insn, | |
938 | long value, | |
939 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
940 | const char **errmsg) | |
941 | { | |
942 | if (value >= 0 && value < 8) | |
943 | return insn | (value << 4); | |
944 | else if (value >= 24 && value <= 31) | |
945 | return insn | ((value - 16) << 4); | |
946 | else | |
947 | { | |
948 | *errmsg = _("invalid register"); | |
949 | return 0; | |
950 | } | |
951 | } | |
952 | ||
953 | static long | |
954 | extract_ry (unsigned long insn, | |
955 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
956 | int *invalid ATTRIBUTE_UNUSED) | |
957 | { | |
958 | int value = (insn >> 4) & 0xf; | |
959 | if (value >= 0 && value < 8) | |
960 | return value; | |
961 | else | |
962 | return value + 16; | |
963 | } | |
964 | ||
252b5132 RH |
965 | /* The BA field in an XL form instruction when it must be the same as |
966 | the BT field in the same instruction. This operand is marked FAKE. | |
967 | The insertion function just copies the BT field into the BA field, | |
968 | and the extraction function just checks that the fields are the | |
969 | same. */ | |
970 | ||
252b5132 | 971 | static unsigned long |
2fbfdc41 AM |
972 | insert_bat (unsigned long insn, |
973 | long value ATTRIBUTE_UNUSED, | |
fa452fa6 | 974 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 975 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 RH |
976 | { |
977 | return insn | (((insn >> 21) & 0x1f) << 16); | |
978 | } | |
979 | ||
980 | static long | |
2fbfdc41 | 981 | extract_bat (unsigned long insn, |
fa452fa6 | 982 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 983 | int *invalid) |
252b5132 | 984 | { |
8427c424 | 985 | if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) |
252b5132 RH |
986 | *invalid = 1; |
987 | return 0; | |
988 | } | |
989 | ||
990 | /* The BB field in an XL form instruction when it must be the same as | |
991 | the BA field in the same instruction. This operand is marked FAKE. | |
992 | The insertion function just copies the BA field into the BB field, | |
993 | and the extraction function just checks that the fields are the | |
994 | same. */ | |
995 | ||
252b5132 | 996 | static unsigned long |
2fbfdc41 AM |
997 | insert_bba (unsigned long insn, |
998 | long value ATTRIBUTE_UNUSED, | |
fa452fa6 | 999 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1000 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 RH |
1001 | { |
1002 | return insn | (((insn >> 16) & 0x1f) << 11); | |
1003 | } | |
1004 | ||
1005 | static long | |
2fbfdc41 | 1006 | extract_bba (unsigned long insn, |
fa452fa6 | 1007 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1008 | int *invalid) |
252b5132 | 1009 | { |
8427c424 | 1010 | if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
252b5132 RH |
1011 | *invalid = 1; |
1012 | return 0; | |
1013 | } | |
1014 | ||
252b5132 RH |
1015 | /* The BD field in a B form instruction when the - modifier is used. |
1016 | This modifier means that the branch is not expected to be taken. | |
94efba12 AM |
1017 | For chips built to versions of the architecture prior to version 2 |
1018 | (ie. not Power4 compatible), we set the y bit of the BO field to 1 | |
1019 | if the offset is negative. When extracting, we require that the y | |
1020 | bit be 1 and that the offset be positive, since if the y bit is 0 | |
1021 | we just want to print the normal form of the instruction. | |
1022 | Power4 compatible targets use two bits, "a", and "t", instead of | |
1023 | the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, | |
1024 | "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 | |
1025 | in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 | |
ba4e851b AM |
1026 | for branch on CTR. We only handle the taken/not-taken hint here. |
1027 | Note that we don't relax the conditions tested here when | |
1028 | disassembling with -Many because insns using extract_bdm and | |
1029 | extract_bdp always occur in pairs. One or the other will always | |
1030 | be valid. */ | |
252b5132 | 1031 | |
8ebac3aa AM |
1032 | #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
1033 | ||
252b5132 | 1034 | static unsigned long |
2fbfdc41 AM |
1035 | insert_bdm (unsigned long insn, |
1036 | long value, | |
fa452fa6 | 1037 | ppc_cpu_t dialect, |
2fbfdc41 | 1038 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 | 1039 | { |
8ebac3aa | 1040 | if ((dialect & ISA_V2) == 0) |
802a735e AM |
1041 | { |
1042 | if ((value & 0x8000) != 0) | |
1043 | insn |= 1 << 21; | |
1044 | } | |
1045 | else | |
1046 | { | |
1047 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
1048 | insn |= 0x02 << 21; | |
1049 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
1050 | insn |= 0x08 << 21; | |
1051 | } | |
252b5132 RH |
1052 | return insn | (value & 0xfffc); |
1053 | } | |
1054 | ||
1055 | static long | |
2fbfdc41 | 1056 | extract_bdm (unsigned long insn, |
fa452fa6 | 1057 | ppc_cpu_t dialect, |
2fbfdc41 | 1058 | int *invalid) |
252b5132 | 1059 | { |
8ebac3aa | 1060 | if ((dialect & ISA_V2) == 0) |
802a735e | 1061 | { |
8427c424 AM |
1062 | if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) |
1063 | *invalid = 1; | |
802a735e | 1064 | } |
8427c424 AM |
1065 | else |
1066 | { | |
1067 | if ((insn & (0x17 << 21)) != (0x06 << 21) | |
1068 | && (insn & (0x1d << 21)) != (0x18 << 21)) | |
1069 | *invalid = 1; | |
1070 | } | |
1071 | ||
802a735e | 1072 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
252b5132 RH |
1073 | } |
1074 | ||
1075 | /* The BD field in a B form instruction when the + modifier is used. | |
1076 | This is like BDM, above, except that the branch is expected to be | |
1077 | taken. */ | |
1078 | ||
252b5132 | 1079 | static unsigned long |
2fbfdc41 AM |
1080 | insert_bdp (unsigned long insn, |
1081 | long value, | |
fa452fa6 | 1082 | ppc_cpu_t dialect, |
2fbfdc41 | 1083 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 | 1084 | { |
8ebac3aa | 1085 | if ((dialect & ISA_V2) == 0) |
802a735e AM |
1086 | { |
1087 | if ((value & 0x8000) == 0) | |
1088 | insn |= 1 << 21; | |
1089 | } | |
1090 | else | |
1091 | { | |
1092 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
1093 | insn |= 0x03 << 21; | |
1094 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
1095 | insn |= 0x09 << 21; | |
1096 | } | |
252b5132 RH |
1097 | return insn | (value & 0xfffc); |
1098 | } | |
1099 | ||
1100 | static long | |
2fbfdc41 | 1101 | extract_bdp (unsigned long insn, |
fa452fa6 | 1102 | ppc_cpu_t dialect, |
2fbfdc41 | 1103 | int *invalid) |
252b5132 | 1104 | { |
8ebac3aa | 1105 | if ((dialect & ISA_V2) == 0) |
802a735e | 1106 | { |
8427c424 AM |
1107 | if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) |
1108 | *invalid = 1; | |
1109 | } | |
1110 | else | |
1111 | { | |
1112 | if ((insn & (0x17 << 21)) != (0x07 << 21) | |
1113 | && (insn & (0x1d << 21)) != (0x19 << 21)) | |
1114 | *invalid = 1; | |
802a735e | 1115 | } |
8427c424 | 1116 | |
802a735e | 1117 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
252b5132 RH |
1118 | } |
1119 | ||
8ebac3aa AM |
1120 | static inline int |
1121 | valid_bo_pre_v2 (long value) | |
252b5132 | 1122 | { |
8ebac3aa AM |
1123 | /* Certain encodings have bits that are required to be zero. |
1124 | These are (z must be zero, y may be anything): | |
1125 | 0000y | |
1126 | 0001y | |
1127 | 001zy | |
1128 | 0100y | |
1129 | 0101y | |
1130 | 011zy | |
1131 | 1z00y | |
1132 | 1z01y | |
1133 | 1z1zz | |
1134 | */ | |
1135 | if ((value & 0x14) == 0) | |
1136 | return 1; | |
1137 | else if ((value & 0x14) == 0x4) | |
1138 | return (value & 0x2) == 0; | |
1139 | else if ((value & 0x14) == 0x10) | |
1140 | return (value & 0x8) == 0; | |
1141 | else | |
1142 | return value == 0x14; | |
1143 | } | |
ba4e851b | 1144 | |
8ebac3aa AM |
1145 | static inline int |
1146 | valid_bo_post_v2 (long value) | |
1147 | { | |
ba4e851b AM |
1148 | /* Certain encodings have bits that are required to be zero. |
1149 | These are (z must be zero, a & t may be anything): | |
1150 | 0000z | |
1151 | 0001z | |
8ebac3aa | 1152 | 001at |
ba4e851b AM |
1153 | 0100z |
1154 | 0101z | |
ba4e851b AM |
1155 | 011at |
1156 | 1a00t | |
1157 | 1a01t | |
1158 | 1z1zz | |
1159 | */ | |
1160 | if ((value & 0x14) == 0) | |
1161 | return (value & 0x1) == 0; | |
1162 | else if ((value & 0x14) == 0x14) | |
1163 | return value == 0x14; | |
802a735e | 1164 | else |
ba4e851b | 1165 | return 1; |
252b5132 RH |
1166 | } |
1167 | ||
8ebac3aa AM |
1168 | /* Check for legal values of a BO field. */ |
1169 | ||
1170 | static int | |
1171 | valid_bo (long value, ppc_cpu_t dialect, int extract) | |
1172 | { | |
1173 | int valid_y = valid_bo_pre_v2 (value); | |
1174 | int valid_at = valid_bo_post_v2 (value); | |
1175 | ||
1176 | /* When disassembling with -Many, accept either encoding on the | |
1177 | second pass through opcodes. */ | |
1178 | if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) | |
1179 | return valid_y || valid_at; | |
1180 | if ((dialect & ISA_V2) == 0) | |
1181 | return valid_y; | |
1182 | else | |
1183 | return valid_at; | |
1184 | } | |
1185 | ||
252b5132 RH |
1186 | /* The BO field in a B form instruction. Warn about attempts to set |
1187 | the field to an illegal value. */ | |
1188 | ||
1189 | static unsigned long | |
2fbfdc41 AM |
1190 | insert_bo (unsigned long insn, |
1191 | long value, | |
fa452fa6 | 1192 | ppc_cpu_t dialect, |
2fbfdc41 | 1193 | const char **errmsg) |
252b5132 | 1194 | { |
ba4e851b | 1195 | if (!valid_bo (value, dialect, 0)) |
252b5132 | 1196 | *errmsg = _("invalid conditional option"); |
989993d8 JB |
1197 | else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) |
1198 | *errmsg = _("invalid counter access"); | |
252b5132 RH |
1199 | return insn | ((value & 0x1f) << 21); |
1200 | } | |
1201 | ||
1202 | static long | |
2fbfdc41 | 1203 | extract_bo (unsigned long insn, |
fa452fa6 | 1204 | ppc_cpu_t dialect, |
2fbfdc41 | 1205 | int *invalid) |
252b5132 RH |
1206 | { |
1207 | long value; | |
1208 | ||
1209 | value = (insn >> 21) & 0x1f; | |
ba4e851b | 1210 | if (!valid_bo (value, dialect, 1)) |
252b5132 RH |
1211 | *invalid = 1; |
1212 | return value; | |
1213 | } | |
1214 | ||
1215 | /* The BO field in a B form instruction when the + or - modifier is | |
1216 | used. This is like the BO field, but it must be even. When | |
1217 | extracting it, we force it to be even. */ | |
1218 | ||
1219 | static unsigned long | |
2fbfdc41 AM |
1220 | insert_boe (unsigned long insn, |
1221 | long value, | |
fa452fa6 | 1222 | ppc_cpu_t dialect, |
2fbfdc41 | 1223 | const char **errmsg) |
252b5132 | 1224 | { |
ba4e851b | 1225 | if (!valid_bo (value, dialect, 0)) |
8427c424 | 1226 | *errmsg = _("invalid conditional option"); |
989993d8 JB |
1227 | else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) |
1228 | *errmsg = _("invalid counter access"); | |
8427c424 AM |
1229 | else if ((value & 1) != 0) |
1230 | *errmsg = _("attempt to set y bit when using + or - modifier"); | |
1231 | ||
252b5132 RH |
1232 | return insn | ((value & 0x1f) << 21); |
1233 | } | |
1234 | ||
1235 | static long | |
2fbfdc41 | 1236 | extract_boe (unsigned long insn, |
fa452fa6 | 1237 | ppc_cpu_t dialect, |
2fbfdc41 | 1238 | int *invalid) |
252b5132 RH |
1239 | { |
1240 | long value; | |
1241 | ||
1242 | value = (insn >> 21) & 0x1f; | |
ba4e851b | 1243 | if (!valid_bo (value, dialect, 1)) |
252b5132 RH |
1244 | *invalid = 1; |
1245 | return value & 0x1e; | |
1246 | } | |
1247 | ||
2fbfdc41 AM |
1248 | /* FXM mask in mfcr and mtcrf instructions. */ |
1249 | ||
1250 | static unsigned long | |
1251 | insert_fxm (unsigned long insn, | |
1252 | long value, | |
fa452fa6 | 1253 | ppc_cpu_t dialect, |
2fbfdc41 | 1254 | const char **errmsg) |
c168870a | 1255 | { |
98e69875 AM |
1256 | /* If we're handling the mfocrf and mtocrf insns ensure that exactly |
1257 | one bit of the mask field is set. */ | |
1258 | if ((insn & (1 << 20)) != 0) | |
1259 | { | |
1260 | if (value == 0 || (value & -value) != value) | |
1261 | { | |
1262 | *errmsg = _("invalid mask field"); | |
1263 | value = 0; | |
1264 | } | |
1265 | } | |
1266 | ||
c168870a AM |
1267 | /* If the optional field on mfcr is missing that means we want to use |
1268 | the old form of the instruction that moves the whole cr. In that | |
1269 | case we'll have VALUE zero. There doesn't seem to be a way to | |
1270 | distinguish this from the case where someone writes mfcr %r3,0. */ | |
98e69875 | 1271 | else if (value == 0) |
c168870a AM |
1272 | ; |
1273 | ||
1274 | /* If only one bit of the FXM field is set, we can use the new form | |
661bd698 | 1275 | of the instruction, which is faster. Unlike the Power4 branch hint |
a30e9cc4 AM |
1276 | encoding, this is not backward compatible. Do not generate the |
1277 | new form unless -mpower4 has been given, or -many and the two | |
1278 | operand form of mfcr was used. */ | |
1279 | else if ((value & -value) == value | |
1280 | && ((dialect & PPC_OPCODE_POWER4) != 0 | |
1281 | || ((dialect & PPC_OPCODE_ANY) != 0 | |
1282 | && (insn & (0x3ff << 1)) == 19 << 1))) | |
c168870a AM |
1283 | insn |= 1 << 20; |
1284 | ||
1285 | /* Any other value on mfcr is an error. */ | |
1286 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
1287 | { | |
8427c424 | 1288 | *errmsg = _("ignoring invalid mfcr mask"); |
c168870a AM |
1289 | value = 0; |
1290 | } | |
1291 | ||
1292 | return insn | ((value & 0xff) << 12); | |
1293 | } | |
1294 | ||
2fbfdc41 AM |
1295 | static long |
1296 | extract_fxm (unsigned long insn, | |
fa452fa6 | 1297 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1298 | int *invalid) |
c168870a AM |
1299 | { |
1300 | long mask = (insn >> 12) & 0xff; | |
1301 | ||
1302 | /* Is this a Power4 insn? */ | |
1303 | if ((insn & (1 << 20)) != 0) | |
1304 | { | |
98e69875 AM |
1305 | /* Exactly one bit of MASK should be set. */ |
1306 | if (mask == 0 || (mask & -mask) != mask) | |
8427c424 | 1307 | *invalid = 1; |
c168870a AM |
1308 | } |
1309 | ||
1310 | /* Check that non-power4 form of mfcr has a zero MASK. */ | |
1311 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
1312 | { | |
8427c424 | 1313 | if (mask != 0) |
c168870a AM |
1314 | *invalid = 1; |
1315 | } | |
1316 | ||
1317 | return mask; | |
1318 | } | |
1319 | ||
b9c361e0 JL |
1320 | static unsigned long |
1321 | insert_li20 (unsigned long insn, | |
1322 | long value, | |
1323 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1324 | const char **errmsg ATTRIBUTE_UNUSED) | |
1325 | { | |
1326 | return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff); | |
1327 | } | |
1328 | ||
1329 | static long | |
1330 | extract_li20 (unsigned long insn, | |
1331 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1332 | int *invalid ATTRIBUTE_UNUSED) | |
1333 | { | |
1334 | long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000; | |
1335 | ||
1336 | return ext | |
1337 | | (((insn >> 11) & 0xf) << 16) | |
1338 | | (((insn >> 17) & 0xf) << 12) | |
1339 | | (((insn >> 16) & 0x1) << 11) | |
1340 | | (insn & 0x7ff); | |
1341 | } | |
1342 | ||
aea77599 AM |
1343 | /* The LS field in a sync instruction that accepts 2 operands |
1344 | Values 2 and 3 are reserved, | |
1345 | must be treated as 0 for future compatibility | |
1346 | Values 0 and 1 can be accepted, if field ESYNC is zero | |
1347 | Otherwise L = complement of ESYNC-bit2 (1<<18) */ | |
1348 | ||
1349 | static unsigned long | |
1350 | insert_ls (unsigned long insn, | |
1351 | long value, | |
1352 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1353 | const char **errmsg ATTRIBUTE_UNUSED) | |
1354 | { | |
1355 | unsigned long ls; | |
1356 | ||
1357 | ls = (insn >> 21) & 0x03; | |
1358 | if (value == 0) | |
1359 | { | |
1360 | if (ls > 1) | |
1361 | return insn & ~(0x3 << 21); | |
1362 | return insn; | |
1363 | } | |
1364 | if ((value & 0x2) != 0) | |
1365 | return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16); | |
1366 | return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16); | |
1367 | } | |
1368 | ||
252b5132 RH |
1369 | /* The MB and ME fields in an M form instruction expressed as a single |
1370 | operand which is itself a bitmask. The extraction function always | |
1371 | marks it as invalid, since we never want to recognize an | |
1372 | instruction which uses a field of this type. */ | |
1373 | ||
1374 | static unsigned long | |
2fbfdc41 AM |
1375 | insert_mbe (unsigned long insn, |
1376 | long value, | |
fa452fa6 | 1377 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1378 | const char **errmsg) |
252b5132 RH |
1379 | { |
1380 | unsigned long uval, mask; | |
1381 | int mb, me, mx, count, last; | |
1382 | ||
1383 | uval = value; | |
1384 | ||
1385 | if (uval == 0) | |
1386 | { | |
8427c424 | 1387 | *errmsg = _("illegal bitmask"); |
252b5132 RH |
1388 | return insn; |
1389 | } | |
1390 | ||
1391 | mb = 0; | |
1392 | me = 32; | |
1393 | if ((uval & 1) != 0) | |
1394 | last = 1; | |
1395 | else | |
1396 | last = 0; | |
1397 | count = 0; | |
1398 | ||
1399 | /* mb: location of last 0->1 transition */ | |
1400 | /* me: location of last 1->0 transition */ | |
1401 | /* count: # transitions */ | |
1402 | ||
0deb7ac5 | 1403 | for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) |
252b5132 RH |
1404 | { |
1405 | if ((uval & mask) && !last) | |
1406 | { | |
1407 | ++count; | |
1408 | mb = mx; | |
1409 | last = 1; | |
1410 | } | |
1411 | else if (!(uval & mask) && last) | |
1412 | { | |
1413 | ++count; | |
1414 | me = mx; | |
1415 | last = 0; | |
1416 | } | |
1417 | } | |
1418 | if (me == 0) | |
1419 | me = 32; | |
1420 | ||
1421 | if (count != 2 && (count != 0 || ! last)) | |
8427c424 | 1422 | *errmsg = _("illegal bitmask"); |
252b5132 RH |
1423 | |
1424 | return insn | (mb << 6) | ((me - 1) << 1); | |
1425 | } | |
1426 | ||
1427 | static long | |
2fbfdc41 | 1428 | extract_mbe (unsigned long insn, |
fa452fa6 | 1429 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1430 | int *invalid) |
252b5132 RH |
1431 | { |
1432 | long ret; | |
1433 | int mb, me; | |
1434 | int i; | |
1435 | ||
8427c424 | 1436 | *invalid = 1; |
252b5132 RH |
1437 | |
1438 | mb = (insn >> 6) & 0x1f; | |
1439 | me = (insn >> 1) & 0x1f; | |
1440 | if (mb < me + 1) | |
1441 | { | |
1442 | ret = 0; | |
1443 | for (i = mb; i <= me; i++) | |
0deb7ac5 | 1444 | ret |= 1L << (31 - i); |
252b5132 RH |
1445 | } |
1446 | else if (mb == me + 1) | |
8427c424 | 1447 | ret = ~0; |
252b5132 RH |
1448 | else /* (mb > me + 1) */ |
1449 | { | |
2fbfdc41 | 1450 | ret = ~0; |
252b5132 | 1451 | for (i = me + 1; i < mb; i++) |
0deb7ac5 | 1452 | ret &= ~(1L << (31 - i)); |
252b5132 RH |
1453 | } |
1454 | return ret; | |
1455 | } | |
1456 | ||
1457 | /* The MB or ME field in an MD or MDS form instruction. The high bit | |
1458 | is wrapped to the low end. */ | |
1459 | ||
252b5132 | 1460 | static unsigned long |
2fbfdc41 AM |
1461 | insert_mb6 (unsigned long insn, |
1462 | long value, | |
fa452fa6 | 1463 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1464 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 RH |
1465 | { |
1466 | return insn | ((value & 0x1f) << 6) | (value & 0x20); | |
1467 | } | |
1468 | ||
252b5132 | 1469 | static long |
2fbfdc41 | 1470 | extract_mb6 (unsigned long insn, |
fa452fa6 | 1471 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1472 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 RH |
1473 | { |
1474 | return ((insn >> 6) & 0x1f) | (insn & 0x20); | |
1475 | } | |
1476 | ||
1477 | /* The NB field in an X form instruction. The value 32 is stored as | |
1478 | 0. */ | |
1479 | ||
252b5132 | 1480 | static long |
2fbfdc41 | 1481 | extract_nb (unsigned long insn, |
fa452fa6 | 1482 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1483 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 RH |
1484 | { |
1485 | long ret; | |
1486 | ||
1487 | ret = (insn >> 11) & 0x1f; | |
1488 | if (ret == 0) | |
1489 | ret = 32; | |
1490 | return ret; | |
1491 | } | |
1492 | ||
989993d8 JB |
1493 | /* The NB field in an lswi instruction, which has special value |
1494 | restrictions. The value 32 is stored as 0. */ | |
1495 | ||
1496 | static unsigned long | |
1497 | insert_nbi (unsigned long insn, | |
1498 | long value, | |
1499 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1500 | const char **errmsg ATTRIBUTE_UNUSED) | |
1501 | { | |
1502 | long rtvalue = (insn & RT_MASK) >> 21; | |
1503 | long ravalue = (insn & RA_MASK) >> 16; | |
1504 | ||
1505 | if (value == 0) | |
1506 | value = 32; | |
1507 | if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 | |
1508 | : ravalue)) | |
1509 | *errmsg = _("address register in load range"); | |
1510 | return insn | ((value & 0x1f) << 11); | |
1511 | } | |
1512 | ||
252b5132 RH |
1513 | /* The NSI field in a D form instruction. This is the same as the SI |
1514 | field, only negated. The extraction function always marks it as | |
1515 | invalid, since we never want to recognize an instruction which uses | |
1516 | a field of this type. */ | |
1517 | ||
252b5132 | 1518 | static unsigned long |
2fbfdc41 AM |
1519 | insert_nsi (unsigned long insn, |
1520 | long value, | |
fa452fa6 | 1521 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1522 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 | 1523 | { |
2fbfdc41 | 1524 | return insn | (-value & 0xffff); |
252b5132 RH |
1525 | } |
1526 | ||
1527 | static long | |
2fbfdc41 | 1528 | extract_nsi (unsigned long insn, |
fa452fa6 | 1529 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1530 | int *invalid) |
252b5132 | 1531 | { |
8427c424 | 1532 | *invalid = 1; |
2fbfdc41 | 1533 | return -(((insn & 0xffff) ^ 0x8000) - 0x8000); |
252b5132 RH |
1534 | } |
1535 | ||
1536 | /* The RA field in a D or X form instruction which is an updating | |
1537 | load, which means that the RA field may not be zero and may not | |
1538 | equal the RT field. */ | |
1539 | ||
1540 | static unsigned long | |
2fbfdc41 AM |
1541 | insert_ral (unsigned long insn, |
1542 | long value, | |
fa452fa6 | 1543 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1544 | const char **errmsg) |
252b5132 RH |
1545 | { |
1546 | if (value == 0 | |
1547 | || (unsigned long) value == ((insn >> 21) & 0x1f)) | |
1548 | *errmsg = "invalid register operand when updating"; | |
1549 | return insn | ((value & 0x1f) << 16); | |
1550 | } | |
1551 | ||
1552 | /* The RA field in an lmw instruction, which has special value | |
1553 | restrictions. */ | |
1554 | ||
1555 | static unsigned long | |
2fbfdc41 AM |
1556 | insert_ram (unsigned long insn, |
1557 | long value, | |
fa452fa6 | 1558 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1559 | const char **errmsg) |
252b5132 RH |
1560 | { |
1561 | if ((unsigned long) value >= ((insn >> 21) & 0x1f)) | |
1562 | *errmsg = _("index register in load range"); | |
1563 | return insn | ((value & 0x1f) << 16); | |
1564 | } | |
1565 | ||
989993d8 | 1566 | /* The RA field in the DQ form lq or an lswx instruction, which have special |
8427c424 | 1567 | value restrictions. */ |
adadcc0c | 1568 | |
adadcc0c | 1569 | static unsigned long |
2fbfdc41 AM |
1570 | insert_raq (unsigned long insn, |
1571 | long value, | |
fa452fa6 | 1572 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1573 | const char **errmsg) |
adadcc0c AM |
1574 | { |
1575 | long rtvalue = (insn & RT_MASK) >> 21; | |
1576 | ||
8427c424 | 1577 | if (value == rtvalue) |
adadcc0c AM |
1578 | *errmsg = _("source and target register operands must be different"); |
1579 | return insn | ((value & 0x1f) << 16); | |
1580 | } | |
1581 | ||
252b5132 RH |
1582 | /* The RA field in a D or X form instruction which is an updating |
1583 | store or an updating floating point load, which means that the RA | |
1584 | field may not be zero. */ | |
1585 | ||
1586 | static unsigned long | |
2fbfdc41 AM |
1587 | insert_ras (unsigned long insn, |
1588 | long value, | |
fa452fa6 | 1589 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1590 | const char **errmsg) |
252b5132 RH |
1591 | { |
1592 | if (value == 0) | |
1593 | *errmsg = _("invalid register operand when updating"); | |
1594 | return insn | ((value & 0x1f) << 16); | |
1595 | } | |
1596 | ||
1597 | /* The RB field in an X form instruction when it must be the same as | |
1598 | the RS field in the instruction. This is used for extended | |
1599 | mnemonics like mr. This operand is marked FAKE. The insertion | |
1600 | function just copies the BT field into the BA field, and the | |
1601 | extraction function just checks that the fields are the same. */ | |
1602 | ||
252b5132 | 1603 | static unsigned long |
2fbfdc41 AM |
1604 | insert_rbs (unsigned long insn, |
1605 | long value ATTRIBUTE_UNUSED, | |
fa452fa6 | 1606 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1607 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 RH |
1608 | { |
1609 | return insn | (((insn >> 21) & 0x1f) << 11); | |
1610 | } | |
1611 | ||
1612 | static long | |
2fbfdc41 | 1613 | extract_rbs (unsigned long insn, |
fa452fa6 | 1614 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1615 | int *invalid) |
252b5132 | 1616 | { |
8427c424 | 1617 | if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) |
252b5132 RH |
1618 | *invalid = 1; |
1619 | return 0; | |
1620 | } | |
1621 | ||
989993d8 JB |
1622 | /* The RB field in an lswx instruction, which has special value |
1623 | restrictions. */ | |
1624 | ||
1625 | static unsigned long | |
1626 | insert_rbx (unsigned long insn, | |
1627 | long value, | |
1628 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1629 | const char **errmsg) | |
1630 | { | |
1631 | long rtvalue = (insn & RT_MASK) >> 21; | |
1632 | ||
1633 | if (value == rtvalue) | |
1634 | *errmsg = _("source and target register operands must be different"); | |
1635 | return insn | ((value & 0x1f) << 11); | |
1636 | } | |
1637 | ||
b9c361e0 JL |
1638 | /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ |
1639 | static unsigned long | |
1640 | insert_sci8 (unsigned long insn, | |
1641 | long value, | |
1642 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1643 | const char **errmsg) | |
1644 | { | |
943d398f AM |
1645 | unsigned int fill_scale = 0; |
1646 | unsigned long ui8 = value; | |
b9c361e0 | 1647 | |
943d398f AM |
1648 | if ((ui8 & 0xffffff00) == 0) |
1649 | ; | |
1650 | else if ((ui8 & 0xffffff00) == 0xffffff00) | |
1651 | fill_scale = 0x400; | |
1652 | else if ((ui8 & 0xffff00ff) == 0) | |
b9c361e0 | 1653 | { |
943d398f AM |
1654 | fill_scale = 1 << 8; |
1655 | ui8 >>= 8; | |
b9c361e0 | 1656 | } |
943d398f | 1657 | else if ((ui8 & 0xffff00ff) == 0xffff00ff) |
b9c361e0 | 1658 | { |
943d398f AM |
1659 | fill_scale = 0x400 | (1 << 8); |
1660 | ui8 >>= 8; | |
b9c361e0 | 1661 | } |
943d398f | 1662 | else if ((ui8 & 0xff00ffff) == 0) |
b9c361e0 | 1663 | { |
943d398f AM |
1664 | fill_scale = 2 << 8; |
1665 | ui8 >>= 16; | |
b9c361e0 | 1666 | } |
943d398f | 1667 | else if ((ui8 & 0xff00ffff) == 0xff00ffff) |
b9c361e0 | 1668 | { |
943d398f AM |
1669 | fill_scale = 0x400 | (2 << 8); |
1670 | ui8 >>= 16; | |
b9c361e0 | 1671 | } |
943d398f | 1672 | else if ((ui8 & 0x00ffffff) == 0) |
b9c361e0 | 1673 | { |
943d398f AM |
1674 | fill_scale = 3 << 8; |
1675 | ui8 >>= 24; | |
b9c361e0 | 1676 | } |
943d398f | 1677 | else if ((ui8 & 0x00ffffff) == 0x00ffffff) |
b9c361e0 | 1678 | { |
943d398f AM |
1679 | fill_scale = 0x400 | (3 << 8); |
1680 | ui8 >>= 24; | |
b9c361e0 | 1681 | } |
943d398f | 1682 | else |
b9c361e0 | 1683 | { |
943d398f AM |
1684 | *errmsg = _("illegal immediate value"); |
1685 | ui8 = 0; | |
b9c361e0 | 1686 | } |
b9c361e0 | 1687 | |
943d398f | 1688 | return insn | fill_scale | (ui8 & 0xff); |
b9c361e0 JL |
1689 | } |
1690 | ||
1691 | static long | |
1692 | extract_sci8 (unsigned long insn, | |
1693 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1694 | int *invalid ATTRIBUTE_UNUSED) | |
1695 | { | |
943d398f AM |
1696 | int fill = insn & 0x400; |
1697 | int scale_factor = (insn & 0x300) >> 5; | |
1698 | long value = (insn & 0xff) << scale_factor; | |
1699 | ||
1700 | if (fill != 0) | |
1701 | value |= ~((long) 0xff << scale_factor); | |
1702 | return value; | |
b9c361e0 JL |
1703 | } |
1704 | ||
1705 | static unsigned long | |
1706 | insert_sci8n (unsigned long insn, | |
1707 | long value, | |
943d398f | 1708 | ppc_cpu_t dialect, |
b9c361e0 JL |
1709 | const char **errmsg) |
1710 | { | |
943d398f | 1711 | return insert_sci8 (insn, -value, dialect, errmsg); |
b9c361e0 JL |
1712 | } |
1713 | ||
1714 | static long | |
1715 | extract_sci8n (unsigned long insn, | |
943d398f AM |
1716 | ppc_cpu_t dialect, |
1717 | int *invalid) | |
b9c361e0 | 1718 | { |
943d398f | 1719 | return -extract_sci8 (insn, dialect, invalid); |
b9c361e0 JL |
1720 | } |
1721 | ||
1722 | static unsigned long | |
1723 | insert_sd4h (unsigned long insn, | |
1724 | long value, | |
1725 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1726 | const char **errmsg ATTRIBUTE_UNUSED) | |
1727 | { | |
1728 | return insn | ((value & 0x1e) << 7); | |
1729 | } | |
1730 | ||
1731 | static long | |
1732 | extract_sd4h (unsigned long insn, | |
1733 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1734 | int *invalid ATTRIBUTE_UNUSED) | |
1735 | { | |
1736 | return ((insn >> 8) & 0xf) << 1; | |
1737 | } | |
1738 | ||
1739 | static unsigned long | |
1740 | insert_sd4w (unsigned long insn, | |
1741 | long value, | |
1742 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1743 | const char **errmsg ATTRIBUTE_UNUSED) | |
1744 | { | |
1745 | return insn | ((value & 0x3c) << 6); | |
1746 | } | |
1747 | ||
1748 | static long | |
1749 | extract_sd4w (unsigned long insn, | |
1750 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1751 | int *invalid ATTRIBUTE_UNUSED) | |
1752 | { | |
1753 | return ((insn >> 8) & 0xf) << 2; | |
1754 | } | |
1755 | ||
1756 | static unsigned long | |
1757 | insert_oimm (unsigned long insn, | |
1758 | long value, | |
1759 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1760 | const char **errmsg ATTRIBUTE_UNUSED) | |
1761 | { | |
1762 | return insn | (((value - 1) & 0x1f) << 4); | |
1763 | } | |
1764 | ||
1765 | static long | |
1766 | extract_oimm (unsigned long insn, | |
1767 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1768 | int *invalid ATTRIBUTE_UNUSED) | |
1769 | { | |
1770 | return ((insn >> 4) & 0x1f) + 1; | |
1771 | } | |
1772 | ||
252b5132 RH |
1773 | /* The SH field in an MD form instruction. This is split. */ |
1774 | ||
252b5132 | 1775 | static unsigned long |
2fbfdc41 AM |
1776 | insert_sh6 (unsigned long insn, |
1777 | long value, | |
fa452fa6 | 1778 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1779 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 RH |
1780 | { |
1781 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); | |
1782 | } | |
1783 | ||
252b5132 | 1784 | static long |
2fbfdc41 | 1785 | extract_sh6 (unsigned long insn, |
fa452fa6 | 1786 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1787 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 RH |
1788 | { |
1789 | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); | |
1790 | } | |
1791 | ||
1792 | /* The SPR field in an XFX form instruction. This is flipped--the | |
1793 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
1794 | ||
1795 | static unsigned long | |
2fbfdc41 AM |
1796 | insert_spr (unsigned long insn, |
1797 | long value, | |
fa452fa6 | 1798 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1799 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 RH |
1800 | { |
1801 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1802 | } | |
1803 | ||
1804 | static long | |
2fbfdc41 | 1805 | extract_spr (unsigned long insn, |
fa452fa6 | 1806 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1807 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 RH |
1808 | { |
1809 | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); | |
1810 | } | |
1811 | ||
da99ee72 | 1812 | /* Some dialects have 8 SPRG registers instead of the standard 4. */ |
b9c361e0 | 1813 | #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE) |
da99ee72 AM |
1814 | |
1815 | static unsigned long | |
1816 | insert_sprg (unsigned long insn, | |
1817 | long value, | |
fa452fa6 | 1818 | ppc_cpu_t dialect, |
da99ee72 AM |
1819 | const char **errmsg) |
1820 | { | |
da99ee72 | 1821 | if (value > 7 |
98c76446 | 1822 | || (value > 3 && (dialect & ALLOW8_SPRG) == 0)) |
da99ee72 AM |
1823 | *errmsg = _("invalid sprg number"); |
1824 | ||
1825 | /* If this is mfsprg4..7 then use spr 260..263 which can be read in | |
1826 | user mode. Anything else must use spr 272..279. */ | |
1827 | if (value <= 3 || (insn & 0x100) != 0) | |
1828 | value |= 0x10; | |
1829 | ||
1830 | return insn | ((value & 0x17) << 16); | |
1831 | } | |
1832 | ||
1833 | static long | |
1834 | extract_sprg (unsigned long insn, | |
fa452fa6 | 1835 | ppc_cpu_t dialect, |
da99ee72 AM |
1836 | int *invalid) |
1837 | { | |
1838 | unsigned long val = (insn >> 16) & 0x1f; | |
1839 | ||
1840 | /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 | |
98c76446 AM |
1841 | If not BOOKE, 405 or VLE, then both use only 272..275. */ |
1842 | if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) | |
e1c93c69 AM |
1843 | || (val - 0x10 > 7 && (insn & 0x100) != 0) |
1844 | || val <= 3 | |
1845 | || (val & 8) != 0) | |
da99ee72 AM |
1846 | *invalid = 1; |
1847 | return val & 7; | |
1848 | } | |
1849 | ||
252b5132 RH |
1850 | /* The TBR field in an XFX instruction. This is just like SPR, but it |
1851 | is optional. When TBR is omitted, it must be inserted as 268 (the | |
1852 | magic number of the TB register). These functions treat 0 | |
1853 | (indicating an omitted optional operand) as 268. This means that | |
1854 | ``mftb 4,0'' is not handled correctly. This does not matter very | |
1855 | much, since the architecture manual does not define mftb as | |
1856 | accepting any values other than 268 or 269. */ | |
1857 | ||
1858 | #define TB (268) | |
1859 | ||
1860 | static unsigned long | |
2fbfdc41 AM |
1861 | insert_tbr (unsigned long insn, |
1862 | long value, | |
fa452fa6 | 1863 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1864 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 RH |
1865 | { |
1866 | if (value == 0) | |
1867 | value = TB; | |
1868 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1869 | } | |
1870 | ||
1871 | static long | |
2fbfdc41 | 1872 | extract_tbr (unsigned long insn, |
fa452fa6 | 1873 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1874 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 RH |
1875 | { |
1876 | long ret; | |
1877 | ||
1878 | ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); | |
1879 | if (ret == TB) | |
1880 | ret = 0; | |
1881 | return ret; | |
1882 | } | |
9b4e5766 PB |
1883 | |
1884 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ | |
1885 | ||
1886 | static unsigned long | |
1887 | insert_xt6 (unsigned long insn, | |
1888 | long value, | |
1889 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1890 | const char **errmsg ATTRIBUTE_UNUSED) | |
1891 | { | |
1892 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); | |
1893 | } | |
1894 | ||
1895 | static long | |
1896 | extract_xt6 (unsigned long insn, | |
1897 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1898 | int *invalid ATTRIBUTE_UNUSED) | |
1899 | { | |
1900 | return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); | |
1901 | } | |
1902 | ||
1903 | /* The XA field in an XX3 form instruction. This is split. */ | |
1904 | ||
1905 | static unsigned long | |
1906 | insert_xa6 (unsigned long insn, | |
1907 | long value, | |
1908 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1909 | const char **errmsg ATTRIBUTE_UNUSED) | |
1910 | { | |
1911 | return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); | |
1912 | } | |
1913 | ||
1914 | static long | |
1915 | extract_xa6 (unsigned long insn, | |
1916 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1917 | int *invalid ATTRIBUTE_UNUSED) | |
1918 | { | |
1919 | return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); | |
1920 | } | |
1921 | ||
1922 | /* The XB field in an XX3 form instruction. This is split. */ | |
1923 | ||
1924 | static unsigned long | |
1925 | insert_xb6 (unsigned long insn, | |
1926 | long value, | |
1927 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1928 | const char **errmsg ATTRIBUTE_UNUSED) | |
1929 | { | |
1930 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); | |
1931 | } | |
1932 | ||
1933 | static long | |
1934 | extract_xb6 (unsigned long insn, | |
1935 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1936 | int *invalid ATTRIBUTE_UNUSED) | |
1937 | { | |
1938 | return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); | |
1939 | } | |
1940 | ||
1941 | /* The XB field in an XX3 form instruction when it must be the same as | |
1942 | the XA field in the instruction. This is used for extended | |
1943 | mnemonics like xvmovdp. This operand is marked FAKE. The insertion | |
1944 | function just copies the XA field into the XB field, and the | |
1945 | extraction function just checks that the fields are the same. */ | |
1946 | ||
1947 | static unsigned long | |
1948 | insert_xb6s (unsigned long insn, | |
1949 | long value ATTRIBUTE_UNUSED, | |
1950 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1951 | const char **errmsg ATTRIBUTE_UNUSED) | |
1952 | { | |
1953 | return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); | |
1954 | } | |
1955 | ||
1956 | static long | |
1957 | extract_xb6s (unsigned long insn, | |
1958 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1959 | int *invalid) | |
1960 | { | |
1961 | if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) | |
1962 | || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) | |
1963 | *invalid = 1; | |
1964 | return 0; | |
1965 | } | |
066be9f7 PB |
1966 | |
1967 | /* The XC field in an XX4 form instruction. This is split. */ | |
1968 | ||
1969 | static unsigned long | |
1970 | insert_xc6 (unsigned long insn, | |
1971 | long value, | |
1972 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1973 | const char **errmsg ATTRIBUTE_UNUSED) | |
1974 | { | |
1975 | return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); | |
1976 | } | |
1977 | ||
1978 | static long | |
1979 | extract_xc6 (unsigned long insn, | |
1980 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1981 | int *invalid ATTRIBUTE_UNUSED) | |
1982 | { | |
1983 | return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); | |
1984 | } | |
1985 | ||
1986 | static unsigned long | |
1987 | insert_dm (unsigned long insn, | |
1988 | long value, | |
1989 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1990 | const char **errmsg) | |
1991 | { | |
1992 | if (value != 0 && value != 1) | |
1993 | *errmsg = _("invalid constant"); | |
1994 | return insn | (((value) ? 3 : 0) << 8); | |
1995 | } | |
1996 | ||
1997 | static long | |
1998 | extract_dm (unsigned long insn, | |
1999 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2000 | int *invalid) | |
2001 | { | |
2002 | long value; | |
2003 | ||
2004 | value = (insn >> 8) & 3; | |
2005 | if (value != 0 && value != 3) | |
2006 | *invalid = 1; | |
2007 | return (value) ? 1 : 0; | |
2008 | } | |
b9c361e0 JL |
2009 | /* The VLESIMM field in an I16A form instruction. This is split. */ |
2010 | ||
2011 | static unsigned long | |
2012 | insert_vlesi (unsigned long insn, | |
2013 | long value, | |
2014 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2015 | const char **errmsg ATTRIBUTE_UNUSED) | |
2016 | { | |
2017 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); | |
2018 | } | |
2019 | ||
2020 | static long | |
2021 | extract_vlesi (unsigned long insn, | |
2022 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2023 | int *invalid ATTRIBUTE_UNUSED) | |
2024 | { | |
2025 | /* RWRW Because I don't know how to make int be 16 and long be 32 */ | |
2026 | /* I can't rely on casting an int to long to get sign extension. */ | |
2027 | long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); | |
2028 | if (value & 0x8000) | |
2029 | value |= 0xffff0000; | |
2030 | return value; | |
2031 | } | |
2032 | ||
2033 | static unsigned long | |
2034 | insert_vlensi (unsigned long insn, | |
2035 | long value, | |
2036 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2037 | const char **errmsg ATTRIBUTE_UNUSED) | |
2038 | { | |
2039 | value = -value; | |
2040 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); | |
2041 | } | |
2042 | static long | |
2043 | extract_vlensi (unsigned long insn, | |
2044 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2045 | int *invalid ATTRIBUTE_UNUSED) | |
2046 | { | |
2047 | long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); | |
2048 | if (value & 0x8000) | |
2049 | value |= 0xffff0000; | |
2050 | *invalid = 1; | |
2051 | return -value; | |
2052 | } | |
2053 | ||
2054 | /* The VLEUIMM field in an I16A form instruction. This is split. */ | |
2055 | ||
2056 | static unsigned long | |
2057 | insert_vleui (unsigned long insn, | |
2058 | long value, | |
2059 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2060 | const char **errmsg ATTRIBUTE_UNUSED) | |
2061 | { | |
2062 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); | |
2063 | } | |
2064 | ||
2065 | static long | |
2066 | extract_vleui (unsigned long insn, | |
2067 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2068 | int *invalid ATTRIBUTE_UNUSED) | |
2069 | { | |
2070 | return ((insn >> 10) & 0xf800) | (insn & 0x7ff); | |
2071 | } | |
2072 | ||
2073 | /* The VLEUIMML field in an I16L form instruction. This is split. */ | |
2074 | ||
2075 | static unsigned long | |
2076 | insert_vleil (unsigned long insn, | |
2077 | long value, | |
2078 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2079 | const char **errmsg ATTRIBUTE_UNUSED) | |
2080 | { | |
2081 | return insn | ((value & 0xf800) << 5) | (value & 0x7ff); | |
2082 | } | |
2083 | ||
2084 | static long | |
2085 | extract_vleil (unsigned long insn, | |
2086 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2087 | int *invalid ATTRIBUTE_UNUSED) | |
2088 | { | |
2089 | return ((insn >> 5) & 0xf800) | (insn & 0x7ff); | |
2090 | } | |
2091 | ||
252b5132 RH |
2092 | \f |
2093 | /* Macros used to form opcodes. */ | |
2094 | ||
2095 | /* The main opcode. */ | |
2096 | #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) | |
2097 | #define OP_MASK OP (0x3f) | |
2098 | ||
2099 | /* The main opcode combined with a trap code in the TO field of a D | |
2100 | form instruction. Used for extended mnemonics for the trap | |
2101 | instructions. */ | |
2102 | #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) | |
2103 | #define OPTO_MASK (OP_MASK | TO_MASK) | |
2104 | ||
2105 | /* The main opcode combined with a comparison size bit in the L field | |
2106 | of a D form or X form instruction. Used for extended mnemonics for | |
2107 | the comparison instructions. */ | |
2108 | #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) | |
2109 | #define OPL_MASK OPL (0x3f,1) | |
2110 | ||
b9c361e0 JL |
2111 | /* The main opcode combined with an update code in D form instruction. |
2112 | Used for extended mnemonics for VLE memory instructions. */ | |
2113 | #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8)) | |
2114 | #define OPVUP_MASK OPVUP (0x3f, 0xff) | |
2115 | ||
252b5132 RH |
2116 | /* An A form instruction. */ |
2117 | #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) | |
2118 | #define A_MASK A (0x3f, 0x1f, 1) | |
2119 | ||
2120 | /* An A_MASK with the FRB field fixed. */ | |
2121 | #define AFRB_MASK (A_MASK | FRB_MASK) | |
2122 | ||
2123 | /* An A_MASK with the FRC field fixed. */ | |
2124 | #define AFRC_MASK (A_MASK | FRC_MASK) | |
2125 | ||
2126 | /* An A_MASK with the FRA and FRC fields fixed. */ | |
2127 | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) | |
2128 | ||
702f0fb4 PB |
2129 | /* An AFRAFRC_MASK, but with L bit clear. */ |
2130 | #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) | |
2131 | ||
252b5132 RH |
2132 | /* A B form instruction. */ |
2133 | #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) | |
2134 | #define B_MASK B (0x3f, 1, 1) | |
2135 | ||
b9c361e0 JL |
2136 | /* A BD8 form instruction. This is a 16-bit instruction. */ |
2137 | #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8)) | |
2138 | #define BD8_MASK BD8 (0x3f, 1, 1) | |
2139 | ||
2140 | /* Another BD8 form instruction. This is a 16-bit instruction. */ | |
2141 | #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11) | |
2142 | #define BD8IO_MASK BD8IO (0x1f) | |
2143 | ||
2144 | /* A BD8 form instruction for simplified mnemonics. */ | |
2145 | #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) | |
2146 | /* A mask that excludes BO32 and BI32. */ | |
2147 | #define EBD8IO1_MASK 0xf800 | |
2148 | /* A mask that includes BO32 and excludes BI32. */ | |
2149 | #define EBD8IO2_MASK 0xfc00 | |
2150 | /* A mask that include BO32 AND BI32. */ | |
2151 | #define EBD8IO3_MASK 0xff00 | |
2152 | ||
2153 | /* A BD15 form instruction. */ | |
2154 | #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1)) | |
2155 | #define BD15_MASK BD15 (0x3f, 0xf, 1) | |
2156 | ||
2157 | /* A BD15 form instruction for extended conditional branch mnemonics. */ | |
2158 | #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1) | |
2159 | #define EBD15_MASK 0xfff00001 | |
2160 | ||
2161 | /* A BD15 form instruction for extended conditional branch mnemonics with BI. */ | |
2162 | #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \ | |
2163 | | (((aa) & 0xf) << 22) \ | |
2164 | | (((bo) & 0x3) << 20) \ | |
2165 | | (((bi) & 0x3) << 16) \ | |
2166 | | ((lk) & 1) | |
2167 | #define EBD15BI_MASK 0xfff30001 | |
2168 | ||
2169 | /* A BD24 form instruction. */ | |
2170 | #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1)) | |
2171 | #define BD24_MASK BD24 (0x3f, 1, 1) | |
2172 | ||
252b5132 RH |
2173 | /* A B form instruction setting the BO field. */ |
2174 | #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) | |
2175 | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) | |
2176 | ||
2177 | /* A BBO_MASK with the y bit of the BO field removed. This permits | |
2178 | matching a conditional branch regardless of the setting of the y | |
94efba12 | 2179 | bit. Similarly for the 'at' bits used for power4 branch hints. */ |
de866fcc | 2180 | #define Y_MASK (((unsigned long) 1) << 21) |
802a735e AM |
2181 | #define AT1_MASK (((unsigned long) 3) << 21) |
2182 | #define AT2_MASK (((unsigned long) 9) << 21) | |
2183 | #define BBOY_MASK (BBO_MASK &~ Y_MASK) | |
2184 | #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) | |
252b5132 RH |
2185 | |
2186 | /* A B form instruction setting the BO field and the condition bits of | |
2187 | the BI field. */ | |
2188 | #define BBOCB(op, bo, cb, aa, lk) \ | |
2189 | (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) | |
2190 | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) | |
2191 | ||
2192 | /* A BBOCB_MASK with the y bit of the BO field removed. */ | |
2193 | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) | |
802a735e AM |
2194 | #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
2195 | #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) | |
252b5132 RH |
2196 | |
2197 | /* A BBOYCB_MASK in which the BI field is fixed. */ | |
2198 | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) | |
802a735e | 2199 | #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
252b5132 | 2200 | |
b9c361e0 JL |
2201 | /* A VLE C form instruction. */ |
2202 | #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1)) | |
2203 | #define C_LK_MASK C_LK(0x7fff, 1) | |
2204 | #define C(x) ((((unsigned long)(x)) & 0xffff)) | |
2205 | #define C_MASK C(0xffff) | |
2206 | ||
23976049 EZ |
2207 | /* An Context form instruction. */ |
2208 | #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) | |
fdd12ef3 | 2209 | #define CTX_MASK CTX(0x3f, 0x7) |
23976049 EZ |
2210 | |
2211 | /* An User Context form instruction. */ | |
2212 | #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) | |
fdd12ef3 | 2213 | #define UCTX_MASK UCTX(0x3f, 0x1f) |
23976049 | 2214 | |
252b5132 RH |
2215 | /* The main opcode mask with the RA field clear. */ |
2216 | #define DRA_MASK (OP_MASK | RA_MASK) | |
2217 | ||
2218 | /* A DS form instruction. */ | |
2219 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) | |
2220 | #define DS_MASK DSO (0x3f, 3) | |
2221 | ||
23976049 EZ |
2222 | /* An EVSEL form instruction. */ |
2223 | #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) | |
2224 | #define EVSEL_MASK EVSEL(0x3f, 0xff) | |
2225 | ||
b9c361e0 JL |
2226 | /* An IA16 form instruction. */ |
2227 | #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) | |
2228 | #define IA16_MASK IA16(0x3f, 0x1f) | |
2229 | ||
2230 | /* An I16A form instruction. */ | |
2231 | #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) | |
2232 | #define I16A_MASK I16A(0x3f, 0x1f) | |
2233 | ||
2234 | /* An I16L form instruction. */ | |
2235 | #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) | |
2236 | #define I16L_MASK I16L(0x3f, 0x1f) | |
2237 | ||
2238 | /* An IM7 form instruction. */ | |
2239 | #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11) | |
2240 | #define IM7_MASK IM7(0x1f) | |
2241 | ||
252b5132 RH |
2242 | /* An M form instruction. */ |
2243 | #define M(op, rc) (OP (op) | ((rc) & 1)) | |
2244 | #define M_MASK M (0x3f, 1) | |
2245 | ||
b9c361e0 JL |
2246 | /* An LI20 form instruction. */ |
2247 | #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15) | |
2248 | #define LI20_MASK LI20(0x3f, 0x1) | |
2249 | ||
252b5132 RH |
2250 | /* An M form instruction with the ME field specified. */ |
2251 | #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) | |
2252 | ||
2253 | /* An M_MASK with the MB and ME fields fixed. */ | |
2254 | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) | |
2255 | ||
2256 | /* An M_MASK with the SH and ME fields fixed. */ | |
2257 | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) | |
2258 | ||
2259 | /* An MD form instruction. */ | |
2260 | #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) | |
2261 | #define MD_MASK MD (0x3f, 0x7, 1) | |
2262 | ||
2263 | /* An MD_MASK with the MB field fixed. */ | |
2264 | #define MDMB_MASK (MD_MASK | MB6_MASK) | |
2265 | ||
2266 | /* An MD_MASK with the SH field fixed. */ | |
2267 | #define MDSH_MASK (MD_MASK | SH6_MASK) | |
2268 | ||
2269 | /* An MDS form instruction. */ | |
2270 | #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) | |
2271 | #define MDS_MASK MDS (0x3f, 0xf, 1) | |
2272 | ||
2273 | /* An MDS_MASK with the MB field fixed. */ | |
2274 | #define MDSMB_MASK (MDS_MASK | MB6_MASK) | |
2275 | ||
2276 | /* An SC form instruction. */ | |
2277 | #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) | |
2278 | #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) | |
2279 | ||
b9c361e0 JL |
2280 | /* An SCI8 form instruction. */ |
2281 | #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11)) | |
2282 | #define SCI8_MASK SCI8(0x3f, 0x1f) | |
2283 | ||
2284 | /* An SCI8 form instruction. */ | |
2285 | #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23)) | |
2286 | #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) | |
2287 | ||
2288 | /* An SD4 form instruction. This is a 16-bit instruction. */ | |
2289 | #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12) | |
2290 | #define SD4_MASK SD4(0xf) | |
2291 | ||
2292 | /* An SE_IM5 form instruction. This is a 16-bit instruction. */ | |
2293 | #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9)) | |
2294 | #define SE_IM5_MASK SE_IM5(0x3f, 1) | |
2295 | ||
2296 | /* An SE_R form instruction. This is a 16-bit instruction. */ | |
2297 | #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4)) | |
2298 | #define SE_R_MASK SE_R(0x3f, 0x3f) | |
2299 | ||
2300 | /* An SE_RR form instruction. This is a 16-bit instruction. */ | |
2301 | #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8)) | |
2302 | #define SE_RR_MASK SE_RR(0x3f, 3) | |
2303 | ||
2304 | /* A VX form instruction. */ | |
786e2c0f C |
2305 | #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
2306 | ||
112290ab | 2307 | /* The mask for an VX form instruction. */ |
786e2c0f C |
2308 | #define VX_MASK VX(0x3f, 0x7ff) |
2309 | ||
fb048c26 PB |
2310 | /* A VX_MASK with the VA field fixed. */ |
2311 | #define VXVA_MASK (VX_MASK | (0x1f << 16)) | |
2312 | ||
2313 | /* A VX_MASK with the VB field fixed. */ | |
2314 | #define VXVB_MASK (VX_MASK | (0x1f << 11)) | |
2315 | ||
2316 | /* A VX_MASK with the VA and VB fields fixed. */ | |
2317 | #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) | |
2318 | ||
2319 | /* A VX_MASK with the VD and VA fields fixed. */ | |
2320 | #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) | |
2321 | ||
2322 | /* A VX_MASK with a UIMM4 field. */ | |
2323 | #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) | |
2324 | ||
2325 | /* A VX_MASK with a UIMM3 field. */ | |
2326 | #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) | |
2327 | ||
2328 | /* A VX_MASK with a UIMM2 field. */ | |
2329 | #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) | |
2330 | ||
b9c361e0 | 2331 | /* A VA form instruction. */ |
2613489e | 2332 | #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) |
786e2c0f | 2333 | |
112290ab | 2334 | /* The mask for an VA form instruction. */ |
2613489e | 2335 | #define VXA_MASK VXA(0x3f, 0x3f) |
786e2c0f | 2336 | |
382c72e9 PB |
2337 | /* A VXA_MASK with a SHB field. */ |
2338 | #define VXASHB_MASK (VXA_MASK | (1 << 10)) | |
2339 | ||
b9c361e0 | 2340 | /* A VXR form instruction. */ |
786e2c0f C |
2341 | #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) |
2342 | ||
112290ab | 2343 | /* The mask for a VXR form instruction. */ |
786e2c0f C |
2344 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
2345 | ||
252b5132 RH |
2346 | /* An X form instruction. */ |
2347 | #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) | |
2348 | ||
b9c361e0 JL |
2349 | /* An EX form instruction. */ |
2350 | #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) | |
2351 | ||
2352 | /* The mask for an EX form instruction. */ | |
2353 | #define EX_MASK EX (0x3f, 0x7ff) | |
2354 | ||
066be9f7 PB |
2355 | /* An XX2 form instruction. */ |
2356 | #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) | |
2357 | ||
9b4e5766 PB |
2358 | /* An XX3 form instruction. */ |
2359 | #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) | |
2360 | ||
066be9f7 PB |
2361 | /* An XX3 form instruction with the RC bit specified. */ |
2362 | #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) | |
2363 | ||
2364 | /* An XX4 form instruction. */ | |
2365 | #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) | |
9b4e5766 | 2366 | |
702f0fb4 PB |
2367 | /* A Z form instruction. */ |
2368 | #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) | |
2369 | ||
252b5132 RH |
2370 | /* An X form instruction with the RC bit specified. */ |
2371 | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) | |
2372 | ||
702f0fb4 PB |
2373 | /* A Z form instruction with the RC bit specified. */ |
2374 | #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) | |
2375 | ||
252b5132 RH |
2376 | /* The mask for an X form instruction. */ |
2377 | #define X_MASK XRC (0x3f, 0x3ff, 1) | |
2378 | ||
e0d602ec BE |
2379 | /* An X form wait instruction with everything filled in except the WC field. */ |
2380 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) | |
2381 | ||
9b4e5766 PB |
2382 | /* The mask for an XX1 form instruction. */ |
2383 | #define XX1_MASK X (0x3f, 0x3ff) | |
2384 | ||
066be9f7 PB |
2385 | /* The mask for an XX2 form instruction. */ |
2386 | #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) | |
2387 | ||
2388 | /* The mask for an XX2 form instruction with the UIM bits specified. */ | |
2389 | #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) | |
2390 | ||
2391 | /* The mask for an XX2 form instruction with the BF bits specified. */ | |
2392 | #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) | |
2393 | ||
9b4e5766 PB |
2394 | /* The mask for an XX3 form instruction. */ |
2395 | #define XX3_MASK XX3 (0x3f, 0xff) | |
2396 | ||
066be9f7 PB |
2397 | /* The mask for an XX3 form instruction with the BF bits specified. */ |
2398 | #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) | |
2399 | ||
2400 | /* The mask for an XX3 form instruction with the DM or SHW bits specified. */ | |
9b4e5766 | 2401 | #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) |
066be9f7 PB |
2402 | #define XX3SHW_MASK XX3DM_MASK |
2403 | ||
2404 | /* The mask for an XX4 form instruction. */ | |
2405 | #define XX4_MASK XX4 (0x3f, 0x3) | |
2406 | ||
2407 | /* An X form wait instruction with everything filled in except the WC field. */ | |
2408 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) | |
9b4e5766 | 2409 | |
702f0fb4 PB |
2410 | /* The mask for a Z form instruction. */ |
2411 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) | |
0bbdef92 | 2412 | #define Z2_MASK ZRC (0x3f, 0xff, 1) |
702f0fb4 | 2413 | |
252b5132 RH |
2414 | /* An X_MASK with the RA field fixed. */ |
2415 | #define XRA_MASK (X_MASK | RA_MASK) | |
2416 | ||
ea192fa3 PB |
2417 | /* An XRA_MASK with the W field clear. */ |
2418 | #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) | |
2419 | ||
252b5132 RH |
2420 | /* An X_MASK with the RB field fixed. */ |
2421 | #define XRB_MASK (X_MASK | RB_MASK) | |
2422 | ||
2423 | /* An X_MASK with the RT field fixed. */ | |
2424 | #define XRT_MASK (X_MASK | RT_MASK) | |
2425 | ||
702f0fb4 PB |
2426 | /* An XRT_MASK mask with the L bits clear. */ |
2427 | #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) | |
2428 | ||
252b5132 RH |
2429 | /* An X_MASK with the RA and RB fields fixed. */ |
2430 | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) | |
2431 | ||
112290ab | 2432 | /* An XRARB_MASK, but with the L bit clear. */ |
5ae2e65e AM |
2433 | #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) |
2434 | ||
252b5132 RH |
2435 | /* An X_MASK with the RT and RA fields fixed. */ |
2436 | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) | |
2437 | ||
5817ffd1 PB |
2438 | /* An X_MASK with the RT and RB fields fixed. */ |
2439 | #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) | |
2440 | ||
98acc1c5 AM |
2441 | /* An XRTRA_MASK, but with L bit clear. */ |
2442 | #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) | |
2443 | ||
5817ffd1 PB |
2444 | /* An X_MASK with the RT, RA and RB fields fixed. */ |
2445 | #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) | |
2446 | ||
2447 | /* An XRTRARB_MASK, but with L bit clear. */ | |
2448 | #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21)) | |
2449 | ||
2450 | /* An XRTRARB_MASK, but with A bit clear. */ | |
2451 | #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25)) | |
2452 | ||
2453 | /* An XRTRARB_MASK, but with BF bits clear. */ | |
2454 | #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23)) | |
2455 | ||
f3806e43 BE |
2456 | /* An X form instruction with the L bit specified. */ |
2457 | #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) | |
252b5132 | 2458 | |
e0d602ec BE |
2459 | /* An X form instruction with the L bits specified. */ |
2460 | #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) | |
2461 | ||
5817ffd1 PB |
2462 | /* An X form instruction with the L bit and RC bit specified. */ |
2463 | #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21)) | |
2464 | ||
19a6653c AM |
2465 | /* An X form instruction with RT fields specified */ |
2466 | #define XRT(op, xop, rt) (X ((op), (xop)) \ | |
2467 | | ((((unsigned long)(rt)) & 0x1f) << 21)) | |
2468 | ||
2469 | /* An X form instruction with RT and RA fields specified */ | |
2470 | #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \ | |
2471 | | ((((unsigned long)(rt)) & 0x1f) << 21) \ | |
2472 | | ((((unsigned long)(ra)) & 0x1f) << 16)) | |
2473 | ||
252b5132 RH |
2474 | /* The mask for an X form comparison instruction. */ |
2475 | #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) | |
2476 | ||
520ceea4 BE |
2477 | /* The mask for an X form comparison instruction with the L field |
2478 | fixed. */ | |
2479 | #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) | |
252b5132 RH |
2480 | |
2481 | /* An X form trap instruction with the TO field specified. */ | |
2482 | #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) | |
2483 | #define XTO_MASK (X_MASK | TO_MASK) | |
2484 | ||
e0c21649 GK |
2485 | /* An X form tlb instruction with the SH field specified. */ |
2486 | #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) | |
2487 | #define XTLB_MASK (X_MASK | SH_MASK) | |
2488 | ||
6ba045b1 AM |
2489 | /* An X form sync instruction. */ |
2490 | #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) | |
2491 | ||
2492 | /* An X form sync instruction with everything filled in except the LS field. */ | |
2493 | #define XSYNC_MASK (0xff9fffff) | |
2494 | ||
aea77599 AM |
2495 | /* An X form sync instruction with everything filled in except the L and E fields. */ |
2496 | #define XSYNCLE_MASK (0xff90ffff) | |
2497 | ||
702f0fb4 PB |
2498 | /* An X_MASK, but with the EH bit clear. */ |
2499 | #define XEH_MASK (X_MASK & ~((unsigned long )1)) | |
2500 | ||
f5c120c5 MG |
2501 | /* An X form AltiVec dss instruction. */ |
2502 | #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) | |
2503 | #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) | |
2504 | ||
252b5132 RH |
2505 | /* An XFL form instruction. */ |
2506 | #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) | |
ea192fa3 | 2507 | #define XFL_MASK XFL (0x3f, 0x3ff, 1) |
252b5132 | 2508 | |
23976049 | 2509 | /* An X form isel instruction. */ |
de866fcc AM |
2510 | #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
2511 | #define XISEL_MASK XISEL(0x3f, 0x1f) | |
23976049 | 2512 | |
252b5132 RH |
2513 | /* An XL form instruction with the LK field set to 0. */ |
2514 | #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) | |
2515 | ||
2516 | /* An XL form instruction which uses the LK field. */ | |
2517 | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) | |
2518 | ||
2519 | /* The mask for an XL form instruction. */ | |
2520 | #define XL_MASK XLLK (0x3f, 0x3ff, 1) | |
2521 | ||
2522 | /* An XL form instruction which explicitly sets the BO field. */ | |
2523 | #define XLO(op, bo, xop, lk) \ | |
2524 | (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) | |
2525 | #define XLO_MASK (XL_MASK | BO_MASK) | |
2526 | ||
2527 | /* An XL form instruction which explicitly sets the y bit of the BO | |
2528 | field. */ | |
2529 | #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) | |
2530 | #define XLYLK_MASK (XL_MASK | Y_MASK) | |
2531 | ||
2532 | /* An XL form instruction which sets the BO field and the condition | |
2533 | bits of the BI field. */ | |
2534 | #define XLOCB(op, bo, cb, xop, lk) \ | |
2535 | (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) | |
2536 | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) | |
2537 | ||
2538 | /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ | |
2539 | #define XLBB_MASK (XL_MASK | BB_MASK) | |
2540 | #define XLYBB_MASK (XLYLK_MASK | BB_MASK) | |
2541 | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) | |
2542 | ||
d0618d1c AM |
2543 | /* A mask for branch instructions using the BH field. */ |
2544 | #define XLBH_MASK (XL_MASK | (0x1c << 11)) | |
2545 | ||
252b5132 RH |
2546 | /* An XL_MASK with the BO and BB fields fixed. */ |
2547 | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) | |
2548 | ||
2549 | /* An XL_MASK with the BO, BI and BB fields fixed. */ | |
2550 | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) | |
2551 | ||
e01d869a AM |
2552 | /* An X form mbar instruction with MO field. */ |
2553 | #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21)) | |
2554 | ||
252b5132 RH |
2555 | /* An XO form instruction. */ |
2556 | #define XO(op, xop, oe, rc) \ | |
2557 | (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) | |
2558 | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) | |
2559 | ||
2560 | /* An XO_MASK with the RB field fixed. */ | |
2561 | #define XORB_MASK (XO_MASK | RB_MASK) | |
2562 | ||
c3d65c1c BE |
2563 | /* An XOPS form instruction for paired singles. */ |
2564 | #define XOPS(op, xop, rc) \ | |
2565 | (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) | |
2566 | #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) | |
2567 | ||
2568 | ||
252b5132 RH |
2569 | /* An XS form instruction. */ |
2570 | #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) | |
2571 | #define XS_MASK XS (0x3f, 0x1ff, 1) | |
2572 | ||
2573 | /* A mask for the FXM version of an XFX form instruction. */ | |
98e69875 | 2574 | #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) |
252b5132 RH |
2575 | |
2576 | /* An XFX form instruction with the FXM field filled in. */ | |
98e69875 AM |
2577 | #define XFXM(op, xop, fxm, p4) \ |
2578 | (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ | |
2579 | | ((unsigned long)(p4) << 20)) | |
252b5132 RH |
2580 | |
2581 | /* An XFX form instruction with the SPR field filled in. */ | |
2582 | #define XSPR(op, xop, spr) \ | |
2583 | (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) | |
2584 | #define XSPR_MASK (X_MASK | SPR_MASK) | |
2585 | ||
2586 | /* An XFX form instruction with the SPR field filled in except for the | |
2587 | SPRBAT field. */ | |
2588 | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) | |
2589 | ||
2590 | /* An XFX form instruction with the SPR field filled in except for the | |
2591 | SPRG field. */ | |
b84bf58a | 2592 | #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) |
252b5132 RH |
2593 | |
2594 | /* An X form instruction with everything filled in except the E field. */ | |
2595 | #define XE_MASK (0xffff7fff) | |
2596 | ||
23976049 EZ |
2597 | /* An X form user context instruction. */ |
2598 | #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) | |
2599 | #define XUC_MASK XUC(0x3f, 0x1f) | |
2600 | ||
c3d65c1c BE |
2601 | /* An XW form instruction. */ |
2602 | #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1)) | |
2603 | /* The mask for a G form instruction. rc not supported at present. */ | |
2604 | #define XW_MASK XW (0x3f, 0x3f, 0) | |
2605 | ||
081ba1b3 AM |
2606 | /* An APU form instruction. */ |
2607 | #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) | |
2608 | ||
2609 | /* The mask for an APU form instruction. */ | |
2610 | #define APU_MASK APU (0x3f, 0x3ff, 1) | |
2611 | #define APU_RT_MASK (APU_MASK | RT_MASK) | |
2612 | #define APU_RA_MASK (APU_MASK | RA_MASK) | |
2613 | ||
252b5132 RH |
2614 | /* The BO encodings used in extended conditional branch mnemonics. */ |
2615 | #define BODNZF (0x0) | |
2616 | #define BODNZFP (0x1) | |
2617 | #define BODZF (0x2) | |
2618 | #define BODZFP (0x3) | |
252b5132 RH |
2619 | #define BODNZT (0x8) |
2620 | #define BODNZTP (0x9) | |
2621 | #define BODZT (0xa) | |
2622 | #define BODZTP (0xb) | |
802a735e AM |
2623 | |
2624 | #define BOF (0x4) | |
2625 | #define BOFP (0x5) | |
94efba12 AM |
2626 | #define BOFM4 (0x6) |
2627 | #define BOFP4 (0x7) | |
252b5132 RH |
2628 | #define BOT (0xc) |
2629 | #define BOTP (0xd) | |
94efba12 AM |
2630 | #define BOTM4 (0xe) |
2631 | #define BOTP4 (0xf) | |
802a735e | 2632 | |
252b5132 RH |
2633 | #define BODNZ (0x10) |
2634 | #define BODNZP (0x11) | |
2635 | #define BODZ (0x12) | |
2636 | #define BODZP (0x13) | |
94efba12 AM |
2637 | #define BODNZM4 (0x18) |
2638 | #define BODNZP4 (0x19) | |
2639 | #define BODZM4 (0x1a) | |
2640 | #define BODZP4 (0x1b) | |
802a735e | 2641 | |
252b5132 RH |
2642 | #define BOU (0x14) |
2643 | ||
b9c361e0 JL |
2644 | /* The BO16 encodings used in extended VLE conditional branch mnemonics. */ |
2645 | #define BO16F (0x0) | |
2646 | #define BO16T (0x1) | |
2647 | ||
2648 | /* The BO32 encodings used in extended VLE conditional branch mnemonics. */ | |
2649 | #define BO32F (0x0) | |
2650 | #define BO32T (0x1) | |
2651 | #define BO32DNZ (0x2) | |
2652 | #define BO32DZ (0x3) | |
2653 | ||
252b5132 RH |
2654 | /* The BI condition bit encodings used in extended conditional branch |
2655 | mnemonics. */ | |
2656 | #define CBLT (0) | |
2657 | #define CBGT (1) | |
2658 | #define CBEQ (2) | |
2659 | #define CBSO (3) | |
2660 | ||
2661 | /* The TO encodings used in extended trap mnemonics. */ | |
2662 | #define TOLGT (0x1) | |
2663 | #define TOLLT (0x2) | |
2664 | #define TOEQ (0x4) | |
2665 | #define TOLGE (0x5) | |
2666 | #define TOLNL (0x5) | |
2667 | #define TOLLE (0x6) | |
2668 | #define TOLNG (0x6) | |
2669 | #define TOGT (0x8) | |
2670 | #define TOGE (0xc) | |
2671 | #define TONL (0xc) | |
2672 | #define TOLT (0x10) | |
2673 | #define TOLE (0x14) | |
2674 | #define TONG (0x14) | |
2675 | #define TONE (0x18) | |
2676 | #define TOU (0x1f) | |
2677 | \f | |
2678 | /* Smaller names for the flags so each entry in the opcodes table will | |
2679 | fit on a single line. */ | |
1cb0a767 | 2680 | #define PPCNONE 0 |
252b5132 | 2681 | #undef PPC |
de866fcc | 2682 | #define PPC PPC_OPCODE_PPC |
661bd698 | 2683 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
661bd698 | 2684 | #define POWER4 PPC_OPCODE_POWER4 |
1ed8e1e4 | 2685 | #define POWER5 PPC_OPCODE_POWER5 |
702f0fb4 | 2686 | #define POWER6 PPC_OPCODE_POWER6 |
066be9f7 | 2687 | #define POWER7 PPC_OPCODE_POWER7 |
5817ffd1 | 2688 | #define POWER8 PPC_OPCODE_POWER8 |
ede602d7 | 2689 | #define CELL PPC_OPCODE_CELL |
bdc70b4a | 2690 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE |
6b069ee7 | 2691 | #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ |
bdc70b4a | 2692 | | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
418c1742 | 2693 | #define PPC403 PPC_OPCODE_403 |
081ba1b3 | 2694 | #define PPC405 PPC_OPCODE_405 |
7d5b217e | 2695 | #define PPC440 PPC_OPCODE_440 |
c8187e15 | 2696 | #define PPC464 PPC440 |
9fe54b1c | 2697 | #define PPC476 PPC_OPCODE_476 |
252b5132 | 2698 | #define PPC750 PPC |
33e8d5ac | 2699 | #define PPC7450 PPC |
252b5132 | 2700 | #define PPC860 PPC |
c3d65c1c | 2701 | #define PPCPS PPC_OPCODE_PPCPS |
a404d431 | 2702 | #define PPCVEC PPC_OPCODE_ALTIVEC |
aea77599 | 2703 | #define PPCVEC2 PPC_OPCODE_ALTIVEC2 |
9b4e5766 | 2704 | #define PPCVSX PPC_OPCODE_VSX |
de866fcc AM |
2705 | #define POWER PPC_OPCODE_POWER |
2706 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | |
81a0b7e2 AM |
2707 | #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON |
2708 | #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON | |
de866fcc | 2709 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
de866fcc | 2710 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 |
661bd698 | 2711 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON |
de866fcc | 2712 | #define MFDEC1 PPC_OPCODE_POWER |
bdc70b4a | 2713 | #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN |
418c1742 | 2714 | #define BOOKE PPC_OPCODE_BOOKE |
b9c361e0 | 2715 | #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE |
36ae0db3 | 2716 | #define PPCE300 PPC_OPCODE_E300 |
b9c361e0 JL |
2717 | #define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE |
2718 | #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE | |
2719 | #define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE | |
de866fcc | 2720 | #define PPCBRLK PPC_OPCODE_BRLOCK |
23976049 | 2721 | #define PPCPMR PPC_OPCODE_PMR |
aea77599 | 2722 | #define PPCTMR PPC_OPCODE_TMR |
de866fcc | 2723 | #define PPCCHLK PPC_OPCODE_CACHELCK |
23976049 | 2724 | #define PPCRFMCI PPC_OPCODE_RFMCI |
19a6653c | 2725 | #define E500MC PPC_OPCODE_E500MC |
634b50f2 | 2726 | #define PPCA2 PPC_OPCODE_A2 |
ce3d2015 | 2727 | #define TITAN PPC_OPCODE_TITAN |
b9c361e0 | 2728 | #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE |
e01d869a | 2729 | #define E500 PPC_OPCODE_E500 |
aea77599 | 2730 | #define E6500 PPC_OPCODE_E6500 |
b9c361e0 | 2731 | #define PPCVLE PPC_OPCODE_VLE |
5817ffd1 | 2732 | #define PPCHTM PPC_OPCODE_HTM |
252b5132 RH |
2733 | \f |
2734 | /* The opcode table. | |
2735 | ||
2736 | The format of the opcode table is: | |
2737 | ||
8ebac3aa | 2738 | NAME OPCODE MASK FLAGS ANTI {OPERANDS} |
252b5132 RH |
2739 | |
2740 | NAME is the name of the instruction. | |
2741 | OPCODE is the instruction opcode. | |
2742 | MASK is the opcode mask; this is used to tell the disassembler | |
2743 | which bits in the actual opcode must match OPCODE. | |
8ebac3aa AM |
2744 | FLAGS are flags indicating which processors support the instruction. |
2745 | ANTI indicates which processors don't support the instruction. | |
252b5132 RH |
2746 | OPERANDS is the list of operands. |
2747 | ||
2748 | The disassembler reads the table in order and prints the first | |
2749 | instruction which matches, so this table is sorted to put more | |
de866fcc AM |
2750 | specific instructions before more general instructions. |
2751 | ||
2752 | This table must be sorted by major opcode. Please try to keep it | |
2753 | vaguely sorted within major opcode too, except of course where | |
2754 | constrained otherwise by disassembler operation. */ | |
252b5132 RH |
2755 | |
2756 | const struct powerpc_opcode powerpc_opcodes[] = { | |
9fe54b1c | 2757 | {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}}, |
1cb0a767 PB |
2758 | {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, |
2759 | {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2760 | {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2761 | {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2762 | {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2763 | {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2764 | {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2765 | {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2766 | {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2767 | {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2768 | {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2769 | {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2770 | {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2771 | {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
2772 | {"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}}, | |
2773 | ||
2774 | {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2775 | {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2776 | {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2777 | {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2778 | {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2779 | {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2780 | {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2781 | {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2782 | {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2783 | {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2784 | {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2785 | {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2786 | {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2787 | {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2788 | {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2789 | {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2790 | {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2791 | {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2792 | {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2793 | {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2794 | {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2795 | {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2796 | {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2797 | {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2798 | {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2799 | {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2800 | {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
2801 | {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
2802 | {"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}}, | |
2803 | {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}}, | |
2804 | ||
2805 | {"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, | |
b9c361e0 JL |
2806 | {"vaddubm", VX (4, 0), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2807 | {"vmaxub", VX (4, 2), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2808 | {"vrlb", VX (4, 4), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2809 | {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2810 | {"vmuloub", VX (4, 8), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2811 | {"vaddfp", VX (4, 10), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
1cb0a767 | 2812 | {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, |
b9c361e0 | 2813 | {"vmrghb", VX (4, 12), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
1cb0a767 | 2814 | {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, |
b9c361e0 JL |
2815 | {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2816 | {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2817 | {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 PB |
2818 | {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, |
2819 | {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2820 | {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2821 | {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2822 | {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
b9c361e0 | 2823 | {"machhwu", XO (4, 12,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 2824 | {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, |
b9c361e0 | 2825 | {"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 PB |
2826 | {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, |
2827 | {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
2828 | {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2829 | {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2830 | {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2831 | {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
b9c361e0 JL |
2832 | {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
2833 | {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, | |
2834 | {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, | |
1cb0a767 | 2835 | {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
b9c361e0 | 2836 | {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
1cb0a767 | 2837 | {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
b9c361e0 JL |
2838 | {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
2839 | {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, | |
2840 | {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, | |
1cb0a767 | 2841 | {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
b9c361e0 | 2842 | {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
1cb0a767 | 2843 | {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
b9c361e0 | 2844 | {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
1cb0a767 | 2845 | {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
b9c361e0 | 2846 | {"vsel", VXA(4, 42), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
1cb0a767 | 2847 | {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
b9c361e0 | 2848 | {"vperm", VXA(4, 43), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
382c72e9 | 2849 | {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}}, |
1cb0a767 | 2850 | {"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, |
b9c361e0 | 2851 | {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}}, |
1cb0a767 | 2852 | {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, |
b9c361e0 | 2853 | {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}}, |
1cb0a767 PB |
2854 | {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, |
2855 | {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
2856 | {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
2857 | {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
2858 | {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
2859 | {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
2860 | {"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2861 | {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2862 | {"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2863 | {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2864 | {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2865 | {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2866 | {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2867 | {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
2868 | {"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, | |
b9c361e0 JL |
2869 | {"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2870 | {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2871 | {"vrlh", VX (4, 68), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2872 | {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2873 | {"vmulouh", VX (4, 72), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2874 | {"vsubfp", VX (4, 74), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
1cb0a767 | 2875 | {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, |
b9c361e0 | 2876 | {"vmrghh", VX (4, 76), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
1cb0a767 | 2877 | {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, |
b9c361e0 | 2878 | {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
1cb0a767 | 2879 | {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, |
b9c361e0 | 2880 | {"mulhhw", XRC(4, 40,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 2881 | {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, |
b9c361e0 JL |
2882 | {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
2883 | {"machhw", XO (4, 44,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2884 | {"machhw.", XO (4, 44,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2885 | {"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2886 | {"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 2887 | {"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, |
b9c361e0 JL |
2888 | {"vadduwm", VX (4, 128), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2889 | {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2890 | {"vrlw", VX (4, 132), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2891 | {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2892 | {"vmrghw", VX (4, 140), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2893 | {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
1cb0a767 PB |
2894 | {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, |
2895 | {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
b9c361e0 JL |
2896 | {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
2897 | {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 2898 | {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, |
b9c361e0 JL |
2899 | {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2900 | {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2901 | {"machhws", XO (4, 108,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2902 | {"machhws.", XO (4, 108,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2903 | {"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2904 | {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
b9c361e0 JL |
2905 | {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2906 | {"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2907 | {"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
fb048c26 | 2908 | {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
2909 | {"vmrglb", VX (4, 268), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2910 | {"vpkshus", VX (4, 270), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
1cb0a767 | 2911 | {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, |
b9c361e0 | 2912 | {"mulchwu", XRC(4, 136,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 2913 | {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, |
b9c361e0 JL |
2914 | {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
2915 | {"macchwu", XO (4, 140,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2916 | {"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
b9c361e0 JL |
2917 | {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2918 | {"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2919 | {"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
fb048c26 | 2920 | {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
2921 | {"vmrglh", VX (4, 332), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2922 | {"vpkswus", VX (4, 334), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
03edbe3b JL |
2923 | {"mulchw", XRC(4, 168,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
2924 | {"mulchw.", XRC(4, 168,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2925 | {"macchw", XO (4, 172,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2926 | {"macchw.", XO (4, 172,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2927 | {"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2928 | {"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
b9c361e0 JL |
2929 | {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2930 | {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2931 | {"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
fb048c26 | 2932 | {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
2933 | {"vmrglw", VX (4, 396), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2934 | {"vpkshss", VX (4, 398), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2935 | {"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2936 | {"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2937 | {"vsl", VX (4, 452), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2938 | {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
fb048c26 | 2939 | {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
2940 | {"vpkswss", VX (4, 462), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2941 | {"macchws", XO (4, 236,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2942 | {"macchws.", XO (4, 236,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2943 | {"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2944 | {"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
2945 | {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2946 | {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2947 | {"evaddiw", VX (4, 514), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB, UIMM}}, | |
2948 | {"vminub", VX (4, 514), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2949 | {"evsubfw", VX (4, 516), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
1cb0a767 | 2950 | {"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}}, |
b9c361e0 JL |
2951 | {"vsrb", VX (4, 516), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2952 | {"evsubifw", VX (4, 518), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, UIMM, RB}}, | |
1cb0a767 | 2953 | {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, |
b9c361e0 JL |
2954 | {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
2955 | {"evabs", VX (4, 520), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
2956 | {"vmuleub", VX (4, 520), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
2957 | {"evneg", VX (4, 521), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
2958 | {"evextsb", VX (4, 522), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
fb048c26 | 2959 | {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
2960 | {"evextsh", VX (4, 523), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, |
2961 | {"evrndw", VX (4, 524), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
fb048c26 | 2962 | {"vspltb", VX (4, 524), VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM4}}, |
b9c361e0 JL |
2963 | {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, |
2964 | {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
fb048c26 | 2965 | {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 | 2966 | {"brinc", VX (4, 527), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
1cb0a767 PB |
2967 | {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, |
2968 | {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
b9c361e0 JL |
2969 | {"evand", VX (4, 529), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
2970 | {"evandc", VX (4, 530), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2971 | {"evxor", VX (4, 534), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2972 | {"evmr", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}}, | |
2973 | {"evor", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2974 | {"evnor", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2975 | {"evnot", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}}, | |
1cb0a767 | 2976 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, |
b9c361e0 JL |
2977 | {"eveqv", VX (4, 537), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
2978 | {"evorc", VX (4, 539), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2979 | {"evnand", VX (4, 542), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2980 | {"evsrwu", VX (4, 544), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2981 | {"evsrws", VX (4, 545), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2982 | {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, | |
2983 | {"evsrwis", VX (4, 547), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, | |
2984 | {"evslw", VX (4, 548), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2985 | {"evslwi", VX (4, 550), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, | |
2986 | {"evrlw", VX (4, 552), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2987 | {"evsplati", VX (4, 553), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}}, | |
2988 | {"evrlwi", VX (4, 554), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, | |
2989 | {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}}, | |
2990 | {"evmergehi", VX (4, 556), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2991 | {"evmergelo", VX (4, 557), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2992 | {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2993 | {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
2994 | {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
2995 | {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
2996 | {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
2997 | {"evcmplts", VX (4, 563), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
2998 | {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
1cb0a767 | 2999 | {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, |
b9c361e0 JL |
3000 | {"vadduhs", VX (4, 576), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3001 | {"vminuh", VX (4, 578), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3002 | {"vsrh", VX (4, 580), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3003 | {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3004 | {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
fb048c26 PB |
3005 | {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
3006 | {"vsplth", VX (4, 588), VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM3}}, | |
3007 | {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, | |
1cb0a767 | 3008 | {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, |
b9c361e0 | 3009 | {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB, CRFS}}, |
1cb0a767 | 3010 | {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, |
b9c361e0 JL |
3011 | {"evfsadd", VX (4, 640), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3012 | {"vadduws", VX (4, 640), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3013 | {"evfssub", VX (4, 641), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3014 | {"vminuw", VX (4, 642), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3015 | {"evfsabs", VX (4, 644), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3016 | {"vsrw", VX (4, 644), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3017 | {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3018 | {"evfsneg", VX (4, 646), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3019 | {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3020 | {"evfsmul", VX (4, 648), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3021 | {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
fb048c26 | 3022 | {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 | 3023 | {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, |
fb048c26 | 3024 | {"vspltw", VX (4, 652), VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM2}}, |
b9c361e0 JL |
3025 | {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, |
3026 | {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
fb048c26 | 3027 | {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
3028 | {"evfscfui", VX (4, 656), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, |
3029 | {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
3030 | {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
3031 | {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
3032 | {"evfsctui", VX (4, 660), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
3033 | {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
3034 | {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
3035 | {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
3036 | {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, | |
1cb0a767 | 3037 | {"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, |
b9c361e0 JL |
3038 | {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, |
3039 | {"evfststgt", VX (4, 668), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3040 | {"evfststlt", VX (4, 669), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3041 | {"evfststeq", VX (4, 670), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
1cb0a767 | 3042 | {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, |
b9c361e0 JL |
3043 | {"efsadd", VX (4, 704), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3044 | {"efssub", VX (4, 705), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3045 | {"efsabs", VX (4, 708), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, | |
3046 | {"vsr", VX (4, 708), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3047 | {"efsnabs", VX (4, 709), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, | |
3048 | {"efsneg", VX (4, 710), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, | |
3049 | {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3050 | {"efsmul", VX (4, 712), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3051 | {"efsdiv", VX (4, 713), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
fb048c26 | 3052 | {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
3053 | {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, |
3054 | {"efscmplt", VX (4, 717), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3055 | {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
fb048c26 | 3056 | {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
3057 | {"efscfd", VX (4, 719), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, |
3058 | {"efscfui", VX (4, 720), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3059 | {"efscfsi", VX (4, 721), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3060 | {"efscfuf", VX (4, 722), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3061 | {"efscfsf", VX (4, 723), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3062 | {"efsctui", VX (4, 724), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3063 | {"efsctsi", VX (4, 725), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3064 | {"efsctuf", VX (4, 726), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3065 | {"efsctsf", VX (4, 727), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3066 | {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
1cb0a767 | 3067 | {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, |
b9c361e0 JL |
3068 | {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, |
3069 | {"efststgt", VX (4, 732), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3070 | {"efststlt", VX (4, 733), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3071 | {"efststeq", VX (4, 734), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3072 | {"efdadd", VX (4, 736), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3073 | {"efdsub", VX (4, 737), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3074 | {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3075 | {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3076 | {"efdabs", VX (4, 740), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, | |
3077 | {"efdnabs", VX (4, 741), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, | |
3078 | {"efdneg", VX (4, 742), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, | |
3079 | {"efdmul", VX (4, 744), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3080 | {"efddiv", VX (4, 745), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3081 | {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3082 | {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3083 | {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3084 | {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3085 | {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3086 | {"efdcfs", VX (4, 751), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3087 | {"efdcfui", VX (4, 752), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3088 | {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3089 | {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3090 | {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3091 | {"efdctui", VX (4, 756), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3092 | {"efdctsi", VX (4, 757), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3093 | {"efdctuf", VX (4, 758), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3094 | {"efdctsf", VX (4, 759), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
3095 | {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, | |
1cb0a767 | 3096 | {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, |
b9c361e0 JL |
3097 | {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, |
3098 | {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3099 | {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3100 | {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, | |
3101 | {"evlddx", VX (4, 768), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3102 | {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3103 | {"evldd", VX (4, 769), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
3104 | {"evldwx", VX (4, 770), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3105 | {"vminsb", VX (4, 770), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3106 | {"evldw", VX (4, 771), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
3107 | {"evldhx", VX (4, 772), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3108 | {"vsrab", VX (4, 772), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3109 | {"evldh", VX (4, 773), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
3110 | {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3111 | {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3112 | {"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3113 | {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, | |
3114 | {"vcfux", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, | |
c7a5aa9c | 3115 | {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, |
b9c361e0 | 3116 | {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
fb048c26 | 3117 | {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, |
b9c361e0 JL |
3118 | {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, |
3119 | {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3120 | {"vpkpx", VX (4, 782), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3121 | {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, | |
3122 | {"mullhwu", XRC(4, 392,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3123 | {"evlwhex", VX (4, 784), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3124 | {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3125 | {"evlwhe", VX (4, 785), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3126 | {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3127 | {"evlwhou", VX (4, 789), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3128 | {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3129 | {"evlwhos", VX (4, 791), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3130 | {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3131 | {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3132 | {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3133 | {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3134 | {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3135 | {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3136 | {"evstddx", VX (4, 800), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3137 | {"evstdd", VX (4, 801), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
3138 | {"evstdwx", VX (4, 802), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3139 | {"evstdw", VX (4, 803), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
3140 | {"evstdhx", VX (4, 804), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3141 | {"evstdh", VX (4, 805), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
3142 | {"evstwhex", VX (4, 816), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3143 | {"evstwhe", VX (4, 817), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3144 | {"evstwhox", VX (4, 820), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3145 | {"evstwho", VX (4, 821), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3146 | {"evstwwex", VX (4, 824), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3147 | {"evstwwe", VX (4, 825), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3148 | {"evstwwox", VX (4, 828), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3149 | {"evstwwo", VX (4, 829), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
3150 | {"vaddshs", VX (4, 832), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3151 | {"vminsh", VX (4, 834), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3152 | {"vsrah", VX (4, 836), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3153 | {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3154 | {"vmulesh", VX (4, 840), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3155 | {"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, | |
c7a5aa9c | 3156 | {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, |
fb048c26 PB |
3157 | {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, |
3158 | {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, | |
b9c361e0 JL |
3159 | {"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
3160 | {"mullhw.", XRC(4, 424,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3161 | {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3162 | {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3163 | {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3164 | {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3165 | {"vaddsws", VX (4, 896), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3166 | {"vminsw", VX (4, 898), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3167 | {"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3168 | {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3169 | {"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, | |
c7a5aa9c | 3170 | {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, |
fb048c26 | 3171 | {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, |
b9c361e0 JL |
3172 | {"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
3173 | {"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3174 | {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3175 | {"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, | |
ab4437c3 | 3176 | {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, |
fb048c26 | 3177 | {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, |
b9c361e0 JL |
3178 | {"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
3179 | {"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3180 | {"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3181 | {"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3182 | {"vsububm", VX (4,1024), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3183 | {"vavgub", VX (4,1026), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
e67ed0e8 | 3184 | {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, |
b9c361e0 JL |
3185 | {"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3186 | {"vand", VX (4,1028), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3187 | {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3188 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3189 | {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3190 | {"evmhossf", VX (4,1031), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3191 | {"evmheumi", VX (4,1032), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3192 | {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3193 | {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3194 | {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3195 | {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3196 | {"vslo", VX (4,1036), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3197 | {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3198 | {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3199 | {"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3200 | {"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 PB |
3201 | {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
3202 | {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
b9c361e0 JL |
3203 | {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3204 | {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3205 | {"evmheumia", VX (4,1064), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3206 | {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3207 | {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3208 | {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3209 | {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3210 | {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3211 | {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3212 | {"vavguh", VX (4,1090), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
e67ed0e8 | 3213 | {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, |
b9c361e0 JL |
3214 | {"vandc", VX (4,1092), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3215 | {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3216 | {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3217 | {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3218 | {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3219 | {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3220 | {"vminfp", VX (4,1098), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3221 | {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3222 | {"vsro", VX (4,1100), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3223 | {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3224 | {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3225 | {"evmwssf", VX (4,1107), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3226 | {"machhwo", XO (4, 44,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3227 | {"evmwumi", VX (4,1112), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3228 | {"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3229 | {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3230 | {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3231 | {"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3232 | {"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 PB |
3233 | {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
3234 | {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
b9c361e0 JL |
3235 | {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3236 | {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3237 | {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3238 | {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3239 | {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3240 | {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3241 | {"evmwumia", VX (4,1144), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3242 | {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3243 | {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3244 | {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3245 | {"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
e67ed0e8 | 3246 | {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, |
c7a5aa9c | 3247 | {"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}}, |
b9c361e0 JL |
3248 | {"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3249 | {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3250 | {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3251 | {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3252 | {"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
3253 | {"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 PB |
3254 | {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
3255 | {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
b9c361e0 JL |
3256 | {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, |
3257 | {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3258 | {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3259 | {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3260 | {"evmra", VX (4,1220), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3261 | {"vxor", VX (4,1220), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3262 | {"evdivws", VX (4,1222), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3263 | {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3264 | {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3265 | {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3266 | {"evdivwu", VX (4,1223), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3267 | {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3268 | {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3269 | {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3270 | {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, | |
3271 | {"machhwso", XO (4, 108,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3272 | {"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3273 | {"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3274 | {"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 PB |
3275 | {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
3276 | {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
b9c361e0 JL |
3277 | {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3278 | {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3279 | {"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3280 | {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3281 | {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
c7a5aa9c | 3282 | {"vnot", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}}, |
b9c361e0 JL |
3283 | {"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3284 | {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
9fe54b1c PB |
3285 | {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3286 | {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3287 | {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3288 | {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3289 | {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3290 | {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3291 | {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3292 | {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3293 | {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3294 | {"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3295 | {"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3296 | {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3297 | {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3298 | {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3299 | {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3300 | {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3301 | {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3302 | {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3303 | {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3304 | {"vavgsh", VX (4,1346), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3305 | {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3306 | {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3307 | {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3308 | {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3309 | {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3310 | {"macchwo", XO (4, 172,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3311 | {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3312 | {"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3313 | {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3314 | {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3315 | {"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3316 | {"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3317 | {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3318 | {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3319 | {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3320 | {"vavgsw", VX (4,1410), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3321 | {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3322 | {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3323 | {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
9fe54b1c PB |
3324 | {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3325 | {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3326 | {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3327 | {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3328 | {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3329 | {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3330 | {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3331 | {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3332 | {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3333 | {"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3334 | {"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3335 | {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3336 | {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3337 | {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3338 | {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3339 | {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3340 | {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3341 | {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3342 | {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3343 | {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3344 | {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3345 | {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3346 | {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, |
3347 | {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3348 | {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3349 | {"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3350 | {"evmwumian", VX (4,1496), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3351 | {"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3352 | {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3353 | {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, | |
3354 | {"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3355 | {"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3356 | {"vsububs", VX (4,1536), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
fb048c26 | 3357 | {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD}}, |
b9c361e0 | 3358 | {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
9fe54b1c PB |
3359 | {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3360 | {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3361 | {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3362 | {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
fb048c26 | 3363 | {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VB}}, |
b9c361e0 JL |
3364 | {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3365 | {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3366 | {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3367 | {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3368 | {"vsubuws", VX (4,1664), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3369 | {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3370 | {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3371 | {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3372 | {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3373 | {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3374 | {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3375 | {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3376 | {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3377 | {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3378 | {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3379 | {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3380 | {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3381 | {"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3382 | {"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3383 | {"vsubshs", VX (4,1856), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3384 | {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3385 | {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3386 | {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3387 | {"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
3388 | {"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3389 | {"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3390 | {"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3391 | {"vsubsws", VX (4,1920), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
3392 | {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, | |
9fe54b1c PB |
3393 | {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3394 | {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3395 | {"vsumsws", VX (4,1928), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, |
3396 | {"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3397 | {"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 3398 | {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, |
9fe54b1c PB |
3399 | {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3400 | {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, | |
b9c361e0 JL |
3401 | {"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, |
3402 | {"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3403 | {"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
3404 | {"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 PB |
3405 | {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}}, |
3406 | ||
3407 | {"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
3408 | {"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
3409 | ||
3410 | {"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
3411 | {"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
3412 | ||
3413 | {"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}}, | |
3414 | ||
3415 | {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}}, | |
3416 | {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}}, | |
3417 | {"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}}, | |
bdc70b4a | 3418 | {"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}}, |
1cb0a767 PB |
3419 | |
3420 | {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}}, | |
3421 | {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}}, | |
3422 | {"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}}, | |
bdc70b4a | 3423 | {"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}}, |
1cb0a767 PB |
3424 | |
3425 | {"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
3426 | {"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
3427 | {"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, | |
3428 | ||
3429 | {"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
3430 | {"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
3431 | {"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, | |
3432 | ||
3433 | {"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}}, | |
3434 | {"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}}, | |
3435 | {"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}}, | |
3436 | {"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
3437 | {"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, | |
3438 | {"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, | |
3439 | ||
3440 | {"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}}, | |
3441 | {"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}}, | |
3442 | {"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, | |
3443 | {"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, | |
3444 | {"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, | |
3445 | ||
3446 | {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
3447 | {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
3448 | {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, | |
3449 | {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, | |
3450 | {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
3451 | {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
3452 | {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, | |
3453 | {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, | |
3454 | {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
3455 | {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
3456 | {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, | |
3457 | {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, | |
3458 | {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
3459 | {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
3460 | {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, | |
3461 | {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, | |
3462 | {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
3463 | {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
3464 | {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}}, | |
3465 | {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
3466 | {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
3467 | {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}}, | |
3468 | {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
3469 | {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
3470 | {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}}, | |
3471 | {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
3472 | {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
3473 | {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}}, | |
3474 | ||
3475 | {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3476 | {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3477 | {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3478 | {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3479 | {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3480 | {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3481 | {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3482 | {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3483 | {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3484 | {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3485 | {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3486 | {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3487 | {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3488 | {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3489 | {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3490 | {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3491 | {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3492 | {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3493 | {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3494 | {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3495 | {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3496 | {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3497 | {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3498 | {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3499 | {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3500 | {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3501 | {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3502 | {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3503 | {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3504 | {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3505 | {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3506 | {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3507 | {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3508 | {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3509 | {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3510 | {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3511 | {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3512 | {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3513 | {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3514 | {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3515 | {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3516 | {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3517 | {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3518 | {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3519 | {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3520 | {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3521 | {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3522 | {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3523 | {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3524 | {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3525 | {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3526 | {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3527 | {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3528 | {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3529 | {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3530 | {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3531 | {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3532 | {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3533 | {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3534 | {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3535 | {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3536 | {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3537 | {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3538 | {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3539 | {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3540 | {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
3541 | {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3542 | {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3543 | {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3544 | {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3545 | {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3546 | {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
3547 | {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3548 | {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3549 | {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3550 | {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3551 | {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3552 | {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
3553 | {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3554 | {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3555 | {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3556 | {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3557 | {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3558 | {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
3559 | ||
3560 | {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3561 | {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3562 | {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3563 | {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3564 | {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3565 | {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3566 | {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3567 | {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3568 | {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3569 | {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3570 | {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3571 | {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3572 | {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3573 | {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3574 | {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3575 | {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3576 | {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3577 | {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3578 | {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3579 | {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3580 | {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3581 | {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3582 | {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3583 | {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3584 | {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3585 | {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3586 | {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3587 | {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3588 | {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3589 | {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3590 | {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3591 | {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3592 | {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3593 | {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3594 | {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3595 | {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3596 | {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3597 | {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3598 | {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3599 | {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3600 | {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3601 | {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
3602 | {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3603 | {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3604 | {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
3605 | {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
3606 | {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
3607 | {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
3608 | {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3609 | {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3610 | {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3611 | {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3612 | {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3613 | {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
3614 | {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3615 | {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3616 | {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
3617 | {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
3618 | {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
3619 | {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
3620 | ||
8ebac3aa AM |
3621 | {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3622 | {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3623 | {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3624 | {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3625 | {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3626 | {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3627 | {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3628 | {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 | 3629 | {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
8ebac3aa AM |
3630 | {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3631 | {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 | 3632 | {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
8ebac3aa AM |
3633 | {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3634 | {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3635 | {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3636 | {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3637 | {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3638 | {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3639 | {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3640 | {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 | 3641 | {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
8ebac3aa AM |
3642 | {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3643 | {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 PB |
3644 | {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
3645 | ||
3646 | {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
3647 | {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
3648 | {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
3649 | {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
3650 | {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
3651 | {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
3652 | {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
3653 | {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
3654 | {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
3655 | {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
3656 | {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
3657 | {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
3658 | {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
3659 | {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
3660 | {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
3661 | {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
3662 | ||
8ebac3aa AM |
3663 | {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3664 | {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3665 | {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3666 | {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3667 | {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3668 | {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3669 | {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3670 | {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 | 3671 | {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
8ebac3aa AM |
3672 | {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3673 | {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 | 3674 | {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
8ebac3aa AM |
3675 | {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3676 | {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3677 | {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3678 | {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}}, |
3679 | {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}}, | |
1cb0a767 | 3680 | {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, |
8ebac3aa AM |
3681 | {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3682 | {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 | 3683 | {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
8ebac3aa AM |
3684 | {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}}, |
3685 | {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}}, | |
1cb0a767 PB |
3686 | {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, |
3687 | ||
3688 | {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
3689 | {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
3690 | {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
3691 | {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
3692 | {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
3693 | {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
3694 | {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
3695 | {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
3696 | {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
3697 | {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
3698 | {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
3699 | {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
3700 | {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
3701 | {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
3702 | {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
3703 | {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
3704 | ||
3705 | {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, | |
3706 | {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, | |
3707 | {"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}}, | |
3708 | {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, | |
3709 | {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, | |
3710 | {"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}}, | |
3711 | {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, | |
3712 | {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, | |
3713 | {"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, | |
3714 | {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, | |
3715 | {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, | |
3716 | {"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, | |
3717 | ||
3718 | {"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, | |
3719 | {"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, | |
3720 | {"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}}, | |
3721 | {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}}, | |
3722 | {"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}}, | |
3723 | ||
3724 | {"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}}, | |
3725 | {"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}}, | |
3726 | {"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}}, | |
3727 | {"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}}, | |
3728 | ||
3729 | {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, | |
3730 | ||
3731 | {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
8ebac3aa | 3732 | {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, |
1cb0a767 | 3733 | {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, |
8ebac3aa AM |
3734 | {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, |
3735 | {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, | |
3736 | {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, | |
1cb0a767 | 3737 | {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, |
8ebac3aa | 3738 | {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, |
1cb0a767 | 3739 | {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, |
8ebac3aa AM |
3740 | {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, |
3741 | {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, | |
3742 | {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, | |
1cb0a767 PB |
3743 | {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, |
3744 | {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, | |
3745 | {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
3746 | {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, | |
8ebac3aa AM |
3747 | {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, |
3748 | {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, | |
3749 | {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, | |
3750 | {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, | |
3751 | {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, | |
3752 | {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, | |
3753 | {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, | |
3754 | {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}}, | |
1cb0a767 PB |
3755 | |
3756 | {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3757 | {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3758 | {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3759 | {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3760 | {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3761 | {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3762 | {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3763 | {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3764 | {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3765 | {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3766 | {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3767 | {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3768 | {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3769 | {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3770 | {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3771 | {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3772 | {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3773 | {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3774 | {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3775 | {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3776 | {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3777 | {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3778 | {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3779 | {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3780 | {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3781 | {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3782 | {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3783 | {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3784 | {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3785 | {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3786 | {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3787 | {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3788 | {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3789 | {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3790 | {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 3791 | {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 3792 | {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3793 | {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3794 | {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa AM |
3795 | {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
3796 | {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3797 | {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3798 | {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3799 | {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3800 | {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3801 | {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3802 | {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3803 | {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3804 | {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3805 | {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3806 | {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3807 | {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3808 | {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3809 | {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3810 | {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3811 | {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3812 | {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3813 | {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3814 | {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3815 | {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3816 | {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3817 | {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3818 | {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3819 | {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3820 | {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3821 | {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3822 | {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3823 | {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3824 | {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3825 | {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3826 | {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3827 | {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3828 | {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3829 | {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3830 | {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3831 | {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3832 | {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3833 | {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3834 | {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3835 | {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3836 | {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3837 | {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
1cb0a767 | 3838 | {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 3839 | {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3840 | {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3841 | {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3842 | {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3843 | {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3844 | {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3845 | {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3846 | {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3847 | {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3848 | {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3849 | {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3850 | {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3851 | {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3852 | {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3853 | {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3854 | {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3855 | {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3856 | {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3857 | {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3858 | {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3859 | {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 3860 | {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 3861 | {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 3862 | {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 PB |
3863 | {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, |
3864 | {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa AM |
3865 | {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
3866 | {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3867 | {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3868 | {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3869 | {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3870 | {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3871 | {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3872 | {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3873 | {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3874 | {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3875 | {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
3876 | {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3877 | {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3878 | {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3879 | {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3880 | {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3881 | {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3882 | {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3883 | {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3884 | {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3885 | {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3886 | {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3887 | {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3888 | {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3889 | {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3890 | {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3891 | {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3892 | {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3893 | {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3894 | {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
3895 | {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
1cb0a767 PB |
3896 | |
3897 | {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
8ebac3aa | 3898 | {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 3899 | {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
3900 | {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
3901 | {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
3902 | {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
1cb0a767 | 3903 | {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa | 3904 | {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 3905 | {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
3906 | {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
3907 | {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
3908 | {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
1cb0a767 | 3909 | {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa | 3910 | {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 PB |
3911 | {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, |
3912 | {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
8ebac3aa | 3913 | {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 3914 | {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
3915 | {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
3916 | {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
3917 | {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
3918 | {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
3919 | {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
3920 | {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
1cb0a767 | 3921 | {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa | 3922 | {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 3923 | {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
3924 | {"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
3925 | {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
3926 | {"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
1cb0a767 | 3927 | {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa | 3928 | {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 3929 | {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
3930 | {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
3931 | {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
3932 | {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
1cb0a767 | 3933 | {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa | 3934 | {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 PB |
3935 | {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, |
3936 | {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
8ebac3aa | 3937 | {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 3938 | {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
3939 | {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
3940 | {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
3941 | {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
3942 | {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
3943 | {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
3944 | {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
1cb0a767 PB |
3945 | |
3946 | {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
3947 | {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
3948 | {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
3949 | {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
3950 | {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
3951 | {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
3952 | {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
3953 | {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
3954 | ||
3955 | {"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}}, | |
3956 | ||
3957 | {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, | |
3958 | {"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
9fe54b1c | 3959 | {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}}, |
1cb0a767 PB |
3960 | |
3961 | {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}}, | |
3962 | {"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}}, | |
9fe54b1c | 3963 | {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}}, |
1cb0a767 PB |
3964 | |
3965 | {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}}, | |
3966 | ||
e0d602ec | 3967 | {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}}, |
1cb0a767 PB |
3968 | |
3969 | {"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
3970 | ||
3971 | {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}}, | |
3972 | {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}}, | |
3973 | ||
3974 | {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, | |
3975 | {"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
3976 | ||
3977 | {"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}}, | |
3978 | ||
3979 | {"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
3980 | ||
3981 | {"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
3982 | ||
9fe54b1c | 3983 | {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476, {0}}, |
1cb0a767 PB |
3984 | |
3985 | {"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, | |
3986 | {"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
3987 | ||
3988 | {"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}}, | |
3989 | ||
3990 | {"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
3991 | ||
3992 | {"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}}, | |
3993 | ||
3994 | {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, | |
3995 | {"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
3996 | ||
3997 | {"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}}, | |
3998 | {"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}}, | |
3999 | ||
4000 | {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}}, | |
4001 | {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}}, | |
4002 | ||
4003 | {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
8ebac3aa | 4004 | {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4005 | {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4006 | {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4007 | {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4008 | {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4009 | {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4010 | {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4011 | {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4012 | {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4013 | {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4014 | {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4015 | {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4016 | {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4017 | {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4018 | {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4019 | {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4020 | {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4021 | {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4022 | {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4023 | {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4024 | {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4025 | {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4026 | {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4027 | {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4028 | {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4029 | {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa AM |
4030 | {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
4031 | {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4032 | {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4033 | {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4034 | {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4035 | {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4036 | {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4037 | {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4038 | {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4039 | {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4040 | {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4041 | {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4042 | {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4043 | {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4044 | {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4045 | {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4046 | {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4047 | {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4048 | {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4049 | {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4050 | {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4051 | {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4052 | {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4053 | {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4054 | {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4055 | {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4056 | {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4057 | {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4058 | {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4059 | {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4060 | {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4061 | {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4062 | {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4063 | {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4064 | {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4065 | {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4066 | {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4067 | {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4068 | {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4069 | {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4070 | {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4071 | {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4072 | {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
1cb0a767 | 4073 | {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4074 | {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4075 | {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4076 | {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4077 | {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4078 | {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4079 | {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4080 | {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4081 | {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4082 | {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4083 | {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4084 | {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4085 | {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4086 | {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4087 | {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4088 | {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4089 | {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa | 4090 | {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
1cb0a767 | 4091 | {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, |
8ebac3aa AM |
4092 | {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, |
4093 | {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4094 | {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4095 | {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4096 | {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4097 | {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4098 | {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4099 | {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4100 | {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4101 | {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4102 | {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}}, | |
4103 | {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4104 | {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4105 | {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4106 | {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4107 | {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4108 | {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4109 | {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4110 | {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4111 | {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4112 | {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4113 | {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4114 | {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4115 | {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4116 | {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4117 | {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4118 | {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4119 | {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4120 | {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4121 | {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
4122 | {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}}, | |
1cb0a767 PB |
4123 | |
4124 | {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
8ebac3aa | 4125 | {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 4126 | {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
4127 | {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
4128 | {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
4129 | {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
4130 | {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
4131 | {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
4132 | {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
4133 | {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
1cb0a767 | 4134 | {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa | 4135 | {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
1cb0a767 | 4136 | {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, |
8ebac3aa AM |
4137 | {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, |
4138 | {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
4139 | {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}}, | |
4140 | {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
4141 | {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
4142 | {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
4143 | {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}}, | |
1cb0a767 PB |
4144 | |
4145 | {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
4146 | {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
4147 | {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
4148 | {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
4149 | {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
4150 | {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
4151 | {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
4152 | {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
4153 | ||
4154 | {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4155 | {"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4156 | ||
4157 | {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4158 | {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4159 | ||
4160 | {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, | |
4161 | {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, | |
4162 | {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4163 | {"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4164 | {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, | |
4165 | {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, | |
4166 | {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4167 | {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
4168 | ||
4169 | {"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
4170 | {"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
4171 | ||
4172 | {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
4173 | {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
4174 | {"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
4175 | {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
4176 | {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
4177 | {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
4178 | ||
4179 | {"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}}, | |
4180 | {"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
4181 | {"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
4182 | ||
4183 | {"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
4184 | {"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
4185 | ||
9f6a6cc0 | 4186 | {"xnop", OP(26), 0xffffffff, PPCCOM, PPCNONE, {0}}, |
1cb0a767 PB |
4187 | {"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, |
4188 | {"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
4189 | ||
4190 | {"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
4191 | {"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
4192 | ||
4193 | {"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
4194 | {"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
4195 | ||
4196 | {"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
4197 | {"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
4198 | ||
4199 | {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, | |
4200 | {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, | |
4201 | {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
4202 | {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, | |
4203 | {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, | |
4204 | {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
4205 | ||
4206 | {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, | |
4207 | {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, | |
4208 | ||
4209 | {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
4210 | {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
4211 | ||
4212 | {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
4213 | {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
4214 | ||
4215 | {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
4216 | {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, | |
4217 | {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
4218 | {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, | |
4219 | ||
4220 | {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, | |
4221 | {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, | |
4222 | ||
4223 | {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, | |
4224 | {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, | |
b9c361e0 | 4225 | {"cmp", X(31,0), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}}, |
bdc70b4a | 4226 | {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
1cb0a767 | 4227 | |
b9c361e0 | 4228 | {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4229 | {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4230 | {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4231 | {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4232 | {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4233 | {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4234 | {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4235 | {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4236 | {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4237 | {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4238 | {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4239 | {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4240 | {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4241 | {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4242 | {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4243 | {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4244 | {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4245 | {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4246 | {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4247 | {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4248 | {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4249 | {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4250 | {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4251 | {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4252 | {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4253 | {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 | 4254 | {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 4255 | {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, |
b9c361e0 JL |
4256 | {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM|PPCVLE, PPCNONE, {0}}, |
4257 | {"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}}, | |
1cb0a767 PB |
4258 | {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}}, |
4259 | ||
03edbe3b JL |
4260 | {"lvsl", X(31,6), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}}, |
4261 | {"lvebx", X(31,7), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}}, | |
1cb0a767 PB |
4262 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
4263 | ||
b9c361e0 | 4264 | {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4265 | {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 JL |
4266 | {"subc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, |
4267 | {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 4268 | {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 JL |
4269 | {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, |
4270 | ||
4271 | {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
4272 | {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
4273 | ||
4274 | {"addc", XO(31,10,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 4275 | {"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 4276 | {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 PB |
4277 | {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
4278 | ||
b9c361e0 JL |
4279 | {"mulhwu", XO(31,11,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
4280 | {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 4281 | |
c7a8dbf9 | 4282 | {"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}}, |
1cb0a767 | 4283 | |
e0d602ec BE |
4284 | {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}}, |
4285 | {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}}, | |
4286 | {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}}, | |
4287 | {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}}, | |
858d7a6d | 4288 | |
1cb0a767 | 4289 | {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}}, |
b9c361e0 | 4290 | {"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}}, |
03edbe3b | 4291 | {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}}, |
1cb0a767 | 4292 | |
b9c361e0 JL |
4293 | {"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, |
4294 | ||
4295 | {"ldx", X(31,21), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}}, | |
4296 | ||
c7a8dbf9 | 4297 | {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}}, |
b9c361e0 JL |
4298 | |
4299 | {"lwzx", X(31,23), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}}, | |
1cb0a767 | 4300 | {"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
de866fcc | 4301 | |
b9c361e0 | 4302 | {"slw", XRC(31,24,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 4303 | {"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, |
b9c361e0 | 4304 | {"slw.", XRC(31,24,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 4305 | {"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, |
de866fcc | 4306 | |
b9c361e0 | 4307 | {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, |
1cb0a767 | 4308 | {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, |
b9c361e0 | 4309 | {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, |
1cb0a767 | 4310 | {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, |
de866fcc | 4311 | |
1cb0a767 PB |
4312 | {"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, |
4313 | {"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
de866fcc | 4314 | |
b9c361e0 JL |
4315 | {"and", XRC(31,28,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
4316 | {"and.", XRC(31,28,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
de866fcc | 4317 | |
e0d602ec BE |
4318 | {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, |
4319 | {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, | |
de866fcc | 4320 | |
c7a8dbf9 AS |
4321 | {"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
4322 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, | |
de866fcc | 4323 | |
b9c361e0 | 4324 | {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, RB}}, |
1cb0a767 | 4325 | {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, |
b9c361e0 | 4326 | {"cmpl", X(31,32), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}}, |
bdc70b4a | 4327 | {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
de866fcc | 4328 | |
03edbe3b JL |
4329 | {"lvsr", X(31,38), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}}, |
4330 | {"lvehx", X(31,39), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}}, | |
1cb0a767 | 4331 | {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
de866fcc | 4332 | |
e67ed0e8 AM |
4333 | {"mviwsplt", X(31,46), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}}, |
4334 | ||
c7a8dbf9 | 4335 | {"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}}, |
de866fcc | 4336 | |
03edbe3b | 4337 | {"lvewx", X(31,71), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}}, |
de866fcc | 4338 | |
066be9f7 PB |
4339 | {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}}, |
4340 | ||
c7a8dbf9 | 4341 | {"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}}, |
de866fcc | 4342 | |
03edbe3b | 4343 | {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}}, |
de866fcc | 4344 | |
b9c361e0 JL |
4345 | {"subf", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
4346 | {"sub", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}}, | |
4347 | {"subf.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
4348 | {"sub.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}}, | |
de866fcc | 4349 | |
e0d602ec BE |
4350 | {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}}, |
4351 | ||
03edbe3b | 4352 | {"lbarx", X(31,52), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, |
066be9f7 | 4353 | |
b9c361e0 JL |
4354 | {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, |
4355 | ||
c7a8dbf9 | 4356 | {"dcbst", X(31,54), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}}, |
b9c361e0 JL |
4357 | |
4358 | {"lwzux", X(31,55), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RAL, RB}}, | |
1cb0a767 | 4359 | {"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
de866fcc | 4360 | |
b9c361e0 JL |
4361 | {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, |
4362 | {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, | |
de866fcc | 4363 | |
b9c361e0 JL |
4364 | {"andc", XRC(31,60,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
4365 | {"andc.", XRC(31,60,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
de866fcc | 4366 | |
e0d602ec BE |
4367 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}}, |
4368 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}}, | |
b9c361e0 JL |
4369 | {"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}}, |
4370 | ||
c7a8dbf9 | 4371 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}}, |
19a6653c | 4372 | |
1cb0a767 PB |
4373 | {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, |
4374 | {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4375 | {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4376 | {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4377 | {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4378 | {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4379 | {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4380 | {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4381 | {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4382 | {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4383 | {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4384 | {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4385 | {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
4386 | {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
b9c361e0 | 4387 | {"td", X(31,68), X_MASK, PPC64|PPCVLE, PPCNONE, {TO, RA, RB}}, |
de866fcc | 4388 | |
1cb0a767 | 4389 | {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
b9c361e0 JL |
4390 | {"mulhd", XO(31,73,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, |
4391 | {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
4392 | ||
4393 | {"mulhw", XO(31,75,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
4394 | {"mulhw.", XO(31,75,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
de866fcc | 4395 | |
03edbe3b JL |
4396 | {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}}, |
4397 | {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
de866fcc | 4398 | |
1cb0a767 | 4399 | {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}}, |
de866fcc | 4400 | |
b9c361e0 JL |
4401 | {"mfmsr", X(31,83), XRARB_MASK, COM|PPCVLE, PPCNONE, {RT}}, |
4402 | ||
4403 | {"ldarx", X(31,84), XEH_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, | |
de866fcc | 4404 | |
c7a8dbf9 AS |
4405 | {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, |
4406 | {"dcbf", X(31,86), XLRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB, L}}, | |
de866fcc | 4407 | |
b9c361e0 JL |
4408 | {"lbzx", X(31,87), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
4409 | ||
c7a8dbf9 | 4410 | {"lbepx", X(31,95), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
de866fcc | 4411 | |
aea77599 AM |
4412 | {"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}}, |
4413 | ||
03edbe3b | 4414 | {"lvx", X(31,103), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}}, |
1cb0a767 | 4415 | {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
de866fcc | 4416 | |
b9c361e0 JL |
4417 | {"neg", XO(31,104,0,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}}, |
4418 | {"neg.", XO(31,104,0,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}}, | |
de866fcc | 4419 | |
1cb0a767 PB |
4420 | {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, |
4421 | {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
de866fcc | 4422 | |
aea77599 AM |
4423 | {"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}}, |
4424 | ||
1cb0a767 | 4425 | {"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, |
de866fcc | 4426 | |
03edbe3b | 4427 | {"lharx", X(31,116), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, |
066be9f7 | 4428 | |
1cb0a767 | 4429 | {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, |
de866fcc | 4430 | |
b9c361e0 JL |
4431 | {"lbzux", X(31,119), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}}, |
4432 | ||
4433 | {"popcntb", X(31,122), XRB_MASK, POWER5|PPCVLE, PPCNONE, {RA, RS}}, | |
de866fcc | 4434 | |
1cb0a767 | 4435 | {"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, |
b9c361e0 | 4436 | {"nor", XRC(31,124,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 4437 | {"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, |
b9c361e0 | 4438 | {"nor.", XRC(31,124,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
19a6653c | 4439 | |
c7a8dbf9 | 4440 | {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}}, |
b9c361e0 JL |
4441 | |
4442 | {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}}, | |
4443 | ||
c7a8dbf9 | 4444 | {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}}, |
de866fcc | 4445 | |
c7a8dbf9 | 4446 | {"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}}, |
1cb0a767 | 4447 | {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
de866fcc | 4448 | |
b9c361e0 | 4449 | {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4450 | {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 4451 | {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4452 | {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
de866fcc | 4453 | |
b9c361e0 | 4454 | {"adde", XO(31,138,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4455 | {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 4456 | {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4457 | {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
de866fcc | 4458 | |
c7a8dbf9 | 4459 | {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, |
de866fcc | 4460 | |
1cb0a767 | 4461 | {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}}, |
03edbe3b JL |
4462 | {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}}, |
4463 | {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}}, | |
de866fcc | 4464 | |
b9c361e0 | 4465 | {"mtmsr", X(31,146), XRLARB_MASK, COM|PPCVLE, PPCNONE, {RS, A_L}}, |
de866fcc | 4466 | |
e0d602ec BE |
4467 | {"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, |
4468 | {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, | |
4469 | ||
b9c361e0 JL |
4470 | {"stdx", X(31,149), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
4471 | ||
4472 | {"stwcx.", XRC(31,150,1), X_MASK, PPC|PPCVLE, PPCNONE, {RS, RA0, RB}}, | |
4473 | ||
4474 | {"stwx", X(31,151), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}}, | |
1cb0a767 | 4475 | {"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}}, |
de866fcc | 4476 | |
1cb0a767 PB |
4477 | {"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
4478 | {"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
de866fcc | 4479 | |
1cb0a767 PB |
4480 | {"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
4481 | {"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
de866fcc | 4482 | |
9fe54b1c | 4483 | {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}}, |
de866fcc | 4484 | |
c7a8dbf9 | 4485 | {"stdepx", X(31,157), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
b9c361e0 | 4486 | |
c7a8dbf9 | 4487 | {"stwepx", X(31,159), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
b9c361e0 JL |
4488 | |
4489 | {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}}, | |
4490 | ||
c7a8dbf9 | 4491 | {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}}, |
de866fcc | 4492 | |
c7a8dbf9 | 4493 | {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}}, |
1cb0a767 | 4494 | {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
de866fcc | 4495 | |
c7a8dbf9 | 4496 | {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, |
de866fcc | 4497 | |
1cb0a767 | 4498 | {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}}, |
de866fcc | 4499 | |
e0d602ec BE |
4500 | {"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}}, |
4501 | ||
b9c361e0 | 4502 | {"stdux", X(31,181), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RAS, RB}}, |
de866fcc | 4503 | |
e0d602ec BE |
4504 | {"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}}, |
4505 | ||
b9c361e0 | 4506 | {"stwux", X(31,183), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RAS, RB}}, |
1cb0a767 | 4507 | {"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, |
de866fcc | 4508 | |
1cb0a767 PB |
4509 | {"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, |
4510 | {"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
de866fcc | 4511 | |
e0d602ec | 4512 | {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}}, |
252b5132 | 4513 | |
aea77599 AM |
4514 | {"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, |
4515 | ||
c7a8dbf9 | 4516 | {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}}, |
1cb0a767 | 4517 | {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
252b5132 | 4518 | |
b9c361e0 | 4519 | {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 4520 | {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
b9c361e0 | 4521 | {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 4522 | {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
252b5132 | 4523 | |
b9c361e0 | 4524 | {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 4525 | {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
b9c361e0 | 4526 | {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 4527 | {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
418c1742 | 4528 | |
b9c361e0 | 4529 | {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}}, |
19a6653c | 4530 | |
bdc70b4a | 4531 | {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, |
418c1742 | 4532 | |
e0d602ec BE |
4533 | {"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}}, |
4534 | ||
4535 | {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, | |
4536 | ||
b9c361e0 JL |
4537 | {"stdcx.", XRC(31,214,1), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
4538 | ||
4539 | {"stbx", X(31,215), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}}, | |
252b5132 | 4540 | |
1cb0a767 PB |
4541 | {"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
4542 | {"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 4543 | |
1cb0a767 PB |
4544 | {"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
4545 | {"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 4546 | |
c7a8dbf9 | 4547 | {"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
b9c361e0 | 4548 | |
c7a8dbf9 | 4549 | {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}}, |
7d5b217e | 4550 | |
03edbe3b | 4551 | {"stvx", X(31,231), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}}, |
1cb0a767 | 4552 | {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
f509565f | 4553 | |
b9c361e0 | 4554 | {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 4555 | {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
b9c361e0 | 4556 | {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 4557 | {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
252b5132 | 4558 | |
b9c361e0 JL |
4559 | {"mulld", XO(31,233,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, |
4560 | {"mulld.", XO(31,233,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
4561 | ||
4562 | {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, | |
1cb0a767 | 4563 | {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
b9c361e0 | 4564 | {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 4565 | {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
252b5132 | 4566 | |
b9c361e0 | 4567 | {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4568 | {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 4569 | {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4570 | {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
252b5132 | 4571 | |
e0d602ec | 4572 | {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, |
b9c361e0 | 4573 | {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}}, |
bdc70b4a AM |
4574 | {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, |
4575 | {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, | |
418c1742 | 4576 | |
c7a8dbf9 AS |
4577 | {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}}, |
4578 | {"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}}, | |
4579 | {"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}}, | |
b9c361e0 JL |
4580 | |
4581 | {"stbux", X(31,247), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}}, | |
252b5132 | 4582 | |
1cb0a767 PB |
4583 | {"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, |
4584 | {"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
252b5132 | 4585 | |
e0d602ec | 4586 | {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}}, |
066be9f7 | 4587 | |
03edbe3b | 4588 | {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
19a6653c | 4589 | |
b9c361e0 | 4590 | {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}}, |
e0d602ec | 4591 | {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}}, |
252b5132 | 4592 | |
aea77599 AM |
4593 | {"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
4594 | ||
1cb0a767 | 4595 | {"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}}, |
1ed8e1e4 | 4596 | |
03edbe3b | 4597 | {"lvepxl", X(31,263), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}}, |
aea77599 | 4598 | |
1cb0a767 PB |
4599 | {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
4600 | {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
4601 | {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
252b5132 | 4602 | |
b9c361e0 | 4603 | {"add", XO(31,266,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4604 | {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 4605 | {"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 4606 | {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
418c1742 | 4607 | |
03edbe3b | 4608 | {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}}, |
19a6653c | 4609 | |
9fe54b1c | 4610 | {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}}, |
418c1742 | 4611 | |
ce3d2015 | 4612 | {"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}}, |
1cb0a767 PB |
4613 | |
4614 | {"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
4615 | {"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
4616 | ||
c7a8dbf9 AS |
4617 | {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}}, |
4618 | {"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}}, | |
4619 | {"dcbt", X(31,278), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}}, | |
b9c361e0 JL |
4620 | |
4621 | {"lhzx", X(31,279), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}}, | |
1cb0a767 | 4622 | |
066be9f7 PB |
4623 | {"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, |
4624 | ||
b9c361e0 JL |
4625 | {"eqv", XRC(31,284,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
4626 | {"eqv.", XRC(31,284,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
1cb0a767 | 4627 | |
03edbe3b | 4628 | {"lhepx", X(31,287), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
1cb0a767 | 4629 | |
b9c361e0 | 4630 | {"mfdcrux", X(31,291), X_MASK, PPC464|PPCVLE, PPCNONE, {RS, RA}}, |
1cb0a767 | 4631 | |
aea77599 | 4632 | {"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
03edbe3b | 4633 | {"lvepx", X(31,295), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}}, |
aea77599 | 4634 | |
ce3d2015 | 4635 | {"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}}, |
1cb0a767 PB |
4636 | {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, |
4637 | ||
c7a8dbf9 | 4638 | {"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA0, RB}}, |
1cb0a767 | 4639 | |
b9c361e0 | 4640 | {"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}}, |
1cb0a767 | 4641 | |
066be9f7 PB |
4642 | {"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, |
4643 | ||
b9c361e0 JL |
4644 | {"xor", XRC(31,316,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
4645 | {"xor.", XRC(31,316,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
1cb0a767 | 4646 | |
03edbe3b | 4647 | {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
1cb0a767 PB |
4648 | |
4649 | {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4650 | {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4651 | {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4652 | {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4653 | {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4654 | {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4655 | {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4656 | {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4657 | {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4658 | {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4659 | {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4660 | {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4661 | {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4662 | {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4663 | {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4664 | {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4665 | {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4666 | {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4667 | {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4668 | {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4669 | {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4670 | {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4671 | {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4672 | {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4673 | {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4674 | {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4675 | {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4676 | {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4677 | {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4678 | {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4679 | {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4680 | {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4681 | {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4682 | {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
b9c361e0 | 4683 | {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}}, |
e0d602ec | 4684 | {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}}, |
1cb0a767 | 4685 | |
aea77599 AM |
4686 | {"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
4687 | ||
c7a8dbf9 | 4688 | {"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA0, RB}}, |
9fe54b1c | 4689 | |
1cb0a767 PB |
4690 | {"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, |
4691 | {"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
4692 | ||
c7a8dbf9 | 4693 | {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, |
066be9f7 | 4694 | |
b9c361e0 | 4695 | {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}}, |
aea77599 | 4696 | {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}}, |
1cb0a767 PB |
4697 | |
4698 | {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, | |
b9c361e0 | 4699 | {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, |
ce3d2015 AM |
4700 | {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, |
4701 | {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, | |
1cb0a767 | 4702 | {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}}, |
b9c361e0 JL |
4703 | {"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, |
4704 | {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, | |
1cb0a767 | 4705 | {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}}, |
ce3d2015 AM |
4706 | {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, |
4707 | {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, | |
bdc70b4a | 4708 | {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, |
1cb0a767 | 4709 | {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}}, |
ce3d2015 | 4710 | {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, |
1cb0a767 PB |
4711 | {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}}, |
4712 | {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}}, | |
4713 | {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}}, | |
b9c361e0 JL |
4714 | {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, |
4715 | {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4716 | {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4717 | {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4718 | {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4719 | {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
1cb0a767 PB |
4720 | {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}}, |
4721 | {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4722 | {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4723 | {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4724 | {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4725 | {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4726 | {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4727 | {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4728 | {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4729 | {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4730 | {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4731 | {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4732 | {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4733 | {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4734 | {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4735 | {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4736 | {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}}, | |
b9c361e0 JL |
4737 | {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, |
4738 | {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {RT, SPRG}}, | |
4739 | {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4740 | {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4741 | {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4742 | {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4743 | {"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4744 | {"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4745 | {"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4746 | {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, | |
4747 | {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, | |
4748 | {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, | |
4749 | {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, | |
1cb0a767 | 4750 | {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}}, |
ce3d2015 | 4751 | {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, |
b9c361e0 JL |
4752 | {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, |
4753 | {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, | |
4754 | {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4755 | {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4756 | {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4757 | {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4758 | {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4759 | {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4760 | {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4761 | {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4762 | {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4763 | {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4764 | {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4765 | {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4766 | {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4767 | {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4768 | {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4769 | {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4770 | {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4771 | {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4772 | {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4773 | {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4774 | {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4775 | {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4776 | {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4777 | {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4778 | {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4779 | {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4780 | {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4781 | {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4782 | {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
4783 | {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, | |
1cb0a767 PB |
4784 | {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, |
4785 | {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, | |
4786 | {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, | |
4787 | {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, | |
ce3d2015 | 4788 | {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
1cb0a767 | 4789 | {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, |
ce3d2015 | 4790 | {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
1cb0a767 PB |
4791 | {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, |
4792 | {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}}, | |
ce3d2015 AM |
4793 | {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
4794 | {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, | |
1cb0a767 PB |
4795 | {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}}, |
4796 | {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4797 | {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4798 | {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4799 | {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4800 | {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4801 | {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, | |
4802 | {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, | |
4803 | {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, | |
ce3d2015 | 4804 | {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, |
1cb0a767 PB |
4805 | {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}}, |
4806 | {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4807 | {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4808 | {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4809 | {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4810 | {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4811 | {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4812 | {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4813 | {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4814 | {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4815 | {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4816 | {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4817 | {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4818 | {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4819 | {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4820 | {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4821 | {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4822 | {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4823 | {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4824 | {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4825 | {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
4826 | {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
ce3d2015 AM |
4827 | {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, PPCNONE, {RT}}, |
4828 | {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
4829 | {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
4830 | {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
4831 | {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
4832 | {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
c7a5aa9c PB |
4833 | {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, PPCNONE, {RT}}, |
4834 | {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, PPCNONE, {RT}}, | |
ce3d2015 AM |
4835 | {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}}, |
4836 | {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
4837 | {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
4838 | {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, PPCNONE, {RT}}, | |
1cb0a767 PB |
4839 | {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}}, |
4840 | {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4841 | {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4842 | {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4843 | {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4844 | {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4845 | {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4846 | {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4847 | {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
ce3d2015 AM |
4848 | {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, PPCNONE, {RT}}, |
4849 | {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RT}}, | |
1cb0a767 PB |
4850 | {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}}, |
4851 | {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
4852 | {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
4853 | {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
4854 | {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4855 | {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4856 | {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4857 | {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4858 | {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4859 | {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4860 | {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
4861 | {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4862 | {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
4863 | {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
4864 | {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4865 | {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
ce3d2015 | 4866 | {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE, {RT}}, |
1cb0a767 PB |
4867 | {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}}, |
4868 | {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4869 | {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4870 | {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4871 | {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4872 | {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4873 | {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4874 | {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4875 | {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4876 | {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4877 | {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4878 | {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4879 | {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
ce3d2015 | 4880 | {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, PPCNONE, {RS}}, |
1cb0a767 PB |
4881 | {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}}, |
4882 | {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4883 | {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4884 | {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4885 | {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4886 | {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4887 | {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4888 | {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4889 | {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4890 | {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4891 | {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4892 | {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4893 | {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
4894 | {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
4895 | {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
b9c361e0 JL |
4896 | {"mfspr", X(31,339), X_MASK, COM|PPCVLE, PPCNONE, {RT, SPR}}, |
4897 | ||
4898 | {"lwax", X(31,341), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}}, | |
1cb0a767 PB |
4899 | |
4900 | {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, | |
4901 | ||
b9c361e0 | 4902 | {"lhax", X(31,343), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
1cb0a767 | 4903 | |
03edbe3b | 4904 | {"lvxl", X(31,359), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}}, |
1cb0a767 PB |
4905 | |
4906 | {"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
4907 | {"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
4908 | ||
4909 | {"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
4910 | {"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
4911 | ||
ce3d2015 | 4912 | {"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}}, |
1cb0a767 | 4913 | |
bdc70b4a AM |
4914 | {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}}, |
4915 | {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}}, | |
4916 | {"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}}, | |
1cb0a767 | 4917 | |
b9c361e0 | 4918 | {"lwaux", X(31,373), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, |
1cb0a767 PB |
4919 | |
4920 | {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, | |
4921 | ||
b9c361e0 | 4922 | {"lhaux", X(31,375), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}}, |
1cb0a767 | 4923 | |
e0d602ec | 4924 | {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}}, |
066be9f7 | 4925 | |
03edbe3b JL |
4926 | {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}}, |
4927 | {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}}, | |
1cb0a767 | 4928 | |
aea77599 AM |
4929 | {"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
4930 | ||
c7a8dbf9 | 4931 | {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}}, |
1cb0a767 PB |
4932 | {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
4933 | ||
51b5d4a8 AM |
4934 | {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, |
4935 | {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
4936 | {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
4937 | {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
066be9f7 | 4938 | |
aea77599 | 4939 | {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
1cb0a767 PB |
4940 | |
4941 | {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, | |
4942 | ||
2f7f7710 AM |
4943 | {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}}, |
4944 | {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}}, | |
e0d602ec | 4945 | |
b9c361e0 | 4946 | {"sthx", X(31,407), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
1cb0a767 | 4947 | |
b9c361e0 JL |
4948 | {"orc", XRC(31,412,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
4949 | {"orc.", XRC(31,412,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
1cb0a767 | 4950 | |
c7a8dbf9 | 4951 | {"sthepx", X(31,415), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
1cb0a767 | 4952 | |
b9c361e0 | 4953 | {"mtdcrux", X(31,419), X_MASK, PPC464|PPCVLE, PPCNONE, {RA, RS}}, |
1cb0a767 | 4954 | |
aea77599 AM |
4955 | {"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
4956 | ||
4957 | {"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, | |
4958 | ||
51b5d4a8 AM |
4959 | {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, |
4960 | {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
4961 | {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
4962 | {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
066be9f7 | 4963 | |
1cb0a767 PB |
4964 | {"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}}, |
4965 | ||
c7a8dbf9 | 4966 | {"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA0, RB}}, |
1cb0a767 | 4967 | |
b9c361e0 | 4968 | {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}}, |
1cb0a767 PB |
4969 | |
4970 | {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}}, | |
4971 | ||
aea77599 AM |
4972 | {"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}}, |
4973 | ||
9f6a6cc0 PB |
4974 | /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for |
4975 | "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ | |
4976 | {"yield", 0x7f7bdb78, 0xffffffff, POWER7, PPCNONE, {0}}, | |
4977 | {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, PPCNONE, {0}}, | |
4978 | {"mdoom", 0x7fdef378, 0xffffffff, POWER7, PPCNONE, {0}}, | |
b9c361e0 JL |
4979 | {"mr", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}}, |
4980 | {"or", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
4981 | {"mr.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}}, | |
4982 | {"or.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
1cb0a767 PB |
4983 | |
4984 | {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4985 | {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4986 | {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4987 | {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4988 | {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4989 | {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4990 | {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4991 | {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4992 | {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4993 | {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4994 | {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4995 | {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4996 | {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4997 | {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4998 | {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
4999 | {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5000 | {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5001 | {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5002 | {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5003 | {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5004 | {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5005 | {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5006 | {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5007 | {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5008 | {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5009 | {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5010 | {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5011 | {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5012 | {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5013 | {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5014 | {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5015 | {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5016 | {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5017 | {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
b9c361e0 | 5018 | {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}}, |
e0d602ec | 5019 | {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}}, |
1cb0a767 | 5020 | |
aea77599 AM |
5021 | {"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
5022 | ||
cee62821 | 5023 | {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, |
b9c361e0 JL |
5024 | {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}}, |
5025 | ||
5026 | {"divdu", XO(31,457,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
5027 | {"divdu.", XO(31,457,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 5028 | |
03edbe3b JL |
5029 | {"divwu", XO(31,459,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
5030 | {"divwu.", XO(31,459,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 5031 | |
03edbe3b | 5032 | {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}}, |
aea77599 | 5033 | {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}}, |
1cb0a767 PB |
5034 | |
5035 | {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, | |
b9c361e0 JL |
5036 | {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, |
5037 | {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, | |
5038 | {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, | |
1cb0a767 | 5039 | {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}}, |
ce3d2015 AM |
5040 | {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, |
5041 | {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, | |
5042 | {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, | |
5043 | {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, | |
1cb0a767 PB |
5044 | {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}}, |
5045 | {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}}, | |
ce3d2015 | 5046 | {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, |
b9c361e0 JL |
5047 | {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, |
5048 | {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, | |
1cb0a767 | 5049 | {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}}, |
b9c361e0 JL |
5050 | {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, |
5051 | {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5052 | {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5053 | {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5054 | {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5055 | {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5056 | {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
1cb0a767 PB |
5057 | {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}}, |
5058 | {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5059 | {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5060 | {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5061 | {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5062 | {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5063 | {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5064 | {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5065 | {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5066 | {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5067 | {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5068 | {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5069 | {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5070 | {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5071 | {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5072 | {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
5073 | {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}}, | |
b9c361e0 JL |
5074 | {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, |
5075 | {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {SPRG, RS}}, | |
5076 | {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, | |
5077 | {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, | |
5078 | {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, | |
5079 | {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, | |
5080 | {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5081 | {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5082 | {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5083 | {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, | |
1cb0a767 | 5084 | {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}}, |
ce3d2015 | 5085 | {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, |
1cb0a767 PB |
5086 | {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}}, |
5087 | {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
b9c361e0 JL |
5088 | {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, |
5089 | {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5090 | {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5091 | {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5092 | {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5093 | {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5094 | {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5095 | {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5096 | {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5097 | {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5098 | {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5099 | {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5100 | {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5101 | {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5102 | {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5103 | {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5104 | {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5105 | {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5106 | {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5107 | {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5108 | {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5109 | {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5110 | {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5111 | {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5112 | {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5113 | {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5114 | {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5115 | {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5116 | {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
5117 | {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, | |
1cb0a767 PB |
5118 | {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, |
5119 | {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, | |
5120 | {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, | |
5121 | {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, | |
ce3d2015 | 5122 | {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
1cb0a767 | 5123 | {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, |
ce3d2015 | 5124 | {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
1cb0a767 PB |
5125 | {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, |
5126 | {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}}, | |
ce3d2015 AM |
5127 | {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
5128 | {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, | |
b9c361e0 JL |
5129 | {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}}, |
5130 | {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}}, | |
1cb0a767 | 5131 | {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, |
ce3d2015 AM |
5132 | {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}}, |
5133 | {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}}, | |
5134 | {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, PPCNONE, {RS}}, | |
5135 | {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}}, | |
5136 | {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}}, | |
5137 | {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}}, | |
c7a5aa9c PB |
5138 | {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, PPCNONE, {RS}}, |
5139 | {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, PPCNONE, {RS}}, | |
1cb0a767 PB |
5140 | {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}}, |
5141 | {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5142 | {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5143 | {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5144 | {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5145 | {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5146 | {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5147 | {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5148 | {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
ce3d2015 AM |
5149 | {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, PPCNONE, {RS}}, |
5150 | {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RS}}, | |
1cb0a767 PB |
5151 | {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}}, |
5152 | {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
5153 | {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
5154 | {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
5155 | {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5156 | {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5157 | {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5158 | {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5159 | {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5160 | {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5161 | {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
5162 | {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5163 | {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
5164 | {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
5165 | {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5166 | {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5167 | {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5168 | {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5169 | {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5170 | {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5171 | {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5172 | {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5173 | {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5174 | {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5175 | {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5176 | {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5177 | {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5178 | {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5179 | {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
ce3d2015 | 5180 | {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, PPCNONE, {RS}}, |
1cb0a767 PB |
5181 | {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}}, |
5182 | {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5183 | {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5184 | {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5185 | {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5186 | {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5187 | {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5188 | {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5189 | {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5190 | {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5191 | {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5192 | {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5193 | {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5194 | {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
5195 | {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
5196 | {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
b9c361e0 JL |
5197 | {"mtspr", X(31,467), X_MASK, COM|PPCVLE, PPCNONE, {SPR, RS}}, |
5198 | ||
c7a8dbf9 | 5199 | {"dcbi", X(31,470), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}}, |
1cb0a767 | 5200 | |
b9c361e0 JL |
5201 | {"nand", XRC(31,476,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
5202 | {"nand.", XRC(31,476,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, | |
1cb0a767 | 5203 | |
03edbe3b | 5204 | {"dsn", X(31,483), XRT_MASK, E500MC|PPCVLE, PPCNONE, {RA, RB}}, |
1cb0a767 | 5205 | |
03edbe3b | 5206 | {"dcread", X(31,486), X_MASK, PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}}, |
1cb0a767 | 5207 | |
c7a8dbf9 | 5208 | {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}}, |
1cb0a767 | 5209 | |
03edbe3b | 5210 | {"stvxl", X(31,487), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}}, |
1cb0a767 PB |
5211 | |
5212 | {"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
5213 | {"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
5214 | ||
03edbe3b JL |
5215 | {"divd", XO(31,489,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, |
5216 | {"divd.", XO(31,489,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 5217 | |
03edbe3b JL |
5218 | {"divw", XO(31,491,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
5219 | {"divw.", XO(31,491,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 5220 | |
aea77599 | 5221 | {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
1cb0a767 PB |
5222 | |
5223 | {"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}}, | |
5224 | ||
5225 | {"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}}, | |
5226 | ||
e0d602ec | 5227 | {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}}, |
066be9f7 | 5228 | |
9fe54b1c | 5229 | {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 5230 | |
03edbe3b | 5231 | {"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7, {BF}}, |
252b5132 | 5232 | |
03edbe3b | 5233 | {"lbdx", X(31,515), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
19a6653c | 5234 | |
1cb0a767 | 5235 | {"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}}, |
252b5132 | 5236 | |
1cb0a767 PB |
5237 | {"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, |
5238 | {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
252b5132 | 5239 | |
b9c361e0 | 5240 | {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5241 | {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 JL |
5242 | {"subco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, |
5243 | {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 5244 | {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 JL |
5245 | {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, |
5246 | ||
5247 | {"addco", XO(31,10,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
1cb0a767 | 5248 | {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 5249 | {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5250 | {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5251 | |
1cb0a767 | 5252 | {"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}}, |
418c1742 | 5253 | |
e0d602ec | 5254 | {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}}, |
418c1742 | 5255 | |
8baf7b78 | 5256 | {"lswx", X(31,533), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, RBX}}, |
1cb0a767 | 5257 | {"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5258 | |
b9c361e0 | 5259 | {"lwbrx", X(31,534), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
1cb0a767 | 5260 | {"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5261 | |
e01d869a | 5262 | {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
702f0fb4 | 5263 | |
b9c361e0 | 5264 | {"srw", XRC(31,536,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 5265 | {"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, |
b9c361e0 | 5266 | {"srw.", XRC(31,536,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 5267 | {"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, |
252b5132 | 5268 | |
1cb0a767 PB |
5269 | {"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5270 | {"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
23976049 | 5271 | |
1cb0a767 PB |
5272 | {"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, |
5273 | {"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
f509565f | 5274 | |
1cb0a767 PB |
5275 | {"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5276 | {"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 5277 | |
03edbe3b | 5278 | {"lhdx", X(31,547), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
19a6653c | 5279 | |
aea77599 AM |
5280 | {"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
5281 | ||
1cb0a767 | 5282 | {"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}}, |
418c1742 | 5283 | |
1cb0a767 PB |
5284 | {"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, |
5285 | {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
252b5132 | 5286 | |
1cb0a767 PB |
5287 | {"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, |
5288 | {"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
5289 | {"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
5290 | {"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
252b5132 | 5291 | |
b9c361e0 | 5292 | {"tlbsync", X(31,566), 0xffffffff, PPC|PPCVLE, PPCNONE, {0}}, |
252b5132 | 5293 | |
e01d869a | 5294 | {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 5295 | |
03edbe3b | 5296 | {"lwdx", X(31,579), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
19a6653c | 5297 | |
aea77599 AM |
5298 | {"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
5299 | ||
1cb0a767 | 5300 | {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
081ba1b3 | 5301 | |
c7a8dbf9 | 5302 | {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, |
066be9f7 | 5303 | |
bdc70b4a | 5304 | {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, |
252b5132 | 5305 | |
8baf7b78 | 5306 | {"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, NBI}}, |
1cb0a767 | 5307 | {"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}}, |
252b5132 | 5308 | |
e01d869a | 5309 | {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, |
1cb0a767 | 5310 | {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, |
aea77599 | 5311 | {"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}}, |
b9c361e0 | 5312 | {"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}}, |
9fe54b1c | 5313 | {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, |
aea77599 | 5314 | {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, |
e01d869a | 5315 | {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, |
1cb0a767 | 5316 | {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}}, |
418c1742 | 5317 | |
e01d869a | 5318 | {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
23976049 | 5319 | |
066be9f7 | 5320 | {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, |
c7a8dbf9 | 5321 | {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}}, |
252b5132 | 5322 | |
03edbe3b | 5323 | {"lddx", X(31,611), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}}, |
19a6653c | 5324 | |
aea77599 AM |
5325 | {"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
5326 | ||
1cb0a767 | 5327 | {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
081ba1b3 | 5328 | |
03edbe3b JL |
5329 | {"nego", XO(31,104,1,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}}, |
5330 | {"nego.", XO(31,104,1,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}}, | |
252b5132 | 5331 | |
1cb0a767 PB |
5332 | {"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, |
5333 | {"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
252b5132 | 5334 | |
81a0b7e2 | 5335 | {"mfsri", X(31,627), X_MASK, M601, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5336 | |
81a0b7e2 | 5337 | {"dclst", X(31,630), XRB_MASK, M601, PPCNONE, {RS, RA}}, |
252b5132 | 5338 | |
e01d869a | 5339 | {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 5340 | |
1cb0a767 | 5341 | {"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, |
19a6653c | 5342 | |
1cb0a767 PB |
5343 | {"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, |
5344 | {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
23976049 | 5345 | |
5817ffd1 PB |
5346 | {"tbegin.", XRC(31,654,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {HTM_R}}, |
5347 | ||
b9c361e0 | 5348 | {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5349 | {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 5350 | {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5351 | {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5352 | |
b9c361e0 | 5353 | {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5354 | {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 5355 | {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5356 | {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5357 | |
bdc70b4a | 5358 | {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, |
418c1742 | 5359 | |
e0d602ec | 5360 | {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}}, |
252b5132 | 5361 | |
b9c361e0 | 5362 | {"stswx", X(31,661), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, RB}}, |
1cb0a767 | 5363 | {"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, |
418c1742 | 5364 | |
b9c361e0 | 5365 | {"stwbrx", X(31,662), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}}, |
1cb0a767 | 5366 | {"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, |
252b5132 | 5367 | |
e01d869a | 5368 | {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
ede602d7 | 5369 | |
1cb0a767 PB |
5370 | {"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5371 | {"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 5372 | |
1cb0a767 PB |
5373 | {"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5374 | {"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 5375 | |
1cb0a767 | 5376 | {"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, |
19a6653c | 5377 | |
aea77599 AM |
5378 | {"stvfrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
5379 | ||
1cb0a767 PB |
5380 | {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, |
5381 | {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
252b5132 | 5382 | |
5817ffd1 PB |
5383 | {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}}, |
5384 | {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}}, | |
5385 | ||
066be9f7 PB |
5386 | {"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, |
5387 | ||
e01d869a | 5388 | {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 5389 | |
1cb0a767 PB |
5390 | {"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, |
5391 | {"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
252b5132 | 5392 | |
1cb0a767 | 5393 | {"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, |
19a6653c | 5394 | |
aea77599 AM |
5395 | {"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
5396 | ||
1cb0a767 | 5397 | {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
081ba1b3 | 5398 | |
c7a8dbf9 | 5399 | {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, |
066be9f7 | 5400 | |
5817ffd1 PB |
5401 | {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, PPCNONE, {BF}}, |
5402 | ||
b9c361e0 | 5403 | {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 5404 | {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
b9c361e0 | 5405 | {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 5406 | {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
418c1742 | 5407 | |
b9c361e0 | 5408 | {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 5409 | {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
b9c361e0 | 5410 | {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 5411 | {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
fdd12ef3 | 5412 | |
b9c361e0 | 5413 | {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}}, |
1cb0a767 | 5414 | {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, |
252b5132 | 5415 | |
066be9f7 PB |
5416 | {"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, |
5417 | ||
e01d869a | 5418 | {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
252b5132 | 5419 | |
1cb0a767 PB |
5420 | {"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5421 | {"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
418c1742 | 5422 | |
1cb0a767 PB |
5423 | {"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5424 | {"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 5425 | |
066be9f7 | 5426 | {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, |
c7a8dbf9 | 5427 | {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRS, RA0, RB}}, |
252b5132 | 5428 | |
1cb0a767 | 5429 | {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, |
19a6653c | 5430 | |
aea77599 AM |
5431 | {"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
5432 | ||
1cb0a767 | 5433 | {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |
081ba1b3 | 5434 | |
1cb0a767 PB |
5435 | {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, |
5436 | {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
5437 | {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
5438 | {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
252b5132 | 5439 | |
b9c361e0 JL |
5440 | {"mulldo", XO(31,233,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, |
5441 | {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
252b5132 | 5442 | |
03edbe3b | 5443 | {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 5444 | {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
03edbe3b | 5445 | {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, |
1cb0a767 | 5446 | {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, |
418c1742 | 5447 | |
03edbe3b | 5448 | {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5449 | {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
03edbe3b | 5450 | {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5451 | {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
702f0fb4 | 5452 | |
5817ffd1 PB |
5453 | {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, |
5454 | {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, | |
5455 | {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {L}}, | |
5456 | ||
03edbe3b | 5457 | {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}}, |
c7a8dbf9 | 5458 | {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA0, RB}}, |
252b5132 | 5459 | |
e01d869a | 5460 | {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 5461 | |
1cb0a767 PB |
5462 | {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, |
5463 | {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
252b5132 | 5464 | |
aea77599 AM |
5465 | {"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
5466 | {"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, | |
1cb0a767 PB |
5467 | {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, |
5468 | {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
ede602d7 | 5469 | |
1cb0a767 PB |
5470 | {"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, |
5471 | {"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
252b5132 | 5472 | |
b9c361e0 | 5473 | {"addo", XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5474 | {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
b9c361e0 | 5475 | {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, |
1cb0a767 | 5476 | {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5477 | |
c7a8dbf9 | 5478 | {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, |
066be9f7 | 5479 | |
5817ffd1 PB |
5480 | {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}}, |
5481 | ||
c7a8dbf9 | 5482 | {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}}, |
252b5132 | 5483 | |
1cb0a767 | 5484 | {"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, |
252b5132 | 5485 | |
03edbe3b | 5486 | {"lhbrx", X(31,790), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}}, |
252b5132 | 5487 | |
c7a8dbf9 | 5488 | {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, |
c72ab5f2 | 5489 | {"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, |
418c1742 | 5490 | |
b9c361e0 | 5491 | {"sraw", XRC(31,792,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 5492 | {"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, |
b9c361e0 | 5493 | {"sraw.", XRC(31,792,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, |
1cb0a767 | 5494 | {"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, |
fdd12ef3 | 5495 | |
1cb0a767 PB |
5496 | {"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, |
5497 | {"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 5498 | |
03edbe3b | 5499 | {"lfddx", X(31,803), X_MASK, E500MC|PPCVLE, PPCNONE, {FRT, RA, RB}}, |
19a6653c | 5500 | |
aea77599 AM |
5501 | {"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
5502 | {"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, | |
1cb0a767 | 5503 | {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, |
252b5132 | 5504 | |
5817ffd1 PB |
5505 | {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}}, |
5506 | ||
81a0b7e2 | 5507 | {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}}, |
252b5132 | 5508 | |
e0d602ec BE |
5509 | {"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}}, |
5510 | ||
1cb0a767 | 5511 | {"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, |
252b5132 | 5512 | |
1cb0a767 | 5513 | {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}}, |
252b5132 | 5514 | |
1cb0a767 | 5515 | {"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, |
fdd12ef3 | 5516 | |
b9c361e0 | 5517 | {"srawi", XRC(31,824,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}}, |
1cb0a767 | 5518 | {"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, |
b9c361e0 | 5519 | {"srawi.", XRC(31,824,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}}, |
1cb0a767 | 5520 | {"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, |
702f0fb4 | 5521 | |
b9c361e0 JL |
5522 | {"sradi", XS(31,413,0), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}}, |
5523 | {"sradi.", XS(31,413,1), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}}, | |
e0c21649 | 5524 | |
aea77599 AM |
5525 | {"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
5526 | ||
1cb0a767 PB |
5527 | {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, |
5528 | {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
252b5132 | 5529 | |
c7a8dbf9 | 5530 | {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, |
9b4e5766 | 5531 | |
5817ffd1 PB |
5532 | {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}}, |
5533 | ||
c7a8dbf9 | 5534 | {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, |
e0d602ec | 5535 | |
1cb0a767 | 5536 | {"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, |
252b5132 | 5537 | |
1cb0a767 | 5538 | {"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, |
418c1742 | 5539 | |
9fe54b1c | 5540 | {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, |
b9c361e0 JL |
5541 | {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}}, |
5542 | {"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}}, | |
9fe54b1c | 5543 | {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}}, |
418c1742 | 5544 | |
9fe54b1c | 5545 | {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}}, |
418c1742 | 5546 | |
aea77599 AM |
5547 | {"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, |
5548 | ||
1cb0a767 PB |
5549 | {"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, |
5550 | {"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
702f0fb4 | 5551 | |
1cb0a767 PB |
5552 | {"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, |
5553 | {"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
252b5132 | 5554 | |
5817ffd1 PB |
5555 | {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}}, |
5556 | ||
1cb0a767 | 5557 | {"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, |
252b5132 | 5558 | |
e0d602ec | 5559 | {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}}, |
066be9f7 | 5560 | |
1cb0a767 PB |
5561 | {"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, |
5562 | {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
252b5132 | 5563 | |
51b5d4a8 AM |
5564 | {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, |
5565 | {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
5566 | {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
5567 | {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
066be9f7 | 5568 | |
c7a8dbf9 | 5569 | {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, |
066be9f7 | 5570 | |
5817ffd1 PB |
5571 | {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}}, |
5572 | ||
c7a8dbf9 AS |
5573 | {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}}, |
5574 | {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}}, | |
252b5132 | 5575 | |
1cb0a767 | 5576 | {"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, |
702f0fb4 | 5577 | |
1cb0a767 | 5578 | {"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, |
f5c120c5 | 5579 | |
1cb0a767 | 5580 | {"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, |
252b5132 | 5581 | |
c7a8dbf9 AS |
5582 | {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, |
5583 | {"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA0, RB}}, | |
6ba045b1 | 5584 | |
1cb0a767 PB |
5585 | {"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5586 | {"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
702f0fb4 | 5587 | |
1cb0a767 PB |
5588 | {"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, |
5589 | {"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
252b5132 | 5590 | |
b9c361e0 | 5591 | {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, |
1cb0a767 | 5592 | {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, |
b9c361e0 | 5593 | {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, |
1cb0a767 | 5594 | {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, |
702f0fb4 | 5595 | |
1cb0a767 | 5596 | {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, |
19a6653c | 5597 | |
aea77599 AM |
5598 | {"stvfrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
5599 | ||
85d4ac0b AM |
5600 | {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, |
5601 | {"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}}, | |
5602 | {"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}}, | |
5603 | ||
1cb0a767 | 5604 | {"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, |
6ba045b1 | 5605 | |
51b5d4a8 AM |
5606 | {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, |
5607 | {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
5608 | {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
5609 | {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, | |
066be9f7 | 5610 | |
5817ffd1 PB |
5611 | {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}}, |
5612 | ||
e0d602ec BE |
5613 | {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, |
5614 | {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, | |
9fe54b1c | 5615 | {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}}, |
702f0fb4 | 5616 | |
1cb0a767 | 5617 | {"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, |
252b5132 | 5618 | |
51b5d4a8 AM |
5619 | {"icswepx", XRC(31,950,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, |
5620 | {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, | |
5621 | ||
1cb0a767 | 5622 | {"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, |
252b5132 | 5623 | |
1cb0a767 PB |
5624 | {"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, |
5625 | {"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
252b5132 | 5626 | |
b9c361e0 JL |
5627 | {"extsb", XRC(31,954,0), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}}, |
5628 | {"extsb.", XRC(31,954,1), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}}, | |
252b5132 | 5629 | |
aea77599 AM |
5630 | {"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
5631 | ||
cee62821 | 5632 | {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, |
b9c361e0 JL |
5633 | {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}}, |
5634 | ||
5635 | {"divduo", XO(31,457,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
5636 | {"divduo.", XO(31,457,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
5637 | ||
5638 | {"divwuo", XO(31,459,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
5639 | {"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
252b5132 | 5640 | |
c7a8dbf9 | 5641 | {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, |
9b4e5766 | 5642 | |
9fe54b1c | 5643 | {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, |
1cb0a767 PB |
5644 | {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, |
5645 | {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, | |
9fe54b1c | 5646 | {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}}, |
418c1742 | 5647 | |
1cb0a767 | 5648 | {"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, |
252b5132 | 5649 | |
03edbe3b | 5650 | {"icbi", X(31,982), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}}, |
252b5132 | 5651 | |
e01d869a | 5652 | {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, |
702f0fb4 | 5653 | |
b9c361e0 JL |
5654 | {"extsw", XRC(31,986,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, |
5655 | {"extsw.", XRC(31,986,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, | |
252b5132 | 5656 | |
c7a8dbf9 | 5657 | {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}}, |
19a6653c | 5658 | |
aea77599 AM |
5659 | {"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, |
5660 | ||
c7a8dbf9 | 5661 | {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}}, |
252b5132 | 5662 | |
1cb0a767 PB |
5663 | {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, |
5664 | {"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
252b5132 | 5665 | |
b9c361e0 JL |
5666 | {"divdo", XO(31,489,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, |
5667 | {"divdo.", XO(31,489,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
5668 | ||
5669 | {"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
5670 | {"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, | |
418c1742 | 5671 | |
5817ffd1 | 5672 | {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, |
702f0fb4 | 5673 | |
ce3d2015 | 5674 | {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, |
252b5132 | 5675 | |
1cb0a767 | 5676 | {"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, |
418c1742 | 5677 | |
03edbe3b | 5678 | {"dcbz", X(31,1014), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}}, |
c7a8dbf9 | 5679 | {"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA0, RB}}, |
786e2c0f | 5680 | |
c7a8dbf9 | 5681 | {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}}, |
ede602d7 | 5682 | |
c7a8dbf9 | 5683 | {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, |
252b5132 | 5684 | |
1cb0a767 PB |
5685 | {"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}}, |
5686 | {"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}}, | |
5687 | {"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}}, | |
252b5132 | 5688 | |
1cb0a767 PB |
5689 | {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, |
5690 | {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, | |
5691 | {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}}, | |
252b5132 | 5692 | |
1cb0a767 PB |
5693 | {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}}, |
5694 | {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}}, | |
5695 | {"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}}, | |
5696 | {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}}, | |
252b5132 | 5697 | |
1cb0a767 PB |
5698 | {"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, |
5699 | {"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
252b5132 | 5700 | |
1cb0a767 PB |
5701 | {"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}}, |
5702 | {"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
252b5132 | 5703 | |
1cb0a767 | 5704 | {"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, |
252b5132 | 5705 | |
1cb0a767 | 5706 | {"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, |
252b5132 | 5707 | |
1cb0a767 PB |
5708 | {"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, |
5709 | {"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, | |
252b5132 | 5710 | |
1cb0a767 PB |
5711 | {"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}}, |
5712 | {"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, | |
252b5132 | 5713 | |
1cb0a767 | 5714 | {"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, |
252b5132 | 5715 | |
1cb0a767 | 5716 | {"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, |
252b5132 | 5717 | |
1cb0a767 | 5718 | {"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, |
252b5132 | 5719 | |
1cb0a767 | 5720 | {"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, |
252b5132 | 5721 | |
1cb0a767 | 5722 | {"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, |
252b5132 | 5723 | |
1cb0a767 | 5724 | {"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, |
252b5132 | 5725 | |
1cb0a767 | 5726 | {"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, |
252b5132 | 5727 | |
1cb0a767 | 5728 | {"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, |
252b5132 | 5729 | |
1cb0a767 PB |
5730 | {"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}}, |
5731 | {"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
252b5132 | 5732 | |
1cb0a767 PB |
5733 | {"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, |
5734 | {"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, | |
252b5132 | 5735 | |
e01d869a | 5736 | {"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, |
252b5132 | 5737 | |
e01d869a | 5738 | {"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, |
252b5132 | 5739 | |
e01d869a | 5740 | {"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, |
252b5132 | 5741 | |
e01d869a | 5742 | {"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, |
252b5132 | 5743 | |
e01d869a | 5744 | {"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}}, |
adadcc0c | 5745 | |
e01d869a | 5746 | {"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}}, |
252b5132 | 5747 | |
e01d869a | 5748 | {"stfd", OP(54), OP_MASK, COM, PPCEFS, {FRS, D, RA0}}, |
c3d65c1c | 5749 | |
e01d869a | 5750 | {"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}}, |
252b5132 | 5751 | |
9fe54b1c | 5752 | {"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}}, |
1cb0a767 | 5753 | {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, |
70dc4e32 | 5754 | {"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, |
418c1742 | 5755 | |
62082a42 | 5756 | {"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, DS, RA0}}, |
1cb0a767 | 5757 | {"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, |
70dc4e32 | 5758 | {"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, |
802a735e | 5759 | |
1cb0a767 PB |
5760 | {"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, |
5761 | {"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}}, | |
5762 | {"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, | |
702f0fb4 | 5763 | |
1cb0a767 PB |
5764 | {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, |
5765 | {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
252b5132 | 5766 | |
1cb0a767 PB |
5767 | {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, |
5768 | {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, | |
252b5132 | 5769 | |
e01d869a AM |
5770 | {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, |
5771 | {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, | |
252b5132 | 5772 | |
e01d869a AM |
5773 | {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, |
5774 | {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, | |
252b5132 | 5775 | |
e01d869a AM |
5776 | {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, |
5777 | {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, | |
252b5132 | 5778 | |
ce3d2015 AM |
5779 | {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}}, |
5780 | {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}}, | |
252b5132 | 5781 | |
066be9f7 | 5782 | {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 5783 | {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, |
066be9f7 | 5784 | {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 5785 | {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, |
1ed8e1e4 | 5786 | |
e01d869a AM |
5787 | {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}}, |
5788 | {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}}, | |
252b5132 | 5789 | |
066be9f7 | 5790 | {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 5791 | {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, |
066be9f7 | 5792 | {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 5793 | {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, |
252b5132 | 5794 | |
e01d869a AM |
5795 | {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, |
5796 | {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 5797 | |
e01d869a AM |
5798 | {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, |
5799 | {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 5800 | |
e01d869a AM |
5801 | {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, |
5802 | {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 5803 | |
e01d869a AM |
5804 | {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, |
5805 | {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 5806 | |
1cb0a767 PB |
5807 | {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, |
5808 | {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
702f0fb4 | 5809 | |
1cb0a767 PB |
5810 | {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, |
5811 | {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, | |
702f0fb4 | 5812 | |
1cb0a767 PB |
5813 | {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, |
5814 | {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
702f0fb4 | 5815 | |
1cb0a767 PB |
5816 | {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, |
5817 | {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, | |
702f0fb4 | 5818 | |
1cb0a767 PB |
5819 | {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, |
5820 | {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
702f0fb4 | 5821 | |
1cb0a767 PB |
5822 | {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, |
5823 | {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
702f0fb4 | 5824 | |
1cb0a767 | 5825 | {"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, |
702f0fb4 | 5826 | |
1cb0a767 PB |
5827 | {"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, |
5828 | {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}}, | |
5829 | {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}}, | |
702f0fb4 | 5830 | |
1cb0a767 PB |
5831 | {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, |
5832 | {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
702f0fb4 | 5833 | |
1cb0a767 PB |
5834 | {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, |
5835 | {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
702f0fb4 | 5836 | |
1cb0a767 PB |
5837 | {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, |
5838 | {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
702f0fb4 | 5839 | |
1cb0a767 PB |
5840 | {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, |
5841 | {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, | |
702f0fb4 | 5842 | |
1cb0a767 PB |
5843 | {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, |
5844 | {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
702f0fb4 | 5845 | |
1cb0a767 PB |
5846 | {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, |
5847 | {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
702f0fb4 | 5848 | |
1cb0a767 PB |
5849 | {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, |
5850 | {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
702f0fb4 | 5851 | |
1cb0a767 | 5852 | {"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, |
702f0fb4 | 5853 | |
1cb0a767 | 5854 | {"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, |
702f0fb4 | 5855 | |
1cb0a767 PB |
5856 | {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, |
5857 | {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
702f0fb4 | 5858 | |
066be9f7 PB |
5859 | {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
5860 | {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
5861 | ||
1cb0a767 PB |
5862 | {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, |
5863 | {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, | |
252b5132 | 5864 | |
e0d602ec BE |
5865 | {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, |
5866 | {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, | |
066be9f7 | 5867 | |
1cb0a767 PB |
5868 | {"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, |
5869 | {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
8dbcd839 | 5870 | |
e0d602ec BE |
5871 | {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, |
5872 | {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, | |
066be9f7 | 5873 | |
066be9f7 PB |
5874 | {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}}, |
5875 | {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}}, | |
5876 | {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}}, | |
1cb0a767 | 5877 | {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, |
066be9f7 | 5878 | {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, |
1cb0a767 PB |
5879 | {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, |
5880 | {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}}, | |
066be9f7 PB |
5881 | {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, |
5882 | {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5883 | {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5884 | {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
5885 | {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5886 | {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5887 | {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
5888 | {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5889 | {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5890 | {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5891 | {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5892 | {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5893 | {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
5894 | {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5895 | {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5896 | {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5897 | {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5898 | {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5899 | {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5900 | {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5901 | {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5902 | {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5903 | {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5904 | {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5905 | {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5906 | {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5907 | {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5908 | {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5909 | {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5910 | {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5911 | {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5912 | {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5913 | {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5914 | {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5915 | {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
5916 | {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5917 | {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5918 | {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5919 | {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5920 | {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5921 | {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5922 | {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5923 | {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, | |
5924 | {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5925 | {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5926 | {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5927 | {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5928 | {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5929 | {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5930 | {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5931 | {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5932 | {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5933 | {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5934 | {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
5935 | {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5936 | {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5937 | {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5938 | {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5939 | {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5940 | {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5941 | {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5942 | {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5943 | {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5944 | {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5945 | {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5946 | {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5947 | {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5948 | {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5949 | {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}}, | |
5950 | {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5951 | {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5952 | {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5953 | {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5954 | {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, | |
5955 | {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5956 | {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5957 | {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5958 | {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5959 | {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5960 | {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5961 | {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5962 | {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5963 | {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5964 | {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5965 | {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5966 | {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5967 | {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5968 | {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5969 | {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, | |
5970 | {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5971 | {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5972 | {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5973 | {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5974 | {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5975 | {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5976 | {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5977 | {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5978 | {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5979 | {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5980 | {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5981 | {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5982 | {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, | |
5983 | {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
1cb0a767 PB |
5984 | {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, |
5985 | {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
066be9f7 PB |
5986 | {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, |
5987 | {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5988 | {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
5989 | {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5990 | {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5991 | {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5992 | {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5993 | {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5994 | {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5995 | {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5996 | {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5997 | {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5998 | {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
5999 | {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6000 | {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6001 | {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6002 | {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6003 | {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6004 | {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6005 | {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6006 | {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6007 | {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6008 | {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6009 | {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6010 | {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6011 | {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6012 | {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6013 | {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
6014 | {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
9b4e5766 | 6015 | |
c72ab5f2 | 6016 | {"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, |
70dc4e32 | 6017 | {"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, |
418c1742 | 6018 | |
62082a42 | 6019 | {"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, DS, RA0}}, |
c72ab5f2 | 6020 | {"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, |
70dc4e32 | 6021 | {"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, |
c72ab5f2 | 6022 | |
1cb0a767 PB |
6023 | {"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}}, |
6024 | {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, | |
9fe54b1c | 6025 | {"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}}, |
fdd12ef3 | 6026 | |
e01d869a | 6027 | {"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, |
252b5132 | 6028 | |
989993d8 JB |
6029 | {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, |
6030 | {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 6031 | |
989993d8 JB |
6032 | {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}}, |
6033 | {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}}, | |
702f0fb4 | 6034 | |
9fe54b1c PB |
6035 | {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, |
6036 | {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, | |
702f0fb4 | 6037 | |
e01d869a AM |
6038 | {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, |
6039 | {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, | |
252b5132 | 6040 | |
e01d869a | 6041 | {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, |
81a0b7e2 | 6042 | {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, |
e01d869a | 6043 | {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, |
81a0b7e2 | 6044 | {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, |
252b5132 | 6045 | |
e01d869a | 6046 | {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, |
81a0b7e2 | 6047 | {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, |
e01d869a | 6048 | {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, |
81a0b7e2 | 6049 | {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, |
252b5132 | 6050 | |
e01d869a | 6051 | {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, |
1cb0a767 | 6052 | {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, |
e01d869a | 6053 | {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, |
1cb0a767 | 6054 | {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, |
252b5132 | 6055 | |
e01d869a | 6056 | {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, |
1cb0a767 | 6057 | {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, |
e01d869a | 6058 | {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, |
1cb0a767 | 6059 | {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, |
252b5132 | 6060 | |
e01d869a | 6061 | {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, |
1cb0a767 | 6062 | {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, |
e01d869a | 6063 | {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, |
1cb0a767 | 6064 | {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, |
252b5132 | 6065 | |
ce3d2015 AM |
6066 | {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}}, |
6067 | {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}}, | |
252b5132 | 6068 | |
e01d869a AM |
6069 | {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, |
6070 | {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 6071 | |
066be9f7 | 6072 | {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 6073 | {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, |
066be9f7 | 6074 | {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 6075 | {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, |
1ed8e1e4 | 6076 | |
e01d869a | 6077 | {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}}, |
1cb0a767 | 6078 | {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, |
e01d869a | 6079 | {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}}, |
1cb0a767 | 6080 | {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, |
252b5132 | 6081 | |
066be9f7 | 6082 | {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 6083 | {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, |
066be9f7 | 6084 | {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
70dc4e32 | 6085 | {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, |
252b5132 | 6086 | |
e01d869a | 6087 | {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6088 | {"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
e01d869a | 6089 | {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6090 | {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
252b5132 | 6091 | |
e01d869a | 6092 | {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6093 | {"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
e01d869a | 6094 | {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6095 | {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
252b5132 | 6096 | |
e01d869a | 6097 | {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6098 | {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
e01d869a | 6099 | {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6100 | {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
252b5132 | 6101 | |
e01d869a | 6102 | {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6103 | {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
e01d869a | 6104 | {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, |
1cb0a767 | 6105 | {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, |
252b5132 | 6106 | |
e01d869a | 6107 | {"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, |
252b5132 | 6108 | |
989993d8 JB |
6109 | {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, |
6110 | {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 6111 | |
a08fc942 PB |
6112 | {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}}, |
6113 | {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}}, | |
702f0fb4 | 6114 | |
1cb0a767 PB |
6115 | {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}}, |
6116 | {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}}, | |
252b5132 | 6117 | |
e01d869a AM |
6118 | {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, |
6119 | {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, | |
252b5132 | 6120 | |
1cb0a767 | 6121 | {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, |
252b5132 | 6122 | |
989993d8 JB |
6123 | {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}}, |
6124 | {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 6125 | |
989993d8 JB |
6126 | {"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}}, |
6127 | {"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}}, | |
702f0fb4 | 6128 | |
1cb0a767 PB |
6129 | {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}}, |
6130 | {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}}, | |
252b5132 | 6131 | |
e01d869a AM |
6132 | {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, |
6133 | {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, | |
252b5132 | 6134 | |
989993d8 JB |
6135 | {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}}, |
6136 | {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 6137 | |
989993d8 JB |
6138 | {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, |
6139 | {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 6140 | |
066be9f7 PB |
6141 | {"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}}, |
6142 | ||
989993d8 | 6143 | {"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, |
702f0fb4 | 6144 | |
9fe54b1c PB |
6145 | {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}}, |
6146 | {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}}, | |
6147 | {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}}, | |
6148 | {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}}, | |
252b5132 | 6149 | |
e01d869a AM |
6150 | {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, |
6151 | {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, | |
252b5132 | 6152 | |
066be9f7 PB |
6153 | {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, |
6154 | {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
6155 | {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
6156 | {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
6157 | ||
6158 | {"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}}, | |
6159 | ||
a08fc942 | 6160 | {"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, |
989993d8 JB |
6161 | {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}}, |
6162 | {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}}, | |
702f0fb4 | 6163 | |
989993d8 JB |
6164 | {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, |
6165 | {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 6166 | |
a08fc942 PB |
6167 | {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, |
6168 | {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, | |
702f0fb4 | 6169 | |
e01d869a AM |
6170 | {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, |
6171 | {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, | |
252b5132 | 6172 | |
a08fc942 PB |
6173 | {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, |
6174 | {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, | |
702f0fb4 | 6175 | |
989993d8 JB |
6176 | {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}}, |
6177 | {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}}, | |
702f0fb4 | 6178 | |
a08fc942 PB |
6179 | {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, |
6180 | {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, | |
702f0fb4 | 6181 | |
1cb0a767 PB |
6182 | {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, |
6183 | {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
6184 | {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
6185 | {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
6186 | {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
6187 | {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
6188 | {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
6189 | {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
ce7a772b | 6190 | |
989993d8 JB |
6191 | {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, |
6192 | {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 6193 | |
989993d8 JB |
6194 | {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, |
6195 | {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 6196 | |
e01d869a AM |
6197 | {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}}, |
6198 | {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}}, | |
252b5132 | 6199 | |
989993d8 | 6200 | {"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, |
702f0fb4 | 6201 | |
a08fc942 | 6202 | {"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}}, |
702f0fb4 | 6203 | |
9fe54b1c | 6204 | {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, |
e01d869a | 6205 | {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, |
9fe54b1c | 6206 | {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, |
e01d869a | 6207 | {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, |
252b5132 | 6208 | |
989993d8 JB |
6209 | {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, |
6210 | {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, | |
702f0fb4 | 6211 | |
a08fc942 PB |
6212 | {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, |
6213 | {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, | |
702f0fb4 | 6214 | |
1cb0a767 | 6215 | {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, |
9fe54b1c | 6216 | {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, |
1cb0a767 | 6217 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, |
9fe54b1c | 6218 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, |
252b5132 | 6219 | |
1cb0a767 | 6220 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, |
9fe54b1c | 6221 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, |
1cb0a767 | 6222 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, |
9fe54b1c | 6223 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, |
252b5132 | 6224 | |
989993d8 JB |
6225 | {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}}, |
6226 | {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}}, | |
702f0fb4 | 6227 | |
1cb0a767 | 6228 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, |
9fe54b1c | 6229 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, |
1cb0a767 | 6230 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, |
9fe54b1c | 6231 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, |
252b5132 | 6232 | |
a08fc942 PB |
6233 | {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}}, |
6234 | {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}}, | |
702f0fb4 | 6235 | |
e0d602ec BE |
6236 | {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, |
6237 | {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, | |
066be9f7 | 6238 | |
e0d602ec BE |
6239 | {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, |
6240 | {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, | |
066be9f7 | 6241 | |
e0d602ec BE |
6242 | {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, |
6243 | {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, | |
252b5132 RH |
6244 | }; |
6245 | ||
6246 | const int powerpc_num_opcodes = | |
6247 | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); | |
6248 | \f | |
b9c361e0 JL |
6249 | /* The VLE opcode table. |
6250 | ||
6251 | The format of this opcode table is the same as the main opcode table. */ | |
6252 | ||
6253 | const struct powerpc_opcode vle_opcodes[] = { | |
6254 | ||
6255 | {"se_illegal", C(0), C_MASK, PPCVLE, PPCNONE, {}}, | |
6256 | {"se_isync", C(1), C_MASK, PPCVLE, PPCNONE, {}}, | |
6257 | {"se_sc", C(2), C_MASK, PPCVLE, PPCNONE, {}}, | |
6258 | {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, PPCNONE, {}}, | |
6259 | {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, PPCNONE, {}}, | |
6260 | {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, PPCNONE, {}}, | |
6261 | {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, PPCNONE, {}}, | |
6262 | {"se_rfi", C(8), C_MASK, PPCVLE, PPCNONE, {}}, | |
6263 | {"se_rfci", C(9), C_MASK, PPCVLE, PPCNONE, {}}, | |
6264 | {"se_rfdi", C(10), C_MASK, PPCVLE, PPCNONE, {}}, | |
6265 | {"se_rfmci", C(11), C_MASK, PPCVLE, PPCNONE, {}}, | |
6266 | {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6267 | {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6268 | {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6269 | {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6270 | {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6271 | {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6272 | {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6273 | {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6274 | {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6275 | {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, | |
6276 | {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6277 | {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, PPCNONE, {ARX, RY}}, | |
6278 | {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, ARY}}, | |
6279 | {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6280 | {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6281 | {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6282 | {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6283 | {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6284 | {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6285 | {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6286 | {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6287 | ||
6288 | {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}}, | |
6289 | {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}}, | |
6290 | {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, | |
6291 | {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}}, | |
6292 | {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, | |
6293 | {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, | |
6294 | {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}}, | |
6295 | {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, | |
6296 | {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}}, | |
6297 | {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, | |
6298 | {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, | |
6299 | {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, | |
6300 | {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, | |
6301 | {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, | |
6302 | {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, PPCNONE, {0}}, | |
6303 | {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, | |
6304 | {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, | |
6305 | {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, | |
6306 | {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, | |
6307 | {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6308 | {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6309 | {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6310 | {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6311 | {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6312 | {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6313 | {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6314 | {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6315 | {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, | |
6316 | {"e_add16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, SI}}, | |
6317 | {"e_la", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6318 | {"e_sub16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, NSI}}, | |
6319 | ||
6320 | {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, | |
6321 | {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, | |
6322 | {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, | |
6323 | {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, | |
6324 | {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6325 | {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6326 | {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6327 | ||
6328 | {"e_lbz", OP(12), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6329 | {"e_stb", OP(13), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6330 | {"e_lha", OP(14), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6331 | ||
6332 | {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6333 | {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6334 | {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6335 | {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, PPCNONE, {0}}, | |
6336 | {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6337 | {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6338 | {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6339 | {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, | |
6340 | {"se_li", IM7(9), IM7_MASK, PPCVLE, PPCNONE, {RX, UI7}}, | |
6341 | ||
6342 | {"e_lwz", OP(20), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6343 | {"e_stw", OP(21), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6344 | {"e_lhz", OP(22), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6345 | {"e_sth", OP(23), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, | |
6346 | ||
6347 | {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6348 | {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6349 | {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6350 | {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6351 | {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6352 | {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6353 | {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, | |
6354 | ||
6355 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, | |
6356 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, | |
6357 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, | |
6358 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, | |
6359 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, | |
6360 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}}, | |
6361 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, | |
6362 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}}, | |
6363 | {"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, | |
6364 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, | |
6365 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, | |
6366 | {"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, | |
6367 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}}, | |
6368 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, | |
6369 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}}, | |
6370 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, | |
6371 | {"e_li", LI20(28,0), LI20_MASK, PPCVLE, PPCNONE, {RT, IMM20}}, | |
6372 | {"e_rlwimi", M(29,0), M_MASK, PPCVLE, PPCNONE, {RA, RS, SH, MB, ME}}, | |
6373 | {"e_rlwinm", M(29,1), M_MASK, PPCVLE, PPCNONE, {RA, RT, SH, MBE, ME}}, | |
6374 | {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, PPCNONE, {B24}}, | |
6375 | {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, PPCNONE, {B24}}, | |
6376 | {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, | |
6377 | {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, | |
6378 | {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, | |
6379 | {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, | |
6380 | {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6381 | {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6382 | {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6383 | {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6384 | {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6385 | {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6386 | {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6387 | {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6388 | {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6389 | {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6390 | {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6391 | {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6392 | {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6393 | {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6394 | {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6395 | {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6396 | {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6397 | {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6398 | {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6399 | {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6400 | {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6401 | {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6402 | {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6403 | {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, | |
6404 | {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}}, | |
6405 | {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}}, | |
6406 | ||
6407 | {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, | |
6408 | {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, | |
6409 | {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, | |
6410 | {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, | |
6411 | ||
6412 | {"e_cmph", X(31,14), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}}, | |
6413 | {"e_cmphl", X(31,46), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}}, | |
6414 | {"e_crandc", XL(31,129), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6415 | {"e_crnand", XL(31,225), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6416 | {"e_crnot", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}}, | |
6417 | {"e_crnor", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6418 | {"e_crclr", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}}, | |
6419 | {"e_crxor", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6420 | {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, PPCNONE, {CRD, CR}}, | |
6421 | {"e_slwi", EX(31,112), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, | |
6422 | {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, | |
6423 | ||
6424 | {"e_crand", XL(31,257), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6425 | ||
6426 | {"e_rlw", EX(31,560), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}}, | |
6427 | {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}}, | |
6428 | ||
6429 | {"e_crset", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}}, | |
6430 | {"e_creqv", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6431 | ||
6432 | {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, | |
6433 | {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, | |
6434 | ||
6435 | {"e_crorc", XL(31,417), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6436 | ||
6437 | {"e_crmove", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}}, | |
6438 | {"e_cror", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, | |
6439 | ||
6440 | {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, PPCNONE, {RS}}, | |
6441 | ||
6442 | {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, | |
6443 | {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, | |
6444 | ||
6445 | {"se_lbz", SD4(8), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}}, | |
6446 | ||
6447 | {"se_stb", SD4(9), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}}, | |
6448 | ||
6449 | {"se_lhz", SD4(10), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}}, | |
6450 | ||
6451 | {"se_sth", SD4(11), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}}, | |
6452 | ||
6453 | {"se_lwz", SD4(12), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}}, | |
6454 | ||
6455 | {"se_stw", SD4(13), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}}, | |
6456 | ||
6457 | {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6458 | {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6459 | {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6460 | {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6461 | {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6462 | {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6463 | {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6464 | {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}}, | |
6465 | {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6466 | {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6467 | {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6468 | {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6469 | {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, | |
6470 | {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}}, | |
6471 | {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, PPCNONE, {BO16, BI16, B8}}, | |
6472 | {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, PPCNONE, {B8}}, | |
6473 | {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, PPCNONE, {B8}}, | |
6474 | }; | |
6475 | ||
6476 | const int vle_num_opcodes = | |
6477 | sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); | |
6478 | \f | |
252b5132 RH |
6479 | /* The macro table. This is only used by the assembler. */ |
6480 | ||
6481 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 | |
6482 | when x=0; 32-x when x is between 1 and 31; are negative if x is | |
6483 | negative; and are 32 or more otherwise. This is what you want | |
6484 | when, for instance, you are emulating a right shift by a | |
6485 | rotate-left-and-mask, because the underlying instructions support | |
6486 | shifts of size 0 but not shifts of size 32. By comparison, when | |
6487 | extracting x bits from some word you want to use just 32-x, because | |
6488 | the underlying instructions don't support extracting 0 bits but do | |
6489 | support extracting the whole word (32 bits in this case). */ | |
6490 | ||
6491 | const struct powerpc_macro powerpc_macros[] = { | |
de866fcc AM |
6492 | {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, |
6493 | {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, | |
bdc7fcfe AM |
6494 | {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, |
6495 | {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, | |
de866fcc AM |
6496 | {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, |
6497 | {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, | |
6498 | {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
6499 | {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
6500 | {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, | |
6501 | {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, | |
6502 | {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
6503 | {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
6504 | {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, | |
6505 | {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, | |
6506 | {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, | |
6507 | {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, | |
6508 | ||
6509 | {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, | |
6510 | {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, | |
6511 | {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
6512 | {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
6513 | {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
6514 | {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
6515 | {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
6516 | {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
6517 | {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
6518 | {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
6519 | {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, | |
6520 | {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, | |
6521 | {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, | |
6522 | {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, | |
6523 | {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
6524 | {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
6525 | {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
6526 | {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
6527 | {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, | |
6528 | {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, | |
6529 | {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
6530 | {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
a4ebc835 AM |
6531 | |
6532 | {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, | |
6533 | {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
6534 | {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
6535 | {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
6536 | {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, | |
6537 | {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
6538 | {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, | |
6539 | {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
6540 | {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, | |
6541 | {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, | |
6542 | {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
252b5132 RH |
6543 | }; |
6544 | ||
6545 | const int powerpc_num_macros = | |
6546 | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); |