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* varobj.h (varobj_floating_p): Declare.
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
930bb4cf 3 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
9b201bb5 6 This file is part of the GNU opcodes library.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
112290ab 18 You should have received a copy of the GNU General Public License
9b201bb5
NC		 19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
c168870a
AM		 41static unsigned long insert_bat (unsigned long, long, int, const char **);
42static long extract_bat (unsigned long, int, int *);
43static unsigned long insert_bba (unsigned long, long, int, const char **);
44static long extract_bba (unsigned long, int, int *);
c168870a
AM		 45static unsigned long insert_bdm (unsigned long, long, int, const char **);
46static long extract_bdm (unsigned long, int, int *);
47static unsigned long insert_bdp (unsigned long, long, int, const char **);
48static long extract_bdp (unsigned long, int, int *);
c168870a
AM		 49static unsigned long insert_bo (unsigned long, long, int, const char **);
50static long extract_bo (unsigned long, int, int *);
51static unsigned long insert_boe (unsigned long, long, int, const char **);
52static long extract_boe (unsigned long, int, int *);
c168870a
AM		 53static unsigned long insert_fxm (unsigned long, long, int, const char **);
54static long extract_fxm (unsigned long, int, int *);
c168870a
AM		 55static unsigned long insert_mbe (unsigned long, long, int, const char **);
56static long extract_mbe (unsigned long, int, int *);
57static unsigned long insert_mb6 (unsigned long, long, int, const char **);
58static long extract_mb6 (unsigned long, int, int *);
c168870a
AM		 59static long extract_nb (unsigned long, int, int *);
60static unsigned long insert_nsi (unsigned long, long, int, const char **);
61static long extract_nsi (unsigned long, int, int *);
62static unsigned long insert_ral (unsigned long, long, int, const char **);
63static unsigned long insert_ram (unsigned long, long, int, const char **);
64static unsigned long insert_raq (unsigned long, long, int, const char **);
65static unsigned long insert_ras (unsigned long, long, int, const char **);
66static unsigned long insert_rbs (unsigned long, long, int, const char **);
67static long extract_rbs (unsigned long, int, int *);
c168870a
AM		 68static unsigned long insert_sh6 (unsigned long, long, int, const char **);
69static long extract_sh6 (unsigned long, int, int *);
70static unsigned long insert_spr (unsigned long, long, int, const char **);
71static long extract_spr (unsigned long, int, int *);
da99ee72
AM		 72static unsigned long insert_sprg (unsigned long, long, int, const char **);
73static long extract_sprg (unsigned long, int, int *);
c168870a
AM		 74static unsigned long insert_tbr (unsigned long, long, int, const char **);
75static long extract_tbr (unsigned long, int, int *);
252b5132
RH		 76\f
77/* The operands table.
78
717bbdf1 79 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 80
81 We used to put parens around the various additions, like the one
82 for BA just below. However, that caused trouble with feeble
83 compilers with a limit on depth of a parenthesized expression, like
84 (reportedly) the compiler in Microsoft Developer Studio 5. So we
85 omit the parens, since the macros are never used in a context where
86 the addition will be ambiguous. */
87
88const struct powerpc_operand powerpc_operands[] =
89{
90 /* The zero index is used to indicate the end of the list of
91 operands. */
92#define UNUSED 0
bbac1f2a 93 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 94
95 /* The BA field in an XL form instruction. */
96#define BA UNUSED + 1
717bbdf1
AM		 97 /* The BI field in a B form or XL form instruction. */
98#define BI BA
99#define BI_MASK (0x1f << 16)
b84bf58a 100 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 101
102 /* The BA field in an XL form instruction when it must be the same
103 as the BT field in the same instruction. */
104#define BAT BA + 1
b84bf58a 105 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 106
107 /* The BB field in an XL form instruction. */
108#define BB BAT + 1
109#define BB_MASK (0x1f << 11)
b84bf58a 110 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 111
112 /* The BB field in an XL form instruction when it must be the same
113 as the BA field in the same instruction. */
114#define BBA BB + 1
b84bf58a 115 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 116
117 /* The BD field in a B form instruction. The lower two bits are
118 forced to zero. */
119#define BD BBA + 1
b84bf58a 120 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 121
122 /* The BD field in a B form instruction when absolute addressing is
123 used. */
124#define BDA BD + 1
b84bf58a 125 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 126
127 /* The BD field in a B form instruction when the - modifier is used.
128 This sets the y bit of the BO field appropriately. */
129#define BDM BDA + 1
b84bf58a 130 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 131 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 132
133 /* The BD field in a B form instruction when the - modifier is used
134 and absolute address is used. */
135#define BDMA BDM + 1
b84bf58a 136 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 137 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 138
139 /* The BD field in a B form instruction when the + modifier is used.
140 This sets the y bit of the BO field appropriately. */
141#define BDP BDMA + 1
b84bf58a 142 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 143 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 144
145 /* The BD field in a B form instruction when the + modifier is used
146 and absolute addressing is used. */
147#define BDPA BDP + 1
b84bf58a 148 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 149 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 150
151 /* The BF field in an X or XL form instruction. */
152#define BF BDPA + 1
717bbdf1
AM		 153 /* The CRFD field in an X form instruction. */
154#define CRFD BF
b84bf58a 155 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132 156
ea192fa3
PB		 157 /* The BF field in an X or XL form instruction. */
158#define BFF BF + 1
159 { 0x7, 23, NULL, NULL, 0 },
160
252b5132
RH		 161 /* An optional BF field. This is used for comparison instructions,
162 in which an omitted BF field is taken as zero. */
ea192fa3 163#define OBF BFF + 1
b84bf58a 164 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 165
166 /* The BFA field in an X or XL form instruction. */
167#define BFA OBF + 1
b84bf58a 168 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132 169
252b5132
RH		 170 /* The BO field in a B form instruction. Certain values are
171 illegal. */
717bbdf1 172#define BO BFA + 1
252b5132 173#define BO_MASK (0x1f << 21)
b84bf58a 174 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 175
176 /* The BO field in a B form instruction when the + or - modifier is
177 used. This is like the BO field, but it must be even. */
178#define BOE BO + 1
b84bf58a 179 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 180
d0618d1c 181#define BH BOE + 1
b84bf58a 182 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 183
252b5132 184 /* The BT field in an X or XL form instruction. */
d0618d1c 185#define BT BH + 1
b84bf58a 186 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 187
188 /* The condition register number portion of the BI field in a B form
189 or XL form instruction. This is used for the extended
190 conditional branch mnemonics, which set the lower two bits of the
191 BI field. This field is optional. */
192#define CR BT + 1
b84bf58a 193 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 194
23976049
EZ		 195 /* The CRB field in an X form instruction. */
196#define CRB CR + 1
717bbdf1
AM		 197 /* The MB field in an M form instruction. */
198#define MB CRB
199#define MB_MASK (0x1f << 6)
b84bf58a 200 { 0x1f, 6, NULL, NULL, 0 },
23976049 201
23976049 202 /* The CRFS field in an X form instruction. */
717bbdf1 203#define CRFS CRB + 1
b84bf58a 204 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 205
418c1742 206 /* The CT field in an X form instruction. */
23976049 207#define CT CRFS + 1
717bbdf1
AM		 208 /* The MO field in an mbar instruction. */
209#define MO CT
b84bf58a 210 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 211
252b5132
RH		 212 /* The D field in a D form instruction. This is a displacement off
213 a register, and implies that the next operand is a register in
214 parentheses. */
418c1742 215#define D CT + 1
b84bf58a 216 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 217
418c1742
MG		 218 /* The DE field in a DE form instruction. This is like D, but is 12
219 bits only. */
220#define DE D + 1
b84bf58a 221 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
418c1742
MG		 222
223 /* The DES field in a DES form instruction. This is like DS, but is 14
224 bits only (12 stored.) */
225#define DES DE + 1
b84bf58a 226 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
418c1742 227
adadcc0c
AM		 228 /* The DQ field in a DQ form instruction. This is like D, but the
229 lower four bits are forced to zero. */
230#define DQ DES + 1
b84bf58a
AM		 231 { 0xfff0, 0, NULL, NULL,
232 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 233
252b5132
RH		 234 /* The DS field in a DS form instruction. This is like D, but the
235 lower two bits are forced to zero. */
adadcc0c 236#define DS DQ + 1
b84bf58a
AM		 237 { 0xfffc, 0, NULL, NULL,
238 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 239
240 /* The E field in a wrteei instruction. */
c3d65c1c 241 /* And the W bit in the pair singles instructions. */
252b5132 242#define E DS + 1
c3d65c1c 243#define PSW E
b84bf58a 244 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 245
246 /* The FL1 field in a POWER SC form instruction. */
247#define FL1 E + 1
717bbdf1
AM		 248 /* The U field in an X form instruction. */
249#define U FL1
b84bf58a 250 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 251
252 /* The FL2 field in a POWER SC form instruction. */
253#define FL2 FL1 + 1
b84bf58a 254 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 255
256 /* The FLM field in an XFL form instruction. */
257#define FLM FL2 + 1
b84bf58a 258 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 259
260 /* The FRA field in an X or A form instruction. */
261#define FRA FLM + 1
262#define FRA_MASK (0x1f << 16)
b84bf58a 263 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 264
265 /* The FRB field in an X or A form instruction. */
266#define FRB FRA + 1
267#define FRB_MASK (0x1f << 11)
b84bf58a 268 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 269
270 /* The FRC field in an A form instruction. */
271#define FRC FRB + 1
272#define FRC_MASK (0x1f << 6)
b84bf58a 273 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 274
275 /* The FRS field in an X form instruction or the FRT field in a D, X
276 or A form instruction. */
277#define FRS FRC + 1
278#define FRT FRS
b84bf58a 279 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 280
281 /* The FXM field in an XFX instruction. */
282#define FXM FRS + 1
b84bf58a 283 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 284
285 /* Power4 version for mfcr. */
286#define FXM4 FXM + 1
b84bf58a 287 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 288
289 /* The L field in a D or X form instruction. */
c168870a 290#define L FXM4 + 1
b84bf58a 291 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 292
1ed8e1e4
AM		 293 /* The LEV field in a POWER SVC form instruction. */
294#define SVC_LEV L + 1
b84bf58a 295 { 0x7f, 5, NULL, NULL, 0 },
252b5132 296
1ed8e1e4
AM		 297 /* The LEV field in an SC form instruction. */
298#define LEV SVC_LEV + 1
b84bf58a 299 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 300
252b5132
RH		 301 /* The LI field in an I form instruction. The lower two bits are
302 forced to zero. */
303#define LI LEV + 1
b84bf58a 304 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 305
306 /* The LI field in an I form instruction when used as an absolute
307 address. */
308#define LIA LI + 1
b84bf58a 309 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 310
6ba045b1
AM		 311 /* The LS field in an X (sync) form instruction. */
312#define LS LIA + 1
b84bf58a 313 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 314
252b5132 315 /* The ME field in an M form instruction. */
717bbdf1 316#define ME LS + 1
252b5132 317#define ME_MASK (0x1f << 1)
b84bf58a 318 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 319
320 /* The MB and ME fields in an M form instruction expressed a single
321 operand which is a bitmask indicating which bits to select. This
322 is a two operand form using PPC_OPERAND_NEXT. See the
323 description in opcode/ppc.h for what this means. */
324#define MBE ME + 1
b84bf58a 325 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 326 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 327
328 /* The MB or ME field in an MD or MDS form instruction. The high
329 bit is wrapped to the low end. */
330#define MB6 MBE + 2
331#define ME6 MB6
332#define MB6_MASK (0x3f << 5)
b84bf58a 333 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 334
335 /* The NB field in an X form instruction. The value 32 is stored as
336 0. */
717bbdf1 337#define NB MB6 + 1
b84bf58a 338 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132
RH		 339
340 /* The NSI field in a D form instruction. This is the same as the
341 SI field, only negated. */
342#define NSI NB + 1
b84bf58a 343 { 0xffff, 0, insert_nsi, extract_nsi,
11b37b7b 344 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 345
adadcc0c 346 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 347#define RA NSI + 1
252b5132 348#define RA_MASK (0x1f << 16)
b84bf58a 349 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 350
fdd12ef3
AM		 351 /* As above, but 0 in the RA field means zero, not r0. */
352#define RA0 RA + 1
b84bf58a 353 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3
AM		 354
355 /* The RA field in the DQ form lq instruction, which has special
adadcc0c 356 value restrictions. */
fdd12ef3 357#define RAQ RA0 + 1
b84bf58a 358 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 359
252b5132
RH		 360 /* The RA field in a D or X form instruction which is an updating
361 load, which means that the RA field may not be zero and may not
362 equal the RT field. */
adadcc0c 363#define RAL RAQ + 1
b84bf58a 364 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 365
366 /* The RA field in an lmw instruction, which has special value
367 restrictions. */
368#define RAM RAL + 1
b84bf58a 369 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 370
371 /* The RA field in a D or X form instruction which is an updating
372 store or an updating floating point load, which means that the RA
373 field may not be zero. */
374#define RAS RAM + 1
b84bf58a 375 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 376
1f6c9eb0 377 /* The RA field of the tlbwe instruction, which is optional. */
fdd12ef3 378#define RAOPT RAS + 1
b84bf58a 379 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 380
252b5132 381 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 382#define RB RAOPT + 1
252b5132 383#define RB_MASK (0x1f << 11)
b84bf58a 384 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 385
386 /* The RB field in an X form instruction when it must be the same as
387 the RS field in the instruction. This is used for extended
388 mnemonics like mr. */
389#define RBS RB + 1
b84bf58a 390 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 391
392 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
393 instruction or the RT field in a D, DS, X, XFX or XO form
394 instruction. */
395#define RS RBS + 1
396#define RT RS
397#define RT_MASK (0x1f << 21)
b84bf58a 398 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 399
717bbdf1
AM		 400 /* The RS and RT fields of the DS form stq instruction, which have
401 special value restrictions. */
adadcc0c 402#define RSQ RS + 1
717bbdf1 403#define RTQ RSQ
b84bf58a 404 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 405
1f6c9eb0 406 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 407#define RSO RSQ + 1
eed0d89a 408#define RTO RSO
b84bf58a 409 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 410
252b5132 411 /* The SH field in an X or M form instruction. */
1f6c9eb0 412#define SH RSO + 1
252b5132 413#define SH_MASK (0x1f << 11)
717bbdf1
AM		 414 /* The other UIMM field in a EVX form instruction. */
415#define EVUIMM SH
b84bf58a 416 { 0x1f, 11, NULL, NULL, 0 },
252b5132
RH		 417
418 /* The SH field in an MD form instruction. This is split. */
419#define SH6 SH + 1
420#define SH6_MASK ((0x1f << 11) | (1 << 1))
b84bf58a 421 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
252b5132 422
1f6c9eb0
ZW		 423 /* The SH field of the tlbwe instruction, which is optional. */
424#define SHO SH6 + 1
b84bf58a 425 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 426
252b5132 427 /* The SI field in a D form instruction. */
1f6c9eb0 428#define SI SHO + 1
b84bf58a 429 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 430
431 /* The SI field in a D form instruction when we accept a wide range
432 of positive values. */
433#define SISIGNOPT SI + 1
b84bf58a 434 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 435
436 /* The SPR field in an XFX form instruction. This is flipped--the
437 lower 5 bits are stored in the upper 5 and vice- versa. */
438#define SPR SISIGNOPT + 1
914749f6 439#define PMR SPR
252b5132 440#define SPR_MASK (0x3ff << 11)
b84bf58a 441 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 442
443 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
444#define SPRBAT SPR + 1
445#define SPRBAT_MASK (0x3 << 17)
b84bf58a 446 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 447
448 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
449#define SPRG SPRBAT + 1
b84bf58a 450 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 451
452 /* The SR field in an X form instruction. */
453#define SR SPRG + 1
b84bf58a 454 { 0xf, 16, NULL, NULL, 0 },
252b5132 455
f5c120c5
MG		 456 /* The STRM field in an X AltiVec form instruction. */
457#define STRM SR + 1
b84bf58a 458 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 459
252b5132 460 /* The SV field in a POWER SC form instruction. */
f5c120c5 461#define SV STRM + 1
b84bf58a 462 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 463
464 /* The TBR field in an XFX form instruction. This is like the SPR
465 field, but it is optional. */
466#define TBR SV + 1
b84bf58a 467 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 468
469 /* The TO field in a D or X form instruction. */
470#define TO TBR + 1
471#define TO_MASK (0x1f << 21)
b84bf58a 472 { 0x1f, 21, NULL, NULL, 0 },
252b5132 473
252b5132 474 /* The UI field in a D form instruction. */
717bbdf1 475#define UI TO + 1
b84bf58a 476 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 477
112290ab 478 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f 479#define VA UI + 1
b84bf58a 480 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 481
112290ab 482 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 483#define VB VA + 1
b84bf58a 484 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 485
112290ab 486 /* The VC field in a VA form instruction. */
786e2c0f 487#define VC VB + 1
b84bf58a 488 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 489
112290ab 490 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 491#define VD VC + 1
492#define VS VD
b84bf58a 493 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 494
8dbcd839 495 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 496#define SIMM VD + 1
8dbcd839 497#define TE SIMM
b84bf58a 498 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 499
8dbcd839 500 /* The UIMM field in a VX form instruction. */
786e2c0f 501#define UIMM SIMM + 1
b84bf58a 502 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 503
112290ab 504 /* The SHB field in a VA form instruction. */
786e2c0f 505#define SHB UIMM + 1
b84bf58a 506 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 507
112290ab 508 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 509#define EVUIMM_2 SHB + 1
b84bf58a 510 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 511
112290ab 512 /* The other UIMM field in a word EVX form instruction. */
23976049 513#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 514 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 515
112290ab 516 /* The other UIMM field in a double EVX form instruction. */
23976049 517#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 518 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 519
ff3a6ee3 520 /* The WS field. */
23976049 521#define WS EVUIMM_8 + 1
b84bf58a 522 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 523
c3d65c1c
BE		 524 /* PowerPC paired singles extensions. */
525 /* W bit in the pair singles instructions for x type instructions. */
526#define PSWM WS + 1
527 { 0x1, 10, 0, 0, 0 },
528
529 /* IDX bits for quantization in the pair singles instructions. */
530#define PSQ PSWM + 1
531 { 0x7, 12, 0, 0, 0 },
532
533 /* IDX bits for quantization in the pair singles x-type instructions. */
534#define PSQM PSQ + 1
535 { 0x7, 7, 0, 0, 0 },
536
537 /* Smaller D field for quantization in the pair singles instructions. */
538#define PSD PSQM + 1
539 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
540
541#define A_L PSD + 1
ea192fa3 542#define W A_L
c3d65c1c 543#define MTMSRD_L W
b84bf58a 544 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 545
c3d65c1c 546#define RMC MTMSRD_L + 1
b84bf58a 547 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 548
549#define R RMC + 1
b84bf58a 550 { 0x1, 16, NULL, NULL, 0 },
702f0fb4
PB		 551
552#define SP R + 1
b84bf58a 553 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 554
555#define S SP + 1
b84bf58a 556 { 0x1, 20, NULL, NULL, 0 },
702f0fb4
PB		 557
558 /* SH field starting at bit position 16. */
559#define SH16 S + 1
0bbdef92
AM		 560 /* The DCM and DGM fields in a Z form instruction. */
561#define DCM SH16
562#define DGM DCM
b84bf58a 563 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 564
702f0fb4 565 /* The EH field in larx instruction. */
717bbdf1 566#define EH SH16 + 1
b84bf58a 567 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 568
569 /* The L field in an mtfsf or XFL form instruction. */
570#define XFL_L EH + 1
571 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
252b5132
RH		 572};
573
b84bf58a
AM		 574const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
575 / sizeof (powerpc_operands[0]));
576
252b5132
RH		 577/* The functions used to insert and extract complicated operands. */
578
579/* The BA field in an XL form instruction when it must be the same as
580 the BT field in the same instruction. This operand is marked FAKE.
581 The insertion function just copies the BT field into the BA field,
582 and the extraction function just checks that the fields are the
583 same. */
584
252b5132 585static unsigned long
2fbfdc41
AM		 586insert_bat (unsigned long insn,
587 long value ATTRIBUTE_UNUSED,
588 int dialect ATTRIBUTE_UNUSED,
589 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 590{
591 return insn | (((insn >> 21) & 0x1f) << 16);
592}
593
594static long
2fbfdc41
AM		 595extract_bat (unsigned long insn,
596 int dialect ATTRIBUTE_UNUSED,
597 int *invalid)
252b5132 598{
8427c424 599 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 600 *invalid = 1;
601 return 0;
602}
603
604/* The BB field in an XL form instruction when it must be the same as
605 the BA field in the same instruction. This operand is marked FAKE.
606 The insertion function just copies the BA field into the BB field,
607 and the extraction function just checks that the fields are the
608 same. */
609
252b5132 610static unsigned long
2fbfdc41
AM		 611insert_bba (unsigned long insn,
612 long value ATTRIBUTE_UNUSED,
613 int dialect ATTRIBUTE_UNUSED,
614 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 615{
616 return insn | (((insn >> 16) & 0x1f) << 11);
617}
618
619static long
2fbfdc41
AM		 620extract_bba (unsigned long insn,
621 int dialect ATTRIBUTE_UNUSED,
622 int *invalid)
252b5132 623{
8427c424 624 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 625 *invalid = 1;
626 return 0;
627}
628
252b5132
RH		 629/* The BD field in a B form instruction when the - modifier is used.
630 This modifier means that the branch is not expected to be taken.
94efba12
AM		 631 For chips built to versions of the architecture prior to version 2
632 (ie. not Power4 compatible), we set the y bit of the BO field to 1
633 if the offset is negative. When extracting, we require that the y
634 bit be 1 and that the offset be positive, since if the y bit is 0
635 we just want to print the normal form of the instruction.
636 Power4 compatible targets use two bits, "a", and "t", instead of
637 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
638 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
639 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 640 for branch on CTR. We only handle the taken/not-taken hint here.
641 Note that we don't relax the conditions tested here when
642 disassembling with -Many because insns using extract_bdm and
643 extract_bdp always occur in pairs. One or the other will always
644 be valid. */
252b5132 645
252b5132 646static unsigned long
2fbfdc41
AM		 647insert_bdm (unsigned long insn,
648 long value,
649 int dialect,
650 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 651{
94efba12 652 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 653 {
654 if ((value & 0x8000) != 0)
655 insn |= 1 << 21;
656 }
657 else
658 {
659 if ((insn & (0x14 << 21)) == (0x04 << 21))
660 insn |= 0x02 << 21;
661 else if ((insn & (0x14 << 21)) == (0x10 << 21))
662 insn |= 0x08 << 21;
663 }
252b5132
RH		 664 return insn | (value & 0xfffc);
665}
666
667static long
2fbfdc41
AM		 668extract_bdm (unsigned long insn,
669 int dialect,
670 int *invalid)
252b5132 671{
8427c424 672 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 673 {
8427c424
AM		 674 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
675 *invalid = 1;
802a735e 676 }
8427c424
AM		 677 else
678 {
679 if ((insn & (0x17 << 21)) != (0x06 << 21)
680 && (insn & (0x1d << 21)) != (0x18 << 21))
681 *invalid = 1;
682 }
683
802a735e 684 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 685}
686
687/* The BD field in a B form instruction when the + modifier is used.
688 This is like BDM, above, except that the branch is expected to be
689 taken. */
690
252b5132 691static unsigned long
2fbfdc41
AM		 692insert_bdp (unsigned long insn,
693 long value,
694 int dialect,
695 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 696{
94efba12 697 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 698 {
699 if ((value & 0x8000) == 0)
700 insn |= 1 << 21;
701 }
702 else
703 {
704 if ((insn & (0x14 << 21)) == (0x04 << 21))
705 insn |= 0x03 << 21;
706 else if ((insn & (0x14 << 21)) == (0x10 << 21))
707 insn |= 0x09 << 21;
708 }
252b5132
RH		 709 return insn | (value & 0xfffc);
710}
711
712static long
2fbfdc41
AM		 713extract_bdp (unsigned long insn,
714 int dialect,
715 int *invalid)
252b5132 716{
8427c424 717 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 718 {
8427c424
AM		 719 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
720 *invalid = 1;
721 }
722 else
723 {
724 if ((insn & (0x17 << 21)) != (0x07 << 21)
725 && (insn & (0x1d << 21)) != (0x19 << 21))
726 *invalid = 1;
802a735e 727 }
8427c424 728
802a735e 729 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 730}
731
732/* Check for legal values of a BO field. */
733
734static int
ba4e851b 735valid_bo (long value, int dialect, int extract)
252b5132 736{
94efba12 737 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 738 {
ba4e851b 739 int valid;
802a735e
AM		 740 /* Certain encodings have bits that are required to be zero.
741 These are (z must be zero, y may be anything):
742 001zy
743 011zy
744 1z00y
745 1z01y
746 1z1zz
747 */
748 switch (value & 0x14)
749 {
750 default:
751 case 0:
ba4e851b
AM		 752 valid = 1;
753 break;
802a735e 754 case 0x4:
ba4e851b
AM		 755 valid = (value & 0x2) == 0;
756 break;
802a735e 757 case 0x10:
ba4e851b
AM		 758 valid = (value & 0x8) == 0;
759 break;
802a735e 760 case 0x14:
ba4e851b
AM		 761 valid = value == 0x14;
762 break;
802a735e 763 }
ba4e851b
AM		 764 /* When disassembling with -Many, accept power4 encodings too. */
765 if (valid
766 || (dialect & PPC_OPCODE_ANY) == 0
767 || !extract)
768 return valid;
802a735e 769 }
ba4e851b
AM		 770
771 /* Certain encodings have bits that are required to be zero.
772 These are (z must be zero, a & t may be anything):
773 0000z
774 0001z
775 0100z
776 0101z
777 001at
778 011at
779 1a00t
780 1a01t
781 1z1zz
782 */
783 if ((value & 0x14) == 0)
784 return (value & 0x1) == 0;
785 else if ((value & 0x14) == 0x14)
786 return value == 0x14;
802a735e 787 else
ba4e851b 788 return 1;
252b5132
RH		 789}
790
791/* The BO field in a B form instruction. Warn about attempts to set
792 the field to an illegal value. */
793
794static unsigned long
2fbfdc41
AM		 795insert_bo (unsigned long insn,
796 long value,
797 int dialect,
798 const char **errmsg)
252b5132 799{
ba4e851b 800 if (!valid_bo (value, dialect, 0))
252b5132
RH		 801 *errmsg = _("invalid conditional option");
802 return insn | ((value & 0x1f) << 21);
803}
804
805static long
2fbfdc41
AM		 806extract_bo (unsigned long insn,
807 int dialect,
808 int *invalid)
252b5132
RH		 809{
810 long value;
811
812 value = (insn >> 21) & 0x1f;
ba4e851b 813 if (!valid_bo (value, dialect, 1))
252b5132
RH		 814 *invalid = 1;
815 return value;
816}
817
818/* The BO field in a B form instruction when the + or - modifier is
819 used. This is like the BO field, but it must be even. When
820 extracting it, we force it to be even. */
821
822static unsigned long
2fbfdc41
AM		 823insert_boe (unsigned long insn,
824 long value,
825 int dialect,
826 const char **errmsg)
252b5132 827{
ba4e851b 828 if (!valid_bo (value, dialect, 0))
8427c424
AM		 829 *errmsg = _("invalid conditional option");
830 else if ((value & 1) != 0)
831 *errmsg = _("attempt to set y bit when using + or - modifier");
832
252b5132
RH		 833 return insn | ((value & 0x1f) << 21);
834}
835
836static long
2fbfdc41
AM		 837extract_boe (unsigned long insn,
838 int dialect,
839 int *invalid)
252b5132
RH		 840{
841 long value;
842
843 value = (insn >> 21) & 0x1f;
ba4e851b 844 if (!valid_bo (value, dialect, 1))
252b5132
RH		 845 *invalid = 1;
846 return value & 0x1e;
847}
848
2fbfdc41
AM		 849/* FXM mask in mfcr and mtcrf instructions. */
850
851static unsigned long
852insert_fxm (unsigned long insn,
853 long value,
854 int dialect,
855 const char **errmsg)
c168870a 856{
98e69875
AM		 857 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
858 one bit of the mask field is set. */
859 if ((insn & (1 << 20)) != 0)
860 {
861 if (value == 0 || (value & -value) != value)
862 {
863 *errmsg = _("invalid mask field");
864 value = 0;
865 }
866 }
867
c168870a
AM		 868 /* If the optional field on mfcr is missing that means we want to use
869 the old form of the instruction that moves the whole cr. In that
870 case we'll have VALUE zero. There doesn't seem to be a way to
871 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 872 else if (value == 0)
c168870a
AM		 873 ;
874
875 /* If only one bit of the FXM field is set, we can use the new form
661bd698 876 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 877 encoding, this is not backward compatible. Do not generate the
878 new form unless -mpower4 has been given, or -many and the two
879 operand form of mfcr was used. */
880 else if ((value & -value) == value
881 && ((dialect & PPC_OPCODE_POWER4) != 0
882 || ((dialect & PPC_OPCODE_ANY) != 0
883 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 884 insn |= 1 << 20;
885
886 /* Any other value on mfcr is an error. */
887 else if ((insn & (0x3ff << 1)) == 19 << 1)
888 {
8427c424 889 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 890 value = 0;
891 }
892
893 return insn | ((value & 0xff) << 12);
894}
895
2fbfdc41
AM		 896static long
897extract_fxm (unsigned long insn,
98e69875 898 int dialect ATTRIBUTE_UNUSED,
2fbfdc41 899 int *invalid)
c168870a
AM		 900{
901 long mask = (insn >> 12) & 0xff;
902
903 /* Is this a Power4 insn? */
904 if ((insn & (1 << 20)) != 0)
905 {
98e69875
AM		 906 /* Exactly one bit of MASK should be set. */
907 if (mask == 0 || (mask & -mask) != mask)
8427c424 908 *invalid = 1;
c168870a
AM		 909 }
910
911 /* Check that non-power4 form of mfcr has a zero MASK. */
912 else if ((insn & (0x3ff << 1)) == 19 << 1)
913 {
8427c424 914 if (mask != 0)
c168870a
AM		 915 *invalid = 1;
916 }
917
918 return mask;
919}
920
252b5132
RH		 921/* The MB and ME fields in an M form instruction expressed as a single
922 operand which is itself a bitmask. The extraction function always
923 marks it as invalid, since we never want to recognize an
924 instruction which uses a field of this type. */
925
926static unsigned long
2fbfdc41
AM		 927insert_mbe (unsigned long insn,
928 long value,
929 int dialect ATTRIBUTE_UNUSED,
930 const char **errmsg)
252b5132
RH		 931{
932 unsigned long uval, mask;
933 int mb, me, mx, count, last;
934
935 uval = value;
936
937 if (uval == 0)
938 {
8427c424 939 *errmsg = _("illegal bitmask");
252b5132
RH		 940 return insn;
941 }
942
943 mb = 0;
944 me = 32;
945 if ((uval & 1) != 0)
946 last = 1;
947 else
948 last = 0;
949 count = 0;
950
951 /* mb: location of last 0->1 transition */
952 /* me: location of last 1->0 transition */
953 /* count: # transitions */
954
0deb7ac5 955 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 956 {
957 if ((uval & mask) && !last)
958 {
959 ++count;
960 mb = mx;
961 last = 1;
962 }
963 else if (!(uval & mask) && last)
964 {
965 ++count;
966 me = mx;
967 last = 0;
968 }
969 }
970 if (me == 0)
971 me = 32;
972
973 if (count != 2 && (count != 0 || ! last))
8427c424 974 *errmsg = _("illegal bitmask");
252b5132
RH		 975
976 return insn | (mb << 6) | ((me - 1) << 1);
977}
978
979static long
2fbfdc41
AM		 980extract_mbe (unsigned long insn,
981 int dialect ATTRIBUTE_UNUSED,
982 int *invalid)
252b5132
RH		 983{
984 long ret;
985 int mb, me;
986 int i;
987
8427c424 988 *invalid = 1;
252b5132
RH		 989
990 mb = (insn >> 6) & 0x1f;
991 me = (insn >> 1) & 0x1f;
992 if (mb < me + 1)
993 {
994 ret = 0;
995 for (i = mb; i <= me; i++)
0deb7ac5 996 ret |= 1L << (31 - i);
252b5132
RH		 997 }
998 else if (mb == me + 1)
8427c424 999 ret = ~0;
252b5132
RH		 1000 else /* (mb > me + 1) */
1001 {
2fbfdc41 1002 ret = ~0;
252b5132 1003 for (i = me + 1; i < mb; i++)
0deb7ac5 1004 ret &= ~(1L << (31 - i));
252b5132
RH		 1005 }
1006 return ret;
1007}
1008
1009/* The MB or ME field in an MD or MDS form instruction. The high bit
1010 is wrapped to the low end. */
1011
252b5132 1012static unsigned long
2fbfdc41
AM		 1013insert_mb6 (unsigned long insn,
1014 long value,
1015 int dialect ATTRIBUTE_UNUSED,
1016 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1017{
1018 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1019}
1020
252b5132 1021static long
2fbfdc41
AM		 1022extract_mb6 (unsigned long insn,
1023 int dialect ATTRIBUTE_UNUSED,
1024 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1025{
1026 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1027}
1028
1029/* The NB field in an X form instruction. The value 32 is stored as
1030 0. */
1031
252b5132 1032static long
2fbfdc41
AM		 1033extract_nb (unsigned long insn,
1034 int dialect ATTRIBUTE_UNUSED,
1035 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1036{
1037 long ret;
1038
1039 ret = (insn >> 11) & 0x1f;
1040 if (ret == 0)
1041 ret = 32;
1042 return ret;
1043}
1044
1045/* The NSI field in a D form instruction. This is the same as the SI
1046 field, only negated. The extraction function always marks it as
1047 invalid, since we never want to recognize an instruction which uses
1048 a field of this type. */
1049
252b5132 1050static unsigned long
2fbfdc41
AM		 1051insert_nsi (unsigned long insn,
1052 long value,
1053 int dialect ATTRIBUTE_UNUSED,
1054 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1055{
2fbfdc41 1056 return insn | (-value & 0xffff);
252b5132
RH		 1057}
1058
1059static long
2fbfdc41
AM		 1060extract_nsi (unsigned long insn,
1061 int dialect ATTRIBUTE_UNUSED,
1062 int *invalid)
252b5132 1063{
8427c424 1064 *invalid = 1;
2fbfdc41 1065 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1066}
1067
1068/* The RA field in a D or X form instruction which is an updating
1069 load, which means that the RA field may not be zero and may not
1070 equal the RT field. */
1071
1072static unsigned long
2fbfdc41
AM		 1073insert_ral (unsigned long insn,
1074 long value,
1075 int dialect ATTRIBUTE_UNUSED,
1076 const char **errmsg)
252b5132
RH		 1077{
1078 if (value == 0
1079 || (unsigned long) value == ((insn >> 21) & 0x1f))
1080 *errmsg = "invalid register operand when updating";
1081 return insn | ((value & 0x1f) << 16);
1082}
1083
1084/* The RA field in an lmw instruction, which has special value
1085 restrictions. */
1086
1087static unsigned long
2fbfdc41
AM		 1088insert_ram (unsigned long insn,
1089 long value,
1090 int dialect ATTRIBUTE_UNUSED,
1091 const char **errmsg)
252b5132
RH		 1092{
1093 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1094 *errmsg = _("index register in load range");
1095 return insn | ((value & 0x1f) << 16);
1096}
1097
fdd12ef3 1098/* The RA field in the DQ form lq instruction, which has special
8427c424 1099 value restrictions. */
adadcc0c 1100
adadcc0c 1101static unsigned long
2fbfdc41
AM		 1102insert_raq (unsigned long insn,
1103 long value,
1104 int dialect ATTRIBUTE_UNUSED,
1105 const char **errmsg)
adadcc0c
AM		 1106{
1107 long rtvalue = (insn & RT_MASK) >> 21;
1108
8427c424 1109 if (value == rtvalue)
adadcc0c
AM		 1110 *errmsg = _("source and target register operands must be different");
1111 return insn | ((value & 0x1f) << 16);
1112}
1113
252b5132
RH		 1114/* The RA field in a D or X form instruction which is an updating
1115 store or an updating floating point load, which means that the RA
1116 field may not be zero. */
1117
1118static unsigned long
2fbfdc41
AM		 1119insert_ras (unsigned long insn,
1120 long value,
1121 int dialect ATTRIBUTE_UNUSED,
1122 const char **errmsg)
252b5132
RH		 1123{
1124 if (value == 0)
1125 *errmsg = _("invalid register operand when updating");
1126 return insn | ((value & 0x1f) << 16);
1127}
1128
1129/* The RB field in an X form instruction when it must be the same as
1130 the RS field in the instruction. This is used for extended
1131 mnemonics like mr. This operand is marked FAKE. The insertion
1132 function just copies the BT field into the BA field, and the
1133 extraction function just checks that the fields are the same. */
1134
252b5132 1135static unsigned long
2fbfdc41
AM		 1136insert_rbs (unsigned long insn,
1137 long value ATTRIBUTE_UNUSED,
1138 int dialect ATTRIBUTE_UNUSED,
1139 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1140{
1141 return insn | (((insn >> 21) & 0x1f) << 11);
1142}
1143
1144static long
2fbfdc41
AM		 1145extract_rbs (unsigned long insn,
1146 int dialect ATTRIBUTE_UNUSED,
1147 int *invalid)
252b5132 1148{
8427c424 1149 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1150 *invalid = 1;
1151 return 0;
1152}
1153
1154/* The SH field in an MD form instruction. This is split. */
1155
252b5132 1156static unsigned long
2fbfdc41
AM		 1157insert_sh6 (unsigned long insn,
1158 long value,
1159 int dialect ATTRIBUTE_UNUSED,
1160 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1161{
1162 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1163}
1164
252b5132 1165static long
2fbfdc41
AM		 1166extract_sh6 (unsigned long insn,
1167 int dialect ATTRIBUTE_UNUSED,
1168 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1169{
1170 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1171}
1172
1173/* The SPR field in an XFX form instruction. This is flipped--the
1174 lower 5 bits are stored in the upper 5 and vice- versa. */
1175
1176static unsigned long
2fbfdc41
AM		 1177insert_spr (unsigned long insn,
1178 long value,
1179 int dialect ATTRIBUTE_UNUSED,
1180 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1181{
1182 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1183}
1184
1185static long
2fbfdc41
AM		 1186extract_spr (unsigned long insn,
1187 int dialect ATTRIBUTE_UNUSED,
1188 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1189{
1190 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1191}
1192
da99ee72
AM		 1193/* Some dialects have 8 SPRG registers instead of the standard 4. */
1194
1195static unsigned long
1196insert_sprg (unsigned long insn,
1197 long value,
1198 int dialect,
1199 const char **errmsg)
1200{
1201 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1202 as a synonym. If ever a 405 specific dialect is added this
1203 check should use that instead. */
1204 if (value > 7
1205 || (value > 3
1206 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1207 *errmsg = _("invalid sprg number");
1208
1209 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1210 user mode. Anything else must use spr 272..279. */
1211 if (value <= 3 || (insn & 0x100) != 0)
1212 value |= 0x10;
1213
1214 return insn | ((value & 0x17) << 16);
1215}
1216
1217static long
1218extract_sprg (unsigned long insn,
1219 int dialect,
1220 int *invalid)
1221{
1222 unsigned long val = (insn >> 16) & 0x1f;
1223
1224 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1225 If not BOOKE or 405, then both use only 272..275. */
1226 if (val <= 3
1227 || (val < 0x10 && (insn & 0x100) != 0)
1228 || (val - 0x10 > 3
1229 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1230 *invalid = 1;
1231 return val & 7;
1232}
1233
252b5132
RH		 1234/* The TBR field in an XFX instruction. This is just like SPR, but it
1235 is optional. When TBR is omitted, it must be inserted as 268 (the
1236 magic number of the TB register). These functions treat 0
1237 (indicating an omitted optional operand) as 268. This means that
1238 ``mftb 4,0'' is not handled correctly. This does not matter very
1239 much, since the architecture manual does not define mftb as
1240 accepting any values other than 268 or 269. */
1241
1242#define TB (268)
1243
1244static unsigned long
2fbfdc41
AM		 1245insert_tbr (unsigned long insn,
1246 long value,
1247 int dialect ATTRIBUTE_UNUSED,
1248 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1249{
1250 if (value == 0)
1251 value = TB;
1252 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1253}
1254
1255static long
2fbfdc41
AM		 1256extract_tbr (unsigned long insn,
1257 int dialect ATTRIBUTE_UNUSED,
1258 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1259{
1260 long ret;
1261
1262 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1263 if (ret == TB)
1264 ret = 0;
1265 return ret;
1266}
1267\f
1268/* Macros used to form opcodes. */
1269
1270/* The main opcode. */
1271#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1272#define OP_MASK OP (0x3f)
1273
1274/* The main opcode combined with a trap code in the TO field of a D
1275 form instruction. Used for extended mnemonics for the trap
1276 instructions. */
1277#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1278#define OPTO_MASK (OP_MASK | TO_MASK)
1279
1280/* The main opcode combined with a comparison size bit in the L field
1281 of a D form or X form instruction. Used for extended mnemonics for
1282 the comparison instructions. */
1283#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1284#define OPL_MASK OPL (0x3f,1)
1285
1286/* An A form instruction. */
1287#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1288#define A_MASK A (0x3f, 0x1f, 1)
1289
1290/* An A_MASK with the FRB field fixed. */
1291#define AFRB_MASK (A_MASK | FRB_MASK)
1292
1293/* An A_MASK with the FRC field fixed. */
1294#define AFRC_MASK (A_MASK | FRC_MASK)
1295
1296/* An A_MASK with the FRA and FRC fields fixed. */
1297#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1298
702f0fb4
PB		 1299/* An AFRAFRC_MASK, but with L bit clear. */
1300#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1301
252b5132
RH		 1302/* A B form instruction. */
1303#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1304#define B_MASK B (0x3f, 1, 1)
1305
1306/* A B form instruction setting the BO field. */
1307#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1308#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1309
1310/* A BBO_MASK with the y bit of the BO field removed. This permits
1311 matching a conditional branch regardless of the setting of the y
94efba12 1312 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 1313#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 1314#define AT1_MASK (((unsigned long) 3) << 21)
1315#define AT2_MASK (((unsigned long) 9) << 21)
1316#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1317#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1318
1319/* A B form instruction setting the BO field and the condition bits of
1320 the BI field. */
1321#define BBOCB(op, bo, cb, aa, lk) \
1322 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1323#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1324
1325/* A BBOCB_MASK with the y bit of the BO field removed. */
1326#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1327#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1328#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1329
1330/* A BBOYCB_MASK in which the BI field is fixed. */
1331#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1332#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1333
23976049
EZ		 1334/* An Context form instruction. */
1335#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1336#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1337
1338/* An User Context form instruction. */
1339#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1340#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1341
252b5132
RH		 1342/* The main opcode mask with the RA field clear. */
1343#define DRA_MASK (OP_MASK | RA_MASK)
1344
1345/* A DS form instruction. */
1346#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1347#define DS_MASK DSO (0x3f, 3)
1348
418c1742
MG		 1349/* A DE form instruction. */
1350#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1351#define DE_MASK DEO (0x3e, 0xf)
1352
23976049
EZ		 1353/* An EVSEL form instruction. */
1354#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1355#define EVSEL_MASK EVSEL(0x3f, 0xff)
1356
252b5132
RH		 1357/* An M form instruction. */
1358#define M(op, rc) (OP (op) | ((rc) & 1))
1359#define M_MASK M (0x3f, 1)
1360
1361/* An M form instruction with the ME field specified. */
1362#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1363
1364/* An M_MASK with the MB and ME fields fixed. */
1365#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1366
1367/* An M_MASK with the SH and ME fields fixed. */
1368#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1369
1370/* An MD form instruction. */
1371#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1372#define MD_MASK MD (0x3f, 0x7, 1)
1373
1374/* An MD_MASK with the MB field fixed. */
1375#define MDMB_MASK (MD_MASK | MB6_MASK)
1376
1377/* An MD_MASK with the SH field fixed. */
1378#define MDSH_MASK (MD_MASK | SH6_MASK)
1379
1380/* An MDS form instruction. */
1381#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1382#define MDS_MASK MDS (0x3f, 0xf, 1)
1383
1384/* An MDS_MASK with the MB field fixed. */
1385#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1386
1387/* An SC form instruction. */
1388#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1389#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1390
112290ab 1391/* An VX form instruction. */
786e2c0f
C		 1392#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1393
112290ab 1394/* The mask for an VX form instruction. */
786e2c0f
C		 1395#define VX_MASK VX(0x3f, 0x7ff)
1396
112290ab 1397/* An VA form instruction. */
2613489e 1398#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1399
112290ab 1400/* The mask for an VA form instruction. */
2613489e 1401#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1402
112290ab 1403/* An VXR form instruction. */
786e2c0f
C		 1404#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1405
112290ab 1406/* The mask for a VXR form instruction. */
786e2c0f
C		 1407#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1408
252b5132
RH		 1409/* An X form instruction. */
1410#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1411
702f0fb4
PB		 1412/* A Z form instruction. */
1413#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1414
252b5132
RH		 1415/* An X form instruction with the RC bit specified. */
1416#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1417
702f0fb4
PB		 1418/* A Z form instruction with the RC bit specified. */
1419#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1420
252b5132
RH		 1421/* The mask for an X form instruction. */
1422#define X_MASK XRC (0x3f, 0x3ff, 1)
1423
702f0fb4
PB		 1424/* The mask for a Z form instruction. */
1425#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 1426#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 1427
252b5132
RH		 1428/* An X_MASK with the RA field fixed. */
1429#define XRA_MASK (X_MASK | RA_MASK)
1430
ea192fa3
PB		 1431/* An XRA_MASK with the W field clear. */
1432#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1433
252b5132
RH		 1434/* An X_MASK with the RB field fixed. */
1435#define XRB_MASK (X_MASK | RB_MASK)
1436
1437/* An X_MASK with the RT field fixed. */
1438#define XRT_MASK (X_MASK | RT_MASK)
1439
702f0fb4
PB		 1440/* An XRT_MASK mask with the L bits clear. */
1441#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1442
252b5132
RH		 1443/* An X_MASK with the RA and RB fields fixed. */
1444#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1445
112290ab 1446/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1447#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1448
252b5132
RH		 1449/* An X_MASK with the RT and RA fields fixed. */
1450#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1451
98acc1c5
AM		 1452/* An XRTRA_MASK, but with L bit clear. */
1453#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1454
f3806e43
BE		 1455/* An X form instruction with the L bit specified. */
1456#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132
RH		 1457
1458/* The mask for an X form comparison instruction. */
1459#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1460
520ceea4
BE		 1461/* The mask for an X form comparison instruction with the L field
1462 fixed. */
1463#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1464
1465/* An X form trap instruction with the TO field specified. */
1466#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1467#define XTO_MASK (X_MASK | TO_MASK)
1468
e0c21649
GK		 1469/* An X form tlb instruction with the SH field specified. */
1470#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1471#define XTLB_MASK (X_MASK | SH_MASK)
1472
6ba045b1
AM		 1473/* An X form sync instruction. */
1474#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1475
1476/* An X form sync instruction with everything filled in except the LS field. */
1477#define XSYNC_MASK (0xff9fffff)
1478
702f0fb4
PB		 1479/* An X_MASK, but with the EH bit clear. */
1480#define XEH_MASK (X_MASK & ~((unsigned long )1))
1481
f5c120c5
MG		 1482/* An X form AltiVec dss instruction. */
1483#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1484#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1485
252b5132
RH		 1486/* An XFL form instruction. */
1487#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 1488#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 1489
23976049 1490/* An X form isel instruction. */
de866fcc
AM		 1491#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1492#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 1493
252b5132
RH		 1494/* An XL form instruction with the LK field set to 0. */
1495#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1496
1497/* An XL form instruction which uses the LK field. */
1498#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1499
1500/* The mask for an XL form instruction. */
1501#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1502
1503/* An XL form instruction which explicitly sets the BO field. */
1504#define XLO(op, bo, xop, lk) \
1505 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1506#define XLO_MASK (XL_MASK | BO_MASK)
1507
1508/* An XL form instruction which explicitly sets the y bit of the BO
1509 field. */
1510#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1511#define XLYLK_MASK (XL_MASK | Y_MASK)
1512
1513/* An XL form instruction which sets the BO field and the condition
1514 bits of the BI field. */
1515#define XLOCB(op, bo, cb, xop, lk) \
1516 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1517#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1518
1519/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1520#define XLBB_MASK (XL_MASK | BB_MASK)
1521#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1522#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1523
d0618d1c
AM		 1524/* A mask for branch instructions using the BH field. */
1525#define XLBH_MASK (XL_MASK | (0x1c << 11))
1526
252b5132
RH		 1527/* An XL_MASK with the BO and BB fields fixed. */
1528#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1529
1530/* An XL_MASK with the BO, BI and BB fields fixed. */
1531#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1532
1533/* An XO form instruction. */
1534#define XO(op, xop, oe, rc) \
1535 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1536#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1537
1538/* An XO_MASK with the RB field fixed. */
1539#define XORB_MASK (XO_MASK | RB_MASK)
1540
c3d65c1c
BE		 1541/* An XOPS form instruction for paired singles. */
1542#define XOPS(op, xop, rc) \
1543 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1544#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1545
1546
252b5132
RH		 1547/* An XS form instruction. */
1548#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1549#define XS_MASK XS (0x3f, 0x1ff, 1)
1550
1551/* A mask for the FXM version of an XFX form instruction. */
98e69875 1552#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1553
1554/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1555#define XFXM(op, xop, fxm, p4) \
1556 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1557 | ((unsigned long)(p4) << 20))
252b5132
RH		 1558
1559/* An XFX form instruction with the SPR field filled in. */
1560#define XSPR(op, xop, spr) \
1561 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1562#define XSPR_MASK (X_MASK | SPR_MASK)
1563
1564/* An XFX form instruction with the SPR field filled in except for the
1565 SPRBAT field. */
1566#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1567
1568/* An XFX form instruction with the SPR field filled in except for the
1569 SPRG field. */
b84bf58a 1570#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 1571
1572/* An X form instruction with everything filled in except the E field. */
1573#define XE_MASK (0xffff7fff)
1574
23976049
EZ		 1575/* An X form user context instruction. */
1576#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1577#define XUC_MASK XUC(0x3f, 0x1f)
1578
c3d65c1c
BE		 1579/* An XW form instruction. */
1580#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1581/* The mask for a G form instruction. rc not supported at present. */
1582#define XW_MASK XW (0x3f, 0x3f, 0)
1583
252b5132
RH		 1584/* The BO encodings used in extended conditional branch mnemonics. */
1585#define BODNZF (0x0)
1586#define BODNZFP (0x1)
1587#define BODZF (0x2)
1588#define BODZFP (0x3)
252b5132
RH		 1589#define BODNZT (0x8)
1590#define BODNZTP (0x9)
1591#define BODZT (0xa)
1592#define BODZTP (0xb)
802a735e
AM		 1593
1594#define BOF (0x4)
1595#define BOFP (0x5)
94efba12
AM		 1596#define BOFM4 (0x6)
1597#define BOFP4 (0x7)
252b5132
RH		 1598#define BOT (0xc)
1599#define BOTP (0xd)
94efba12
AM		 1600#define BOTM4 (0xe)
1601#define BOTP4 (0xf)
802a735e 1602
252b5132
RH		 1603#define BODNZ (0x10)
1604#define BODNZP (0x11)
1605#define BODZ (0x12)
1606#define BODZP (0x13)
94efba12
AM		 1607#define BODNZM4 (0x18)
1608#define BODNZP4 (0x19)
1609#define BODZM4 (0x1a)
1610#define BODZP4 (0x1b)
802a735e 1611
252b5132
RH		 1612#define BOU (0x14)
1613
1614/* The BI condition bit encodings used in extended conditional branch
1615 mnemonics. */
1616#define CBLT (0)
1617#define CBGT (1)
1618#define CBEQ (2)
1619#define CBSO (3)
1620
1621/* The TO encodings used in extended trap mnemonics. */
1622#define TOLGT (0x1)
1623#define TOLLT (0x2)
1624#define TOEQ (0x4)
1625#define TOLGE (0x5)
1626#define TOLNL (0x5)
1627#define TOLLE (0x6)
1628#define TOLNG (0x6)
1629#define TOGT (0x8)
1630#define TOGE (0xc)
1631#define TONL (0xc)
1632#define TOLT (0x10)
1633#define TOLE (0x14)
1634#define TONG (0x14)
1635#define TONE (0x18)
1636#define TOU (0x1f)
1637\f
1638/* Smaller names for the flags so each entry in the opcodes table will
1639 fit on a single line. */
1640#undef PPC
de866fcc 1641#define PPC PPC_OPCODE_PPC
661bd698 1642#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
94efba12 1643#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
661bd698 1644#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 1645#define POWER5 PPC_OPCODE_POWER5
702f0fb4 1646#define POWER6 PPC_OPCODE_POWER6
ede602d7 1647#define CELL PPC_OPCODE_CELL
de866fcc
AM		 1648#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1649#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
418c1742 1650#define PPC403 PPC_OPCODE_403
e0c21649 1651#define PPC405 PPC403
7d5b217e 1652#define PPC440 PPC_OPCODE_440
252b5132 1653#define PPC750 PPC
33e8d5ac 1654#define PPC7450 PPC
252b5132 1655#define PPC860 PPC
c3d65c1c 1656#define PPCPS PPC_OPCODE_PPCPS
a404d431 1657#define PPCVEC PPC_OPCODE_ALTIVEC
de866fcc
AM		 1658#define POWER PPC_OPCODE_POWER
1659#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1660#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1661#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1662#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1663#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1664#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 1665#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc
AM		 1666#define MFDEC1 PPC_OPCODE_POWER
1667#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742 1668#define BOOKE PPC_OPCODE_BOOKE
de866fcc
AM		 1669#define BOOKE64 PPC_OPCODE_BOOKE64
1670#define CLASSIC PPC_OPCODE_CLASSIC
36ae0db3 1671#define PPCE300 PPC_OPCODE_E300
23976049 1672#define PPCSPE PPC_OPCODE_SPE
de866fcc 1673#define PPCISEL PPC_OPCODE_ISEL
23976049 1674#define PPCEFS PPC_OPCODE_EFS
de866fcc 1675#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 1676#define PPCPMR PPC_OPCODE_PMR
de866fcc 1677#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1678#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1679#define PPCRFMCI PPC_OPCODE_RFMCI
252b5132
RH		 1680\f
1681/* The opcode table.
1682
1683 The format of the opcode table is:
1684
de866fcc 1685 NAME OPCODE MASK FLAGS {OPERANDS}
252b5132
RH		 1686
1687 NAME is the name of the instruction.
1688 OPCODE is the instruction opcode.
1689 MASK is the opcode mask; this is used to tell the disassembler
1690 which bits in the actual opcode must match OPCODE.
1691 FLAGS are flags indicated what processors support the instruction.
1692 OPERANDS is the list of operands.
1693
1694 The disassembler reads the table in order and prints the first
1695 instruction which matches, so this table is sorted to put more
de866fcc
AM		 1696 specific instructions before more general instructions.
1697
1698 This table must be sorted by major opcode. Please try to keep it
1699 vaguely sorted within major opcode too, except of course where
1700 constrained otherwise by disassembler operation. */
252b5132
RH		 1701
1702const struct powerpc_opcode powerpc_opcodes[] = {
de866fcc
AM		 1703{"attn", X(0,256), X_MASK, POWER4, {0}},
1704{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, {RA, SI}},
1705{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, {RA, SI}},
1706{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, {RA, SI}},
1707{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, {RA, SI}},
1708{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, {RA, SI}},
1709{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, {RA, SI}},
1710{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, {RA, SI}},
1711{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, {RA, SI}},
1712{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, {RA, SI}},
1713{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, {RA, SI}},
1714{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, {RA, SI}},
1715{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, {RA, SI}},
1716{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, {RA, SI}},
1717{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, {RA, SI}},
1718{"tdi", OP(2), OP_MASK, PPC64, {TO, RA, SI}},
1719
1720{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, {RA, SI}},
1721{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, {RA, SI}},
1722{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, {RA, SI}},
1723{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, {RA, SI}},
1724{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, {RA, SI}},
1725{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, {RA, SI}},
1726{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, {RA, SI}},
1727{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, {RA, SI}},
1728{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, {RA, SI}},
1729{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, {RA, SI}},
1730{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, {RA, SI}},
1731{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, {RA, SI}},
1732{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, {RA, SI}},
1733{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, {RA, SI}},
1734{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, {RA, SI}},
1735{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, {RA, SI}},
1736{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, {RA, SI}},
1737{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, {RA, SI}},
1738{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, {RA, SI}},
1739{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, {RA, SI}},
1740{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, {RA, SI}},
1741{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, {RA, SI}},
1742{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, {RA, SI}},
1743{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, {RA, SI}},
1744{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, {RA, SI}},
1745{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, {RA, SI}},
1746{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, {RA, SI}},
1747{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, {RA, SI}},
1748{"twi", OP(3), OP_MASK, PPCCOM, {TO, RA, SI}},
1749{"ti", OP(3), OP_MASK, PWRCOM, {TO, RA, SI}},
1750
1751{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1752{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, {VD, VA, VB}},
1753{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, {VD, VA, VB}},
1754{"vrlb", VX (4, 4), VX_MASK, PPCVEC, {VD, VA, VB}},
1755{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1756{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, {VD, VA, VB}},
1757{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, {VD, VA, VB}},
1758{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}},
1759{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, {VD, VA, VB}},
1760{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}},
1761{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, {VD, VA, VB}},
1762{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1763{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1764{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1765{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1766{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1767{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1768{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1769{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1770{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1771{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1772{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1773{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1774{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1775{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1776{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1777{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1778{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1779{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1780{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1781{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1782{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1783{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1784{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1785{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1786{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1787{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1788{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1789{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1790{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1791{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1792{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1793{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1794{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1795{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, {VD, VA, VB, SHB}},
1796{"ps_sel", A (4, 23,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1797{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
1798{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1799{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
1800{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1801{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1802{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1803{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1804{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1805{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1806{"ps_msub", A (4, 28,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1807{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1808{"ps_madd", A (4, 29,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1809{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1810{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1811{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1812{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1813{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1814{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1815{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, {VD, VA, VB}},
1816{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, {VD, VA, VB}},
1817{"vrlh", VX (4, 68), VX_MASK, PPCVEC, {VD, VA, VB}},
1818{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1819{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, {VD, VA, VB}},
1820{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, {VD, VA, VB}},
1821{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}},
1822{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, {VD, VA, VB}},
1823{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}},
1824{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, {VD, VA, VB}},
1825{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, {FRT, FRB}},
1826{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1827{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, {FRT, FRB}},
1828{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1829{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1830{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1831{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1832{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1833{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1834{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, {VD, VA, VB}},
1835{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, {VD, VA, VB}},
1836{"vrlw", VX (4, 132), VX_MASK, PPCVEC, {VD, VA, VB}},
1837{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1838{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, {VD, VA, VB}},
1839{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, {VD, VA, VB}},
1840{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, {FRT, FRB}},
1841{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, {FRT, FRB}},
1842{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1843{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1844{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1845{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1846{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, {VD, VA, VB}},
1847{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1848{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1849{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1850{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1851{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, {VD, VA, VB}},
1852{"vslb", VX (4, 260), VX_MASK, PPCVEC, {VD, VA, VB}},
1853{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, {VD, VA, VB}},
1854{"vrefp", VX (4, 266), VX_MASK, PPCVEC, {VD, VB}},
1855{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, {VD, VA, VB}},
1856{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, {VD, VA, VB}},
1857{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, {FRT, FRB}},
1858{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1859{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, {FRT, FRB}},
1860{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1861{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1862{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1863{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, {VD, VA, VB}},
1864{"vslh", VX (4, 324), VX_MASK, PPCVEC, {VD, VA, VB}},
1865{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, {VD, VA, VB}},
1866{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, {VD, VB}},
1867{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, {VD, VA, VB}},
1868{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, {VD, VA, VB}},
1869{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1870{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1871{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1872{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1873{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1874{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1875{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, {VD, VA, VB}},
1876{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, {VD, VA, VB}},
1877{"vslw", VX (4, 388), VX_MASK, PPCVEC, {VD, VA, VB}},
1878{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, {VD, VB}},
1879{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, {VD, VA, VB}},
1880{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, {VD, VA, VB}},
1881{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1882{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1883{"vsl", VX (4, 452), VX_MASK, PPCVEC, {VD, VA, VB}},
1884{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1885{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, {VD, VB}},
1886{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, {VD, VA, VB}},
1887{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1888{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1889{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1890{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1891{"evaddw", VX (4, 512), VX_MASK, PPCSPE, {RS, RA, RB}},
1892{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, {VD, VA, VB}},
1893{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, {RS, RB, UIMM}},
1894{"vminub", VX (4, 514), VX_MASK, PPCVEC, {VD, VA, VB}},
1895{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, {RS, RA, RB}},
1896{"evsubw", VX (4, 516), VX_MASK, PPCSPE, {RS, RB, RA}},
1897{"vsrb", VX (4, 516), VX_MASK, PPCVEC, {VD, VA, VB}},
1898{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, {RS, UIMM, RB}},
1899{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, {RS, RB, UIMM}},
1900{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1901{"evabs", VX (4, 520), VX_MASK, PPCSPE, {RS, RA}},
1902{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, {VD, VA, VB}},
1903{"evneg", VX (4, 521), VX_MASK, PPCSPE, {RS, RA}},
1904{"evextsb", VX (4, 522), VX_MASK, PPCSPE, {RS, RA}},
1905{"vrfin", VX (4, 522), VX_MASK, PPCVEC, {VD, VB}},
1906{"evextsh", VX (4, 523), VX_MASK, PPCSPE, {RS, RA}},
1907{"evrndw", VX (4, 524), VX_MASK, PPCSPE, {RS, RA}},
1908{"vspltb", VX (4, 524), VX_MASK, PPCVEC, {VD, VB, UIMM}},
1909{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, {RS, RA}},
1910{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, {RS, RA}},
1911{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, {VD, VB}},
1912{"brinc", VX (4, 527), VX_MASK, PPCSPE, {RS, RA, RB}},
1913{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, {FRT, FRB}},
1914{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, {FRT, FRB}},
1915{"evand", VX (4, 529), VX_MASK, PPCSPE, {RS, RA, RB}},
1916{"evandc", VX (4, 530), VX_MASK, PPCSPE, {RS, RA, RB}},
1917{"evxor", VX (4, 534), VX_MASK, PPCSPE, {RS, RA, RB}},
1918{"evmr", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, BBA}},
1919{"evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}},
1920{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}},
1921{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}},
1922{"eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}},
1923{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}},
1924{"evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}},
1925{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, {RS, RA, RB}},
1926{"evsrws", VX (4, 545), VX_MASK, PPCSPE, {RS, RA, RB}},
1927{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1928{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1929{"evslw", VX (4, 548), VX_MASK, PPCSPE, {RS, RA, RB}},
1930{"evslwi", VX (4, 550), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1931{"evrlw", VX (4, 552), VX_MASK, PPCSPE, {RS, RA, RB}},
1932{"evsplati", VX (4, 553), VX_MASK, PPCSPE, {RS, SIMM}},
1933{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1934{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, {RS, SIMM}},
1935{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, {RS, RA, RB}},
1936{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, {RS, RA, RB}},
1937{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, {RS, RA, RB}},
1938{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, {RS, RA, RB}},
1939{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1940{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1941{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1942{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1943{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1944{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}},
1945{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}},
1946{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}},
1947{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1948{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, {VD, VA, VB}},
1949{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}},
1950{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}},
1951{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}},
1952{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}},
1953{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}},
1954{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}},
1955{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}},
1956{"vminuw", VX (4, 642), VX_MASK, PPCVEC, {VD, VA, VB}},
1957{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, {RS, RA}},
1958{"vsrw", VX (4, 644), VX_MASK, PPCVEC, {VD, VA, VB}},
1959{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, {RS, RA}},
1960{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, {RS, RA}},
1961{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1962{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, {RS, RA, RB}},
1963{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, {RS, RA, RB}},
1964{"vrfip", VX (4, 650), VX_MASK, PPCVEC, {VD, VB}},
1965{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1966{"vspltw", VX (4, 652), VX_MASK, PPCVEC, {VD, VB, UIMM}},
1967{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1968{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1969{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, {VD, VB}},
1970{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, {RS, RB}},
1971{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, {RS, RB}},
1972{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, {RS, RB}},
1973{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, {RS, RB}},
1974{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, {RS, RB}},
1975{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, {RS, RB}},
1976{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}},
1977{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}},
1978{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}},
1979{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}},
1980{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1981{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1982{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1983{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}},
1984{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}},
1985{"efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}},
1986{"vsr", VX (4, 708), VX_MASK, PPCVEC, {VD, VA, VB}},
1987{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, {RS, RA}},
1988{"efsneg", VX (4, 710), VX_MASK, PPCEFS, {RS, RA}},
1989{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1990{"efsmul", VX (4, 712), VX_MASK, PPCEFS, {RS, RA, RB}},
1991{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, {RS, RA, RB}},
1992{"vrfim", VX (4, 714), VX_MASK, PPCVEC, {VD, VB}},
1993{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, {CRFD, RA, RB}},
1994{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, {CRFD, RA, RB}},
1995{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, {CRFD, RA, RB}},
1996{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, {VD, VB}},
1997{"efscfd", VX (4, 719), VX_MASK, PPCEFS, {RS, RB}},
1998{"efscfui", VX (4, 720), VX_MASK, PPCEFS, {RS, RB}},
1999{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, {RS, RB}},
2000{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, {RS, RB}},
2001{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, {RS, RB}},
2002{"efsctui", VX (4, 724), VX_MASK, PPCEFS, {RS, RB}},
2003{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, {RS, RB}},
2004{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}},
2005{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}},
2006{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}},
2007{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}},
2008{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2009{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2010{"efststeq", VX (4, 734), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2011{"efdadd", VX (4, 736), VX_MASK, PPCEFS, {RS, RA, RB}},
2012{"efdsub", VX (4, 737), VX_MASK, PPCEFS, {RS, RA, RB}},
2013{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, {RS, RB}},
2014{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, {RS, RB}},
2015{"efdabs", VX (4, 740), VX_MASK, PPCEFS, {RS, RA}},
2016{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, {RS, RA}},
2017{"efdneg", VX (4, 742), VX_MASK, PPCEFS, {RS, RA}},
2018{"efdmul", VX (4, 744), VX_MASK, PPCEFS, {RS, RA, RB}},
2019{"efddiv", VX (4, 745), VX_MASK, PPCEFS, {RS, RA, RB}},
2020{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, {RS, RB}},
2021{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, {RS, RB}},
2022{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2023{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2024{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2025{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, {RS, RB}},
2026{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, {RS, RB}},
2027{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, {RS, RB}},
2028{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, {RS, RB}},
2029{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, {RS, RB}},
2030{"efdctui", VX (4, 756), VX_MASK, PPCEFS, {RS, RB}},
2031{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, {RS, RB}},
2032{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}},
2033{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}},
2034{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}},
2035{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}},
2036{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2037{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2038{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2039{"evlddx", VX (4, 768), VX_MASK, PPCSPE, {RS, RA, RB}},
2040{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, {VD, VA, VB}},
2041{"evldd", VX (4, 769), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2042{"evldwx", VX (4, 770), VX_MASK, PPCSPE, {RS, RA, RB}},
2043{"vminsb", VX (4, 770), VX_MASK, PPCVEC, {VD, VA, VB}},
2044{"evldw", VX (4, 771), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2045{"evldhx", VX (4, 772), VX_MASK, PPCSPE, {RS, RA, RB}},
2046{"vsrab", VX (4, 772), VX_MASK, PPCVEC, {VD, VA, VB}},
2047{"evldh", VX (4, 773), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2048{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2049{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, {RS, RA, RB}},
2050{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, {VD, VA, VB}},
2051{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
2052{"vcfux", VX (4, 778), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2053{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, {RS, RA, RB}},
2054{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, {VD, SIMM}},
2055{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
2056{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, {RS, RA, RB}},
2057{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, {VD, VA, VB}},
2058{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
2059{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2060{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, {RS, RA, RB}},
2061{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2062{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2063{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, {RS, RA, RB}},
2064{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2065{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, {RS, RA, RB}},
2066{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2067{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2068{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, {RS, RA, RB}},
2069{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2070{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2071{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, {RS, RA, RB}},
2072{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2073{"evstddx", VX (4, 800), VX_MASK, PPCSPE, {RS, RA, RB}},
2074{"evstdd", VX (4, 801), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2075{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, {RS, RA, RB}},
2076{"evstdw", VX (4, 803), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2077{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, {RS, RA, RB}},
2078{"evstdh", VX (4, 805), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2079{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, {RS, RA, RB}},
2080{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2081{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, {RS, RA, RB}},
2082{"evstwho", VX (4, 821), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2083{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, {RS, RA, RB}},
2084{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2085{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, {RS, RA, RB}},
2086{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2087{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, {VD, VA, VB}},
2088{"vminsh", VX (4, 834), VX_MASK, PPCVEC, {VD, VA, VB}},
2089{"vsrah", VX (4, 836), VX_MASK, PPCVEC, {VD, VA, VB}},
2090{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2091{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, {VD, VA, VB}},
2092{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2093{"vspltish", VX (4, 844), VX_MASK, PPCVEC, {VD, SIMM}},
2094{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, {VD, VB}},
2095{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2096{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2097{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2098{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2099{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2100{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2101{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, {VD, VA, VB}},
2102{"vminsw", VX (4, 898), VX_MASK, PPCVEC, {VD, VA, VB}},
2103{"vsraw", VX (4, 900), VX_MASK, PPCVEC, {VD, VA, VB}},
2104{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2105{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2106{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, {VD, SIMM}},
2107{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2108{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2109{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2110{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2111{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, {VD, VB}},
2112{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2113{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2114{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2115{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2116{"vsububm", VX (4,1024), VX_MASK, PPCVEC, {VD, VA, VB}},
2117{"vavgub", VX (4,1026), VX_MASK, PPCVEC, {VD, VA, VB}},
2118{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}},
2119{"vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}},
2120{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2121{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}},
2122{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}},
2123{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}},
2124{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, {VD, VA, VB}},
2125{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, {RS, RA, RB}},
2126{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, {RS, RA, RB}},
2127{"vslo", VX (4,1036), VX_MASK, PPCVEC, {VD, VA, VB}},
2128{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, {RS, RA, RB}},
2129{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, {RS, RA, RB}},
2130{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2131{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2132{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2133{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2134{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, {RS, RA, RB}},
2135{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, {RS, RA, RB}},
2136{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, {RS, RA, RB}},
2137{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, {RS, RA, RB}},
2138{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, {RS, RA, RB}},
2139{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, {RS, RA, RB}},
2140{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, {RS, RA, RB}},
2141{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, {RS, RA, RB}},
2142{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, {VD, VA, VB}},
2143{"vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}},
2144{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}},
2145{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2146{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}},
2147{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}},
2148{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}},
2149{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, {RS, RA, RB}},
2150{"vsro", VX (4,1100), VX_MASK, PPCVEC, {VD, VA, VB}},
2151{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, {RS, RA, RB}},
2152{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, {RS, RA, RB}},
2153{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, {RS, RA, RB}},
2154{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2155{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, {RS, RA, RB}},
2156{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2157{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, {RS, RA, RB}},
2158{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, {RS, RA, RB}},
2159{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2160{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2161{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2162{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2163{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, {RS, RA, RB}},
2164{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, {RS, RA, RB}},
2165{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, {RS, RA, RB}},
2166{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, {RS, RA, RB}},
2167{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, {RS, RA, RB}},
2168{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, {RS, RA, RB}},
2169{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, {RS, RA, RB}},
2170{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, {RS, RA, RB}},
2171{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, {RS, RA, RB}},
2172{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, {VD, VA, VB}},
2173{"vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}},
2174{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}},
2175{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2176{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2177{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2178{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2179{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2180{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, {RS, RA}},
2181{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, {RS, RA}},
2182{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, {RS, RA}},
2183{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, {RS, RA}},
2184{"evmra", VX (4,1220), VX_MASK, PPCSPE, {RS, RA}},
2185{"vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}},
2186{"evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}},
2187{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2188{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}},
2189{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}},
2190{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}},
2191{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, {RS, RA}},
2192{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, {RS, RA}},
2193{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2194{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2195{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2196{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2197{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2198{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2199{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, {RS, RA, RB}},
2200{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, {RS, RA, RB}},
2201{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, {VD, VA, VB}},
2202{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, {RS, RA, RB}},
2203{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}},
2204{"vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}},
2205{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}},
2206{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}},
2207{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}},
2208{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}},
2209{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, {RS, RA, RB}},
2210{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, {RS, RA, RB}},
2211{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, {RS, RA, RB}},
2212{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, {RS, RA, RB}},
2213{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2214{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2215{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, {RS, RA, RB}},
2216{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, {RS, RA, RB}},
2217{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, {RS, RA, RB}},
2218{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, {RS, RA, RB}},
2219{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, {RS, RA, RB}},
2220{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, {RS, RA, RB}},
2221{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}},
2222{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}},
2223{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}},
2224{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}},
2225{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}},
2226{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}},
2227{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2228{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, {RS, RA, RB}},
2229{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2230{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, {RS, RA, RB}},
2231{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, {RS, RA, RB}},
2232{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2233{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2234{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, {RS, RA, RB}},
2235{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, {VD, VA, VB}},
2236{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, {RS, RA, RB}},
2237{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, {VD, VA, VB}},
2238{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}},
2239{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}},
2240{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}},
2241{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}},
2242{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}},
2243{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}},
2244{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, {RS, RA, RB}},
2245{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, {RS, RA, RB}},
2246{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, {RS, RA, RB}},
2247{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, {RS, RA, RB}},
2248{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2249{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2250{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, {RS, RA, RB}},
2251{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, {RS, RA, RB}},
2252{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, {RS, RA, RB}},
2253{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, {RS, RA, RB}},
2254{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, {RS, RA, RB}},
2255{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, {RS, RA, RB}},
2256{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}},
2257{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}},
2258{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2259{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}},
2260{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}},
2261{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}},
2262{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2263{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}},
2264{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2265{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, {RS, RA, RB}},
2266{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, {RS, RA, RB}},
2267{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2268{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2269{"vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}},
2270{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}},
2271{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2272{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}},
2273{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}},
2274{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}},
2275{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2276{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}},
2277{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}},
2278{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2279{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}},
2280{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2281{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}},
2282{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2283{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}},
2284{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2285{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2286{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}},
2287{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2288{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2289{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2290{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2291{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2292{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}},
2293{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2294{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}},
2295{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2296{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2297{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2298{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2299{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2300{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2301{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2302{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}},
2303
2304{"mulli", OP(7), OP_MASK, PPCCOM, {RT, RA, SI}},
2305{"muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}},
2306
2307{"subfic", OP(8), OP_MASK, PPCCOM, {RT, RA, SI}},
2308{"sfi", OP(8), OP_MASK, PWRCOM, {RT, RA, SI}},
2309
2310{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}},
2311
2312{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}},
2313{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}},
2314{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}},
2315{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}},
2316
2317{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}},
2318{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}},
2319{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}},
2320{"cmpli", OP(10), OP_MASK, PWRCOM, {BF, RA, UI}},
2321
2322{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, {OBF, RA, SI}},
2323{"cmpdi", OPL(11,1), OPL_MASK, PPC64, {OBF, RA, SI}},
2324{"cmpi", OP(11), OP_MASK, PPC, {BF, L, RA, SI}},
2325{"cmpi", OP(11), OP_MASK, PWRCOM, {BF, RA, SI}},
2326
2327{"addic", OP(12), OP_MASK, PPCCOM, {RT, RA, SI}},
2328{"ai", OP(12), OP_MASK, PWRCOM, {RT, RA, SI}},
2329{"subic", OP(12), OP_MASK, PPCCOM, {RT, RA, NSI}},
2330
2331{"addic.", OP(13), OP_MASK, PPCCOM, {RT, RA, SI}},
2332{"ai.", OP(13), OP_MASK, PWRCOM, {RT, RA, SI}},
2333{"subic.", OP(13), OP_MASK, PPCCOM, {RT, RA, NSI}},
2334
2335{"li", OP(14), DRA_MASK, PPCCOM, {RT, SI}},
2336{"lil", OP(14), DRA_MASK, PWRCOM, {RT, SI}},
2337{"addi", OP(14), OP_MASK, PPCCOM, {RT, RA0, SI}},
2338{"cal", OP(14), OP_MASK, PWRCOM, {RT, D, RA0}},
2339{"subi", OP(14), OP_MASK, PPCCOM, {RT, RA0, NSI}},
2340{"la", OP(14), OP_MASK, PPCCOM, {RT, D, RA0}},
2341
2342{"lis", OP(15), DRA_MASK, PPCCOM, {RT, SISIGNOPT}},
2343{"liu", OP(15), DRA_MASK, PWRCOM, {RT, SISIGNOPT}},
2344{"addis", OP(15), OP_MASK, PPCCOM, {RT, RA0, SISIGNOPT}},
2345{"cau", OP(15), OP_MASK, PWRCOM, {RT, RA0, SISIGNOPT}},
2346{"subis", OP(15), OP_MASK, PPCCOM, {RT, RA0, NSI}},
2347
2348{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}},
2349{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}},
2350{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BD}},
2351{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, {BD}},
2352{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}},
2353{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}},
2354{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BD}},
2355{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, {BD}},
2356{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}},
2357{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}},
2358{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDA}},
2359{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, {BDA}},
2360{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}},
2361{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}},
2362{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDA}},
2363{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, {BDA}},
2364{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}},
2365{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}},
2366{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, {BD}},
2367{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}},
2368{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}},
2369{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, {BD}},
2370{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}},
2371{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}},
2372{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, {BDA}},
2373{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}},
2374{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}},
2375{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, {BDA}},
2376
2377{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2378{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2379{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2380{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2381{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2382{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2383{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2384{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2385{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2386{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2387{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2388{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2389{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2390{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2391{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2392{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2393{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2394{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2395{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2396{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2397{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2398{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2399{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2400{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2401{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2402{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2403{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2404{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2405{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2406{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2407{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2408{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2409{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2410{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2411{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2412{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2413{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2414{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2415{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2416{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2417{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2418{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2419{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2420{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2421{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2422{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2423{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2424{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2425{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2426{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2427{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}},
2428{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2429{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2430{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}},
2431{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2432{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2433{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2434{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2435{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2436{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2437{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2438{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2439{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}},
2440{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2441{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2442{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}},
2443{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2444{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2445{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
2446{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2447{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2448{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}},
2449{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2450{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2451{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2452{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2453{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2454{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2455{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2456{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2457{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2458{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2459{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2460{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2461
2462{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2463{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2464{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2465{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2466{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2467{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2468{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2469{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2470{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2471{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2472{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2473{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2474{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2475{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2476{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2477{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2478{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2479{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2480{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2481{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2482{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2483{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2484{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2485{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2486{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2487{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2488{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}},
2489{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2490{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2491{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}},
2492{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2493{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2494{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2495{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2496{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2497{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2498{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2499{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2500{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}},
2501{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2502{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2503{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}},
2504{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2505{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2506{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
2507{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2508{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2509{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}},
2510{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2511{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2512{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2513{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2514{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2515{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2516{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2517{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2518{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2519{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2520{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2521{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2522
2523{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2524{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2525{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2526{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2527{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2528{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2529{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2530{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2531{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2532{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2533{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2534{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2535{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2536{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2537{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2538{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2539{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2540{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2541{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2542{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2543{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2544{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2545{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2546{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2547
2548{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}},
2549{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}},
2550{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BD}},
2551{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, {BI, BD}},
2552{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}},
2553{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}},
2554{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BD}},
2555{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, {BI, BD}},
2556{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2557{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2558{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}},
2559{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}},
2560{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2561{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2562{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}},
2563{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}},
2564
2565{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2566{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2567{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2568{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2569{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2570{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2571{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2572{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2573{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2574{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2575{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2576{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2577{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2578{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2579{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2580{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2581{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2582{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2583{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2584{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2585{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2586{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2587{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2588{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2589
2590{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}},
2591{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}},
2592{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BD}},
2593{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, {BI, BD}},
2594{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}},
2595{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}},
2596{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BD}},
2597{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, {BI, BD}},
2598{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2599{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2600{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}},
2601{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}},
2602{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2603{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2604{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}},
2605{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}},
2606
2607{"bc-", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDM}},
2608{"bc+", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDP}},
2609{"bc", B(16,0,0), B_MASK, COM, {BO, BI, BD}},
2610{"bcl-", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDM}},
2611{"bcl+", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDP}},
2612{"bcl", B(16,0,1), B_MASK, COM, {BO, BI, BD}},
2613{"bca-", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDMA}},
2614{"bca+", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDPA}},
2615{"bca", B(16,1,0), B_MASK, COM, {BO, BI, BDA}},
2616{"bcla-", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDMA}},
2617{"bcla+", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDPA}},
2618{"bcla", B(16,1,1), B_MASK, COM, {BO, BI, BDA}},
2619
2620{"svc", SC(17,0,0), SC_MASK, POWER, {SVC_LEV, FL1, FL2}},
2621{"svcl", SC(17,0,1), SC_MASK, POWER, {SVC_LEV, FL1, FL2}},
2622{"sc", SC(17,1,0), SC_MASK, PPC, {LEV}},
2623{"svca", SC(17,1,0), SC_MASK, PWRCOM, {SV}},
2624{"svcla", SC(17,1,1), SC_MASK, POWER, {SV}},
2625
2626{"b", B(18,0,0), B_MASK, COM, {LI}},
2627{"bl", B(18,0,1), B_MASK, COM, {LI}},
2628{"ba", B(18,1,0), B_MASK, COM, {LIA}},
2629{"bla", B(18,1,1), B_MASK, COM, {LIA}},
2630
2631{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
2632
2633{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
2634{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2635{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
2636{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2637{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2638{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2639{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
2640{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2641{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
2642{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2643{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2644{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2645{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
2646{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, {0}},
2647{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
2648{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, {0}},
2649{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2650{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2651{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2652{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2653{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2654{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2655{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2656{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2657
2658{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2659{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2660{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2661{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2662{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2663{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2664{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2665{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2666{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2667{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2668{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2669{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2670{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2671{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2672{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2673{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2674{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2675{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2676{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2677{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2678{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2679{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2680{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2681{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2682{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2683{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2684{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2685{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2686{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2687{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2688{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2689{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2690{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2691{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2692{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2693{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2694{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2695{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2696{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2697{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2698{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2699{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2700{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2701{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2702{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2703{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2704{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2705{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2706{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2707{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2708{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2709{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2710{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2711{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2712{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2713{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2714{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2715{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2716{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2717{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2718{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2719{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2720{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2721{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2722{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2723{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2724{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2725{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2726{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2727{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2728{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2729{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2730{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2731{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2732{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2733{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2734{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2735{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2736{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2737{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2738{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2739{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2740{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2741{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2742{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2743{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2744{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2745{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2746{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2747{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2748{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2749{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2750{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2751{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2752{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2753{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2754{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2755{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2756{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2757{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2758{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2759{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2760{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2761{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2762{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2763{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2764{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2765{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2766{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2767{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2768{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2769{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2770{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2771{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2772{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2773{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2774{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2775{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2776{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2777{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2778{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2779{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2780{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2781{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2782{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2783{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2784{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2785{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2786{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2787{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2788{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2789{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2790{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2791{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2792{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2793{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2794{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2795{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2796{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2797{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2798
2799{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2800{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2801{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2802{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2803{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2804{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2805{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2806{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2807{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2808{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2809{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2810{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2811{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2812{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2813{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, {BI}},
2814{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2815{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2816{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, {BI}},
2817{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2818{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2819{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, {BI}},
2820{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, {BI}},
2821{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, {BI}},
2822{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, {BI}},
2823{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2824{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2825{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2826{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2827{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2828{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2829{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2830{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2831{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2832{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2833{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2834{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2835{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2836{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2837{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, {BI}},
2838{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2839{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2840{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, {BI}},
2841{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2842{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2843{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, {BI}},
2844{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, {BI}},
2845{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, {BI}},
2846{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, {BI}},
2847
2848{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
2849{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
2850{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
2851{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
2852{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, {BO, BI, BH}},
2853{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, {BO, BI}},
2854{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
2855{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}},
2856
2857{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}},
2858{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}},
2859
2860{"rfid", XL(19,18), 0xffffffff, PPC64, {0}},
2861
2862{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}},
2863{"crnor", XL(19,33), XL_MASK, COM, {BT, BA, BB}},
2864{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}},
2865
2866{"rfi", XL(19,50), 0xffffffff, COM, {0}},
2867{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE, {0}},
2868
2869{"rfsvc", XL(19,82), 0xffffffff, POWER, {0}},
2870
2871{"crandc", XL(19,129), XL_MASK, COM, {BT, BA, BB}},
2872
2873{"isync", XL(19,150), 0xffffffff, PPCCOM, {0}},
2874{"ics", XL(19,150), 0xffffffff, PWRCOM, {0}},
2875
2876{"crclr", XL(19,193), XL_MASK, PPCCOM, {BT, BAT, BBA}},
2877{"crxor", XL(19,193), XL_MASK, COM, {BT, BA, BB}},
2878
2879{"crnand", XL(19,225), XL_MASK, COM, {BT, BA, BB}},
2880
2881{"crand", XL(19,257), XL_MASK, COM, {BT, BA, BB}},
2882
2883{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, {0}},
2884
2885{"crset", XL(19,289), XL_MASK, PPCCOM, {BT, BAT, BBA}},
2886{"creqv", XL(19,289), XL_MASK, COM, {BT, BA, BB}},
2887
2888{"doze", XL(19,402), 0xffffffff, POWER6, {0}},
2889
2890{"crorc", XL(19,417), XL_MASK, COM, {BT, BA, BB}},
2891
2892{"nap", XL(19,434), 0xffffffff, POWER6, {0}},
2893
2894{"crmove", XL(19,449), XL_MASK, PPCCOM, {BT, BA, BBA}},
2895{"cror", XL(19,449), XL_MASK, COM, {BT, BA, BB}},
2896
2897{"sleep", XL(19,466), 0xffffffff, POWER6, {0}},
2898{"rvwinkle", XL(19,498), 0xffffffff, POWER6, {0}},
2899
2900{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, {0}},
2901{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, {0}},
2902
2903{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2904{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2905{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2906{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2907{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2908{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2909{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2910{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2911{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2912{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2913{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2914{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2915{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2916{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2917{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2918{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2919{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2920{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2921{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2922{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2923{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2924{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2925{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2926{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2927{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2928{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2929{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2930{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2931{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2932{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2933{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2934{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2935{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2936{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2937{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2938{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2939{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2940{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2941{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2942{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2943{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2944{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2945{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2946{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2947{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2948{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2949{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2950{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2951{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2952{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2953{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2954{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2955{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2956{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2957{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2958{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2959{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2960{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2961{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2962{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2963{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2964{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2965{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2966{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2967{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2968{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2969{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2970{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2971{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2972{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2973{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2974{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2975{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2976{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2977{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2978{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2979{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2980{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2981{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2982{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2983{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2984{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2985{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2986{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2987{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2988{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2989{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2990{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2991{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2992{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2993{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2994{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2995{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2996{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2997{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2998{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2999{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3000{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3001{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3002{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3003{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3004{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3005{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3006{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3007{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3008{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3009{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3010{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3011{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3012{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3013{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3014{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3015{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3016{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3017{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3018{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3019{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3020{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3021{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3022{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3023
3024{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, {BI}},
3025{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3026{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, {BI}},
3027{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3028{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3029{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3030{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, {BI}},
3031{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, {BI}},
3032{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, {BI}},
3033{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, {BI}},
3034{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, {BI}},
3035{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3036{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, {BI}},
3037{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3038{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3039{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3040{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, {BI}},
3041{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, {BI}},
3042{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, {BI}},
3043{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, {BI}},
3044
3045{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
3046{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
3047{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
3048{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
3049{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, {BO, BI, BH}},
3050{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, {BO, BI}},
3051{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
3052{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}},
3053
3054{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}},
3055{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}},
3056
3057{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3058{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3059
3060{"rlwimi.", M(20,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3061{"rlimi.", M(20,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3062
3063{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, {RA, RS, SH}},
3064{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, {RA, RS, MB}},
3065{"rlwinm", M(21,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3066{"rlinm", M(21,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3067{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, {RA, RS, SH}},
3068{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, {RA, RS, MB}},
3069{"rlwinm.", M(21,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3070{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3071
3072{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}},
3073{"be", B(22,0,0), B_MASK, BOOKE64, {LI}},
3074{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}},
3075{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}},
3076{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}},
3077{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}},
3078
3079{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}},
3080{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
3081{"rlnm", M(23,0), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}},
3082{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, {RA, RS, RB}},
3083{"rlwnm.", M(23,1), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
3084{"rlnm.", M(23,1), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}},
3085
3086{"nop", OP(24), 0xffffffff, PPCCOM, {0}},
3087{"ori", OP(24), OP_MASK, PPCCOM, {RA, RS, UI}},
3088{"oril", OP(24), OP_MASK, PWRCOM, {RA, RS, UI}},
3089
3090{"oris", OP(25), OP_MASK, PPCCOM, {RA, RS, UI}},
3091{"oriu", OP(25), OP_MASK, PWRCOM, {RA, RS, UI}},
3092
3093{"xori", OP(26), OP_MASK, PPCCOM, {RA, RS, UI}},
3094{"xoril", OP(26), OP_MASK, PWRCOM, {RA, RS, UI}},
3095
3096{"xoris", OP(27), OP_MASK, PPCCOM, {RA, RS, UI}},
3097{"xoriu", OP(27), OP_MASK, PWRCOM, {RA, RS, UI}},
3098
3099{"andi.", OP(28), OP_MASK, PPCCOM, {RA, RS, UI}},
3100{"andil.", OP(28), OP_MASK, PWRCOM, {RA, RS, UI}},
3101
3102{"andis.", OP(29), OP_MASK, PPCCOM, {RA, RS, UI}},
3103{"andiu.", OP(29), OP_MASK, PWRCOM, {RA, RS, UI}},
3104
3105{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, {RA, RS, SH6}},
3106{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, {RA, RS, MB6}},
3107{"rldicl", MD(30,0,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3108{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, {RA, RS, SH6}},
3109{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, {RA, RS, MB6}},
3110{"rldicl.", MD(30,0,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3111
3112{"rldicr", MD(30,1,0), MD_MASK, PPC64, {RA, RS, SH6, ME6}},
3113{"rldicr.", MD(30,1,1), MD_MASK, PPC64, {RA, RS, SH6, ME6}},
3114
3115{"rldic", MD(30,2,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3116{"rldic.", MD(30,2,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3117
3118{"rldimi", MD(30,3,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3119{"rldimi.", MD(30,3,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3120
3121{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, {RA, RS, RB}},
3122{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, {RA, RS, RB, MB6}},
3123{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, {RA, RS, RB}},
3124{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, {RA, RS, RB, MB6}},
3125
3126{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, {RA, RS, RB, ME6}},
3127{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, {RA, RS, RB, ME6}},
3128
3129{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
3130{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, {OBF, RA, RB}},
3131{"cmp", X(31,0), XCMP_MASK, PPC, {BF, L, RA, RB}},
3132{"cmp", X(31,0), XCMPL_MASK, PWRCOM, {BF, RA, RB}},
3133
3134{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, {RA, RB}},
3135{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, {RA, RB}},
3136{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, {RA, RB}},
3137{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, {RA, RB}},
3138{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, {RA, RB}},
3139{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, {RA, RB}},
3140{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, {RA, RB}},
3141{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, {RA, RB}},
3142{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, {RA, RB}},
3143{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, {RA, RB}},
3144{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, {RA, RB}},
3145{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, {RA, RB}},
3146{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, {RA, RB}},
3147{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, {RA, RB}},
3148{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, {RA, RB}},
3149{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, {RA, RB}},
3150{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, {RA, RB}},
3151{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, {RA, RB}},
3152{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, {RA, RB}},
3153{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, {RA, RB}},
3154{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, {RA, RB}},
3155{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, {RA, RB}},
3156{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, {RA, RB}},
3157{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, {RA, RB}},
3158{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, {RA, RB}},
3159{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, {RA, RB}},
3160{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, {RA, RB}},
3161{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, {RA, RB}},
3162{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, {0}},
3163{"tw", X(31,4), X_MASK, PPCCOM, {TO, RA, RB}},
3164{"t", X(31,4), X_MASK, PWRCOM, {TO, RA, RB}},
3165
3166{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}},
3167{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}},
3168
3169{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3170{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3171{"subc", XO(31,8,0,0), XO_MASK, PPC, {RT, RB, RA}},
3172{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3173{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3174{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RB, RA}},
3175
3176{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3177{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, {RT, RA, RB}},
3178
3179{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3180{"a", XO(31,10,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3181{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3182{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3183
3184{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, {RT, RA, RB}},
3185{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, {RT, RA, RB}},
3186
3187{"isellt", X(31,15), X_MASK, PPCISEL, {RT, RA, RB}},
3188
3189{"mfcr", XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}},
3190{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}},
3191{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, {RT, FXM}},
3192
3193{"lwarx", X(31,20), XEH_MASK, PPC, {RT, RA0, RB, EH}},
3194
3195{"ldx", X(31,21), X_MASK, PPC64, {RT, RA0, RB}},
3196
3197{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, {CT, RA, RB}},
3198
3199{"lwzx", X(31,23), X_MASK, PPCCOM, {RT, RA0, RB}},
3200{"lx", X(31,23), X_MASK, PWRCOM, {RT, RA, RB}},
3201
3202{"slw", XRC(31,24,0), X_MASK, PPCCOM, {RA, RS, RB}},
3203{"sl", XRC(31,24,0), X_MASK, PWRCOM, {RA, RS, RB}},
3204{"slw.", XRC(31,24,1), X_MASK, PPCCOM, {RA, RS, RB}},
3205{"sl.", XRC(31,24,1), X_MASK, PWRCOM, {RA, RS, RB}},
3206
3207{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, {RA, RS}},
3208{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, {RA, RS}},
3209{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, {RA, RS}},
3210{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, {RA, RS}},
3211
3212{"sld", XRC(31,27,0), X_MASK, PPC64, {RA, RS, RB}},
3213{"sld.", XRC(31,27,1), X_MASK, PPC64, {RA, RS, RB}},
3214
3215{"and", XRC(31,28,0), X_MASK, COM, {RA, RS, RB}},
3216{"and.", XRC(31,28,1), X_MASK, COM, {RA, RS, RB}},
3217
3218{"maskg", XRC(31,29,0), X_MASK, M601, {RA, RS, RB}},
3219{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}},
3220
3221{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}},
3222
3223{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}},
3224
3225{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
3226{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, {OBF, RA, RB}},
3227{"cmpl", X(31,32), XCMP_MASK, PPC, {BF, L, RA, RB}},
3228{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, {BF, RA, RB}},
3229
3230{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}},
3231{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}},
3232
3233{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}},
3234
3235{"lvewx", X(31,71), X_MASK, PPCVEC, {VD, RA, RB}},
3236
3237{"iseleq", X(31,79), X_MASK, PPCISEL, {RT, RA, RB}},
3238
3239{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, {RT, RA, RB, CRB}},
3240
3241{"subf", XO(31,40,0,0), XO_MASK, PPC, {RT, RA, RB}},
3242{"sub", XO(31,40,0,0), XO_MASK, PPC, {RT, RB, RA}},
3243{"subf.", XO(31,40,0,1), XO_MASK, PPC, {RT, RA, RB}},
3244{"sub.", XO(31,40,0,1), XO_MASK, PPC, {RT, RB, RA}},
3245
3246{"ldux", X(31,53), X_MASK, PPC64, {RT, RAL, RB}},
3247
3248{"dcbst", X(31,54), XRT_MASK, PPC, {RA, RB}},
3249
3250{"lwzux", X(31,55), X_MASK, PPCCOM, {RT, RAL, RB}},
3251{"lux", X(31,55), X_MASK, PWRCOM, {RT, RA, RB}},
3252
3253{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, {RA, RS}},
3254{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, {RA, RS}},
3255
3256{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}},
3257{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}},
3258
3259{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}},
3260
3261{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}},
3262
3263{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}},
3264{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, {RA, RB}},
3265{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, {RA, RB}},
3266{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, {RA, RB}},
3267{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, {RA, RB}},
3268{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, {RA, RB}},
3269{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, {RA, RB}},
3270{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, {RA, RB}},
3271{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, {RA, RB}},
3272{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, {RA, RB}},
3273{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, {RA, RB}},
3274{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, {RA, RB}},
3275{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, {RA, RB}},
3276{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}},
3277{"td", X(31,68), X_MASK, PPC64, {TO, RA, RB}},
3278
3279{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3280{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}},
3281
3282{"mulhw", XO(31,75,0,0), XO_MASK, PPC, {RT, RA, RB}},
3283{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, {RT, RA, RB}},
3284
3285{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, {RA, RS, RB}},
3286{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, {RA, RS, RB}},
3287
3288{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, {SR, RS}},
3289
3290{"mfmsr", X(31,83), XRARB_MASK, COM, {RT}},
3291
3292{"ldarx", X(31,84), XEH_MASK, PPC64, {RT, RA0, RB, EH}},
3293
3294{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, {RA, RB}},
3295{"dcbf", X(31,86), XLRT_MASK, PPC, {RA, RB, L}},
3296
3297{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}},
3298
3299{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}},
3300
3301{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}},
3302
3303{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
3304
3305{"neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}},
3306{"neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}},
3307
3308{"mul", XO(31,107,0,0), XO_MASK, M601, {RT, RA, RB}},
3309{"mul.", XO(31,107,0,1), XO_MASK, M601, {RT, RA, RB}},
3310
3311{"mtsrdin", X(31,114), XRA_MASK, PPC64, {RS, RB}},
3312
3313{"clf", X(31,118), XTO_MASK, POWER, {RA, RB}},
3314
3315{"lbzux", X(31,119), X_MASK, COM, {RT, RAL, RB}},
3316
3317{"popcntb", X(31,122), XRB_MASK, POWER5, {RA, RS}},
3318
3319{"not", XRC(31,124,0), X_MASK, COM, {RA, RS, RBS}},
3320{"nor", XRC(31,124,0), X_MASK, COM, {RA, RS, RB}},
3321{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}},
3322{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}},
3323
3324{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}},
3325
3326{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}},
3327
3328{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}},
3329
3330{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}},
3331
3332{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}},
3333
3334{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3335{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3336{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3337{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3338
3339{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3340{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3341{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3342{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3343
3344{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}},
3345
3346{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}},
3347{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}},
3348{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, {FXM, RS}},
3349
3350{"mtmsr", X(31,146), XRLARB_MASK, COM, {RS, A_L}},
3351
3352{"stdx", X(31,149), X_MASK, PPC64, {RS, RA0, RB}},
3353
3354{"stwcx.", XRC(31,150,1), X_MASK, PPC, {RS, RA0, RB}},
3355
3356{"stwx", X(31,151), X_MASK, PPCCOM, {RS, RA0, RB}},
3357{"stx", X(31,151), X_MASK, PWRCOM, {RS, RA, RB}},
3358
3359{"slq", XRC(31,152,0), X_MASK, M601, {RA, RS, RB}},
3360{"slq.", XRC(31,152,1), X_MASK, M601, {RA, RS, RB}},
3361
3362{"sle", XRC(31,153,0), X_MASK, M601, {RA, RS, RB}},
3363{"sle.", XRC(31,153,1), X_MASK, M601, {RA, RS, RB}},
3364
3365{"prtyw", X(31,154), XRB_MASK, POWER6, {RA, RS}},
3366
3367{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}},
3368
3369{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}},
3370
3371{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}},
3372
3373{"dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}},
3374
3375{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}},
3376
3377{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}},
3378
3379{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}},
3380
3381{"stdux", X(31,181), X_MASK, PPC64, {RS, RAS, RB}},
3382
3383{"stwux", X(31,183), X_MASK, PPCCOM, {RS, RAS, RB}},
3384{"stux", X(31,183), X_MASK, PWRCOM, {RS, RA0, RB}},
3385
3386{"sliq", XRC(31,184,0), X_MASK, M601, {RA, RS, SH}},
3387{"sliq.", XRC(31,184,1), X_MASK, M601, {RA, RS, SH}},
3388
3389{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}},
252b5132 3390
de866fcc 3391{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}},
252b5132 3392
de866fcc 3393{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}},
252b5132 3394
de866fcc
AM		 3395{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3396{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3397{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3398{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 3399
de866fcc
AM		 3400{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3401{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3402{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3403{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, {RT, RA}},
418c1742 3404
de866fcc 3405{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, {SR, RS}},
418c1742 3406
de866fcc 3407{"stdcx.", XRC(31,214,1), X_MASK, PPC64, {RS, RA0, RB}},
252b5132 3408
de866fcc 3409{"stbx", X(31,215), X_MASK, COM, {RS, RA0, RB}},
252b5132 3410
de866fcc
AM		 3411{"sllq", XRC(31,216,0), X_MASK, M601, {RA, RS, RB}},
3412{"sllq.", XRC(31,216,1), X_MASK, M601, {RA, RS, RB}},
252b5132 3413
de866fcc
AM		 3414{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}},
3415{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}},
252b5132 3416
de866fcc 3417{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}},
252b5132 3418
de866fcc 3419{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}},
7d5b217e 3420
de866fcc 3421{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}},
f509565f 3422
de866fcc
AM		 3423{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3424{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3425{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3426{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 3427
de866fcc
AM		 3428{"mulld", XO(31,233,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3429{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, {RT, RA, RB}},
252b5132 3430
de866fcc
AM		 3431{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3432{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3433{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3434{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 3435
de866fcc
AM		 3436{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3437{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3438{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3439{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 3440
de866fcc
AM		 3441{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}},
3442{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}},
3443{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}},
418c1742 3444
de866fcc 3445{"dcbtst", X(31,246), X_MASK, PPC, {CT, RA, RB}},
418c1742 3446
de866fcc 3447{"stbux", X(31,247), X_MASK, COM, {RS, RAS, RB}},
252b5132 3448
de866fcc
AM		 3449{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}},
3450{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}},
252b5132 3451
de866fcc 3452{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}},
f509565f 3453
de866fcc 3454{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}},
252b5132 3455
de866fcc 3456{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}},
252b5132 3457
de866fcc 3458{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}},
1ed8e1e4 3459
de866fcc
AM		 3460{"doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}},
3461{"doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 3462
de866fcc
AM		 3463{"add", XO(31,266,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3464{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3465{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3466{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
418c1742 3467
de866fcc 3468{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}},
418c1742 3469
de866fcc 3470{"mfapidi", X(31,275), X_MASK, BOOKE, {RT, RA}},
252b5132 3471
de866fcc
AM		 3472{"lscbx", XRC(31,277,0), X_MASK, M601, {RT, RA, RB}},
3473{"lscbx.", XRC(31,277,1), X_MASK, M601, {RT, RA, RB}},
23976049 3474
de866fcc
AM		 3475{"dcbt", X(31,278), X_MASK, PPC, {CT, RA, RB}},
3476
3477{"lhzx", X(31,279), X_MASK, COM, {RT, RA0, RB}},
3478
3479{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}},
3480{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}},
3481
3482{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}},
3483
3484{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}},
3485
3486{"tlbie", X(31,306), XRTLRA_MASK, PPC, {RB, L}},
3487{"tlbi", X(31,306), XRT_MASK, POWER, {RA0, RB}},
3488
3489{"eciwx", X(31,310), X_MASK, PPC, {RT, RA, RB}},
3490
3491{"lhzux", X(31,311), X_MASK, COM, {RT, RAL, RB}},
3492
3493{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}},
3494{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}},
3495
3496{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}},
3497
3498{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}},
3499{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, {RT}},
3500{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, {RT}},
3501{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, {RT}},
3502{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, {RT}},
3503{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, {RT}},
3504{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, {RT}},
3505{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, {RT}},
3506{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, {RT}},
3507{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, {RT}},
3508{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, {RT}},
3509{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, {RT}},
3510{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, {RT}},
3511{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, {RT}},
3512{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, {RT}},
3513{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, {RT}},
3514{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, {RT}},
3515{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, {RT}},
3516{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, {RT}},
3517{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, {RT}},
3518{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, {RT}},
3519{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, {RT}},
3520{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, {RT}},
3521{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, {RT}},
3522{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, {RT}},
3523{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, {RT}},
3524{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, {RT}},
3525{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, {RT}},
3526{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, {RT}},
3527{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, {RT}},
3528{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, {RT}},
3529{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, {RT}},
3530{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, {RT}},
3531{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, {RT}},
3532{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, {RT, SPR}},
3533
3534{"div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}},
3535{"div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}},
3536
3537{"mfpmr", X(31,334), X_MASK, PPCPMR, {RT, PMR}},
3538
3539{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}},
3540{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}},
3541{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, {RT}},
3542{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, {RT}},
3543{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, {RT}},
3544{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, {RT}},
3545{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, {RT}},
3546{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, {RT}},
3547{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, {RT}},
3548{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, {RT}},
3549{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, {RT}},
3550{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, {RT}},
3551{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, {RT}},
3552{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, {RT}},
3553{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, {RT}},
3554{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, {RT}},
3555{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, {RT}},
3556{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, {RT}},
3557{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, {RT}},
3558{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, {RT}},
3559{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, {RT}},
3560{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, {RT}},
3561{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, {RT}},
3562{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, {RT}},
3563{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, {RT}},
3564{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, {RT}},
3565{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, {RT}},
3566{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, {RT}},
3567{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, {RT}},
3568{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, {RT}},
3569{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, {RT}},
3570{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, {RT}},
3571{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, {RT}},
3572{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, {RT}},
3573{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, {RT}},
3574{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, {RT}},
3575{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, {RT}},
3576{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, {RT}},
3577{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, {RT}},
3578{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, {RT}},
3579{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, {RT, SPRG}},
3580{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}},
3581{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}},
3582{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}},
3583{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}},
3584{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}},
3585{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}},
3586{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, {RT}},
3587{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, {RT}},
3588{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, {RT}},
3589{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, {RT}},
3590{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, {RT}},
3591{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, {RT}},
3592{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, {RT}},
3593{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, {RT}},
3594{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, {RT}},
3595{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, {RT}},
3596{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, {RT}},
3597{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, {RT}},
3598{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, {RT}},
3599{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, {RT}},
3600{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, {RT}},
3601{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, {RT}},
3602{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, {RT}},
3603{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, {RT}},
3604{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, {RT}},
3605{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, {RT}},
3606{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, {RT}},
3607{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, {RT}},
3608{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, {RT}},
3609{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, {RT}},
3610{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, {RT}},
3611{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, {RT}},
3612{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, {RT}},
3613{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, {RT}},
3614{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, {RT}},
3615{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, {RT}},
3616{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, {RT}},
3617{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, {RT}},
3618{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, {RT}},
3619{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, {RT}},
3620{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, {RT}},
3621{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, {RT}},
3622{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, {RT}},
3623{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, {RT}},
3624{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, {RT}},
3625{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, {RT}},
3626{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, {RT}},
3627{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, {RT}},
3628{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, {RT}},
3629{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3630{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, {RT}},
3631{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3632{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, {RT}},
3633{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, {RT}},
3634{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3635{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3636{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, {RT}},
3637{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, {RT}},
3638{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, {RT}},
3639{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, {RT}},
3640{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, {RT}},
3641{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, {RT}},
3642{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}},
3643{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, {RT}},
3644{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, {RT}},
3645{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, {RT}},
3646{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, {RT}},
3647{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, {RT}},
3648{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, {RT}},
3649{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, {RT}},
3650{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, {RT}},
3651{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, {RT}},
3652{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, {RT}},
3653{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, {RT}},
3654{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, {RT}},
3655{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, {RT}},
3656{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, {RT}},
3657{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, {RT}},
3658{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, {RT}},
3659{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, {RT}},
3660{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, {RT}},
3661{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, {RT}},
3662{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, {RT}},
3663{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, {RT}},
3664{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, {RT}},
3665{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, {RT}},
3666{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, {RT}},
3667{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, {RT}},
3668{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, {RT}},
3669{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, {RT}},
3670{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, {RT}},
3671{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, {RT}},
3672{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, {RT}},
3673{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, {RT}},
3674{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, {RT}},
3675{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, {RT}},
3676{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, {RT}},
3677{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, {RT}},
3678{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, {RT}},
3679{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, {RT}},
3680{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, {RT}},
3681{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, {RT}},
3682{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, {RT}},
3683{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, {RT}},
3684{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, {RT}},
3685{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, {RT}},
3686{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, {RT}},
3687{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, {RT}},
3688{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, {RT}},
3689{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, {RT}},
3690{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, {RT}},
3691{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, {RT}},
3692{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, {RT}},
3693{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, {RT}},
3694{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, {RT}},
3695{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, {RT}},
3696{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, {RT}},
3697{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, {RT}},
3698{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, {RT}},
3699{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, {RT}},
3700{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, {RT}},
3701{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, {RT}},
3702{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, {RT}},
3703{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, {RT}},
3704{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, {RT}},
3705{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, {RT}},
3706{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, {RT}},
3707{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, {RT}},
3708{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, {RT}},
3709{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, {RT}},
3710{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, {RT}},
3711{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, {RT}},
3712{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, {RT}},
3713{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, {RT}},
3714{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, {RT}},
3715{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, {RT}},
3716{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, {RT}},
3717{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, {RT}},
3718{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, {RT}},
3719{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, {RT}},
3720{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, {RT}},
3721{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, {RT}},
3722{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, {RT}},
3723{"mfspr", X(31,339), X_MASK, COM, {RT, SPR}},
3724
3725{"lwax", X(31,341), X_MASK, PPC64, {RT, RA0, RB}},
3726
3727{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
3728
3729{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}},
3730
3731{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}},
3732
3733{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}},
3734
3735{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}},
3736{"abs.", XO(31,360,0,1), XORB_MASK, M601, {RT, RA}},
3737
3738{"divs", XO(31,363,0,0), XO_MASK, M601, {RT, RA, RB}},
3739{"divs.", XO(31,363,0,1), XO_MASK, M601, {RT, RA, RB}},
3740
3741{"tlbia", X(31,370), 0xffffffff, PPC, {0}},
3742
3743{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, {RT}},
3744{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, {RT}},
3745{"mftb", X(31,371), X_MASK, CLASSIC, {RT, TBR}},
3746
3747{"lwaux", X(31,373), X_MASK, PPC64, {RT, RAL, RB}},
3748
3749{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
3750
3751{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}},
3752
3753{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}},
3754
3755{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}},
3756
3757{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}},
3758
3759{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
3760
3761{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
3762
3763{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}},
3764
3765{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}},
3766
3767{"sthx", X(31,407), X_MASK, COM, {RS, RA0, RB}},
3768
3769{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}},
3770{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}},
3771
3772{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}},
3773
3774{"slbie", X(31,434), XRTRA_MASK, PPC64, {RB}},
3775
3776{"ecowx", X(31,438), X_MASK, PPC, {RT, RA, RB}},
3777
3778{"sthux", X(31,439), X_MASK, COM, {RS, RAS, RB}},
3779
3780{"mr", XRC(31,444,0), X_MASK, COM, {RA, RS, RBS}},
3781{"or", XRC(31,444,0), X_MASK, COM, {RA, RS, RB}},
3782{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}},
3783{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}},
3784
3785{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}},
3786
3787{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}},
3788{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}},
3789{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}},
3790{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, {RS}},
3791{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, {RS}},
3792{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, {RS}},
3793{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, {RS}},
3794{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, {RS}},
3795{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, {RS}},
3796{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, {RS}},
3797{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, {RS}},
3798{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, {RS}},
3799{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, {RS}},
3800{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, {RS}},
3801{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, {RS}},
3802{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, {RS}},
3803{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, {RS}},
3804{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, {RS}},
3805{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, {RS}},
3806{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, {RS}},
3807{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, {RS}},
3808{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, {RS}},
3809{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, {RS}},
3810{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, {RS}},
3811{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, {RS}},
3812{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, {RS}},
3813{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, {RS}},
3814{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, {RS}},
3815{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, {RS}},
3816{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, {RS}},
3817{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, {RS}},
3818{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, {RS}},
3819{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, {RS}},
3820{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, {RS}},
3821{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, {SPR, RS}},
3822
3823{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}},
3824
3825{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}},
3826
3827{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3828{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}},
3829
3830{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}},
3831
3832{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}},
3833{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}},
3834
3835{"mtpmr", X(31,462), X_MASK, PPCPMR, {PMR, RS}},
3836
3837{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}},
3838{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}},
3839{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, {RS}},
3840{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, {RS}},
3841{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, {RS}},
3842{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, {RS}},
3843{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, {RS}},
3844{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, {RS}},
3845{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, {RS}},
3846{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, {RS}},
3847{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, {RS}},
3848{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, {RS}},
3849{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, {RS}},
3850{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, {RS}},
3851{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, {RS}},
3852{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, {RS}},
3853{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, {RS}},
3854{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, {RS}},
3855{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, {RS}},
3856{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, {RS}},
3857{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, {RS}},
3858{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, {RS}},
3859{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, {RS}},
3860{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, {RS}},
3861{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, {RS}},
3862{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, {RS}},
3863{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, {RS}},
3864{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, {RS}},
3865{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, {RS}},
3866{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, {RS}},
3867{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, {RS}},
3868{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, {RS}},
3869{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, {RS}},
3870{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, {RS}},
3871{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, {RS}},
3872{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, {RS}},
3873{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, {RS}},
3874{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, {RS}},
3875{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, {RS}},
3876{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, {RS}},
3877{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, {SPRG, RS}},
3878{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, {RS}},
3879{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, {RS}},
3880{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, {RS}},
3881{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, {RS}},
3882{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, {RS}},
3883{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, {RS}},
3884{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, {RS}},
3885{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, {RS}},
3886{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, {RS}},
3887{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, {RS}},
3888{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, {RS}},
3889{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, {RS}},
3890{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, {RS}},
3891{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, {RS}},
3892{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, {RS}},
3893{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, {RS}},
3894{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, {RS}},
3895{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, {RS}},
3896{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, {RS}},
3897{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, {RS}},
3898{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, {RS}},
3899{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, {RS}},
3900{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, {RS}},
3901{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, {RS}},
3902{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, {RS}},
3903{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, {RS}},
3904{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, {RS}},
3905{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, {RS}},
3906{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, {RS}},
3907{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, {RS}},
3908{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, {RS}},
3909{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, {RS}},
3910{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, {RS}},
3911{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, {RS}},
3912{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, {RS}},
3913{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, {RS}},
3914{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, {RS}},
3915{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, {RS}},
3916{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, {RS}},
3917{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, {RS}},
3918{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, {RS}},
3919{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, {RS}},
3920{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, {RS}},
3921{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, {RS}},
3922{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, {RS}},
3923{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, {RS}},
3924{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3925{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, {RS}},
3926{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3927{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, {RS}},
3928{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, {RS}},
3929{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3930{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3931{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, {RS}},
3932{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, {RS}},
3933{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, {RS}},
3934{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, {RS}},
3935{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, {RS}},
3936{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, {RS}},
3937{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, {RS}},
3938{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, {RS}},
3939{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, {RS}},
3940{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, {RS}},
3941{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, {RS}},
3942{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, {RS}},
3943{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, {RS}},
3944{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, {RS}},
3945{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, {RS}},
3946{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, {RS}},
3947{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, {RS}},
3948{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, {RS}},
3949{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, {RS}},
3950{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, {RS}},
3951{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, {RS}},
3952{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, {RS}},
3953{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, {RS}},
3954{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, {RS}},
3955{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, {RS}},
3956{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, {RS}},
3957{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, {RS}},
3958{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, {RS}},
3959{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, {RS}},
3960{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, {RS}},
3961{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, {RS}},
3962{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, {RS}},
3963{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, {RS}},
3964{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, {RS}},
3965{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, {RS}},
3966{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, {RS}},
3967{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, {RS}},
3968{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, {RS}},
3969{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, {RS}},
3970{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, {RS}},
3971{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, {RS}},
3972{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, {RS}},
3973{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, {RS}},
3974{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, {RS}},
3975{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, {RS}},
3976{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, {RS}},
3977{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, {RS}},
3978{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, {RS}},
3979{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, {RS}},
3980{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, {RS}},
3981{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, {RS}},
3982{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, {RS}},
3983{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, {RS}},
3984{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, {RS}},
3985{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, {RS}},
3986{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, {RS}},
3987{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, {RS}},
3988{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, {RS}},
3989{"mtspr", X(31,467), X_MASK, COM, {SPR, RS}},
3990
3991{"dcbi", X(31,470), XRT_MASK, PPC, {RA, RB}},
3992
3993{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}},
3994{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}},
3995
3996{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}},
3997
3998{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}},
3999
4000{"icbtls", X(31,486), X_MASK, PPCCHLK, {CT, RA, RB}},
4001
4002{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}},
4003
4004{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}},
4005{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}},
4006{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}},
4007
4008{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}},
4009{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}},
4010
4011{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}},
4012
4013{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}},
4014{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}},
4015
4016{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}},
4017
4018{"slbia", X(31,498), 0xffffffff, PPC64, {0}},
4019
4020{"cli", X(31,502), XRB_MASK, POWER, {RT, RA}},
252b5132 4021
de866fcc 4022{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}},
252b5132 4023
de866fcc 4024{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}},
23976049 4025
de866fcc 4026{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}},
252b5132 4027
de866fcc 4028{"bblels", X(31,518), X_MASK, PPCBRLK, {0}},
252b5132 4029
de866fcc 4030{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}},
252b5132 4031
de866fcc
AM		 4032{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4033{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4034{"subco", XO(31,8,1,0), XO_MASK, PPC, {RT, RB, RA}},
4035{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4036{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
4037{"subco.", XO(31,8,1,1), XO_MASK, PPC, {RT, RB, RA}},
252b5132 4038
de866fcc
AM		 4039{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4040{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4041{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4042{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4043
de866fcc 4044{"clcs", X(31,531), XRB_MASK, M601, {RT, RA}},
418c1742 4045
de866fcc 4046{"ldbrx", X(31,532), X_MASK, CELL, {RT, RA0, RB}},
418c1742 4047
de866fcc
AM		 4048{"lswx", X(31,533), X_MASK, PPCCOM, {RT, RA0, RB}},
4049{"lsx", X(31,533), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4050
de866fcc
AM		 4051{"lwbrx", X(31,534), X_MASK, PPCCOM, {RT, RA0, RB}},
4052{"lbrx", X(31,534), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4053
de866fcc 4054{"lfsx", X(31,535), X_MASK, COM, {FRT, RA0, RB}},
702f0fb4 4055
de866fcc
AM		 4056{"srw", XRC(31,536,0), X_MASK, PPCCOM, {RA, RS, RB}},
4057{"sr", XRC(31,536,0), X_MASK, PWRCOM, {RA, RS, RB}},
4058{"srw.", XRC(31,536,1), X_MASK, PPCCOM, {RA, RS, RB}},
4059{"sr.", XRC(31,536,1), X_MASK, PWRCOM, {RA, RS, RB}},
252b5132 4060
de866fcc
AM		 4061{"rrib", XRC(31,537,0), X_MASK, M601, {RA, RS, RB}},
4062{"rrib.", XRC(31,537,1), X_MASK, M601, {RA, RS, RB}},
23976049 4063
de866fcc
AM		 4064{"srd", XRC(31,539,0), X_MASK, PPC64, {RA, RS, RB}},
4065{"srd.", XRC(31,539,1), X_MASK, PPC64, {RA, RS, RB}},
f509565f 4066
de866fcc
AM		 4067{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}},
4068{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4069
de866fcc 4070{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}},
252b5132 4071
de866fcc 4072{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}},
252b5132 4073
de866fcc 4074{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
702f0fb4 4075
de866fcc 4076{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}},
418c1742 4077
de866fcc 4078{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}},
252b5132 4079
de866fcc
AM		 4080{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}},
4081{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}},
4082{"subfo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RA, RB}},
4083{"subo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RB, RA}},
252b5132 4084
de866fcc 4085{"tlbsync", X(31,566), 0xffffffff, PPC, {0}},
252b5132 4086
de866fcc 4087{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}},
252b5132 4088
de866fcc 4089{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}},
252b5132 4090
de866fcc 4091{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}},
252b5132 4092
de866fcc
AM		 4093{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}},
4094{"lsi", X(31,597), X_MASK, PWRCOM, {RT, RA0, NB}},
252b5132 4095
de866fcc
AM		 4096{"msync", X(31,598), 0xffffffff, BOOKE, {0}},
4097{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, {0}},
4098{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, {0}},
4099{"sync", X(31,598), XSYNC_MASK, PPCCOM, {LS}},
4100{"dcs", X(31,598), 0xffffffff, PWRCOM, {0}},
418c1742 4101
de866fcc 4102{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}},
23976049 4103
de866fcc
AM		 4104{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}},
4105{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}},
252b5132 4106
de866fcc
AM		 4107{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}},
4108{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}},
252b5132 4109
de866fcc
AM		 4110{"mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}},
4111{"mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 4112
de866fcc 4113{"mfsri", X(31,627), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4114
de866fcc 4115{"dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}},
252b5132 4116
de866fcc 4117{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}},
252b5132 4118
de866fcc 4119{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}},
252b5132 4120
de866fcc 4121{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
23976049 4122
de866fcc
AM		 4123{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4124{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4125{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4126{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4127
de866fcc
AM		 4128{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4129{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4130{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4131{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4132
de866fcc 4133{"mfsrin", X(31,659), XRA_MASK, PPC32, {RT, RB}},
418c1742 4134
de866fcc 4135{"stdbrx", X(31,660), X_MASK, CELL, {RS, RA0, RB}},
252b5132 4136
de866fcc
AM		 4137{"stswx", X(31,661), X_MASK, PPCCOM, {RS, RA0, RB}},
4138{"stsx", X(31,661), X_MASK, PWRCOM, {RS, RA0, RB}},
418c1742 4139
de866fcc
AM		 4140{"stwbrx", X(31,662), X_MASK, PPCCOM, {RS, RA0, RB}},
4141{"stbrx", X(31,662), X_MASK, PWRCOM, {RS, RA0, RB}},
252b5132 4142
de866fcc 4143{"stfsx", X(31,663), X_MASK, COM, {FRS, RA0, RB}},
ede602d7 4144
de866fcc
AM		 4145{"srq", XRC(31,664,0), X_MASK, M601, {RA, RS, RB}},
4146{"srq.", XRC(31,664,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4147
de866fcc
AM		 4148{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}},
4149{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4150
de866fcc 4151{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}},
252b5132 4152
de866fcc 4153{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}},
252b5132 4154
de866fcc 4155{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
252b5132 4156
de866fcc 4157{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}},
252b5132 4158
de866fcc
AM		 4159{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}},
4160{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}},
252b5132 4161
de866fcc 4162{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}},
418c1742 4163
de866fcc
AM		 4164{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4165{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4166{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4167{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, {RT, RA}},
418c1742 4168
de866fcc
AM		 4169{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4170{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4171{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4172{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, {RT, RA}},
fdd12ef3 4173
de866fcc
AM		 4174{"stswi", X(31,725), X_MASK, PPCCOM, {RS, RA0, NB}},
4175{"stsi", X(31,725), X_MASK, PWRCOM, {RS, RA0, NB}},
252b5132 4176
de866fcc 4177{"stfdx", X(31,727), X_MASK, COM, {FRS, RA0, RB}},
252b5132 4178
de866fcc
AM		 4179{"srlq", XRC(31,728,0), X_MASK, M601, {RA, RS, RB}},
4180{"srlq.", XRC(31,728,1), X_MASK, M601, {RA, RS, RB}},
418c1742 4181
de866fcc
AM		 4182{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}},
4183{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4184
de866fcc
AM		 4185{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}},
4186{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}},
252b5132 4187
de866fcc
AM		 4188{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4189{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4190{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4191{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 4192
de866fcc
AM		 4193{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, {RT, RA, RB}},
4194{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, {RT, RA, RB}},
252b5132 4195
de866fcc
AM		 4196{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4197{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4198{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4199{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, {RT, RA}},
418c1742 4200
de866fcc
AM		 4201{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4202{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4203{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4204{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
702f0fb4 4205
de866fcc 4206{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}},
252b5132 4207
de866fcc 4208{"stfdux", X(31,759), X_MASK, COM, {FRS, RAS, RB}},
252b5132 4209
de866fcc
AM		 4210{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}},
4211{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}},
252b5132 4212
de866fcc 4213{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}},
418c1742 4214
de866fcc 4215{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}},
252b5132 4216
de866fcc 4217{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}},
ede602d7 4218
de866fcc
AM		 4219{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}},
4220{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 4221
de866fcc
AM		 4222{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4223{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4224{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4225{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4226
de866fcc
AM		 4227{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}},
4228{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}},
252b5132 4229
de866fcc 4230{"lwzcix", X(31,789), X_MASK, POWER6, {RT, RA0, RB}},
252b5132 4231
de866fcc 4232{"lhbrx", X(31,790), X_MASK, COM, {RT, RA0, RB}},
252b5132 4233
de866fcc
AM		 4234{"lfqx", X(31,791), X_MASK, POWER2, {FRT, RA, RB}},
4235{"lfdpx", X(31,791), X_MASK, POWER6, {FRT, RA, RB}},
418c1742 4236
de866fcc
AM		 4237{"sraw", XRC(31,792,0), X_MASK, PPCCOM, {RA, RS, RB}},
4238{"sra", XRC(31,792,0), X_MASK, PWRCOM, {RA, RS, RB}},
4239{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, {RA, RS, RB}},
4240{"sra.", XRC(31,792,1), X_MASK, PWRCOM, {RA, RS, RB}},
fdd12ef3 4241
de866fcc
AM		 4242{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}},
4243{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}},
252b5132 4244
de866fcc 4245{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}},
252b5132 4246
de866fcc 4247{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}},
418c1742 4248
de866fcc 4249{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}},
252b5132 4250
de866fcc 4251{"rac", X(31,818), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4252
de866fcc 4253{"lhzcix", X(31,821), X_MASK, POWER6, {RT, RA0, RB}},
252b5132 4254
de866fcc 4255{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, {STRM}},
252b5132 4256
de866fcc 4257{"lfqux", X(31,823), X_MASK, POWER2, {FRT, RA, RB}},
fdd12ef3 4258
de866fcc
AM		 4259{"srawi", XRC(31,824,0), X_MASK, PPCCOM, {RA, RS, SH}},
4260{"srai", XRC(31,824,0), X_MASK, PWRCOM, {RA, RS, SH}},
4261{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, {RA, RS, SH}},
4262{"srai.", XRC(31,824,1), X_MASK, PWRCOM, {RA, RS, SH}},
702f0fb4 4263
de866fcc
AM		 4264{"sradi", XS(31,413,0), XS_MASK, PPC64, {RA, RS, SH6}},
4265{"sradi.", XS(31,413,1), XS_MASK, PPC64, {RA, RS, SH6}},
e0c21649 4266
de866fcc
AM		 4267{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}},
4268{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
4269{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
252b5132 4270
de866fcc 4271{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}},
252b5132 4272
de866fcc 4273{"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}},
418c1742 4274
de866fcc
AM		 4275{"mbar", X(31,854), X_MASK, BOOKE, {MO}},
4276{"eieio", X(31,854), 0xffffffff, PPC, {0}},
418c1742 4277
de866fcc 4278{"lfiwax", X(31,855), X_MASK, POWER6, {FRT, RA0, RB}},
418c1742 4279
de866fcc
AM		 4280{"abso", XO(31,360,1,0), XORB_MASK, M601, {RT, RA}},
4281{"abso.", XO(31,360,1,1), XORB_MASK, M601, {RT, RA}},
702f0fb4 4282
de866fcc
AM		 4283{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}},
4284{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 4285
de866fcc 4286{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}},
252b5132 4287
de866fcc 4288{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
252b5132 4289
de866fcc 4290{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
418c1742 4291
de866fcc 4292{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
418c1742 4293
de866fcc
AM		 4294{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
4295{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
252b5132 4296
de866fcc
AM		 4297{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}},
4298{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}},
4299{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}},
702f0fb4 4300
de866fcc 4301{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}},
f5c120c5 4302
de866fcc 4303{"sthbrx", X(31,918), X_MASK, COM, {RS, RA0, RB}},
252b5132 4304
de866fcc
AM		 4305{"stfqx", X(31,919), X_MASK, POWER2, {FRS, RA, RB}},
4306{"stfdpx", X(31,919), X_MASK, POWER6, {FRS, RA, RB}},
6ba045b1 4307
de866fcc
AM		 4308{"sraq", XRC(31,920,0), X_MASK, M601, {RA, RS, RB}},
4309{"sraq.", XRC(31,920,1), X_MASK, M601, {RA, RS, RB}},
702f0fb4 4310
de866fcc
AM		 4311{"srea", XRC(31,921,0), X_MASK, M601, {RA, RS, RB}},
4312{"srea.", XRC(31,921,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4313
de866fcc
AM		 4314{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, {RA, RS}},
4315{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, {RA, RS}},
4316{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}},
4317{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}},
702f0fb4 4318
de866fcc 4319{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}},
702f0fb4 4320
de866fcc 4321{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}},
418c1742 4322
de866fcc 4323{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}},
6ba045b1 4324
de866fcc
AM		 4325{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, {RT, RA}},
4326{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, {RT, RA}},
4327{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
702f0fb4 4328
de866fcc 4329{"sthcix", X(31,949), X_MASK, POWER6, {RS, RA0, RB}},
252b5132 4330
de866fcc 4331{"stfqux", X(31,951), X_MASK, POWER2, {FRS, RA, RB}},
252b5132 4332
de866fcc
AM		 4333{"sraiq", XRC(31,952,0), X_MASK, M601, {RA, RS, SH}},
4334{"sraiq.", XRC(31,952,1), X_MASK, M601, {RA, RS, SH}},
252b5132 4335
de866fcc
AM		 4336{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}},
4337{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}},
252b5132 4338
de866fcc 4339{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}},
418c1742 4340
de866fcc 4341{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}},
418c1742 4342
de866fcc 4343{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}},
252b5132 4344
de866fcc
AM		 4345{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}},
4346{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}},
702f0fb4 4347
de866fcc 4348{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}},
252b5132 4349
de866fcc
AM		 4350{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
4351{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
252b5132 4352
de866fcc
AM		 4353{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}},
4354{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}},
4355{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
4356{"tlbld", X(31,978), XRTRA_MASK, PPC, {RB}},
418c1742 4357
de866fcc 4358{"stbcix", X(31,981), X_MASK, POWER6, {RS, RA0, RB}},
252b5132 4359
de866fcc 4360{"icbi", X(31,982), XRT_MASK, PPC, {RA, RB}},
252b5132 4361
de866fcc 4362{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}},
702f0fb4 4363
de866fcc
AM		 4364{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}},
4365{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}},
252b5132 4366
de866fcc
AM		 4367{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}},
4368{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}},
252b5132 4369
de866fcc 4370{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}},
252b5132 4371
de866fcc
AM		 4372{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}},
4373{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}},
4374{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}},
252b5132 4375
de866fcc
AM		 4376{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}},
4377{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}},
418c1742 4378
de866fcc 4379{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}},
252b5132 4380
de866fcc
AM		 4381{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
4382{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
702f0fb4 4383
de866fcc 4384{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}},
252b5132 4385
de866fcc 4386{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}},
418c1742 4387
de866fcc
AM		 4388{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
4389{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
786e2c0f 4390
de866fcc 4391{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}},
ede602d7 4392
de866fcc 4393{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
252b5132 4394
de866fcc
AM		 4395{"cctpl", 0x7c210b78, 0xffffffff, CELL, {0}},
4396{"cctpm", 0x7c421378, 0xffffffff, CELL, {0}},
4397{"cctph", 0x7c631b78, 0xffffffff, CELL, {0}},
252b5132 4398
de866fcc
AM		 4399{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
4400{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
4401{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, {0}},
252b5132 4402
de866fcc
AM		 4403{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, {0}},
4404{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, {0}},
4405{"db12cyc", 0x7fdef378, 0xffffffff, CELL, {0}},
4406{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, {0}},
252b5132 4407
de866fcc
AM		 4408{"lwz", OP(32), OP_MASK, PPCCOM, {RT, D, RA0}},
4409{"l", OP(32), OP_MASK, PWRCOM, {RT, D, RA0}},
252b5132 4410
de866fcc
AM		 4411{"lwzu", OP(33), OP_MASK, PPCCOM, {RT, D, RAL}},
4412{"lu", OP(33), OP_MASK, PWRCOM, {RT, D, RA0}},
252b5132 4413
de866fcc 4414{"lbz", OP(34), OP_MASK, COM, {RT, D, RA0}},
252b5132 4415
de866fcc 4416{"lbzu", OP(35), OP_MASK, COM, {RT, D, RAL}},
252b5132 4417
de866fcc
AM		 4418{"stw", OP(36), OP_MASK, PPCCOM, {RS, D, RA0}},
4419{"st", OP(36), OP_MASK, PWRCOM, {RS, D, RA0}},
252b5132 4420
de866fcc
AM		 4421{"stwu", OP(37), OP_MASK, PPCCOM, {RS, D, RAS}},
4422{"stu", OP(37), OP_MASK, PWRCOM, {RS, D, RA0}},
252b5132 4423
de866fcc 4424{"stb", OP(38), OP_MASK, COM, {RS, D, RA0}},
252b5132 4425
de866fcc 4426{"stbu", OP(39), OP_MASK, COM, {RS, D, RAS}},
252b5132 4427
de866fcc 4428{"lhz", OP(40), OP_MASK, COM, {RT, D, RA0}},
252b5132 4429
de866fcc 4430{"lhzu", OP(41), OP_MASK, COM, {RT, D, RAL}},
252b5132 4431
de866fcc 4432{"lha", OP(42), OP_MASK, COM, {RT, D, RA0}},
252b5132 4433
de866fcc 4434{"lhau", OP(43), OP_MASK, COM, {RT, D, RAL}},
252b5132 4435
de866fcc 4436{"sth", OP(44), OP_MASK, COM, {RS, D, RA0}},
252b5132 4437
de866fcc 4438{"sthu", OP(45), OP_MASK, COM, {RS, D, RAS}},
252b5132 4439
de866fcc
AM		 4440{"lmw", OP(46), OP_MASK, PPCCOM, {RT, D, RAM}},
4441{"lm", OP(46), OP_MASK, PWRCOM, {RT, D, RA0}},
252b5132 4442
de866fcc
AM		 4443{"stmw", OP(47), OP_MASK, PPCCOM, {RS, D, RA0}},
4444{"stm", OP(47), OP_MASK, PWRCOM, {RS, D, RA0}},
252b5132 4445
de866fcc 4446{"lfs", OP(48), OP_MASK, COM, {FRT, D, RA0}},
252b5132 4447
de866fcc 4448{"lfsu", OP(49), OP_MASK, COM, {FRT, D, RAS}},
252b5132 4449
de866fcc 4450{"lfd", OP(50), OP_MASK, COM, {FRT, D, RA0}},
252b5132 4451
de866fcc 4452{"lfdu", OP(51), OP_MASK, COM, {FRT, D, RAS}},
252b5132 4453
de866fcc 4454{"stfs", OP(52), OP_MASK, COM, {FRS, D, RA0}},
adadcc0c 4455
de866fcc 4456{"stfsu", OP(53), OP_MASK, COM, {FRS, D, RAS}},
252b5132 4457
de866fcc 4458{"stfd", OP(54), OP_MASK, COM, {FRS, D, RA0}},
c3d65c1c 4459
de866fcc 4460{"stfdu", OP(55), OP_MASK, COM, {FRS, D, RAS}},
252b5132 4461
de866fcc 4462{"lq", OP(56), OP_MASK, POWER4, {RTQ, DQ, RAQ}},
c3d65c1c 4463
de866fcc 4464{"lfq", OP(56), OP_MASK, POWER2, {FRT, D, RA0}},
702f0fb4 4465
de866fcc 4466{"psq_l", OP(56), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}},
418c1742 4467
de866fcc 4468{"lfqu", OP(57), OP_MASK, POWER2, {FRT, D, RA0}},
802a735e 4469
de866fcc 4470{"psq_lu", OP(57), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}},
802a735e 4471
de866fcc 4472{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}},
fdd12ef3 4473
de866fcc
AM		 4474{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}},
4475{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}},
4476{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}},
4477{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}},
4478{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}},
4479{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}},
4480{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}},
4481{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}},
4482{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}},
4483{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}},
4484{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}},
4485{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}},
4486{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}},
4487{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}},
702f0fb4 4488
de866fcc
AM		 4489{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}},
4490{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}},
4491{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}},
702f0fb4 4492
de866fcc
AM		 4493{"dadd", XRC(59,2,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4494{"dadd.", XRC(59,2,1), X_MASK, POWER6, {FRT, FRA, FRB}},
252b5132 4495
de866fcc
AM		 4496{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
4497{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
252b5132 4498
de866fcc
AM		 4499{"fdivs", A(59,18,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
4500{"fdivs.", A(59,18,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
252b5132 4501
de866fcc
AM		 4502{"fsubs", A(59,20,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
4503{"fsubs.", A(59,20,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
252b5132 4504
de866fcc
AM		 4505{"fadds", A(59,21,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
4506{"fadds.", A(59,21,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
252b5132 4507
de866fcc
AM		 4508{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, {FRT, FRB}},
4509{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, {FRT, FRB}},
252b5132 4510
de866fcc
AM		 4511{"fres", A(59,24,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
4512{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
1ed8e1e4 4513
de866fcc
AM		 4514{"fmuls", A(59,25,0), AFRB_MASK, PPC, {FRT, FRA, FRC}},
4515{"fmuls.", A(59,25,1), AFRB_MASK, PPC, {FRT, FRA, FRC}},
252b5132 4516
de866fcc
AM		 4517{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
4518{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
252b5132 4519
de866fcc
AM		 4520{"fmsubs", A(59,28,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4521{"fmsubs.", A(59,28,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
252b5132 4522
de866fcc
AM		 4523{"fmadds", A(59,29,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4524{"fmadds.", A(59,29,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
252b5132 4525
de866fcc
AM		 4526{"fnmsubs", A(59,30,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4527{"fnmsubs.", A(59,30,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
702f0fb4 4528
de866fcc
AM		 4529{"fnmadds", A(59,31,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4530{"fnmadds.", A(59,31,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
702f0fb4 4531
de866fcc
AM		 4532{"dmul", XRC(59,34,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4533{"dmul.", XRC(59,34,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4534
de866fcc
AM		 4535{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
4536{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
702f0fb4 4537
de866fcc
AM		 4538{"dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4539{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4540
de866fcc
AM		 4541{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}},
4542{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}},
702f0fb4 4543
de866fcc
AM		 4544{"dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4545{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4546
de866fcc
AM		 4547{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4548{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4549
de866fcc 4550{"dcmpo", X(59,130), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4551
de866fcc
AM		 4552{"dtstex", X(59,162), X_MASK, POWER6, {BF, FRA, FRB}},
4553{"dtstdc", Z(59,194), Z_MASK, POWER6, {BF, FRA, DCM}},
4554{"dtstdg", Z(59,226), Z_MASK, POWER6, {BF, FRA, DGM}},
702f0fb4 4555
de866fcc
AM		 4556{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4557{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4558
de866fcc
AM		 4559{"dctdp", XRC(59,258,0), X_MASK, POWER6, {FRT, FRB}},
4560{"dctdp.", XRC(59,258,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4561
de866fcc
AM		 4562{"dctfix", XRC(59,290,0), X_MASK, POWER6, {FRT, FRB}},
4563{"dctfix.", XRC(59,290,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4564
de866fcc
AM		 4565{"ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
4566{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
702f0fb4 4567
de866fcc
AM		 4568{"dxex", XRC(59,354,0), X_MASK, POWER6, {FRT, FRB}},
4569{"dxex.", XRC(59,354,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4570
de866fcc
AM		 4571{"dsub", XRC(59,514,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4572{"dsub.", XRC(59,514,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4573
de866fcc
AM		 4574{"ddiv", XRC(59,546,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4575{"ddiv.", XRC(59,546,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4576
de866fcc 4577{"dcmpu", X(59,642), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4578
de866fcc 4579{"dtstsf", X(59,674), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4580
de866fcc
AM		 4581{"drsp", XRC(59,770,0), X_MASK, POWER6, {FRT, FRB}},
4582{"drsp.", XRC(59,770,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4583
de866fcc
AM		 4584{"denbcd", XRC(59,834,0), X_MASK, POWER6, {S, FRT, FRB}},
4585{"denbcd.", XRC(59,834,1), X_MASK, POWER6, {S, FRT, FRB}},
252b5132 4586
de866fcc
AM		 4587{"diex", XRC(59,866,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4588{"diex.", XRC(59,866,1), X_MASK, POWER6, {FRT, FRA, FRB}},
8dbcd839 4589
de866fcc 4590{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}},
252b5132 4591
de866fcc
AM		 4592{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
4593{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
702f0fb4 4594
de866fcc 4595{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}},
418c1742 4596
de866fcc 4597{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}},
802a735e 4598
de866fcc
AM		 4599{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}},
4600{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}},
4601{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}},
4602{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}},
4603{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}},
4604{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}},
4605{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}},
4606{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}},
4607{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}},
4608{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}},
4609{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}},
4610{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}},
802a735e 4611
de866fcc
AM		 4612{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}},
4613{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}},
4614{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}},
fdd12ef3 4615
de866fcc 4616{"fcmpu", X(63,0), X_MASK|(3<<21), COM, {BF, FRA, FRB}},
252b5132 4617
de866fcc
AM		 4618{"daddq", XRC(63,2,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4619{"daddq.", XRC(63,2,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4620
de866fcc
AM		 4621{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
4622{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
702f0fb4 4623
de866fcc
AM		 4624{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4625{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4626
de866fcc
AM		 4627{"frsp", XRC(63,12,0), XRA_MASK, COM, {FRT, FRB}},
4628{"frsp.", XRC(63,12,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4629
de866fcc
AM		 4630{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, {FRT, FRB}},
4631{"fcir", XRC(63,14,0), XRA_MASK, POWER2, {FRT, FRB}},
4632{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, {FRT, FRB}},
4633{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, {FRT, FRB}},
252b5132 4634
de866fcc
AM		 4635{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, {FRT, FRB}},
4636{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, {FRT, FRB}},
4637{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, {FRT, FRB}},
4638{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, {FRT, FRB}},
252b5132 4639
de866fcc
AM		 4640{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4641{"fd", A(63,18,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
4642{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4643{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
252b5132 4644
de866fcc
AM		 4645{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4646{"fs", A(63,20,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
4647{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4648{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
252b5132 4649
de866fcc
AM		 4650{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4651{"fa", A(63,21,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
4652{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4653{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
252b5132 4654
de866fcc
AM		 4655{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}},
4656{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}},
252b5132 4657
de866fcc
AM		 4658{"fsel", A(63,23,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4659{"fsel.", A(63,23,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
252b5132 4660
de866fcc
AM		 4661{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
4662{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
1ed8e1e4 4663
de866fcc
AM		 4664{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}},
4665{"fm", A(63,25,0), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}},
4666{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}},
4667{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}},
252b5132 4668
de866fcc
AM		 4669{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
4670{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
252b5132 4671
de866fcc
AM		 4672{"fmsub", A(63,28,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4673{"fms", A(63,28,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4674{"fmsub.", A(63,28,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4675{"fms.", A(63,28,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4676
de866fcc
AM		 4677{"fmadd", A(63,29,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4678{"fma", A(63,29,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4679{"fmadd.", A(63,29,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4680{"fma.", A(63,29,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4681
de866fcc
AM		 4682{"fnmsub", A(63,30,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4683{"fnms", A(63,30,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4684{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4685{"fnms.", A(63,30,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4686
de866fcc
AM		 4687{"fnmadd", A(63,31,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4688{"fnma", A(63,31,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4689{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4690{"fnma.", A(63,31,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4691
de866fcc 4692{"fcmpo", X(63,32), X_MASK|(3<<21), COM, {BF, FRA, FRB}},
252b5132 4693
de866fcc
AM		 4694{"dmulq", XRC(63,34,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4695{"dmulq.", XRC(63,34,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4696
de866fcc
AM		 4697{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
4698{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
702f0fb4 4699
de866fcc
AM		 4700{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, {BT}},
4701{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, {BT}},
252b5132 4702
de866fcc
AM		 4703{"fneg", XRC(63,40,0), XRA_MASK, COM, {FRT, FRB}},
4704{"fneg.", XRC(63,40,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4705
de866fcc 4706{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
252b5132 4707
de866fcc
AM		 4708{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4709{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4710
de866fcc
AM		 4711{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}},
4712{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}},
702f0fb4 4713
de866fcc
AM		 4714{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, {BT}},
4715{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, {BT}},
252b5132 4716
de866fcc
AM		 4717{"fmr", XRC(63,72,0), XRA_MASK, COM, {FRT, FRB}},
4718{"fmr.", XRC(63,72,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4719
de866fcc
AM		 4720{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4721{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4722
de866fcc
AM		 4723{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4724{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4725
de866fcc 4726{"dcmpoq", X(63,130), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4727
de866fcc
AM		 4728{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
4729{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
252b5132 4730
de866fcc
AM		 4731{"fnabs", XRC(63,136,0), XRA_MASK, COM, {FRT, FRB}},
4732{"fnabs.", XRC(63,136,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4733
de866fcc
AM		 4734{"dtstexq", X(63,162), X_MASK, POWER6, {BF, FRA, FRB}},
4735{"dtstdcq", Z(63,194), Z_MASK, POWER6, {BF, FRA, DCM}},
4736{"dtstdgq", Z(63,226), Z_MASK, POWER6, {BF, FRA, DGM}},
702f0fb4 4737
de866fcc
AM		 4738{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4739{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4740
de866fcc
AM		 4741{"dctqpq", XRC(63,258,0), X_MASK, POWER6, {FRT, FRB}},
4742{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4743
de866fcc
AM		 4744{"fabs", XRC(63,264,0), XRA_MASK, COM, {FRT, FRB}},
4745{"fabs.", XRC(63,264,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4746
de866fcc
AM		 4747{"dctfixq", XRC(63,290,0), X_MASK, POWER6, {FRT, FRB}},
4748{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4749
de866fcc
AM		 4750{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
4751{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
702f0fb4 4752
de866fcc
AM		 4753{"dxexq", XRC(63,354,0), X_MASK, POWER6, {FRT, FRB}},
4754{"dxexq.", XRC(63,354,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4755
de866fcc
AM		 4756{"frin", XRC(63,392,0), XRA_MASK, POWER5, {FRT, FRB}},
4757{"frin.", XRC(63,392,1), XRA_MASK, POWER5, {FRT, FRB}},
4758{"friz", XRC(63,424,0), XRA_MASK, POWER5, {FRT, FRB}},
4759{"friz.", XRC(63,424,1), XRA_MASK, POWER5, {FRT, FRB}},
4760{"frip", XRC(63,456,0), XRA_MASK, POWER5, {FRT, FRB}},
4761{"frip.", XRC(63,456,1), XRA_MASK, POWER5, {FRT, FRB}},
4762{"frim", XRC(63,488,0), XRA_MASK, POWER5, {FRT, FRB}},
4763{"frim.", XRC(63,488,1), XRA_MASK, POWER5, {FRT, FRB}},
ce7a772b 4764
de866fcc
AM		 4765{"dsubq", XRC(63,514,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4766{"dsubq.", XRC(63,514,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4767
de866fcc
AM		 4768{"ddivq", XRC(63,546,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4769{"ddivq.", XRC(63,546,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4770
de866fcc
AM		 4771{"mffs", XRC(63,583,0), XRARB_MASK, COM, {FRT}},
4772{"mffs.", XRC(63,583,1), XRARB_MASK, COM, {FRT}},
252b5132 4773
de866fcc 4774{"dcmpuq", X(63,642), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4775
de866fcc 4776{"dtstsfq", X(63,674), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4777
de866fcc
AM		 4778{"mtfsf", XFL(63,711,0), XFL_MASK, COM, {FLM, FRB, XFL_L, W}},
4779{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, {FLM, FRB, XFL_L, W}},
252b5132 4780
de866fcc
AM		 4781{"drdpq", XRC(63,770,0), X_MASK, POWER6, {FRT, FRB}},
4782{"drdpq.", XRC(63,770,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4783
de866fcc
AM		 4784{"dcffixq", XRC(63,802,0), X_MASK, POWER6, {FRT, FRB}},
4785{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4786
de866fcc
AM		 4787{"fctid", XRC(63,814,0), XRA_MASK, PPC64, {FRT, FRB}},
4788{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, {FRT, FRB}},
252b5132 4789
de866fcc
AM		 4790{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, {FRT, FRB}},
4791{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, {FRT, FRB}},
252b5132 4792
de866fcc
AM		 4793{"denbcdq", XRC(63,834,0), X_MASK, POWER6, {S, FRT, FRB}},
4794{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, {S, FRT, FRB}},
702f0fb4 4795
de866fcc
AM		 4796{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, {FRT, FRB}},
4797{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, {FRT, FRB}},
252b5132 4798
de866fcc
AM		 4799{"diexq", XRC(63,866,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4800{"diexq.", XRC(63,866,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4801
252b5132
RH		 4802};
4803
4804const int powerpc_num_opcodes =
4805 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4806\f
4807/* The macro table. This is only used by the assembler. */
4808
4809/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4810 when x=0; 32-x when x is between 1 and 31; are negative if x is
4811 negative; and are 32 or more otherwise. This is what you want
4812 when, for instance, you are emulating a right shift by a
4813 rotate-left-and-mask, because the underlying instructions support
4814 shifts of size 0 but not shifts of size 32. By comparison, when
4815 extracting x bits from some word you want to use just 32-x, because
4816 the underlying instructions don't support extracting 0 bits but do
4817 support extracting the whole word (32 bits in this case). */
4818
4819const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 4820{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
4821{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
4822{"extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)"},
4823{"extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)"},
4824{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
4825{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
4826{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
4827{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
4828{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
4829{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
4830{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
4831{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
4832{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
4833{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
4834{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
4835{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
4836
4837{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
4838{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
4839{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4840{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4841{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4842{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4843{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4844{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4845{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4846{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4847{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
4848{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
4849{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
4850{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
4851{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4852{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4853{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4854{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4855{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
4856{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
4857{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
4858{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 4859};
4860
4861const int powerpc_num_macros =
4862 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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