Commit | Line | Data |
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252b5132 | 1 | /* ppc-opc.c -- PowerPC opcode list |
219d1afa | 2 | Copyright (C) 1994-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
9b201bb5 | 5 | This file is part of the GNU opcodes library. |
252b5132 | 6 | |
9b201bb5 NC |
7 | This library is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
252b5132 | 11 | |
9b201bb5 NC |
12 | It is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
252b5132 | 16 | |
112290ab | 17 | You should have received a copy of the GNU General Public License |
9b201bb5 NC |
18 | along with this file; see the file COPYING. If not, write to the |
19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 | 21 | |
0d8dfecf | 22 | #include "sysdep.h" |
df7b86aa | 23 | #include <stdio.h> |
252b5132 RH |
24 | #include "opcode/ppc.h" |
25 | #include "opintl.h" | |
26 | ||
27 | /* This file holds the PowerPC opcode table. The opcode table | |
28 | includes almost all of the extended instruction mnemonics. This | |
29 | permits the disassembler to use them, and simplifies the assembler | |
30 | logic, at the cost of increasing the table size. The table is | |
31 | strictly constant data, so the compiler should be able to put it in | |
b80c7270 | 32 | the text segment. |
252b5132 RH |
33 | |
34 | This file also holds the operand table. All knowledge about | |
35 | inserting operands into instructions and vice-versa is kept in this | |
36 | file. */ | |
252b5132 | 37 | |
b80c7270 | 38 | /* The functions used to insert and extract complicated operands. */ |
252b5132 | 39 | |
b80c7270 | 40 | /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ |
252b5132 | 41 | |
0f873fd5 PB |
42 | static uint64_t |
43 | insert_arx (uint64_t insn, | |
44 | int64_t value, | |
b80c7270 AM |
45 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
46 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 47 | { |
b80c7270 AM |
48 | if (value >= 8 && value < 24) |
49 | return insn | ((value - 8) & 0xf); | |
50 | else | |
51 | { | |
52 | *errmsg = _("invalid register"); | |
53 | return 0; | |
54 | } | |
55 | } | |
b9c361e0 | 56 | |
0f873fd5 PB |
57 | static int64_t |
58 | extract_arx (uint64_t insn, | |
b80c7270 AM |
59 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
60 | int *invalid ATTRIBUTE_UNUSED) | |
61 | { | |
62 | return (insn & 0xf) + 8; | |
63 | } | |
b9c361e0 | 64 | |
0f873fd5 PB |
65 | static uint64_t |
66 | insert_ary (uint64_t insn, | |
67 | int64_t value, | |
b80c7270 AM |
68 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
69 | const char **errmsg ATTRIBUTE_UNUSED) | |
70 | { | |
71 | if (value >= 8 && value < 24) | |
72 | return insn | (((value - 8) & 0xf) << 4); | |
73 | else | |
74 | { | |
75 | *errmsg = _("invalid register"); | |
76 | return 0; | |
77 | } | |
78 | } | |
23976049 | 79 | |
0f873fd5 PB |
80 | static int64_t |
81 | extract_ary (uint64_t insn, | |
b80c7270 AM |
82 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
83 | int *invalid ATTRIBUTE_UNUSED) | |
84 | { | |
85 | return ((insn >> 4) & 0xf) + 8; | |
86 | } | |
418c1742 | 87 | |
0f873fd5 PB |
88 | static uint64_t |
89 | insert_rx (uint64_t insn, | |
90 | int64_t value, | |
b80c7270 AM |
91 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
92 | const char **errmsg) | |
93 | { | |
94 | if (value >= 0 && value < 8) | |
95 | return insn | value; | |
96 | else if (value >= 24 && value <= 31) | |
97 | return insn | (value - 16); | |
98 | else | |
99 | { | |
100 | *errmsg = _("invalid register"); | |
101 | return 0; | |
102 | } | |
103 | } | |
252b5132 | 104 | |
0f873fd5 PB |
105 | static int64_t |
106 | extract_rx (uint64_t insn, | |
b80c7270 AM |
107 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
108 | int *invalid ATTRIBUTE_UNUSED) | |
109 | { | |
0f873fd5 | 110 | int64_t value = insn & 0xf; |
b80c7270 AM |
111 | if (value >= 0 && value < 8) |
112 | return value; | |
113 | else | |
114 | return value + 16; | |
115 | } | |
b9c361e0 | 116 | |
0f873fd5 PB |
117 | static uint64_t |
118 | insert_ry (uint64_t insn, | |
119 | int64_t value, | |
b80c7270 AM |
120 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
121 | const char **errmsg) | |
122 | { | |
123 | if (value >= 0 && value < 8) | |
124 | return insn | (value << 4); | |
125 | else if (value >= 24 && value <= 31) | |
126 | return insn | ((value - 16) << 4); | |
127 | else | |
128 | { | |
129 | *errmsg = _("invalid register"); | |
130 | return 0; | |
131 | } | |
132 | } | |
a680de9a | 133 | |
0f873fd5 PB |
134 | static int64_t |
135 | extract_ry (uint64_t insn, | |
b80c7270 AM |
136 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
137 | int *invalid ATTRIBUTE_UNUSED) | |
138 | { | |
0f873fd5 | 139 | int64_t value = (insn >> 4) & 0xf; |
b80c7270 AM |
140 | if (value >= 0 && value < 8) |
141 | return value; | |
142 | else | |
143 | return value + 16; | |
144 | } | |
a680de9a | 145 | |
98553ad3 PB |
146 | /* The BA and BB fields in an XL form instruction or the RA and RB fields or |
147 | VRA and VRB fields in a VX form instruction when they must be the same. | |
148 | This is used for extended mnemonics like crclr. The extraction function | |
149 | enforces that the fields are the same. */ | |
adadcc0c | 150 | |
0f873fd5 | 151 | static uint64_t |
98553ad3 PB |
152 | insert_bab (uint64_t insn, |
153 | int64_t value, | |
b80c7270 AM |
154 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
155 | const char **errmsg ATTRIBUTE_UNUSED) | |
156 | { | |
98553ad3 PB |
157 | value &= 0x1f; |
158 | return insn | (value << 16) | (value << 11); | |
b80c7270 | 159 | } |
252b5132 | 160 | |
0f873fd5 | 161 | static int64_t |
98553ad3 | 162 | extract_bab (uint64_t insn, |
b80c7270 AM |
163 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
164 | int *invalid) | |
165 | { | |
98553ad3 PB |
166 | int64_t ba = (insn >> 16) & 0x1f; |
167 | int64_t bb = (insn >> 11) & 0x1f; | |
168 | ||
169 | if (ba != bb) | |
b80c7270 | 170 | *invalid = 1; |
98553ad3 | 171 | return ba; |
b80c7270 | 172 | } |
19a6653c | 173 | |
98553ad3 PB |
174 | /* The BT, BA and BB fields in an XL form instruction when they must all be |
175 | the same. This is used for extended mnemonics like crclr. The extraction | |
176 | function enforces that the fields are the same. */ | |
a680de9a | 177 | |
0f873fd5 | 178 | static uint64_t |
98553ad3 PB |
179 | insert_btab (uint64_t insn, |
180 | int64_t value, | |
181 | ppc_cpu_t dialect, | |
182 | const char **errmsg) | |
b80c7270 | 183 | { |
98553ad3 PB |
184 | value &= 0x1f; |
185 | return (value << 21) | insert_bab (insn, value, dialect, errmsg); | |
b80c7270 | 186 | } |
a680de9a | 187 | |
0f873fd5 | 188 | static int64_t |
98553ad3 PB |
189 | extract_btab (uint64_t insn, |
190 | ppc_cpu_t dialect, | |
b80c7270 AM |
191 | int *invalid) |
192 | { | |
98553ad3 PB |
193 | int64_t bt = (insn >> 21) & 0x1f; |
194 | int64_t bab = extract_bab (insn, dialect, invalid); | |
195 | ||
196 | if (bt != bab) | |
b80c7270 | 197 | *invalid = 1; |
98553ad3 | 198 | return bt; |
b80c7270 | 199 | } |
252b5132 | 200 | |
b80c7270 AM |
201 | /* The BD field in a B form instruction when the - modifier is used. |
202 | This modifier means that the branch is not expected to be taken. | |
203 | For chips built to versions of the architecture prior to version 2 | |
204 | (ie. not Power4 compatible), we set the y bit of the BO field to 1 | |
205 | if the offset is negative. When extracting, we require that the y | |
206 | bit be 1 and that the offset be positive, since if the y bit is 0 | |
207 | we just want to print the normal form of the instruction. | |
208 | Power4 compatible targets use two bits, "a", and "t", instead of | |
209 | the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, | |
210 | "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 | |
211 | in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 | |
212 | for branch on CTR. We only handle the taken/not-taken hint here. | |
213 | Note that we don't relax the conditions tested here when | |
214 | disassembling with -Many because insns using extract_bdm and | |
215 | extract_bdp always occur in pairs. One or the other will always | |
216 | be valid. */ | |
252b5132 | 217 | |
b80c7270 | 218 | #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
252b5132 | 219 | |
0f873fd5 PB |
220 | static uint64_t |
221 | insert_bdm (uint64_t insn, | |
222 | int64_t value, | |
b80c7270 AM |
223 | ppc_cpu_t dialect, |
224 | const char **errmsg ATTRIBUTE_UNUSED) | |
225 | { | |
226 | if ((dialect & ISA_V2) == 0) | |
227 | { | |
228 | if ((value & 0x8000) != 0) | |
229 | insn |= 1 << 21; | |
230 | } | |
231 | else | |
232 | { | |
233 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
234 | insn |= 0x02 << 21; | |
235 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
236 | insn |= 0x08 << 21; | |
237 | } | |
238 | return insn | (value & 0xfffc); | |
239 | } | |
252b5132 | 240 | |
0f873fd5 PB |
241 | static int64_t |
242 | extract_bdm (uint64_t insn, | |
b80c7270 AM |
243 | ppc_cpu_t dialect, |
244 | int *invalid) | |
245 | { | |
246 | if ((dialect & ISA_V2) == 0) | |
247 | { | |
248 | if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) | |
249 | *invalid = 1; | |
250 | } | |
251 | else | |
252 | { | |
253 | if ((insn & (0x17 << 21)) != (0x06 << 21) | |
254 | && (insn & (0x1d << 21)) != (0x18 << 21)) | |
255 | *invalid = 1; | |
256 | } | |
252b5132 | 257 | |
b80c7270 AM |
258 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
259 | } | |
989993d8 | 260 | |
b80c7270 AM |
261 | /* The BD field in a B form instruction when the + modifier is used. |
262 | This is like BDM, above, except that the branch is expected to be | |
263 | taken. */ | |
252b5132 | 264 | |
0f873fd5 PB |
265 | static uint64_t |
266 | insert_bdp (uint64_t insn, | |
267 | int64_t value, | |
b80c7270 AM |
268 | ppc_cpu_t dialect, |
269 | const char **errmsg ATTRIBUTE_UNUSED) | |
270 | { | |
271 | if ((dialect & ISA_V2) == 0) | |
272 | { | |
273 | if ((value & 0x8000) == 0) | |
274 | insn |= 1 << 21; | |
275 | } | |
276 | else | |
277 | { | |
278 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
279 | insn |= 0x03 << 21; | |
280 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
281 | insn |= 0x09 << 21; | |
282 | } | |
283 | return insn | (value & 0xfffc); | |
284 | } | |
989993d8 | 285 | |
0f873fd5 PB |
286 | static int64_t |
287 | extract_bdp (uint64_t insn, | |
b80c7270 AM |
288 | ppc_cpu_t dialect, |
289 | int *invalid) | |
290 | { | |
291 | if ((dialect & ISA_V2) == 0) | |
292 | { | |
293 | if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) | |
294 | *invalid = 1; | |
295 | } | |
296 | else | |
297 | { | |
298 | if ((insn & (0x17 << 21)) != (0x07 << 21) | |
299 | && (insn & (0x1d << 21)) != (0x19 << 21)) | |
300 | *invalid = 1; | |
301 | } | |
252b5132 | 302 | |
b80c7270 AM |
303 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
304 | } | |
252b5132 | 305 | |
b80c7270 | 306 | static inline int |
0f873fd5 | 307 | valid_bo_pre_v2 (int64_t value) |
b80c7270 AM |
308 | { |
309 | /* Certain encodings have bits that are required to be zero. | |
310 | These are (z must be zero, y may be anything): | |
311 | 0000y | |
312 | 0001y | |
313 | 001zy | |
314 | 0100y | |
315 | 0101y | |
316 | 011zy | |
317 | 1z00y | |
318 | 1z01y | |
319 | 1z1zz | |
320 | */ | |
321 | if ((value & 0x14) == 0) | |
322 | return 1; | |
323 | else if ((value & 0x14) == 0x4) | |
324 | return (value & 0x2) == 0; | |
325 | else if ((value & 0x14) == 0x10) | |
326 | return (value & 0x8) == 0; | |
327 | else | |
328 | return value == 0x14; | |
329 | } | |
989993d8 | 330 | |
b80c7270 | 331 | static inline int |
0f873fd5 | 332 | valid_bo_post_v2 (int64_t value) |
b80c7270 AM |
333 | { |
334 | /* Certain encodings have bits that are required to be zero. | |
335 | These are (z must be zero, a & t may be anything): | |
336 | 0000z | |
337 | 0001z | |
338 | 001at | |
339 | 0100z | |
340 | 0101z | |
341 | 011at | |
342 | 1a00t | |
343 | 1a01t | |
344 | 1z1zz | |
345 | */ | |
346 | if ((value & 0x14) == 0) | |
347 | return (value & 0x1) == 0; | |
348 | else if ((value & 0x14) == 0x14) | |
349 | return value == 0x14; | |
350 | else | |
351 | return 1; | |
352 | } | |
c168870a | 353 | |
b80c7270 | 354 | /* Check for legal values of a BO field. */ |
252b5132 | 355 | |
b80c7270 | 356 | static int |
0f873fd5 | 357 | valid_bo (int64_t value, ppc_cpu_t dialect, int extract) |
b80c7270 AM |
358 | { |
359 | int valid_y = valid_bo_pre_v2 (value); | |
360 | int valid_at = valid_bo_post_v2 (value); | |
b9c361e0 | 361 | |
b80c7270 AM |
362 | /* When disassembling with -Many, accept either encoding on the |
363 | second pass through opcodes. */ | |
364 | if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) | |
365 | return valid_y || valid_at; | |
366 | if ((dialect & ISA_V2) == 0) | |
367 | return valid_y; | |
368 | else | |
369 | return valid_at; | |
370 | } | |
a5721ba2 | 371 | |
b80c7270 AM |
372 | /* The BO field in a B form instruction. Warn about attempts to set |
373 | the field to an illegal value. */ | |
252b5132 | 374 | |
0f873fd5 PB |
375 | static uint64_t |
376 | insert_bo (uint64_t insn, | |
377 | int64_t value, | |
b80c7270 AM |
378 | ppc_cpu_t dialect, |
379 | const char **errmsg) | |
380 | { | |
381 | if (!valid_bo (value, dialect, 0)) | |
382 | *errmsg = _("invalid conditional option"); | |
383 | else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) | |
384 | *errmsg = _("invalid counter access"); | |
385 | return insn | ((value & 0x1f) << 21); | |
386 | } | |
a680de9a | 387 | |
0f873fd5 PB |
388 | static int64_t |
389 | extract_bo (uint64_t insn, | |
b80c7270 AM |
390 | ppc_cpu_t dialect, |
391 | int *invalid) | |
392 | { | |
0f873fd5 | 393 | int64_t value = (insn >> 21) & 0x1f; |
b80c7270 AM |
394 | if (!valid_bo (value, dialect, 1)) |
395 | *invalid = 1; | |
396 | return value; | |
397 | } | |
252b5132 | 398 | |
b80c7270 AM |
399 | /* The BO field in a B form instruction when the + or - modifier is |
400 | used. This is like the BO field, but it must be even. When | |
401 | extracting it, we force it to be even. */ | |
1ed8e1e4 | 402 | |
0f873fd5 PB |
403 | static uint64_t |
404 | insert_boe (uint64_t insn, | |
405 | int64_t value, | |
b80c7270 AM |
406 | ppc_cpu_t dialect, |
407 | const char **errmsg) | |
408 | { | |
409 | if (!valid_bo (value, dialect, 0)) | |
410 | *errmsg = _("invalid conditional option"); | |
411 | else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) | |
412 | *errmsg = _("invalid counter access"); | |
413 | else if ((value & 1) != 0) | |
414 | *errmsg = _("attempt to set y bit when using + or - modifier"); | |
252b5132 | 415 | |
b80c7270 AM |
416 | return insn | ((value & 0x1f) << 21); |
417 | } | |
252b5132 | 418 | |
0f873fd5 PB |
419 | static int64_t |
420 | extract_boe (uint64_t insn, | |
b80c7270 AM |
421 | ppc_cpu_t dialect, |
422 | int *invalid) | |
423 | { | |
0f873fd5 | 424 | int64_t value = (insn >> 21) & 0x1f; |
b80c7270 AM |
425 | if (!valid_bo (value, dialect, 1)) |
426 | *invalid = 1; | |
427 | return value & 0x1e; | |
428 | } | |
252b5132 | 429 | |
b80c7270 AM |
430 | /* The DCMX field in a X form instruction when the field is split |
431 | into separate DC, DM and DX fields. */ | |
252b5132 | 432 | |
0f873fd5 PB |
433 | static uint64_t |
434 | insert_dcmxs (uint64_t insn, | |
435 | int64_t value, | |
b80c7270 AM |
436 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
437 | const char **errmsg ATTRIBUTE_UNUSED) | |
438 | { | |
439 | return (insn | |
440 | | ((value & 0x1f) << 16) | |
441 | | ((value & 0x20) >> 3) | |
442 | | (value & 0x40)); | |
443 | } | |
252b5132 | 444 | |
0f873fd5 PB |
445 | static int64_t |
446 | extract_dcmxs (uint64_t insn, | |
b80c7270 AM |
447 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
448 | int *invalid ATTRIBUTE_UNUSED) | |
449 | { | |
450 | return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); | |
451 | } | |
252b5132 | 452 | |
b80c7270 AM |
453 | /* The D field in a DX form instruction when the field is split |
454 | into separate D0, D1 and D2 fields. */ | |
989993d8 | 455 | |
0f873fd5 PB |
456 | static uint64_t |
457 | insert_dxd (uint64_t insn, | |
458 | int64_t value, | |
b80c7270 AM |
459 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
460 | const char **errmsg ATTRIBUTE_UNUSED) | |
461 | { | |
462 | return insn | (value & 0xffc1) | ((value & 0x3e) << 15); | |
463 | } | |
e43de63c | 464 | |
0f873fd5 PB |
465 | static int64_t |
466 | extract_dxd (uint64_t insn, | |
b80c7270 AM |
467 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
468 | int *invalid ATTRIBUTE_UNUSED) | |
469 | { | |
0f873fd5 | 470 | uint64_t dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); |
b80c7270 AM |
471 | return (dxd ^ 0x8000) - 0x8000; |
472 | } | |
252b5132 | 473 | |
0f873fd5 PB |
474 | static uint64_t |
475 | insert_dxdn (uint64_t insn, | |
476 | int64_t value, | |
b80c7270 AM |
477 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
478 | const char **errmsg ATTRIBUTE_UNUSED) | |
479 | { | |
480 | return insert_dxd (insn, -value, dialect, errmsg); | |
481 | } | |
252b5132 | 482 | |
0f873fd5 PB |
483 | static int64_t |
484 | extract_dxdn (uint64_t insn, | |
b80c7270 | 485 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
9cf7e568 | 486 | int *invalid) |
b80c7270 AM |
487 | { |
488 | return -extract_dxd (insn, dialect, invalid); | |
489 | } | |
fdd12ef3 | 490 | |
b80c7270 | 491 | /* FXM mask in mfcr and mtcrf instructions. */ |
adadcc0c | 492 | |
0f873fd5 PB |
493 | static uint64_t |
494 | insert_fxm (uint64_t insn, | |
495 | int64_t value, | |
b80c7270 AM |
496 | ppc_cpu_t dialect, |
497 | const char **errmsg) | |
498 | { | |
499 | /* If we're handling the mfocrf and mtocrf insns ensure that exactly | |
500 | one bit of the mask field is set. */ | |
501 | if ((insn & (1 << 20)) != 0) | |
502 | { | |
503 | if (value == 0 || (value & -value) != value) | |
504 | { | |
505 | *errmsg = _("invalid mask field"); | |
506 | value = 0; | |
507 | } | |
508 | } | |
252b5132 | 509 | |
b80c7270 AM |
510 | /* If only one bit of the FXM field is set, we can use the new form |
511 | of the instruction, which is faster. Unlike the Power4 branch hint | |
512 | encoding, this is not backward compatible. Do not generate the | |
513 | new form unless -mpower4 has been given, or -many and the two | |
514 | operand form of mfcr was used. */ | |
515 | else if (value > 0 | |
516 | && (value & -value) == value | |
517 | && ((dialect & PPC_OPCODE_POWER4) != 0 | |
518 | || ((dialect & PPC_OPCODE_ANY) != 0 | |
519 | && (insn & (0x3ff << 1)) == 19 << 1))) | |
520 | insn |= 1 << 20; | |
252b5132 | 521 | |
b80c7270 AM |
522 | /* Any other value on mfcr is an error. */ |
523 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
524 | { | |
525 | /* A value of -1 means we used the one operand form of | |
526 | mfcr which is valid. */ | |
527 | if (value != -1) | |
528 | *errmsg = _("invalid mfcr mask"); | |
529 | value = 0; | |
530 | } | |
252b5132 | 531 | |
b80c7270 AM |
532 | return insn | ((value & 0xff) << 12); |
533 | } | |
1f6c9eb0 | 534 | |
0f873fd5 PB |
535 | static int64_t |
536 | extract_fxm (uint64_t insn, | |
b80c7270 AM |
537 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
538 | int *invalid) | |
539 | { | |
9cf7e568 AM |
540 | /* Return a value of -1 for a missing optional operand, which is |
541 | used as a flag by insert_fxm. */ | |
542 | if (*invalid < 0) | |
543 | return -1; | |
252b5132 | 544 | |
9cf7e568 | 545 | int64_t mask = (insn >> 12) & 0xff; |
b80c7270 AM |
546 | /* Is this a Power4 insn? */ |
547 | if ((insn & (1 << 20)) != 0) | |
548 | { | |
549 | /* Exactly one bit of MASK should be set. */ | |
550 | if (mask == 0 || (mask & -mask) != mask) | |
551 | *invalid = 1; | |
552 | } | |
252b5132 | 553 | |
b80c7270 AM |
554 | /* Check that non-power4 form of mfcr has a zero MASK. */ |
555 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
556 | { | |
557 | if (mask != 0) | |
558 | *invalid = 1; | |
559 | else | |
560 | mask = -1; | |
561 | } | |
989993d8 | 562 | |
b80c7270 AM |
563 | return mask; |
564 | } | |
cee62821 | 565 | |
0f873fd5 PB |
566 | static uint64_t |
567 | insert_li20 (uint64_t insn, | |
568 | int64_t value, | |
b80c7270 AM |
569 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
570 | const char **errmsg ATTRIBUTE_UNUSED) | |
571 | { | |
572 | return (insn | |
573 | | ((value & 0xf0000) >> 5) | |
574 | | ((value & 0x0f800) << 5) | |
575 | | (value & 0x7ff)); | |
576 | } | |
a680de9a | 577 | |
0f873fd5 PB |
578 | static int64_t |
579 | extract_li20 (uint64_t insn, | |
b80c7270 AM |
580 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
581 | int *invalid ATTRIBUTE_UNUSED) | |
582 | { | |
f143cb5f AM |
583 | return ((((insn << 5) & 0xf0000) |
584 | | ((insn >> 5) & 0xf800) | |
585 | | (insn & 0x7ff)) ^ 0x80000) - 0x80000; | |
b80c7270 | 586 | } |
e3c2f928 | 587 | |
b80c7270 AM |
588 | /* The 2-bit L field in a SYNC or WC field in a WAIT instruction. |
589 | For SYNC, some L values are reserved: | |
590 | * Value 3 is reserved on newer server cpus. | |
591 | * Values 2 and 3 are reserved on all other cpus. */ | |
adadcc0c | 592 | |
0f873fd5 PB |
593 | static uint64_t |
594 | insert_ls (uint64_t insn, | |
595 | int64_t value, | |
b80c7270 AM |
596 | ppc_cpu_t dialect, |
597 | const char **errmsg) | |
598 | { | |
599 | /* For SYNC, some L values are illegal. */ | |
600 | if (((insn >> 1) & 0x3ff) == 598) | |
601 | { | |
0f873fd5 | 602 | int64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; |
b80c7270 AM |
603 | if (value > max_lvalue) |
604 | { | |
605 | *errmsg = _("illegal L operand value"); | |
606 | return insn; | |
607 | } | |
608 | } | |
1f6c9eb0 | 609 | |
b80c7270 AM |
610 | return insn | ((value & 0x3) << 21); |
611 | } | |
b9c361e0 | 612 | |
0f873fd5 PB |
613 | static int64_t |
614 | extract_ls (uint64_t insn, | |
b80c7270 AM |
615 | ppc_cpu_t dialect, |
616 | int *invalid) | |
617 | { | |
9cf7e568 AM |
618 | /* Missing optional operands have a value of zero. */ |
619 | if (*invalid < 0) | |
620 | return 0; | |
b9c361e0 | 621 | |
9cf7e568 | 622 | uint64_t lvalue = (insn >> 21) & 3; |
b80c7270 AM |
623 | if (((insn >> 1) & 0x3ff) == 598) |
624 | { | |
0f873fd5 | 625 | uint64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; |
b80c7270 AM |
626 | if (lvalue > max_lvalue) |
627 | *invalid = 1; | |
628 | } | |
629 | return lvalue; | |
630 | } | |
b9c361e0 | 631 | |
b80c7270 AM |
632 | /* The 4-bit E field in a sync instruction that accepts 2 operands. |
633 | If ESYNC is non-zero, then the L field must be either 0 or 1 and | |
634 | the complement of ESYNC-bit2. */ | |
b9c361e0 | 635 | |
0f873fd5 PB |
636 | static uint64_t |
637 | insert_esync (uint64_t insn, | |
638 | int64_t value, | |
9cf7e568 | 639 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 AM |
640 | const char **errmsg) |
641 | { | |
0f873fd5 | 642 | uint64_t ls = (insn >> 21) & 0x03; |
b9c361e0 | 643 | |
9cf7e568 AM |
644 | if (value != 0 |
645 | && ((~value >> 1) & 0x1) != ls) | |
b80c7270 | 646 | *errmsg = _("incompatible L operand value"); |
b9c361e0 | 647 | |
b80c7270 AM |
648 | return insn | ((value & 0xf) << 16); |
649 | } | |
b9c361e0 | 650 | |
0f873fd5 PB |
651 | static int64_t |
652 | extract_esync (uint64_t insn, | |
9cf7e568 | 653 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 AM |
654 | int *invalid) |
655 | { | |
9cf7e568 AM |
656 | if (*invalid < 0) |
657 | return 0; | |
b9c361e0 | 658 | |
9cf7e568 AM |
659 | uint64_t ls = (insn >> 21) & 0x3; |
660 | uint64_t value = (insn >> 16) & 0xf; | |
661 | if (value != 0 | |
662 | && ((~value >> 1) & 0x1) != ls) | |
b80c7270 | 663 | *invalid = 1; |
9cf7e568 | 664 | return value; |
b80c7270 | 665 | } |
e3c2f928 | 666 | |
b80c7270 AM |
667 | /* The MB and ME fields in an M form instruction expressed as a single |
668 | operand which is itself a bitmask. The extraction function always | |
669 | marks it as invalid, since we never want to recognize an | |
670 | instruction which uses a field of this type. */ | |
5817ffd1 | 671 | |
0f873fd5 PB |
672 | static uint64_t |
673 | insert_mbe (uint64_t insn, | |
674 | int64_t value, | |
b80c7270 AM |
675 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
676 | const char **errmsg) | |
677 | { | |
0f873fd5 PB |
678 | uint64_t uval, mask; |
679 | long mb, me, mx, count, last; | |
252b5132 | 680 | |
b80c7270 | 681 | uval = value; |
1f6c9eb0 | 682 | |
b80c7270 AM |
683 | if (uval == 0) |
684 | { | |
685 | *errmsg = _("illegal bitmask"); | |
686 | return insn; | |
687 | } | |
252b5132 | 688 | |
b80c7270 AM |
689 | mb = 0; |
690 | me = 32; | |
691 | if ((uval & 1) != 0) | |
692 | last = 1; | |
693 | else | |
694 | last = 0; | |
695 | count = 0; | |
252b5132 | 696 | |
b80c7270 AM |
697 | /* mb: location of last 0->1 transition */ |
698 | /* me: location of last 1->0 transition */ | |
699 | /* count: # transitions */ | |
b9c361e0 | 700 | |
0f873fd5 | 701 | for (mx = 0, mask = (uint64_t) 1 << 31; mx < 32; ++mx, mask >>= 1) |
b80c7270 AM |
702 | { |
703 | if ((uval & mask) && !last) | |
704 | { | |
705 | ++count; | |
706 | mb = mx; | |
707 | last = 1; | |
708 | } | |
709 | else if (!(uval & mask) && last) | |
710 | { | |
711 | ++count; | |
712 | me = mx; | |
713 | last = 0; | |
714 | } | |
715 | } | |
716 | if (me == 0) | |
717 | me = 32; | |
252b5132 | 718 | |
b80c7270 AM |
719 | if (count != 2 && (count != 0 || ! last)) |
720 | *errmsg = _("illegal bitmask"); | |
252b5132 | 721 | |
b80c7270 AM |
722 | return insn | (mb << 6) | ((me - 1) << 1); |
723 | } | |
252b5132 | 724 | |
0f873fd5 PB |
725 | static int64_t |
726 | extract_mbe (uint64_t insn, | |
b80c7270 AM |
727 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
728 | int *invalid) | |
729 | { | |
0f873fd5 PB |
730 | int64_t ret; |
731 | long mb, me; | |
732 | long i; | |
252b5132 | 733 | |
b80c7270 | 734 | *invalid = 1; |
f5c120c5 | 735 | |
b80c7270 AM |
736 | mb = (insn >> 6) & 0x1f; |
737 | me = (insn >> 1) & 0x1f; | |
738 | if (mb < me + 1) | |
739 | { | |
740 | ret = 0; | |
741 | for (i = mb; i <= me; i++) | |
0f873fd5 | 742 | ret |= (uint64_t) 1 << (31 - i); |
b80c7270 AM |
743 | } |
744 | else if (mb == me + 1) | |
745 | ret = ~0; | |
746 | else /* (mb > me + 1) */ | |
747 | { | |
748 | ret = ~0; | |
749 | for (i = me + 1; i < mb; i++) | |
0f873fd5 | 750 | ret &= ~((uint64_t) 1 << (31 - i)); |
b80c7270 AM |
751 | } |
752 | return ret; | |
753 | } | |
aea77599 | 754 | |
b80c7270 AM |
755 | /* The MB or ME field in an MD or MDS form instruction. The high bit |
756 | is wrapped to the low end. */ | |
252b5132 | 757 | |
0f873fd5 PB |
758 | static uint64_t |
759 | insert_mb6 (uint64_t insn, | |
760 | int64_t value, | |
b80c7270 AM |
761 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
762 | const char **errmsg ATTRIBUTE_UNUSED) | |
763 | { | |
764 | return insn | ((value & 0x1f) << 6) | (value & 0x20); | |
765 | } | |
252b5132 | 766 | |
0f873fd5 PB |
767 | static int64_t |
768 | extract_mb6 (uint64_t insn, | |
b80c7270 AM |
769 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
770 | int *invalid ATTRIBUTE_UNUSED) | |
771 | { | |
772 | return ((insn >> 6) & 0x1f) | (insn & 0x20); | |
773 | } | |
252b5132 | 774 | |
b80c7270 AM |
775 | /* The NB field in an X form instruction. The value 32 is stored as |
776 | 0. */ | |
786e2c0f | 777 | |
0f873fd5 PB |
778 | static int64_t |
779 | extract_nb (uint64_t insn, | |
b80c7270 AM |
780 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
781 | int *invalid ATTRIBUTE_UNUSED) | |
782 | { | |
0f873fd5 | 783 | int64_t ret; |
a47622ac | 784 | |
b80c7270 AM |
785 | ret = (insn >> 11) & 0x1f; |
786 | if (ret == 0) | |
787 | ret = 32; | |
788 | return ret; | |
789 | } | |
b9c361e0 | 790 | |
b80c7270 AM |
791 | /* The NB field in an lswi instruction, which has special value |
792 | restrictions. The value 32 is stored as 0. */ | |
b9c361e0 | 793 | |
0f873fd5 PB |
794 | static uint64_t |
795 | insert_nbi (uint64_t insn, | |
796 | int64_t value, | |
b80c7270 AM |
797 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
798 | const char **errmsg ATTRIBUTE_UNUSED) | |
799 | { | |
0f873fd5 PB |
800 | int64_t rtvalue = (insn >> 21) & 0x1f; |
801 | int64_t ravalue = (insn >> 16) & 0x1f; | |
b9c361e0 | 802 | |
b80c7270 AM |
803 | if (value == 0) |
804 | value = 32; | |
805 | if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 | |
806 | : ravalue)) | |
807 | *errmsg = _("address register in load range"); | |
808 | return insn | ((value & 0x1f) << 11); | |
809 | } | |
786e2c0f | 810 | |
b80c7270 AM |
811 | /* The NSI field in a D form instruction. This is the same as the SI |
812 | field, only negated. The extraction function always marks it as | |
813 | invalid, since we never want to recognize an instruction which uses | |
814 | a field of this type. */ | |
786e2c0f | 815 | |
0f873fd5 PB |
816 | static uint64_t |
817 | insert_nsi (uint64_t insn, | |
818 | int64_t value, | |
b80c7270 AM |
819 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
820 | const char **errmsg ATTRIBUTE_UNUSED) | |
821 | { | |
822 | return insn | (-value & 0xffff); | |
823 | } | |
786e2c0f | 824 | |
0f873fd5 PB |
825 | static int64_t |
826 | extract_nsi (uint64_t insn, | |
b80c7270 AM |
827 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
828 | int *invalid) | |
829 | { | |
830 | *invalid = 1; | |
831 | return -(((insn & 0xffff) ^ 0x8000) - 0x8000); | |
832 | } | |
786e2c0f | 833 | |
b80c7270 AM |
834 | /* The RA field in a D or X form instruction which is an updating |
835 | load, which means that the RA field may not be zero and may not | |
836 | equal the RT field. */ | |
786e2c0f | 837 | |
0f873fd5 PB |
838 | static uint64_t |
839 | insert_ral (uint64_t insn, | |
840 | int64_t value, | |
b80c7270 AM |
841 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
842 | const char **errmsg) | |
843 | { | |
844 | if (value == 0 | |
0f873fd5 | 845 | || (uint64_t) value == ((insn >> 21) & 0x1f)) |
b80c7270 AM |
846 | *errmsg = "invalid register operand when updating"; |
847 | return insn | ((value & 0x1f) << 16); | |
848 | } | |
786e2c0f | 849 | |
0f873fd5 PB |
850 | static int64_t |
851 | extract_ral (uint64_t insn, | |
b80c7270 AM |
852 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
853 | int *invalid) | |
854 | { | |
0f873fd5 PB |
855 | int64_t rtvalue = (insn >> 21) & 0x1f; |
856 | int64_t ravalue = (insn >> 16) & 0x1f; | |
fb048c26 | 857 | |
b80c7270 AM |
858 | if (rtvalue == ravalue || ravalue == 0) |
859 | *invalid = 1; | |
860 | return ravalue; | |
861 | } | |
a680de9a | 862 | |
b80c7270 AM |
863 | /* The RA field in an lmw instruction, which has special value |
864 | restrictions. */ | |
c0637f3a | 865 | |
0f873fd5 PB |
866 | static uint64_t |
867 | insert_ram (uint64_t insn, | |
868 | int64_t value, | |
b80c7270 AM |
869 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
870 | const char **errmsg) | |
871 | { | |
0f873fd5 | 872 | if ((uint64_t) value >= ((insn >> 21) & 0x1f)) |
b80c7270 AM |
873 | *errmsg = _("index register in load range"); |
874 | return insn | ((value & 0x1f) << 16); | |
875 | } | |
c0637f3a | 876 | |
0f873fd5 PB |
877 | static int64_t |
878 | extract_ram (uint64_t insn, | |
b80c7270 AM |
879 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
880 | int *invalid) | |
881 | { | |
0f873fd5 PB |
882 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
883 | uint64_t ravalue = (insn >> 16) & 0x1f; | |
ff3a6ee3 | 884 | |
b80c7270 AM |
885 | if (ravalue >= rtvalue) |
886 | *invalid = 1; | |
887 | return ravalue; | |
888 | } | |
23976049 | 889 | |
b80c7270 AM |
890 | /* The RA field in the DQ form lq or an lswx instruction, which have special |
891 | value restrictions. */ | |
e3c2f928 | 892 | |
0f873fd5 PB |
893 | static uint64_t |
894 | insert_raq (uint64_t insn, | |
895 | int64_t value, | |
b80c7270 AM |
896 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
897 | const char **errmsg) | |
898 | { | |
0f873fd5 | 899 | int64_t rtvalue = (insn >> 21) & 0x1f; |
23976049 | 900 | |
b80c7270 AM |
901 | if (value == rtvalue) |
902 | *errmsg = _("source and target register operands must be different"); | |
903 | return insn | ((value & 0x1f) << 16); | |
904 | } | |
e3c2f928 | 905 | |
0f873fd5 PB |
906 | static int64_t |
907 | extract_raq (uint64_t insn, | |
b80c7270 AM |
908 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
909 | int *invalid) | |
910 | { | |
9cf7e568 AM |
911 | if (*invalid < 0) |
912 | return 0; | |
913 | ||
0f873fd5 PB |
914 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
915 | uint64_t ravalue = (insn >> 16) & 0x1f; | |
b80c7270 AM |
916 | if (ravalue == rtvalue) |
917 | *invalid = 1; | |
918 | return ravalue; | |
919 | } | |
e3c2f928 | 920 | |
b80c7270 AM |
921 | /* The RA field in a D or X form instruction which is an updating |
922 | store or an updating floating point load, which means that the RA | |
923 | field may not be zero. */ | |
ff3a6ee3 | 924 | |
0f873fd5 PB |
925 | static uint64_t |
926 | insert_ras (uint64_t insn, | |
927 | int64_t value, | |
b80c7270 AM |
928 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
929 | const char **errmsg) | |
930 | { | |
931 | if (value == 0) | |
932 | *errmsg = _("invalid register operand when updating"); | |
933 | return insn | ((value & 0x1f) << 16); | |
934 | } | |
c3d65c1c | 935 | |
0f873fd5 PB |
936 | static int64_t |
937 | extract_ras (uint64_t insn, | |
b80c7270 AM |
938 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
939 | int *invalid) | |
940 | { | |
0f873fd5 | 941 | uint64_t ravalue = (insn >> 16) & 0x1f; |
c3d65c1c | 942 | |
b80c7270 AM |
943 | if (ravalue == 0) |
944 | *invalid = 1; | |
945 | return ravalue; | |
946 | } | |
c3d65c1c | 947 | |
98553ad3 PB |
948 | /* The RS and RB fields in an X form instruction when they must be the same. |
949 | This is used for extended mnemonics like mr. The extraction function | |
950 | enforces that the fields are the same. */ | |
c3d65c1c | 951 | |
0f873fd5 | 952 | static uint64_t |
98553ad3 PB |
953 | insert_rsb (uint64_t insn, |
954 | int64_t value, | |
b80c7270 AM |
955 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
956 | const char **errmsg ATTRIBUTE_UNUSED) | |
957 | { | |
98553ad3 PB |
958 | value &= 0x1f; |
959 | return insn | (value << 21) | (value << 11); | |
b80c7270 | 960 | } |
5ae2e65e | 961 | |
0f873fd5 | 962 | static int64_t |
98553ad3 | 963 | extract_rsb (uint64_t insn, |
b80c7270 AM |
964 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
965 | int *invalid) | |
966 | { | |
98553ad3 PB |
967 | int64_t rs = (insn >> 21) & 0x1f; |
968 | int64_t rb = (insn >> 11) & 0x1f; | |
969 | ||
970 | if (rs != rb) | |
b80c7270 | 971 | *invalid = 1; |
98553ad3 | 972 | return rs; |
b80c7270 | 973 | } |
702f0fb4 | 974 | |
b80c7270 AM |
975 | /* The RB field in an lswx instruction, which has special value |
976 | restrictions. */ | |
702f0fb4 | 977 | |
0f873fd5 PB |
978 | static uint64_t |
979 | insert_rbx (uint64_t insn, | |
980 | int64_t value, | |
b80c7270 AM |
981 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
982 | const char **errmsg) | |
983 | { | |
0f873fd5 | 984 | int64_t rtvalue = (insn >> 21) & 0x1f; |
a680de9a | 985 | |
b80c7270 AM |
986 | if (value == rtvalue) |
987 | *errmsg = _("source and target register operands must be different"); | |
988 | return insn | ((value & 0x1f) << 11); | |
989 | } | |
a680de9a | 990 | |
0f873fd5 PB |
991 | static int64_t |
992 | extract_rbx (uint64_t insn, | |
b80c7270 AM |
993 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
994 | int *invalid) | |
995 | { | |
0f873fd5 PB |
996 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
997 | uint64_t rbvalue = (insn >> 11) & 0x1f; | |
702f0fb4 | 998 | |
b80c7270 AM |
999 | if (rbvalue == rtvalue) |
1000 | *invalid = 1; | |
1001 | return rbvalue; | |
1002 | } | |
702f0fb4 | 1003 | |
b80c7270 | 1004 | /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ |
0f873fd5 PB |
1005 | static uint64_t |
1006 | insert_sci8 (uint64_t insn, | |
1007 | int64_t value, | |
b80c7270 AM |
1008 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1009 | const char **errmsg) | |
1010 | { | |
0f873fd5 PB |
1011 | uint64_t fill_scale = 0; |
1012 | uint64_t ui8 = value; | |
c0637f3a | 1013 | |
b80c7270 AM |
1014 | if ((ui8 & 0xffffff00) == 0) |
1015 | ; | |
1016 | else if ((ui8 & 0xffffff00) == 0xffffff00) | |
1017 | fill_scale = 0x400; | |
1018 | else if ((ui8 & 0xffff00ff) == 0) | |
1019 | { | |
1020 | fill_scale = 1 << 8; | |
1021 | ui8 >>= 8; | |
1022 | } | |
1023 | else if ((ui8 & 0xffff00ff) == 0xffff00ff) | |
1024 | { | |
1025 | fill_scale = 0x400 | (1 << 8); | |
1026 | ui8 >>= 8; | |
1027 | } | |
1028 | else if ((ui8 & 0xff00ffff) == 0) | |
1029 | { | |
1030 | fill_scale = 2 << 8; | |
1031 | ui8 >>= 16; | |
1032 | } | |
1033 | else if ((ui8 & 0xff00ffff) == 0xff00ffff) | |
1034 | { | |
1035 | fill_scale = 0x400 | (2 << 8); | |
1036 | ui8 >>= 16; | |
1037 | } | |
1038 | else if ((ui8 & 0x00ffffff) == 0) | |
1039 | { | |
1040 | fill_scale = 3 << 8; | |
1041 | ui8 >>= 24; | |
1042 | } | |
1043 | else if ((ui8 & 0x00ffffff) == 0x00ffffff) | |
1044 | { | |
1045 | fill_scale = 0x400 | (3 << 8); | |
1046 | ui8 >>= 24; | |
1047 | } | |
1048 | else | |
1049 | { | |
1050 | *errmsg = _("illegal immediate value"); | |
1051 | ui8 = 0; | |
1052 | } | |
702f0fb4 | 1053 | |
b80c7270 AM |
1054 | return insn | fill_scale | (ui8 & 0xff); |
1055 | } | |
ea192fa3 | 1056 | |
0f873fd5 PB |
1057 | static int64_t |
1058 | extract_sci8 (uint64_t insn, | |
b80c7270 AM |
1059 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1060 | int *invalid ATTRIBUTE_UNUSED) | |
1061 | { | |
0f873fd5 PB |
1062 | int64_t fill = insn & 0x400; |
1063 | int64_t scale_factor = (insn & 0x300) >> 5; | |
1064 | int64_t value = (insn & 0xff) << scale_factor; | |
081ba1b3 | 1065 | |
b80c7270 | 1066 | if (fill != 0) |
0f873fd5 | 1067 | value |= ~((int64_t) 0xff << scale_factor); |
b80c7270 AM |
1068 | return value; |
1069 | } | |
081ba1b3 | 1070 | |
0f873fd5 PB |
1071 | static uint64_t |
1072 | insert_sci8n (uint64_t insn, | |
1073 | int64_t value, | |
b80c7270 AM |
1074 | ppc_cpu_t dialect, |
1075 | const char **errmsg) | |
1076 | { | |
1077 | return insert_sci8 (insn, -value, dialect, errmsg); | |
1078 | } | |
081ba1b3 | 1079 | |
0f873fd5 PB |
1080 | static int64_t |
1081 | extract_sci8n (uint64_t insn, | |
b80c7270 AM |
1082 | ppc_cpu_t dialect, |
1083 | int *invalid) | |
1084 | { | |
1085 | return -extract_sci8 (insn, dialect, invalid); | |
1086 | } | |
081ba1b3 | 1087 | |
0f873fd5 PB |
1088 | static uint64_t |
1089 | insert_sd4h (uint64_t insn, | |
1090 | int64_t value, | |
b80c7270 AM |
1091 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1092 | const char **errmsg ATTRIBUTE_UNUSED) | |
1093 | { | |
1094 | return insn | ((value & 0x1e) << 7); | |
1095 | } | |
081ba1b3 | 1096 | |
0f873fd5 PB |
1097 | static int64_t |
1098 | extract_sd4h (uint64_t insn, | |
b80c7270 AM |
1099 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1100 | int *invalid ATTRIBUTE_UNUSED) | |
1101 | { | |
1102 | return ((insn >> 8) & 0xf) << 1; | |
1103 | } | |
081ba1b3 | 1104 | |
0f873fd5 PB |
1105 | static uint64_t |
1106 | insert_sd4w (uint64_t insn, | |
1107 | int64_t value, | |
b80c7270 AM |
1108 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1109 | const char **errmsg ATTRIBUTE_UNUSED) | |
1110 | { | |
1111 | return insn | ((value & 0x3c) << 6); | |
1112 | } | |
081ba1b3 | 1113 | |
0f873fd5 PB |
1114 | static int64_t |
1115 | extract_sd4w (uint64_t insn, | |
b80c7270 AM |
1116 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1117 | int *invalid ATTRIBUTE_UNUSED) | |
1118 | { | |
1119 | return ((insn >> 8) & 0xf) << 2; | |
1120 | } | |
b9c361e0 | 1121 | |
0f873fd5 PB |
1122 | static uint64_t |
1123 | insert_oimm (uint64_t insn, | |
1124 | int64_t value, | |
b80c7270 AM |
1125 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1126 | const char **errmsg ATTRIBUTE_UNUSED) | |
1127 | { | |
1128 | return insn | (((value - 1) & 0x1f) << 4); | |
1129 | } | |
b9c361e0 | 1130 | |
0f873fd5 PB |
1131 | static int64_t |
1132 | extract_oimm (uint64_t insn, | |
b80c7270 AM |
1133 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1134 | int *invalid ATTRIBUTE_UNUSED) | |
1135 | { | |
1136 | return ((insn >> 4) & 0x1f) + 1; | |
1137 | } | |
b9c361e0 | 1138 | |
b80c7270 | 1139 | /* The SH field in an MD form instruction. This is split. */ |
b9c361e0 | 1140 | |
0f873fd5 PB |
1141 | static uint64_t |
1142 | insert_sh6 (uint64_t insn, | |
1143 | int64_t value, | |
b80c7270 AM |
1144 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1145 | const char **errmsg ATTRIBUTE_UNUSED) | |
1146 | { | |
1147 | /* SH6 operand in the rldixor instructions. */ | |
1148 | if (PPC_OP (insn) == 4) | |
1149 | return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5); | |
1150 | else | |
1151 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); | |
1152 | } | |
9b4e5766 | 1153 | |
0f873fd5 PB |
1154 | static int64_t |
1155 | extract_sh6 (uint64_t insn, | |
b80c7270 AM |
1156 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1157 | int *invalid ATTRIBUTE_UNUSED) | |
1158 | { | |
1159 | /* SH6 operand in the rldixor instructions. */ | |
1160 | if (PPC_OP (insn) == 4) | |
1161 | return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20); | |
1162 | else | |
1163 | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); | |
1164 | } | |
a680de9a | 1165 | |
b80c7270 AM |
1166 | /* The SPR field in an XFX form instruction. This is flipped--the |
1167 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
9b4e5766 | 1168 | |
0f873fd5 PB |
1169 | static uint64_t |
1170 | insert_spr (uint64_t insn, | |
1171 | int64_t value, | |
b80c7270 AM |
1172 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1173 | const char **errmsg ATTRIBUTE_UNUSED) | |
1174 | { | |
1175 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1176 | } | |
9b4e5766 | 1177 | |
0f873fd5 PB |
1178 | static int64_t |
1179 | extract_spr (uint64_t insn, | |
b80c7270 AM |
1180 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1181 | int *invalid ATTRIBUTE_UNUSED) | |
1182 | { | |
1183 | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); | |
1184 | } | |
9b4e5766 | 1185 | |
fa758a70 AC |
1186 | /* Some dialects have 8 [DI]BAT registers instead of the standard 4. */ |
1187 | #define ALLOW8_BAT (PPC_OPCODE_750) | |
1188 | ||
16065af1 AM |
1189 | static uint64_t |
1190 | insert_sprbat (uint64_t insn, | |
1191 | int64_t value, | |
fa758a70 AC |
1192 | ppc_cpu_t dialect, |
1193 | const char **errmsg) | |
1194 | { | |
1195 | if (value > 7 | |
1196 | || (value > 3 && (dialect & ALLOW8_BAT) == 0)) | |
1197 | *errmsg = _("invalid bat number"); | |
1198 | ||
1199 | /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */ | |
1200 | if (value > 3) | |
1201 | value = ((value & 3) << 6) | 1; | |
1202 | else | |
1203 | value = value << 6; | |
1204 | ||
1205 | return insn | (value << 11); | |
1206 | } | |
1207 | ||
16065af1 AM |
1208 | static int64_t |
1209 | extract_sprbat (uint64_t insn, | |
fa758a70 AC |
1210 | ppc_cpu_t dialect, |
1211 | int *invalid) | |
1212 | { | |
16065af1 | 1213 | uint64_t val = (insn >> 17) & 0x3; |
fa758a70 AC |
1214 | |
1215 | val = val + ((insn >> 9) & 0x4); | |
1216 | if (val > 3 && (dialect & ALLOW8_BAT) == 0) | |
1217 | *invalid = 1; | |
1218 | return val; | |
1219 | } | |
1220 | ||
b80c7270 AM |
1221 | /* Some dialects have 8 SPRG registers instead of the standard 4. */ |
1222 | #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) | |
066be9f7 | 1223 | |
0f873fd5 PB |
1224 | static uint64_t |
1225 | insert_sprg (uint64_t insn, | |
1226 | int64_t value, | |
b80c7270 AM |
1227 | ppc_cpu_t dialect, |
1228 | const char **errmsg) | |
1229 | { | |
1230 | if (value > 7 | |
1231 | || (value > 3 && (dialect & ALLOW8_SPRG) == 0)) | |
1232 | *errmsg = _("invalid sprg number"); | |
066be9f7 | 1233 | |
b80c7270 AM |
1234 | /* If this is mfsprg4..7 then use spr 260..263 which can be read in |
1235 | user mode. Anything else must use spr 272..279. */ | |
1236 | if (value <= 3 || (insn & 0x100) != 0) | |
1237 | value |= 0x10; | |
066be9f7 | 1238 | |
b80c7270 AM |
1239 | return insn | ((value & 0x17) << 16); |
1240 | } | |
e0d602ec | 1241 | |
0f873fd5 PB |
1242 | static int64_t |
1243 | extract_sprg (uint64_t insn, | |
b80c7270 AM |
1244 | ppc_cpu_t dialect, |
1245 | int *invalid) | |
1246 | { | |
0f873fd5 | 1247 | uint64_t val = (insn >> 16) & 0x1f; |
4bc0608a | 1248 | |
b80c7270 AM |
1249 | /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 |
1250 | If not BOOKE, 405 or VLE, then both use only 272..275. */ | |
1251 | if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) | |
1252 | || (val - 0x10 > 7 && (insn & 0x100) != 0) | |
1253 | || val <= 3 | |
1254 | || (val & 8) != 0) | |
1255 | *invalid = 1; | |
1256 | return val & 7; | |
1257 | } | |
a680de9a | 1258 | |
b80c7270 AM |
1259 | /* The TBR field in an XFX instruction. This is just like SPR, but it |
1260 | is optional. */ | |
e3c2f928 | 1261 | |
0f873fd5 PB |
1262 | static uint64_t |
1263 | insert_tbr (uint64_t insn, | |
1264 | int64_t value, | |
b80c7270 AM |
1265 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1266 | const char **errmsg) | |
1267 | { | |
1268 | if (value != 268 && value != 269) | |
1269 | *errmsg = _("invalid tbr number"); | |
1270 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1271 | } | |
252b5132 | 1272 | |
0f873fd5 PB |
1273 | static int64_t |
1274 | extract_tbr (uint64_t insn, | |
b80c7270 AM |
1275 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1276 | int *invalid) | |
1277 | { | |
9cf7e568 AM |
1278 | if (*invalid < 0) |
1279 | return 268; | |
1280 | ||
0f873fd5 | 1281 | int64_t ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
b80c7270 AM |
1282 | if (ret != 268 && ret != 269) |
1283 | *invalid = 1; | |
1284 | return ret; | |
1285 | } | |
252b5132 | 1286 | |
b80c7270 | 1287 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
b9c361e0 | 1288 | |
0f873fd5 PB |
1289 | static uint64_t |
1290 | insert_xt6 (uint64_t insn, | |
1291 | int64_t value, | |
b9c361e0 JL |
1292 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1293 | const char **errmsg ATTRIBUTE_UNUSED) | |
1294 | { | |
b80c7270 | 1295 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); |
b9c361e0 JL |
1296 | } |
1297 | ||
0f873fd5 PB |
1298 | static int64_t |
1299 | extract_xt6 (uint64_t insn, | |
b9c361e0 JL |
1300 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1301 | int *invalid ATTRIBUTE_UNUSED) | |
43e65147 | 1302 | { |
b80c7270 | 1303 | return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); |
b9c361e0 JL |
1304 | } |
1305 | ||
b80c7270 | 1306 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
0f873fd5 PB |
1307 | static uint64_t |
1308 | insert_xtq6 (uint64_t insn, | |
1309 | int64_t value, | |
b80c7270 AM |
1310 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1311 | const char **errmsg ATTRIBUTE_UNUSED) | |
1312 | { | |
1313 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); | |
1314 | } | |
1315 | ||
0f873fd5 PB |
1316 | static int64_t |
1317 | extract_xtq6 (uint64_t insn, | |
b80c7270 AM |
1318 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1319 | int *invalid ATTRIBUTE_UNUSED) | |
1320 | { | |
1321 | return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); | |
1322 | } | |
1323 | ||
1324 | /* The XA field in an XX3 form instruction. This is split. */ | |
1325 | ||
0f873fd5 PB |
1326 | static uint64_t |
1327 | insert_xa6 (uint64_t insn, | |
1328 | int64_t value, | |
b9c361e0 JL |
1329 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1330 | const char **errmsg ATTRIBUTE_UNUSED) | |
1331 | { | |
b80c7270 | 1332 | return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); |
b9c361e0 JL |
1333 | } |
1334 | ||
0f873fd5 PB |
1335 | static int64_t |
1336 | extract_xa6 (uint64_t insn, | |
b9c361e0 JL |
1337 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1338 | int *invalid ATTRIBUTE_UNUSED) | |
1339 | { | |
b80c7270 | 1340 | return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); |
b9c361e0 JL |
1341 | } |
1342 | ||
b80c7270 AM |
1343 | /* The XB field in an XX3 form instruction. This is split. */ |
1344 | ||
0f873fd5 PB |
1345 | static uint64_t |
1346 | insert_xb6 (uint64_t insn, | |
1347 | int64_t value, | |
b80c7270 AM |
1348 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1349 | const char **errmsg ATTRIBUTE_UNUSED) | |
b9c361e0 | 1350 | { |
b80c7270 | 1351 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
b9c361e0 JL |
1352 | } |
1353 | ||
0f873fd5 PB |
1354 | static int64_t |
1355 | extract_xb6 (uint64_t insn, | |
b80c7270 AM |
1356 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1357 | int *invalid ATTRIBUTE_UNUSED) | |
b9c361e0 | 1358 | { |
b80c7270 | 1359 | return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); |
b9c361e0 JL |
1360 | } |
1361 | ||
98553ad3 PB |
1362 | /* The XA and XB fields in an XX3 form instruction when they must be the same. |
1363 | This is used for extended mnemonics like xvmovdp. The extraction function | |
1364 | enforces that the fields are the same. */ | |
b80c7270 | 1365 | |
0f873fd5 | 1366 | static uint64_t |
98553ad3 PB |
1367 | insert_xab6 (uint64_t insn, |
1368 | int64_t value, | |
1369 | ppc_cpu_t dialect, | |
1370 | const char **errmsg) | |
b9c361e0 | 1371 | { |
98553ad3 PB |
1372 | return insert_xa6 (insn, value, dialect, errmsg) |
1373 | | insert_xb6 (insn, value, dialect, errmsg); | |
b9c361e0 JL |
1374 | } |
1375 | ||
0f873fd5 | 1376 | static int64_t |
98553ad3 PB |
1377 | extract_xab6 (uint64_t insn, |
1378 | ppc_cpu_t dialect, | |
b80c7270 | 1379 | int *invalid) |
b9c361e0 | 1380 | { |
98553ad3 PB |
1381 | int64_t xa6 = extract_xa6 (insn, dialect, invalid); |
1382 | int64_t xb6 = extract_xb6 (insn, dialect, invalid); | |
1383 | ||
1384 | if (xa6 != xb6) | |
b80c7270 | 1385 | *invalid = 1; |
98553ad3 | 1386 | return xa6; |
b9c361e0 JL |
1387 | } |
1388 | ||
b80c7270 | 1389 | /* The XC field in an XX4 form instruction. This is split. */ |
252b5132 | 1390 | |
0f873fd5 PB |
1391 | static uint64_t |
1392 | insert_xc6 (uint64_t insn, | |
1393 | int64_t value, | |
fa452fa6 | 1394 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1395 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 | 1396 | { |
b80c7270 | 1397 | return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); |
252b5132 RH |
1398 | } |
1399 | ||
0f873fd5 PB |
1400 | static int64_t |
1401 | extract_xc6 (uint64_t insn, | |
fa452fa6 | 1402 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 | 1403 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 | 1404 | { |
b80c7270 AM |
1405 | return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); |
1406 | } | |
1407 | ||
0f873fd5 PB |
1408 | static uint64_t |
1409 | insert_dm (uint64_t insn, | |
1410 | int64_t value, | |
b80c7270 AM |
1411 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1412 | const char **errmsg) | |
1413 | { | |
1414 | if (value != 0 && value != 1) | |
1415 | *errmsg = _("invalid constant"); | |
1416 | return insn | (((value) ? 3 : 0) << 8); | |
1417 | } | |
1418 | ||
0f873fd5 PB |
1419 | static int64_t |
1420 | extract_dm (uint64_t insn, | |
b80c7270 AM |
1421 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1422 | int *invalid) | |
1423 | { | |
0f873fd5 | 1424 | int64_t value = (insn >> 8) & 3; |
b80c7270 | 1425 | if (value != 0 && value != 3) |
252b5132 | 1426 | *invalid = 1; |
b80c7270 | 1427 | return (value) ? 1 : 0; |
252b5132 RH |
1428 | } |
1429 | ||
b80c7270 | 1430 | /* The VLESIMM field in an I16A form instruction. This is split. */ |
252b5132 | 1431 | |
0f873fd5 PB |
1432 | static uint64_t |
1433 | insert_vlesi (uint64_t insn, | |
1434 | int64_t value, | |
b80c7270 AM |
1435 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1436 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1437 | { |
b80c7270 | 1438 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
252b5132 RH |
1439 | } |
1440 | ||
0f873fd5 PB |
1441 | static int64_t |
1442 | extract_vlesi (uint64_t insn, | |
b80c7270 AM |
1443 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1444 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1445 | { |
0f873fd5 | 1446 | int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
b80c7270 AM |
1447 | value = (value ^ 0x8000) - 0x8000; |
1448 | return value; | |
252b5132 RH |
1449 | } |
1450 | ||
0f873fd5 PB |
1451 | static uint64_t |
1452 | insert_vlensi (uint64_t insn, | |
1453 | int64_t value, | |
b80c7270 AM |
1454 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1455 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1456 | { |
b80c7270 AM |
1457 | value = -value; |
1458 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); | |
252b5132 | 1459 | } |
0f873fd5 PB |
1460 | static int64_t |
1461 | extract_vlensi (uint64_t insn, | |
b80c7270 | 1462 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
9cf7e568 | 1463 | int *invalid) |
252b5132 | 1464 | { |
0f873fd5 | 1465 | int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
b80c7270 AM |
1466 | value = (value ^ 0x8000) - 0x8000; |
1467 | /* Don't use for disassembly. */ | |
1468 | *invalid = 1; | |
1469 | return -value; | |
252b5132 RH |
1470 | } |
1471 | ||
b80c7270 | 1472 | /* The VLEUIMM field in an I16A form instruction. This is split. */ |
252b5132 | 1473 | |
0f873fd5 PB |
1474 | static uint64_t |
1475 | insert_vleui (uint64_t insn, | |
1476 | int64_t value, | |
b80c7270 AM |
1477 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1478 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1479 | { |
b80c7270 | 1480 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
252b5132 RH |
1481 | } |
1482 | ||
0f873fd5 PB |
1483 | static int64_t |
1484 | extract_vleui (uint64_t insn, | |
b80c7270 AM |
1485 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1486 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1487 | { |
b80c7270 AM |
1488 | return ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
1489 | } | |
8427c424 | 1490 | |
b80c7270 AM |
1491 | /* The VLEUIMML field in an I16L form instruction. This is split. */ |
1492 | ||
0f873fd5 PB |
1493 | static uint64_t |
1494 | insert_vleil (uint64_t insn, | |
1495 | int64_t value, | |
b80c7270 AM |
1496 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1497 | const char **errmsg ATTRIBUTE_UNUSED) | |
1498 | { | |
1499 | return insn | ((value & 0xf800) << 5) | (value & 0x7ff); | |
252b5132 RH |
1500 | } |
1501 | ||
0f873fd5 PB |
1502 | static int64_t |
1503 | extract_vleil (uint64_t insn, | |
b80c7270 AM |
1504 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1505 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1506 | { |
b80c7270 | 1507 | return ((insn >> 5) & 0xf800) | (insn & 0x7ff); |
8ebac3aa | 1508 | } |
ba4e851b | 1509 | |
0f873fd5 PB |
1510 | static uint64_t |
1511 | insert_evuimm1_ex0 (uint64_t insn, | |
1512 | int64_t value, | |
74081948 AF |
1513 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1514 | const char **errmsg) | |
1515 | { | |
1516 | if (value > 0 && value <= 0x1f) | |
1517 | return insn | ((value & 0x1f) << 11); | |
1518 | else | |
1519 | { | |
1520 | *errmsg = _("UIMM = 00000 is illegal"); | |
1521 | return 0; | |
1522 | } | |
1523 | } | |
1524 | ||
0f873fd5 PB |
1525 | static int64_t |
1526 | extract_evuimm1_ex0 (uint64_t insn, | |
74081948 AF |
1527 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1528 | int *invalid) | |
1529 | { | |
0f873fd5 | 1530 | int64_t value = ((insn >> 11) & 0x1f); |
74081948 AF |
1531 | if (value == 0) |
1532 | *invalid = 1; | |
1533 | ||
1534 | return value; | |
1535 | } | |
1536 | ||
0f873fd5 PB |
1537 | static uint64_t |
1538 | insert_evuimm2_ex0 (uint64_t insn, | |
1539 | int64_t value, | |
b80c7270 AM |
1540 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1541 | const char **errmsg) | |
8ebac3aa | 1542 | { |
b80c7270 AM |
1543 | if (value > 0 && value <= 0x3e) |
1544 | return insn | ((value & 0x3e) << 10); | |
802a735e | 1545 | else |
b80c7270 AM |
1546 | { |
1547 | *errmsg = _("UIMM = 00000 is illegal"); | |
1548 | return 0; | |
1549 | } | |
252b5132 RH |
1550 | } |
1551 | ||
0f873fd5 PB |
1552 | static int64_t |
1553 | extract_evuimm2_ex0 (uint64_t insn, | |
b80c7270 AM |
1554 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1555 | int *invalid) | |
8ebac3aa | 1556 | { |
0f873fd5 | 1557 | int64_t value = ((insn >> 10) & 0x3e); |
b80c7270 AM |
1558 | if (value == 0) |
1559 | *invalid = 1; | |
8ebac3aa | 1560 | |
b80c7270 | 1561 | return value; |
8ebac3aa AM |
1562 | } |
1563 | ||
0f873fd5 PB |
1564 | static uint64_t |
1565 | insert_evuimm4_ex0 (uint64_t insn, | |
1566 | int64_t value, | |
b80c7270 AM |
1567 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1568 | const char **errmsg) | |
252b5132 | 1569 | { |
b80c7270 AM |
1570 | if (value > 0 && value <= 0x7c) |
1571 | return insn | ((value & 0x7c) << 9); | |
1572 | else | |
1573 | { | |
1574 | *errmsg = _("UIMM = 00000 is illegal"); | |
1575 | return 0; | |
1576 | } | |
252b5132 RH |
1577 | } |
1578 | ||
0f873fd5 PB |
1579 | static int64_t |
1580 | extract_evuimm4_ex0 (uint64_t insn, | |
b80c7270 AM |
1581 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1582 | int *invalid) | |
252b5132 | 1583 | { |
0f873fd5 | 1584 | int64_t value = ((insn >> 9) & 0x7c); |
b80c7270 | 1585 | if (value == 0) |
252b5132 | 1586 | *invalid = 1; |
b80c7270 | 1587 | |
252b5132 RH |
1588 | return value; |
1589 | } | |
1590 | ||
0f873fd5 PB |
1591 | static uint64_t |
1592 | insert_evuimm8_ex0 (uint64_t insn, | |
1593 | int64_t value, | |
b80c7270 AM |
1594 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1595 | const char **errmsg) | |
1596 | { | |
1597 | if (value > 0 && value <= 0xf8) | |
1598 | return insn | ((value & 0xf8) << 8); | |
1599 | else | |
1600 | { | |
1601 | *errmsg = _("UIMM = 00000 is illegal"); | |
1602 | return 0; | |
1603 | } | |
252b5132 RH |
1604 | } |
1605 | ||
0f873fd5 PB |
1606 | static int64_t |
1607 | extract_evuimm8_ex0 (uint64_t insn, | |
b80c7270 AM |
1608 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1609 | int *invalid) | |
252b5132 | 1610 | { |
0f873fd5 | 1611 | int64_t value = ((insn >> 8) & 0xf8); |
b80c7270 | 1612 | if (value == 0) |
252b5132 | 1613 | *invalid = 1; |
252b5132 | 1614 | |
b80c7270 AM |
1615 | return value; |
1616 | } | |
a680de9a | 1617 | |
0f873fd5 PB |
1618 | static uint64_t |
1619 | insert_evuimm_lt8 (uint64_t insn, | |
1620 | int64_t value, | |
74081948 AF |
1621 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1622 | const char **errmsg) | |
1623 | { | |
1624 | if (value >= 0 && value <= 7) | |
1625 | return insn | ((value & 0x7) << 11); | |
1626 | else | |
1627 | { | |
1628 | *errmsg = _("UIMM values >7 are illegal"); | |
1629 | return 0; | |
1630 | } | |
1631 | } | |
1632 | ||
0f873fd5 PB |
1633 | static int64_t |
1634 | extract_evuimm_lt8 (uint64_t insn, | |
74081948 AF |
1635 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1636 | int *invalid) | |
1637 | { | |
0f873fd5 | 1638 | int64_t value = ((insn >> 11) & 0x1f); |
74081948 AF |
1639 | if (value > 7) |
1640 | *invalid = 1; | |
1641 | ||
1642 | return value; | |
1643 | } | |
1644 | ||
0f873fd5 PB |
1645 | static uint64_t |
1646 | insert_evuimm_lt16 (uint64_t insn, | |
1647 | int64_t value, | |
b80c7270 AM |
1648 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1649 | const char **errmsg) | |
a680de9a | 1650 | { |
b80c7270 AM |
1651 | if (value >= 0 && value <= 15) |
1652 | return insn | ((value & 0xf) << 11); | |
1653 | else | |
1654 | { | |
1655 | *errmsg = _("UIMM values >15 are illegal"); | |
1656 | return 0; | |
1657 | } | |
a680de9a PB |
1658 | } |
1659 | ||
0f873fd5 PB |
1660 | static int64_t |
1661 | extract_evuimm_lt16 (uint64_t insn, | |
b80c7270 AM |
1662 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1663 | int *invalid) | |
a680de9a | 1664 | { |
0f873fd5 | 1665 | int64_t value = ((insn >> 11) & 0x1f); |
b80c7270 AM |
1666 | if (value > 15) |
1667 | *invalid = 1; | |
a680de9a | 1668 | |
b80c7270 AM |
1669 | return value; |
1670 | } | |
a680de9a | 1671 | |
0f873fd5 PB |
1672 | static uint64_t |
1673 | insert_rD_rS_even (uint64_t insn, | |
1674 | int64_t value, | |
b80c7270 AM |
1675 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1676 | const char **errmsg) | |
a680de9a | 1677 | { |
b80c7270 AM |
1678 | if ((value & 0x1) == 0) |
1679 | return insn | ((value & 0x1e) << 21); | |
1680 | else | |
1681 | { | |
1682 | *errmsg = _("GPR odd is illegal"); | |
1683 | return 0; | |
1684 | } | |
a680de9a PB |
1685 | } |
1686 | ||
0f873fd5 PB |
1687 | static int64_t |
1688 | extract_rD_rS_even (uint64_t insn, | |
b80c7270 AM |
1689 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1690 | int *invalid) | |
a680de9a | 1691 | { |
0f873fd5 | 1692 | int64_t value = ((insn >> 21) & 0x1f); |
b80c7270 AM |
1693 | if ((value & 0x1) != 0) |
1694 | *invalid = 1; | |
1695 | ||
1696 | return value; | |
a680de9a PB |
1697 | } |
1698 | ||
0f873fd5 PB |
1699 | static uint64_t |
1700 | insert_off_lsp (uint64_t insn, | |
1701 | int64_t value, | |
b80c7270 AM |
1702 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1703 | const char **errmsg) | |
a680de9a | 1704 | { |
b80c7270 AM |
1705 | if (value > 0 && value <= 0x3) |
1706 | return insn | (value & 0x3); | |
1707 | else | |
1708 | { | |
1709 | *errmsg = _("invalid offset"); | |
1710 | return 0; | |
1711 | } | |
a680de9a PB |
1712 | } |
1713 | ||
0f873fd5 PB |
1714 | static int64_t |
1715 | extract_off_lsp (uint64_t insn, | |
b80c7270 AM |
1716 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1717 | int *invalid) | |
a680de9a | 1718 | { |
0f873fd5 | 1719 | int64_t value = (insn & 0x3); |
b80c7270 AM |
1720 | if (value == 0) |
1721 | *invalid = 1; | |
1722 | ||
1723 | return value; | |
a680de9a | 1724 | } |
74081948 | 1725 | |
0f873fd5 PB |
1726 | static uint64_t |
1727 | insert_off_spe2 (uint64_t insn, | |
1728 | int64_t value, | |
74081948 AF |
1729 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1730 | const char **errmsg) | |
1731 | { | |
1732 | if (value > 0 && value <= 0x7) | |
1733 | return insn | (value & 0x7); | |
1734 | else | |
1735 | { | |
1736 | *errmsg = _("invalid offset"); | |
1737 | return 0; | |
1738 | } | |
1739 | } | |
1740 | ||
0f873fd5 PB |
1741 | static int64_t |
1742 | extract_off_spe2 (uint64_t insn, | |
74081948 AF |
1743 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1744 | int *invalid) | |
1745 | { | |
0f873fd5 | 1746 | int64_t value = (insn & 0x7); |
74081948 AF |
1747 | if (value == 0) |
1748 | *invalid = 1; | |
1749 | ||
1750 | return value; | |
1751 | } | |
1752 | ||
0f873fd5 PB |
1753 | static uint64_t |
1754 | insert_Ddd (uint64_t insn, | |
1755 | int64_t value, | |
74081948 AF |
1756 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1757 | const char **errmsg) | |
1758 | { | |
1759 | if (value >= 0 && value <= 0x7) | |
1760 | return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2); | |
1761 | else | |
1762 | { | |
1763 | *errmsg = _("invalid Ddd value"); | |
1764 | return 0; | |
1765 | } | |
1766 | } | |
1767 | ||
0f873fd5 PB |
1768 | static int64_t |
1769 | extract_Ddd (uint64_t insn, | |
74081948 AF |
1770 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1771 | int *invalid ATTRIBUTE_UNUSED) | |
1772 | { | |
1773 | return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4); | |
1774 | } | |
9cf7e568 AM |
1775 | |
1776 | static uint64_t | |
1777 | insert_sxl (uint64_t insn, | |
1778 | int64_t value, | |
1779 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1780 | const char **errmsg ATTRIBUTE_UNUSED) | |
1781 | { | |
1782 | return insn | ((value & 0x1) << 11); | |
1783 | } | |
1784 | ||
1785 | static int64_t | |
1786 | extract_sxl (uint64_t insn, | |
1787 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1788 | int *invalid) | |
1789 | { | |
1790 | if (*invalid < 0) | |
1791 | return 1; | |
1792 | return (insn >> 11) & 0x1; | |
1793 | } | |
b80c7270 AM |
1794 | \f |
1795 | /* The operands table. | |
a680de9a | 1796 | |
b80c7270 | 1797 | The fields are bitm, shift, insert, extract, flags. |
2fbfdc41 | 1798 | |
b80c7270 AM |
1799 | We used to put parens around the various additions, like the one |
1800 | for BA just below. However, that caused trouble with feeble | |
1801 | compilers with a limit on depth of a parenthesized expression, like | |
1802 | (reportedly) the compiler in Microsoft Developer Studio 5. So we | |
1803 | omit the parens, since the macros are never used in a context where | |
1804 | the addition will be ambiguous. */ | |
1805 | ||
1806 | const struct powerpc_operand powerpc_operands[] = | |
c168870a | 1807 | { |
b80c7270 AM |
1808 | /* The zero index is used to indicate the end of the list of |
1809 | operands. */ | |
1810 | #define UNUSED 0 | |
1811 | { 0, 0, NULL, NULL, 0 }, | |
1812 | ||
1813 | /* The BA field in an XL form instruction. */ | |
1814 | #define BA UNUSED + 1 | |
1815 | /* The BI field in a B form or XL form instruction. */ | |
1816 | #define BI BA | |
1817 | #define BI_MASK (0x1f << 16) | |
1818 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
1819 | ||
98553ad3 PB |
1820 | /* The BT, BA and BB fields in a XL form instruction when they must all |
1821 | be the same. */ | |
1822 | #define BTAB BA + 1 | |
1823 | { 0x1f, 21, insert_btab, extract_btab, PPC_OPERAND_CR_BIT }, | |
b80c7270 AM |
1824 | |
1825 | /* The BB field in an XL form instruction. */ | |
98553ad3 | 1826 | #define BB BTAB + 1 |
b80c7270 AM |
1827 | #define BB_MASK (0x1f << 11) |
1828 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
1829 | ||
98553ad3 PB |
1830 | /* The BA and BB fields in a XL form instruction when they must be |
1831 | the same. */ | |
1832 | #define BAB BB + 1 | |
1833 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_CR_BIT }, | |
1834 | ||
1835 | /* The VRA and VRB fields in a VX form instruction when they must be the same. | |
1836 | This is used for extended mnemonics like vmr. */ | |
1837 | #define VAB BAB + 1 | |
1838 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_VR }, | |
1839 | ||
1840 | /* The RA and RB fields in a VX form instruction when they must be the same. | |
1841 | This is used for extended mnemonics like evmr. */ | |
1842 | #define RAB VAB + 1 | |
1843 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_GPR }, | |
b80c7270 AM |
1844 | |
1845 | /* The BD field in a B form instruction. The lower two bits are | |
1846 | forced to zero. */ | |
98553ad3 | 1847 | #define BD RAB + 1 |
b80c7270 AM |
1848 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
1849 | ||
1850 | /* The BD field in a B form instruction when absolute addressing is | |
1851 | used. */ | |
1852 | #define BDA BD + 1 | |
1853 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
1854 | ||
1855 | /* The BD field in a B form instruction when the - modifier is used. | |
1856 | This sets the y bit of the BO field appropriately. */ | |
1857 | #define BDM BDA + 1 | |
1858 | { 0xfffc, 0, insert_bdm, extract_bdm, | |
1859 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
1860 | ||
1861 | /* The BD field in a B form instruction when the - modifier is used | |
1862 | and absolute address is used. */ | |
1863 | #define BDMA BDM + 1 | |
1864 | { 0xfffc, 0, insert_bdm, extract_bdm, | |
1865 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
1866 | ||
1867 | /* The BD field in a B form instruction when the + modifier is used. | |
1868 | This sets the y bit of the BO field appropriately. */ | |
1869 | #define BDP BDMA + 1 | |
1870 | { 0xfffc, 0, insert_bdp, extract_bdp, | |
1871 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
1872 | ||
1873 | /* The BD field in a B form instruction when the + modifier is used | |
1874 | and absolute addressing is used. */ | |
1875 | #define BDPA BDP + 1 | |
1876 | { 0xfffc, 0, insert_bdp, extract_bdp, | |
1877 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
1878 | ||
1879 | /* The BF field in an X or XL form instruction. */ | |
1880 | #define BF BDPA + 1 | |
1881 | /* The CRFD field in an X form instruction. */ | |
1882 | #define CRFD BF | |
1883 | /* The CRD field in an XL form instruction. */ | |
1884 | #define CRD BF | |
1885 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, | |
1886 | ||
1887 | /* The BF field in an X or XL form instruction. */ | |
1888 | #define BFF BF + 1 | |
1889 | { 0x7, 23, NULL, NULL, 0 }, | |
1890 | ||
1891 | /* An optional BF field. This is used for comparison instructions, | |
1892 | in which an omitted BF field is taken as zero. */ | |
1893 | #define OBF BFF + 1 | |
1894 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
1895 | ||
1896 | /* The BFA field in an X or XL form instruction. */ | |
1897 | #define BFA OBF + 1 | |
1898 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, | |
1899 | ||
1900 | /* The BO field in a B form instruction. Certain values are | |
1901 | illegal. */ | |
1902 | #define BO BFA + 1 | |
1903 | #define BO_MASK (0x1f << 21) | |
1904 | { 0x1f, 21, insert_bo, extract_bo, 0 }, | |
1905 | ||
1906 | /* The BO field in a B form instruction when the + or - modifier is | |
1907 | used. This is like the BO field, but it must be even. */ | |
1908 | #define BOE BO + 1 | |
1909 | { 0x1e, 21, insert_boe, extract_boe, 0 }, | |
1910 | ||
1911 | /* The RM field in an X form instruction. */ | |
1912 | #define RM BOE + 1 | |
74081948 | 1913 | #define DD RM |
b80c7270 AM |
1914 | { 0x3, 11, NULL, NULL, 0 }, |
1915 | ||
1916 | #define BH RM + 1 | |
1917 | { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
1918 | ||
1919 | /* The BT field in an X or XL form instruction. */ | |
1920 | #define BT BH + 1 | |
1921 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
1922 | ||
1923 | /* The BI16 field in a BD8 form instruction. */ | |
1924 | #define BI16 BT + 1 | |
1925 | { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
1926 | ||
1927 | /* The BI32 field in a BD15 form instruction. */ | |
1928 | #define BI32 BI16 + 1 | |
1929 | { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
98e69875 | 1930 | |
b80c7270 AM |
1931 | /* The BO32 field in a BD15 form instruction. */ |
1932 | #define BO32 BI32 + 1 | |
1933 | { 0x3, 20, NULL, NULL, 0 }, | |
c168870a | 1934 | |
b80c7270 AM |
1935 | /* The B8 field in a BD8 form instruction. */ |
1936 | #define B8 BO32 + 1 | |
1937 | { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 1938 | |
b80c7270 AM |
1939 | /* The B15 field in a BD15 form instruction. The lowest bit is |
1940 | forced to zero. */ | |
1941 | #define B15 B8 + 1 | |
1942 | { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 1943 | |
b80c7270 AM |
1944 | /* The B24 field in a BD24 form instruction. The lowest bit is |
1945 | forced to zero. */ | |
1946 | #define B24 B15 + 1 | |
1947 | { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 1948 | |
b80c7270 AM |
1949 | /* The condition register number portion of the BI field in a B form |
1950 | or XL form instruction. This is used for the extended | |
1951 | conditional branch mnemonics, which set the lower two bits of the | |
1952 | BI field. This field is optional. */ | |
1953 | #define CR B24 + 1 | |
1954 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
c168870a | 1955 | |
b80c7270 AM |
1956 | /* The CRB field in an X form instruction. */ |
1957 | #define CRB CR + 1 | |
1958 | /* The MB field in an M form instruction. */ | |
1959 | #define MB CRB | |
1960 | #define MB_MASK (0x1f << 6) | |
1961 | { 0x1f, 6, NULL, NULL, 0 }, | |
c168870a | 1962 | |
b80c7270 AM |
1963 | /* The CRD32 field in an XL form instruction. */ |
1964 | #define CRD32 CRB + 1 | |
1965 | { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, | |
c168870a | 1966 | |
b80c7270 AM |
1967 | /* The CRFS field in an X form instruction. */ |
1968 | #define CRFS CRD32 + 1 | |
1969 | { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, | |
b9c361e0 | 1970 | |
b80c7270 AM |
1971 | #define CRS CRFS + 1 |
1972 | { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 1973 | |
b80c7270 AM |
1974 | /* The CT field in an X form instruction. */ |
1975 | #define CT CRS + 1 | |
1976 | /* The MO field in an mbar instruction. */ | |
1977 | #define MO CT | |
1978 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 1979 | |
b80c7270 AM |
1980 | /* The D field in a D form instruction. This is a displacement off |
1981 | a register, and implies that the next operand is a register in | |
1982 | parentheses. */ | |
1983 | #define D CT + 1 | |
1984 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
aea77599 | 1985 | |
b80c7270 AM |
1986 | /* The D8 field in a D form instruction. This is a displacement off |
1987 | a register, and implies that the next operand is a register in | |
1988 | parentheses. */ | |
1989 | #define D8 D + 1 | |
1990 | { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
7b934113 | 1991 | |
b80c7270 AM |
1992 | /* The DCMX field in an X form instruction. */ |
1993 | #define DCMX D8 + 1 | |
1994 | { 0x7f, 16, NULL, NULL, 0 }, | |
7b934113 | 1995 | |
b80c7270 AM |
1996 | /* The split DCMX field in an X form instruction. */ |
1997 | #define DCMXS DCMX + 1 | |
1998 | { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, | |
73f07bff | 1999 | |
b80c7270 AM |
2000 | /* The DQ field in a DQ form instruction. This is like D, but the |
2001 | lower four bits are forced to zero. */ | |
2002 | #define DQ DCMXS + 1 | |
2003 | { 0xfff0, 0, NULL, NULL, | |
2004 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, | |
73f07bff | 2005 | |
b80c7270 AM |
2006 | /* The DS field in a DS form instruction. This is like D, but the |
2007 | lower two bits are forced to zero. */ | |
2008 | #define DS DQ + 1 | |
2009 | { 0xfffc, 0, NULL, NULL, | |
2010 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, | |
7b934113 | 2011 | |
b80c7270 AM |
2012 | /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits |
2013 | unsigned imediate */ | |
2014 | #define DUIS DS + 1 | |
2015 | #define BHRBE DUIS | |
2016 | { 0x3ff, 11, NULL, NULL, 0 }, | |
aea77599 | 2017 | |
b80c7270 AM |
2018 | /* The split D field in a DX form instruction. */ |
2019 | #define DXD DUIS + 1 | |
2020 | { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, | |
2021 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, | |
7b934113 | 2022 | |
b80c7270 AM |
2023 | /* The split ND field in a DX form instruction. |
2024 | This is the same as the DX field, only negated. */ | |
2025 | #define NDXD DXD + 1 | |
2026 | { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, | |
2027 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, | |
7b934113 | 2028 | |
b80c7270 AM |
2029 | /* The E field in a wrteei instruction. */ |
2030 | /* And the W bit in the pair singles instructions. */ | |
2031 | /* And the ST field in a VX form instruction. */ | |
2032 | #define E NDXD + 1 | |
2033 | #define PSW E | |
2034 | #define ST E | |
2035 | { 0x1, 15, NULL, NULL, 0 }, | |
aea77599 | 2036 | |
b80c7270 AM |
2037 | /* The FL1 field in a POWER SC form instruction. */ |
2038 | #define FL1 E + 1 | |
2039 | /* The U field in an X form instruction. */ | |
2040 | #define U FL1 | |
2041 | { 0xf, 12, NULL, NULL, 0 }, | |
73f07bff | 2042 | |
b80c7270 AM |
2043 | /* The FL2 field in a POWER SC form instruction. */ |
2044 | #define FL2 FL1 + 1 | |
2045 | { 0x7, 2, NULL, NULL, 0 }, | |
73f07bff | 2046 | |
b80c7270 AM |
2047 | /* The FLM field in an XFL form instruction. */ |
2048 | #define FLM FL2 + 1 | |
2049 | { 0xff, 17, NULL, NULL, 0 }, | |
73f07bff | 2050 | |
b80c7270 AM |
2051 | /* The FRA field in an X or A form instruction. */ |
2052 | #define FRA FLM + 1 | |
2053 | #define FRA_MASK (0x1f << 16) | |
2054 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2055 | |
b80c7270 AM |
2056 | /* The FRAp field of DFP instructions. */ |
2057 | #define FRAp FRA + 1 | |
2058 | { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2059 | |
b80c7270 AM |
2060 | /* The FRB field in an X or A form instruction. */ |
2061 | #define FRB FRAp + 1 | |
2062 | #define FRB_MASK (0x1f << 11) | |
2063 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, | |
2064 | ||
2065 | /* The FRBp field of DFP instructions. */ | |
2066 | #define FRBp FRB + 1 | |
2067 | { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2068 | |
b80c7270 AM |
2069 | /* The FRC field in an A form instruction. */ |
2070 | #define FRC FRBp + 1 | |
2071 | #define FRC_MASK (0x1f << 6) | |
2072 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2073 | |
b80c7270 AM |
2074 | /* The FRS field in an X form instruction or the FRT field in a D, X |
2075 | or A form instruction. */ | |
2076 | #define FRS FRC + 1 | |
2077 | #define FRT FRS | |
2078 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2079 | |
b80c7270 AM |
2080 | /* The FRSp field of stfdp or the FRTp field of lfdp and DFP |
2081 | instructions. */ | |
2082 | #define FRSp FRS + 1 | |
2083 | #define FRTp FRSp | |
2084 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2085 | |
b80c7270 AM |
2086 | /* The FXM field in an XFX instruction. */ |
2087 | #define FXM FRSp + 1 | |
2088 | { 0xff, 12, insert_fxm, extract_fxm, 0 }, | |
252b5132 | 2089 | |
b80c7270 AM |
2090 | /* Power4 version for mfcr. */ |
2091 | #define FXM4 FXM + 1 | |
9cf7e568 | 2092 | { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, |
252b5132 | 2093 | |
b80c7270 | 2094 | /* The IMM20 field in an LI instruction. */ |
9cf7e568 | 2095 | #define IMM20 FXM4 + 1 |
b80c7270 | 2096 | { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, |
252b5132 | 2097 | |
b80c7270 AM |
2098 | /* The L field in a D or X form instruction. */ |
2099 | #define L IMM20 + 1 | |
2100 | { 0x1, 21, NULL, NULL, 0 }, | |
252b5132 | 2101 | |
b80c7270 AM |
2102 | /* The optional L field in tlbie and tlbiel instructions. */ |
2103 | #define LOPT L + 1 | |
2104 | /* The R field in a HTM X form instruction. */ | |
2105 | #define HTM_R LOPT | |
2106 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2107 | |
b80c7270 AM |
2108 | /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ |
2109 | #define L32OPT LOPT + 1 | |
2110 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, | |
252b5132 | 2111 | |
b80c7270 AM |
2112 | /* The L field in dcbf instruction. */ |
2113 | #define L2OPT L32OPT + 1 | |
2114 | { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2115 | |
b80c7270 AM |
2116 | /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ |
2117 | #define SVC_LEV L2OPT + 1 | |
2118 | { 0x7f, 5, NULL, NULL, 0 }, | |
252b5132 | 2119 | |
b80c7270 AM |
2120 | /* The LEV field in an SC form instruction. */ |
2121 | #define LEV SVC_LEV + 1 | |
2122 | { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2123 | |
b80c7270 AM |
2124 | /* The LI field in an I form instruction. The lower two bits are |
2125 | forced to zero. */ | |
2126 | #define LI LEV + 1 | |
2127 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2128 | |
b80c7270 AM |
2129 | /* The LI field in an I form instruction when used as an absolute |
2130 | address. */ | |
2131 | #define LIA LI + 1 | |
2132 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2133 | |
b80c7270 AM |
2134 | /* The LS or WC field in an X (sync or wait) form instruction. */ |
2135 | #define LS LIA + 1 | |
2136 | #define WC LS | |
2137 | { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2138 | |
b80c7270 AM |
2139 | /* The ME field in an M form instruction. */ |
2140 | #define ME LS + 1 | |
2141 | #define ME_MASK (0x1f << 1) | |
2142 | { 0x1f, 1, NULL, NULL, 0 }, | |
989993d8 | 2143 | |
b80c7270 AM |
2144 | /* The MB and ME fields in an M form instruction expressed a single |
2145 | operand which is a bitmask indicating which bits to select. This | |
2146 | is a two operand form using PPC_OPERAND_NEXT. See the | |
2147 | description in opcode/ppc.h for what this means. */ | |
2148 | #define MBE ME + 1 | |
2149 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, | |
2150 | { -1, 0, insert_mbe, extract_mbe, 0 }, | |
989993d8 | 2151 | |
b80c7270 AM |
2152 | /* The MB or ME field in an MD or MDS form instruction. The high |
2153 | bit is wrapped to the low end. */ | |
2154 | #define MB6 MBE + 2 | |
2155 | #define ME6 MB6 | |
2156 | #define MB6_MASK (0x3f << 5) | |
2157 | { 0x3f, 5, insert_mb6, extract_mb6, 0 }, | |
989993d8 | 2158 | |
b80c7270 AM |
2159 | /* The NB field in an X form instruction. The value 32 is stored as |
2160 | 0. */ | |
2161 | #define NB MB6 + 1 | |
2162 | { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, | |
252b5132 | 2163 | |
b80c7270 AM |
2164 | /* The NBI field in an lswi instruction, which has special value |
2165 | restrictions. The value 32 is stored as 0. */ | |
2166 | #define NBI NB + 1 | |
2167 | { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, | |
252b5132 | 2168 | |
b80c7270 AM |
2169 | /* The NSI field in a D form instruction. This is the same as the |
2170 | SI field, only negated. */ | |
2171 | #define NSI NBI + 1 | |
2172 | { 0xffff, 0, insert_nsi, extract_nsi, | |
2173 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2174 | |
b80c7270 AM |
2175 | /* The NSI field in a D form instruction when we accept a wide range |
2176 | of positive values. */ | |
2177 | #define NSISIGNOPT NSI + 1 | |
2178 | { 0xffff, 0, insert_nsi, extract_nsi, | |
2179 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
252b5132 | 2180 | |
b80c7270 AM |
2181 | /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
2182 | #define RA NSISIGNOPT + 1 | |
2183 | #define RA_MASK (0x1f << 16) | |
2184 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, | |
252b5132 | 2185 | |
b80c7270 AM |
2186 | /* As above, but 0 in the RA field means zero, not r0. */ |
2187 | #define RA0 RA + 1 | |
2188 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2189 | |
b80c7270 AM |
2190 | /* The RA field in the DQ form lq or an lswx instruction, which have |
2191 | special value restrictions. */ | |
2192 | #define RAQ RA0 + 1 | |
2193 | #define RAX RAQ | |
2194 | { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2195 | |
b80c7270 AM |
2196 | /* The RA field in a D or X form instruction which is an updating |
2197 | load, which means that the RA field may not be zero and may not | |
2198 | equal the RT field. */ | |
2199 | #define RAL RAQ + 1 | |
2200 | { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 }, | |
252b5132 | 2201 | |
b80c7270 AM |
2202 | /* The RA field in an lmw instruction, which has special value |
2203 | restrictions. */ | |
2204 | #define RAM RAL + 1 | |
2205 | { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 }, | |
252b5132 | 2206 | |
b80c7270 AM |
2207 | /* The RA field in a D or X form instruction which is an updating |
2208 | store or an updating floating point load, which means that the RA | |
2209 | field may not be zero. */ | |
2210 | #define RAS RAM + 1 | |
2211 | { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2212 | |
b80c7270 AM |
2213 | /* The RA field of the tlbwe, dccci and iccci instructions, |
2214 | which are optional. */ | |
2215 | #define RAOPT RAS + 1 | |
2216 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2217 | |
b80c7270 AM |
2218 | /* The RB field in an X, XO, M, or MDS form instruction. */ |
2219 | #define RB RAOPT + 1 | |
2220 | #define RB_MASK (0x1f << 11) | |
2221 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, | |
adadcc0c | 2222 | |
98553ad3 PB |
2223 | /* The RS and RB fields in an X form instruction when they must be the same. |
2224 | This is used for extended mnemonics like mr. */ | |
2225 | #define RSB RB + 1 | |
2226 | { 0x1f, 11, insert_rsb, extract_rsb, PPC_OPERAND_GPR }, | |
adadcc0c | 2227 | |
b80c7270 AM |
2228 | /* The RB field in an lswx instruction, which has special value |
2229 | restrictions. */ | |
98553ad3 | 2230 | #define RBX RSB + 1 |
b80c7270 | 2231 | { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR }, |
adadcc0c | 2232 | |
b80c7270 AM |
2233 | /* The RB field of the dccci and iccci instructions, which are optional. */ |
2234 | #define RBOPT RBX + 1 | |
2235 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2236 | |
b80c7270 AM |
2237 | /* The RC register field in an maddld, maddhd or maddhdu instruction. */ |
2238 | #define RC RBOPT + 1 | |
2239 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, | |
73f07bff | 2240 | |
b80c7270 AM |
2241 | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
2242 | instruction or the RT field in a D, DS, X, XFX or XO form | |
2243 | instruction. */ | |
2244 | #define RS RC + 1 | |
2245 | #define RT RS | |
2246 | #define RT_MASK (0x1f << 21) | |
2247 | #define RD RS | |
2248 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, | |
252b5132 | 2249 | |
b80c7270 AM |
2250 | #define RD_EVEN RS + 1 |
2251 | #define RS_EVEN RD_EVEN | |
2252 | { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR }, | |
252b5132 | 2253 | |
b80c7270 AM |
2254 | /* The RS and RT fields of the DS form stq and DQ form lq instructions, |
2255 | which have special value restrictions. */ | |
2256 | #define RSQ RS_EVEN + 1 | |
2257 | #define RTQ RSQ | |
2258 | #define Q_MASK (1 << 21) | |
2259 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, | |
73f07bff | 2260 | |
b80c7270 AM |
2261 | /* The RS field of the tlbwe instruction, which is optional. */ |
2262 | #define RSO RSQ + 1 | |
2263 | #define RTO RSO | |
2264 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2265 | |
b80c7270 AM |
2266 | /* The RX field of the SE_RR form instruction. */ |
2267 | #define RX RSO + 1 | |
2268 | { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, | |
252b5132 | 2269 | |
b80c7270 AM |
2270 | /* The ARX field of the SE_RR form instruction. */ |
2271 | #define ARX RX + 1 | |
2272 | { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, | |
252b5132 | 2273 | |
b80c7270 AM |
2274 | /* The RY field of the SE_RR form instruction. */ |
2275 | #define RY ARX + 1 | |
2276 | #define RZ RY | |
2277 | { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, | |
252b5132 | 2278 | |
b80c7270 AM |
2279 | /* The ARY field of the SE_RR form instruction. */ |
2280 | #define ARY RY + 1 | |
2281 | { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, | |
989993d8 | 2282 | |
b80c7270 AM |
2283 | /* The SCLSCI8 field in a D form instruction. */ |
2284 | #define SCLSCI8 ARY + 1 | |
2285 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, | |
989993d8 | 2286 | |
b80c7270 AM |
2287 | /* The SCLSCI8N field in a D form instruction. This is the same as the |
2288 | SCLSCI8 field, only negated. */ | |
2289 | #define SCLSCI8N SCLSCI8 + 1 | |
2290 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, | |
2291 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, | |
989993d8 | 2292 | |
b80c7270 AM |
2293 | /* The SD field of the SD4 form instruction. */ |
2294 | #define SE_SD SCLSCI8N + 1 | |
2295 | { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, | |
73f07bff | 2296 | |
b80c7270 AM |
2297 | /* The SD field of the SD4 form instruction, for halfword. */ |
2298 | #define SE_SDH SE_SD + 1 | |
2299 | { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, | |
73f07bff | 2300 | |
b80c7270 AM |
2301 | /* The SD field of the SD4 form instruction, for word. */ |
2302 | #define SE_SDW SE_SDH + 1 | |
2303 | { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, | |
b9c361e0 | 2304 | |
b80c7270 AM |
2305 | /* The SH field in an X or M form instruction. */ |
2306 | #define SH SE_SDW + 1 | |
2307 | #define SH_MASK (0x1f << 11) | |
2308 | /* The other UIMM field in a EVX form instruction. */ | |
2309 | #define EVUIMM SH | |
2310 | /* The FC field in an atomic X form instruction. */ | |
2311 | #define FC SH | |
2312 | { 0x1f, 11, NULL, NULL, 0 }, | |
b9c361e0 | 2313 | |
74081948 AF |
2314 | #define EVUIMM_LT8 SH + 1 |
2315 | { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 }, | |
2316 | ||
2317 | #define EVUIMM_LT16 EVUIMM_LT8 + 1 | |
b80c7270 | 2318 | { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 }, |
b9c361e0 | 2319 | |
b80c7270 AM |
2320 | /* The SI field in a HTM X form instruction. */ |
2321 | #define HTM_SI EVUIMM_LT16 + 1 | |
2322 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, | |
943d398f | 2323 | |
b80c7270 AM |
2324 | /* The SH field in an MD form instruction. This is split. */ |
2325 | #define SH6 HTM_SI + 1 | |
2326 | #define SH6_MASK ((0x1f << 11) | (1 << 1)) | |
2327 | { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, | |
b9c361e0 | 2328 | |
b80c7270 AM |
2329 | /* The SH field of some variants of the tlbre and tlbwe |
2330 | instructions, and the ELEV field of the e_sc instruction. */ | |
2331 | #define SHO SH6 + 1 | |
2332 | #define ELEV SHO | |
2333 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2334 | |
b80c7270 AM |
2335 | /* The SI field in a D form instruction. */ |
2336 | #define SI SHO + 1 | |
2337 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, | |
b9c361e0 | 2338 | |
b80c7270 AM |
2339 | /* The SI field in a D form instruction when we accept a wide range |
2340 | of positive values. */ | |
2341 | #define SISIGNOPT SI + 1 | |
2342 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
b9c361e0 | 2343 | |
b80c7270 AM |
2344 | /* The SI8 field in a D form instruction. */ |
2345 | #define SI8 SISIGNOPT + 1 | |
2346 | { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, | |
b9c361e0 | 2347 | |
b80c7270 AM |
2348 | /* The SPR field in an XFX form instruction. This is flipped--the |
2349 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
2350 | #define SPR SI8 + 1 | |
2351 | #define PMR SPR | |
2352 | #define TMR SPR | |
2353 | #define SPR_MASK (0x3ff << 11) | |
2354 | { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR }, | |
b9c361e0 | 2355 | |
b80c7270 AM |
2356 | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ |
2357 | #define SPRBAT SPR + 1 | |
fa758a70 AC |
2358 | #define SPRBAT_MASK (0xc1 << 11) |
2359 | { 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR }, | |
2360 | ||
2361 | /* The GQR index number in an XFX form m[ft]gqr instruction. */ | |
2362 | #define SPRGQR SPRBAT + 1 | |
2363 | #define SPRGQR_MASK (0x7 << 16) | |
2364 | { 0x7, 16, NULL, NULL, PPC_OPERAND_GQR }, | |
b9c361e0 | 2365 | |
b80c7270 | 2366 | /* The SPRG register number in an XFX form m[ft]sprg instruction. */ |
fa758a70 | 2367 | #define SPRG SPRGQR + 1 |
b80c7270 | 2368 | { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, |
b9c361e0 | 2369 | |
b80c7270 AM |
2370 | /* The SR field in an X form instruction. */ |
2371 | #define SR SPRG + 1 | |
2372 | /* The 4-bit UIMM field in a VX form instruction. */ | |
2373 | #define UIMM4 SR | |
2374 | { 0xf, 16, NULL, NULL, 0 }, | |
b9c361e0 | 2375 | |
b80c7270 AM |
2376 | /* The STRM field in an X AltiVec form instruction. */ |
2377 | #define STRM SR + 1 | |
2378 | /* The T field in a tlbilx form instruction. */ | |
2379 | #define T STRM | |
2380 | /* The L field in wclr instructions. */ | |
2381 | #define L2 STRM | |
2382 | { 0x3, 21, NULL, NULL, 0 }, | |
252b5132 | 2383 | |
b80c7270 AM |
2384 | /* The ESYNC field in an X (sync) form instruction. */ |
2385 | #define ESYNC STRM + 1 | |
2386 | { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2387 | |
b80c7270 AM |
2388 | /* The SV field in a POWER SC form instruction. */ |
2389 | #define SV ESYNC + 1 | |
2390 | { 0x3fff, 2, NULL, NULL, 0 }, | |
252b5132 | 2391 | |
b80c7270 AM |
2392 | /* The TBR field in an XFX form instruction. This is like the SPR |
2393 | field, but it is optional. */ | |
2394 | #define TBR SV + 1 | |
2395 | { 0x3ff, 11, insert_tbr, extract_tbr, | |
9cf7e568 | 2396 | PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL }, |
252b5132 | 2397 | |
b80c7270 | 2398 | /* The TO field in a D or X form instruction. */ |
9cf7e568 | 2399 | #define TO TBR + 1 |
b80c7270 AM |
2400 | #define DUI TO |
2401 | #define TO_MASK (0x1f << 21) | |
2402 | { 0x1f, 21, NULL, NULL, 0 }, | |
252b5132 | 2403 | |
b80c7270 AM |
2404 | /* The UI field in a D form instruction. */ |
2405 | #define UI TO + 1 | |
2406 | { 0xffff, 0, NULL, NULL, 0 }, | |
252b5132 | 2407 | |
b80c7270 AM |
2408 | #define UISIGNOPT UI + 1 |
2409 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, | |
da99ee72 | 2410 | |
b80c7270 AM |
2411 | /* The IMM field in an SE_IM5 instruction. */ |
2412 | #define UI5 UISIGNOPT + 1 | |
2413 | { 0x1f, 4, NULL, NULL, 0 }, | |
da99ee72 | 2414 | |
b80c7270 AM |
2415 | /* The OIMM field in an SE_OIM5 instruction. */ |
2416 | #define OIMM5 UI5 + 1 | |
2417 | { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, | |
da99ee72 | 2418 | |
b80c7270 AM |
2419 | /* The UI7 field in an SE_LI instruction. */ |
2420 | #define UI7 OIMM5 + 1 | |
2421 | { 0x7f, 4, NULL, NULL, 0 }, | |
da99ee72 | 2422 | |
b80c7270 AM |
2423 | /* The VA field in a VA, VX or VXR form instruction. */ |
2424 | #define VA UI7 + 1 | |
2425 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, | |
da99ee72 | 2426 | |
b80c7270 AM |
2427 | /* The VB field in a VA, VX or VXR form instruction. */ |
2428 | #define VB VA + 1 | |
2429 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, | |
da99ee72 | 2430 | |
b80c7270 AM |
2431 | /* The VC field in a VA form instruction. */ |
2432 | #define VC VB + 1 | |
2433 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, | |
252b5132 | 2434 | |
b80c7270 AM |
2435 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
2436 | #define VD VC + 1 | |
2437 | #define VS VD | |
2438 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, | |
252b5132 | 2439 | |
b80c7270 AM |
2440 | /* The SIMM field in a VX form instruction, and TE in Z form. */ |
2441 | #define SIMM VD + 1 | |
2442 | #define TE SIMM | |
2443 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, | |
252b5132 | 2444 | |
b80c7270 AM |
2445 | /* The UIMM field in a VX form instruction. */ |
2446 | #define UIMM SIMM + 1 | |
2447 | #define DCTL UIMM | |
2448 | { 0x1f, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2449 | |
b80c7270 AM |
2450 | /* The 3-bit UIMM field in a VX form instruction. */ |
2451 | #define UIMM3 UIMM + 1 | |
2452 | { 0x7, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2453 | |
b80c7270 AM |
2454 | /* The 6-bit UIM field in a X form instruction. */ |
2455 | #define UIM6 UIMM3 + 1 | |
2456 | { 0x3f, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2457 | |
b80c7270 AM |
2458 | /* The SIX field in a VX form instruction. */ |
2459 | #define SIX UIM6 + 1 | |
74081948 | 2460 | #define MMMM SIX |
b80c7270 | 2461 | { 0xf, 11, NULL, NULL, 0 }, |
9b4e5766 | 2462 | |
b80c7270 AM |
2463 | /* The PS field in a VX form instruction. */ |
2464 | #define PS SIX + 1 | |
2465 | { 0x1, 9, NULL, NULL, 0 }, | |
a680de9a | 2466 | |
b80c7270 AM |
2467 | /* The SHB field in a VA form instruction. */ |
2468 | #define SHB PS + 1 | |
2469 | { 0xf, 6, NULL, NULL, 0 }, | |
a680de9a | 2470 | |
b80c7270 | 2471 | /* The other UIMM field in a half word EVX form instruction. */ |
74081948 AF |
2472 | #define EVUIMM_1 SHB + 1 |
2473 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS }, | |
2474 | ||
2475 | #define EVUIMM_1_EX0 EVUIMM_1 + 1 | |
2476 | { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS }, | |
2477 | ||
2478 | #define EVUIMM_2 EVUIMM_1_EX0 + 1 | |
b80c7270 | 2479 | { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
9b4e5766 | 2480 | |
b80c7270 AM |
2481 | #define EVUIMM_2_EX0 EVUIMM_2 + 1 |
2482 | { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2483 | |
b80c7270 AM |
2484 | /* The other UIMM field in a word EVX form instruction. */ |
2485 | #define EVUIMM_4 EVUIMM_2_EX0 + 1 | |
2486 | { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2487 | |
b80c7270 AM |
2488 | #define EVUIMM_4_EX0 EVUIMM_4 + 1 |
2489 | { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2490 | |
b80c7270 AM |
2491 | /* The other UIMM field in a double EVX form instruction. */ |
2492 | #define EVUIMM_8 EVUIMM_4_EX0 + 1 | |
2493 | { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2494 | |
b80c7270 AM |
2495 | #define EVUIMM_8_EX0 EVUIMM_8 + 1 |
2496 | { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2497 | |
b80c7270 AM |
2498 | /* The WS or DRM field in an X form instruction. */ |
2499 | #define WS EVUIMM_8_EX0 + 1 | |
2500 | #define DRM WS | |
74081948 AF |
2501 | /* The NNN field in a VX form instruction for SPE2 */ |
2502 | #define NNN WS | |
b80c7270 | 2503 | { 0x7, 11, NULL, NULL, 0 }, |
9b4e5766 | 2504 | |
b80c7270 AM |
2505 | /* PowerPC paired singles extensions. */ |
2506 | /* W bit in the pair singles instructions for x type instructions. */ | |
2507 | #define PSWM WS + 1 | |
2508 | /* The BO16 field in a BD8 form instruction. */ | |
2509 | #define BO16 PSWM | |
2510 | { 0x1, 10, 0, 0, 0 }, | |
9b4e5766 | 2511 | |
b80c7270 AM |
2512 | /* IDX bits for quantization in the pair singles instructions. */ |
2513 | #define PSQ PSWM + 1 | |
2514 | { 0x7, 12, 0, 0, PPC_OPERAND_GQR }, | |
066be9f7 | 2515 | |
b80c7270 AM |
2516 | /* IDX bits for quantization in the pair singles x-type instructions. */ |
2517 | #define PSQM PSQ + 1 | |
2518 | { 0x7, 7, 0, 0, PPC_OPERAND_GQR }, | |
066be9f7 | 2519 | |
b80c7270 AM |
2520 | /* Smaller D field for quantization in the pair singles instructions. */ |
2521 | #define PSD PSQM + 1 | |
2522 | { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
066be9f7 | 2523 | |
b80c7270 AM |
2524 | /* The L field in an mtmsrd or A form instruction or R or W in an |
2525 | X form. */ | |
2526 | #define A_L PSD + 1 | |
2527 | #define W A_L | |
2528 | #define X_R A_L | |
2529 | { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
066be9f7 | 2530 | |
b80c7270 AM |
2531 | /* The RMC or CY field in a Z23 form instruction. */ |
2532 | #define RMC A_L + 1 | |
2533 | #define CY RMC | |
2534 | { 0x3, 9, NULL, NULL, 0 }, | |
066be9f7 | 2535 | |
b80c7270 AM |
2536 | #define R RMC + 1 |
2537 | { 0x1, 16, NULL, NULL, 0 }, | |
066be9f7 | 2538 | |
b80c7270 AM |
2539 | #define RIC R + 1 |
2540 | { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
7b934113 | 2541 | |
b80c7270 AM |
2542 | #define PRS RIC + 1 |
2543 | { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2544 | |
b80c7270 AM |
2545 | #define SP PRS + 1 |
2546 | { 0x3, 19, NULL, NULL, 0 }, | |
b9c361e0 | 2547 | |
b80c7270 AM |
2548 | #define S SP + 1 |
2549 | { 0x1, 20, NULL, NULL, 0 }, | |
b9c361e0 | 2550 | |
b80c7270 AM |
2551 | /* The S field in a XL form instruction. */ |
2552 | #define SXL S + 1 | |
9cf7e568 | 2553 | { 0x1, 11, insert_sxl, extract_sxl, PPC_OPERAND_OPTIONAL }, |
b80c7270 AM |
2554 | |
2555 | /* SH field starting at bit position 16. */ | |
9cf7e568 | 2556 | #define SH16 SXL + 1 |
b80c7270 AM |
2557 | /* The DCM and DGM fields in a Z form instruction. */ |
2558 | #define DCM SH16 | |
2559 | #define DGM DCM | |
2560 | { 0x3f, 10, NULL, NULL, 0 }, | |
2561 | ||
2562 | /* The EH field in larx instruction. */ | |
2563 | #define EH SH16 + 1 | |
2564 | { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2565 | |
b80c7270 AM |
2566 | /* The L field in an mtfsf or XFL form instruction. */ |
2567 | /* The A field in a HTM X form instruction. */ | |
2568 | #define XFL_L EH + 1 | |
2569 | #define HTM_A XFL_L | |
2570 | { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, | |
b9c361e0 | 2571 | |
b80c7270 AM |
2572 | /* Xilinx APU related masks and macros */ |
2573 | #define FCRT XFL_L + 1 | |
2574 | #define FCRT_MASK (0x1f << 21) | |
2575 | { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, | |
b9c361e0 | 2576 | |
b80c7270 AM |
2577 | /* Xilinx FSL related masks and macros */ |
2578 | #define FSL FCRT + 1 | |
2579 | #define FSL_MASK (0x1f << 11) | |
2580 | { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, | |
b9c361e0 | 2581 | |
b80c7270 AM |
2582 | /* Xilinx UDI related masks and macros */ |
2583 | #define URT FSL + 1 | |
2584 | { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 2585 | |
b80c7270 AM |
2586 | #define URA URT + 1 |
2587 | { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 2588 | |
b80c7270 AM |
2589 | #define URB URA + 1 |
2590 | { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 2591 | |
b80c7270 AM |
2592 | #define URC URB + 1 |
2593 | { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, | |
e3c2f928 | 2594 | |
b80c7270 AM |
2595 | /* The VLESIMM field in a D form instruction. */ |
2596 | #define VLESIMM URC + 1 | |
2597 | { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, | |
2598 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 2599 | |
b80c7270 AM |
2600 | /* The VLENSIMM field in a D form instruction. */ |
2601 | #define VLENSIMM VLESIMM + 1 | |
2602 | { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, | |
2603 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 2604 | |
b80c7270 AM |
2605 | /* The VLEUIMM field in a D form instruction. */ |
2606 | #define VLEUIMM VLENSIMM + 1 | |
2607 | { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, | |
e3c2f928 | 2608 | |
b80c7270 AM |
2609 | /* The VLEUIMML field in a D form instruction. */ |
2610 | #define VLEUIMML VLEUIMM + 1 | |
2611 | { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, | |
e3c2f928 | 2612 | |
b80c7270 AM |
2613 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is |
2614 | split. */ | |
2615 | #define XS6 VLEUIMML + 1 | |
2616 | #define XT6 XS6 | |
2617 | { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, | |
e3c2f928 | 2618 | |
b80c7270 AM |
2619 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
2620 | #define XSQ6 XT6 + 1 | |
2621 | #define XTQ6 XSQ6 | |
2622 | { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, | |
e3c2f928 | 2623 | |
b80c7270 AM |
2624 | /* The XA field in an XX3 form instruction. This is split. */ |
2625 | #define XA6 XTQ6 + 1 | |
2626 | { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, | |
e3c2f928 | 2627 | |
b80c7270 AM |
2628 | /* The XB field in an XX2 or XX3 form instruction. This is split. */ |
2629 | #define XB6 XA6 + 1 | |
2630 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, | |
e3c2f928 | 2631 | |
98553ad3 PB |
2632 | /* The XA and XB fields in an XX3 form instruction when they must be the same. |
2633 | This is used in extended mnemonics like xvmovdp. This is split. */ | |
2634 | #define XAB6 XB6 + 1 | |
2635 | { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR }, | |
e3c2f928 | 2636 | |
b80c7270 | 2637 | /* The XC field in an XX4 form instruction. This is split. */ |
98553ad3 | 2638 | #define XC6 XAB6 + 1 |
b80c7270 | 2639 | { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, |
e3c2f928 | 2640 | |
b80c7270 AM |
2641 | /* The DM or SHW field in an XX3 form instruction. */ |
2642 | #define DM XC6 + 1 | |
2643 | #define SHW DM | |
2644 | { 0x3, 8, NULL, NULL, 0 }, | |
e3c2f928 | 2645 | |
b80c7270 AM |
2646 | /* The DM field in an extended mnemonic XX3 form instruction. */ |
2647 | #define DMEX DM + 1 | |
2648 | { 0x3, 8, insert_dm, extract_dm, 0 }, | |
e3c2f928 | 2649 | |
b80c7270 AM |
2650 | /* The UIM field in an XX2 form instruction. */ |
2651 | #define UIM DMEX + 1 | |
2652 | /* The 2-bit UIMM field in a VX form instruction. */ | |
2653 | #define UIMM2 UIM | |
2654 | /* The 2-bit L field in a darn instruction. */ | |
2655 | #define LRAND UIM | |
2656 | { 0x3, 16, NULL, NULL, 0 }, | |
e3c2f928 | 2657 | |
b80c7270 AM |
2658 | #define ERAT_T UIM + 1 |
2659 | { 0x7, 21, NULL, NULL, 0 }, | |
e3c2f928 | 2660 | |
b80c7270 AM |
2661 | #define IH ERAT_T + 1 |
2662 | { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
e3c2f928 | 2663 | |
b80c7270 AM |
2664 | /* The 8-bit IMM8 field in a XX1 form instruction. */ |
2665 | #define IMM8 IH + 1 | |
2666 | { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 2667 | |
b80c7270 AM |
2668 | #define VX_OFF IMM8 + 1 |
2669 | { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 }, | |
74081948 AF |
2670 | |
2671 | #define VX_OFF_SPE2 VX_OFF + 1 | |
2672 | { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 }, | |
2673 | ||
2674 | #define BBB VX_OFF_SPE2 + 1 | |
2675 | { 0x7, 13, NULL, NULL, 0 }, | |
2676 | ||
2677 | #define DDD BBB + 1 | |
2678 | #define VX_MASK_DDD (VX_MASK & ~0x1) | |
2679 | { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, | |
2680 | ||
2681 | #define HH DDD + 1 | |
2682 | { 0x3, 13, NULL, NULL, 0 }, | |
b80c7270 AM |
2683 | }; |
2684 | ||
2685 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | |
2686 | / sizeof (powerpc_operands[0])); | |
252b5132 RH |
2687 | \f |
2688 | /* Macros used to form opcodes. */ | |
2689 | ||
2690 | /* The main opcode. */ | |
0f873fd5 | 2691 | #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26) |
252b5132 RH |
2692 | #define OP_MASK OP (0x3f) |
2693 | ||
2694 | /* The main opcode combined with a trap code in the TO field of a D | |
2695 | form instruction. Used for extended mnemonics for the trap | |
2696 | instructions. */ | |
0f873fd5 | 2697 | #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21)) |
252b5132 RH |
2698 | #define OPTO_MASK (OP_MASK | TO_MASK) |
2699 | ||
2700 | /* The main opcode combined with a comparison size bit in the L field | |
2701 | of a D form or X form instruction. Used for extended mnemonics for | |
2702 | the comparison instructions. */ | |
0f873fd5 | 2703 | #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21)) |
252b5132 RH |
2704 | #define OPL_MASK OPL (0x3f,1) |
2705 | ||
b9c361e0 JL |
2706 | /* The main opcode combined with an update code in D form instruction. |
2707 | Used for extended mnemonics for VLE memory instructions. */ | |
0f873fd5 | 2708 | #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8)) |
b9c361e0 JL |
2709 | #define OPVUP_MASK OPVUP (0x3f, 0xff) |
2710 | ||
b80c7270 AM |
2711 | /* The main opcode combined with an update code and the RT fields |
2712 | specified in D form instruction. Used for VLE volatile context | |
2713 | save/restore instructions. */ | |
2714 | #define OPVUPRT(x,vup,rt) \ | |
2715 | (OPVUP (x, vup) \ | |
0f873fd5 | 2716 | | ((((uint64_t)(rt)) & 0x1f) << 21)) |
dfdaec14 AJ |
2717 | #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) |
2718 | ||
252b5132 | 2719 | /* An A form instruction. */ |
b80c7270 AM |
2720 | #define A(op, xop, rc) \ |
2721 | (OP (op) \ | |
0f873fd5 PB |
2722 | | ((((uint64_t)(xop)) & 0x1f) << 1) \ |
2723 | | (((uint64_t)(rc)) & 1)) | |
252b5132 RH |
2724 | #define A_MASK A (0x3f, 0x1f, 1) |
2725 | ||
2726 | /* An A_MASK with the FRB field fixed. */ | |
2727 | #define AFRB_MASK (A_MASK | FRB_MASK) | |
2728 | ||
2729 | /* An A_MASK with the FRC field fixed. */ | |
2730 | #define AFRC_MASK (A_MASK | FRC_MASK) | |
2731 | ||
2732 | /* An A_MASK with the FRA and FRC fields fixed. */ | |
2733 | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) | |
2734 | ||
702f0fb4 | 2735 | /* An AFRAFRC_MASK, but with L bit clear. */ |
0f873fd5 | 2736 | #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16)) |
702f0fb4 | 2737 | |
252b5132 | 2738 | /* A B form instruction. */ |
b80c7270 AM |
2739 | #define B(op, aa, lk) \ |
2740 | (OP (op) \ | |
0f873fd5 | 2741 | | ((((uint64_t)(aa)) & 1) << 1) \ |
b80c7270 | 2742 | | ((lk) & 1)) |
252b5132 RH |
2743 | #define B_MASK B (0x3f, 1, 1) |
2744 | ||
b9c361e0 | 2745 | /* A BD8 form instruction. This is a 16-bit instruction. */ |
b80c7270 | 2746 | #define BD8(op, aa, lk) \ |
0f873fd5 | 2747 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 AM |
2748 | | (((aa) & 1) << 9) \ |
2749 | | (((lk) & 1) << 8)) | |
b9c361e0 JL |
2750 | #define BD8_MASK BD8 (0x3f, 1, 1) |
2751 | ||
2752 | /* Another BD8 form instruction. This is a 16-bit instruction. */ | |
0f873fd5 | 2753 | #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11) |
b9c361e0 JL |
2754 | #define BD8IO_MASK BD8IO (0x1f) |
2755 | ||
2756 | /* A BD8 form instruction for simplified mnemonics. */ | |
2757 | #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) | |
2758 | /* A mask that excludes BO32 and BI32. */ | |
2759 | #define EBD8IO1_MASK 0xf800 | |
2760 | /* A mask that includes BO32 and excludes BI32. */ | |
2761 | #define EBD8IO2_MASK 0xfc00 | |
2762 | /* A mask that include BO32 AND BI32. */ | |
2763 | #define EBD8IO3_MASK 0xff00 | |
2764 | ||
2765 | /* A BD15 form instruction. */ | |
b80c7270 AM |
2766 | #define BD15(op, aa, lk) \ |
2767 | (OP (op) \ | |
0f873fd5 | 2768 | | ((((uint64_t)(aa)) & 0xf) << 22) \ |
b80c7270 | 2769 | | ((lk) & 1)) |
b9c361e0 JL |
2770 | #define BD15_MASK BD15 (0x3f, 0xf, 1) |
2771 | ||
2772 | /* A BD15 form instruction for extended conditional branch mnemonics. */ | |
b80c7270 AM |
2773 | #define EBD15(op, aa, bo, lk) \ |
2774 | (((op) & 0x3f) << 26) \ | |
2775 | | (((aa) & 0xf) << 22) \ | |
2776 | | (((bo) & 0x3) << 20) \ | |
2777 | | ((lk) & 1) | |
b9c361e0 JL |
2778 | #define EBD15_MASK 0xfff00001 |
2779 | ||
b80c7270 AM |
2780 | /* A BD15 form instruction for extended conditional branch mnemonics |
2781 | with BI. */ | |
2782 | #define EBD15BI(op, aa, bo, bi, lk) \ | |
2783 | ((((op) & 0x3f) << 26) \ | |
2784 | | (((aa) & 0xf) << 22) \ | |
2785 | | (((bo) & 0x3) << 20) \ | |
2786 | | (((bi) & 0x3) << 16) \ | |
2787 | | ((lk) & 1)) | |
2788 | ||
b9c361e0 JL |
2789 | #define EBD15BI_MASK 0xfff30001 |
2790 | ||
2791 | /* A BD24 form instruction. */ | |
b80c7270 AM |
2792 | #define BD24(op, aa, lk) \ |
2793 | (OP (op) \ | |
0f873fd5 | 2794 | | ((((uint64_t)(aa)) & 1) << 25) \ |
b80c7270 | 2795 | | ((lk) & 1)) |
b9c361e0 JL |
2796 | #define BD24_MASK BD24 (0x3f, 1, 1) |
2797 | ||
252b5132 | 2798 | /* A B form instruction setting the BO field. */ |
b80c7270 AM |
2799 | #define BBO(op, bo, aa, lk) \ |
2800 | (B ((op), (aa), (lk)) \ | |
0f873fd5 | 2801 | | ((((uint64_t)(bo)) & 0x1f) << 21)) |
252b5132 RH |
2802 | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
2803 | ||
2804 | /* A BBO_MASK with the y bit of the BO field removed. This permits | |
2805 | matching a conditional branch regardless of the setting of the y | |
94efba12 | 2806 | bit. Similarly for the 'at' bits used for power4 branch hints. */ |
0f873fd5 PB |
2807 | #define Y_MASK (((uint64_t) 1) << 21) |
2808 | #define AT1_MASK (((uint64_t) 3) << 21) | |
2809 | #define AT2_MASK (((uint64_t) 9) << 21) | |
802a735e AM |
2810 | #define BBOY_MASK (BBO_MASK &~ Y_MASK) |
2811 | #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) | |
252b5132 RH |
2812 | |
2813 | /* A B form instruction setting the BO field and the condition bits of | |
2814 | the BI field. */ | |
2815 | #define BBOCB(op, bo, cb, aa, lk) \ | |
0f873fd5 | 2816 | (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16)) |
252b5132 RH |
2817 | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
2818 | ||
2819 | /* A BBOCB_MASK with the y bit of the BO field removed. */ | |
2820 | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) | |
802a735e AM |
2821 | #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
2822 | #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) | |
252b5132 RH |
2823 | |
2824 | /* A BBOYCB_MASK in which the BI field is fixed. */ | |
2825 | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) | |
802a735e | 2826 | #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
252b5132 | 2827 | |
b9c361e0 | 2828 | /* A VLE C form instruction. */ |
0f873fd5 | 2829 | #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1)) |
b9c361e0 | 2830 | #define C_LK_MASK C_LK(0x7fff, 1) |
0f873fd5 | 2831 | #define C(x) ((((uint64_t)(x)) & 0xffff)) |
b9c361e0 JL |
2832 | #define C_MASK C(0xffff) |
2833 | ||
23976049 | 2834 | /* An Context form instruction. */ |
0f873fd5 | 2835 | #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7)) |
fdd12ef3 | 2836 | #define CTX_MASK CTX(0x3f, 0x7) |
23976049 EZ |
2837 | |
2838 | /* An User Context form instruction. */ | |
0f873fd5 | 2839 | #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) |
fdd12ef3 | 2840 | #define UCTX_MASK UCTX(0x3f, 0x1f) |
23976049 | 2841 | |
252b5132 RH |
2842 | /* The main opcode mask with the RA field clear. */ |
2843 | #define DRA_MASK (OP_MASK | RA_MASK) | |
2844 | ||
a680de9a PB |
2845 | /* A DQ form VSX instruction. */ |
2846 | #define DQX(op, xop) (OP (op) | ((xop) & 0x7)) | |
2847 | #define DQX_MASK DQX (0x3f, 7) | |
2848 | ||
252b5132 RH |
2849 | /* A DS form instruction. */ |
2850 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) | |
2851 | #define DS_MASK DSO (0x3f, 3) | |
2852 | ||
a680de9a | 2853 | /* An DX form instruction. */ |
0f873fd5 | 2854 | #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
a680de9a | 2855 | #define DX_MASK DX (0x3f, 0x1f) |
1437d063 PB |
2856 | /* An DX form instruction with the D bits specified. */ |
2857 | #define NODX_MASK (DX_MASK | 0x1fffc1) | |
a680de9a | 2858 | |
23976049 | 2859 | /* An EVSEL form instruction. */ |
0f873fd5 | 2860 | #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3) |
23976049 EZ |
2861 | #define EVSEL_MASK EVSEL(0x3f, 0xff) |
2862 | ||
b9c361e0 | 2863 | /* An IA16 form instruction. */ |
0f873fd5 | 2864 | #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
2865 | #define IA16_MASK IA16(0x3f, 0x1f) |
2866 | ||
2867 | /* An I16A form instruction. */ | |
0f873fd5 | 2868 | #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
2869 | #define I16A_MASK I16A(0x3f, 0x1f) |
2870 | ||
2871 | /* An I16L form instruction. */ | |
0f873fd5 | 2872 | #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
2873 | #define I16L_MASK I16L(0x3f, 0x1f) |
2874 | ||
2875 | /* An IM7 form instruction. */ | |
0f873fd5 | 2876 | #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11) |
b9c361e0 JL |
2877 | #define IM7_MASK IM7(0x1f) |
2878 | ||
252b5132 RH |
2879 | /* An M form instruction. */ |
2880 | #define M(op, rc) (OP (op) | ((rc) & 1)) | |
2881 | #define M_MASK M (0x3f, 1) | |
2882 | ||
b9c361e0 | 2883 | /* An LI20 form instruction. */ |
0f873fd5 | 2884 | #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15) |
b9c361e0 JL |
2885 | #define LI20_MASK LI20(0x3f, 0x1) |
2886 | ||
252b5132 | 2887 | /* An M form instruction with the ME field specified. */ |
b80c7270 AM |
2888 | #define MME(op, me, rc) \ |
2889 | (M ((op), (rc)) \ | |
0f873fd5 | 2890 | | ((((uint64_t)(me)) & 0x1f) << 1)) |
252b5132 RH |
2891 | |
2892 | /* An M_MASK with the MB and ME fields fixed. */ | |
2893 | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) | |
2894 | ||
2895 | /* An M_MASK with the SH and ME fields fixed. */ | |
2896 | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) | |
2897 | ||
2898 | /* An MD form instruction. */ | |
b80c7270 AM |
2899 | #define MD(op, xop, rc) \ |
2900 | (OP (op) \ | |
0f873fd5 | 2901 | | ((((uint64_t)(xop)) & 0x7) << 2) \ |
b80c7270 | 2902 | | ((rc) & 1)) |
252b5132 RH |
2903 | #define MD_MASK MD (0x3f, 0x7, 1) |
2904 | ||
2905 | /* An MD_MASK with the MB field fixed. */ | |
2906 | #define MDMB_MASK (MD_MASK | MB6_MASK) | |
2907 | ||
2908 | /* An MD_MASK with the SH field fixed. */ | |
2909 | #define MDSH_MASK (MD_MASK | SH6_MASK) | |
2910 | ||
2911 | /* An MDS form instruction. */ | |
b80c7270 AM |
2912 | #define MDS(op, xop, rc) \ |
2913 | (OP (op) \ | |
0f873fd5 | 2914 | | ((((uint64_t)(xop)) & 0xf) << 1) \ |
b80c7270 | 2915 | | ((rc) & 1)) |
252b5132 RH |
2916 | #define MDS_MASK MDS (0x3f, 0xf, 1) |
2917 | ||
2918 | /* An MDS_MASK with the MB field fixed. */ | |
2919 | #define MDSMB_MASK (MDS_MASK | MB6_MASK) | |
2920 | ||
2921 | /* An SC form instruction. */ | |
b80c7270 AM |
2922 | #define SC(op, sa, lk) \ |
2923 | (OP (op) \ | |
0f873fd5 | 2924 | | ((((uint64_t)(sa)) & 1) << 1) \ |
b80c7270 AM |
2925 | | ((lk) & 1)) |
2926 | #define SC_MASK \ | |
2927 | (OP_MASK \ | |
0f873fd5 PB |
2928 | | (((uint64_t) 0x3ff) << 16) \ |
2929 | | (((uint64_t) 1) << 1) \ | |
b80c7270 | 2930 | | 1) |
252b5132 | 2931 | |
b9c361e0 | 2932 | /* An SCI8 form instruction. */ |
0f873fd5 | 2933 | #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11)) |
b9c361e0 JL |
2934 | #define SCI8_MASK SCI8(0x3f, 0x1f) |
2935 | ||
2936 | /* An SCI8 form instruction. */ | |
b80c7270 AM |
2937 | #define SCI8BF(op, fop, xop) \ |
2938 | (OP (op) \ | |
0f873fd5 | 2939 | | ((((uint64_t)(xop)) & 0x1f) << 11) \ |
b80c7270 | 2940 | | (((fop) & 7) << 23)) |
b9c361e0 JL |
2941 | #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) |
2942 | ||
2943 | /* An SD4 form instruction. This is a 16-bit instruction. */ | |
0f873fd5 | 2944 | #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12) |
b9c361e0 JL |
2945 | #define SD4_MASK SD4(0xf) |
2946 | ||
2947 | /* An SE_IM5 form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 2948 | #define SE_IM5(op, xop) \ |
0f873fd5 | 2949 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 2950 | | (((xop) & 0x1) << 9)) |
b9c361e0 JL |
2951 | #define SE_IM5_MASK SE_IM5(0x3f, 1) |
2952 | ||
2953 | /* An SE_R form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 2954 | #define SE_R(op, xop) \ |
0f873fd5 | 2955 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 2956 | | (((xop) & 0x3f) << 4)) |
b9c361e0 JL |
2957 | #define SE_R_MASK SE_R(0x3f, 0x3f) |
2958 | ||
2959 | /* An SE_RR form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 2960 | #define SE_RR(op, xop) \ |
0f873fd5 | 2961 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 2962 | | (((xop) & 0x3) << 8)) |
b9c361e0 JL |
2963 | #define SE_RR_MASK SE_RR(0x3f, 3) |
2964 | ||
2965 | /* A VX form instruction. */ | |
0f873fd5 | 2966 | #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) |
786e2c0f | 2967 | |
112290ab | 2968 | /* The mask for an VX form instruction. */ |
786e2c0f C |
2969 | #define VX_MASK VX(0x3f, 0x7ff) |
2970 | ||
e3c2f928 | 2971 | /* A VX LSP form instruction. */ |
0f873fd5 | 2972 | #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff)) |
e3c2f928 AF |
2973 | |
2974 | /* The mask for an VX LSP form instruction. */ | |
2975 | #define VX_LSP_MASK VX_LSP(0x3f, 0xffff) | |
2976 | #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc) | |
2977 | ||
74081948 AF |
2978 | /* Additional format of VX SPE2 form instruction. */ |
2979 | #define VX_RA_CONST(op, xop, bits11_15) \ | |
2980 | (OP (op) \ | |
0f873fd5 PB |
2981 | | (((uint64_t)(bits11_15) & 0x1f) << 16) \ |
2982 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
2983 | #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f) |
2984 | ||
2985 | #define VX_RB_CONST(op, xop, bits16_20) \ | |
2986 | (OP (op) \ | |
0f873fd5 PB |
2987 | | (((uint64_t)(bits16_20) & 0x1f) << 11) \ |
2988 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
2989 | #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f) |
2990 | ||
2991 | #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8) | |
2992 | ||
2993 | #define VX_SPE_CRFD(op, xop, bits9_10) \ | |
2994 | (OP (op) \ | |
0f873fd5 PB |
2995 | | (((uint64_t)(bits9_10) & 0x3) << 21) \ |
2996 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
2997 | #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3) |
2998 | ||
2999 | #define VX_SPE2_CLR(op, xop, bit16) \ | |
3000 | (OP (op) \ | |
0f873fd5 PB |
3001 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3002 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3003 | #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1) |
3004 | ||
3005 | #define VX_SPE2_SPLATB(op, xop, bits19_20) \ | |
3006 | (OP (op) \ | |
0f873fd5 PB |
3007 | | (((uint64_t)(bits19_20) & 0x3) << 11) \ |
3008 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3009 | #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3) |
3010 | ||
3011 | #define VX_SPE2_OCTET(op, xop, bits16_17) \ | |
3012 | (OP (op) \ | |
0f873fd5 PB |
3013 | | (((uint64_t)(bits16_17) & 0x3) << 14) \ |
3014 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3015 | #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7) |
3016 | ||
3017 | #define VX_SPE2_DDHH(op, xop, bit16) \ | |
3018 | (OP (op) \ | |
0f873fd5 PB |
3019 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3020 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3021 | #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1) |
3022 | ||
3023 | #define VX_SPE2_HH(op, xop, bit16, bits19_20) \ | |
3024 | (OP (op) \ | |
0f873fd5 PB |
3025 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3026 | | (((uint64_t)(bits19_20) & 0x3) << 11) \ | |
3027 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3028 | #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3) |
3029 | ||
3030 | #define VX_SPE2_EVMAR(op, xop) \ | |
3031 | (OP (op) \ | |
0f873fd5 PB |
3032 | | ((uint64_t)(0x1) << 11) \ |
3033 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3034 | #define VX_SPE2_EVMAR_MASK \ |
3035 | (VX_SPE2_EVMAR(0x3f, 0x7ff) \ | |
0f873fd5 | 3036 | | ((uint64_t)(0x1) << 11)) |
74081948 | 3037 | |
fb048c26 PB |
3038 | /* A VX_MASK with the VA field fixed. */ |
3039 | #define VXVA_MASK (VX_MASK | (0x1f << 16)) | |
3040 | ||
3041 | /* A VX_MASK with the VB field fixed. */ | |
3042 | #define VXVB_MASK (VX_MASK | (0x1f << 11)) | |
3043 | ||
3044 | /* A VX_MASK with the VA and VB fields fixed. */ | |
3045 | #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) | |
3046 | ||
3047 | /* A VX_MASK with the VD and VA fields fixed. */ | |
3048 | #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) | |
3049 | ||
3050 | /* A VX_MASK with a UIMM4 field. */ | |
3051 | #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) | |
3052 | ||
3053 | /* A VX_MASK with a UIMM3 field. */ | |
3054 | #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) | |
3055 | ||
3056 | /* A VX_MASK with a UIMM2 field. */ | |
3057 | #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) | |
3058 | ||
c0637f3a PB |
3059 | /* A VX_MASK with a PS field. */ |
3060 | #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) | |
3061 | ||
a680de9a PB |
3062 | /* A VX_MASK with the VA field fixed with a PS field. */ |
3063 | #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) | |
3064 | ||
b9c361e0 | 3065 | /* A VA form instruction. */ |
0f873fd5 | 3066 | #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f)) |
786e2c0f | 3067 | |
112290ab | 3068 | /* The mask for an VA form instruction. */ |
2613489e | 3069 | #define VXA_MASK VXA(0x3f, 0x3f) |
786e2c0f | 3070 | |
382c72e9 PB |
3071 | /* A VXA_MASK with a SHB field. */ |
3072 | #define VXASHB_MASK (VXA_MASK | (1 << 10)) | |
3073 | ||
b9c361e0 | 3074 | /* A VXR form instruction. */ |
b80c7270 AM |
3075 | #define VXR(op, xop, rc) \ |
3076 | (OP (op) \ | |
0f873fd5 PB |
3077 | | (((uint64_t)(rc) & 1) << 10) \ |
3078 | | (((uint64_t)(xop)) & 0x3ff)) | |
786e2c0f | 3079 | |
112290ab | 3080 | /* The mask for a VXR form instruction. */ |
786e2c0f C |
3081 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
3082 | ||
a680de9a PB |
3083 | /* A VX form instruction with a VA tertiary opcode. */ |
3084 | #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) | |
3085 | ||
0f873fd5 | 3086 | #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
6fd3a02d PB |
3087 | #define VXASH_MASK VXASH (0x3f, 0x1f) |
3088 | ||
252b5132 | 3089 | /* An X form instruction. */ |
0f873fd5 | 3090 | #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) |
252b5132 | 3091 | |
a680de9a PB |
3092 | /* A X form instruction for Quad-Precision FP Instructions. */ |
3093 | #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) | |
3094 | ||
b9c361e0 | 3095 | /* An EX form instruction. */ |
0f873fd5 | 3096 | #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) |
b9c361e0 JL |
3097 | |
3098 | /* The mask for an EX form instruction. */ | |
3099 | #define EX_MASK EX (0x3f, 0x7ff) | |
3100 | ||
066be9f7 | 3101 | /* An XX2 form instruction. */ |
0f873fd5 | 3102 | #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2)) |
066be9f7 | 3103 | |
a680de9a PB |
3104 | /* A XX2 form instruction with the VA bits specified. */ |
3105 | #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) | |
3106 | ||
9b4e5766 | 3107 | /* An XX3 form instruction. */ |
0f873fd5 | 3108 | #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3)) |
9b4e5766 | 3109 | |
066be9f7 | 3110 | /* An XX3 form instruction with the RC bit specified. */ |
b80c7270 AM |
3111 | #define XX3RC(op, xop, rc) \ |
3112 | (OP (op) \ | |
0f873fd5 PB |
3113 | | (((uint64_t)(rc) & 1) << 10) \ |
3114 | | ((((uint64_t)(xop)) & 0x7f) << 3)) | |
066be9f7 PB |
3115 | |
3116 | /* An XX4 form instruction. */ | |
0f873fd5 | 3117 | #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4)) |
9b4e5766 | 3118 | |
702f0fb4 | 3119 | /* A Z form instruction. */ |
0f873fd5 | 3120 | #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1)) |
702f0fb4 | 3121 | |
252b5132 RH |
3122 | /* An X form instruction with the RC bit specified. */ |
3123 | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) | |
3124 | ||
a680de9a PB |
3125 | /* A X form instruction for Quad-Precision FP Instructions with RC bit. */ |
3126 | #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) | |
3127 | ||
6fd3a02d | 3128 | /* An X form instruction with the RA bits specified as two ops. */ |
b80c7270 AM |
3129 | #define XMMF(op, xop, mop0, mop1) \ |
3130 | (X ((op), (xop)) \ | |
3131 | | ((mop0) & 3) << 19 \ | |
3132 | | ((mop1) & 7) << 16) | |
6fd3a02d | 3133 | |
702f0fb4 PB |
3134 | /* A Z form instruction with the RC bit specified. */ |
3135 | #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) | |
3136 | ||
252b5132 RH |
3137 | /* The mask for an X form instruction. */ |
3138 | #define X_MASK XRC (0x3f, 0x3ff, 1) | |
3139 | ||
a680de9a PB |
3140 | /* The mask for an X form instruction with the BF bits specified. */ |
3141 | #define XBF_MASK (X_MASK | (3 << 21)) | |
3142 | ||
b80c7270 AM |
3143 | /* An X form wait instruction with everything filled in except the WC |
3144 | field. */ | |
e0d602ec BE |
3145 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
3146 | ||
9b4e5766 PB |
3147 | /* The mask for an XX1 form instruction. */ |
3148 | #define XX1_MASK X (0x3f, 0x3ff) | |
3149 | ||
c0637f3a PB |
3150 | /* An XX1_MASK with the RB field fixed. */ |
3151 | #define XX1RB_MASK (XX1_MASK | RB_MASK) | |
3152 | ||
066be9f7 PB |
3153 | /* The mask for an XX2 form instruction. */ |
3154 | #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) | |
3155 | ||
3156 | /* The mask for an XX2 form instruction with the UIM bits specified. */ | |
3157 | #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) | |
3158 | ||
a680de9a PB |
3159 | /* The mask for an XX2 form instruction with the 4 UIM bits specified. */ |
3160 | #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) | |
3161 | ||
066be9f7 PB |
3162 | /* The mask for an XX2 form instruction with the BF bits specified. */ |
3163 | #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) | |
3164 | ||
b80c7270 AM |
3165 | /* The mask for an XX2 form instruction with the BF and DCMX bits |
3166 | specified. */ | |
a680de9a PB |
3167 | #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) |
3168 | ||
b80c7270 AM |
3169 | /* The mask for an XX2 form instruction with a split DCMX bits |
3170 | specified. */ | |
a680de9a PB |
3171 | #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) |
3172 | ||
9b4e5766 PB |
3173 | /* The mask for an XX3 form instruction. */ |
3174 | #define XX3_MASK XX3 (0x3f, 0xff) | |
3175 | ||
066be9f7 PB |
3176 | /* The mask for an XX3 form instruction with the BF bits specified. */ |
3177 | #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) | |
3178 | ||
b80c7270 AM |
3179 | /* The mask for an XX3 form instruction with the DM or SHW bits |
3180 | specified. */ | |
9b4e5766 | 3181 | #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) |
066be9f7 PB |
3182 | #define XX3SHW_MASK XX3DM_MASK |
3183 | ||
3184 | /* The mask for an XX4 form instruction. */ | |
3185 | #define XX4_MASK XX4 (0x3f, 0x3) | |
3186 | ||
b80c7270 AM |
3187 | /* An X form wait instruction with everything filled in except the WC |
3188 | field. */ | |
066be9f7 | 3189 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
9b4e5766 | 3190 | |
6fd3a02d PB |
3191 | /* The mask for an XMMF form instruction. */ |
3192 | #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) | |
3193 | ||
702f0fb4 PB |
3194 | /* The mask for a Z form instruction. */ |
3195 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) | |
0bbdef92 | 3196 | #define Z2_MASK ZRC (0x3f, 0xff, 1) |
702f0fb4 | 3197 | |
a680de9a | 3198 | /* An X_MASK with the RA/VA field fixed. */ |
252b5132 | 3199 | #define XRA_MASK (X_MASK | RA_MASK) |
a680de9a | 3200 | #define XVA_MASK XRA_MASK |
252b5132 | 3201 | |
a680de9a | 3202 | /* An XRA_MASK with the A_L/W field clear. */ |
0f873fd5 | 3203 | #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16)) |
a680de9a | 3204 | #define XRLA_MASK XWRA_MASK |
ea192fa3 | 3205 | |
252b5132 RH |
3206 | /* An X_MASK with the RB field fixed. */ |
3207 | #define XRB_MASK (X_MASK | RB_MASK) | |
3208 | ||
3209 | /* An X_MASK with the RT field fixed. */ | |
3210 | #define XRT_MASK (X_MASK | RT_MASK) | |
3211 | ||
702f0fb4 | 3212 | /* An XRT_MASK mask with the L bits clear. */ |
0f873fd5 | 3213 | #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21)) |
702f0fb4 | 3214 | |
252b5132 RH |
3215 | /* An X_MASK with the RA and RB fields fixed. */ |
3216 | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) | |
3217 | ||
a680de9a PB |
3218 | /* An XBF_MASK with the RA and RB fields fixed. */ |
3219 | #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) | |
3220 | ||
112290ab | 3221 | /* An XRARB_MASK, but with the L bit clear. */ |
0f873fd5 | 3222 | #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16)) |
5ae2e65e | 3223 | |
a680de9a | 3224 | /* An XRARB_MASK, but with the L bits in a darn instruction clear. */ |
0f873fd5 | 3225 | #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16)) |
a680de9a | 3226 | |
252b5132 RH |
3227 | /* An X_MASK with the RT and RA fields fixed. */ |
3228 | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) | |
3229 | ||
5817ffd1 PB |
3230 | /* An X_MASK with the RT and RB fields fixed. */ |
3231 | #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) | |
3232 | ||
98acc1c5 | 3233 | /* An XRTRA_MASK, but with L bit clear. */ |
0f873fd5 | 3234 | #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21)) |
98acc1c5 | 3235 | |
5817ffd1 PB |
3236 | /* An X_MASK with the RT, RA and RB fields fixed. */ |
3237 | #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) | |
3238 | ||
3239 | /* An XRTRARB_MASK, but with L bit clear. */ | |
0f873fd5 | 3240 | #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21)) |
5817ffd1 PB |
3241 | |
3242 | /* An XRTRARB_MASK, but with A bit clear. */ | |
0f873fd5 | 3243 | #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25)) |
5817ffd1 PB |
3244 | |
3245 | /* An XRTRARB_MASK, but with BF bits clear. */ | |
0f873fd5 | 3246 | #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23)) |
5817ffd1 | 3247 | |
f3806e43 | 3248 | /* An X form instruction with the L bit specified. */ |
b80c7270 AM |
3249 | #define XOPL(op, xop, l) \ |
3250 | (X ((op), (xop)) \ | |
0f873fd5 | 3251 | | ((((uint64_t)(l)) & 1) << 21)) |
252b5132 | 3252 | |
e0d602ec | 3253 | /* An X form instruction with the L bits specified. */ |
b80c7270 AM |
3254 | #define XOPL2(op, xop, l) \ |
3255 | (X ((op), (xop)) \ | |
0f873fd5 | 3256 | | ((((uint64_t)(l)) & 3) << 21)) |
e0d602ec | 3257 | |
5817ffd1 | 3258 | /* An X form instruction with the L bit and RC bit specified. */ |
b80c7270 AM |
3259 | #define XRCL(op, xop, l, rc) \ |
3260 | (XRC ((op), (xop), (rc)) \ | |
0f873fd5 | 3261 | | ((((uint64_t)(l)) & 1) << 21)) |
5817ffd1 | 3262 | |
19a6653c | 3263 | /* An X form instruction with RT fields specified */ |
b80c7270 AM |
3264 | #define XRT(op, xop, rt) \ |
3265 | (X ((op), (xop)) \ | |
0f873fd5 | 3266 | | ((((uint64_t)(rt)) & 0x1f) << 21)) |
19a6653c AM |
3267 | |
3268 | /* An X form instruction with RT and RA fields specified */ | |
b80c7270 AM |
3269 | #define XRTRA(op, xop, rt, ra) \ |
3270 | (X ((op), (xop)) \ | |
0f873fd5 PB |
3271 | | ((((uint64_t)(rt)) & 0x1f) << 21) \ |
3272 | | ((((uint64_t)(ra)) & 0x1f) << 16)) | |
19a6653c | 3273 | |
252b5132 | 3274 | /* The mask for an X form comparison instruction. */ |
0f873fd5 | 3275 | #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22)) |
252b5132 | 3276 | |
520ceea4 BE |
3277 | /* The mask for an X form comparison instruction with the L field |
3278 | fixed. */ | |
0f873fd5 | 3279 | #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21)) |
252b5132 RH |
3280 | |
3281 | /* An X form trap instruction with the TO field specified. */ | |
b80c7270 AM |
3282 | #define XTO(op, xop, to) \ |
3283 | (X ((op), (xop)) \ | |
0f873fd5 | 3284 | | ((((uint64_t)(to)) & 0x1f) << 21)) |
252b5132 RH |
3285 | #define XTO_MASK (X_MASK | TO_MASK) |
3286 | ||
e0c21649 | 3287 | /* An X form tlb instruction with the SH field specified. */ |
b80c7270 AM |
3288 | #define XTLB(op, xop, sh) \ |
3289 | (X ((op), (xop)) \ | |
0f873fd5 | 3290 | | ((((uint64_t)(sh)) & 0x1f) << 11)) |
e0c21649 GK |
3291 | #define XTLB_MASK (X_MASK | SH_MASK) |
3292 | ||
6ba045b1 | 3293 | /* An X form sync instruction. */ |
b80c7270 AM |
3294 | #define XSYNC(op, xop, l) \ |
3295 | (X ((op), (xop)) \ | |
0f873fd5 | 3296 | | ((((uint64_t)(l)) & 3) << 21)) |
6ba045b1 | 3297 | |
b80c7270 AM |
3298 | /* An X form sync instruction with everything filled in except the LS |
3299 | field. */ | |
6ba045b1 AM |
3300 | #define XSYNC_MASK (0xff9fffff) |
3301 | ||
b80c7270 AM |
3302 | /* An X form sync instruction with everything filled in except the L |
3303 | and E fields. */ | |
aea77599 AM |
3304 | #define XSYNCLE_MASK (0xff90ffff) |
3305 | ||
702f0fb4 | 3306 | /* An X_MASK, but with the EH bit clear. */ |
0f873fd5 | 3307 | #define XEH_MASK (X_MASK & ~((uint64_t )1)) |
702f0fb4 | 3308 | |
f5c120c5 | 3309 | /* An X form AltiVec dss instruction. */ |
0f873fd5 | 3310 | #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25)) |
f5c120c5 MG |
3311 | #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) |
3312 | ||
252b5132 | 3313 | /* An XFL form instruction. */ |
b80c7270 AM |
3314 | #define XFL(op, xop, rc) \ |
3315 | (OP (op) \ | |
0f873fd5 PB |
3316 | | ((((uint64_t)(xop)) & 0x3ff) << 1) \ |
3317 | | (((uint64_t)(rc)) & 1)) | |
ea192fa3 | 3318 | #define XFL_MASK XFL (0x3f, 0x3ff, 1) |
252b5132 | 3319 | |
23976049 | 3320 | /* An X form isel instruction. */ |
0f873fd5 | 3321 | #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
de866fcc | 3322 | #define XISEL_MASK XISEL(0x3f, 0x1f) |
23976049 | 3323 | |
252b5132 | 3324 | /* An XL form instruction with the LK field set to 0. */ |
0f873fd5 | 3325 | #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) |
252b5132 RH |
3326 | |
3327 | /* An XL form instruction which uses the LK field. */ | |
3328 | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) | |
3329 | ||
3330 | /* The mask for an XL form instruction. */ | |
3331 | #define XL_MASK XLLK (0x3f, 0x3ff, 1) | |
3332 | ||
c0637f3a PB |
3333 | /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ |
3334 | #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) | |
3335 | ||
252b5132 RH |
3336 | /* An XL form instruction which explicitly sets the BO field. */ |
3337 | #define XLO(op, bo, xop, lk) \ | |
0f873fd5 | 3338 | (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21)) |
252b5132 RH |
3339 | #define XLO_MASK (XL_MASK | BO_MASK) |
3340 | ||
3341 | /* An XL form instruction which explicitly sets the y bit of the BO | |
3342 | field. */ | |
b80c7270 AM |
3343 | #define XLYLK(op, xop, y, lk) \ |
3344 | (XLLK ((op), (xop), (lk)) \ | |
0f873fd5 | 3345 | | ((((uint64_t)(y)) & 1) << 21)) |
252b5132 RH |
3346 | #define XLYLK_MASK (XL_MASK | Y_MASK) |
3347 | ||
3348 | /* An XL form instruction which sets the BO field and the condition | |
3349 | bits of the BI field. */ | |
3350 | #define XLOCB(op, bo, cb, xop, lk) \ | |
0f873fd5 | 3351 | (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16)) |
252b5132 RH |
3352 | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
3353 | ||
3354 | /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ | |
3355 | #define XLBB_MASK (XL_MASK | BB_MASK) | |
3356 | #define XLYBB_MASK (XLYLK_MASK | BB_MASK) | |
3357 | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) | |
3358 | ||
d0618d1c AM |
3359 | /* A mask for branch instructions using the BH field. */ |
3360 | #define XLBH_MASK (XL_MASK | (0x1c << 11)) | |
3361 | ||
252b5132 RH |
3362 | /* An XL_MASK with the BO and BB fields fixed. */ |
3363 | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) | |
3364 | ||
3365 | /* An XL_MASK with the BO, BI and BB fields fixed. */ | |
3366 | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) | |
3367 | ||
e01d869a | 3368 | /* An X form mbar instruction with MO field. */ |
b80c7270 AM |
3369 | #define XMBAR(op, xop, mo) \ |
3370 | (X ((op), (xop)) \ | |
0f873fd5 | 3371 | | ((((uint64_t)(mo)) & 1) << 21)) |
e01d869a | 3372 | |
252b5132 | 3373 | /* An XO form instruction. */ |
b80c7270 AM |
3374 | #define XO(op, xop, oe, rc) \ |
3375 | (OP (op) \ | |
0f873fd5 PB |
3376 | | ((((uint64_t)(xop)) & 0x1ff) << 1) \ |
3377 | | ((((uint64_t)(oe)) & 1) << 10) \ | |
b80c7270 | 3378 | | (((unsigned long)(rc)) & 1)) |
252b5132 RH |
3379 | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
3380 | ||
3381 | /* An XO_MASK with the RB field fixed. */ | |
3382 | #define XORB_MASK (XO_MASK | RB_MASK) | |
3383 | ||
c3d65c1c | 3384 | /* An XOPS form instruction for paired singles. */ |
b80c7270 AM |
3385 | #define XOPS(op, xop, rc) \ |
3386 | (OP (op) \ | |
0f873fd5 PB |
3387 | | ((((uint64_t)(xop)) & 0x3ff) << 1) \ |
3388 | | (((uint64_t)(rc)) & 1)) | |
c3d65c1c BE |
3389 | #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) |
3390 | ||
3391 | ||
252b5132 | 3392 | /* An XS form instruction. */ |
b80c7270 AM |
3393 | #define XS(op, xop, rc) \ |
3394 | (OP (op) \ | |
0f873fd5 PB |
3395 | | ((((uint64_t)(xop)) & 0x1ff) << 2) \ |
3396 | | (((uint64_t)(rc)) & 1)) | |
252b5132 RH |
3397 | #define XS_MASK XS (0x3f, 0x1ff, 1) |
3398 | ||
3399 | /* A mask for the FXM version of an XFX form instruction. */ | |
98e69875 | 3400 | #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) |
252b5132 RH |
3401 | |
3402 | /* An XFX form instruction with the FXM field filled in. */ | |
b80c7270 AM |
3403 | #define XFXM(op, xop, fxm, p4) \ |
3404 | (X ((op), (xop)) \ | |
0f873fd5 PB |
3405 | | ((((uint64_t)(fxm)) & 0xff) << 12) \ |
3406 | | ((uint64_t)(p4) << 20)) | |
252b5132 RH |
3407 | |
3408 | /* An XFX form instruction with the SPR field filled in. */ | |
b80c7270 AM |
3409 | #define XSPR(op, xop, spr) \ |
3410 | (X ((op), (xop)) \ | |
0f873fd5 PB |
3411 | | ((((uint64_t)(spr)) & 0x1f) << 16) \ |
3412 | | ((((uint64_t)(spr)) & 0x3e0) << 6)) | |
252b5132 RH |
3413 | #define XSPR_MASK (X_MASK | SPR_MASK) |
3414 | ||
3415 | /* An XFX form instruction with the SPR field filled in except for the | |
3416 | SPRBAT field. */ | |
3417 | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) | |
3418 | ||
fa758a70 AC |
3419 | /* An XFX form instruction with the SPR field filled in except for the |
3420 | SPRGQR field. */ | |
3421 | #define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK) | |
3422 | ||
252b5132 RH |
3423 | /* An XFX form instruction with the SPR field filled in except for the |
3424 | SPRG field. */ | |
b84bf58a | 3425 | #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) |
252b5132 RH |
3426 | |
3427 | /* An X form instruction with everything filled in except the E field. */ | |
3428 | #define XE_MASK (0xffff7fff) | |
3429 | ||
23976049 | 3430 | /* An X form user context instruction. */ |
0f873fd5 | 3431 | #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) |
23976049 EZ |
3432 | #define XUC_MASK XUC(0x3f, 0x1f) |
3433 | ||
c3d65c1c | 3434 | /* An XW form instruction. */ |
b80c7270 AM |
3435 | #define XW(op, xop, rc) \ |
3436 | (OP (op) \ | |
0f873fd5 | 3437 | | ((((uint64_t)(xop)) & 0x3f) << 1) \ |
b80c7270 | 3438 | | ((rc) & 1)) |
c3d65c1c BE |
3439 | /* The mask for a G form instruction. rc not supported at present. */ |
3440 | #define XW_MASK XW (0x3f, 0x3f, 0) | |
3441 | ||
081ba1b3 | 3442 | /* An APU form instruction. */ |
b80c7270 AM |
3443 | #define APU(op, xop, rc) \ |
3444 | (OP (op) \ | |
0f873fd5 | 3445 | | (((uint64_t)(xop)) & 0x3ff) << 1 \ |
b80c7270 | 3446 | | ((rc) & 1)) |
081ba1b3 AM |
3447 | |
3448 | /* The mask for an APU form instruction. */ | |
3449 | #define APU_MASK APU (0x3f, 0x3ff, 1) | |
3450 | #define APU_RT_MASK (APU_MASK | RT_MASK) | |
3451 | #define APU_RA_MASK (APU_MASK | RA_MASK) | |
3452 | ||
252b5132 RH |
3453 | /* The BO encodings used in extended conditional branch mnemonics. */ |
3454 | #define BODNZF (0x0) | |
3455 | #define BODNZFP (0x1) | |
3456 | #define BODZF (0x2) | |
3457 | #define BODZFP (0x3) | |
252b5132 RH |
3458 | #define BODNZT (0x8) |
3459 | #define BODNZTP (0x9) | |
3460 | #define BODZT (0xa) | |
3461 | #define BODZTP (0xb) | |
802a735e AM |
3462 | |
3463 | #define BOF (0x4) | |
3464 | #define BOFP (0x5) | |
94efba12 AM |
3465 | #define BOFM4 (0x6) |
3466 | #define BOFP4 (0x7) | |
252b5132 RH |
3467 | #define BOT (0xc) |
3468 | #define BOTP (0xd) | |
94efba12 AM |
3469 | #define BOTM4 (0xe) |
3470 | #define BOTP4 (0xf) | |
802a735e | 3471 | |
252b5132 RH |
3472 | #define BODNZ (0x10) |
3473 | #define BODNZP (0x11) | |
3474 | #define BODZ (0x12) | |
3475 | #define BODZP (0x13) | |
94efba12 AM |
3476 | #define BODNZM4 (0x18) |
3477 | #define BODNZP4 (0x19) | |
3478 | #define BODZM4 (0x1a) | |
3479 | #define BODZP4 (0x1b) | |
802a735e | 3480 | |
252b5132 RH |
3481 | #define BOU (0x14) |
3482 | ||
b9c361e0 JL |
3483 | /* The BO16 encodings used in extended VLE conditional branch mnemonics. */ |
3484 | #define BO16F (0x0) | |
3485 | #define BO16T (0x1) | |
3486 | ||
3487 | /* The BO32 encodings used in extended VLE conditional branch mnemonics. */ | |
3488 | #define BO32F (0x0) | |
3489 | #define BO32T (0x1) | |
3490 | #define BO32DNZ (0x2) | |
3491 | #define BO32DZ (0x3) | |
3492 | ||
252b5132 RH |
3493 | /* The BI condition bit encodings used in extended conditional branch |
3494 | mnemonics. */ | |
3495 | #define CBLT (0) | |
3496 | #define CBGT (1) | |
3497 | #define CBEQ (2) | |
3498 | #define CBSO (3) | |
3499 | ||
3500 | /* The TO encodings used in extended trap mnemonics. */ | |
3501 | #define TOLGT (0x1) | |
3502 | #define TOLLT (0x2) | |
3503 | #define TOEQ (0x4) | |
3504 | #define TOLGE (0x5) | |
3505 | #define TOLNL (0x5) | |
3506 | #define TOLLE (0x6) | |
3507 | #define TOLNG (0x6) | |
3508 | #define TOGT (0x8) | |
3509 | #define TOGE (0xc) | |
3510 | #define TONL (0xc) | |
3511 | #define TOLT (0x10) | |
3512 | #define TOLE (0x14) | |
3513 | #define TONG (0x14) | |
3514 | #define TONE (0x18) | |
3515 | #define TOU (0x1f) | |
3516 | \f | |
3517 | /* Smaller names for the flags so each entry in the opcodes table will | |
3518 | fit on a single line. */ | |
3519 | #undef PPC | |
de866fcc | 3520 | #define PPC PPC_OPCODE_PPC |
661bd698 | 3521 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
661bd698 | 3522 | #define POWER4 PPC_OPCODE_POWER4 |
1ed8e1e4 | 3523 | #define POWER5 PPC_OPCODE_POWER5 |
702f0fb4 | 3524 | #define POWER6 PPC_OPCODE_POWER6 |
066be9f7 | 3525 | #define POWER7 PPC_OPCODE_POWER7 |
5817ffd1 | 3526 | #define POWER8 PPC_OPCODE_POWER8 |
a680de9a | 3527 | #define POWER9 PPC_OPCODE_POWER9 |
ede602d7 | 3528 | #define CELL PPC_OPCODE_CELL |
bdc70b4a | 3529 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE |
6b069ee7 | 3530 | #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ |
bdc70b4a | 3531 | | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
418c1742 | 3532 | #define PPC403 PPC_OPCODE_403 |
081ba1b3 | 3533 | #define PPC405 PPC_OPCODE_405 |
7d5b217e | 3534 | #define PPC440 PPC_OPCODE_440 |
c8187e15 | 3535 | #define PPC464 PPC440 |
9fe54b1c | 3536 | #define PPC476 PPC_OPCODE_476 |
ef5a96d5 | 3537 | #define PPC750 PPC_OPCODE_750 |
fa758a70 AC |
3538 | #define GEKKO PPC_OPCODE_750 |
3539 | #define BROADWAY PPC_OPCODE_750 | |
ef5a96d5 AM |
3540 | #define PPC7450 PPC_OPCODE_7450 |
3541 | #define PPC860 PPC_OPCODE_860 | |
c3d65c1c | 3542 | #define PPCPS PPC_OPCODE_PPCPS |
a404d431 | 3543 | #define PPCVEC PPC_OPCODE_ALTIVEC |
9a85b496 AM |
3544 | #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500) |
3545 | #define PPCVEC3 PPC_OPCODE_POWER9 | |
9b4e5766 | 3546 | #define PPCVSX PPC_OPCODE_VSX |
9570835e AM |
3547 | #define PPCVSX2 PPC_OPCODE_POWER8 |
3548 | #define PPCVSX3 PPC_OPCODE_POWER9 | |
de866fcc AM |
3549 | #define POWER PPC_OPCODE_POWER |
3550 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | |
81a0b7e2 | 3551 | #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON |
b80c7270 AM |
3552 | #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \ |
3553 | | PPC_OPCODE_COMMON) | |
de866fcc | 3554 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
de866fcc | 3555 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 |
661bd698 | 3556 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON |
de866fcc | 3557 | #define MFDEC1 PPC_OPCODE_POWER |
b80c7270 AM |
3558 | #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \ |
3559 | | PPC_OPCODE_TITAN) | |
418c1742 | 3560 | #define BOOKE PPC_OPCODE_BOOKE |
14b57c7c | 3561 | #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS |
36ae0db3 | 3562 | #define PPCE300 PPC_OPCODE_E300 |
14b57c7c | 3563 | #define PPCSPE PPC_OPCODE_SPE |
74081948 | 3564 | #define PPCSPE2 PPC_OPCODE_SPE2 |
14b57c7c AM |
3565 | #define PPCISEL PPC_OPCODE_ISEL |
3566 | #define PPCEFS PPC_OPCODE_EFS | |
74081948 | 3567 | #define PPCEFS2 PPC_OPCODE_EFS2 |
de866fcc | 3568 | #define PPCBRLK PPC_OPCODE_BRLOCK |
23976049 | 3569 | #define PPCPMR PPC_OPCODE_PMR |
aea77599 | 3570 | #define PPCTMR PPC_OPCODE_TMR |
de866fcc | 3571 | #define PPCCHLK PPC_OPCODE_CACHELCK |
fa758a70 | 3572 | #define PPCRFMCI PPC_OPCODE_RFMCI |
19a6653c | 3573 | #define E500MC PPC_OPCODE_E500MC |
634b50f2 | 3574 | #define PPCA2 PPC_OPCODE_A2 |
43e65147 | 3575 | #define TITAN PPC_OPCODE_TITAN |
62adc510 | 3576 | #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN |
e01d869a | 3577 | #define E500 PPC_OPCODE_E500 |
aea77599 | 3578 | #define E6500 PPC_OPCODE_E6500 |
b9c361e0 | 3579 | #define PPCVLE PPC_OPCODE_VLE |
ef85eab0 | 3580 | #define PPCHTM PPC_OPCODE_POWER8 |
dfdaec14 | 3581 | #define E200Z4 PPC_OPCODE_E200Z4 |
e3c2f928 | 3582 | #define PPCLSP PPC_OPCODE_LSP |
4fff86c5 PB |
3583 | /* The list of embedded processors that use the embedded operand ordering |
3584 | for the 3 operand dcbt and dcbtst instructions. */ | |
3585 | #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ | |
14b57c7c | 3586 | | PPC_OPCODE_A2) |
4fff86c5 PB |
3587 | |
3588 | ||
252b5132 RH |
3589 | \f |
3590 | /* The opcode table. | |
3591 | ||
3592 | The format of the opcode table is: | |
3593 | ||
8ebac3aa | 3594 | NAME OPCODE MASK FLAGS ANTI {OPERANDS} |
252b5132 RH |
3595 | |
3596 | NAME is the name of the instruction. | |
3597 | OPCODE is the instruction opcode. | |
3598 | MASK is the opcode mask; this is used to tell the disassembler | |
3599 | which bits in the actual opcode must match OPCODE. | |
8ebac3aa AM |
3600 | FLAGS are flags indicating which processors support the instruction. |
3601 | ANTI indicates which processors don't support the instruction. | |
252b5132 RH |
3602 | OPERANDS is the list of operands. |
3603 | ||
3604 | The disassembler reads the table in order and prints the first | |
3605 | instruction which matches, so this table is sorted to put more | |
de866fcc AM |
3606 | specific instructions before more general instructions. |
3607 | ||
3608 | This table must be sorted by major opcode. Please try to keep it | |
3609 | vaguely sorted within major opcode too, except of course where | |
3610 | constrained otherwise by disassembler operation. */ | |
252b5132 RH |
3611 | |
3612 | const struct powerpc_opcode powerpc_opcodes[] = { | |
14b57c7c AM |
3613 | {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, |
3614 | {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3615 | {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3616 | {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3617 | {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3618 | {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3619 | {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3620 | {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3621 | {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3622 | {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3623 | {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3624 | {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3625 | {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3626 | {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3627 | {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3628 | {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
3629 | {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, | |
3630 | ||
3631 | {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3632 | {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3633 | {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3634 | {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3635 | {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3636 | {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3637 | {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3638 | {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3639 | {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3640 | {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3641 | {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3642 | {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3643 | {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3644 | {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3645 | {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3646 | {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3647 | {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3648 | {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3649 | {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3650 | {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3651 | {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3652 | {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3653 | {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3654 | {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3655 | {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3656 | {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3657 | {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3658 | {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3659 | {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
3660 | {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
3661 | {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, | |
3662 | {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, | |
3663 | ||
3664 | {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
3665 | {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3666 | {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, | |
3667 | {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3668 | {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3669 | {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3670 | {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3671 | {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3672 | {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3673 | {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, | |
3674 | {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3675 | {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, | |
3676 | {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3677 | {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3678 | {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3679 | {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3680 | {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3681 | {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3682 | {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3683 | {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
3684 | {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3685 | {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
3686 | {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3687 | {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
3688 | {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
3689 | {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3690 | {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3691 | {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3692 | {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3693 | {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3694 | {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3695 | {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3696 | {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, | |
3697 | {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
3698 | {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3699 | {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
3700 | {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3701 | {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3702 | {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3703 | {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
3704 | {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3705 | {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
3706 | {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3707 | {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
3708 | {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3709 | {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
3710 | {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
3711 | {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, | |
3712 | {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
3713 | {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3714 | {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, | |
3715 | {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3716 | {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, | |
3717 | {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
3718 | {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
3719 | {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
3720 | {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
3721 | {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
3722 | {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
3723 | {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
3724 | {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
3725 | {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
3726 | {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3727 | {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3728 | {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3729 | {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3730 | {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, | |
3731 | {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3732 | {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
3733 | {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3734 | {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
3735 | {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3736 | {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
3737 | {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
3738 | {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
3739 | {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
3740 | {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3741 | {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3742 | {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3743 | {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3744 | {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3745 | {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3746 | {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3747 | {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3748 | {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, | |
3749 | {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3750 | {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, | |
3751 | {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3752 | {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3753 | {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3754 | {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3755 | {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3756 | {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3757 | {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3758 | {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3759 | {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3760 | {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
3761 | {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3762 | {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3763 | {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3764 | {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3765 | {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3766 | {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3767 | {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3768 | {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3769 | {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3770 | {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3771 | {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3772 | {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3773 | {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3774 | {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3775 | {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
3776 | {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3777 | {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3778 | {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3779 | {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3780 | {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3781 | {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3782 | {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3783 | {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3784 | {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3785 | {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3786 | {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3787 | {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3788 | {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3789 | {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3790 | {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3791 | {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3792 | {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3793 | {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3794 | {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3795 | {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3796 | {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3797 | {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3798 | {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3799 | {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3800 | {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3801 | {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3802 | {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3803 | {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3804 | {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3805 | {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3806 | {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3807 | {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3808 | {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3809 | {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3810 | {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
3811 | {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3812 | {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3813 | {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3814 | {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3815 | {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3816 | {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3817 | {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3818 | {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3819 | {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3820 | {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3821 | {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3822 | {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3823 | {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3824 | {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3825 | {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3826 | {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
3827 | {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3828 | {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3829 | {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3830 | {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3831 | {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3832 | {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3833 | {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3834 | {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3835 | {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
3836 | {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3837 | {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3838 | {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, | |
3839 | {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, | |
3840 | {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3841 | {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3842 | {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, | |
3843 | {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3844 | {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, | |
3845 | {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, | |
3846 | {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3847 | {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3848 | {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3849 | {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3850 | {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3851 | {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3852 | {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3853 | {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3854 | {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, | |
3855 | {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
3856 | {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3857 | {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3858 | {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3859 | {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3860 | {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3861 | {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
3862 | {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3863 | {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3864 | {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
98553ad3 | 3865 | {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RAB}}, |
14b57c7c | 3866 | {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
98553ad3 | 3867 | {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RAB}}, |
14b57c7c | 3868 | {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
3869 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
3870 | {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3871 | {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3872 | {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3873 | {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3874 | {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3875 | {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
3876 | {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
3877 | {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3878 | {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
3879 | {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3880 | {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, | |
3881 | {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
3882 | {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, | |
3883 | {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3884 | {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3885 | {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3886 | {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3887 | {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3888 | {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3889 | {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3890 | {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3891 | {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3892 | {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, | |
3893 | {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3894 | {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
3895 | {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3896 | {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3897 | {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3898 | {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3899 | {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3900 | {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, | |
3901 | {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
3902 | {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3903 | {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, | |
3904 | {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, | |
3905 | {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, | |
3906 | {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3907 | {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3908 | {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 | 3909 | {"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c | 3910 | {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
74081948 | 3911 | {"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
3912 | {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3913 | {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3914 | {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3915 | {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
3916 | {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 3917 | {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, |
14b57c7c AM |
3918 | {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3919 | {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
3920 | {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 | 3921 | {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c | 3922 | {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
74081948 | 3923 | {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
3924 | {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3925 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, | |
3926 | {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
3927 | {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3928 | {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3929 | {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3930 | {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
74081948 | 3931 | {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
3932 | {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3933 | {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
3934 | {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
3935 | {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
74081948 | 3936 | {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
3937 | {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3938 | {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
3939 | {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
3940 | {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
3941 | {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, | |
3942 | {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
3943 | {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3944 | {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
3945 | {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
74081948 AF |
3946 | {"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, |
3947 | {"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3948 | {"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3949 | {"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3950 | {"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3951 | {"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3952 | {"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3953 | {"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3954 | {"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3955 | {"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3956 | {"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3957 | {"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3958 | {"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3959 | {"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3960 | {"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3961 | {"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3962 | {"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
3963 | {"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
14b57c7c | 3964 | {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
74081948 | 3965 | {"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, |
14b57c7c AM |
3966 | {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3967 | {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 | 3968 | {"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c | 3969 | {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 3970 | {"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c AM |
3971 | {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, |
3972 | {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
3973 | {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
3974 | {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
3975 | {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 3976 | {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, |
14b57c7c AM |
3977 | {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3978 | {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
3979 | {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 | 3980 | {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c | 3981 | {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
74081948 | 3982 | {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c AM |
3983 | {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3984 | {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
3985 | {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
3986 | {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
3987 | {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
3988 | {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
3989 | {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 3990 | {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
3991 | {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3992 | {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
3993 | {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
3994 | {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 3995 | {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
3996 | {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3997 | {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
3998 | {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
3999 | {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4000 | {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, | |
4001 | {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4002 | {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4003 | {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4004 | {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4005 | {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
4006 | {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 AF |
4007 | {"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, |
4008 | {"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
4009 | {"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, | |
4010 | {"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
14b57c7c AM |
4011 | {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, |
4012 | {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
4013 | {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
74081948 | 4014 | {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, |
14b57c7c AM |
4015 | {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
4016 | {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 AF |
4017 | {"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, |
4018 | {"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
4019 | {"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, | |
4020 | {"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
14b57c7c AM |
4021 | {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4022 | {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4023 | {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4024 | {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 AF |
4025 | {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4026 | {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
4027 | {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, | |
4028 | {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
4029 | {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, | |
14b57c7c AM |
4030 | {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4031 | {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4032 | {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 4033 | {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4034 | {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4035 | {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4036 | {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 AF |
4037 | {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4038 | {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
14b57c7c | 4039 | {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
74081948 AF |
4040 | {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4041 | {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
14b57c7c AM |
4042 | {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4043 | {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4044 | {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4045 | {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4046 | {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4047 | {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4048 | {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4049 | {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4050 | {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4051 | {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4052 | {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4053 | {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4054 | {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4055 | {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4056 | {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4057 | {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, | |
4058 | {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4059 | {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4060 | {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4061 | {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, | |
4062 | {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4063 | {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, | |
4064 | {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4065 | {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4066 | {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, | |
4067 | {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4068 | {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4069 | {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4070 | {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4071 | {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4072 | {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4073 | {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4074 | {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4075 | {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4076 | {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4077 | {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4078 | {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4079 | {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4080 | {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4081 | {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4082 | {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4083 | {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4084 | {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4085 | {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4086 | {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4087 | {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4088 | {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4089 | {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4090 | {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4091 | {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4092 | {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4093 | {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4094 | {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4095 | {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4096 | {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4097 | {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4098 | {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4099 | {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4100 | {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4101 | {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4102 | {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4103 | {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, | |
4104 | {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4105 | {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
4106 | {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4107 | {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4108 | {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4109 | {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4110 | {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4111 | {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4112 | {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4113 | {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4114 | {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4115 | {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4116 | {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4117 | {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4118 | {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4119 | {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, | |
4120 | {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4121 | {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4122 | {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4123 | {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4124 | {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4125 | {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4126 | {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4127 | {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4128 | {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4129 | {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4130 | {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
4131 | {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4132 | {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4133 | {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4134 | {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4135 | {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4136 | {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, | |
4137 | {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4138 | {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4139 | {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4140 | {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4141 | {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4142 | {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
62adc510 AM |
4143 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4144 | {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4145 | {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4146 | {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4147 | {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4148 | {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4149 | {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4150 | {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4151 | {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4152 | {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4153 | {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4154 | {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4155 | {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4156 | {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4157 | {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4158 | {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4159 | {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4160 | {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4161 | {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4162 | {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4163 | {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4164 | {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4165 | {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4166 | {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4167 | {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4168 | {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, | |
4169 | {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4170 | {"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4171 | {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4172 | {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4173 | {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4174 | {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4175 | {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4176 | {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4177 | {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4178 | {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4179 | {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4180 | {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4181 | {"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4182 | {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4183 | {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4184 | {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4185 | {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4186 | {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4187 | {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4188 | {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4189 | {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4190 | {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4191 | {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4192 | {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4193 | {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4194 | {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4195 | {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4196 | {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
74081948 | 4197 | {"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4198 | {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4199 | {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 | 4200 | {"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4201 | {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4202 | {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4203 | {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4204 | {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4205 | {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4206 | {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4207 | {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4208 | {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4209 | {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4210 | {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4211 | {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
98553ad3 | 4212 | {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VAB}}, |
14b57c7c AM |
4213 | {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4214 | {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4215 | {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4216 | {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4217 | {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4218 | {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4219 | {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4220 | {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4221 | {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4222 | {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4223 | {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4224 | {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4225 | {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4226 | {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4227 | {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4228 | {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4229 | {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4230 | {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4231 | {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4232 | {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 4233 | {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 4234 | {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 4235 | {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
14b57c7c AM |
4236 | {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4237 | {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4238 | {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4239 | {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4240 | {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4241 | {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4242 | {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4243 | {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4244 | {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4245 | {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4246 | {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4247 | {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4248 | {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4249 | {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4250 | {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4251 | {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4252 | {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4253 | {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4254 | {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4255 | {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
98553ad3 | 4256 | {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VAB}}, |
14b57c7c AM |
4257 | {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4258 | {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
62adc510 AM |
4259 | {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4260 | {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4261 | {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4262 | {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4263 | {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4264 | {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4265 | {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4266 | {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4267 | {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4268 | {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4269 | {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4270 | {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4271 | {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4272 | {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4273 | {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4274 | {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4275 | {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4276 | {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4277 | {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4278 | {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4279 | {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4280 | {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4281 | {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4282 | {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4283 | {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4284 | {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 AF |
4285 | {"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4286 | {"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4287 | {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4288 | {"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
62adc510 AM |
4289 | {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4290 | {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c | 4291 | {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
74081948 | 4292 | {"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4293 | {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4294 | {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4295 | {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4296 | {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4297 | {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4298 | {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4299 | {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4300 | {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 4301 | {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4302 | {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4303 | {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4304 | {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4305 | {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4306 | {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4307 | {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4308 | {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4309 | {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4310 | {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
74081948 AF |
4311 | {"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4312 | {"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4313 | {"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4314 | {"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c AM |
4315 | {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4316 | {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4317 | {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4318 | {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4319 | {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4320 | {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4321 | {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4322 | {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4323 | {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4324 | {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4325 | {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4326 | {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4327 | {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4328 | {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4329 | {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
62adc510 AM |
4330 | {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4331 | {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4332 | {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4333 | {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4334 | {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4335 | {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4336 | {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4337 | {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4338 | {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4339 | {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4340 | {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4341 | {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4342 | {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4343 | {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4344 | {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4345 | {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4346 | {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4347 | {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4348 | {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4349 | {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4350 | {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4351 | {"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4352 | {"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4353 | {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4354 | {"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 4355 | {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
62adc510 AM |
4356 | {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4357 | {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
74081948 | 4358 | {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4359 | {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, |
4360 | {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4361 | {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4362 | {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4363 | {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4364 | {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
74081948 | 4365 | {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 4366 | {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4367 | {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4368 | {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4369 | {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4370 | {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4371 | {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4372 | {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4373 | {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4374 | {"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4375 | {"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4376 | {"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4377 | {"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c AM |
4378 | {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4379 | {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4380 | {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4381 | {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, | |
4382 | {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, | |
4383 | {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4384 | {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4385 | {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4386 | {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4387 | {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4388 | {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4389 | {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4390 | {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4391 | {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4392 | {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4393 | {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4394 | {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4395 | {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4396 | {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4397 | {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, | |
4398 | {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4399 | {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4400 | {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4401 | {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4402 | {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
4403 | {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4404 | {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, | |
4405 | {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4406 | {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4407 | {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4408 | {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4409 | {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
4410 | {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4411 | {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4412 | {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, | |
4413 | {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4414 | {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4415 | {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4416 | {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4417 | {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4418 | {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4419 | {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
4420 | {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, | |
4421 | {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4422 | {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 4423 | {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 4424 | {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 4425 | {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c AM |
4426 | {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
4427 | {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4428 | {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4429 | {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4430 | {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4431 | {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4432 | {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4433 | {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4434 | {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4435 | {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
4436 | {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4437 | {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4438 | {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4439 | {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4440 | {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4441 | {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4442 | {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4443 | {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
62adc510 AM |
4444 | {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4445 | {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4446 | {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4447 | {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4448 | {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4449 | {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4450 | {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4451 | {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4452 | {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4453 | {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4454 | {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4455 | {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4456 | {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4457 | {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4458 | {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
4459 | {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4460 | {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4461 | {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4462 | {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4463 | {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 4464 | {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 4465 | {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 4466 | {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c AM |
4467 | {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4468 | {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4469 | {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4470 | {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4471 | {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, | |
4472 | ||
4473 | {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
4474 | {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
4475 | ||
4476 | {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
4477 | {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
4478 | ||
4479 | {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, | |
4480 | ||
4481 | {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, | |
4482 | {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, | |
a5721ba2 | 4483 | {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, |
14b57c7c AM |
4484 | {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, |
4485 | ||
4486 | {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, | |
4487 | {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, | |
a5721ba2 | 4488 | {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, |
14b57c7c AM |
4489 | {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, |
4490 | ||
4491 | {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
4492 | {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
4493 | {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, | |
4494 | ||
4495 | {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
4496 | {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
4497 | {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, | |
4498 | ||
4499 | {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, | |
4500 | {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, | |
4501 | {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, | |
4502 | {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
4503 | {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, | |
4504 | {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, | |
4505 | ||
4506 | {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, | |
4507 | {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, | |
4508 | {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, | |
4509 | {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, | |
4510 | {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, | |
4511 | ||
4512 | {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
4513 | {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
4514 | {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, | |
4515 | {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, | |
4516 | {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
4517 | {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
4518 | {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, | |
4519 | {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, | |
4520 | {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
4521 | {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
4522 | {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, | |
4523 | {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, | |
4524 | {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
4525 | {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
4526 | {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, | |
4527 | {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, | |
4528 | {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
4529 | {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
4530 | {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}}, | |
4531 | {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
4532 | {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
4533 | {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}}, | |
4534 | {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
4535 | {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
4536 | {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}}, | |
4537 | {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
4538 | {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
4539 | {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}}, | |
4540 | ||
4541 | {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4542 | {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4543 | {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4544 | {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4545 | {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4546 | {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4547 | {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4548 | {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4549 | {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4550 | {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4551 | {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4552 | {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4553 | {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4554 | {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4555 | {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4556 | {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4557 | {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4558 | {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4559 | {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4560 | {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4561 | {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4562 | {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4563 | {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4564 | {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4565 | {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4566 | {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4567 | {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4568 | {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4569 | {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4570 | {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4571 | {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4572 | {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4573 | {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4574 | {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4575 | {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4576 | {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4577 | {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4578 | {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4579 | {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4580 | {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4581 | {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4582 | {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4583 | {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4584 | {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4585 | {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4586 | {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4587 | {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4588 | {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4589 | {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4590 | {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4591 | {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4592 | {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4593 | {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4594 | {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4595 | {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4596 | {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4597 | {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4598 | {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4599 | {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4600 | {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4601 | {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4602 | {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4603 | {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4604 | {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4605 | {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4606 | {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
4607 | {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4608 | {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4609 | {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4610 | {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4611 | {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4612 | {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
4613 | {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4614 | {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4615 | {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4616 | {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4617 | {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4618 | {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
4619 | {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4620 | {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4621 | {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4622 | {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4623 | {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4624 | {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
4625 | ||
4626 | {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4627 | {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4628 | {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4629 | {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4630 | {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4631 | {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4632 | {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4633 | {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4634 | {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4635 | {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4636 | {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4637 | {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4638 | {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4639 | {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4640 | {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4641 | {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4642 | {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4643 | {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4644 | {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4645 | {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4646 | {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4647 | {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4648 | {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4649 | {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4650 | {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4651 | {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4652 | {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4653 | {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4654 | {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4655 | {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4656 | {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4657 | {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4658 | {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4659 | {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4660 | {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4661 | {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4662 | {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4663 | {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4664 | {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4665 | {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4666 | {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4667 | {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
4668 | {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4669 | {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4670 | {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
4671 | {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
4672 | {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
4673 | {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
4674 | {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4675 | {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4676 | {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4677 | {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4678 | {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4679 | {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
4680 | {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4681 | {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4682 | {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
4683 | {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
4684 | {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
4685 | {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
4686 | ||
4687 | {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4688 | {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4689 | {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4690 | {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4691 | {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4692 | {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4693 | {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4694 | {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4695 | {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4696 | {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4697 | {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4698 | {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4699 | {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4700 | {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4701 | {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4702 | {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4703 | {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4704 | {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4705 | {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4706 | {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4707 | {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4708 | {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4709 | {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4710 | {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4711 | ||
4712 | {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
4713 | {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
4714 | {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4715 | {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
4716 | {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
4717 | {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
4718 | {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4719 | {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
4720 | {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
4721 | {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
4722 | {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4723 | {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
4724 | {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
4725 | {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
4726 | {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4727 | {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
4728 | ||
4729 | {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4730 | {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4731 | {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4732 | {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4733 | {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4734 | {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4735 | {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4736 | {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4737 | {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4738 | {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4739 | {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4740 | {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4741 | {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4742 | {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4743 | {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4744 | {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
4745 | {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
4746 | {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4747 | {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4748 | {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4749 | {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4750 | {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
4751 | {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
4752 | {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4753 | ||
4754 | {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
4755 | {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
4756 | {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4757 | {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
4758 | {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
4759 | {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
4760 | {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
4761 | {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
4762 | {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
4763 | {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
4764 | {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4765 | {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
4766 | {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
4767 | {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
4768 | {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
4769 | {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
4770 | ||
4771 | {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, | |
4772 | {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, | |
4773 | {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, | |
4774 | {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, | |
4775 | {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, | |
4776 | {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, | |
4777 | {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, | |
4778 | {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, | |
4779 | {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, | |
4780 | {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, | |
4781 | {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, | |
4782 | {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, | |
4783 | ||
4784 | {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, | |
dce75bf9 | 4785 | {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, |
14b57c7c AM |
4786 | {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, |
4787 | {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, | |
4788 | {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, | |
4789 | {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, | |
4790 | ||
4791 | {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, | |
4792 | {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, | |
4793 | {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, | |
4794 | {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, | |
4795 | ||
4796 | {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, | |
4797 | ||
1437d063 | 4798 | {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, |
14b57c7c AM |
4799 | {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, |
4800 | {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, | |
4801 | ||
4802 | {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
4803 | {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4804 | {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
4805 | {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4806 | {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4807 | {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4808 | {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
4809 | {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4810 | {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
4811 | {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4812 | {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4813 | {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
4814 | {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
4815 | {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, | |
4816 | {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
4817 | {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, | |
4818 | {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4819 | {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4820 | {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4821 | {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4822 | {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4823 | {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4824 | {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4825 | {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
4826 | ||
4827 | {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4828 | {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4829 | {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4830 | {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4831 | {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4832 | {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4833 | {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4834 | {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4835 | {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4836 | {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4837 | {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4838 | {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4839 | {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4840 | {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4841 | {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4842 | {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4843 | {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4844 | {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4845 | {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4846 | {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4847 | {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4848 | {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4849 | {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4850 | {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4851 | {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4852 | {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4853 | {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4854 | {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4855 | {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4856 | {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4857 | {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4858 | {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4859 | {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4860 | {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4861 | {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4862 | {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4863 | {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4864 | {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4865 | {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4866 | {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4867 | {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4868 | {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4869 | {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4870 | {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4871 | {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4872 | {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4873 | {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4874 | {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4875 | {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4876 | {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4877 | {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4878 | {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4879 | {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4880 | {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4881 | {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4882 | {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4883 | {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4884 | {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4885 | {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4886 | {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4887 | {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4888 | {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4889 | {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4890 | {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4891 | {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4892 | {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4893 | {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4894 | {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4895 | {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4896 | {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4897 | {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4898 | {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4899 | {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4900 | {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4901 | {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4902 | {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4903 | {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4904 | {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4905 | {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4906 | {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4907 | {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4908 | {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4909 | {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4910 | {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4911 | {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4912 | {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4913 | {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4914 | {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4915 | {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4916 | {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4917 | {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4918 | {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4919 | {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4920 | {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4921 | {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4922 | {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4923 | {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4924 | {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4925 | {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4926 | {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4927 | {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4928 | {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4929 | {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4930 | {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4931 | {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4932 | {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4933 | {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4934 | {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, | |
4935 | {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
4936 | {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4937 | {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4938 | {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4939 | {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4940 | {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4941 | {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4942 | {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4943 | {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4944 | {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4945 | {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4946 | {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
4947 | {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4948 | {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4949 | {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4950 | {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4951 | {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4952 | {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4953 | {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4954 | {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4955 | {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4956 | {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4957 | {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4958 | {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4959 | {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4960 | {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4961 | {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4962 | {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4963 | {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4964 | {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4965 | {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4966 | {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
4967 | ||
4968 | {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4969 | {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4970 | {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4971 | {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4972 | {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4973 | {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4974 | {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4975 | {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4976 | {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4977 | {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4978 | {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4979 | {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4980 | {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4981 | {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4982 | {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
4983 | {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4984 | {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4985 | {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
4986 | {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4987 | {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4988 | {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
4989 | {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
4990 | {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
4991 | {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
4992 | {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4993 | {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4994 | {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4995 | {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4996 | {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4997 | {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
4998 | {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
4999 | {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5000 | {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
5001 | {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5002 | {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5003 | {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5004 | {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
5005 | {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5006 | {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
5007 | {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
5008 | {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5009 | {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
5010 | {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5011 | {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5012 | {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5013 | {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5014 | {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5015 | {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5016 | ||
5017 | {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5018 | {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5019 | {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5020 | {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5021 | {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, | |
5022 | {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, | |
5023 | {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, | |
5024 | {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, | |
5025 | ||
5026 | {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, | |
5027 | ||
98553ad3 | 5028 | {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, |
14b57c7c AM |
5029 | {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5030 | {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, | |
5031 | ||
5032 | {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, | |
5033 | {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, | |
5034 | {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, | |
5035 | ||
dce75bf9 | 5036 | {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, |
14b57c7c AM |
5037 | {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, |
5038 | ||
5039 | {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, | |
5040 | ||
5041 | {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5042 | ||
5043 | {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, | |
5044 | ||
5045 | {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
5046 | {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, | |
5047 | ||
98553ad3 | 5048 | {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, |
14b57c7c AM |
5049 | {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5050 | ||
5051 | {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, | |
5052 | ||
5053 | {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5054 | ||
5055 | {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5056 | ||
5057 | {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, | |
5058 | ||
98553ad3 | 5059 | {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, |
14b57c7c AM |
5060 | {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5061 | ||
5062 | {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, | |
5063 | {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, | |
5064 | ||
5065 | {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5066 | ||
5067 | {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5068 | ||
5069 | {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5070 | ||
98553ad3 | 5071 | {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, |
14b57c7c AM |
5072 | {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5073 | ||
5074 | {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5075 | {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5076 | ||
5077 | {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}}, | |
5078 | {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}}, | |
5079 | ||
5080 | {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5081 | {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5082 | {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5083 | {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5084 | {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5085 | {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5086 | {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5087 | {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5088 | {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5089 | {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5090 | {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5091 | {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5092 | {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5093 | {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5094 | {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5095 | {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5096 | {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5097 | {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5098 | {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5099 | {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5100 | {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5101 | {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5102 | {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5103 | {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5104 | {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5105 | {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5106 | {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5107 | {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5108 | {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5109 | {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5110 | {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5111 | {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5112 | {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5113 | {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5114 | {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5115 | {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5116 | {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5117 | {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5118 | {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5119 | {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5120 | {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5121 | {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5122 | {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5123 | {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5124 | {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5125 | {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5126 | {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5127 | {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5128 | {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5129 | {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5130 | {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5131 | {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5132 | {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5133 | {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5134 | {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5135 | {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5136 | {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5137 | {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5138 | {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5139 | {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5140 | {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5141 | {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5142 | {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5143 | {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5144 | {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5145 | {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5146 | {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5147 | {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5148 | {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5149 | {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5150 | {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5151 | {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5152 | {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5153 | {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5154 | {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5155 | {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5156 | {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5157 | {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5158 | {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5159 | {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5160 | {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5161 | {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5162 | {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5163 | {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5164 | {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5165 | {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5166 | {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5167 | {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5168 | {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
5169 | {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5170 | {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5171 | {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5172 | {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5173 | {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5174 | {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5175 | {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5176 | {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5177 | {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5178 | {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5179 | {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
5180 | {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5181 | {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5182 | {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5183 | {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5184 | {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5185 | {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5186 | {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5187 | {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5188 | {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5189 | {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5190 | {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5191 | {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5192 | {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5193 | {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5194 | {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5195 | {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5196 | {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5197 | {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5198 | {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5199 | {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5200 | ||
5201 | {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
5202 | {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5203 | {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
5204 | {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5205 | {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5206 | {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5207 | {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5208 | {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5209 | {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5210 | {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5211 | {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
5212 | {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5213 | {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
5214 | {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5215 | {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5216 | {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
5217 | {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5218 | {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5219 | {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5220 | {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5221 | ||
5222 | {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5223 | {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5224 | {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5225 | {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, | |
5226 | {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, | |
5227 | {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, | |
5228 | {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, | |
5229 | {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, | |
5230 | ||
5231 | {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, | |
5232 | {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, | |
5233 | {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, | |
5234 | {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, | |
5235 | {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, | |
5236 | {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, | |
5237 | ||
5238 | {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5239 | {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5240 | ||
5241 | {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5242 | {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5243 | ||
5244 | {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, | |
5245 | {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, | |
5246 | {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5247 | {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5248 | {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, | |
5249 | {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, | |
5250 | {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5251 | {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5252 | ||
5253 | {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5254 | {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5255 | ||
5256 | {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, | |
5257 | {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5258 | {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5259 | {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, | |
5260 | {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5261 | {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5262 | ||
5263 | {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
5264 | {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5265 | {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5266 | ||
5267 | {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5268 | {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5269 | ||
5270 | {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
5271 | {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5272 | {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5273 | ||
5274 | {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5275 | {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5276 | ||
5277 | {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5278 | {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5279 | ||
5280 | {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5281 | {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5282 | ||
5283 | {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, | |
5284 | {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, | |
5285 | {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5286 | {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, | |
5287 | {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, | |
5288 | {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5289 | ||
5290 | {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, | |
5291 | {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, | |
5292 | ||
5293 | {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5294 | {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5295 | ||
5296 | {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5297 | {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5298 | ||
5299 | {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, | |
5300 | {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, | |
5301 | {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, | |
5302 | {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, | |
5303 | ||
5304 | {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, | |
5305 | {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, | |
5306 | ||
5307 | {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, | |
5308 | {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, | |
a5721ba2 | 5309 | {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
bdc70b4a | 5310 | {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
1cb0a767 | 5311 | |
14b57c7c AM |
5312 | {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
5313 | {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5314 | {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5315 | {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5316 | {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5317 | {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5318 | {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5319 | {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5320 | {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5321 | {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5322 | {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5323 | {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5324 | {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5325 | {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5326 | {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5327 | {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5328 | {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5329 | {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5330 | {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5331 | {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5332 | {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5333 | {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5334 | {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5335 | {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5336 | {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5337 | {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5338 | {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5339 | {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5340 | {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, | |
5341 | {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5342 | {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5343 | {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, | |
5344 | {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, | |
5345 | ||
5346 | {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
5347 | {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
5348 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
5349 | ||
5350 | {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5351 | {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5352 | {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
5353 | {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5354 | {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5355 | {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
5356 | ||
5357 | {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
5358 | {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
5359 | ||
5360 | {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5361 | {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5362 | {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5363 | {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5364 | ||
5365 | {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
5366 | {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
5367 | ||
5368 | {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, | |
5369 | ||
5370 | {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, | |
5371 | ||
5372 | {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, | |
5373 | {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, | |
5374 | {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, | |
5375 | {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, | |
5376 | ||
5377 | {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, | |
5378 | {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, | |
5379 | ||
5380 | {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, | |
5381 | ||
5382 | {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, | |
5383 | ||
5384 | {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, | |
5385 | ||
5386 | {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, | |
5387 | {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5388 | ||
5389 | {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
5390 | {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
5391 | {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
5392 | {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
5393 | ||
5394 | {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
5395 | {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
5396 | {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
5397 | {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
5398 | ||
5399 | {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
5400 | {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
5401 | ||
5402 | {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, | |
5403 | {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
5404 | ||
5405 | {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, | |
5406 | {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, | |
5407 | ||
5408 | {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | |
5409 | ||
5410 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, | |
5411 | {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}}, | |
5412 | ||
5413 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | |
5414 | ||
5415 | {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, | |
5416 | {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, | |
a5721ba2 | 5417 | {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
bdc70b4a | 5418 | {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
de866fcc | 5419 | |
14b57c7c AM |
5420 | {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
5421 | {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
5422 | {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 5423 | |
ac8f0f72 | 5424 | {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, |
e67ed0e8 | 5425 | |
14b57c7c | 5426 | {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
de866fcc | 5427 | |
14b57c7c | 5428 | {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
de866fcc | 5429 | |
14b57c7c | 5430 | {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, |
066be9f7 | 5431 | |
14b57c7c | 5432 | {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
c0637f3a | 5433 | |
14b57c7c | 5434 | {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
de866fcc | 5435 | |
14b57c7c | 5436 | {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, |
de866fcc | 5437 | |
14b57c7c AM |
5438 | {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5439 | {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
5440 | {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
5441 | {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
de866fcc | 5442 | |
14b57c7c AM |
5443 | {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, |
5444 | {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, | |
5445 | {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, | |
5446 | {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, | |
e0d602ec | 5447 | |
14b57c7c | 5448 | {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
066be9f7 | 5449 | |
14b57c7c | 5450 | {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
43e65147 | 5451 | |
14b57c7c | 5452 | {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, |
43e65147 | 5453 | |
14b57c7c AM |
5454 | {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, |
5455 | {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 5456 | |
14b57c7c AM |
5457 | {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
5458 | {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, | |
de866fcc | 5459 | |
14b57c7c AM |
5460 | {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5461 | {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
de866fcc | 5462 | |
14b57c7c AM |
5463 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
5464 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, | |
5465 | {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, | |
43e65147 | 5466 | |
14b57c7c | 5467 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
19a6653c | 5468 | |
14b57c7c AM |
5469 | {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, |
5470 | {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5471 | {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5472 | {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5473 | {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5474 | {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5475 | {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5476 | {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5477 | {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5478 | {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5479 | {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5480 | {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5481 | {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5482 | {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5483 | {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, | |
5484 | {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, | |
de866fcc | 5485 | |
14b57c7c AM |
5486 | {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5487 | {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
5488 | {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 5489 | |
14b57c7c AM |
5490 | {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5491 | {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
de866fcc | 5492 | |
62adc510 AM |
5493 | {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, |
5494 | {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, | |
de866fcc | 5495 | |
14b57c7c | 5496 | {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, |
de866fcc | 5497 | |
14b57c7c | 5498 | {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, |
43e65147 | 5499 | |
14b57c7c | 5500 | {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, |
de866fcc | 5501 | |
c7a8dbf9 | 5502 | {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, |
a5721ba2 | 5503 | {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}}, |
de866fcc | 5504 | |
14b57c7c | 5505 | {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, |
43e65147 | 5506 | |
14b57c7c | 5507 | {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
de866fcc | 5508 | |
14b57c7c | 5509 | {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, |
aea77599 | 5510 | |
14b57c7c AM |
5511 | {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
5512 | {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 5513 | |
14b57c7c AM |
5514 | {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, |
5515 | {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, | |
de866fcc | 5516 | |
14b57c7c AM |
5517 | {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
5518 | {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
de866fcc | 5519 | |
ac8f0f72 | 5520 | {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}}, |
aea77599 | 5521 | |
14b57c7c | 5522 | {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, |
de866fcc | 5523 | |
14b57c7c AM |
5524 | {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, |
5525 | {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, | |
5526 | {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, | |
c0637f3a | 5527 | |
14b57c7c | 5528 | {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
066be9f7 | 5529 | |
14b57c7c | 5530 | {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, |
de866fcc | 5531 | |
14b57c7c | 5532 | {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, |
43e65147 | 5533 | |
14b57c7c | 5534 | {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, |
de866fcc | 5535 | |
98553ad3 | 5536 | {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 5537 | {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, |
98553ad3 | 5538 | {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 5539 | {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, |
19a6653c | 5540 | |
14b57c7c | 5541 | {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
43e65147 | 5542 | |
fd486b63 | 5543 | {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
a680de9a | 5544 | |
14b57c7c | 5545 | {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, |
43e65147 | 5546 | |
14b57c7c | 5547 | {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
de866fcc | 5548 | |
14b57c7c AM |
5549 | {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
5550 | {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 5551 | |
14b57c7c AM |
5552 | {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5553 | {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5554 | {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5555 | {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 5556 | |
14b57c7c AM |
5557 | {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5558 | {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5559 | {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5560 | {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 5561 | |
14b57c7c | 5562 | {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
c0637f3a | 5563 | |
14b57c7c AM |
5564 | {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
5565 | {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, | |
de866fcc | 5566 | |
14b57c7c AM |
5567 | {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, |
5568 | {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, | |
5569 | {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, | |
de866fcc | 5570 | |
14b57c7c | 5571 | {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, |
de866fcc | 5572 | |
14b57c7c | 5573 | {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, |
c0637f3a | 5574 | |
14b57c7c AM |
5575 | {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
5576 | {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, | |
e0d602ec | 5577 | |
14b57c7c | 5578 | {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
43e65147 | 5579 | |
14b57c7c | 5580 | {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, |
43e65147 | 5581 | |
14b57c7c AM |
5582 | {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
5583 | {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, | |
de866fcc | 5584 | |
14b57c7c AM |
5585 | {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5586 | {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
de866fcc | 5587 | |
14b57c7c AM |
5588 | {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5589 | {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
de866fcc | 5590 | |
14b57c7c | 5591 | {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, |
de866fcc | 5592 | |
14b57c7c | 5593 | {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 5594 | |
14b57c7c | 5595 | {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 5596 | |
14b57c7c | 5597 | {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, |
43e65147 | 5598 | |
14b57c7c | 5599 | {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
de866fcc | 5600 | |
14b57c7c AM |
5601 | {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
5602 | {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 5603 | |
14b57c7c | 5604 | {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, |
19dfcc89 | 5605 | |
14b57c7c AM |
5606 | {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
5607 | {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, | |
de866fcc | 5608 | |
14b57c7c | 5609 | {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, |
de866fcc | 5610 | |
14b57c7c AM |
5611 | {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, |
5612 | {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, | |
5613 | {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
5614 | {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, | |
e0d602ec | 5615 | |
14b57c7c | 5616 | {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, |
de866fcc | 5617 | |
73f07bff | 5618 | {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, |
14b57c7c | 5619 | {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, |
e0d602ec | 5620 | |
14b57c7c AM |
5621 | {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, |
5622 | {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
de866fcc | 5623 | |
14b57c7c AM |
5624 | {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, |
5625 | {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
de866fcc | 5626 | |
14b57c7c | 5627 | {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, |
252b5132 | 5628 | |
14b57c7c | 5629 | {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, |
a680de9a | 5630 | |
14b57c7c | 5631 | {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
aea77599 | 5632 | |
14b57c7c AM |
5633 | {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
5634 | {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 5635 | |
14b57c7c AM |
5636 | {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5637 | {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
5638 | {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
5639 | {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 5640 | |
14b57c7c AM |
5641 | {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5642 | {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
5643 | {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
5644 | {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 5645 | |
14b57c7c | 5646 | {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, |
19a6653c | 5647 | |
14b57c7c | 5648 | {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, |
418c1742 | 5649 | |
14b57c7c AM |
5650 | {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
5651 | {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
5652 | {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, | |
5653 | {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, | |
e0d602ec | 5654 | |
14b57c7c | 5655 | {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
e0d602ec | 5656 | |
14b57c7c | 5657 | {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
43e65147 | 5658 | |
14b57c7c | 5659 | {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, |
252b5132 | 5660 | |
14b57c7c AM |
5661 | {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5662 | {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 5663 | |
14b57c7c AM |
5664 | {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5665 | {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 5666 | |
14b57c7c | 5667 | {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 5668 | |
14b57c7c | 5669 | {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, |
a680de9a | 5670 | |
14b57c7c | 5671 | {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
7d5b217e | 5672 | |
14b57c7c AM |
5673 | {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
5674 | {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
f509565f | 5675 | |
14b57c7c AM |
5676 | {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5677 | {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
5678 | {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
5679 | {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 5680 | |
14b57c7c AM |
5681 | {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5682 | {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 5683 | |
14b57c7c AM |
5684 | {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5685 | {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
5686 | {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
5687 | {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 5688 | |
14b57c7c AM |
5689 | {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5690 | {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5691 | {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5692 | {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 5693 | |
14b57c7c AM |
5694 | {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, |
5695 | {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, | |
5696 | {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, | |
bdc70b4a | 5697 | {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, |
418c1742 | 5698 | |
14b57c7c AM |
5699 | {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
5700 | {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
5701 | {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, | |
c0637f3a | 5702 | |
14b57c7c AM |
5703 | {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
5704 | {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, | |
5705 | {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, | |
5706 | {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, | |
4fff86c5 | 5707 | |
14b57c7c | 5708 | {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, |
252b5132 | 5709 | |
14b57c7c AM |
5710 | {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, |
5711 | {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 5712 | |
14b57c7c | 5713 | {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, |
066be9f7 | 5714 | |
14b57c7c | 5715 | {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
19a6653c | 5716 | |
14b57c7c AM |
5717 | {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, |
5718 | {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, | |
252b5132 | 5719 | |
ac8f0f72 | 5720 | {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 5721 | |
14b57c7c | 5722 | {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, |
1ed8e1e4 | 5723 | |
ac8f0f72 | 5724 | {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 5725 | |
14b57c7c AM |
5726 | {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5727 | {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, | |
5728 | {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 5729 | |
14b57c7c | 5730 | {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, |
a680de9a | 5731 | |
14b57c7c AM |
5732 | {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5733 | {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
5734 | {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
5735 | {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
418c1742 | 5736 | |
14b57c7c | 5737 | {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, |
a680de9a | 5738 | |
14b57c7c AM |
5739 | {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, |
5740 | {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
a680de9a | 5741 | |
14b57c7c | 5742 | {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
19a6653c | 5743 | |
62adc510 | 5744 | {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}}, |
a5721ba2 | 5745 | {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, |
418c1742 | 5746 | |
14b57c7c | 5747 | {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, |
1cb0a767 | 5748 | |
73f07bff | 5749 | {"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, |
c0637f3a | 5750 | |
14b57c7c AM |
5751 | {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, |
5752 | {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, | |
1cb0a767 | 5753 | |
14b57c7c AM |
5754 | {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
5755 | {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, | |
5756 | {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, | |
5757 | {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, | |
4fff86c5 | 5758 | |
14b57c7c | 5759 | {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, |
1cb0a767 | 5760 | |
14b57c7c | 5761 | {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, |
066be9f7 | 5762 | |
14b57c7c AM |
5763 | {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5764 | {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 5765 | |
14b57c7c | 5766 | {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
1cb0a767 | 5767 | |
62adc510 | 5768 | {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}}, |
1cb0a767 | 5769 | |
ac8f0f72 AM |
5770 | {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}}, |
5771 | {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}}, | |
aea77599 | 5772 | |
14b57c7c | 5773 | {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 5774 | |
14b57c7c | 5775 | {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, |
c0637f3a | 5776 | |
14b57c7c AM |
5777 | {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, |
5778 | {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, | |
a5721ba2 | 5779 | {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, |
14b57c7c | 5780 | {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, |
1cb0a767 | 5781 | |
14b57c7c | 5782 | {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, |
a680de9a | 5783 | |
14b57c7c | 5784 | {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, |
a680de9a | 5785 | |
14b57c7c | 5786 | {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
1cb0a767 | 5787 | |
14b57c7c | 5788 | {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, |
1cb0a767 | 5789 | |
14b57c7c | 5790 | {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, |
066be9f7 | 5791 | |
14b57c7c AM |
5792 | {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5793 | {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 5794 | |
14b57c7c | 5795 | {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
1cb0a767 | 5796 | |
14b57c7c AM |
5797 | {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, |
5798 | {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, | |
5799 | {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, | |
5800 | {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, | |
5801 | {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, | |
5802 | {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, | |
5803 | {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, | |
5804 | {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, | |
5805 | {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, | |
5806 | {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, | |
5807 | {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, | |
5808 | {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, | |
5809 | {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, | |
5810 | {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, | |
5811 | {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, | |
5812 | {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, | |
5813 | {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, | |
5814 | {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, | |
5815 | {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, | |
5816 | {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, | |
5817 | {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, | |
5818 | {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, | |
5819 | {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, | |
5820 | {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, | |
5821 | {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, | |
5822 | {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, | |
5823 | {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, | |
5824 | {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, | |
5825 | {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, | |
5826 | {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, | |
5827 | {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, | |
5828 | {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, | |
5829 | {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, | |
5830 | {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, | |
5831 | {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, | |
5832 | {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, | |
1cb0a767 | 5833 | |
ac8f0f72 | 5834 | {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 5835 | |
14b57c7c | 5836 | {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, |
9fe54b1c | 5837 | |
14b57c7c AM |
5838 | {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
5839 | {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
1cb0a767 | 5840 | |
14b57c7c | 5841 | {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
066be9f7 | 5842 | |
14b57c7c | 5843 | {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, |
c03dc33b | 5844 | {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}}, |
1cb0a767 | 5845 | |
14b57c7c AM |
5846 | {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}}, |
5847 | ||
5848 | {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, | |
5849 | {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, | |
5850 | {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, | |
5851 | {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, | |
5852 | {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, | |
5853 | {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, | |
5854 | {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, | |
5855 | {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, | |
5856 | {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, | |
5857 | {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, | |
5858 | {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, | |
bdc70b4a | 5859 | {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, |
14b57c7c AM |
5860 | {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, |
5861 | {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, | |
5862 | {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, | |
5863 | {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, | |
5864 | {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, | |
5865 | {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, | |
5866 | {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, | |
5867 | {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, | |
5868 | {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, | |
5869 | {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, | |
5870 | {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, | |
5871 | {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, | |
5872 | {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, | |
5873 | {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, | |
5874 | {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, | |
5875 | {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, | |
5876 | {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, | |
5877 | {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, | |
5878 | {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, | |
5879 | {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, | |
5880 | {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, | |
5881 | {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, | |
5882 | {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, | |
5883 | {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, | |
5884 | {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, | |
5885 | {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, | |
5886 | {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, | |
5887 | {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, | |
5888 | {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, | |
5889 | {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, | |
5890 | {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, | |
5891 | {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
5892 | {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
5893 | {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
5894 | {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
5895 | {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, | |
5896 | {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, | |
5897 | {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, | |
5898 | {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, | |
5899 | {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, | |
5900 | {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, | |
5901 | {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, | |
5902 | {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, | |
5903 | {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, | |
5904 | {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, | |
5905 | {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, | |
5906 | {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, | |
5907 | {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, | |
5908 | {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, | |
5909 | {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, | |
5910 | {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, | |
5911 | {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, | |
5912 | {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, | |
5913 | {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, | |
5914 | {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, | |
5915 | {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, | |
5916 | {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, | |
5917 | {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, | |
5918 | {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, | |
5919 | {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, | |
5920 | {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, | |
5921 | {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, | |
5922 | {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, | |
5923 | {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, | |
5924 | {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, | |
5925 | {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, | |
5926 | {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, | |
5927 | {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, | |
5928 | {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, | |
5929 | {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, | |
5930 | {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, | |
5931 | {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, | |
5932 | {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, | |
5933 | {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, | |
5934 | {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, | |
5935 | {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, | |
5936 | {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, | |
5937 | {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, | |
5938 | {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, | |
4b94dd2d AM |
5939 | {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, |
5940 | {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, | |
14b57c7c AM |
5941 | {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, |
5942 | {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, | |
4b94dd2d AM |
5943 | {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
5944 | {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, | |
14b57c7c AM |
5945 | {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
5946 | {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, | |
5947 | {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, | |
5948 | {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, | |
5949 | {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, | |
5950 | {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, | |
5951 | {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, | |
5952 | {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, | |
5953 | {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
5954 | {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
5955 | {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
5956 | {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, | |
5957 | {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, | |
5958 | {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, | |
5959 | {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, | |
bb71536f AM |
5960 | {"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, |
5961 | {"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, | |
5962 | {"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, | |
5963 | {"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, | |
5964 | {"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, | |
5965 | {"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, | |
5966 | {"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, | |
5967 | {"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, | |
5968 | {"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, | |
5969 | {"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, | |
5970 | {"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, | |
5971 | {"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, | |
14b57c7c AM |
5972 | {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, |
5973 | {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, | |
5974 | {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, | |
5975 | {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, | |
5976 | {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, | |
5977 | {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, | |
5978 | {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, | |
5979 | {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, | |
5980 | {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, | |
5981 | {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, | |
5982 | {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, | |
5983 | {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, | |
5984 | {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, | |
5985 | {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, | |
5986 | {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, | |
5987 | {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, | |
5988 | {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, | |
5989 | {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, | |
5990 | {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, | |
5991 | {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, | |
5992 | {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, | |
5993 | {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, | |
5994 | {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, | |
5995 | {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, | |
5996 | {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, | |
5997 | {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, | |
5998 | {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, | |
fa758a70 AC |
5999 | {"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, 0, {RT, SPRGQR}}, |
6000 | {"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, 0, {RT}}, | |
6001 | {"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, 0, {RT}}, | |
6002 | {"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, 0, {RT}}, | |
6003 | {"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, 0, {RT}}, | |
14b57c7c AM |
6004 | {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, |
6005 | {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, | |
6006 | {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, | |
6007 | {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, | |
6008 | {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, | |
6009 | {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, | |
6010 | {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, | |
6011 | {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, | |
6012 | {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, | |
6013 | {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, | |
6014 | {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, | |
6015 | {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, | |
6016 | {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, | |
6017 | {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, | |
6018 | {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, | |
6019 | {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, | |
6020 | {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, | |
6021 | {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, | |
6022 | {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, | |
6023 | {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, | |
6024 | {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, | |
6025 | {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, | |
6026 | {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, | |
6027 | {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, | |
6028 | {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, | |
6029 | {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, | |
6030 | {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, | |
6031 | {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, | |
6032 | {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, | |
6033 | {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, | |
6034 | {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, | |
6035 | {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, | |
6036 | {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, | |
6037 | {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, | |
6038 | {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, | |
6039 | {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, | |
6040 | {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, | |
6041 | {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, | |
6042 | {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, | |
6043 | {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, | |
6044 | {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, | |
6045 | {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, | |
6046 | {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, | |
6047 | {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, | |
fa758a70 AC |
6048 | {"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, 0, {RT}}, |
6049 | {"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, 0, {RT}}, | |
14b57c7c | 6050 | {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, |
fa758a70 AC |
6051 | {"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, 0, {RT}}, |
6052 | {"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, 0, {RT}}, | |
14b57c7c AM |
6053 | {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, |
6054 | {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, | |
6055 | {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, | |
fa758a70 | 6056 | {"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, 0, {RT}}, |
14b57c7c AM |
6057 | {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, |
6058 | {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, | |
6059 | {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, | |
6060 | {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, | |
6061 | {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, | |
6062 | {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, | |
6063 | {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, | |
6064 | {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, | |
6065 | {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, | |
6066 | {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, | |
6067 | {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, | |
6068 | {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, | |
6069 | {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, | |
6070 | {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, | |
6071 | ||
6072 | {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, | |
6073 | ||
6074 | {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, | |
6075 | ||
6076 | {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, | |
6077 | ||
6078 | {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6079 | ||
6080 | {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, | |
6081 | {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, | |
6082 | ||
6083 | {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6084 | {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6085 | ||
6086 | {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
6087 | ||
6088 | {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, | |
1cb0a767 | 6089 | |
db76a700 | 6090 | {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
14b57c7c | 6091 | {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, |
db76a700 | 6092 | {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
1cb0a767 | 6093 | |
14b57c7c | 6094 | {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
1cb0a767 | 6095 | |
14b57c7c | 6096 | {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
1cb0a767 | 6097 | |
14b57c7c | 6098 | {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, |
1cb0a767 | 6099 | |
14b57c7c | 6100 | {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
066be9f7 | 6101 | |
14b57c7c AM |
6102 | {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, |
6103 | {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, | |
1cb0a767 | 6104 | |
ac8f0f72 | 6105 | {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6106 | |
14b57c7c AM |
6107 | {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
6108 | {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
1cb0a767 | 6109 | |
14b57c7c AM |
6110 | {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6111 | {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6112 | {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6113 | {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 6114 | |
14b57c7c AM |
6115 | {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
6116 | {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
a680de9a | 6117 | |
14b57c7c | 6118 | {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
1cb0a767 | 6119 | |
14b57c7c | 6120 | {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, |
1cb0a767 | 6121 | |
14b57c7c | 6122 | {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, |
a680de9a | 6123 | |
14b57c7c | 6124 | {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, |
c0637f3a | 6125 | |
14b57c7c AM |
6126 | {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, |
6127 | {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, | |
e0d602ec | 6128 | |
14b57c7c | 6129 | {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, |
1cb0a767 | 6130 | |
14b57c7c AM |
6131 | {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6132 | {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 6133 | |
14b57c7c | 6134 | {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
1cb0a767 | 6135 | |
62adc510 | 6136 | {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}}, |
1cb0a767 | 6137 | |
ac8f0f72 | 6138 | {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6139 | |
14b57c7c | 6140 | {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
aea77599 | 6141 | |
14b57c7c AM |
6142 | {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6143 | {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6144 | {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6145 | {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 6146 | |
14b57c7c | 6147 | {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
a680de9a | 6148 | |
14b57c7c | 6149 | {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}}, |
c0637f3a | 6150 | |
14b57c7c | 6151 | {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, |
1cb0a767 | 6152 | |
14b57c7c | 6153 | {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 6154 | |
14b57c7c | 6155 | {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
1cb0a767 | 6156 | |
14b57c7c | 6157 | {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, |
1cb0a767 | 6158 | |
14b57c7c | 6159 | {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}}, |
1cb0a767 | 6160 | |
14b57c7c | 6161 | {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}}, |
aea77599 | 6162 | |
9f6a6cc0 | 6163 | /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for |
14b57c7c AM |
6164 | "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ |
6165 | {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}}, | |
6166 | {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}}, | |
6167 | {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}}, | |
98553ad3 | 6168 | {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 6169 | {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, |
98553ad3 | 6170 | {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c AM |
6171 | {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, |
6172 | ||
6173 | {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, | |
6174 | {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, | |
6175 | {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, | |
6176 | {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, | |
6177 | {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, | |
6178 | {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, | |
6179 | {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, | |
6180 | {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, | |
6181 | {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, | |
6182 | {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, | |
6183 | {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, | |
6184 | {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, | |
6185 | {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, | |
6186 | {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, | |
6187 | {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, | |
6188 | {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, | |
6189 | {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, | |
6190 | {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, | |
6191 | {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, | |
6192 | {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, | |
6193 | {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, | |
6194 | {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, | |
6195 | {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, | |
6196 | {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, | |
6197 | {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, | |
6198 | {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, | |
6199 | {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, | |
6200 | {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, | |
6201 | {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, | |
6202 | {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, | |
6203 | {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, | |
6204 | {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, | |
6205 | {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, | |
6206 | {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, | |
6207 | {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, | |
6208 | {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, | |
6209 | ||
ac8f0f72 | 6210 | {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}}, |
14b57c7c | 6211 | |
62adc510 | 6212 | {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
14b57c7c AM |
6213 | {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
6214 | ||
6215 | {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6216 | {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6217 | ||
6218 | {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6219 | {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6220 | ||
6221 | {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, | |
c03dc33b | 6222 | {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}}, |
14b57c7c AM |
6223 | |
6224 | {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, | |
6225 | ||
6226 | {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, | |
6227 | {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, | |
6228 | {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, | |
6229 | {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, | |
6230 | {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, | |
6231 | {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, | |
6232 | {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, | |
6233 | {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, | |
6234 | {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, | |
6235 | {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, | |
6236 | {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, | |
6237 | {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, | |
6238 | {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, | |
6239 | {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, | |
6240 | {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, | |
6241 | {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, | |
6242 | {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, | |
6243 | {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, | |
6244 | {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, | |
6245 | {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, | |
6246 | {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, | |
6247 | {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, | |
6248 | {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, | |
6249 | {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, | |
6250 | {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, | |
6251 | {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, | |
6252 | {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, | |
6253 | {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, | |
6254 | {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, | |
6255 | {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, | |
6256 | {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, | |
6257 | {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, | |
6258 | {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, | |
6259 | {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, | |
6260 | {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, | |
6261 | {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, | |
6262 | {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, | |
6263 | {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, | |
6264 | {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, | |
6265 | {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, | |
6266 | {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, | |
6267 | {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, | |
6268 | {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, | |
6269 | {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, | |
6270 | {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, | |
6271 | {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, | |
6272 | {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, | |
6273 | {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6274 | {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6275 | {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6276 | {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6277 | {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, | |
6278 | {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, | |
6279 | {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, | |
6280 | {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, | |
6281 | {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, | |
6282 | {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, | |
6283 | {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, | |
6284 | {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, | |
6285 | {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, | |
6286 | {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, | |
6287 | {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, | |
6288 | {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, | |
6289 | {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, | |
6290 | {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, | |
6291 | {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, | |
6292 | {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, | |
6293 | {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, | |
6294 | {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, | |
6295 | {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, | |
6296 | {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, | |
6297 | {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, | |
6298 | {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, | |
6299 | {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, | |
6300 | {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, | |
6301 | {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, | |
6302 | {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, | |
6303 | {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, | |
6304 | {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, | |
6305 | {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, | |
6306 | {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, | |
6307 | {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, | |
6308 | {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, | |
6309 | {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, | |
6310 | {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, | |
6311 | {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, | |
6312 | {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, | |
6313 | {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, | |
4b94dd2d AM |
6314 | {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, |
6315 | {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, | |
14b57c7c AM |
6316 | {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, |
6317 | {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, | |
4b94dd2d AM |
6318 | {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
6319 | {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, | |
14b57c7c AM |
6320 | {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
6321 | {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, | |
6322 | {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
6323 | {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
6324 | {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
bb71536f AM |
6325 | {"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}}, |
6326 | {"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}}, | |
6327 | {"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}}, | |
6328 | {"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}}, | |
6329 | {"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}}, | |
6330 | {"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}}, | |
14b57c7c AM |
6331 | {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, |
6332 | {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, | |
6333 | {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, | |
6334 | {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, | |
6335 | {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, | |
6336 | {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, | |
6337 | {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, | |
6338 | {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, | |
fa758a70 AC |
6339 | {"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, 0, {SPRGQR, RS}}, |
6340 | {"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, 0, {RS}}, | |
6341 | {"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, 0, {RS}}, | |
6342 | {"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, 0, {RS}}, | |
6343 | {"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, 0, {RS}}, | |
14b57c7c AM |
6344 | {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, |
6345 | {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, | |
6346 | {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, | |
6347 | {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, | |
6348 | {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, | |
6349 | {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, | |
6350 | {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, | |
6351 | {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, | |
6352 | {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, | |
6353 | {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, | |
6354 | {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, | |
6355 | {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, | |
6356 | {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, | |
6357 | {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, | |
6358 | {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, | |
6359 | {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, | |
6360 | {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, | |
6361 | {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, | |
6362 | {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, | |
6363 | {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, | |
6364 | {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, | |
6365 | {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, | |
6366 | {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, | |
6367 | {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, | |
6368 | {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, | |
6369 | {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, | |
6370 | {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, | |
6371 | {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, | |
6372 | {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, | |
6373 | {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, | |
6374 | {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, | |
6375 | {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, | |
6376 | {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, | |
6377 | {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, | |
6378 | {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, | |
6379 | {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, | |
6380 | {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, | |
6381 | {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, | |
6382 | {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, | |
6383 | {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, | |
fa758a70 AC |
6384 | {"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, 0, {RS}}, |
6385 | {"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, 0, {RS}}, | |
14b57c7c | 6386 | {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, |
fa758a70 AC |
6387 | {"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, 0, {RS}}, |
6388 | {"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, 0, {RS}}, | |
6389 | {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, | |
14b57c7c AM |
6390 | {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, |
6391 | {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, | |
fa758a70 | 6392 | {"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, 0, {RS}}, |
14b57c7c AM |
6393 | {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, |
6394 | {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, | |
6395 | {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, | |
6396 | {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, | |
6397 | {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, | |
6398 | {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, | |
6399 | {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, | |
6400 | {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, | |
6401 | {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, | |
6402 | {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, | |
6403 | {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, | |
6404 | {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, | |
6405 | {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, | |
6406 | {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, | |
6407 | ||
6408 | {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, | |
6409 | ||
6410 | {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, | |
6411 | {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
6412 | ||
6413 | {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, | |
6414 | ||
62adc510 | 6415 | {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}}, |
14b57c7c AM |
6416 | |
6417 | {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, | |
6418 | ||
6419 | {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, | |
6420 | ||
6421 | {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, | |
6422 | {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, | |
6423 | ||
6424 | {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6425 | {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6426 | ||
6427 | {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6428 | {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6429 | ||
6430 | {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, | |
6431 | ||
6432 | {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}}, | |
4bc0608a | 6433 | {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, |
1cb0a767 | 6434 | |
14b57c7c | 6435 | {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, |
1cb0a767 | 6436 | |
14b57c7c | 6437 | {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
066be9f7 | 6438 | |
14b57c7c | 6439 | {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, |
1cb0a767 | 6440 | |
14b57c7c | 6441 | {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, |
252b5132 | 6442 | |
dfdaec14 | 6443 | {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 6444 | {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 6445 | |
14b57c7c | 6446 | {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}}, |
252b5132 | 6447 | |
14b57c7c AM |
6448 | {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, |
6449 | {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 6450 | |
14b57c7c AM |
6451 | {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6452 | {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6453 | {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
6454 | {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6455 | {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6456 | {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
43e65147 | 6457 | |
14b57c7c AM |
6458 | {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6459 | {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6460 | {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6461 | {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6462 | |
14b57c7c | 6463 | {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
c0637f3a | 6464 | |
14b57c7c | 6465 | {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, |
418c1742 | 6466 | |
14b57c7c | 6467 | {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, |
418c1742 | 6468 | |
14b57c7c AM |
6469 | {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, |
6470 | {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6471 | |
14b57c7c AM |
6472 | {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, |
6473 | {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6474 | |
14b57c7c | 6475 | {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
702f0fb4 | 6476 | |
14b57c7c AM |
6477 | {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
6478 | {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
6479 | {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
6480 | {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
252b5132 | 6481 | |
14b57c7c AM |
6482 | {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6483 | {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
23976049 | 6484 | |
14b57c7c AM |
6485 | {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
6486 | {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, | |
a680de9a | 6487 | |
14b57c7c AM |
6488 | {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
6489 | {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
f509565f | 6490 | |
14b57c7c AM |
6491 | {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6492 | {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6493 | |
dfdaec14 | 6494 | {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 6495 | {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 6496 | |
ac8f0f72 | 6497 | {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6498 | |
14b57c7c | 6499 | {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, |
418c1742 | 6500 | |
14b57c7c AM |
6501 | {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, |
6502 | {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 6503 | |
14b57c7c AM |
6504 | {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6505 | {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
6506 | {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6507 | {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
252b5132 | 6508 | |
14b57c7c | 6509 | {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, |
252b5132 | 6510 | |
14b57c7c | 6511 | {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 6512 | |
14b57c7c AM |
6513 | {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
6514 | {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, | |
a680de9a | 6515 | |
14b57c7c | 6516 | {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, |
a680de9a | 6517 | |
dfdaec14 | 6518 | {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 6519 | {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 6520 | |
ac8f0f72 | 6521 | {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6522 | |
14b57c7c | 6523 | {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
a680de9a | 6524 | |
14b57c7c | 6525 | {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 6526 | |
14b57c7c | 6527 | {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
066be9f7 | 6528 | |
14b57c7c | 6529 | {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, |
252b5132 | 6530 | |
14b57c7c AM |
6531 | {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, |
6532 | {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, | |
252b5132 | 6533 | |
dc302c00 | 6534 | {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, |
e01d869a | 6535 | {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, |
14b57c7c | 6536 | {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, |
fd486b63 PB |
6537 | {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, |
6538 | {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, | |
14b57c7c AM |
6539 | {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, |
6540 | {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, | |
6541 | {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, | |
6542 | {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}}, | |
418c1742 | 6543 | |
14b57c7c | 6544 | {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
23976049 | 6545 | |
066be9f7 | 6546 | {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, |
14b57c7c | 6547 | {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, |
252b5132 | 6548 | |
14b57c7c | 6549 | {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, |
19a6653c | 6550 | |
ac8f0f72 | 6551 | {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6552 | |
14b57c7c | 6553 | {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
a680de9a | 6554 | |
14b57c7c | 6555 | {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 6556 | |
14b57c7c AM |
6557 | {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, |
6558 | {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, | |
252b5132 | 6559 | |
14b57c7c AM |
6560 | {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6561 | {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 6562 | |
14b57c7c | 6563 | {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, |
252b5132 | 6564 | |
14b57c7c | 6565 | {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, |
252b5132 | 6566 | |
14b57c7c | 6567 | {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 6568 | |
dfdaec14 | 6569 | {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 6570 | {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 6571 | |
14b57c7c AM |
6572 | {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6573 | {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
23976049 | 6574 | |
14b57c7c | 6575 | {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
c0637f3a | 6576 | |
14b57c7c | 6577 | {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, |
5817ffd1 | 6578 | |
14b57c7c AM |
6579 | {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6580 | {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6581 | {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6582 | {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6583 | |
14b57c7c AM |
6584 | {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6585 | {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6586 | {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6587 | {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6588 | |
14b57c7c | 6589 | {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, |
418c1742 | 6590 | |
14b57c7c | 6591 | {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, |
252b5132 | 6592 | |
14b57c7c AM |
6593 | {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, |
6594 | {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
418c1742 | 6595 | |
14b57c7c AM |
6596 | {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
6597 | {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
252b5132 | 6598 | |
14b57c7c | 6599 | {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
ede602d7 | 6600 | |
14b57c7c AM |
6601 | {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6602 | {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6603 | |
14b57c7c AM |
6604 | {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6605 | {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6606 | |
dfdaec14 | 6607 | {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 6608 | {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 6609 | |
ac8f0f72 | 6610 | {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6611 | |
14b57c7c AM |
6612 | {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6613 | {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 6614 | |
14b57c7c AM |
6615 | {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, |
6616 | {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, | |
5817ffd1 | 6617 | |
14b57c7c | 6618 | {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
066be9f7 | 6619 | |
14b57c7c | 6620 | {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 6621 | |
14b57c7c AM |
6622 | {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6623 | {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 6624 | |
dfdaec14 | 6625 | {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 6626 | {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 6627 | |
ac8f0f72 | 6628 | {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6629 | |
14b57c7c | 6630 | {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
a680de9a | 6631 | |
14b57c7c | 6632 | {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 6633 | |
14b57c7c | 6634 | {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
066be9f7 | 6635 | |
14b57c7c | 6636 | {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, |
5817ffd1 | 6637 | |
14b57c7c AM |
6638 | {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6639 | {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6640 | {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6641 | {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 6642 | |
14b57c7c AM |
6643 | {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6644 | {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6645 | {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6646 | {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
fdd12ef3 | 6647 | |
14b57c7c AM |
6648 | {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, |
6649 | {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, | |
252b5132 | 6650 | |
14b57c7c | 6651 | {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
066be9f7 | 6652 | |
14b57c7c | 6653 | {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
252b5132 | 6654 | |
14b57c7c AM |
6655 | {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6656 | {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
418c1742 | 6657 | |
14b57c7c AM |
6658 | {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6659 | {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6660 | |
066be9f7 | 6661 | {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, |
14b57c7c | 6662 | {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, |
252b5132 | 6663 | |
14b57c7c | 6664 | {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, |
19a6653c | 6665 | |
ac8f0f72 | 6666 | {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6667 | |
14b57c7c | 6668 | {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
a680de9a | 6669 | |
14b57c7c | 6670 | {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 6671 | |
14b57c7c AM |
6672 | {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6673 | {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6674 | {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6675 | {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 6676 | |
14b57c7c AM |
6677 | {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6678 | {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
252b5132 | 6679 | |
14b57c7c AM |
6680 | {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6681 | {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6682 | {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6683 | {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 6684 | |
14b57c7c AM |
6685 | {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6686 | {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6687 | {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6688 | {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
702f0fb4 | 6689 | |
14b57c7c AM |
6690 | {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
6691 | {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}}, | |
6692 | {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, | |
5817ffd1 | 6693 | |
14b57c7c | 6694 | {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, |
a680de9a | 6695 | |
14b57c7c AM |
6696 | {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
6697 | {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, | |
252b5132 | 6698 | |
14b57c7c | 6699 | {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 6700 | |
14b57c7c AM |
6701 | {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6702 | {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 6703 | |
ac8f0f72 | 6704 | {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}}, |
a680de9a | 6705 | |
fd486b63 | 6706 | {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, |
a680de9a | 6707 | |
ac8f0f72 | 6708 | {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}}, |
14b57c7c AM |
6709 | {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, |
6710 | {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
ede602d7 | 6711 | |
14b57c7c AM |
6712 | {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6713 | {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 6714 | |
14b57c7c AM |
6715 | {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6716 | {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6717 | {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6718 | {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6719 | |
14b57c7c AM |
6720 | {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, |
6721 | {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, | |
a680de9a | 6722 | |
14b57c7c AM |
6723 | {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
6724 | {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
066be9f7 | 6725 | |
14b57c7c | 6726 | {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
5817ffd1 | 6727 | |
14b57c7c | 6728 | {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
252b5132 | 6729 | |
14b57c7c | 6730 | {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 6731 | |
14b57c7c | 6732 | {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, |
252b5132 | 6733 | |
73f07bff | 6734 | {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, |
14b57c7c | 6735 | {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
418c1742 | 6736 | |
14b57c7c AM |
6737 | {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
6738 | {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
6739 | {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
6740 | {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
fdd12ef3 | 6741 | |
14b57c7c AM |
6742 | {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
6743 | {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
252b5132 | 6744 | |
74081948 | 6745 | {"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, |
14b57c7c | 6746 | {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, |
19a6653c | 6747 | |
ac8f0f72 AM |
6748 | {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, |
6749 | {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}}, | |
14b57c7c | 6750 | {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, |
252b5132 | 6751 | |
14b57c7c AM |
6752 | {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
6753 | {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
a680de9a | 6754 | |
14b57c7c | 6755 | {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
5817ffd1 | 6756 | |
14b57c7c | 6757 | {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, |
252b5132 | 6758 | |
14b57c7c | 6759 | {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, |
e0d602ec | 6760 | |
14b57c7c | 6761 | {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 6762 | |
14b57c7c | 6763 | {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, |
252b5132 | 6764 | |
14b57c7c | 6765 | {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
fdd12ef3 | 6766 | |
14b57c7c AM |
6767 | {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, |
6768 | {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, | |
6769 | {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, | |
6770 | {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, | |
702f0fb4 | 6771 | |
14b57c7c AM |
6772 | {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, |
6773 | {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, | |
e0c21649 | 6774 | |
ac8f0f72 | 6775 | {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6776 | |
fd486b63 | 6777 | {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, |
a680de9a | 6778 | |
14b57c7c AM |
6779 | {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6780 | {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 6781 | |
14b57c7c | 6782 | {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
a680de9a | 6783 | {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, |
9b4e5766 | 6784 | |
14b57c7c | 6785 | {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
5817ffd1 | 6786 | |
14b57c7c | 6787 | {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, |
e0d602ec | 6788 | |
fd486b63 | 6789 | {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}}, |
14b57c7c | 6790 | {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
a680de9a | 6791 | {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
252b5132 | 6792 | |
14b57c7c | 6793 | {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
418c1742 | 6794 | |
9fe54b1c | 6795 | {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, |
14b57c7c AM |
6796 | {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, |
6797 | {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, | |
6798 | {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, | |
418c1742 | 6799 | |
14b57c7c | 6800 | {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, |
418c1742 | 6801 | |
ac8f0f72 | 6802 | {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6803 | |
14b57c7c AM |
6804 | {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
6805 | {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, | |
702f0fb4 | 6806 | |
14b57c7c AM |
6807 | {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6808 | {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 6809 | |
14b57c7c | 6810 | {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 6811 | |
14b57c7c | 6812 | {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
5817ffd1 | 6813 | |
14b57c7c | 6814 | {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, |
a680de9a | 6815 | |
14b57c7c | 6816 | {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 6817 | |
14b57c7c | 6818 | {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}}, |
a680de9a | 6819 | |
14b57c7c | 6820 | {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, |
066be9f7 | 6821 | |
14b57c7c AM |
6822 | {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, |
6823 | {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, | |
a680de9a | 6824 | |
fd486b63 | 6825 | {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, |
a680de9a | 6826 | |
14b57c7c AM |
6827 | {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6828 | {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 6829 | |
14b57c7c AM |
6830 | {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6831 | {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6832 | {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6833 | {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 6834 | |
14b57c7c AM |
6835 | {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
6836 | {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
066be9f7 | 6837 | |
14b57c7c | 6838 | {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
5817ffd1 | 6839 | |
14b57c7c AM |
6840 | {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, |
6841 | {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, | |
252b5132 | 6842 | |
14b57c7c | 6843 | {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
a680de9a | 6844 | {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
702f0fb4 | 6845 | |
14b57c7c | 6846 | {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
f5c120c5 | 6847 | |
14b57c7c | 6848 | {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, |
252b5132 | 6849 | |
73f07bff | 6850 | {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, |
14b57c7c | 6851 | {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, |
6ba045b1 | 6852 | |
14b57c7c AM |
6853 | {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6854 | {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
702f0fb4 | 6855 | |
14b57c7c AM |
6856 | {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6857 | {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6858 | |
14b57c7c AM |
6859 | {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, |
6860 | {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
6861 | {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
6862 | {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
702f0fb4 | 6863 | |
74081948 | 6864 | {"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, |
14b57c7c | 6865 | {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, |
19a6653c | 6866 | |
ac8f0f72 | 6867 | {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6868 | |
14b57c7c | 6869 | {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, |
a5721ba2 AM |
6870 | {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}}, |
6871 | {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, | |
85d4ac0b | 6872 | |
14b57c7c | 6873 | {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6ba045b1 | 6874 | |
14b57c7c AM |
6875 | {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6876 | {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6877 | {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6878 | {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 6879 | |
14b57c7c AM |
6880 | {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
6881 | {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
a680de9a | 6882 | |
14b57c7c | 6883 | {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
5817ffd1 | 6884 | |
e0d602ec BE |
6885 | {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, |
6886 | {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, | |
14b57c7c | 6887 | {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, |
702f0fb4 | 6888 | |
14b57c7c | 6889 | {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
252b5132 | 6890 | |
14b57c7c AM |
6891 | {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, |
6892 | {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, | |
51b5d4a8 | 6893 | |
14b57c7c | 6894 | {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, |
252b5132 | 6895 | |
14b57c7c AM |
6896 | {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6897 | {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 6898 | |
14b57c7c AM |
6899 | {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, |
6900 | {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, | |
252b5132 | 6901 | |
ac8f0f72 | 6902 | {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6903 | |
62adc510 | 6904 | {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
14b57c7c | 6905 | {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
43e65147 | 6906 | |
14b57c7c AM |
6907 | {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6908 | {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 6909 | |
14b57c7c AM |
6910 | {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6911 | {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
252b5132 | 6912 | |
14b57c7c | 6913 | {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
a680de9a | 6914 | {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, |
9b4e5766 | 6915 | |
9fe54b1c | 6916 | {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, |
14b57c7c AM |
6917 | {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, |
6918 | {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, | |
6919 | {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, | |
418c1742 | 6920 | |
14b57c7c | 6921 | {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, |
c4e676f1 | 6922 | |
14b57c7c | 6923 | {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
252b5132 | 6924 | |
14b57c7c | 6925 | {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, |
252b5132 | 6926 | |
14b57c7c | 6927 | {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, |
702f0fb4 | 6928 | |
14b57c7c AM |
6929 | {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
6930 | {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, | |
252b5132 | 6931 | |
14b57c7c | 6932 | {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
19a6653c | 6933 | |
ac8f0f72 | 6934 | {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6935 | |
14b57c7c | 6936 | {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, |
252b5132 | 6937 | |
14b57c7c AM |
6938 | {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
6939 | {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, | |
252b5132 | 6940 | |
14b57c7c AM |
6941 | {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6942 | {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 6943 | |
14b57c7c AM |
6944 | {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6945 | {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
418c1742 | 6946 | |
14b57c7c | 6947 | {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
a680de9a | 6948 | |
14b57c7c | 6949 | {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
702f0fb4 | 6950 | |
14b57c7c | 6951 | {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, |
252b5132 | 6952 | |
14b57c7c | 6953 | {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
418c1742 | 6954 | |
14b57c7c AM |
6955 | {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, |
6956 | {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, | |
786e2c0f | 6957 | |
14b57c7c | 6958 | {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
ede602d7 | 6959 | |
14b57c7c | 6960 | {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, |
252b5132 | 6961 | |
14b57c7c AM |
6962 | {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}}, |
6963 | {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}}, | |
6964 | {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}}, | |
252b5132 | 6965 | |
14b57c7c AM |
6966 | {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
6967 | {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, | |
6968 | {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, | |
252b5132 | 6969 | |
14b57c7c AM |
6970 | {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}}, |
6971 | {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}}, | |
6972 | {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}}, | |
6973 | {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}}, | |
252b5132 | 6974 | |
14b57c7c AM |
6975 | {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, |
6976 | {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 6977 | |
14b57c7c AM |
6978 | {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, |
6979 | {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 6980 | |
14b57c7c | 6981 | {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 6982 | |
14b57c7c | 6983 | {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 6984 | |
14b57c7c AM |
6985 | {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
6986 | {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 6987 | |
14b57c7c AM |
6988 | {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, |
6989 | {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 6990 | |
14b57c7c | 6991 | {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
252b5132 | 6992 | |
14b57c7c | 6993 | {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
252b5132 | 6994 | |
14b57c7c | 6995 | {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 6996 | |
14b57c7c | 6997 | {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 6998 | |
14b57c7c | 6999 | {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 7000 | |
14b57c7c | 7001 | {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 7002 | |
14b57c7c | 7003 | {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
252b5132 | 7004 | |
14b57c7c | 7005 | {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
252b5132 | 7006 | |
14b57c7c AM |
7007 | {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, |
7008 | {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 7009 | |
14b57c7c AM |
7010 | {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
7011 | {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 7012 | |
14b57c7c | 7013 | {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
252b5132 | 7014 | |
14b57c7c | 7015 | {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
252b5132 | 7016 | |
14b57c7c | 7017 | {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
252b5132 | 7018 | |
14b57c7c | 7019 | {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
252b5132 | 7020 | |
14b57c7c | 7021 | {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
adadcc0c | 7022 | |
14b57c7c | 7023 | {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
252b5132 | 7024 | |
14b57c7c | 7025 | {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
c3d65c1c | 7026 | |
14b57c7c | 7027 | {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
252b5132 | 7028 | |
73f07bff | 7029 | {"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, |
14b57c7c AM |
7030 | {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
7031 | {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, | |
418c1742 | 7032 | |
14b57c7c AM |
7033 | {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, |
7034 | {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, | |
73f07bff | 7035 | {"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, |
14b57c7c AM |
7036 | {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
7037 | {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, | |
802a735e | 7038 | |
14b57c7c AM |
7039 | {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, |
7040 | {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, | |
7041 | {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, | |
702f0fb4 | 7042 | |
14b57c7c AM |
7043 | {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
7044 | {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7045 | |
14b57c7c AM |
7046 | {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, |
7047 | {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, | |
252b5132 | 7048 | |
14b57c7c AM |
7049 | {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7050 | {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7051 | |
14b57c7c AM |
7052 | {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7053 | {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7054 | |
14b57c7c AM |
7055 | {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7056 | {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7057 | |
14b57c7c AM |
7058 | {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, |
7059 | {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, | |
252b5132 | 7060 | |
14b57c7c AM |
7061 | {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7062 | {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7063 | {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7064 | {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
1ed8e1e4 | 7065 | |
14b57c7c AM |
7066 | {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
7067 | {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, | |
252b5132 | 7068 | |
14b57c7c AM |
7069 | {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7070 | {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7071 | {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7072 | {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
252b5132 | 7073 | |
14b57c7c AM |
7074 | {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7075 | {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7076 | |
14b57c7c AM |
7077 | {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7078 | {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7079 | |
14b57c7c AM |
7080 | {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7081 | {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 7082 | |
14b57c7c AM |
7083 | {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7084 | {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 7085 | |
14b57c7c AM |
7086 | {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
7087 | {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
702f0fb4 | 7088 | |
14b57c7c AM |
7089 | {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, |
7090 | {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, | |
702f0fb4 | 7091 | |
14b57c7c AM |
7092 | {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
7093 | {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, | |
702f0fb4 | 7094 | |
14b57c7c AM |
7095 | {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, |
7096 | {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, | |
702f0fb4 | 7097 | |
14b57c7c AM |
7098 | {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
7099 | {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, | |
702f0fb4 | 7100 | |
14b57c7c AM |
7101 | {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, |
7102 | {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
702f0fb4 | 7103 | |
14b57c7c | 7104 | {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
702f0fb4 | 7105 | |
14b57c7c AM |
7106 | {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
7107 | {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, | |
7108 | {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, | |
7109 | ||
7110 | {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
7111 | {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
7112 | ||
7113 | {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7114 | {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7115 | ||
7116 | {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7117 | {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7118 | ||
7119 | {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, | |
7120 | {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, | |
7121 | ||
7122 | {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7123 | {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7124 | ||
7125 | {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7126 | {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7127 | ||
7128 | {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7129 | {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7130 | ||
7131 | {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, | |
7132 | ||
7133 | {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, | |
7134 | {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, | |
7135 | ||
7136 | {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7137 | {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7138 | ||
7139 | {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7140 | {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7141 | ||
7142 | {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, | |
7143 | {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, | |
7144 | ||
7145 | {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
7146 | {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
7147 | ||
7148 | {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7149 | {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7150 | ||
7151 | {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
7152 | {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
7153 | ||
7154 | {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7155 | {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7156 | {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, | |
7157 | {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7158 | {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7159 | {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7160 | {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, | |
7161 | {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7162 | {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
98553ad3 | 7163 | {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XAB6, DMEX}}, |
14b57c7c | 7164 | {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
98553ad3 | 7165 | {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
7166 | {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
7167 | {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, | |
7168 | {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7169 | {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7170 | {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7171 | {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7172 | {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7173 | {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7174 | {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7175 | {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7176 | {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7177 | {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7178 | {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7179 | {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7180 | {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7181 | {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7182 | {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7183 | {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7184 | {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7185 | {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7186 | {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7187 | {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7188 | {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7189 | {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7190 | {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7191 | {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7192 | {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7193 | {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7194 | {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
7195 | {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7196 | {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7197 | {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7198 | {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7199 | {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, | |
7200 | {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7201 | {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7202 | {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7203 | {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7204 | {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7205 | {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7206 | {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7207 | {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7208 | {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7209 | {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7210 | {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7211 | {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7212 | {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7213 | {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7214 | {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7215 | {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7216 | {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7217 | {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7218 | {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7219 | {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, | |
7220 | {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, | |
7221 | {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7222 | {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7223 | {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7224 | {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7225 | {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
7226 | {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7227 | {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7228 | {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7229 | {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, | |
7230 | {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, | |
7231 | {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7232 | {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7233 | {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7234 | {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7235 | {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7236 | {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7237 | {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7238 | {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7239 | {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7240 | {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7241 | {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7242 | {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7243 | {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7244 | {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7245 | {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7246 | {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7247 | {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7248 | {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7249 | {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7250 | {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7251 | {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7252 | {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7253 | {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7254 | {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7255 | {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
7256 | {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7257 | {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7258 | {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7259 | {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7260 | {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7261 | {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7262 | {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7263 | {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7264 | {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7265 | {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7266 | {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7267 | {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7268 | {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7269 | {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7270 | {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7271 | {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7272 | {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7273 | {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7274 | {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7275 | {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, | |
7276 | {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7277 | {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7278 | {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7279 | {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7280 | {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7281 | {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7282 | {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7283 | {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7284 | {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7285 | {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7286 | {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7287 | {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7288 | {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7289 | {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7290 | {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7291 | {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, | |
7292 | {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, | |
7293 | {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7294 | {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7295 | {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7296 | {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7297 | {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7298 | {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7299 | {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7300 | {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, | |
7301 | {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7302 | {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7303 | {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7304 | {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7305 | {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7306 | {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7307 | {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7308 | {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7309 | {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7310 | {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7311 | {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7312 | {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
98553ad3 | 7313 | {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
7314 | {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
7315 | {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7316 | {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7317 | {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7318 | {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, | |
7319 | {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7320 | {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7321 | {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7322 | {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7323 | {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7324 | {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7325 | {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7326 | {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7327 | {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, | |
7328 | {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7329 | {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7330 | {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7331 | {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7332 | {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7333 | {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7334 | {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7335 | {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7336 | {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7337 | {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7338 | {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7339 | {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7340 | {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
7341 | {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
98553ad3 | 7342 | {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
7343 | {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
7344 | {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7345 | {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7346 | {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7347 | {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, | |
7348 | {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7349 | {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7350 | {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7351 | {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7352 | ||
7353 | {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, | |
7354 | {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, | |
7355 | ||
7356 | {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, | |
7357 | {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, | |
7358 | {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, | |
7359 | {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, | |
73f07bff | 7360 | {"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, |
14b57c7c AM |
7361 | {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, |
7362 | {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, | |
7363 | ||
7364 | {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, | |
7365 | {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, | |
73f07bff | 7366 | {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, |
14b57c7c AM |
7367 | |
7368 | {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, | |
7369 | ||
73f07bff AM |
7370 | {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
7371 | {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
14b57c7c | 7372 | |
73f07bff AM |
7373 | {"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, |
7374 | {"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, | |
14b57c7c AM |
7375 | |
7376 | {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
7377 | {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
7378 | ||
7379 | {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, | |
7380 | {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, | |
7381 | ||
7382 | {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, | |
7383 | {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, | |
7384 | ||
7385 | {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
7386 | {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
7387 | ||
7388 | {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
7389 | {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
7390 | {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
7391 | {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
7392 | ||
7393 | {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
7394 | {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
7395 | {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
7396 | {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
7397 | ||
7398 | {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
7399 | {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
7400 | {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
7401 | {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
7402 | ||
7403 | {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
7404 | {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
7405 | {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
7406 | {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
7407 | ||
7408 | {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
7409 | {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
7410 | {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
7411 | {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
7412 | ||
7413 | {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, | |
7414 | {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, | |
7415 | ||
7416 | {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7417 | {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7418 | ||
7419 | {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7420 | {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7421 | {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7422 | {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
1ed8e1e4 | 7423 | |
14b57c7c AM |
7424 | {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
7425 | {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, | |
7426 | {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, | |
7427 | {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, | |
252b5132 | 7428 | |
14b57c7c AM |
7429 | {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7430 | {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7431 | {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7432 | {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
252b5132 | 7433 | |
14b57c7c AM |
7434 | {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7435 | {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7436 | {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7437 | {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7438 | |
14b57c7c AM |
7439 | {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7440 | {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7441 | {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7442 | {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7443 | |
14b57c7c AM |
7444 | {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7445 | {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7446 | {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7447 | {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7448 | |
14b57c7c AM |
7449 | {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7450 | {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7451 | {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
7452 | {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7453 | |
14b57c7c | 7454 | {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, |
252b5132 | 7455 | |
73f07bff AM |
7456 | {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
7457 | {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 7458 | |
73f07bff AM |
7459 | {"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, |
7460 | {"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, | |
702f0fb4 | 7461 | |
14b57c7c AM |
7462 | {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
7463 | {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 7464 | |
14b57c7c | 7465 | {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, |
a680de9a | 7466 | |
14b57c7c AM |
7467 | {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}}, |
7468 | {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}}, | |
252b5132 | 7469 | |
14b57c7c AM |
7470 | {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
7471 | {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 7472 | |
14b57c7c | 7473 | {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, |
252b5132 | 7474 | |
73f07bff AM |
7475 | {"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
7476 | {"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 7477 | |
73f07bff AM |
7478 | {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, |
7479 | {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, | |
702f0fb4 | 7480 | |
14b57c7c AM |
7481 | {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}}, |
7482 | {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}}, | |
252b5132 | 7483 | |
14b57c7c AM |
7484 | {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
7485 | {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 7486 | |
73f07bff AM |
7487 | {"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
7488 | {"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 7489 | |
73f07bff AM |
7490 | {"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
7491 | {"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 7492 | |
14b57c7c | 7493 | {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
a680de9a | 7494 | |
14b57c7c | 7495 | {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, |
066be9f7 | 7496 | |
14b57c7c | 7497 | {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
702f0fb4 | 7498 | |
14b57c7c | 7499 | {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 7500 | |
14b57c7c AM |
7501 | {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, |
7502 | {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, | |
7503 | {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, | |
7504 | {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, | |
252b5132 | 7505 | |
14b57c7c AM |
7506 | {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
7507 | {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 7508 | |
14b57c7c AM |
7509 | {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7510 | {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7511 | {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7512 | {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 7513 | |
14b57c7c | 7514 | {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, |
066be9f7 | 7515 | |
14b57c7c | 7516 | {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
a680de9a | 7517 | |
14b57c7c | 7518 | {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 7519 | |
14b57c7c AM |
7520 | {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, |
7521 | {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, | |
702f0fb4 | 7522 | |
73f07bff AM |
7523 | {"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
7524 | {"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 7525 | |
73f07bff AM |
7526 | {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
7527 | {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, | |
702f0fb4 | 7528 | |
14b57c7c AM |
7529 | {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
7530 | {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 7531 | |
14b57c7c AM |
7532 | {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
7533 | {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, | |
702f0fb4 | 7534 | |
73f07bff AM |
7535 | {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, |
7536 | {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, | |
702f0fb4 | 7537 | |
14b57c7c AM |
7538 | {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
7539 | {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, | |
702f0fb4 | 7540 | |
14b57c7c AM |
7541 | {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
7542 | {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 7543 | |
14b57c7c AM |
7544 | {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
7545 | {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 7546 | |
14b57c7c AM |
7547 | {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
7548 | {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 7549 | |
14b57c7c AM |
7550 | {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
7551 | {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 7552 | |
14b57c7c AM |
7553 | {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
7554 | {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 7555 | |
14b57c7c AM |
7556 | {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
7557 | {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 7558 | |
14b57c7c AM |
7559 | {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
7560 | {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 7561 | |
14b57c7c AM |
7562 | {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
7563 | {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
ce7a772b | 7564 | |
73f07bff AM |
7565 | {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
7566 | {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 7567 | |
14b57c7c AM |
7568 | {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
7569 | {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 7570 | |
73f07bff AM |
7571 | {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
7572 | {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 7573 | |
14b57c7c AM |
7574 | {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
7575 | {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 7576 | |
14b57c7c AM |
7577 | {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, |
7578 | {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, | |
252b5132 | 7579 | |
6fd3a02d PB |
7580 | {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, |
7581 | {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, | |
7582 | {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, | |
7583 | {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, | |
7584 | {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, | |
7585 | {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, | |
7586 | ||
14b57c7c | 7587 | {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
702f0fb4 | 7588 | |
14b57c7c | 7589 | {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 7590 | |
14b57c7c AM |
7591 | {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, |
7592 | {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, | |
a680de9a | 7593 | |
14b57c7c | 7594 | {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, |
702f0fb4 | 7595 | |
14b57c7c AM |
7596 | {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, |
7597 | {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, | |
7598 | {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, | |
7599 | {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, | |
252b5132 | 7600 | |
73f07bff AM |
7601 | {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, |
7602 | {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, | |
702f0fb4 | 7603 | |
73f07bff AM |
7604 | {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
7605 | {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, | |
702f0fb4 | 7606 | |
14b57c7c AM |
7607 | {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
7608 | {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7609 | {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7610 | {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7611 | {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7612 | {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7613 | {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
a680de9a | 7614 | |
14b57c7c AM |
7615 | {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
7616 | {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
7617 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
7618 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 7619 | |
14b57c7c AM |
7620 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
7621 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
7622 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
7623 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 7624 | |
73f07bff AM |
7625 | {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, |
7626 | {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, | |
702f0fb4 | 7627 | |
14b57c7c AM |
7628 | {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
7629 | {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7630 | {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7631 | {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7632 | {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7633 | {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7634 | {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7635 | {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
7636 | {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
a680de9a | 7637 | |
14b57c7c | 7638 | {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
c0637f3a | 7639 | |
14b57c7c AM |
7640 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
7641 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
7642 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
7643 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 7644 | |
73f07bff AM |
7645 | {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, |
7646 | {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, | |
702f0fb4 | 7647 | |
14b57c7c | 7648 | {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
a680de9a | 7649 | |
14b57c7c AM |
7650 | {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
7651 | {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 7652 | |
14b57c7c AM |
7653 | {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
7654 | {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 7655 | |
14b57c7c | 7656 | {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
c0637f3a | 7657 | |
14b57c7c AM |
7658 | {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
7659 | {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
252b5132 RH |
7660 | }; |
7661 | ||
2ceb7719 | 7662 | const unsigned int powerpc_num_opcodes = |
252b5132 RH |
7663 | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
7664 | \f | |
b9c361e0 JL |
7665 | /* The VLE opcode table. |
7666 | ||
7667 | The format of this opcode table is the same as the main opcode table. */ | |
7668 | ||
7669 | const struct powerpc_opcode vle_opcodes[] = { | |
14b57c7c AM |
7670 | {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, |
7671 | {"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, | |
7672 | {"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, | |
7673 | {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, | |
7674 | {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, | |
7675 | {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, | |
7676 | {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, | |
7677 | {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, | |
7678 | {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, | |
7679 | {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, | |
7680 | {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, | |
a8cc8a54 | 7681 | {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}}, |
14b57c7c AM |
7682 | {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, |
7683 | {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7684 | {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7685 | {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7686 | {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7687 | {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7688 | {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7689 | {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7690 | {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7691 | {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, | |
7692 | {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7693 | {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, | |
7694 | {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, | |
7695 | {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7696 | {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7697 | {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7698 | {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7699 | {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7700 | {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7701 | {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7702 | {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
7703 | ||
e3c2f928 AF |
7704 | /* by major opcode */ |
7705 | {"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
7706 | {"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
7707 | {"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7708 | {"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7709 | {"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7710 | {"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7711 | {"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7712 | {"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7713 | {"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7714 | {"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7715 | {"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7716 | {"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7717 | {"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7718 | {"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7719 | {"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7720 | {"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7721 | {"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7722 | {"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7723 | {"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7724 | {"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7725 | {"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7726 | {"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7727 | {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7728 | {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7729 | {"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7730 | {"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7731 | {"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7732 | {"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7733 | {"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7734 | {"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7735 | {"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7736 | {"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7737 | {"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7738 | {"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7739 | {"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7740 | {"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7741 | {"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
7742 | {"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
7743 | {"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
7744 | {"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
7745 | {"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
7746 | {"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7747 | {"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7748 | {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7749 | {"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7750 | {"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7751 | {"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7752 | {"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7753 | {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, | |
7754 | {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, | |
7755 | {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7756 | {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7757 | {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7758 | {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7759 | {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7760 | {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7761 | {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7762 | {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7763 | {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7764 | {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7765 | {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7766 | {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7767 | {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7768 | {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7769 | {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7770 | {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7771 | {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7772 | {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7773 | {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7774 | {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7775 | {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7776 | {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
7777 | {"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7778 | {"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7779 | {"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7780 | {"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7781 | {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}}, | |
7782 | {"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7783 | {"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7784 | {"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7785 | {"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7786 | {"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7787 | {"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
7788 | {"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
7789 | {"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7790 | {"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7791 | {"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
7792 | {"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
7793 | {"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7794 | {"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7795 | {"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
7796 | {"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
7797 | {"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7798 | {"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7799 | {"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
7800 | {"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
7801 | {"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7802 | {"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7803 | {"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7804 | {"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7805 | {"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7806 | {"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7807 | {"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7808 | {"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7809 | {"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7810 | {"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7811 | {"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7812 | {"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7813 | {"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7814 | {"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7815 | {"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7816 | {"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7817 | {"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7818 | {"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7819 | {"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7820 | {"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7821 | {"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7822 | {"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7823 | {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
7824 | {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
7825 | {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
7826 | {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
7827 | {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
7828 | {"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7829 | {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7830 | {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7831 | {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7832 | {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7833 | {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7834 | {"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7835 | {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7836 | {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7837 | {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7838 | {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7839 | {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7840 | {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7841 | {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7842 | {"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7843 | {"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7844 | {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7845 | {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7846 | {"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7847 | {"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7848 | {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7849 | {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7850 | {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7851 | {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7852 | {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7853 | {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7854 | {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7855 | {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7856 | {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7857 | {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7858 | {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7859 | {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7860 | {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7861 | {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7862 | {"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7863 | {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7864 | {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7865 | {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7866 | {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7867 | {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7868 | {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7869 | {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7870 | {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7871 | {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7872 | {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7873 | {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7874 | {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7875 | {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7876 | {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7877 | {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7878 | {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7879 | {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7880 | {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7881 | {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7882 | {"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7883 | {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7884 | {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7885 | {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7886 | {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7887 | {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
7888 | {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7889 | {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7890 | {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7891 | {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7892 | {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7893 | {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7894 | {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7895 | {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7896 | {"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7897 | {"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7898 | {"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7899 | {"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7900 | {"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7901 | {"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7902 | {"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7903 | {"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7904 | {"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7905 | {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7906 | {"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7907 | {"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7908 | {"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7909 | {"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7910 | {"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7911 | {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7912 | {"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7913 | {"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7914 | {"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7915 | {"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7916 | {"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7917 | {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7918 | {"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7919 | {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7920 | {"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7921 | {"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7922 | {"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7923 | {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7924 | {"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7925 | {"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7926 | {"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7927 | {"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7928 | {"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7929 | {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7930 | {"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7931 | {"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7932 | {"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7933 | {"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7934 | {"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7935 | {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7936 | {"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7937 | {"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7938 | {"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7939 | {"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7940 | {"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7941 | {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7942 | {"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7943 | {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7944 | {"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7945 | {"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7946 | {"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7947 | {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7948 | {"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7949 | {"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7950 | {"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7951 | {"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7952 | {"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7953 | {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7954 | {"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7955 | {"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7956 | {"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7957 | {"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7958 | {"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7959 | {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7960 | {"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7961 | {"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7962 | {"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7963 | {"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7964 | {"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7965 | {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7966 | {"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7967 | {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7968 | {"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7969 | {"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7970 | {"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7971 | {"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7972 | {"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7973 | {"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7974 | {"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7975 | {"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7976 | {"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7977 | {"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7978 | {"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7979 | {"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7980 | {"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7981 | {"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7982 | {"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7983 | {"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7984 | {"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7985 | {"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7986 | {"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7987 | {"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7988 | {"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7989 | {"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7990 | {"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7991 | {"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7992 | {"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7993 | {"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7994 | {"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7995 | {"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7996 | {"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7997 | {"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7998 | {"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
7999 | {"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8000 | {"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8001 | {"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8002 | {"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8003 | {"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8004 | {"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8005 | {"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8006 | {"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8007 | {"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8008 | {"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8009 | {"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8010 | {"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8011 | {"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8012 | {"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8013 | {"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8014 | {"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8015 | {"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8016 | {"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8017 | {"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8018 | {"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8019 | {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8020 | {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8021 | {"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8022 | {"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8023 | {"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8024 | {"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8025 | {"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8026 | {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8027 | {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8028 | {"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8029 | {"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8030 | {"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8031 | {"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8032 | {"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8033 | {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8034 | {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8035 | {"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8036 | {"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8037 | {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8038 | {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8039 | {"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8040 | {"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8041 | {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8042 | {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8043 | {"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8044 | {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8045 | {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8046 | {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8047 | {"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8048 | {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8049 | {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8050 | {"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8051 | {"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8052 | {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8053 | {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8054 | {"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8055 | {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8056 | {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8057 | {"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8058 | {"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8059 | {"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8060 | {"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8061 | {"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8062 | {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8063 | {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8064 | {"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8065 | {"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8066 | {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8067 | {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8068 | {"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8069 | {"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8070 | {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8071 | {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8072 | {"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8073 | {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8074 | {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8075 | {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8076 | {"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8077 | {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8078 | {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8079 | {"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8080 | {"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8081 | {"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8082 | {"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8083 | {"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8084 | {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8085 | {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8086 | {"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8087 | {"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8088 | {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8089 | {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8090 | {"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8091 | {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8092 | {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8093 | {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8094 | {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8095 | {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8096 | {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8097 | {"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8098 | {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8099 | {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8100 | {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8101 | {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8102 | {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8103 | {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8104 | {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8105 | {"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8106 | {"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8107 | {"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8108 | {"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8109 | {"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8110 | {"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8111 | {"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8112 | {"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8113 | {"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8114 | {"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8115 | {"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8116 | {"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8117 | {"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8118 | {"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8119 | {"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8120 | {"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8121 | {"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8122 | {"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8123 | {"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8124 | {"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8125 | {"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8126 | {"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8127 | {"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8128 | {"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8129 | {"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8130 | {"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8131 | {"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8132 | {"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8133 | {"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8134 | {"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8135 | {"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8136 | {"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8137 | {"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8138 | {"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8139 | {"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8140 | {"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8141 | {"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8142 | {"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8143 | {"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8144 | {"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8145 | {"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8146 | {"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8147 | {"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8148 | {"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8149 | {"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8150 | {"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8151 | {"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8152 | {"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8153 | {"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8154 | {"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8155 | {"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8156 | {"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8157 | {"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8158 | {"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8159 | {"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8160 | {"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8161 | {"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8162 | {"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8163 | {"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8164 | {"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8165 | {"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8166 | {"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8167 | {"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8168 | {"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8169 | {"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8170 | {"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8171 | {"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8172 | {"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8173 | {"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8174 | {"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8175 | {"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8176 | {"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8177 | {"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8178 | {"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8179 | {"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8180 | {"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8181 | {"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8182 | {"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8183 | {"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8184 | {"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8185 | {"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8186 | {"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8187 | {"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8188 | {"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8189 | {"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8190 | {"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8191 | {"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8192 | {"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8193 | {"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8194 | {"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8195 | {"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8196 | {"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8197 | {"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8198 | {"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8199 | {"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8200 | {"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8201 | {"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8202 | {"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8203 | {"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8204 | {"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8205 | {"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8206 | {"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8207 | {"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8208 | {"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8209 | {"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8210 | {"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8211 | {"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8212 | {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8213 | {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8214 | {"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8215 | {"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8216 | {"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8217 | {"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8218 | {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8219 | {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8220 | {"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8221 | {"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8222 | {"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8223 | {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8224 | {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8225 | {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8226 | {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8227 | {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8228 | {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8229 | {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8230 | {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8231 | {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8232 | {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8233 | {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8234 | {"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8235 | {"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8236 | {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8237 | {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8238 | {"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8239 | {"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8240 | {"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8241 | {"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8242 | {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8243 | {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8244 | {"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8245 | {"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8246 | {"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8247 | {"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8248 | {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8249 | {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8250 | {"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8251 | {"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8252 | {"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8253 | {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8254 | {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8255 | {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8256 | {"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8257 | {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8258 | {"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8259 | {"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8260 | {"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8261 | {"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8262 | {"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8263 | {"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8264 | {"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8265 | {"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8266 | {"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8267 | {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8268 | {"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8269 | {"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8270 | {"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8271 | {"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8272 | {"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8273 | {"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8274 | {"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8275 | {"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8276 | {"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
8277 | {"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8278 | {"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
8279 | {"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8280 | {"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
8281 | {"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8282 | {"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8283 | {"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8284 | {"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8285 | {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8286 | {"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8287 | {"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8288 | {"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8289 | {"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8290 | {"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8291 | {"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8292 | {"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8293 | {"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8294 | {"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8295 | {"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8296 | {"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
8297 | {"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8298 | {"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, | |
8299 | {"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8300 | {"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, | |
8301 | {"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8302 | {"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
8303 | {"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8304 | {"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
8305 | {"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8306 | {"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
8307 | {"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8308 | {"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
8309 | {"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8310 | {"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
8311 | {"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8312 | {"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, | |
8313 | {"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8314 | {"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, | |
8315 | {"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8316 | {"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
8317 | {"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8318 | {"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
8319 | {"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8320 | {"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
8321 | {"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8322 | {"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, | |
8323 | {"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8324 | {"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, | |
8325 | {"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8326 | {"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, | |
8327 | {"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8328 | {"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, | |
8329 | {"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8330 | {"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
8331 | {"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8332 | {"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
8333 | {"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8334 | {"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
8335 | {"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8336 | {"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8337 | {"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8338 | {"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8339 | {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8340 | {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8341 | {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8342 | {"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8343 | {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8344 | {"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8345 | {"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8346 | {"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8347 | {"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8348 | {"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8349 | {"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8350 | {"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
8351 | {"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8352 | {"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, | |
8353 | {"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8354 | {"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, | |
8355 | {"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8356 | {"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
8357 | {"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8358 | {"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
8359 | {"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8360 | {"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}}, | |
8361 | {"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8362 | {"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, | |
8363 | {"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8364 | {"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, | |
8365 | {"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8366 | {"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, | |
8367 | {"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
8368 | {"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, | |
8369 | {"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8370 | {"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
8371 | {"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8372 | {"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
8373 | {"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8374 | {"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
8375 | {"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8376 | {"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, | |
8377 | {"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8378 | {"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, | |
8379 | {"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8380 | {"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, | |
8381 | {"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
8382 | {"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, | |
8383 | ||
14b57c7c | 8384 | {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
dfdaec14 | 8385 | {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
14b57c7c | 8386 | {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
dfdaec14 | 8387 | {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
14b57c7c AM |
8388 | {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
8389 | {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
8390 | {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
8391 | {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
8392 | {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
8393 | {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
8394 | {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
8395 | {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
8396 | {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
8397 | {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
8398 | {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
8399 | {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
8400 | {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}}, | |
8401 | {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
8402 | {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
8403 | {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
8404 | {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
8405 | {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8406 | {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8407 | {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8408 | {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8409 | {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8410 | {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8411 | {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8412 | {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
8413 | {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
d2e6c9a3 | 8414 | {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
8415 | {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
8416 | {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 8417 | {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
8418 | {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
8419 | {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 8420 | {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
8421 | {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
8422 | {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 8423 | {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
8424 | {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
8425 | {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 8426 | {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
8427 | {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
8428 | {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 AF |
8429 | {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
8430 | {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
14b57c7c AM |
8431 | {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, |
8432 | {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8433 | {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, | |
8434 | ||
8435 | {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
8436 | {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
8437 | {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
8438 | {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
8439 | {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8440 | {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8441 | {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8442 | ||
8443 | {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8444 | {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8445 | {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8446 | ||
8447 | {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8448 | {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8449 | {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8450 | {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, | |
8451 | {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8452 | {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8453 | {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8454 | {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8455 | {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, | |
8456 | ||
8457 | {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8458 | {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8459 | {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8460 | {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
8461 | ||
8462 | {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8463 | {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8464 | {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8465 | {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8466 | {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8467 | {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8468 | {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
8469 | ||
8470 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
8471 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
8472 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
8473 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
8474 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
8475 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, | |
8476 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
8477 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, | |
14b57c7c AM |
8478 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
8479 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
14b57c7c AM |
8480 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, |
8481 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
8482 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, | |
8483 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
8484 | {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, | |
8485 | {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, | |
8486 | {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, | |
8487 | {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, | |
8488 | {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, | |
8489 | {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, | |
8490 | {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, | |
8491 | {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, | |
8492 | {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, | |
8493 | {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8494 | {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8495 | {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8496 | {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8497 | {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8498 | {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8499 | {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8500 | {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8501 | {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8502 | {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8503 | {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8504 | {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8505 | {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8506 | {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8507 | {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8508 | {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8509 | {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8510 | {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8511 | {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8512 | {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8513 | {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8514 | {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8515 | {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8516 | {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
8517 | {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, | |
8518 | {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, | |
8519 | ||
8520 | {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
8521 | {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
8522 | {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
8523 | {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
8524 | ||
8525 | {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, | |
a8cc8a54 | 8526 | {"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}}, |
14b57c7c AM |
8527 | {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, |
8528 | {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
8529 | {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
98553ad3 | 8530 | {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BAB}}, |
14b57c7c | 8531 | {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
98553ad3 | 8532 | {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BTAB}}, |
14b57c7c AM |
8533 | {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
8534 | {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, | |
8535 | {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
8536 | {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
8537 | ||
8538 | {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
8539 | ||
8540 | {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, | |
8541 | {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, | |
8542 | ||
98553ad3 | 8543 | {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BTAB}}, |
14b57c7c AM |
8544 | {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
8545 | ||
8546 | {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
8547 | {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
8548 | ||
8549 | {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
8550 | ||
98553ad3 | 8551 | {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BAB}}, |
14b57c7c AM |
8552 | {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
8553 | ||
8554 | {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, | |
8555 | ||
8556 | {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
8557 | {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
8558 | ||
8559 | {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, | |
8560 | ||
8561 | {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, | |
8562 | ||
8563 | {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, | |
8564 | ||
8565 | {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, | |
8566 | ||
8567 | {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, | |
8568 | ||
8569 | {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, | |
8570 | ||
8571 | {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8572 | {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8573 | {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8574 | {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8575 | {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8576 | {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8577 | {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8578 | {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, | |
8579 | {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8580 | {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8581 | {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8582 | {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8583 | {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
8584 | {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, | |
8585 | {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, | |
8586 | {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, | |
8587 | {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, | |
b9c361e0 JL |
8588 | }; |
8589 | ||
2ceb7719 | 8590 | const unsigned int vle_num_opcodes = |
b9c361e0 JL |
8591 | sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); |
8592 | \f | |
252b5132 RH |
8593 | /* The macro table. This is only used by the assembler. */ |
8594 | ||
8595 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 | |
8596 | when x=0; 32-x when x is between 1 and 31; are negative if x is | |
8597 | negative; and are 32 or more otherwise. This is what you want | |
8598 | when, for instance, you are emulating a right shift by a | |
8599 | rotate-left-and-mask, because the underlying instructions support | |
8600 | shifts of size 0 but not shifts of size 32. By comparison, when | |
8601 | extracting x bits from some word you want to use just 32-x, because | |
8602 | the underlying instructions don't support extracting 0 bits but do | |
8603 | support extracting the whole word (32 bits in this case). */ | |
8604 | ||
8605 | const struct powerpc_macro powerpc_macros[] = { | |
de866fcc AM |
8606 | {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, |
8607 | {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, | |
bdc7fcfe AM |
8608 | {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, |
8609 | {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, | |
de866fcc AM |
8610 | {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, |
8611 | {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, | |
8612 | {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
8613 | {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
8614 | {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, | |
8615 | {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, | |
8616 | {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
8617 | {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
8618 | {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, | |
8619 | {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, | |
8620 | {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, | |
14b57c7c | 8621 | {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, |
de866fcc AM |
8622 | |
8623 | {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, | |
8624 | {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, | |
8625 | {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
8626 | {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
8627 | {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
8628 | {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
8629 | {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
8630 | {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
8631 | {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
8632 | {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
8633 | {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, | |
8634 | {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, | |
8635 | {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, | |
8636 | {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, | |
8637 | {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
8638 | {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
8639 | {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
8640 | {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
8641 | {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, | |
8642 | {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, | |
8643 | {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
8644 | {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
a4ebc835 AM |
8645 | |
8646 | {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, | |
8647 | {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
8648 | {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
8649 | {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
8650 | {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, | |
8651 | {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
8652 | {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, | |
8653 | {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
8654 | {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, | |
8655 | {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, | |
8656 | {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
74081948 AF |
8657 | |
8658 | /* old SPE instructions have new names with the same opcodes */ | |
8659 | {"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"}, | |
8660 | {"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"}, | |
8661 | {"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"}, | |
8662 | {"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"}, | |
8663 | {"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"}, | |
8664 | {"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"}, | |
8665 | {"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"}, | |
8666 | {"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"}, | |
8667 | {"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"}, | |
8668 | {"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"}, | |
8669 | {"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"}, | |
8670 | {"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"}, | |
8671 | {"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"}, | |
8672 | {"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"}, | |
8673 | {"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"}, | |
8674 | {"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"}, | |
8675 | {"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"}, | |
8676 | {"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"}, | |
8677 | {"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"}, | |
8678 | {"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"}, | |
8679 | {"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"}, | |
8680 | {"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"}, | |
8681 | {"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"}, | |
8682 | ||
8683 | /* SPE2 instructions which just are mapped to SPE2 */ | |
8684 | {"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"}, | |
8685 | {"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"}, | |
8686 | {"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"}, | |
8687 | {"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"} | |
252b5132 RH |
8688 | }; |
8689 | ||
8690 | const int powerpc_num_macros = | |
8691 | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); | |
74081948 AF |
8692 | |
8693 | /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */ | |
8694 | const struct powerpc_opcode spe2_opcodes[] = { | |
8695 | {"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8696 | {"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8697 | {"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8698 | {"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8699 | {"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8700 | {"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8701 | {"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8702 | {"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8703 | {"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8704 | {"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8705 | {"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8706 | {"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8707 | {"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8708 | {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8709 | {"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8710 | {"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8711 | {"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8712 | {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8713 | {"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8714 | {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8715 | {"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8716 | {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8717 | {"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8718 | {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8719 | {"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8720 | {"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8721 | {"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8722 | {"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8723 | {"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8724 | {"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8725 | {"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8726 | {"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8727 | {"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8728 | {"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8729 | {"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8730 | {"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8731 | {"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8732 | {"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8733 | {"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8734 | {"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8735 | {"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8736 | {"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8737 | {"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8738 | {"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8739 | {"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8740 | {"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8741 | {"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8742 | {"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8743 | {"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8744 | {"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8745 | {"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8746 | {"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8747 | {"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8748 | {"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8749 | {"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8750 | {"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8751 | {"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8752 | {"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8753 | {"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8754 | {"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8755 | {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8756 | {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8757 | {"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8758 | {"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8759 | {"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8760 | {"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8761 | {"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8762 | {"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8763 | {"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8764 | {"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8765 | {"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8766 | {"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8767 | {"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8768 | {"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8769 | {"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8770 | {"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8771 | {"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8772 | {"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8773 | {"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8774 | {"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8775 | {"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8776 | {"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8777 | {"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8778 | {"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8779 | {"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8780 | {"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8781 | {"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8782 | {"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8783 | {"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8784 | {"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8785 | {"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8786 | {"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8787 | {"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8788 | {"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8789 | {"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8790 | {"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8791 | {"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8792 | {"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8793 | {"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8794 | {"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8795 | {"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8796 | {"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8797 | {"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8798 | {"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8799 | {"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8800 | {"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8801 | {"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8802 | {"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8803 | {"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8804 | {"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8805 | {"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8806 | {"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8807 | {"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8808 | {"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8809 | {"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8810 | {"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8811 | {"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8812 | {"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8813 | {"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8814 | {"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8815 | {"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8816 | {"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8817 | {"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8818 | {"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8819 | {"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8820 | {"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8821 | {"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8822 | {"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8823 | {"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8824 | {"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8825 | {"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8826 | {"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8827 | {"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8828 | {"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8829 | {"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8830 | {"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8831 | {"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8832 | {"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8833 | {"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8834 | {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8835 | {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8836 | {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8837 | {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8838 | {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8839 | {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8840 | {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8841 | {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8842 | {"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8843 | {"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8844 | {"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8845 | {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8846 | {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8847 | {"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8848 | {"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8849 | {"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8850 | {"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8851 | {"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8852 | {"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8853 | {"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8854 | {"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8855 | {"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8856 | {"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8857 | {"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8858 | {"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8859 | {"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8860 | {"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8861 | {"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8862 | {"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8863 | {"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8864 | {"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8865 | {"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8866 | {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8867 | {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8868 | {"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8869 | {"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8870 | {"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8871 | {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8872 | {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8873 | {"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8874 | {"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8875 | {"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8876 | {"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8877 | {"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8878 | {"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8879 | {"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8880 | {"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8881 | {"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8882 | {"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8883 | {"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8884 | {"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8885 | {"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8886 | {"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8887 | {"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8888 | {"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8889 | {"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8890 | {"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8891 | {"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8892 | {"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8893 | {"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8894 | {"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8895 | {"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8896 | {"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8897 | {"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8898 | {"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8899 | {"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8900 | {"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8901 | {"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8902 | {"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8903 | {"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, | |
8904 | {"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, | |
8905 | {"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, | |
8906 | {"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, | |
8907 | {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8908 | {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8909 | {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8910 | {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8911 | {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8912 | {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8913 | {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8914 | {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8915 | {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8916 | {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8917 | {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8918 | {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8919 | {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8920 | {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8921 | {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8922 | {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8923 | {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8924 | {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8925 | {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8926 | {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8927 | {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8928 | {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8929 | {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8930 | {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8931 | {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8932 | {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8933 | {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8934 | {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8935 | {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8936 | {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8937 | {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8938 | {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8939 | {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8940 | {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8941 | {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8942 | {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8943 | {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8944 | {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8945 | {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8946 | {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8947 | {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8948 | {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8949 | {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8950 | {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8951 | {"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8952 | {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8953 | {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8954 | {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8955 | {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8956 | {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8957 | {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8958 | {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8959 | {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8960 | {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8961 | {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8962 | {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8963 | {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8964 | {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8965 | {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8966 | {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8967 | {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8968 | {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8969 | {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8970 | {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8971 | {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8972 | {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8973 | {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8974 | {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8975 | {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8976 | {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8977 | {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8978 | {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8979 | {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8980 | {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8981 | {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8982 | {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8983 | {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8984 | {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8985 | {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8986 | {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8987 | {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8988 | {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8989 | {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8990 | {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8991 | {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
8992 | {"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8993 | {"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
8994 | {"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
8995 | {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
8996 | {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
8997 | {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
8998 | {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
8999 | {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9000 | {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9001 | {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9002 | {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9003 | {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9004 | {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9005 | {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9006 | {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9007 | {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9008 | {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9009 | {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9010 | {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9011 | {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9012 | {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9013 | {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9014 | {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9015 | {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9016 | {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9017 | {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9018 | {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9019 | {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9020 | {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9021 | {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9022 | {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9023 | {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9024 | {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9025 | {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9026 | {"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9027 | {"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9028 | {"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9029 | {"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9030 | {"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9031 | {"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9032 | {"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9033 | {"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9034 | {"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, | |
9035 | {"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, | |
9036 | {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}}, | |
9037 | {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}}, | |
9038 | {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, | |
9039 | {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
9040 | {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
9041 | {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
9042 | {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, | |
9043 | {"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9044 | {"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9045 | {"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9046 | {"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9047 | {"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9048 | {"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9049 | {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}}, | |
9050 | {"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9051 | {"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9052 | {"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9053 | {"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9054 | {"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9055 | {"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9056 | {"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9057 | {"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9058 | {"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9059 | {"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9060 | {"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9061 | {"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9062 | {"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9063 | {"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9064 | {"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9065 | {"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9066 | {"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9067 | {"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9068 | {"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
9069 | {"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
9070 | {"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9071 | {"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9072 | {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
9073 | {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
9074 | {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
9075 | {"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9076 | {"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}}, | |
9077 | {"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9078 | {"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}}, | |
9079 | {"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9080 | {"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9081 | {"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9082 | {"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9083 | {"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9084 | {"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}}, | |
9085 | {"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9086 | {"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}}, | |
9087 | {"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9088 | {"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9089 | {"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9090 | {"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9091 | {"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9092 | {"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9093 | {"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9094 | {"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
9095 | {"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9096 | {"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
9097 | {"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9098 | {"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
9099 | {"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9100 | {"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}}, | |
9101 | {"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9102 | {"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9103 | {"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9104 | {"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9105 | {"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9106 | {"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9107 | {"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9108 | {"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9109 | {"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9110 | {"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9111 | {"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9112 | {"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9113 | {"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9114 | {"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9115 | {"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9116 | {"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9117 | {"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9118 | {"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9119 | {"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9120 | {"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9121 | {"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9122 | {"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9123 | {"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9124 | {"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9125 | {"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9126 | {"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9127 | {"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9128 | {"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9129 | {"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9130 | {"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9131 | {"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9132 | {"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}}, | |
9133 | {"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9134 | {"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
9135 | {"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9136 | {"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
9137 | {"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9138 | {"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
9139 | {"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9140 | {"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
9141 | {"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9142 | {"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9143 | {"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9144 | {"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9145 | {"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9146 | {"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9147 | {"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9148 | {"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9149 | {"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9150 | {"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9151 | {"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9152 | {"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9153 | {"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9154 | {"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9155 | {"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9156 | {"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9157 | {"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9158 | {"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9159 | {"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9160 | {"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9161 | {"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9162 | {"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}}, | |
9163 | {"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9164 | {"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9165 | {"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9166 | {"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9167 | {"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9168 | {"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9169 | {"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9170 | {"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9171 | {"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9172 | {"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9173 | {"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9174 | {"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9175 | {"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9176 | {"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9177 | {"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9178 | {"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9179 | {"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9180 | {"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9181 | {"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9182 | {"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9183 | {"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9184 | {"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9185 | {"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9186 | {"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9187 | {"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9188 | {"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9189 | {"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9190 | {"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9191 | {"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9192 | {"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9193 | {"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9194 | {"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9195 | {"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9196 | {"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9197 | {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9198 | {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9199 | {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9200 | {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9201 | {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9202 | {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9203 | {"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9204 | {"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9205 | {"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9206 | {"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9207 | {"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9208 | {"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9209 | {"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9210 | {"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9211 | {"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9212 | {"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9213 | {"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9214 | {"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9215 | {"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9216 | {"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9217 | {"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9218 | {"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9219 | {"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9220 | {"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9221 | {"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9222 | {"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9223 | {"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9224 | {"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9225 | {"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9226 | {"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9227 | {"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9228 | {"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9229 | {"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9230 | {"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9231 | {"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9232 | {"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9233 | {"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9234 | {"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9235 | {"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9236 | {"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9237 | {"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9238 | {"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9239 | {"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9240 | {"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9241 | {"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9242 | {"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9243 | {"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9244 | {"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9245 | {"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9246 | {"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9247 | {"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9248 | {"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9249 | {"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9250 | {"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9251 | {"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9252 | {"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9253 | {"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9254 | {"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9255 | {"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9256 | {"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9257 | {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}}, | |
9258 | {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9259 | {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9260 | {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9261 | {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9262 | {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9263 | {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9264 | {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9265 | {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9266 | {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9267 | {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9268 | {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9269 | {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9270 | {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9271 | {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9272 | {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9273 | {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9274 | {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9275 | {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9276 | {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9277 | {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9278 | {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9279 | {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9280 | {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9281 | {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9282 | {"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9283 | {"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9284 | {"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9285 | {"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9286 | {"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9287 | {"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9288 | {"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9289 | {"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9290 | {"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9291 | {"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9292 | {"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9293 | {"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9294 | {"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9295 | {"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9296 | {"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9297 | {"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9298 | {"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9299 | {"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9300 | {"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9301 | {"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9302 | {"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9303 | {"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9304 | {"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9305 | {"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9306 | {"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9307 | {"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9308 | {"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9309 | {"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9310 | {"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9311 | {"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9312 | {"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9313 | {"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9314 | {"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9315 | {"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9316 | {"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9317 | {"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9318 | {"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9319 | {"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9320 | {"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9321 | {"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9322 | {"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9323 | {"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9324 | {"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9325 | {"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9326 | {"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9327 | {"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9328 | {"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9329 | {"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9330 | {"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9331 | {"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9332 | {"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9333 | {"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9334 | {"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9335 | {"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9336 | {"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9337 | {"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9338 | {"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9339 | {"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9340 | {"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9341 | {"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9342 | {"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9343 | {"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9344 | {"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9345 | {"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9346 | {"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9347 | {"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9348 | {"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9349 | {"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9350 | {"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9351 | {"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9352 | {"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9353 | {"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9354 | {"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9355 | {"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9356 | {"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9357 | {"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9358 | {"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9359 | {"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9360 | {"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9361 | {"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9362 | {"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9363 | {"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9364 | {"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9365 | {"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9366 | {"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9367 | {"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9368 | {"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9369 | {"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9370 | {"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9371 | {"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9372 | {"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9373 | {"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9374 | {"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9375 | {"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9376 | {"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9377 | {"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9378 | {"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9379 | {"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9380 | {"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9381 | {"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9382 | {"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9383 | {"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9384 | {"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9385 | {"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9386 | {"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9387 | {"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9388 | {"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9389 | {"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9390 | {"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9391 | {"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9392 | {"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9393 | {"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9394 | {"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9395 | {"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9396 | {"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9397 | {"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9398 | {"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9399 | {"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9400 | {"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9401 | {"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9402 | {"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9403 | {"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9404 | {"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9405 | {"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9406 | {"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9407 | {"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9408 | {"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9409 | {"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9410 | {"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9411 | {"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9412 | {"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9413 | {"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9414 | {"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9415 | {"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9416 | {"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9417 | {"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9418 | {"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9419 | {"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9420 | {"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9421 | {"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9422 | {"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9423 | {"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9424 | {"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9425 | {"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9426 | {"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9427 | {"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9428 | {"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9429 | {"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9430 | {"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9431 | {"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9432 | {"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9433 | {"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9434 | {"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9435 | {"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9436 | {"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9437 | {"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9438 | {"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9439 | {"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9440 | {"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9441 | {"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9442 | {"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9443 | {"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9444 | {"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9445 | {"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9446 | {"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9447 | {"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9448 | {"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9449 | {"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9450 | {"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9451 | {"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9452 | {"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9453 | {"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9454 | {"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9455 | {"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9456 | {"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9457 | {"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9458 | {"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9459 | {"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9460 | {"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9461 | {"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9462 | {"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9463 | {"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9464 | {"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9465 | {"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9466 | {"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9467 | {"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9468 | {"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9469 | {"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9470 | {"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9471 | {"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9472 | {"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9473 | {"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9474 | {"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9475 | {"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9476 | {"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9477 | {"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9478 | {"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9479 | }; | |
9480 | ||
2ceb7719 | 9481 | const unsigned int spe2_num_opcodes = |
74081948 | 9482 | sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]); |