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include/opcode/
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
aea77599 3 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
6b069ee7 4 Free Software Foundation, Inc.
252b5132
RH		 5 Written by Ian Lance Taylor, Cygnus Support
6
9b201bb5 7 This file is part of the GNU opcodes library.
252b5132 8
9b201bb5
NC		 9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
252b5132 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
252b5132 18
112290ab 19 You should have received a copy of the GNU General Public License
9b201bb5
NC		 20 along with this file; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132
RH		 23
24#include <stdio.h>
0d8dfecf 25#include "sysdep.h"
252b5132
RH		 26#include "opcode/ppc.h"
27#include "opintl.h"
28
29/* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
34 the .text section.
35
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
38 file. */
39\f
40/* Local insertion and extraction functions. */
41
fa452fa6
PB		 42static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
43static long extract_bat (unsigned long, ppc_cpu_t, int *);
44static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_bba (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_bdm (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bdp (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bo (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_boe (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_fxm (unsigned long, ppc_cpu_t, int *);
aea77599 56static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 57static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
58static long extract_mbe (unsigned long, ppc_cpu_t, int *);
59static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
60static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
61static long extract_nb (unsigned long, ppc_cpu_t, int *);
989993d8 62static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 63static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
64static long extract_nsi (unsigned long, ppc_cpu_t, int *);
65static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
66static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
67static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
68static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
69static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
70static long extract_rbs (unsigned long, ppc_cpu_t, int *);
989993d8 71static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 72static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
74static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_spr (unsigned long, ppc_cpu_t, int *);
76static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
77static long extract_sprg (unsigned long, ppc_cpu_t, int *);
78static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
79static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 80static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
81static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
82static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
83static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
84static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
85static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
86static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
87static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
066be9f7
PB		 88static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
89static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
90static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
91static long extract_dm (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 92\f
93/* The operands table.
94
717bbdf1 95 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 96
97 We used to put parens around the various additions, like the one
98 for BA just below. However, that caused trouble with feeble
99 compilers with a limit on depth of a parenthesized expression, like
100 (reportedly) the compiler in Microsoft Developer Studio 5. So we
101 omit the parens, since the macros are never used in a context where
102 the addition will be ambiguous. */
103
104const struct powerpc_operand powerpc_operands[] =
105{
106 /* The zero index is used to indicate the end of the list of
107 operands. */
108#define UNUSED 0
bbac1f2a 109 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 110
111 /* The BA field in an XL form instruction. */
112#define BA UNUSED + 1
717bbdf1
AM		 113 /* The BI field in a B form or XL form instruction. */
114#define BI BA
115#define BI_MASK (0x1f << 16)
b84bf58a 116 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 117
118 /* The BA field in an XL form instruction when it must be the same
119 as the BT field in the same instruction. */
120#define BAT BA + 1
b84bf58a 121 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 122
123 /* The BB field in an XL form instruction. */
124#define BB BAT + 1
125#define BB_MASK (0x1f << 11)
b84bf58a 126 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 127
128 /* The BB field in an XL form instruction when it must be the same
129 as the BA field in the same instruction. */
130#define BBA BB + 1
b84bf58a 131 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 132
133 /* The BD field in a B form instruction. The lower two bits are
134 forced to zero. */
135#define BD BBA + 1
b84bf58a 136 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 137
138 /* The BD field in a B form instruction when absolute addressing is
139 used. */
140#define BDA BD + 1
b84bf58a 141 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 142
143 /* The BD field in a B form instruction when the - modifier is used.
144 This sets the y bit of the BO field appropriately. */
145#define BDM BDA + 1
b84bf58a 146 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 147 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 148
149 /* The BD field in a B form instruction when the - modifier is used
150 and absolute address is used. */
151#define BDMA BDM + 1
b84bf58a 152 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 153 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 154
155 /* The BD field in a B form instruction when the + modifier is used.
156 This sets the y bit of the BO field appropriately. */
157#define BDP BDMA + 1
b84bf58a 158 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 159 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 160
161 /* The BD field in a B form instruction when the + modifier is used
162 and absolute addressing is used. */
163#define BDPA BDP + 1
b84bf58a 164 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 165 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 166
167 /* The BF field in an X or XL form instruction. */
168#define BF BDPA + 1
717bbdf1
AM		 169 /* The CRFD field in an X form instruction. */
170#define CRFD BF
b84bf58a 171 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132 172
ea192fa3
PB		 173 /* The BF field in an X or XL form instruction. */
174#define BFF BF + 1
175 { 0x7, 23, NULL, NULL, 0 },
176
252b5132
RH		 177 /* An optional BF field. This is used for comparison instructions,
178 in which an omitted BF field is taken as zero. */
ea192fa3 179#define OBF BFF + 1
b84bf58a 180 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 181
182 /* The BFA field in an X or XL form instruction. */
183#define BFA OBF + 1
b84bf58a 184 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132 185
252b5132
RH		 186 /* The BO field in a B form instruction. Certain values are
187 illegal. */
717bbdf1 188#define BO BFA + 1
252b5132 189#define BO_MASK (0x1f << 21)
b84bf58a 190 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 191
192 /* The BO field in a B form instruction when the + or - modifier is
193 used. This is like the BO field, but it must be even. */
194#define BOE BO + 1
b84bf58a 195 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 196
d0618d1c 197#define BH BOE + 1
b84bf58a 198 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 199
252b5132 200 /* The BT field in an X or XL form instruction. */
d0618d1c 201#define BT BH + 1
b84bf58a 202 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 203
204 /* The condition register number portion of the BI field in a B form
205 or XL form instruction. This is used for the extended
206 conditional branch mnemonics, which set the lower two bits of the
207 BI field. This field is optional. */
208#define CR BT + 1
b84bf58a 209 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 210
23976049
EZ		 211 /* The CRB field in an X form instruction. */
212#define CRB CR + 1
717bbdf1
AM		 213 /* The MB field in an M form instruction. */
214#define MB CRB
215#define MB_MASK (0x1f << 6)
b84bf58a 216 { 0x1f, 6, NULL, NULL, 0 },
23976049 217
23976049 218 /* The CRFS field in an X form instruction. */
717bbdf1 219#define CRFS CRB + 1
b84bf58a 220 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 221
418c1742 222 /* The CT field in an X form instruction. */
23976049 223#define CT CRFS + 1
717bbdf1
AM		 224 /* The MO field in an mbar instruction. */
225#define MO CT
b84bf58a 226 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 227
252b5132
RH		 228 /* The D field in a D form instruction. This is a displacement off
229 a register, and implies that the next operand is a register in
230 parentheses. */
418c1742 231#define D CT + 1
b84bf58a 232 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 233
adadcc0c
AM		 234 /* The DQ field in a DQ form instruction. This is like D, but the
235 lower four bits are forced to zero. */
2f3bb96a 236#define DQ D + 1
b84bf58a
AM		 237 { 0xfff0, 0, NULL, NULL,
238 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 239
252b5132
RH		 240 /* The DS field in a DS form instruction. This is like D, but the
241 lower two bits are forced to zero. */
adadcc0c 242#define DS DQ + 1
b84bf58a
AM		 243 { 0xfffc, 0, NULL, NULL,
244 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 245
19a6653c
AM		 246 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
247#define DUIS DS + 1
248 { 0x3ff, 11, NULL, NULL, 0 },
249
252b5132 250 /* The E field in a wrteei instruction. */
c3d65c1c 251 /* And the W bit in the pair singles instructions. */
19a6653c 252#define E DUIS + 1
c3d65c1c 253#define PSW E
b84bf58a 254 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 255
256 /* The FL1 field in a POWER SC form instruction. */
257#define FL1 E + 1
717bbdf1
AM		 258 /* The U field in an X form instruction. */
259#define U FL1
b84bf58a 260 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 261
262 /* The FL2 field in a POWER SC form instruction. */
263#define FL2 FL1 + 1
b84bf58a 264 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 265
266 /* The FLM field in an XFL form instruction. */
267#define FLM FL2 + 1
b84bf58a 268 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 269
270 /* The FRA field in an X or A form instruction. */
271#define FRA FLM + 1
272#define FRA_MASK (0x1f << 16)
b84bf58a 273 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132 274
989993d8
JB		 275 /* The FRAp field of DFP instructions. */
276#define FRAp FRA + 1
277 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
278
252b5132 279 /* The FRB field in an X or A form instruction. */
989993d8 280#define FRB FRAp + 1
252b5132 281#define FRB_MASK (0x1f << 11)
b84bf58a 282 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132 283
989993d8
JB		 284 /* The FRBp field of DFP instructions. */
285#define FRBp FRB + 1
286 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
287
252b5132 288 /* The FRC field in an A form instruction. */
989993d8 289#define FRC FRBp + 1
252b5132 290#define FRC_MASK (0x1f << 6)
b84bf58a 291 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 292
293 /* The FRS field in an X form instruction or the FRT field in a D, X
294 or A form instruction. */
295#define FRS FRC + 1
296#define FRT FRS
b84bf58a 297 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132 298
989993d8
JB		 299 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
300 instructions. */
301#define FRSp FRS + 1
302#define FRTp FRSp
303 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
304
252b5132 305 /* The FXM field in an XFX instruction. */
989993d8 306#define FXM FRSp + 1
b84bf58a 307 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 308
309 /* Power4 version for mfcr. */
310#define FXM4 FXM + 1
b84bf58a 311 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 312
313 /* The L field in a D or X form instruction. */
c168870a 314#define L FXM4 + 1
b84bf58a 315 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 316
1ed8e1e4
AM		 317 /* The LEV field in a POWER SVC form instruction. */
318#define SVC_LEV L + 1
b84bf58a 319 { 0x7f, 5, NULL, NULL, 0 },
252b5132 320
1ed8e1e4
AM		 321 /* The LEV field in an SC form instruction. */
322#define LEV SVC_LEV + 1
b84bf58a 323 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 324
252b5132
RH		 325 /* The LI field in an I form instruction. The lower two bits are
326 forced to zero. */
327#define LI LEV + 1
b84bf58a 328 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 329
330 /* The LI field in an I form instruction when used as an absolute
331 address. */
332#define LIA LI + 1
b84bf58a 333 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 334
066be9f7 335 /* The LS or WC field in an X (sync or wait) form instruction. */
6ba045b1 336#define LS LIA + 1
066be9f7 337#define WC LS
b84bf58a 338 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 339
252b5132 340 /* The ME field in an M form instruction. */
717bbdf1 341#define ME LS + 1
252b5132 342#define ME_MASK (0x1f << 1)
b84bf58a 343 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 344
345 /* The MB and ME fields in an M form instruction expressed a single
346 operand which is a bitmask indicating which bits to select. This
347 is a two operand form using PPC_OPERAND_NEXT. See the
348 description in opcode/ppc.h for what this means. */
349#define MBE ME + 1
b84bf58a 350 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 351 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 352
353 /* The MB or ME field in an MD or MDS form instruction. The high
354 bit is wrapped to the low end. */
355#define MB6 MBE + 2
356#define ME6 MB6
357#define MB6_MASK (0x3f << 5)
b84bf58a 358 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 359
360 /* The NB field in an X form instruction. The value 32 is stored as
361 0. */
717bbdf1 362#define NB MB6 + 1
b84bf58a 363 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132 364
989993d8
JB		 365 /* The NBI field in an lswi instruction, which has special value
366 restrictions. The value 32 is stored as 0. */
367#define NBI NB + 1
368 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
369
252b5132
RH		 370 /* The NSI field in a D form instruction. This is the same as the
371 SI field, only negated. */
989993d8 372#define NSI NBI + 1
b84bf58a 373 { 0xffff, 0, insert_nsi, extract_nsi,
11b37b7b 374 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 375
adadcc0c 376 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 377#define RA NSI + 1
252b5132 378#define RA_MASK (0x1f << 16)
b84bf58a 379 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 380
fdd12ef3
AM		 381 /* As above, but 0 in the RA field means zero, not r0. */
382#define RA0 RA + 1
b84bf58a 383 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3 384
989993d8 385 /* The RA field in the DQ form lq or an lswx instruction, which have special
adadcc0c 386 value restrictions. */
fdd12ef3 387#define RAQ RA0 + 1
989993d8 388#define RAX RAQ
b84bf58a 389 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 390
252b5132
RH		 391 /* The RA field in a D or X form instruction which is an updating
392 load, which means that the RA field may not be zero and may not
393 equal the RT field. */
adadcc0c 394#define RAL RAQ + 1
b84bf58a 395 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 396
397 /* The RA field in an lmw instruction, which has special value
398 restrictions. */
399#define RAM RAL + 1
b84bf58a 400 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 401
402 /* The RA field in a D or X form instruction which is an updating
403 store or an updating floating point load, which means that the RA
404 field may not be zero. */
405#define RAS RAM + 1
b84bf58a 406 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 407
cee62821
PB		 408 /* The RA field of the tlbwe, dccci and iccci instructions,
409 which are optional. */
fdd12ef3 410#define RAOPT RAS + 1
b84bf58a 411 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 412
252b5132 413 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 414#define RB RAOPT + 1
252b5132 415#define RB_MASK (0x1f << 11)
b84bf58a 416 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 417
418 /* The RB field in an X form instruction when it must be the same as
419 the RS field in the instruction. This is used for extended
420 mnemonics like mr. */
421#define RBS RB + 1
b84bf58a 422 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132 423
989993d8
JB		 424 /* The RB field in an lswx instruction, which has special value
425 restrictions. */
426#define RBX RBS + 1
427 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
428
cee62821 429 /* The RB field of the dccci and iccci instructions, which are optional. */
989993d8 430#define RBOPT RBX + 1
cee62821
PB		 431 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
432
252b5132
RH		 433 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
434 instruction or the RT field in a D, DS, X, XFX or XO form
435 instruction. */
cee62821 436#define RS RBOPT + 1
252b5132
RH		 437#define RT RS
438#define RT_MASK (0x1f << 21)
b84bf58a 439 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 440
717bbdf1
AM		 441 /* The RS and RT fields of the DS form stq instruction, which have
442 special value restrictions. */
adadcc0c 443#define RSQ RS + 1
717bbdf1 444#define RTQ RSQ
b84bf58a 445 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 446
1f6c9eb0 447 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 448#define RSO RSQ + 1
eed0d89a 449#define RTO RSO
b84bf58a 450 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 451
252b5132 452 /* The SH field in an X or M form instruction. */
1f6c9eb0 453#define SH RSO + 1
252b5132 454#define SH_MASK (0x1f << 11)
717bbdf1
AM		 455 /* The other UIMM field in a EVX form instruction. */
456#define EVUIMM SH
b84bf58a 457 { 0x1f, 11, NULL, NULL, 0 },
252b5132
RH		 458
459 /* The SH field in an MD form instruction. This is split. */
460#define SH6 SH + 1
461#define SH6_MASK ((0x1f << 11) | (1 << 1))
b84bf58a 462 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
252b5132 463
1f6c9eb0
ZW		 464 /* The SH field of the tlbwe instruction, which is optional. */
465#define SHO SH6 + 1
b84bf58a 466 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 467
252b5132 468 /* The SI field in a D form instruction. */
1f6c9eb0 469#define SI SHO + 1
b84bf58a 470 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 471
472 /* The SI field in a D form instruction when we accept a wide range
473 of positive values. */
474#define SISIGNOPT SI + 1
b84bf58a 475 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 476
477 /* The SPR field in an XFX form instruction. This is flipped--the
478 lower 5 bits are stored in the upper 5 and vice- versa. */
479#define SPR SISIGNOPT + 1
914749f6 480#define PMR SPR
aea77599 481#define TMR SPR
252b5132 482#define SPR_MASK (0x3ff << 11)
b84bf58a 483 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 484
485 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
486#define SPRBAT SPR + 1
487#define SPRBAT_MASK (0x3 << 17)
b84bf58a 488 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 489
490 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
491#define SPRG SPRBAT + 1
b84bf58a 492 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 493
494 /* The SR field in an X form instruction. */
495#define SR SPRG + 1
b84bf58a 496 { 0xf, 16, NULL, NULL, 0 },
252b5132 497
f5c120c5
MG		 498 /* The STRM field in an X AltiVec form instruction. */
499#define STRM SR + 1
19a6653c
AM		 500 /* The T field in a tlbilx form instruction. */
501#define T STRM
b84bf58a 502 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 503
aea77599
AM		 504 /* The ESYNC field in an X (sync) form instruction. */
505#define ESYNC STRM + 1
506 { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
507
252b5132 508 /* The SV field in a POWER SC form instruction. */
aea77599 509#define SV ESYNC + 1
b84bf58a 510 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 511
512 /* The TBR field in an XFX form instruction. This is like the SPR
513 field, but it is optional. */
514#define TBR SV + 1
b84bf58a 515 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 516
517 /* The TO field in a D or X form instruction. */
518#define TO TBR + 1
19a6653c 519#define DUI TO
252b5132 520#define TO_MASK (0x1f << 21)
b84bf58a 521 { 0x1f, 21, NULL, NULL, 0 },
252b5132 522
252b5132 523 /* The UI field in a D form instruction. */
717bbdf1 524#define UI TO + 1
b84bf58a 525 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 526
112290ab 527 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f 528#define VA UI + 1
b84bf58a 529 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 530
112290ab 531 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 532#define VB VA + 1
b84bf58a 533 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 534
112290ab 535 /* The VC field in a VA form instruction. */
786e2c0f 536#define VC VB + 1
b84bf58a 537 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 538
112290ab 539 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 540#define VD VC + 1
541#define VS VD
b84bf58a 542 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 543
8dbcd839 544 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 545#define SIMM VD + 1
8dbcd839 546#define TE SIMM
b84bf58a 547 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 548
8dbcd839 549 /* The UIMM field in a VX form instruction. */
786e2c0f 550#define UIMM SIMM + 1
aea77599 551#define DCTL UIMM
b84bf58a 552 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 553
112290ab 554 /* The SHB field in a VA form instruction. */
786e2c0f 555#define SHB UIMM + 1
b84bf58a 556 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 557
112290ab 558 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 559#define EVUIMM_2 SHB + 1
b84bf58a 560 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 561
112290ab 562 /* The other UIMM field in a word EVX form instruction. */
23976049 563#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 564 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 565
112290ab 566 /* The other UIMM field in a double EVX form instruction. */
23976049 567#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 568 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 569
ff3a6ee3 570 /* The WS field. */
23976049 571#define WS EVUIMM_8 + 1
b84bf58a 572 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 573
c3d65c1c
BE		 574 /* PowerPC paired singles extensions. */
575 /* W bit in the pair singles instructions for x type instructions. */
576#define PSWM WS + 1
577 { 0x1, 10, 0, 0, 0 },
578
579 /* IDX bits for quantization in the pair singles instructions. */
580#define PSQ PSWM + 1
581 { 0x7, 12, 0, 0, 0 },
582
583 /* IDX bits for quantization in the pair singles x-type instructions. */
584#define PSQM PSQ + 1
585 { 0x7, 7, 0, 0, 0 },
586
587 /* Smaller D field for quantization in the pair singles instructions. */
588#define PSD PSQM + 1
589 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
590
591#define A_L PSD + 1
ea192fa3 592#define W A_L
c3d65c1c 593#define MTMSRD_L W
b84bf58a 594 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 595
c3d65c1c 596#define RMC MTMSRD_L + 1
b84bf58a 597 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 598
599#define R RMC + 1
b84bf58a 600 { 0x1, 16, NULL, NULL, 0 },
702f0fb4
PB		 601
602#define SP R + 1
b84bf58a 603 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 604
605#define S SP + 1
b84bf58a 606 { 0x1, 20, NULL, NULL, 0 },
702f0fb4
PB		 607
608 /* SH field starting at bit position 16. */
609#define SH16 S + 1
0bbdef92
AM		 610 /* The DCM and DGM fields in a Z form instruction. */
611#define DCM SH16
612#define DGM DCM
b84bf58a 613 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 614
702f0fb4 615 /* The EH field in larx instruction. */
717bbdf1 616#define EH SH16 + 1
b84bf58a 617 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 618
619 /* The L field in an mtfsf or XFL form instruction. */
620#define XFL_L EH + 1
621 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 622
623 /* Xilinx APU related masks and macros */
624#define FCRT XFL_L + 1
625#define FCRT_MASK (0x1f << 21)
626 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
627
628 /* Xilinx FSL related masks and macros */
629#define FSL FCRT + 1
630#define FSL_MASK (0x1f << 11)
631 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
632
633 /* Xilinx UDI related masks and macros */
634#define URT FSL + 1
635 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
636
637#define URA URT + 1
638 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
639
640#define URB URA + 1
641 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
642
643#define URC URB + 1
644 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
645
9b4e5766
PB		 646 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
647#define XS6 URC + 1
648#define XT6 XS6
649 { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
650
651 /* The XA field in an XX3 form instruction. This is split. */
652#define XA6 XT6 + 1
653 { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
654
066be9f7 655 /* The XB field in an XX2 or XX3 form instruction. This is split. */
9b4e5766
PB		 656#define XB6 XA6 + 1
657 { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
658
659 /* The XB field in an XX3 form instruction when it must be the same as
660 the XA field in the instruction. This is used in extended mnemonics
661 like xvmovdp. This is split. */
662#define XB6S XB6 + 1
663 { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
664
066be9f7
PB		 665 /* The XC field in an XX4 form instruction. This is split. */
666#define XC6 XB6S + 1
667 { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
668
669 /* The DM or SHW field in an XX3 form instruction. */
670#define DM XC6 + 1
671#define SHW DM
9b4e5766 672 { 0x3, 8, NULL, NULL, 0 },
066be9f7
PB		 673
674 /* The DM field in an extended mnemonic XX3 form instruction. */
675#define DMEX DM + 1
676 { 0x3, 8, insert_dm, extract_dm, 0 },
677
678 /* The UIM field in an XX2 form instruction. */
679#define UIM DMEX + 1
680 { 0x3, 16, NULL, NULL, 0 },
e0d602ec
BE		 681
682#define ERAT_T UIM + 1
683 { 0x7, 21, NULL, NULL, 0 },
252b5132
RH		 684};
685
b84bf58a
AM		 686const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
687 / sizeof (powerpc_operands[0]));
688
252b5132
RH		 689/* The functions used to insert and extract complicated operands. */
690
691/* The BA field in an XL form instruction when it must be the same as
692 the BT field in the same instruction. This operand is marked FAKE.
693 The insertion function just copies the BT field into the BA field,
694 and the extraction function just checks that the fields are the
695 same. */
696
252b5132 697static unsigned long
2fbfdc41
AM		 698insert_bat (unsigned long insn,
699 long value ATTRIBUTE_UNUSED,
fa452fa6 700 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 701 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 702{
703 return insn | (((insn >> 21) & 0x1f) << 16);
704}
705
706static long
2fbfdc41 707extract_bat (unsigned long insn,
fa452fa6 708 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 709 int *invalid)
252b5132 710{
8427c424 711 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 712 *invalid = 1;
713 return 0;
714}
715
716/* The BB field in an XL form instruction when it must be the same as
717 the BA field in the same instruction. This operand is marked FAKE.
718 The insertion function just copies the BA field into the BB field,
719 and the extraction function just checks that the fields are the
720 same. */
721
252b5132 722static unsigned long
2fbfdc41
AM		 723insert_bba (unsigned long insn,
724 long value ATTRIBUTE_UNUSED,
fa452fa6 725 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 726 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 727{
728 return insn | (((insn >> 16) & 0x1f) << 11);
729}
730
731static long
2fbfdc41 732extract_bba (unsigned long insn,
fa452fa6 733 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 734 int *invalid)
252b5132 735{
8427c424 736 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 737 *invalid = 1;
738 return 0;
739}
740
252b5132
RH		 741/* The BD field in a B form instruction when the - modifier is used.
742 This modifier means that the branch is not expected to be taken.
94efba12
AM		 743 For chips built to versions of the architecture prior to version 2
744 (ie. not Power4 compatible), we set the y bit of the BO field to 1
745 if the offset is negative. When extracting, we require that the y
746 bit be 1 and that the offset be positive, since if the y bit is 0
747 we just want to print the normal form of the instruction.
748 Power4 compatible targets use two bits, "a", and "t", instead of
749 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
750 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
751 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 752 for branch on CTR. We only handle the taken/not-taken hint here.
753 Note that we don't relax the conditions tested here when
754 disassembling with -Many because insns using extract_bdm and
755 extract_bdp always occur in pairs. One or the other will always
756 be valid. */
252b5132 757
8ebac3aa
AM		 758#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
759
252b5132 760static unsigned long
2fbfdc41
AM		 761insert_bdm (unsigned long insn,
762 long value,
fa452fa6 763 ppc_cpu_t dialect,
2fbfdc41 764 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 765{
8ebac3aa 766 if ((dialect & ISA_V2) == 0)
802a735e
AM		 767 {
768 if ((value & 0x8000) != 0)
769 insn |= 1 << 21;
770 }
771 else
772 {
773 if ((insn & (0x14 << 21)) == (0x04 << 21))
774 insn |= 0x02 << 21;
775 else if ((insn & (0x14 << 21)) == (0x10 << 21))
776 insn |= 0x08 << 21;
777 }
252b5132
RH		 778 return insn | (value & 0xfffc);
779}
780
781static long
2fbfdc41 782extract_bdm (unsigned long insn,
fa452fa6 783 ppc_cpu_t dialect,
2fbfdc41 784 int *invalid)
252b5132 785{
8ebac3aa 786 if ((dialect & ISA_V2) == 0)
802a735e 787 {
8427c424
AM		 788 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
789 *invalid = 1;
802a735e 790 }
8427c424
AM		 791 else
792 {
793 if ((insn & (0x17 << 21)) != (0x06 << 21)
794 && (insn & (0x1d << 21)) != (0x18 << 21))
795 *invalid = 1;
796 }
797
802a735e 798 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 799}
800
801/* The BD field in a B form instruction when the + modifier is used.
802 This is like BDM, above, except that the branch is expected to be
803 taken. */
804
252b5132 805static unsigned long
2fbfdc41
AM		 806insert_bdp (unsigned long insn,
807 long value,
fa452fa6 808 ppc_cpu_t dialect,
2fbfdc41 809 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 810{
8ebac3aa 811 if ((dialect & ISA_V2) == 0)
802a735e
AM		 812 {
813 if ((value & 0x8000) == 0)
814 insn |= 1 << 21;
815 }
816 else
817 {
818 if ((insn & (0x14 << 21)) == (0x04 << 21))
819 insn |= 0x03 << 21;
820 else if ((insn & (0x14 << 21)) == (0x10 << 21))
821 insn |= 0x09 << 21;
822 }
252b5132
RH		 823 return insn | (value & 0xfffc);
824}
825
826static long
2fbfdc41 827extract_bdp (unsigned long insn,
fa452fa6 828 ppc_cpu_t dialect,
2fbfdc41 829 int *invalid)
252b5132 830{
8ebac3aa 831 if ((dialect & ISA_V2) == 0)
802a735e 832 {
8427c424
AM		 833 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
834 *invalid = 1;
835 }
836 else
837 {
838 if ((insn & (0x17 << 21)) != (0x07 << 21)
839 && (insn & (0x1d << 21)) != (0x19 << 21))
840 *invalid = 1;
802a735e 841 }
8427c424 842
802a735e 843 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 844}
845
8ebac3aa
AM		 846static inline int
847valid_bo_pre_v2 (long value)
252b5132 848{
8ebac3aa
AM		 849 /* Certain encodings have bits that are required to be zero.
850 These are (z must be zero, y may be anything):
851 0000y
852 0001y
853 001zy
854 0100y
855 0101y
856 011zy
857 1z00y
858 1z01y
859 1z1zz
860 */
861 if ((value & 0x14) == 0)
862 return 1;
863 else if ((value & 0x14) == 0x4)
864 return (value & 0x2) == 0;
865 else if ((value & 0x14) == 0x10)
866 return (value & 0x8) == 0;
867 else
868 return value == 0x14;
869}
ba4e851b 870
8ebac3aa
AM		 871static inline int
872valid_bo_post_v2 (long value)
873{
ba4e851b
AM		 874 /* Certain encodings have bits that are required to be zero.
875 These are (z must be zero, a & t may be anything):
876 0000z
877 0001z
8ebac3aa 878 001at
ba4e851b
AM		 879 0100z
880 0101z
ba4e851b
AM		 881 011at
882 1a00t
883 1a01t
884 1z1zz
885 */
886 if ((value & 0x14) == 0)
887 return (value & 0x1) == 0;
888 else if ((value & 0x14) == 0x14)
889 return value == 0x14;
802a735e 890 else
ba4e851b 891 return 1;
252b5132
RH		 892}
893
8ebac3aa
AM		 894/* Check for legal values of a BO field. */
895
896static int
897valid_bo (long value, ppc_cpu_t dialect, int extract)
898{
899 int valid_y = valid_bo_pre_v2 (value);
900 int valid_at = valid_bo_post_v2 (value);
901
902 /* When disassembling with -Many, accept either encoding on the
903 second pass through opcodes. */
904 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
905 return valid_y || valid_at;
906 if ((dialect & ISA_V2) == 0)
907 return valid_y;
908 else
909 return valid_at;
910}
911
252b5132
RH		 912/* The BO field in a B form instruction. Warn about attempts to set
913 the field to an illegal value. */
914
915static unsigned long
2fbfdc41
AM		 916insert_bo (unsigned long insn,
917 long value,
fa452fa6 918 ppc_cpu_t dialect,
2fbfdc41 919 const char **errmsg)
252b5132 920{
ba4e851b 921 if (!valid_bo (value, dialect, 0))
252b5132 922 *errmsg = _("invalid conditional option");
989993d8
JB		 923 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
924 *errmsg = _("invalid counter access");
252b5132
RH		 925 return insn | ((value & 0x1f) << 21);
926}
927
928static long
2fbfdc41 929extract_bo (unsigned long insn,
fa452fa6 930 ppc_cpu_t dialect,
2fbfdc41 931 int *invalid)
252b5132
RH		 932{
933 long value;
934
935 value = (insn >> 21) & 0x1f;
ba4e851b 936 if (!valid_bo (value, dialect, 1))
252b5132
RH		 937 *invalid = 1;
938 return value;
939}
940
941/* The BO field in a B form instruction when the + or - modifier is
942 used. This is like the BO field, but it must be even. When
943 extracting it, we force it to be even. */
944
945static unsigned long
2fbfdc41
AM		 946insert_boe (unsigned long insn,
947 long value,
fa452fa6 948 ppc_cpu_t dialect,
2fbfdc41 949 const char **errmsg)
252b5132 950{
ba4e851b 951 if (!valid_bo (value, dialect, 0))
8427c424 952 *errmsg = _("invalid conditional option");
989993d8
JB		 953 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
954 *errmsg = _("invalid counter access");
8427c424
AM		 955 else if ((value & 1) != 0)
956 *errmsg = _("attempt to set y bit when using + or - modifier");
957
252b5132
RH		 958 return insn | ((value & 0x1f) << 21);
959}
960
961static long
2fbfdc41 962extract_boe (unsigned long insn,
fa452fa6 963 ppc_cpu_t dialect,
2fbfdc41 964 int *invalid)
252b5132
RH		 965{
966 long value;
967
968 value = (insn >> 21) & 0x1f;
ba4e851b 969 if (!valid_bo (value, dialect, 1))
252b5132
RH		 970 *invalid = 1;
971 return value & 0x1e;
972}
973
2fbfdc41
AM		 974/* FXM mask in mfcr and mtcrf instructions. */
975
976static unsigned long
977insert_fxm (unsigned long insn,
978 long value,
fa452fa6 979 ppc_cpu_t dialect,
2fbfdc41 980 const char **errmsg)
c168870a 981{
98e69875
AM		 982 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
983 one bit of the mask field is set. */
984 if ((insn & (1 << 20)) != 0)
985 {
986 if (value == 0 || (value & -value) != value)
987 {
988 *errmsg = _("invalid mask field");
989 value = 0;
990 }
991 }
992
c168870a
AM		 993 /* If the optional field on mfcr is missing that means we want to use
994 the old form of the instruction that moves the whole cr. In that
995 case we'll have VALUE zero. There doesn't seem to be a way to
996 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 997 else if (value == 0)
c168870a
AM		 998 ;
999
1000 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1001 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1002 encoding, this is not backward compatible. Do not generate the
1003 new form unless -mpower4 has been given, or -many and the two
1004 operand form of mfcr was used. */
1005 else if ((value & -value) == value
1006 && ((dialect & PPC_OPCODE_POWER4) != 0
1007 || ((dialect & PPC_OPCODE_ANY) != 0
1008 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1009 insn |= 1 << 20;
1010
1011 /* Any other value on mfcr is an error. */
1012 else if ((insn & (0x3ff << 1)) == 19 << 1)
1013 {
8427c424 1014 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 1015 value = 0;
1016 }
1017
1018 return insn | ((value & 0xff) << 12);
1019}
1020
2fbfdc41
AM		 1021static long
1022extract_fxm (unsigned long insn,
fa452fa6 1023 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1024 int *invalid)
c168870a
AM		 1025{
1026 long mask = (insn >> 12) & 0xff;
1027
1028 /* Is this a Power4 insn? */
1029 if ((insn & (1 << 20)) != 0)
1030 {
98e69875
AM		 1031 /* Exactly one bit of MASK should be set. */
1032 if (mask == 0 || (mask & -mask) != mask)
8427c424 1033 *invalid = 1;
c168870a
AM		 1034 }
1035
1036 /* Check that non-power4 form of mfcr has a zero MASK. */
1037 else if ((insn & (0x3ff << 1)) == 19 << 1)
1038 {
8427c424 1039 if (mask != 0)
c168870a
AM		 1040 *invalid = 1;
1041 }
1042
1043 return mask;
1044}
1045
aea77599
AM		 1046/* The LS field in a sync instruction that accepts 2 operands
1047 Values 2 and 3 are reserved,
1048 must be treated as 0 for future compatibility
1049 Values 0 and 1 can be accepted, if field ESYNC is zero
1050 Otherwise L = complement of ESYNC-bit2 (1<<18) */
1051
1052static unsigned long
1053insert_ls (unsigned long insn,
1054 long value,
1055 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1056 const char **errmsg ATTRIBUTE_UNUSED)
1057{
1058 unsigned long ls;
1059
1060 ls = (insn >> 21) & 0x03;
1061 if (value == 0)
1062 {
1063 if (ls > 1)
1064 return insn & ~(0x3 << 21);
1065 return insn;
1066 }
1067 if ((value & 0x2) != 0)
1068 return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
1069 return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
1070}
1071
252b5132
RH		 1072/* The MB and ME fields in an M form instruction expressed as a single
1073 operand which is itself a bitmask. The extraction function always
1074 marks it as invalid, since we never want to recognize an
1075 instruction which uses a field of this type. */
1076
1077static unsigned long
2fbfdc41
AM		 1078insert_mbe (unsigned long insn,
1079 long value,
fa452fa6 1080 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1081 const char **errmsg)
252b5132
RH		 1082{
1083 unsigned long uval, mask;
1084 int mb, me, mx, count, last;
1085
1086 uval = value;
1087
1088 if (uval == 0)
1089 {
8427c424 1090 *errmsg = _("illegal bitmask");
252b5132
RH		 1091 return insn;
1092 }
1093
1094 mb = 0;
1095 me = 32;
1096 if ((uval & 1) != 0)
1097 last = 1;
1098 else
1099 last = 0;
1100 count = 0;
1101
1102 /* mb: location of last 0->1 transition */
1103 /* me: location of last 1->0 transition */
1104 /* count: # transitions */
1105
0deb7ac5 1106 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1107 {
1108 if ((uval & mask) && !last)
1109 {
1110 ++count;
1111 mb = mx;
1112 last = 1;
1113 }
1114 else if (!(uval & mask) && last)
1115 {
1116 ++count;
1117 me = mx;
1118 last = 0;
1119 }
1120 }
1121 if (me == 0)
1122 me = 32;
1123
1124 if (count != 2 && (count != 0 || ! last))
8427c424 1125 *errmsg = _("illegal bitmask");
252b5132
RH		 1126
1127 return insn | (mb << 6) | ((me - 1) << 1);
1128}
1129
1130static long
2fbfdc41 1131extract_mbe (unsigned long insn,
fa452fa6 1132 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1133 int *invalid)
252b5132
RH		 1134{
1135 long ret;
1136 int mb, me;
1137 int i;
1138
8427c424 1139 *invalid = 1;
252b5132
RH		 1140
1141 mb = (insn >> 6) & 0x1f;
1142 me = (insn >> 1) & 0x1f;
1143 if (mb < me + 1)
1144 {
1145 ret = 0;
1146 for (i = mb; i <= me; i++)
0deb7ac5 1147 ret |= 1L << (31 - i);
252b5132
RH		 1148 }
1149 else if (mb == me + 1)
8427c424 1150 ret = ~0;
252b5132
RH		 1151 else /* (mb > me + 1) */
1152 {
2fbfdc41 1153 ret = ~0;
252b5132 1154 for (i = me + 1; i < mb; i++)
0deb7ac5 1155 ret &= ~(1L << (31 - i));
252b5132
RH		 1156 }
1157 return ret;
1158}
1159
1160/* The MB or ME field in an MD or MDS form instruction. The high bit
1161 is wrapped to the low end. */
1162
252b5132 1163static unsigned long
2fbfdc41
AM		 1164insert_mb6 (unsigned long insn,
1165 long value,
fa452fa6 1166 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1167 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1168{
1169 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1170}
1171
252b5132 1172static long
2fbfdc41 1173extract_mb6 (unsigned long insn,
fa452fa6 1174 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1175 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1176{
1177 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1178}
1179
1180/* The NB field in an X form instruction. The value 32 is stored as
1181 0. */
1182
252b5132 1183static long
2fbfdc41 1184extract_nb (unsigned long insn,
fa452fa6 1185 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1186 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1187{
1188 long ret;
1189
1190 ret = (insn >> 11) & 0x1f;
1191 if (ret == 0)
1192 ret = 32;
1193 return ret;
1194}
1195
989993d8
JB		 1196/* The NB field in an lswi instruction, which has special value
1197 restrictions. The value 32 is stored as 0. */
1198
1199static unsigned long
1200insert_nbi (unsigned long insn,
1201 long value,
1202 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1203 const char **errmsg ATTRIBUTE_UNUSED)
1204{
1205 long rtvalue = (insn & RT_MASK) >> 21;
1206 long ravalue = (insn & RA_MASK) >> 16;
1207
1208 if (value == 0)
1209 value = 32;
1210 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1211 : ravalue))
1212 *errmsg = _("address register in load range");
1213 return insn | ((value & 0x1f) << 11);
1214}
1215
252b5132
RH		 1216/* The NSI field in a D form instruction. This is the same as the SI
1217 field, only negated. The extraction function always marks it as
1218 invalid, since we never want to recognize an instruction which uses
1219 a field of this type. */
1220
252b5132 1221static unsigned long
2fbfdc41
AM		 1222insert_nsi (unsigned long insn,
1223 long value,
fa452fa6 1224 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1225 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1226{
2fbfdc41 1227 return insn | (-value & 0xffff);
252b5132
RH		 1228}
1229
1230static long
2fbfdc41 1231extract_nsi (unsigned long insn,
fa452fa6 1232 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1233 int *invalid)
252b5132 1234{
8427c424 1235 *invalid = 1;
2fbfdc41 1236 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1237}
1238
1239/* The RA field in a D or X form instruction which is an updating
1240 load, which means that the RA field may not be zero and may not
1241 equal the RT field. */
1242
1243static unsigned long
2fbfdc41
AM		 1244insert_ral (unsigned long insn,
1245 long value,
fa452fa6 1246 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1247 const char **errmsg)
252b5132
RH		 1248{
1249 if (value == 0
1250 || (unsigned long) value == ((insn >> 21) & 0x1f))
1251 *errmsg = "invalid register operand when updating";
1252 return insn | ((value & 0x1f) << 16);
1253}
1254
1255/* The RA field in an lmw instruction, which has special value
1256 restrictions. */
1257
1258static unsigned long
2fbfdc41
AM		 1259insert_ram (unsigned long insn,
1260 long value,
fa452fa6 1261 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1262 const char **errmsg)
252b5132
RH		 1263{
1264 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1265 *errmsg = _("index register in load range");
1266 return insn | ((value & 0x1f) << 16);
1267}
1268
989993d8 1269/* The RA field in the DQ form lq or an lswx instruction, which have special
8427c424 1270 value restrictions. */
adadcc0c 1271
adadcc0c 1272static unsigned long
2fbfdc41
AM		 1273insert_raq (unsigned long insn,
1274 long value,
fa452fa6 1275 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1276 const char **errmsg)
adadcc0c
AM		 1277{
1278 long rtvalue = (insn & RT_MASK) >> 21;
1279
8427c424 1280 if (value == rtvalue)
adadcc0c
AM		 1281 *errmsg = _("source and target register operands must be different");
1282 return insn | ((value & 0x1f) << 16);
1283}
1284
252b5132
RH		 1285/* The RA field in a D or X form instruction which is an updating
1286 store or an updating floating point load, which means that the RA
1287 field may not be zero. */
1288
1289static unsigned long
2fbfdc41
AM		 1290insert_ras (unsigned long insn,
1291 long value,
fa452fa6 1292 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1293 const char **errmsg)
252b5132
RH		 1294{
1295 if (value == 0)
1296 *errmsg = _("invalid register operand when updating");
1297 return insn | ((value & 0x1f) << 16);
1298}
1299
1300/* The RB field in an X form instruction when it must be the same as
1301 the RS field in the instruction. This is used for extended
1302 mnemonics like mr. This operand is marked FAKE. The insertion
1303 function just copies the BT field into the BA field, and the
1304 extraction function just checks that the fields are the same. */
1305
252b5132 1306static unsigned long
2fbfdc41
AM		 1307insert_rbs (unsigned long insn,
1308 long value ATTRIBUTE_UNUSED,
fa452fa6 1309 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1310 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1311{
1312 return insn | (((insn >> 21) & 0x1f) << 11);
1313}
1314
1315static long
2fbfdc41 1316extract_rbs (unsigned long insn,
fa452fa6 1317 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1318 int *invalid)
252b5132 1319{
8427c424 1320 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1321 *invalid = 1;
1322 return 0;
1323}
1324
989993d8
JB		 1325/* The RB field in an lswx instruction, which has special value
1326 restrictions. */
1327
1328static unsigned long
1329insert_rbx (unsigned long insn,
1330 long value,
1331 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1332 const char **errmsg)
1333{
1334 long rtvalue = (insn & RT_MASK) >> 21;
1335
1336 if (value == rtvalue)
1337 *errmsg = _("source and target register operands must be different");
1338 return insn | ((value & 0x1f) << 11);
1339}
1340
252b5132
RH		 1341/* The SH field in an MD form instruction. This is split. */
1342
252b5132 1343static unsigned long
2fbfdc41
AM		 1344insert_sh6 (unsigned long insn,
1345 long value,
fa452fa6 1346 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1347 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1348{
1349 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1350}
1351
252b5132 1352static long
2fbfdc41 1353extract_sh6 (unsigned long insn,
fa452fa6 1354 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1355 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1356{
1357 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1358}
1359
1360/* The SPR field in an XFX form instruction. This is flipped--the
1361 lower 5 bits are stored in the upper 5 and vice- versa. */
1362
1363static unsigned long
2fbfdc41
AM		 1364insert_spr (unsigned long insn,
1365 long value,
fa452fa6 1366 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1367 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1368{
1369 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1370}
1371
1372static long
2fbfdc41 1373extract_spr (unsigned long insn,
fa452fa6 1374 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1375 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1376{
1377 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1378}
1379
da99ee72
AM		 1380/* Some dialects have 8 SPRG registers instead of the standard 4. */
1381
1382static unsigned long
1383insert_sprg (unsigned long insn,
1384 long value,
fa452fa6 1385 ppc_cpu_t dialect,
da99ee72
AM		 1386 const char **errmsg)
1387{
da99ee72
AM		 1388 if (value > 7
1389 || (value > 3
081ba1b3 1390 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
da99ee72
AM		 1391 *errmsg = _("invalid sprg number");
1392
1393 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1394 user mode. Anything else must use spr 272..279. */
1395 if (value <= 3 || (insn & 0x100) != 0)
1396 value |= 0x10;
1397
1398 return insn | ((value & 0x17) << 16);
1399}
1400
1401static long
1402extract_sprg (unsigned long insn,
fa452fa6 1403 ppc_cpu_t dialect,
da99ee72
AM		 1404 int *invalid)
1405{
1406 unsigned long val = (insn >> 16) & 0x1f;
1407
1408 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1409 If not BOOKE or 405, then both use only 272..275. */
e1c93c69
AM		 1410 if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1411 || (val - 0x10 > 7 && (insn & 0x100) != 0)
1412 || val <= 3
1413 || (val & 8) != 0)
da99ee72
AM		 1414 *invalid = 1;
1415 return val & 7;
1416}
1417
252b5132
RH		 1418/* The TBR field in an XFX instruction. This is just like SPR, but it
1419 is optional. When TBR is omitted, it must be inserted as 268 (the
1420 magic number of the TB register). These functions treat 0
1421 (indicating an omitted optional operand) as 268. This means that
1422 ``mftb 4,0'' is not handled correctly. This does not matter very
1423 much, since the architecture manual does not define mftb as
1424 accepting any values other than 268 or 269. */
1425
1426#define TB (268)
1427
1428static unsigned long
2fbfdc41
AM		 1429insert_tbr (unsigned long insn,
1430 long value,
fa452fa6 1431 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1432 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1433{
1434 if (value == 0)
1435 value = TB;
1436 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1437}
1438
1439static long
2fbfdc41 1440extract_tbr (unsigned long insn,
fa452fa6 1441 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1442 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1443{
1444 long ret;
1445
1446 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1447 if (ret == TB)
1448 ret = 0;
1449 return ret;
1450}
9b4e5766
PB		 1451
1452/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1453
1454static unsigned long
1455insert_xt6 (unsigned long insn,
1456 long value,
1457 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1458 const char **errmsg ATTRIBUTE_UNUSED)
1459{
1460 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1461}
1462
1463static long
1464extract_xt6 (unsigned long insn,
1465 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1466 int *invalid ATTRIBUTE_UNUSED)
1467{
1468 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1469}
1470
1471/* The XA field in an XX3 form instruction. This is split. */
1472
1473static unsigned long
1474insert_xa6 (unsigned long insn,
1475 long value,
1476 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1477 const char **errmsg ATTRIBUTE_UNUSED)
1478{
1479 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1480}
1481
1482static long
1483extract_xa6 (unsigned long insn,
1484 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1485 int *invalid ATTRIBUTE_UNUSED)
1486{
1487 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1488}
1489
1490/* The XB field in an XX3 form instruction. This is split. */
1491
1492static unsigned long
1493insert_xb6 (unsigned long insn,
1494 long value,
1495 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1496 const char **errmsg ATTRIBUTE_UNUSED)
1497{
1498 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1499}
1500
1501static long
1502extract_xb6 (unsigned long insn,
1503 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1504 int *invalid ATTRIBUTE_UNUSED)
1505{
1506 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1507}
1508
1509/* The XB field in an XX3 form instruction when it must be the same as
1510 the XA field in the instruction. This is used for extended
1511 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1512 function just copies the XA field into the XB field, and the
1513 extraction function just checks that the fields are the same. */
1514
1515static unsigned long
1516insert_xb6s (unsigned long insn,
1517 long value ATTRIBUTE_UNUSED,
1518 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1519 const char **errmsg ATTRIBUTE_UNUSED)
1520{
1521 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1522}
1523
1524static long
1525extract_xb6s (unsigned long insn,
1526 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1527 int *invalid)
1528{
1529 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1530 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1531 *invalid = 1;
1532 return 0;
1533}
066be9f7
PB		 1534
1535/* The XC field in an XX4 form instruction. This is split. */
1536
1537static unsigned long
1538insert_xc6 (unsigned long insn,
1539 long value,
1540 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1541 const char **errmsg ATTRIBUTE_UNUSED)
1542{
1543 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1544}
1545
1546static long
1547extract_xc6 (unsigned long insn,
1548 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1549 int *invalid ATTRIBUTE_UNUSED)
1550{
1551 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1552}
1553
1554static unsigned long
1555insert_dm (unsigned long insn,
1556 long value,
1557 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1558 const char **errmsg)
1559{
1560 if (value != 0 && value != 1)
1561 *errmsg = _("invalid constant");
1562 return insn | (((value) ? 3 : 0) << 8);
1563}
1564
1565static long
1566extract_dm (unsigned long insn,
1567 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1568 int *invalid)
1569{
1570 long value;
1571
1572 value = (insn >> 8) & 3;
1573 if (value != 0 && value != 3)
1574 *invalid = 1;
1575 return (value) ? 1 : 0;
1576}
252b5132
RH		 1577\f
1578/* Macros used to form opcodes. */
1579
1580/* The main opcode. */
1581#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1582#define OP_MASK OP (0x3f)
1583
1584/* The main opcode combined with a trap code in the TO field of a D
1585 form instruction. Used for extended mnemonics for the trap
1586 instructions. */
1587#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1588#define OPTO_MASK (OP_MASK | TO_MASK)
1589
1590/* The main opcode combined with a comparison size bit in the L field
1591 of a D form or X form instruction. Used for extended mnemonics for
1592 the comparison instructions. */
1593#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1594#define OPL_MASK OPL (0x3f,1)
1595
1596/* An A form instruction. */
1597#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1598#define A_MASK A (0x3f, 0x1f, 1)
1599
1600/* An A_MASK with the FRB field fixed. */
1601#define AFRB_MASK (A_MASK | FRB_MASK)
1602
1603/* An A_MASK with the FRC field fixed. */
1604#define AFRC_MASK (A_MASK | FRC_MASK)
1605
1606/* An A_MASK with the FRA and FRC fields fixed. */
1607#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1608
702f0fb4
PB		 1609/* An AFRAFRC_MASK, but with L bit clear. */
1610#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1611
252b5132
RH		 1612/* A B form instruction. */
1613#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1614#define B_MASK B (0x3f, 1, 1)
1615
1616/* A B form instruction setting the BO field. */
1617#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1618#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1619
1620/* A BBO_MASK with the y bit of the BO field removed. This permits
1621 matching a conditional branch regardless of the setting of the y
94efba12 1622 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 1623#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 1624#define AT1_MASK (((unsigned long) 3) << 21)
1625#define AT2_MASK (((unsigned long) 9) << 21)
1626#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1627#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1628
1629/* A B form instruction setting the BO field and the condition bits of
1630 the BI field. */
1631#define BBOCB(op, bo, cb, aa, lk) \
1632 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1633#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1634
1635/* A BBOCB_MASK with the y bit of the BO field removed. */
1636#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1637#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1638#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1639
1640/* A BBOYCB_MASK in which the BI field is fixed. */
1641#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1642#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1643
23976049
EZ		 1644/* An Context form instruction. */
1645#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1646#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1647
1648/* An User Context form instruction. */
1649#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1650#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1651
252b5132
RH		 1652/* The main opcode mask with the RA field clear. */
1653#define DRA_MASK (OP_MASK | RA_MASK)
1654
1655/* A DS form instruction. */
1656#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1657#define DS_MASK DSO (0x3f, 3)
1658
23976049
EZ		 1659/* An EVSEL form instruction. */
1660#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1661#define EVSEL_MASK EVSEL(0x3f, 0xff)
1662
252b5132
RH		 1663/* An M form instruction. */
1664#define M(op, rc) (OP (op) | ((rc) & 1))
1665#define M_MASK M (0x3f, 1)
1666
1667/* An M form instruction with the ME field specified. */
1668#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1669
1670/* An M_MASK with the MB and ME fields fixed. */
1671#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1672
1673/* An M_MASK with the SH and ME fields fixed. */
1674#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1675
1676/* An MD form instruction. */
1677#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1678#define MD_MASK MD (0x3f, 0x7, 1)
1679
1680/* An MD_MASK with the MB field fixed. */
1681#define MDMB_MASK (MD_MASK | MB6_MASK)
1682
1683/* An MD_MASK with the SH field fixed. */
1684#define MDSH_MASK (MD_MASK | SH6_MASK)
1685
1686/* An MDS form instruction. */
1687#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1688#define MDS_MASK MDS (0x3f, 0xf, 1)
1689
1690/* An MDS_MASK with the MB field fixed. */
1691#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1692
1693/* An SC form instruction. */
1694#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1695#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1696
112290ab 1697/* An VX form instruction. */
786e2c0f
C		 1698#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1699
112290ab 1700/* The mask for an VX form instruction. */
786e2c0f
C		 1701#define VX_MASK VX(0x3f, 0x7ff)
1702
112290ab 1703/* An VA form instruction. */
2613489e 1704#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1705
112290ab 1706/* The mask for an VA form instruction. */
2613489e 1707#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1708
112290ab 1709/* An VXR form instruction. */
786e2c0f
C		 1710#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1711
112290ab 1712/* The mask for a VXR form instruction. */
786e2c0f
C		 1713#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1714
252b5132
RH		 1715/* An X form instruction. */
1716#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1717
066be9f7
PB		 1718/* An XX2 form instruction. */
1719#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
1720
9b4e5766
PB		 1721/* An XX3 form instruction. */
1722#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1723
066be9f7
PB		 1724/* An XX3 form instruction with the RC bit specified. */
1725#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
1726
1727/* An XX4 form instruction. */
1728#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
9b4e5766 1729
702f0fb4
PB		 1730/* A Z form instruction. */
1731#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1732
252b5132
RH		 1733/* An X form instruction with the RC bit specified. */
1734#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1735
702f0fb4
PB		 1736/* A Z form instruction with the RC bit specified. */
1737#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1738
252b5132
RH		 1739/* The mask for an X form instruction. */
1740#define X_MASK XRC (0x3f, 0x3ff, 1)
1741
e0d602ec
BE		 1742/* An X form wait instruction with everything filled in except the WC field. */
1743#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1744
9b4e5766
PB		 1745/* The mask for an XX1 form instruction. */
1746#define XX1_MASK X (0x3f, 0x3ff)
1747
066be9f7
PB		 1748/* The mask for an XX2 form instruction. */
1749#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
1750
1751/* The mask for an XX2 form instruction with the UIM bits specified. */
1752#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
1753
1754/* The mask for an XX2 form instruction with the BF bits specified. */
1755#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
1756
9b4e5766
PB		 1757/* The mask for an XX3 form instruction. */
1758#define XX3_MASK XX3 (0x3f, 0xff)
1759
066be9f7
PB		 1760/* The mask for an XX3 form instruction with the BF bits specified. */
1761#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
1762
1763/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
9b4e5766 1764#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
066be9f7
PB		 1765#define XX3SHW_MASK XX3DM_MASK
1766
1767/* The mask for an XX4 form instruction. */
1768#define XX4_MASK XX4 (0x3f, 0x3)
1769
1770/* An X form wait instruction with everything filled in except the WC field. */
1771#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
9b4e5766 1772
702f0fb4
PB		 1773/* The mask for a Z form instruction. */
1774#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 1775#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 1776
252b5132
RH		 1777/* An X_MASK with the RA field fixed. */
1778#define XRA_MASK (X_MASK | RA_MASK)
1779
ea192fa3
PB		 1780/* An XRA_MASK with the W field clear. */
1781#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1782
252b5132
RH		 1783/* An X_MASK with the RB field fixed. */
1784#define XRB_MASK (X_MASK | RB_MASK)
1785
1786/* An X_MASK with the RT field fixed. */
1787#define XRT_MASK (X_MASK | RT_MASK)
1788
702f0fb4
PB		 1789/* An XRT_MASK mask with the L bits clear. */
1790#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1791
252b5132
RH		 1792/* An X_MASK with the RA and RB fields fixed. */
1793#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1794
112290ab 1795/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1796#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1797
252b5132
RH		 1798/* An X_MASK with the RT and RA fields fixed. */
1799#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1800
98acc1c5
AM		 1801/* An XRTRA_MASK, but with L bit clear. */
1802#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1803
f3806e43
BE		 1804/* An X form instruction with the L bit specified. */
1805#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 1806
e0d602ec
BE		 1807/* An X form instruction with the L bits specified. */
1808#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1809
19a6653c
AM		 1810/* An X form instruction with RT fields specified */
1811#define XRT(op, xop, rt) (X ((op), (xop)) \
1812 | ((((unsigned long)(rt)) & 0x1f) << 21))
1813
1814/* An X form instruction with RT and RA fields specified */
1815#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1816 | ((((unsigned long)(rt)) & 0x1f) << 21) \
1817 | ((((unsigned long)(ra)) & 0x1f) << 16))
1818
252b5132
RH		 1819/* The mask for an X form comparison instruction. */
1820#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1821
520ceea4
BE		 1822/* The mask for an X form comparison instruction with the L field
1823 fixed. */
1824#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1825
1826/* An X form trap instruction with the TO field specified. */
1827#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1828#define XTO_MASK (X_MASK | TO_MASK)
1829
e0c21649
GK		 1830/* An X form tlb instruction with the SH field specified. */
1831#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1832#define XTLB_MASK (X_MASK | SH_MASK)
1833
6ba045b1
AM		 1834/* An X form sync instruction. */
1835#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1836
1837/* An X form sync instruction with everything filled in except the LS field. */
1838#define XSYNC_MASK (0xff9fffff)
1839
aea77599
AM		 1840/* An X form sync instruction with everything filled in except the L and E fields. */
1841#define XSYNCLE_MASK (0xff90ffff)
1842
702f0fb4
PB		 1843/* An X_MASK, but with the EH bit clear. */
1844#define XEH_MASK (X_MASK & ~((unsigned long )1))
1845
f5c120c5
MG		 1846/* An X form AltiVec dss instruction. */
1847#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1848#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1849
252b5132
RH		 1850/* An XFL form instruction. */
1851#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 1852#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 1853
23976049 1854/* An X form isel instruction. */
de866fcc
AM		 1855#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1856#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 1857
252b5132
RH		 1858/* An XL form instruction with the LK field set to 0. */
1859#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1860
1861/* An XL form instruction which uses the LK field. */
1862#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1863
1864/* The mask for an XL form instruction. */
1865#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1866
1867/* An XL form instruction which explicitly sets the BO field. */
1868#define XLO(op, bo, xop, lk) \
1869 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1870#define XLO_MASK (XL_MASK | BO_MASK)
1871
1872/* An XL form instruction which explicitly sets the y bit of the BO
1873 field. */
1874#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1875#define XLYLK_MASK (XL_MASK | Y_MASK)
1876
1877/* An XL form instruction which sets the BO field and the condition
1878 bits of the BI field. */
1879#define XLOCB(op, bo, cb, xop, lk) \
1880 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1881#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1882
1883/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1884#define XLBB_MASK (XL_MASK | BB_MASK)
1885#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1886#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1887
d0618d1c
AM		 1888/* A mask for branch instructions using the BH field. */
1889#define XLBH_MASK (XL_MASK | (0x1c << 11))
1890
252b5132
RH		 1891/* An XL_MASK with the BO and BB fields fixed. */
1892#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1893
1894/* An XL_MASK with the BO, BI and BB fields fixed. */
1895#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1896
e01d869a
AM		 1897/* An X form mbar instruction with MO field. */
1898#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
1899
252b5132
RH		 1900/* An XO form instruction. */
1901#define XO(op, xop, oe, rc) \
1902 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1903#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1904
1905/* An XO_MASK with the RB field fixed. */
1906#define XORB_MASK (XO_MASK | RB_MASK)
1907
c3d65c1c
BE		 1908/* An XOPS form instruction for paired singles. */
1909#define XOPS(op, xop, rc) \
1910 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1911#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1912
1913
252b5132
RH		 1914/* An XS form instruction. */
1915#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1916#define XS_MASK XS (0x3f, 0x1ff, 1)
1917
1918/* A mask for the FXM version of an XFX form instruction. */
98e69875 1919#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1920
1921/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1922#define XFXM(op, xop, fxm, p4) \
1923 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1924 | ((unsigned long)(p4) << 20))
252b5132
RH		 1925
1926/* An XFX form instruction with the SPR field filled in. */
1927#define XSPR(op, xop, spr) \
1928 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1929#define XSPR_MASK (X_MASK | SPR_MASK)
1930
1931/* An XFX form instruction with the SPR field filled in except for the
1932 SPRBAT field. */
1933#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1934
1935/* An XFX form instruction with the SPR field filled in except for the
1936 SPRG field. */
b84bf58a 1937#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 1938
1939/* An X form instruction with everything filled in except the E field. */
1940#define XE_MASK (0xffff7fff)
1941
23976049
EZ		 1942/* An X form user context instruction. */
1943#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1944#define XUC_MASK XUC(0x3f, 0x1f)
1945
c3d65c1c
BE		 1946/* An XW form instruction. */
1947#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1948/* The mask for a G form instruction. rc not supported at present. */
1949#define XW_MASK XW (0x3f, 0x3f, 0)
1950
081ba1b3
AM		 1951/* An APU form instruction. */
1952#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1953
1954/* The mask for an APU form instruction. */
1955#define APU_MASK APU (0x3f, 0x3ff, 1)
1956#define APU_RT_MASK (APU_MASK | RT_MASK)
1957#define APU_RA_MASK (APU_MASK | RA_MASK)
1958
252b5132
RH		 1959/* The BO encodings used in extended conditional branch mnemonics. */
1960#define BODNZF (0x0)
1961#define BODNZFP (0x1)
1962#define BODZF (0x2)
1963#define BODZFP (0x3)
252b5132
RH		 1964#define BODNZT (0x8)
1965#define BODNZTP (0x9)
1966#define BODZT (0xa)
1967#define BODZTP (0xb)
802a735e
AM		 1968
1969#define BOF (0x4)
1970#define BOFP (0x5)
94efba12
AM		 1971#define BOFM4 (0x6)
1972#define BOFP4 (0x7)
252b5132
RH		 1973#define BOT (0xc)
1974#define BOTP (0xd)
94efba12
AM		 1975#define BOTM4 (0xe)
1976#define BOTP4 (0xf)
802a735e 1977
252b5132
RH		 1978#define BODNZ (0x10)
1979#define BODNZP (0x11)
1980#define BODZ (0x12)
1981#define BODZP (0x13)
94efba12
AM		 1982#define BODNZM4 (0x18)
1983#define BODNZP4 (0x19)
1984#define BODZM4 (0x1a)
1985#define BODZP4 (0x1b)
802a735e 1986
252b5132
RH		 1987#define BOU (0x14)
1988
1989/* The BI condition bit encodings used in extended conditional branch
1990 mnemonics. */
1991#define CBLT (0)
1992#define CBGT (1)
1993#define CBEQ (2)
1994#define CBSO (3)
1995
1996/* The TO encodings used in extended trap mnemonics. */
1997#define TOLGT (0x1)
1998#define TOLLT (0x2)
1999#define TOEQ (0x4)
2000#define TOLGE (0x5)
2001#define TOLNL (0x5)
2002#define TOLLE (0x6)
2003#define TOLNG (0x6)
2004#define TOGT (0x8)
2005#define TOGE (0xc)
2006#define TONL (0xc)
2007#define TOLT (0x10)
2008#define TOLE (0x14)
2009#define TONG (0x14)
2010#define TONE (0x18)
2011#define TOU (0x1f)
2012\f
2013/* Smaller names for the flags so each entry in the opcodes table will
2014 fit on a single line. */
1cb0a767 2015#define PPCNONE 0
252b5132 2016#undef PPC
de866fcc 2017#define PPC PPC_OPCODE_PPC
661bd698 2018#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 2019#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 2020#define POWER5 PPC_OPCODE_POWER5
702f0fb4 2021#define POWER6 PPC_OPCODE_POWER6
066be9f7 2022#define POWER7 PPC_OPCODE_POWER7
ede602d7 2023#define CELL PPC_OPCODE_CELL
bdc70b4a 2024#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
6b069ee7 2025#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
bdc70b4a 2026 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
418c1742 2027#define PPC403 PPC_OPCODE_403
081ba1b3 2028#define PPC405 PPC_OPCODE_405
7d5b217e 2029#define PPC440 PPC_OPCODE_440
c8187e15 2030#define PPC464 PPC440
9fe54b1c 2031#define PPC476 PPC_OPCODE_476
252b5132 2032#define PPC750 PPC
33e8d5ac 2033#define PPC7450 PPC
252b5132 2034#define PPC860 PPC
c3d65c1c 2035#define PPCPS PPC_OPCODE_PPCPS
a404d431 2036#define PPCVEC PPC_OPCODE_ALTIVEC
aea77599 2037#define PPCVEC2 PPC_OPCODE_ALTIVEC2
9b4e5766 2038#define PPCVSX PPC_OPCODE_VSX
de866fcc
AM		 2039#define POWER PPC_OPCODE_POWER
2040#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
81a0b7e2
AM		 2041#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2042#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
de866fcc 2043#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
de866fcc 2044#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 2045#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc 2046#define MFDEC1 PPC_OPCODE_POWER
bdc70b4a 2047#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
418c1742 2048#define BOOKE PPC_OPCODE_BOOKE
6b069ee7 2049#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_EFS
36ae0db3 2050#define PPCE300 PPC_OPCODE_E300
23976049 2051#define PPCSPE PPC_OPCODE_SPE
de866fcc 2052#define PPCISEL PPC_OPCODE_ISEL
23976049 2053#define PPCEFS PPC_OPCODE_EFS
de866fcc 2054#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 2055#define PPCPMR PPC_OPCODE_PMR
aea77599 2056#define PPCTMR PPC_OPCODE_TMR
de866fcc 2057#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 2058#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 2059#define E500MC PPC_OPCODE_E500MC
634b50f2 2060#define PPCA2 PPC_OPCODE_A2
ce3d2015
AM		 2061#define TITAN PPC_OPCODE_TITAN
2062#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
e01d869a 2063#define E500 PPC_OPCODE_E500
aea77599 2064#define E6500 PPC_OPCODE_E6500
252b5132
RH		 2065\f
2066/* The opcode table.
2067
2068 The format of the opcode table is:
2069
8ebac3aa 2070 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
252b5132
RH		 2071
2072 NAME is the name of the instruction.
2073 OPCODE is the instruction opcode.
2074 MASK is the opcode mask; this is used to tell the disassembler
2075 which bits in the actual opcode must match OPCODE.
8ebac3aa
AM		 2076 FLAGS are flags indicating which processors support the instruction.
2077 ANTI indicates which processors don't support the instruction.
252b5132
RH		 2078 OPERANDS is the list of operands.
2079
2080 The disassembler reads the table in order and prints the first
2081 instruction which matches, so this table is sorted to put more
de866fcc
AM		 2082 specific instructions before more general instructions.
2083
2084 This table must be sorted by major opcode. Please try to keep it
2085 vaguely sorted within major opcode too, except of course where
2086 constrained otherwise by disassembler operation. */
252b5132
RH		 2087
2088const struct powerpc_opcode powerpc_opcodes[] = {
9fe54b1c 2089{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}},
1cb0a767
PB		 2090{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2091{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2092{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2093{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2094{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2095{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2096{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2097{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2098{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2099{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2100{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2101{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2102{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2103{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2104{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
2105
2106{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2107{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2108{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2109{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2110{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2111{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2112{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2113{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2114{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2115{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2116{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2117{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2118{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2119{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2120{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2121{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2122{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2123{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2124{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2125{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2126{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2127{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2128{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2129{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2130{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2131{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2132{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2133{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2134{"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
2135{"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
2136
2137{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2138{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2139{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2140{"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2141{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2142{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2143{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2144{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
2145{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2146{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
2147{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2148{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2149{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2150{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2151{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2152{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2153{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2154{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
ce3d2015 2155{"machhwu", XO (4, 12,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2156{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
ce3d2015 2157{"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2158{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2159{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2160{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2161{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2162{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2163{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2164{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2165{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2166{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2167{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2168{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2169{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2170{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2171{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2172{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2173{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2174{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2175{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2176{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2177{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2178{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2179{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2180{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2181{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}},
2182{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2183{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
2184{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2185{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
2186{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2187{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2188{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2189{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2190{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2191{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2192{"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2193{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2194{"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2195{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2196{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2197{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2198{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2199{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2200{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2201{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2202{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2203{"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2204{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2205{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2206{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2207{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
2208{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2209{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
2210{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2211{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015 2212{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2213{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015
AM		 2214{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2215{"machhw", XO (4, 44,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2216{"machhw.", XO (4, 44,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2217{"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2218{"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2219{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2220{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2221{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2222{"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2223{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2224{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2225{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2226{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2227{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015
AM		 2228{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2229{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2230{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
aea77599 2231{"vabsdub", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
1cb0a767
PB		 2232{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2233{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2234{"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2235{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2236{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2237{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
aea77599 2238{"vabsduh", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
1cb0a767
PB		 2239{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2240{"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2241{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2242{"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2243{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2244{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2245{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015 2246{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2247{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015
AM		 2248{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2249{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2250{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
aea77599 2251{"vabsduw", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
1cb0a767
PB		 2252{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2253{"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2254{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2255{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2256{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2257{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2258{"mulchw", XRC(4, 168,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2259{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2260{"macchw", XO (4, 172,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2261{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2262{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2263{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2264{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2265{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2266{"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2267{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2268{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2269{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2270{"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2271{"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2272{"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2273{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2274{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2275{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2276{"macchws", XO (4, 236,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2277{"macchws.", XO (4, 236,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2278{"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2279{"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2280{"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2281{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2282{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
2283{"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2284{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2285{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}},
2286{"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2287{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}},
2288{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
2289{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2290{"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2291{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2292{"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2293{"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2294{"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2295{"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2296{"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2297{"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2298{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2299{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2300{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2301{"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2302{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2303{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2304{"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2305{"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2306{"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2307{"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
2308{"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2309{"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2310{"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
2311{"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2312{"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2313{"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2314{"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2315{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2316{"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2317{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2318{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2319{"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2320{"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2321{"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2322{"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
2323{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2324{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
2325{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2326{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2327{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2328{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2329{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2330{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2331{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2332{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2333{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2334{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2335{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2336{"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2337{"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2338{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2339{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2340{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2341{"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2342{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2343{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2344{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}},
2345{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2346{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2347{"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2348{"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2349{"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2350{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2351{"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2352{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2353{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2354{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2355{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2356{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2357{"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2358{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2359{"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2360{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2361{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2362{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2363{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2364{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2365{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2366{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2367{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2368{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2369{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2370{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2371{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2372{"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2373{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2374{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2375{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2376{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2377{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2378{"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2379{"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2380{"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2381{"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2382{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2383{"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2384{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2385{"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2386{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2387{"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2388{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2389{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2390{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2391{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2392{"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2393{"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2394{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2395{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2396{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2397{"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2398{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2399{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2400{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2401{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2402{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2403{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2404{"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2405{"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2406{"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2407{"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2408{"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2409{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2410{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2411{"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2412{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2413{"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2414{"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2415{"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2416{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2417{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2418{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2419{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2420{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2421{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2422{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2423{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2424{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2425{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2426{"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2427{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2428{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2429{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2430{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2431{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2432{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2433{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2434{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2435{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2436{"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2437{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2438{"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2439{"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2440{"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2441{"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2442{"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2443{"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2444{"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2445{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2446{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2447{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2448{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
2449{"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2450{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2451{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
2452{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
2453{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2454{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2455{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
ce3d2015 2456{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2457{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2458{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2459{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2460{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2461{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2462{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2463{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
ce3d2015 2464{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2465{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2466{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2467{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2468{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2469{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2470{"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2471{"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2472{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2473{"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2474{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2475{"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2476{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2477{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2478{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2479{"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2480{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2481{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2482{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2483{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2484{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2485{"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2486{"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2487{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2488{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2489{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2490{"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
2491{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
ce3d2015
AM		 2492{"mullhw", XRC(4, 424,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2493{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2494{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2495{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2496{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2497{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2498{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2499{"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2500{"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2501{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2502{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2503{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
ce3d2015
AM		 2504{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2505{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2506{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2507{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2508{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
ce3d2015
AM		 2509{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2510{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2511{"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2512{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2513{"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2514{"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2515{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2516{"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2517{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2518{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2519{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2520{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2521{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2522{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2523{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2524{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2525{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2526{"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2527{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2528{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2529{"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2530{"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2531{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2532{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2533{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2534{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2535{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2536{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2537{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2538{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2539{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2540{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2541{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2542{"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2543{"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2544{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2545{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2546{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2547{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2548{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2549{"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2550{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2551{"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2552{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2553{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2554{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2555{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2556{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2557{"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2558{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2559{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2560{"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2561{"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2562{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2563{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2564{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2565{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2566{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2567{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2568{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2569{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2570{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2571{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2572{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2573{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2574{"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2575{"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2576{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2577{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2578{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
ce3d2015
AM		 2579{"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2580{"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2581{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2582{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2583{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2584{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2585{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2586{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2587{"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2588{"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2589{"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2590{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2591{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2592{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2593{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2594{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2595{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2596{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2597{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
ce3d2015
AM		 2598{"machhwso", XO (4, 108,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2599{"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2600{"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2601{"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2602{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2603{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2604{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2605{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2606{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2607{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2608{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2609{"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2610{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
9fe54b1c
PB		 2611{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2612{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2613{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2614{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2615{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2616{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2617{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2618{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2619{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2620{"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2621{"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2622{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2623{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2624{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2625{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2626{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2627{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2628{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2629{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2630{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2631{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2632{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2633{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2634{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2635{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2636{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2637{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2638{"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2639{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2640{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2641{"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2642{"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2643{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2644{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2645{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2646{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2647{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2648{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2649{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
9fe54b1c
PB		 2650{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2651{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2652{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2653{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2654{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2655{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2656{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2657{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2658{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2659{"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2660{"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2661{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2662{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2663{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2664{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2665{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2666{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2667{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2668{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2669{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2670{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2671{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2672{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2673{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2674{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2675{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2676{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2677{"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2678{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2679{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2680{"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2681{"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2682{"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2683{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}},
2684{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2685{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2686{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2687{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2688{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2689{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}},
2690{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2691{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2692{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2693{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2694{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2695{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2696{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2697{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2698{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2699{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2700{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2701{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2702{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2703{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2704{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2705{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767 2706{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2707{"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2708{"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2709{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2710{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2711{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2712{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
ce3d2015
AM		 2713{"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2714{"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2715{"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2716{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2717{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2718{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2719{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2720{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767 2721{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2722{"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2723{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2724{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2725{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2726{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
ce3d2015
AM		 2727{"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2728{"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2729{"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2730{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2731{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}},
2732
2733{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2734{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2735
2736{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2737{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2738
2739{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
2740
2741{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
2742{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
2743{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
bdc70b4a 2744{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
1cb0a767
PB		 2745
2746{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
2747{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
2748{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
bdc70b4a 2749{"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
1cb0a767
PB		 2750
2751{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2752{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2753{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
2754
2755{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2756{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2757{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
2758
2759{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}},
2760{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
2761{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}},
2762{"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
2763{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
2764{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
2765
2766{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}},
2767{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
2768{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
2769{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
2770{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
2771
2772{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2773{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2774{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
2775{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
2776{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2777{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2778{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
2779{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
2780{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2781{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2782{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
2783{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
2784{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2785{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2786{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
2787{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
2788{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2789{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2790{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}},
2791{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2792{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2793{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}},
2794{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2795{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2796{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}},
2797{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2798{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2799{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}},
2800
2801{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2802{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2803{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2804{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2805{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2806{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2807{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2808{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2809{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2810{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2811{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2812{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2813{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2814{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2815{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2816{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2817{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2818{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2819{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2820{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2821{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2822{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2823{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2824{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2825{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2826{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2827{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2828{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2829{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2830{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2831{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2832{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2833{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2834{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2835{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2836{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2837{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2838{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2839{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2840{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2841{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2842{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2843{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2844{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2845{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2846{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2847{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2848{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2849{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2850{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2851{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2852{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2853{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2854{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2855{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2856{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2857{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2858{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2859{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2860{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2861{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2862{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2863{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2864{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2865{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2866{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2867{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2868{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2869{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2870{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2871{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2872{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2873{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2874{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2875{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2876{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2877{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2878{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2879{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2880{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2881{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2882{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2883{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2884{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2885
2886{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2887{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2888{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2889{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2890{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2891{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2892{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2893{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2894{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2895{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2896{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2897{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2898{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2899{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2900{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2901{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2902{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2903{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2904{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2905{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2906{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2907{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2908{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2909{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2910{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2911{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2912{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2913{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2914{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2915{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2916{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2917{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2918{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2919{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2920{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2921{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2922{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2923{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2924{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2925{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2926{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2927{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2928{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2929{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2930{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2931{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2932{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2933{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2934{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2935{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2936{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2937{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2938{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2939{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2940{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2941{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2942{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2943{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2944{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2945{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2946
8ebac3aa
AM		 2947{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2948{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2949{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2950{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2951{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2952{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2953{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2954{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2955{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2956{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2957{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2958{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2959{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2960{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2961{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2962{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2963{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2964{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2965{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2966{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2967{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2968{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2969{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767
PB		 2970{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2971
2972{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2973{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2974{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2975{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2976{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2977{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2978{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2979{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2980{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2981{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2982{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2983{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2984{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2985{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2986{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2987{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2988
8ebac3aa
AM		 2989{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2990{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2991{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2992{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2993{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2994{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2995{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2996{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2997{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2998{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2999{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 3000{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 3001{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3002{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 3003{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 3004{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3005{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 3006{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 3007{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3008{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 3009{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 3010{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3011{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767
PB		 3012{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3013
3014{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
3015{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
3016{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
3017{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
3018{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
3019{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
3020{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
3021{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
3022{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
3023{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
3024{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3025{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
3026{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
3027{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
3028{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3029{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
3030
3031{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
3032{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
3033{"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}},
3034{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
3035{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
3036{"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}},
3037{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
3038{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
3039{"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
3040{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
3041{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
3042{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
3043
3044{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3045{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3046{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
3047{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
3048{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
3049
3050{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}},
3051{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}},
3052{"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}},
3053{"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}},
3054
3055{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
3056
3057{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa 3058{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767 3059{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa
AM		 3060{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3061{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3062{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767 3063{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa 3064{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767 3065{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa
AM		 3066{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3067{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3068{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767
PB		 3069{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3070{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
3071{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3072{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
8ebac3aa
AM		 3073{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3074{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3075{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3076{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3077{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3078{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3079{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3080{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
1cb0a767
PB		 3081
3082{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3083{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3084{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3085{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3086{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3087{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3088{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3089{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3090{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3091{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3092{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3093{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3094{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3095{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3096{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3097{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3098{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3099{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3100{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3101{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3102{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3103{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3104{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3105{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3106{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3107{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3108{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3109{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3110{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3111{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3112{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3113{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3114{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3115{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3116{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3117{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3118{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3119{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3120{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3121{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3122{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3123{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3124{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3125{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3126{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3127{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3128{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3129{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3130{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3131{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3132{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3133{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3134{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3135{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3136{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3137{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3138{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3139{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3140{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3141{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3142{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3143{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3144{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3145{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3146{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3147{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3148{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3149{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3150{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3151{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3152{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3153{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3154{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3155{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3156{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3157{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3158{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3159{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3160{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3161{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3162{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3163{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767 3164{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3165{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3166{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3167{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3168{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3169{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3170{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3171{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3172{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3173{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3174{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3175{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3176{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3177{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3178{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3179{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3180{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3181{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3182{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3183{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3184{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3185{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3186{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3187{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3188{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3189{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3190{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3191{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3192{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3193{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3194{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3195{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3196{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3197{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3198{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3199{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3200{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3201{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3202{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3203{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3204{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3205{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3206{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3207{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3208{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3209{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3210{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3211{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3212{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3213{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3214{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3215{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3216{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3217{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3218{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3219{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3220{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3221{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767
PB		 3222
3223{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3224{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3225{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3226{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3227{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3228{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3229{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3230{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3231{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3232{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3233{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3234{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3235{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3236{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767
PB		 3237{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3238{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3239{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3240{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3241{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3242{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3243{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3244{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3245{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3246{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767 3247{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3248{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3249{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3250{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3251{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3252{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3253{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3254{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3255{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3256{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3257{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3258{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3259{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3260{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767
PB		 3261{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3262{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3263{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3264{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3265{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3266{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3267{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3268{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3269{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3270{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767
PB		 3271
3272{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3273{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3274{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3275{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3276{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3277{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3278{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3279{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3280
3281{"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}},
3282
3283{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3284{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
9fe54b1c 3285{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
1cb0a767
PB		 3286
3287{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
3288{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
9fe54b1c 3289{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
1cb0a767
PB		 3290
3291{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
3292
e0d602ec 3293{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
1cb0a767
PB		 3294
3295{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3296
3297{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}},
3298{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
3299
3300{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3301{"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3302
3303{"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}},
3304
3305{"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3306
3307{"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3308
9fe54b1c 3309{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476, {0}},
1cb0a767
PB		 3310
3311{"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3312{"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3313
3314{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}},
3315
3316{"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3317
3318{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}},
3319
3320{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3321{"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3322
3323{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}},
3324{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}},
3325
3326{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3327{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3328
3329{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3330{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3331{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3332{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3333{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3334{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3335{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3336{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3337{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3338{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3339{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3340{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3341{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3342{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3343{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3344{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3345{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3346{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3347{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3348{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3349{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3350{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3351{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3352{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3353{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3354{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3355{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3356{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3357{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3358{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3359{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3360{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3361{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3362{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3363{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3364{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3365{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3366{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3367{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3368{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3369{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3370{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3371{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3372{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3373{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3374{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3375{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3376{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3377{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3378{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3379{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3380{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3381{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3382{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3383{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3384{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3385{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3386{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3387{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3388{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3389{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3390{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3391{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3392{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3393{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3394{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3395{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3396{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3397{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3398{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767 3399{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3400{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3401{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3402{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3403{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3404{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3405{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3406{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3407{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3408{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3409{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3410{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3411{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3412{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3413{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3414{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3415{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3416{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3417{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3418{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3419{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3420{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3421{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3422{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3423{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3424{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3425{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3426{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3427{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3428{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3429{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3430{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3431{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3432{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3433{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3434{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3435{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3436{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3437{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3438{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3439{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3440{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3441{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3442{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3443{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3444{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3445{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3446{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3447{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3448{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767
PB		 3449
3450{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3451{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3452{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3453{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3454{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3455{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3456{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3457{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3458{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3459{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767 3460{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3461{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3462{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3463{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3464{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3465{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3466{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3467{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3468{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3469{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767
PB		 3470
3471{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3472{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3473{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3474{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3475{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3476{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3477{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3478{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3479
3480{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3481{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3482
3483{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3484{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3485
3486{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
3487{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
3488{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3489{"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3490{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
3491{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
3492{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3493{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3494
3495{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
3496{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
3497
3498{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3499{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3500{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3501{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3502{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3503{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3504
3505{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}},
3506{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3507{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3508
3509{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3510{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3511
3512{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3513{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3514
3515{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3516{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3517
3518{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3519{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3520
3521{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3522{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3523
3524{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
3525{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
3526{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3527{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
3528{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
3529{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3530
3531{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
3532{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
3533
3534{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3535{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3536
3537{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3538{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3539
3540{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3541{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
3542{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3543{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
3544
3545{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
3546{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
3547
3548{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
3549{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
3550{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
bdc70b4a 3551{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
1cb0a767
PB		 3552
3553{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3554{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3555{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3556{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3557{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3558{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3559{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3560{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3561{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3562{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3563{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3564{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3565{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3566{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3567{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3568{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3569{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3570{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3571{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3572{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3573{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3574{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3575{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3576{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3577{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3578{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3579{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3580{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3581{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}},
3582{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}},
3583{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
3584
3585{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3586{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3587{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3588
3589{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3590{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
81a0b7e2 3591{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
1cb0a767
PB		 3592{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3593{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3594{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
3595
3596{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3597{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3598
3599{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3600{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3601{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3602{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3603
3604{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3605{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3606
3607{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
3608
e0d602ec
BE		 3609{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
3610{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
3611{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
3612{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
858d7a6d 3613
1cb0a767 3614{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
70dc4e32 3615{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
09a8ad8d 3616{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}},
1cb0a767
PB		 3617
3618{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}},
de866fcc 3619
1cb0a767
PB		 3620{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
3621
9fe54b1c 3622{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
1cb0a767
PB		 3623
3624{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
3625{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3626
1cb0a767
PB		 3627{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3628{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
3629{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3630{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
de866fcc 3631
1cb0a767
PB		 3632{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
3633{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
3634{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
3635{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
de866fcc 3636
1cb0a767
PB		 3637{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3638{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
de866fcc 3639
1cb0a767
PB		 3640{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3641{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3642
e0d602ec
BE		 3643{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
3644{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
de866fcc 3645
e0d602ec
BE		 3646{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
3647{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
de866fcc 3648
1cb0a767
PB		 3649{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
3650{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
3651{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
bdc70b4a 3652{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
de866fcc 3653
1cb0a767
PB		 3654{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3655{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3656{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3657
1cb0a767 3658{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
de866fcc 3659
1cb0a767 3660{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
de866fcc 3661
066be9f7
PB		 3662{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
3663
1cb0a767 3664{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
de866fcc 3665
ce3d2015 3666{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE, {RT, RA, RB, CRB}},
de866fcc 3667
1cb0a767
PB		 3668{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3669{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
3670{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3671{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
de866fcc 3672
e0d602ec
BE		 3673{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
3674
066be9f7
PB		 3675{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
3676
1cb0a767 3677{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
de866fcc 3678
1cb0a767 3679{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}},
de866fcc 3680
1cb0a767
PB		 3681{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}},
3682{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3683
1cb0a767
PB		 3684{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
3685{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
de866fcc 3686
1cb0a767
PB		 3687{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3688{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3689
e0d602ec
BE		 3690{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3691{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3692{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2, PPCNONE, {WC}},
19a6653c 3693
e0d602ec 3694{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
19a6653c 3695
1cb0a767
PB		 3696{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3697{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3698{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3699{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3700{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3701{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3702{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3703{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3704{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3705{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3706{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3707{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3708{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3709{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3710{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}},
de866fcc 3711
1cb0a767
PB		 3712{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3713{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3714{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
de866fcc 3715
1cb0a767
PB		 3716{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3717{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
de866fcc 3718
ce3d2015
AM		 3719{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
3720{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
de866fcc 3721
1cb0a767 3722{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
de866fcc 3723
1cb0a767 3724{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}},
de866fcc 3725
1cb0a767 3726{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}},
de866fcc 3727
9fe54b1c 3728{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA, RB}},
1cb0a767 3729{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}},
de866fcc 3730
1cb0a767 3731{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
de866fcc 3732
e0d602ec 3733{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
de866fcc 3734
aea77599
AM		 3735{"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}},
3736
1cb0a767
PB		 3737{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3738{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3739
1cb0a767
PB		 3740{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
3741{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
de866fcc 3742
1cb0a767
PB		 3743{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3744{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
de866fcc 3745
aea77599
AM		 3746{"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
3747
1cb0a767 3748{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
de866fcc 3749
066be9f7
PB		 3750{"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
3751
1cb0a767 3752{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
de866fcc 3753
1cb0a767 3754{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
de866fcc 3755
1cb0a767 3756{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}},
de866fcc 3757
1cb0a767
PB		 3758{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3759{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3760{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3761{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3762
e0d602ec 3763{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
19a6653c 3764
9fe54b1c 3765{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
de866fcc 3766
ce3d2015 3767{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
de866fcc 3768
1cb0a767
PB		 3769{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3770{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3771
1cb0a767
PB		 3772{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3773{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3774{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3775{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3776
1cb0a767
PB		 3777{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3778{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3779{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3780{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3781
aea77599
AM		 3782{"mviwsplt", X(31,142), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
3783
3784{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
de866fcc 3785
1cb0a767 3786{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
09a8ad8d
AM		 3787{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
3788{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
de866fcc 3789
1cb0a767 3790{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}},
de866fcc 3791
e0d602ec
BE		 3792{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
3793{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
3794
1cb0a767 3795{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
de866fcc 3796
1cb0a767 3797{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}},
de866fcc 3798
1cb0a767
PB		 3799{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
3800{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
de866fcc 3801
1cb0a767
PB		 3802{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3803{"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
de866fcc 3804
1cb0a767
PB		 3805{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3806{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
de866fcc 3807
9fe54b1c 3808{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
de866fcc 3809
e0d602ec 3810{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
19a6653c 3811
e0d602ec 3812{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
de866fcc 3813
9fe54b1c 3814{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
de866fcc 3815
ce3d2015 3816{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
de866fcc 3817
1cb0a767
PB		 3818{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3819{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3820
aea77599 3821{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
de866fcc 3822
1cb0a767 3823{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
de866fcc 3824
e0d602ec
BE		 3825{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
3826
1cb0a767 3827{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}},
de866fcc 3828
e0d602ec
BE		 3829{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
3830
1cb0a767
PB		 3831{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}},
3832{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
de866fcc 3833
1cb0a767
PB		 3834{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
3835{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
de866fcc 3836
e0d602ec 3837{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
252b5132 3838
aea77599
AM		 3839{"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
3840
1cb0a767
PB		 3841{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3842{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 3843
1cb0a767
PB		 3844{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3845{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3846{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3847{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3848
1cb0a767
PB		 3849{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3850{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3851{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3852{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 3853
e0d602ec 3854{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}},
19a6653c 3855
bdc70b4a 3856{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
418c1742 3857
e0d602ec
BE		 3858{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
3859
3860{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
3861
1cb0a767 3862{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
252b5132 3863
1cb0a767 3864{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
252b5132 3865
1cb0a767
PB		 3866{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3867{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 3868
1cb0a767
PB		 3869{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3870{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 3871
e0d602ec 3872{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
252b5132 3873
ce3d2015 3874{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
7d5b217e 3875
1cb0a767
PB		 3876{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3877{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
f509565f 3878
1cb0a767
PB		 3879{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3880{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3881{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3882{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3883
1cb0a767
PB		 3884{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3885{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
252b5132 3886
1cb0a767
PB		 3887{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3888{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3889{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3890{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3891
1cb0a767
PB		 3892{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3893{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3894{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3895{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 3896
e0d602ec
BE		 3897{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
3898{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}},
bdc70b4a
AM		 3899{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
3900{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
418c1742 3901
066be9f7 3902{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
80890a61 3903{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
70dc4e32 3904{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}},
418c1742 3905
1cb0a767 3906{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
252b5132 3907
1cb0a767
PB		 3908{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
3909{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 3910
e0d602ec 3911{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}},
066be9f7 3912
e0d602ec 3913{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
19a6653c 3914
ce3d2015 3915{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
e0d602ec 3916{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
252b5132 3917
aea77599
AM		 3918{"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
3919
1cb0a767 3920{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
1ed8e1e4 3921
aea77599
AM		 3922{"lvepxl", X(31,263), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
3923
1cb0a767
PB		 3924{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3925{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3926{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 3927
1cb0a767
PB		 3928{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3929{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3930{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3931{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
418c1742 3932
e0d602ec 3933{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
19a6653c 3934
9fe54b1c 3935{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
418c1742 3936
ce3d2015 3937{"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}},
1cb0a767
PB		 3938
3939{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
3940{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
3941
066be9f7 3942{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
80890a61 3943{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
70dc4e32 3944{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}},
1cb0a767
PB		 3945
3946{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
3947
066be9f7
PB		 3948{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
3949
1cb0a767
PB		 3950{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3951{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3952
e0d602ec 3953{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 3954
3955{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
3956
aea77599
AM		 3957{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
3958{"lvepx", X(31,295), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
3959
ce3d2015 3960{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
1cb0a767
PB		 3961{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
3962
ce3d2015 3963{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA, RB}},
1cb0a767
PB		 3964
3965{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
3966
066be9f7
PB		 3967{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
3968
1cb0a767
PB		 3969{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3970{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3971
e0d602ec 3972{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 3973
3974{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
3975{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
3976{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}},
3977{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}},
3978{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}},
3979{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}},
3980{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}},
3981{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}},
3982{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}},
3983{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}},
3984{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}},
3985{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}},
3986{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}},
3987{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}},
3988{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}},
3989{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}},
3990{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}},
3991{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}},
3992{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}},
3993{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}},
3994{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}},
3995{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}},
3996{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}},
3997{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}},
3998{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}},
3999{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}},
4000{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}},
4001{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}},
4002{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}},
4003{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}},
4004{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}},
4005{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
4006{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
4007{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
ce3d2015 4008{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}},
e0d602ec 4009{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
1cb0a767 4010
aea77599
AM		 4011{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4012
ce3d2015 4013{"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}},
9fe54b1c 4014
1cb0a767
PB		 4015{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4016{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4017
066be9f7
PB		 4018{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
4019
1cb0a767 4020{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
aea77599 4021{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}},
1cb0a767
PB		 4022
4023{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
4024{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}},
ce3d2015
AM		 4025{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
4026{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
1cb0a767
PB		 4027{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
4028{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}},
4029{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}},
4030{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
ce3d2015
AM		 4031{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
4032{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
bdc70b4a 4033{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
1cb0a767 4034{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
ce3d2015 4035{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
1cb0a767
PB		 4036{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
4037{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}},
4038{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}},
4039{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4040{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4041{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4042{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4043{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4044{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4045{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
4046{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
4047{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
4048{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}},
4049{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}},
4050{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}},
4051{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}},
4052{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}},
4053{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}},
4054{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}},
4055{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}},
4056{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}},
4057{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}},
4058{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}},
4059{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}},
4060{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}},
4061{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}},
4062{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4063{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}},
4064{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4065{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4066{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4067{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4068{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4069{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4070{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4071{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}},
4072{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}},
4073{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}},
4074{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}},
4075{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}},
ce3d2015 4076{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
1cb0a767
PB		 4077{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4078{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}},
4079{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4080{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4081{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4082{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4083{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4084{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4085{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4086{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4087{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4088{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4089{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4090{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4091{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4092{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4093{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4094{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4095{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4096{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4097{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4098{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4099{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4100{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4101{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4102{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4103{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4104{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4105{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4106{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4107{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4108{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4109{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4110{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
4111{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
4112{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
ce3d2015 4113{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
1cb0a767 4114{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
ce3d2015 4115{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
1cb0a767
PB		 4116{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4117{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
ce3d2015
AM		 4118{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
4119{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
1cb0a767
PB		 4120{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}},
4121{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}},
4122{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}},
4123{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}},
4124{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}},
4125{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}},
4126{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
4127{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
4128{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
ce3d2015 4129{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
1cb0a767
PB		 4130{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}},
4131{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}},
4132{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}},
4133{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}},
4134{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}},
4135{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}},
4136{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}},
4137{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}},
4138{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}},
4139{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}},
4140{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}},
4141{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}},
4142{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}},
4143{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}},
4144{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}},
4145{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}},
4146{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}},
4147{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}},
4148{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}},
4149{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}},
4150{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}},
4151{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}},
ce3d2015
AM		 4152{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, PPCNONE, {RT}},
4153{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, PPCNONE, {RT}},
4154{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, PPCNONE, {RT}},
4155{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}},
4156{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}},
4157{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}},
4158{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}},
4159{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}},
4160{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}},
4161{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, PPCNONE, {RT}},
1cb0a767
PB		 4162{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}},
4163{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}},
4164{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}},
4165{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}},
4166{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}},
4167{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}},
4168{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}},
4169{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}},
4170{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}},
ce3d2015
AM		 4171{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, PPCNONE, {RT}},
4172{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RT}},
1cb0a767
PB		 4173{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}},
4174{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}},
4175{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}},
4176{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}},
4177{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}},
4178{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}},
4179{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}},
4180{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}},
4181{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}},
4182{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}},
4183{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}},
4184{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}},
4185{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}},
4186{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}},
4187{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}},
4188{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}},
ce3d2015 4189{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE, {RT}},
1cb0a767
PB		 4190{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}},
4191{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}},
4192{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}},
4193{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}},
4194{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}},
4195{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}},
4196{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}},
4197{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}},
4198{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}},
4199{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}},
4200{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}},
4201{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}},
4202{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}},
ce3d2015 4203{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4204{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}},
4205{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}},
4206{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}},
4207{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}},
4208{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}},
4209{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}},
4210{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}},
4211{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}},
4212{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}},
4213{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}},
4214{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}},
4215{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}},
4216{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}},
4217{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
4218{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
4219{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}},
4220
4221{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
4222
4223{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4224
4225{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
4226
4227{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
4228
4229{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4230{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
4231
4232{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4233{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4234
ce3d2015 4235{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
1cb0a767 4236
bdc70b4a
AM		 4237{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}},
4238{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
4239{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}},
1cb0a767
PB		 4240
4241{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
4242
4243{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4244
4245{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
4246
e0d602ec 4247{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
066be9f7 4248
ce3d2015 4249{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
e0d602ec 4250{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
1cb0a767 4251
aea77599
AM		 4252{"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4253
ce3d2015 4254{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
1cb0a767
PB		 4255{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4256
51b5d4a8
AM		 4257{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4258{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4259{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4260{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7 4261
aea77599 4262{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
1cb0a767
PB		 4263
4264{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
4265
2f7f7710
AM		 4266{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
4267{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
e0d602ec 4268
1cb0a767
PB		 4269{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
4270
4271{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4272{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4273
e0d602ec 4274{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
1cb0a767
PB		 4275
4276{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
4277
aea77599
AM		 4278{"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4279
4280{"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
4281
51b5d4a8
AM		 4282{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4283{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4284{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4285{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7 4286
1cb0a767
PB		 4287{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
4288
ce3d2015 4289{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA, RB}},
1cb0a767
PB		 4290
4291{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
4292
4293{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
4294
aea77599
AM		 4295{"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}},
4296
1cb0a767
PB		 4297{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
4298{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4299{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
4300{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4301
4302{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}},
4303{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}},
4304{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}},
4305{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}},
4306{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}},
4307{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}},
4308{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}},
4309{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}},
4310{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}},
4311{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}},
4312{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}},
4313{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}},
4314{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}},
4315{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}},
4316{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}},
4317{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}},
4318{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}},
4319{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}},
4320{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}},
4321{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}},
4322{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}},
4323{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}},
4324{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}},
4325{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}},
4326{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}},
4327{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}},
4328{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}},
4329{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}},
4330{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}},
4331{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}},
4332{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}},
4333{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
4334{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
4335{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
ce3d2015 4336{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}},
e0d602ec 4337{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
1cb0a767 4338
aea77599
AM		 4339{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4340
cee62821 4341{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
9fe54b1c 4342{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
1cb0a767
PB		 4343
4344{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4345{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4346
4347{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4348{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4349
4350{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
aea77599 4351{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}},
1cb0a767
PB		 4352
4353{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
4354{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}},
4355{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}},
ce3d2015 4356{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}},
1cb0a767 4357{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
ce3d2015
AM		 4358{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
4359{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
4360{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
4361{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
1cb0a767
PB		 4362{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}},
4363{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}},
ce3d2015 4364{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
1cb0a767
PB		 4365{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}},
4366{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}},
4367{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}},
4368{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4369{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4370{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4371{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4372{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4373{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4374{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4375{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}},
4376{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}},
4377{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}},
4378{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}},
4379{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}},
4380{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
4381{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
4382{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
4383{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
4384{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
4385{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
4386{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}},
4387{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}},
4388{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}},
4389{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}},
4390{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}},
4391{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}},
4392{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4393{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}},
4394{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}},
4395{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}},
4396{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}},
4397{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}},
4398{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4399{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4400{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4401{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4402{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}},
ce3d2015 4403{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
1cb0a767
PB		 4404{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}},
4405{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}},
4406{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4407{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4408{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4409{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4410{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4411{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4412{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4413{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4414{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4415{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4416{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4417{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4418{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4419{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4420{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4421{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4422{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4423{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4424{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4425{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4426{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4427{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4428{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4429{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4430{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4431{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4432{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4433{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4434{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4435{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4436{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4437{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
4438{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
4439{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
ce3d2015 4440{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
1cb0a767 4441{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
ce3d2015 4442{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
1cb0a767
PB		 4443{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4444{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
ce3d2015
AM		 4445{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
4446{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
1cb0a767
PB		 4447{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
4448{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
4449{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
ce3d2015
AM		 4450{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}},
4451{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}},
4452{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, PPCNONE, {RS}},
4453{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}},
4454{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}},
4455{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4456{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}},
4457{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}},
4458{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}},
4459{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}},
4460{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}},
4461{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}},
4462{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}},
4463{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}},
4464{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}},
ce3d2015
AM		 4465{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, PPCNONE, {RS}},
4466{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4467{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}},
4468{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}},
4469{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}},
4470{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}},
4471{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}},
4472{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}},
4473{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}},
4474{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}},
4475{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}},
4476{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}},
4477{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}},
4478{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}},
4479{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}},
4480{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}},
4481{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}},
4482{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}},
4483{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}},
4484{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}},
4485{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}},
4486{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}},
4487{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}},
4488{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}},
4489{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}},
4490{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}},
4491{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}},
4492{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}},
4493{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}},
4494{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}},
4495{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}},
ce3d2015 4496{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4497{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}},
4498{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}},
4499{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}},
4500{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}},
4501{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}},
4502{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}},
4503{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}},
4504{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}},
4505{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}},
4506{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}},
4507{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}},
4508{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}},
4509{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}},
4510{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}},
4511{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
4512{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
4513{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}},
4514
4515{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}},
4516
4517{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4518{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4519
4520{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
4521
9fe54b1c 4522{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA, RB}},
1cb0a767 4523
ce3d2015 4524{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
1cb0a767
PB		 4525
4526{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
4527
4528{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4529{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
4530
4531{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4532{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4533
4534{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4535{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4536
aea77599 4537{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
1cb0a767
PB		 4538
4539{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}},
4540
4541{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
4542
e0d602ec 4543{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
066be9f7 4544
9fe54b1c 4545{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}},
1cb0a767 4546
066be9f7 4547{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
252b5132 4548
1cb0a767 4549{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4550
1cb0a767 4551{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}},
252b5132 4552
1cb0a767
PB		 4553{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4554{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4555
1cb0a767
PB		 4556{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4557{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
81a0b7e2 4558{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
1cb0a767
PB		 4559{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4560{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
81a0b7e2 4561{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
252b5132 4562
1cb0a767
PB		 4563{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4564{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4565{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4566{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4567
1cb0a767 4568{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
418c1742 4569
e0d602ec 4570{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
418c1742 4571
989993d8 4572{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
1cb0a767 4573{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4574
1cb0a767
PB		 4575{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
4576{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4577
e01d869a 4578{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
702f0fb4 4579
1cb0a767
PB		 4580{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4581{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4582{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4583{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
252b5132 4584
1cb0a767
PB		 4585{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4586{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
23976049 4587
1cb0a767
PB		 4588{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4589{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
f509565f 4590
1cb0a767
PB		 4591{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4592{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4593
1cb0a767 4594{"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4595
aea77599
AM		 4596{"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4597
1cb0a767 4598{"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
418c1742 4599
1cb0a767
PB		 4600{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4601{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4602
1cb0a767
PB		 4603{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4604{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
4605{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4606{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
252b5132 4607
1cb0a767 4608{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}},
252b5132 4609
e01d869a 4610{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 4611
1cb0a767 4612{"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4613
aea77599
AM		 4614{"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4615
1cb0a767 4616{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4617
066be9f7
PB		 4618{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
4619
bdc70b4a 4620{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
252b5132 4621
989993d8 4622{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RA0, NBI}},
1cb0a767 4623{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
252b5132 4624
e01d869a 4625{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
1cb0a767 4626{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
aea77599 4627{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
9fe54b1c
PB		 4628{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
4629{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
aea77599 4630{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
e01d869a 4631{"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
1cb0a767 4632{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
418c1742 4633
e01d869a 4634{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
23976049 4635
066be9f7 4636{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
e0d602ec 4637{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}},
252b5132 4638
1cb0a767 4639{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4640
aea77599
AM		 4641{"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4642
1cb0a767 4643{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4644
1cb0a767
PB		 4645{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
4646{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
252b5132 4647
1cb0a767
PB		 4648{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4649{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4650
81a0b7e2 4651{"mfsri", X(31,627), X_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4652
81a0b7e2 4653{"dclst", X(31,630), XRB_MASK, M601, PPCNONE, {RS, RA}},
252b5132 4654
e01d869a 4655{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 4656
1cb0a767 4657{"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4658
1cb0a767
PB		 4659{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4660{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
23976049 4661
1cb0a767
PB		 4662{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4663{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4664{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4665{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4666
1cb0a767
PB		 4667{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4668{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4669{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4670{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4671
bdc70b4a 4672{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
418c1742 4673
e0d602ec 4674{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
252b5132 4675
f383de66 4676{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
1cb0a767 4677{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
418c1742 4678
1cb0a767
PB		 4679{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
4680{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
252b5132 4681
e01d869a 4682{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
ede602d7 4683
1cb0a767
PB		 4684{"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4685{"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4686
1cb0a767
PB		 4687{"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4688{"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4689
1cb0a767 4690{"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4691
aea77599
AM		 4692{"stvfrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4693
1cb0a767
PB		 4694{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4695{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4696
066be9f7
PB		 4697{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
4698
e01d869a 4699{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 4700
1cb0a767
PB		 4701{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4702{"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4703
1cb0a767 4704{"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4705
aea77599
AM		 4706{"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4707
1cb0a767 4708{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4709
066be9f7
PB		 4710{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
4711
1cb0a767
PB		 4712{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4713{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4714{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4715{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 4716
1cb0a767
PB		 4717{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4718{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4719{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4720{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
fdd12ef3 4721
f383de66 4722{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
1cb0a767 4723{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
252b5132 4724
066be9f7
PB		 4725{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
4726
e01d869a 4727{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
252b5132 4728
1cb0a767
PB		 4729{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4730{"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
418c1742 4731
1cb0a767
PB		 4732{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4733{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4734
066be9f7 4735{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
e0d602ec 4736{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, PPCNONE, {FRS, RA, RB}},
252b5132 4737
1cb0a767 4738{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4739
aea77599
AM		 4740{"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4741
1cb0a767 4742{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4743
1cb0a767
PB		 4744{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4745{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4746{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4747{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 4748
1cb0a767
PB		 4749{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4750{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
252b5132 4751
1cb0a767
PB		 4752{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4753{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4754{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4755{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 4756
1cb0a767
PB		 4757{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4758{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4759{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4760{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
702f0fb4 4761
9fe54b1c 4762{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
1cb0a767 4763{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
252b5132 4764
e01d869a 4765{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 4766
1cb0a767
PB		 4767{"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4768{"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4769
aea77599
AM		 4770{"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4771{"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
1cb0a767
PB		 4772{"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4773{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
ede602d7 4774
1cb0a767
PB		 4775{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4776{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4777
1cb0a767
PB		 4778{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4779{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4780{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4781{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4782
066be9f7
PB		 4783{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
4784
9fe54b1c 4785{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
252b5132 4786
1cb0a767 4787{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4788
1cb0a767 4789{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
252b5132 4790
989993d8 4791{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA, RB}},
c72ab5f2 4792{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
418c1742 4793
1cb0a767
PB		 4794{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4795{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4796{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4797{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
fdd12ef3 4798
1cb0a767
PB		 4799{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4800{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
252b5132 4801
1cb0a767 4802{"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
19a6653c 4803
aea77599
AM		 4804{"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4805{"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
1cb0a767 4806{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
252b5132 4807
81a0b7e2 4808{"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4809
e0d602ec
BE		 4810{"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}},
4811
1cb0a767 4812{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4813
1cb0a767 4814{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}},
252b5132 4815
1cb0a767 4816{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
fdd12ef3 4817
1cb0a767
PB		 4818{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4819{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
4820{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4821{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
702f0fb4 4822
1cb0a767
PB		 4823{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
4824{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
e0c21649 4825
aea77599
AM		 4826{"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4827
1cb0a767
PB		 4828{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4829{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4830
1cb0a767 4831{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
9b4e5766 4832
e0d602ec
BE		 4833{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA, RB}},
4834
1cb0a767 4835{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
252b5132 4836
1cb0a767 4837{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
418c1742 4838
9fe54b1c
PB		 4839{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
4840{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}},
e01d869a 4841{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}},
9fe54b1c 4842{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}},
418c1742 4843
9fe54b1c 4844{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}},
418c1742 4845
aea77599
AM		 4846{"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4847
1cb0a767
PB		 4848{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4849{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
702f0fb4 4850
1cb0a767
PB		 4851{"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4852{"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4853
1cb0a767 4854{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4855
e0d602ec 4856{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}},
066be9f7 4857
1cb0a767
PB		 4858{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4859{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4860
51b5d4a8
AM		 4861{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4862{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4863{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4864{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7
PB		 4865
4866{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
4867
9fe54b1c
PB		 4868{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4869{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
252b5132 4870
1cb0a767 4871{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
702f0fb4 4872
1cb0a767 4873{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
f5c120c5 4874
1cb0a767 4875{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
252b5132 4876
989993d8 4877{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA, RB}},
c72ab5f2 4878{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
6ba045b1 4879
1cb0a767
PB		 4880{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4881{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
702f0fb4 4882
1cb0a767
PB		 4883{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4884{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4885
1cb0a767
PB		 4886{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
4887{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
4888{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
4889{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
702f0fb4 4890
1cb0a767 4891{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
19a6653c 4892
aea77599
AM		 4893{"stvfrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4894
85d4ac0b
AM		 4895{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
4896{"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}},
4897{"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
4898
1cb0a767 4899{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
6ba045b1 4900
51b5d4a8
AM		 4901{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4902{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4903{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4904{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7 4905
e0d602ec
BE		 4906{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
4907{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
9fe54b1c 4908{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
702f0fb4 4909
1cb0a767 4910{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
252b5132 4911
51b5d4a8
AM		 4912{"icswepx", XRC(31,950,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
4913{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
4914
1cb0a767 4915{"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
252b5132 4916
1cb0a767
PB		 4917{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4918{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4919
1cb0a767
PB		 4920{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}},
4921{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
252b5132 4922
aea77599
AM		 4923{"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4924
cee62821 4925{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
9fe54b1c 4926{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
418c1742 4927
1cb0a767
PB		 4928{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4929{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
702f0fb4 4930
1cb0a767
PB		 4931{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4932{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
252b5132 4933
1cb0a767 4934{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
9b4e5766 4935
9fe54b1c 4936{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
1cb0a767
PB		 4937{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
4938{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
9fe54b1c 4939{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
418c1742 4940
1cb0a767 4941{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
252b5132 4942
1cb0a767 4943{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}},
252b5132 4944
e01d869a 4945{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
702f0fb4 4946
1cb0a767
PB		 4947{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
4948{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
252b5132 4949
e0d602ec 4950{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
19a6653c 4951
aea77599
AM		 4952{"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4953
ce3d2015 4954{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
252b5132 4955
1cb0a767
PB		 4956{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4957{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
252b5132 4958
1cb0a767
PB		 4959{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4960{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
418c1742 4961
1cb0a767
PB		 4962{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4963{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
702f0fb4 4964
ce3d2015 4965{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
252b5132 4966
1cb0a767 4967{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
418c1742 4968
1cb0a767
PB		 4969{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
4970{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
786e2c0f 4971
e0d602ec 4972{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
ede602d7 4973
9fe54b1c 4974{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA, RB}},
252b5132 4975
1cb0a767
PB		 4976{"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}},
4977{"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}},
4978{"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}},
252b5132 4979
1cb0a767
PB		 4980{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4981{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4982{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}},
252b5132 4983
1cb0a767
PB		 4984{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}},
4985{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}},
4986{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}},
4987{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}},
252b5132 4988
1cb0a767
PB		 4989{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
4990{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4991
1cb0a767
PB		 4992{"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}},
4993{"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4994
1cb0a767 4995{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 4996
1cb0a767 4997{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 4998
1cb0a767
PB		 4999{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
5000{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 5001
1cb0a767
PB		 5002{"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}},
5003{"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 5004
1cb0a767 5005{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
252b5132 5006
1cb0a767 5007{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
252b5132 5008
1cb0a767 5009{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 5010
1cb0a767 5011{"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 5012
1cb0a767 5013{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 5014
1cb0a767 5015{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 5016
1cb0a767 5017{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
252b5132 5018
1cb0a767 5019{"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
252b5132 5020
1cb0a767
PB		 5021{"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}},
5022{"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 5023
1cb0a767
PB		 5024{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
5025{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 5026
e01d869a 5027{"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
252b5132 5028
e01d869a 5029{"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
252b5132 5030
e01d869a 5031{"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
252b5132 5032
e01d869a 5033{"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
252b5132 5034
e01d869a 5035{"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
adadcc0c 5036
e01d869a 5037{"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
252b5132 5038
e01d869a 5039{"stfd", OP(54), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
c3d65c1c 5040
e01d869a 5041{"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
252b5132 5042
9fe54b1c 5043{"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}},
1cb0a767 5044{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
70dc4e32 5045{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
418c1742 5046
989993d8 5047{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, D, RA0}},
1cb0a767 5048{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
70dc4e32 5049{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
802a735e 5050
1cb0a767
PB		 5051{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
5052{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
5053{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
702f0fb4 5054
1cb0a767
PB		 5055{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5056{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
252b5132 5057
1cb0a767
PB		 5058{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
5059{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
252b5132 5060
e01d869a
AM		 5061{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5062{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
252b5132 5063
e01d869a
AM		 5064{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5065{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
252b5132 5066
e01d869a
AM		 5067{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5068{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
252b5132 5069
ce3d2015
AM		 5070{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
5071{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
252b5132 5072
066be9f7 5073{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5074{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
066be9f7 5075{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5076{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
1ed8e1e4 5077
e01d869a
AM		 5078{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
5079{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
252b5132 5080
066be9f7 5081{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5082{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
066be9f7 5083{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5084{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
252b5132 5085
e01d869a
AM		 5086{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5087{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
252b5132 5088
e01d869a
AM		 5089{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5090{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
252b5132 5091
e01d869a
AM		 5092{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5093{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
702f0fb4 5094
e01d869a
AM		 5095{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5096{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
702f0fb4 5097
1cb0a767
PB		 5098{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5099{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5100
1cb0a767
PB		 5101{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
5102{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
702f0fb4 5103
1cb0a767
PB		 5104{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5105{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 5106
1cb0a767
PB		 5107{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
5108{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
702f0fb4 5109
1cb0a767
PB		 5110{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5111{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 5112
1cb0a767
PB		 5113{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5114{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 5115
1cb0a767 5116{"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 5117
1cb0a767
PB		 5118{"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
5119{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
5120{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
702f0fb4 5121
1cb0a767
PB		 5122{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5123{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 5124
1cb0a767
PB		 5125{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5126{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5127
1cb0a767
PB		 5128{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5129{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5130
1cb0a767
PB		 5131{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
5132{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
702f0fb4 5133
1cb0a767
PB		 5134{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5135{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5136
1cb0a767
PB		 5137{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5138{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5139
1cb0a767
PB		 5140{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5141{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5142
1cb0a767 5143{"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 5144
1cb0a767 5145{"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 5146
1cb0a767
PB		 5147{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5148{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5149
066be9f7
PB		 5150{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5151{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5152
1cb0a767
PB		 5153{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
5154{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
252b5132 5155
e0d602ec
BE		 5156{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5157{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5158
1cb0a767
PB		 5159{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5160{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
8dbcd839 5161
e0d602ec
BE		 5162{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5163{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5164
066be9f7
PB		 5165{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
5166{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
5167{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
1cb0a767 5168{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
066be9f7 5169{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
1cb0a767
PB		 5170{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5171{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
066be9f7
PB		 5172{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5173{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5174{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5175{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5176{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5177{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5178{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5179{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5180{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5181{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5182{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5183{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5184{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5185{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5186{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5187{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5188{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5189{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5190{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5191{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5192{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5193{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5194{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5195{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5196{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5197{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5198{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5199{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5200{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5201{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5202{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5203{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5204{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5205{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5206{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5207{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5208{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5209{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5210{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5211{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5212{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5213{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5214{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5215{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5216{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5217{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5218{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5219{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5220{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5221{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5222{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5223{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5224{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5225{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5226{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5227{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5228{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5229{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5230{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5231{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5232{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5233{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5234{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5235{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5236{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5237{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5238{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5239{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5240{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
5241{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5242{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5243{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5244{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5245{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5246{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5247{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5248{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5249{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5250{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5251{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5252{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5253{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5254{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5255{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5256{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5257{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5258{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5259{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5260{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
5261{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5262{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5263{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5264{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5265{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5266{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5267{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5268{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5269{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5270{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5271{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5272{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5273{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5274{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
1cb0a767
PB		 5275{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
5276{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
066be9f7
PB		 5277{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5278{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5279{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5280{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5281{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5282{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5283{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5284{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5285{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5286{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5287{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5288{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5289{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5290{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5291{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5292{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5293{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5294{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5295{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5296{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5297{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5298{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5299{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5300{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5301{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5302{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5303{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5304{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5305{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
9b4e5766 5306
c72ab5f2 5307{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
70dc4e32 5308{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
418c1742 5309
989993d8 5310{"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, D, RA0}},
c72ab5f2 5311{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
70dc4e32 5312{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
c72ab5f2 5313
1cb0a767
PB		 5314{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}},
5315{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
9fe54b1c 5316{"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}},
fdd12ef3 5317
e01d869a 5318{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
252b5132 5319
989993d8
JB		 5320{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5321{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5322
989993d8
JB		 5323{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
5324{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
702f0fb4 5325
9fe54b1c
PB		 5326{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
5327{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5328
e01d869a
AM		 5329{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5330{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5331
e01d869a 5332{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5333{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
e01d869a 5334{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5335{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
252b5132 5336
e01d869a 5337{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5338{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
e01d869a 5339{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5340{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
252b5132 5341
e01d869a 5342{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5343{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
e01d869a 5344{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5345{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 5346
e01d869a 5347{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5348{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
e01d869a 5349{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5350{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 5351
e01d869a 5352{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5353{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
e01d869a 5354{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5355{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 5356
ce3d2015
AM		 5357{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
5358{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
252b5132 5359
e01d869a
AM		 5360{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5361{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
252b5132 5362
066be9f7 5363{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5364{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
066be9f7 5365{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5366{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
1ed8e1e4 5367
e01d869a 5368{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
1cb0a767 5369{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
e01d869a 5370{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
1cb0a767 5371{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
252b5132 5372
066be9f7 5373{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5374{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
066be9f7 5375{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5376{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
252b5132 5377
e01d869a 5378{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5379{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5380{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5381{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5382
e01d869a 5383{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5384{"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5385{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5386{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5387
e01d869a 5388{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5389{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5390{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5391{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5392
e01d869a 5393{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5394{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5395{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5396{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5397
e01d869a 5398{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
252b5132 5399
989993d8
JB		 5400{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5401{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5402
a08fc942
PB		 5403{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
5404{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
702f0fb4 5405
1cb0a767
PB		 5406{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}},
5407{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}},
252b5132 5408
e01d869a
AM		 5409{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5410{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5411
1cb0a767 5412{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
252b5132 5413
989993d8
JB		 5414{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
5415{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
702f0fb4 5416
989993d8
JB		 5417{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
5418{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
702f0fb4 5419
1cb0a767
PB		 5420{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}},
5421{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}},
252b5132 5422
e01d869a
AM		 5423{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5424{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5425
989993d8
JB		 5426{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
5427{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
702f0fb4 5428
989993d8
JB		 5429{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
5430{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
702f0fb4 5431
066be9f7
PB		 5432{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}},
5433
989993d8 5434{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
702f0fb4 5435
9fe54b1c
PB		 5436{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5437{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5438{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5439{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
252b5132 5440
e01d869a
AM		 5441{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5442{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5443
066be9f7
PB		 5444{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5445{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5446{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5447{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5448
5449{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}},
5450
a08fc942 5451{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
989993d8
JB		 5452{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}},
5453{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}},
702f0fb4 5454
989993d8
JB		 5455{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
5456{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
702f0fb4 5457
a08fc942
PB		 5458{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
5459{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
702f0fb4 5460
e01d869a
AM		 5461{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5462{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5463
a08fc942
PB		 5464{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
5465{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
702f0fb4 5466
989993d8
JB		 5467{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
5468{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
702f0fb4 5469
a08fc942
PB		 5470{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
5471{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
702f0fb4 5472
1cb0a767
PB		 5473{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5474{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5475{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5476{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5477{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5478{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5479{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5480{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
ce7a772b 5481
989993d8
JB		 5482{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5483{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5484
989993d8
JB		 5485{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5486{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5487
e01d869a
AM		 5488{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}},
5489{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}},
252b5132 5490
989993d8 5491{"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
702f0fb4 5492
a08fc942 5493{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}},
702f0fb4 5494
9fe54b1c 5495{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
e01d869a 5496{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
9fe54b1c 5497{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
e01d869a 5498{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
252b5132 5499
989993d8
JB		 5500{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
5501{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
702f0fb4 5502
a08fc942
PB		 5503{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
5504{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
702f0fb4 5505
1cb0a767 5506{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5507{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
1cb0a767 5508{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5509{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
252b5132 5510
1cb0a767 5511{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5512{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
1cb0a767 5513{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5514{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
252b5132 5515
989993d8
JB		 5516{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
5517{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
702f0fb4 5518
1cb0a767 5519{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5520{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
1cb0a767 5521{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5522{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
252b5132 5523
a08fc942
PB		 5524{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
5525{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
702f0fb4 5526
e0d602ec
BE		 5527{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5528{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5529
e0d602ec
BE		 5530{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5531{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5532
e0d602ec
BE		 5533{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5534{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
252b5132
RH		 5535};
5536
5537const int powerpc_num_opcodes =
5538 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5539\f
5540/* The macro table. This is only used by the assembler. */
5541
5542/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5543 when x=0; 32-x when x is between 1 and 31; are negative if x is
5544 negative; and are 32 or more otherwise. This is what you want
5545 when, for instance, you are emulating a right shift by a
5546 rotate-left-and-mask, because the underlying instructions support
5547 shifts of size 0 but not shifts of size 32. By comparison, when
5548 extracting x bits from some word you want to use just 32-x, because
5549 the underlying instructions don't support extracting 0 bits but do
5550 support extracting the whole word (32 bits in this case). */
5551
5552const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 5553{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
5554{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
bdc7fcfe
AM		 5555{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5556{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
de866fcc
AM		 5557{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
5558{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5559{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5560{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5561{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
5562{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
5563{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5564{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5565{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
5566{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
5567{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
5568{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
5569
5570{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5571{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5572{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5573{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5574{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5575{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5576{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5577{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5578{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5579{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5580{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5581{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5582{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5583{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5584{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5585{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5586{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5587{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5588{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5589{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5590{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5591{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 5592};
5593
5594const int powerpc_num_macros =
5595 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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