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1 | /* RISC-V disassembler |
2 | Copyright 2011-2016 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of the GNU opcodes library. | |
8 | ||
9 | This library is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | It is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "sysdep.h" | |
24 | #include "dis-asm.h" | |
25 | #include "libiberty.h" | |
26 | #include "opcode/riscv.h" | |
27 | #include "opintl.h" | |
28 | #include "elf-bfd.h" | |
29 | #include "elf/riscv.h" | |
30 | ||
31 | #include <stdint.h> | |
32 | #include <ctype.h> | |
33 | ||
34 | struct riscv_private_data | |
35 | { | |
36 | bfd_vma gp; | |
37 | bfd_vma print_addr; | |
38 | bfd_vma hi_addr[OP_MASK_RD + 1]; | |
39 | }; | |
40 | ||
41 | static const char * const *riscv_gpr_names; | |
42 | static const char * const *riscv_fpr_names; | |
43 | ||
44 | /* Other options. */ | |
45 | static int no_aliases; /* If set disassemble as most general inst. */ | |
46 | ||
47 | static void | |
48 | set_default_riscv_dis_options (void) | |
49 | { | |
50 | riscv_gpr_names = riscv_gpr_names_abi; | |
51 | riscv_fpr_names = riscv_fpr_names_abi; | |
52 | no_aliases = 0; | |
53 | } | |
54 | ||
55 | static void | |
56 | parse_riscv_dis_option (const char *option) | |
57 | { | |
58 | if (strcmp (option, "no-aliases") == 0) | |
59 | no_aliases = 1; | |
60 | else if (strcmp (option, "numeric") == 0) | |
61 | { | |
62 | riscv_gpr_names = riscv_gpr_names_numeric; | |
63 | riscv_fpr_names = riscv_fpr_names_numeric; | |
64 | } | |
65 | else | |
66 | { | |
67 | /* Invalid option. */ | |
68 | fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option); | |
69 | } | |
70 | } | |
71 | ||
72 | static void | |
73 | parse_riscv_dis_options (const char *opts_in) | |
74 | { | |
75 | char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; | |
76 | ||
77 | set_default_riscv_dis_options (); | |
78 | ||
79 | for ( ; opt_end != NULL; opt = opt_end + 1) | |
80 | { | |
81 | if ((opt_end = strchr (opt, ',')) != NULL) | |
82 | *opt_end = 0; | |
83 | parse_riscv_dis_option (opt); | |
84 | } | |
85 | ||
86 | free (opts); | |
87 | } | |
88 | ||
89 | /* Print one argument from an array. */ | |
90 | ||
91 | static void | |
92 | arg_print (struct disassemble_info *info, unsigned long val, | |
93 | const char* const* array, size_t size) | |
94 | { | |
95 | const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; | |
96 | (*info->fprintf_func) (info->stream, "%s", s); | |
97 | } | |
98 | ||
99 | static void | |
100 | maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) | |
101 | { | |
102 | if (pd->hi_addr[base_reg] != (bfd_vma)-1) | |
103 | { | |
104 | pd->print_addr = pd->hi_addr[base_reg] + offset; | |
105 | pd->hi_addr[base_reg] = -1; | |
106 | } | |
107 | else if (base_reg == X_GP && pd->gp != (bfd_vma)-1) | |
108 | pd->print_addr = pd->gp + offset; | |
109 | else if (base_reg == X_TP || base_reg == 0) | |
110 | pd->print_addr = offset; | |
111 | } | |
112 | ||
113 | /* Print insn arguments for 32/64-bit code. */ | |
114 | ||
115 | static void | |
116 | print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) | |
117 | { | |
118 | struct riscv_private_data *pd = info->private_data; | |
119 | int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; | |
120 | int rd = (l >> OP_SH_RD) & OP_MASK_RD; | |
121 | fprintf_ftype print = info->fprintf_func; | |
122 | ||
123 | if (*d != '\0') | |
124 | print (info->stream, "\t"); | |
125 | ||
126 | for (; *d != '\0'; d++) | |
127 | { | |
128 | switch (*d) | |
129 | { | |
130 | case 'C': /* RVC */ | |
131 | switch (*++d) | |
132 | { | |
133 | case 's': /* RS1 x8-x15 */ | |
134 | case 'w': /* RS1 x8-x15 */ | |
135 | print (info->stream, "%s", | |
136 | riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); | |
137 | break; | |
138 | case 't': /* RS2 x8-x15 */ | |
139 | case 'x': /* RS2 x8-x15 */ | |
140 | print (info->stream, "%s", | |
141 | riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); | |
142 | break; | |
143 | case 'U': /* RS1, constrained to equal RD */ | |
144 | print (info->stream, "%s", riscv_gpr_names[rd]); | |
145 | break; | |
146 | case 'c': /* RS1, constrained to equal sp */ | |
147 | print (info->stream, "%s", riscv_gpr_names[X_SP]); | |
148 | break; | |
149 | case 'V': /* RS2 */ | |
150 | print (info->stream, "%s", | |
151 | riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]); | |
152 | break; | |
153 | case 'i': | |
154 | print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); | |
155 | break; | |
156 | case 'j': | |
157 | print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); | |
158 | break; | |
159 | case 'k': | |
160 | print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l)); | |
161 | break; | |
162 | case 'l': | |
163 | print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l)); | |
164 | break; | |
165 | case 'm': | |
166 | print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l)); | |
167 | break; | |
168 | case 'n': | |
169 | print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l)); | |
170 | break; | |
171 | case 'K': | |
172 | print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l)); | |
173 | break; | |
174 | case 'L': | |
175 | print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l)); | |
176 | break; | |
177 | case 'M': | |
178 | print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l)); | |
179 | break; | |
180 | case 'N': | |
181 | print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l)); | |
182 | break; | |
183 | case 'p': | |
184 | info->target = EXTRACT_RVC_B_IMM (l) + pc; | |
185 | (*info->print_address_func) (info->target, info); | |
186 | break; | |
187 | case 'a': | |
188 | info->target = EXTRACT_RVC_J_IMM (l) + pc; | |
189 | (*info->print_address_func) (info->target, info); | |
190 | break; | |
191 | case 'u': | |
192 | print (info->stream, "0x%x", | |
193 | (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1))); | |
194 | break; | |
195 | case '>': | |
196 | print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f); | |
197 | break; | |
198 | case '<': | |
199 | print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f); | |
200 | break; | |
201 | case 'T': /* floating-point RS2 */ | |
202 | print (info->stream, "%s", | |
203 | riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]); | |
204 | break; | |
205 | case 'D': /* floating-point RS2 x8-x15 */ | |
206 | print (info->stream, "%s", | |
207 | riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); | |
208 | break; | |
209 | } | |
210 | break; | |
211 | ||
212 | case ',': | |
213 | case '(': | |
214 | case ')': | |
215 | case '[': | |
216 | case ']': | |
217 | print (info->stream, "%c", *d); | |
218 | break; | |
219 | ||
220 | case '0': | |
221 | /* Only print constant 0 if it is the last argument */ | |
222 | if (!d[1]) | |
223 | print (info->stream, "0"); | |
224 | break; | |
225 | ||
226 | case 'b': | |
227 | case 's': | |
228 | print (info->stream, "%s", riscv_gpr_names[rs1]); | |
229 | break; | |
230 | ||
231 | case 't': | |
232 | print (info->stream, "%s", | |
233 | riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); | |
234 | break; | |
235 | ||
236 | case 'u': | |
237 | print (info->stream, "0x%x", | |
238 | (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); | |
239 | break; | |
240 | ||
241 | case 'm': | |
242 | arg_print (info, EXTRACT_OPERAND (RM, l), | |
243 | riscv_rm, ARRAY_SIZE (riscv_rm)); | |
244 | break; | |
245 | ||
246 | case 'P': | |
247 | arg_print (info, EXTRACT_OPERAND (PRED, l), | |
248 | riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); | |
249 | break; | |
250 | ||
251 | case 'Q': | |
252 | arg_print (info, EXTRACT_OPERAND (SUCC, l), | |
253 | riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); | |
254 | break; | |
255 | ||
256 | case 'o': | |
257 | maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); | |
258 | case 'j': | |
259 | if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) | |
260 | || (l & MASK_JALR) == MATCH_JALR) | |
261 | maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); | |
262 | print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l)); | |
263 | break; | |
264 | ||
265 | case 'q': | |
266 | maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); | |
267 | print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); | |
268 | break; | |
269 | ||
270 | case 'a': | |
271 | info->target = EXTRACT_UJTYPE_IMM (l) + pc; | |
272 | (*info->print_address_func) (info->target, info); | |
273 | break; | |
274 | ||
275 | case 'p': | |
276 | info->target = EXTRACT_SBTYPE_IMM (l) + pc; | |
277 | (*info->print_address_func) (info->target, info); | |
278 | break; | |
279 | ||
280 | case 'd': | |
281 | if ((l & MASK_AUIPC) == MATCH_AUIPC) | |
282 | pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l); | |
283 | else if ((l & MASK_LUI) == MATCH_LUI) | |
284 | pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); | |
285 | else if ((l & MASK_C_LUI) == MATCH_C_LUI) | |
286 | pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l); | |
287 | print (info->stream, "%s", riscv_gpr_names[rd]); | |
288 | break; | |
289 | ||
290 | case 'z': | |
291 | print (info->stream, "%s", riscv_gpr_names[0]); | |
292 | break; | |
293 | ||
294 | case '>': | |
295 | print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l)); | |
296 | break; | |
297 | ||
298 | case '<': | |
299 | print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l)); | |
300 | break; | |
301 | ||
302 | case 'S': | |
303 | case 'U': | |
304 | print (info->stream, "%s", riscv_fpr_names[rs1]); | |
305 | break; | |
306 | ||
307 | case 'T': | |
308 | print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]); | |
309 | break; | |
310 | ||
311 | case 'D': | |
312 | print (info->stream, "%s", riscv_fpr_names[rd]); | |
313 | break; | |
314 | ||
315 | case 'R': | |
316 | print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]); | |
317 | break; | |
318 | ||
319 | case 'E': | |
320 | { | |
321 | const char* csr_name = NULL; | |
322 | unsigned int csr = EXTRACT_OPERAND (CSR, l); | |
323 | switch (csr) | |
324 | { | |
325 | #define DECLARE_CSR(name, num) case num: csr_name = #name; break; | |
326 | #include "opcode/riscv-opc.h" | |
327 | #undef DECLARE_CSR | |
328 | } | |
329 | if (csr_name) | |
330 | print (info->stream, "%s", csr_name); | |
331 | else | |
332 | print (info->stream, "0x%x", csr); | |
333 | break; | |
334 | } | |
335 | ||
336 | case 'Z': | |
337 | print (info->stream, "%d", rs1); | |
338 | break; | |
339 | ||
340 | default: | |
341 | /* xgettext:c-format */ | |
342 | print (info->stream, _("# internal error, undefined modifier (%c)"), | |
343 | *d); | |
344 | return; | |
345 | } | |
346 | } | |
347 | } | |
348 | ||
349 | /* Print the RISC-V instruction at address MEMADDR in debugged memory, | |
350 | on using INFO. Returns length of the instruction, in bytes. | |
351 | BIGENDIAN must be 1 if this is big-endian code, 0 if | |
352 | this is little-endian code. */ | |
353 | ||
354 | static int | |
355 | riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) | |
356 | { | |
357 | const struct riscv_opcode *op; | |
358 | static bfd_boolean init = 0; | |
359 | static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; | |
360 | struct riscv_private_data *pd; | |
361 | int insnlen; | |
362 | ||
363 | #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) | |
364 | ||
365 | /* Build a hash table to shorten the search time. */ | |
366 | if (! init) | |
367 | { | |
368 | for (op = riscv_opcodes; op->name; op++) | |
369 | if (!riscv_hash[OP_HASH_IDX (op->match)]) | |
370 | riscv_hash[OP_HASH_IDX (op->match)] = op; | |
371 | ||
372 | init = 1; | |
373 | } | |
374 | ||
375 | if (info->private_data == NULL) | |
376 | { | |
377 | int i; | |
378 | ||
379 | pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); | |
380 | pd->gp = -1; | |
381 | pd->print_addr = -1; | |
382 | for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) | |
383 | pd->hi_addr[i] = -1; | |
384 | ||
385 | for (i = 0; i < info->symtab_size; i++) | |
386 | if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0) | |
387 | pd->gp = bfd_asymbol_value (info->symtab[i]); | |
388 | } | |
389 | else | |
390 | pd = info->private_data; | |
391 | ||
392 | insnlen = riscv_insn_length (word); | |
393 | ||
394 | info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; | |
395 | info->bytes_per_line = 8; | |
396 | info->display_endian = info->endian; | |
397 | info->insn_info_valid = 1; | |
398 | info->branch_delay_insns = 0; | |
399 | info->data_size = 0; | |
400 | info->insn_type = dis_nonbranch; | |
401 | info->target = 0; | |
402 | info->target2 = 0; | |
403 | ||
404 | op = riscv_hash[OP_HASH_IDX (word)]; | |
405 | if (op != NULL) | |
406 | { | |
407 | int xlen = 0; | |
408 | ||
409 | /* The incoming section might not always be complete. */ | |
410 | if (info->section != NULL) | |
411 | { | |
412 | Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); | |
413 | xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; | |
414 | } | |
415 | ||
416 | for (; op->name; op++) | |
417 | { | |
418 | /* Does the opcode match? */ | |
419 | if (! (op->match_func) (op, word)) | |
420 | continue; | |
421 | /* Is this a pseudo-instruction and may we print it as such? */ | |
422 | if (no_aliases && (op->pinfo & INSN_ALIAS)) | |
423 | continue; | |
424 | /* Is this instruction restricted to a certain value of XLEN? */ | |
425 | if (isdigit (op->subset[0]) && atoi (op->subset) != xlen) | |
426 | continue; | |
427 | ||
428 | /* It's a match. */ | |
429 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
430 | print_insn_args (op->args, word, memaddr, info); | |
431 | ||
432 | /* Try to disassemble multi-instruction addressing sequences. */ | |
433 | if (pd->print_addr != (bfd_vma)-1) | |
434 | { | |
435 | info->target = pd->print_addr; | |
436 | (*info->fprintf_func) (info->stream, " # "); | |
437 | (*info->print_address_func) (info->target, info); | |
438 | pd->print_addr = -1; | |
439 | } | |
440 | ||
441 | return insnlen; | |
442 | } | |
443 | } | |
444 | ||
445 | /* We did not find a match, so just print the instruction bits. */ | |
446 | info->insn_type = dis_noninsn; | |
447 | (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word); | |
448 | return insnlen; | |
449 | } | |
450 | ||
451 | int | |
452 | print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) | |
453 | { | |
454 | bfd_byte packet[2]; | |
455 | insn_t insn = 0; | |
456 | bfd_vma n; | |
457 | int status; | |
458 | ||
459 | if (info->disassembler_options != NULL) | |
460 | { | |
461 | parse_riscv_dis_options (info->disassembler_options); | |
462 | /* Avoid repeatedly parsing the options. */ | |
463 | info->disassembler_options = NULL; | |
464 | } | |
465 | else if (riscv_gpr_names == NULL) | |
466 | set_default_riscv_dis_options (); | |
467 | ||
468 | /* Instructions are a sequence of 2-byte packets in little-endian order. */ | |
469 | for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2) | |
470 | { | |
471 | status = (*info->read_memory_func) (memaddr + n, packet, 2, info); | |
472 | if (status != 0) | |
473 | { | |
474 | /* Don't fail just because we fell off the end. */ | |
475 | if (n > 0) | |
476 | break; | |
477 | (*info->memory_error_func) (status, memaddr, info); | |
478 | return status; | |
479 | } | |
480 | ||
481 | insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n); | |
482 | } | |
483 | ||
484 | return riscv_disassemble_insn (memaddr, insn, info); | |
485 | } | |
486 | ||
487 | void | |
488 | print_riscv_disassembler_options (FILE *stream) | |
489 | { | |
490 | fprintf (stream, _("\n\ | |
491 | The following RISC-V-specific disassembler options are supported for use\n\ | |
492 | with the -M switch (multiple options should be separated by commas):\n")); | |
493 | ||
494 | fprintf (stream, _("\n\ | |
495 | numeric Print numeric reigster names, rather than ABI names.\n")); | |
496 | ||
497 | fprintf (stream, _("\n\ | |
498 | no-aliases Disassemble only into canonical instructions, rather\n\ | |
499 | than into pseudoinstructions.\n")); | |
500 | ||
501 | fprintf (stream, _("\n")); | |
502 | } |