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e23eba97 | 1 | /* RISC-V disassembler |
b3adc24a | 2 | Copyright (C) 2011-2020 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of the GNU opcodes library. | |
8 | ||
9 | This library is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | It is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "sysdep.h" | |
88c1242d | 24 | #include "disassemble.h" |
e23eba97 NC |
25 | #include "libiberty.h" |
26 | #include "opcode/riscv.h" | |
27 | #include "opintl.h" | |
28 | #include "elf-bfd.h" | |
29 | #include "elf/riscv.h" | |
39ff0b81 | 30 | #include "elfxx-riscv.h" |
e23eba97 | 31 | |
2d5d5a8f | 32 | #include "bfd_stdint.h" |
e23eba97 NC |
33 | #include <ctype.h> |
34 | ||
8f595e9b NC |
35 | static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; |
36 | ||
e23eba97 NC |
37 | struct riscv_private_data |
38 | { | |
39 | bfd_vma gp; | |
40 | bfd_vma print_addr; | |
41 | bfd_vma hi_addr[OP_MASK_RD + 1]; | |
42 | }; | |
43 | ||
44 | static const char * const *riscv_gpr_names; | |
45 | static const char * const *riscv_fpr_names; | |
46 | ||
47 | /* Other options. */ | |
48 | static int no_aliases; /* If set disassemble as most general inst. */ | |
49 | ||
50 | static void | |
51 | set_default_riscv_dis_options (void) | |
52 | { | |
53 | riscv_gpr_names = riscv_gpr_names_abi; | |
54 | riscv_fpr_names = riscv_fpr_names_abi; | |
55 | no_aliases = 0; | |
56 | } | |
57 | ||
8f595e9b NC |
58 | static bfd_boolean |
59 | parse_riscv_dis_option_without_args (const char *option) | |
e23eba97 NC |
60 | { |
61 | if (strcmp (option, "no-aliases") == 0) | |
62 | no_aliases = 1; | |
63 | else if (strcmp (option, "numeric") == 0) | |
64 | { | |
65 | riscv_gpr_names = riscv_gpr_names_numeric; | |
66 | riscv_fpr_names = riscv_fpr_names_numeric; | |
67 | } | |
8f595e9b NC |
68 | else |
69 | return FALSE; | |
70 | return TRUE; | |
71 | } | |
72 | ||
73 | static void | |
74 | parse_riscv_dis_option (const char *option) | |
75 | { | |
76 | char *equal, *value; | |
77 | ||
78 | if (parse_riscv_dis_option_without_args (option)) | |
79 | return; | |
80 | ||
81 | equal = strchr (option, '='); | |
82 | if (equal == NULL) | |
83 | { | |
84 | /* The option without '=' should be defined above. */ | |
85 | opcodes_error_handler (_("unrecognized disassembler option: %s"), option); | |
86 | return; | |
87 | } | |
88 | if (equal == option | |
89 | || *(equal + 1) == '\0') | |
90 | { | |
91 | /* Invalid options with '=', no option name before '=', | |
92 | and no value after '='. */ | |
93 | opcodes_error_handler (_("unrecognized disassembler option with '=': %s"), | |
94 | option); | |
95 | return; | |
96 | } | |
97 | ||
98 | *equal = '\0'; | |
99 | value = equal + 1; | |
100 | if (strcmp (option, "priv-spec") == 0) | |
101 | { | |
102 | if (!riscv_get_priv_spec_class (value, &default_priv_spec)) | |
103 | opcodes_error_handler (_("unknown privilege spec set by %s=%s"), | |
104 | option, value); | |
105 | } | |
e23eba97 NC |
106 | else |
107 | { | |
a6743a54 AM |
108 | /* xgettext:c-format */ |
109 | opcodes_error_handler (_("unrecognized disassembler option: %s"), option); | |
e23eba97 NC |
110 | } |
111 | } | |
112 | ||
113 | static void | |
114 | parse_riscv_dis_options (const char *opts_in) | |
115 | { | |
116 | char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; | |
117 | ||
118 | set_default_riscv_dis_options (); | |
119 | ||
120 | for ( ; opt_end != NULL; opt = opt_end + 1) | |
121 | { | |
122 | if ((opt_end = strchr (opt, ',')) != NULL) | |
123 | *opt_end = 0; | |
124 | parse_riscv_dis_option (opt); | |
125 | } | |
126 | ||
127 | free (opts); | |
128 | } | |
129 | ||
130 | /* Print one argument from an array. */ | |
131 | ||
132 | static void | |
133 | arg_print (struct disassemble_info *info, unsigned long val, | |
134 | const char* const* array, size_t size) | |
135 | { | |
136 | const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; | |
137 | (*info->fprintf_func) (info->stream, "%s", s); | |
138 | } | |
139 | ||
140 | static void | |
141 | maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) | |
142 | { | |
143 | if (pd->hi_addr[base_reg] != (bfd_vma)-1) | |
144 | { | |
35fd2b2b | 145 | pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset; |
e23eba97 NC |
146 | pd->hi_addr[base_reg] = -1; |
147 | } | |
148 | else if (base_reg == X_GP && pd->gp != (bfd_vma)-1) | |
149 | pd->print_addr = pd->gp + offset; | |
150 | else if (base_reg == X_TP || base_reg == 0) | |
151 | pd->print_addr = offset; | |
152 | } | |
153 | ||
154 | /* Print insn arguments for 32/64-bit code. */ | |
155 | ||
156 | static void | |
157 | print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) | |
158 | { | |
159 | struct riscv_private_data *pd = info->private_data; | |
160 | int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; | |
161 | int rd = (l >> OP_SH_RD) & OP_MASK_RD; | |
162 | fprintf_ftype print = info->fprintf_func; | |
163 | ||
164 | if (*d != '\0') | |
165 | print (info->stream, "\t"); | |
166 | ||
167 | for (; *d != '\0'; d++) | |
168 | { | |
169 | switch (*d) | |
170 | { | |
171 | case 'C': /* RVC */ | |
172 | switch (*++d) | |
173 | { | |
174 | case 's': /* RS1 x8-x15 */ | |
175 | case 'w': /* RS1 x8-x15 */ | |
176 | print (info->stream, "%s", | |
177 | riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); | |
178 | break; | |
179 | case 't': /* RS2 x8-x15 */ | |
180 | case 'x': /* RS2 x8-x15 */ | |
181 | print (info->stream, "%s", | |
182 | riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); | |
183 | break; | |
184 | case 'U': /* RS1, constrained to equal RD */ | |
185 | print (info->stream, "%s", riscv_gpr_names[rd]); | |
186 | break; | |
187 | case 'c': /* RS1, constrained to equal sp */ | |
188 | print (info->stream, "%s", riscv_gpr_names[X_SP]); | |
189 | break; | |
190 | case 'V': /* RS2 */ | |
191 | print (info->stream, "%s", | |
192 | riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]); | |
193 | break; | |
194 | case 'i': | |
195 | print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); | |
196 | break; | |
f91d48de | 197 | case 'o': |
e23eba97 NC |
198 | case 'j': |
199 | print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); | |
200 | break; | |
201 | case 'k': | |
202 | print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l)); | |
203 | break; | |
204 | case 'l': | |
205 | print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l)); | |
206 | break; | |
207 | case 'm': | |
208 | print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l)); | |
209 | break; | |
210 | case 'n': | |
211 | print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l)); | |
212 | break; | |
213 | case 'K': | |
214 | print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l)); | |
215 | break; | |
216 | case 'L': | |
217 | print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l)); | |
218 | break; | |
219 | case 'M': | |
220 | print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l)); | |
221 | break; | |
222 | case 'N': | |
223 | print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l)); | |
224 | break; | |
225 | case 'p': | |
226 | info->target = EXTRACT_RVC_B_IMM (l) + pc; | |
227 | (*info->print_address_func) (info->target, info); | |
228 | break; | |
229 | case 'a': | |
230 | info->target = EXTRACT_RVC_J_IMM (l) + pc; | |
231 | (*info->print_address_func) (info->target, info); | |
232 | break; | |
233 | case 'u': | |
234 | print (info->stream, "0x%x", | |
235 | (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1))); | |
236 | break; | |
237 | case '>': | |
238 | print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f); | |
239 | break; | |
240 | case '<': | |
241 | print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f); | |
242 | break; | |
243 | case 'T': /* floating-point RS2 */ | |
244 | print (info->stream, "%s", | |
245 | riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]); | |
246 | break; | |
247 | case 'D': /* floating-point RS2 x8-x15 */ | |
248 | print (info->stream, "%s", | |
249 | riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); | |
250 | break; | |
251 | } | |
252 | break; | |
253 | ||
254 | case ',': | |
255 | case '(': | |
256 | case ')': | |
257 | case '[': | |
258 | case ']': | |
259 | print (info->stream, "%c", *d); | |
260 | break; | |
261 | ||
262 | case '0': | |
263 | /* Only print constant 0 if it is the last argument */ | |
264 | if (!d[1]) | |
265 | print (info->stream, "0"); | |
266 | break; | |
267 | ||
268 | case 'b': | |
269 | case 's': | |
35eeb78f JW |
270 | if ((l & MASK_JALR) == MATCH_JALR) |
271 | maybe_print_address (pd, rs1, 0); | |
e23eba97 NC |
272 | print (info->stream, "%s", riscv_gpr_names[rs1]); |
273 | break; | |
274 | ||
275 | case 't': | |
276 | print (info->stream, "%s", | |
277 | riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); | |
278 | break; | |
279 | ||
280 | case 'u': | |
281 | print (info->stream, "0x%x", | |
282 | (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); | |
283 | break; | |
284 | ||
285 | case 'm': | |
286 | arg_print (info, EXTRACT_OPERAND (RM, l), | |
287 | riscv_rm, ARRAY_SIZE (riscv_rm)); | |
288 | break; | |
289 | ||
290 | case 'P': | |
291 | arg_print (info, EXTRACT_OPERAND (PRED, l), | |
292 | riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); | |
293 | break; | |
294 | ||
295 | case 'Q': | |
296 | arg_print (info, EXTRACT_OPERAND (SUCC, l), | |
297 | riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); | |
298 | break; | |
299 | ||
300 | case 'o': | |
301 | maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); | |
b52d3cfc | 302 | /* Fall through. */ |
e23eba97 NC |
303 | case 'j': |
304 | if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) | |
305 | || (l & MASK_JALR) == MATCH_JALR) | |
306 | maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); | |
307 | print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l)); | |
308 | break; | |
309 | ||
310 | case 'q': | |
311 | maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); | |
312 | print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); | |
313 | break; | |
314 | ||
315 | case 'a': | |
316 | info->target = EXTRACT_UJTYPE_IMM (l) + pc; | |
317 | (*info->print_address_func) (info->target, info); | |
318 | break; | |
319 | ||
320 | case 'p': | |
321 | info->target = EXTRACT_SBTYPE_IMM (l) + pc; | |
322 | (*info->print_address_func) (info->target, info); | |
323 | break; | |
324 | ||
325 | case 'd': | |
326 | if ((l & MASK_AUIPC) == MATCH_AUIPC) | |
327 | pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l); | |
328 | else if ((l & MASK_LUI) == MATCH_LUI) | |
329 | pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); | |
330 | else if ((l & MASK_C_LUI) == MATCH_C_LUI) | |
331 | pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l); | |
332 | print (info->stream, "%s", riscv_gpr_names[rd]); | |
333 | break; | |
334 | ||
335 | case 'z': | |
336 | print (info->stream, "%s", riscv_gpr_names[0]); | |
337 | break; | |
338 | ||
339 | case '>': | |
340 | print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l)); | |
341 | break; | |
342 | ||
343 | case '<': | |
344 | print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l)); | |
345 | break; | |
346 | ||
347 | case 'S': | |
348 | case 'U': | |
349 | print (info->stream, "%s", riscv_fpr_names[rs1]); | |
350 | break; | |
351 | ||
352 | case 'T': | |
353 | print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]); | |
354 | break; | |
355 | ||
356 | case 'D': | |
357 | print (info->stream, "%s", riscv_fpr_names[rd]); | |
358 | break; | |
359 | ||
360 | case 'R': | |
361 | print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]); | |
362 | break; | |
363 | ||
364 | case 'E': | |
365 | { | |
8f595e9b NC |
366 | static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR. */ |
367 | static bfd_boolean init_csr = FALSE; | |
e23eba97 | 368 | unsigned int csr = EXTRACT_OPERAND (CSR, l); |
8f595e9b NC |
369 | |
370 | if (!init_csr) | |
e23eba97 | 371 | { |
8f595e9b NC |
372 | unsigned int i; |
373 | for (i = 0; i < 4096; i++) | |
374 | riscv_csr_hash[i] = NULL; | |
375 | ||
376 | /* Set to the newest privilege version. */ | |
377 | if (default_priv_spec == PRIV_SPEC_CLASS_NONE) | |
378 | default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1; | |
379 | ||
08ccfccf NC |
380 | #define DECLARE_CSR(name, num, class, define_version, abort_version) \ |
381 | if (riscv_csr_hash[num] == NULL \ | |
382 | && ((define_version == PRIV_SPEC_CLASS_NONE \ | |
383 | && abort_version == PRIV_SPEC_CLASS_NONE) \ | |
384 | || (default_priv_spec >= define_version \ | |
385 | && default_priv_spec < abort_version))) \ | |
8f595e9b NC |
386 | riscv_csr_hash[num] = #name; |
387 | #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \ | |
388 | DECLARE_CSR (name, num, class, define_version, abort_version) | |
e23eba97 NC |
389 | #include "opcode/riscv-opc.h" |
390 | #undef DECLARE_CSR | |
391 | } | |
8f595e9b NC |
392 | |
393 | if (riscv_csr_hash[csr] != NULL) | |
394 | print (info->stream, "%s", riscv_csr_hash[csr]); | |
e23eba97 NC |
395 | else |
396 | print (info->stream, "0x%x", csr); | |
397 | break; | |
398 | } | |
399 | ||
400 | case 'Z': | |
401 | print (info->stream, "%d", rs1); | |
402 | break; | |
403 | ||
404 | default: | |
405 | /* xgettext:c-format */ | |
406 | print (info->stream, _("# internal error, undefined modifier (%c)"), | |
407 | *d); | |
408 | return; | |
409 | } | |
410 | } | |
411 | } | |
412 | ||
413 | /* Print the RISC-V instruction at address MEMADDR in debugged memory, | |
414 | on using INFO. Returns length of the instruction, in bytes. | |
415 | BIGENDIAN must be 1 if this is big-endian code, 0 if | |
416 | this is little-endian code. */ | |
417 | ||
418 | static int | |
419 | riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) | |
420 | { | |
421 | const struct riscv_opcode *op; | |
422 | static bfd_boolean init = 0; | |
423 | static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; | |
424 | struct riscv_private_data *pd; | |
425 | int insnlen; | |
426 | ||
427 | #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) | |
428 | ||
429 | /* Build a hash table to shorten the search time. */ | |
430 | if (! init) | |
431 | { | |
432 | for (op = riscv_opcodes; op->name; op++) | |
433 | if (!riscv_hash[OP_HASH_IDX (op->match)]) | |
434 | riscv_hash[OP_HASH_IDX (op->match)] = op; | |
435 | ||
436 | init = 1; | |
437 | } | |
438 | ||
439 | if (info->private_data == NULL) | |
440 | { | |
441 | int i; | |
442 | ||
443 | pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); | |
444 | pd->gp = -1; | |
445 | pd->print_addr = -1; | |
446 | for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) | |
447 | pd->hi_addr[i] = -1; | |
448 | ||
449 | for (i = 0; i < info->symtab_size; i++) | |
b5292032 | 450 | if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0) |
e23eba97 NC |
451 | pd->gp = bfd_asymbol_value (info->symtab[i]); |
452 | } | |
453 | else | |
454 | pd = info->private_data; | |
455 | ||
456 | insnlen = riscv_insn_length (word); | |
457 | ||
d7560e2d JW |
458 | /* RISC-V instructions are always little-endian. */ |
459 | info->endian_code = BFD_ENDIAN_LITTLE; | |
460 | ||
e23eba97 NC |
461 | info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; |
462 | info->bytes_per_line = 8; | |
d7560e2d JW |
463 | /* We don't support constant pools, so this must be code. */ |
464 | info->display_endian = info->endian_code; | |
e23eba97 NC |
465 | info->insn_info_valid = 1; |
466 | info->branch_delay_insns = 0; | |
467 | info->data_size = 0; | |
468 | info->insn_type = dis_nonbranch; | |
469 | info->target = 0; | |
470 | info->target2 = 0; | |
471 | ||
472 | op = riscv_hash[OP_HASH_IDX (word)]; | |
473 | if (op != NULL) | |
474 | { | |
1080bf78 | 475 | unsigned xlen = 0; |
e23eba97 | 476 | |
2922d21d AW |
477 | /* If XLEN is not known, get its value from the ELF class. */ |
478 | if (info->mach == bfd_mach_riscv64) | |
479 | xlen = 64; | |
480 | else if (info->mach == bfd_mach_riscv32) | |
481 | xlen = 32; | |
482 | else if (info->section != NULL) | |
e23eba97 NC |
483 | { |
484 | Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); | |
485 | xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; | |
486 | } | |
487 | ||
488 | for (; op->name; op++) | |
489 | { | |
490 | /* Does the opcode match? */ | |
491 | if (! (op->match_func) (op, word)) | |
492 | continue; | |
493 | /* Is this a pseudo-instruction and may we print it as such? */ | |
494 | if (no_aliases && (op->pinfo & INSN_ALIAS)) | |
495 | continue; | |
496 | /* Is this instruction restricted to a certain value of XLEN? */ | |
43135d3b | 497 | if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) |
e23eba97 NC |
498 | continue; |
499 | ||
500 | /* It's a match. */ | |
501 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
502 | print_insn_args (op->args, word, memaddr, info); | |
503 | ||
504 | /* Try to disassemble multi-instruction addressing sequences. */ | |
505 | if (pd->print_addr != (bfd_vma)-1) | |
506 | { | |
507 | info->target = pd->print_addr; | |
508 | (*info->fprintf_func) (info->stream, " # "); | |
509 | (*info->print_address_func) (info->target, info); | |
510 | pd->print_addr = -1; | |
511 | } | |
512 | ||
eb41b248 JW |
513 | /* Finish filling out insn_info fields. */ |
514 | switch (op->pinfo & INSN_TYPE) | |
515 | { | |
516 | case INSN_BRANCH: | |
517 | info->insn_type = dis_branch; | |
518 | break; | |
519 | case INSN_CONDBRANCH: | |
520 | info->insn_type = dis_condbranch; | |
521 | break; | |
522 | case INSN_JSR: | |
523 | info->insn_type = dis_jsr; | |
524 | break; | |
525 | case INSN_DREF: | |
526 | info->insn_type = dis_dref; | |
527 | break; | |
528 | default: | |
529 | break; | |
530 | } | |
531 | ||
532 | if (op->pinfo & INSN_DATA_SIZE) | |
533 | { | |
534 | int size = ((op->pinfo & INSN_DATA_SIZE) | |
535 | >> INSN_DATA_SIZE_SHIFT); | |
536 | info->data_size = 1 << (size - 1); | |
537 | } | |
538 | ||
e23eba97 NC |
539 | return insnlen; |
540 | } | |
541 | } | |
542 | ||
543 | /* We did not find a match, so just print the instruction bits. */ | |
544 | info->insn_type = dis_noninsn; | |
545 | (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word); | |
546 | return insnlen; | |
547 | } | |
548 | ||
549 | int | |
550 | print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) | |
551 | { | |
552 | bfd_byte packet[2]; | |
553 | insn_t insn = 0; | |
554 | bfd_vma n; | |
555 | int status; | |
556 | ||
557 | if (info->disassembler_options != NULL) | |
558 | { | |
559 | parse_riscv_dis_options (info->disassembler_options); | |
560 | /* Avoid repeatedly parsing the options. */ | |
561 | info->disassembler_options = NULL; | |
562 | } | |
563 | else if (riscv_gpr_names == NULL) | |
564 | set_default_riscv_dis_options (); | |
565 | ||
566 | /* Instructions are a sequence of 2-byte packets in little-endian order. */ | |
567 | for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2) | |
568 | { | |
569 | status = (*info->read_memory_func) (memaddr + n, packet, 2, info); | |
570 | if (status != 0) | |
571 | { | |
572 | /* Don't fail just because we fell off the end. */ | |
573 | if (n > 0) | |
574 | break; | |
575 | (*info->memory_error_func) (status, memaddr, info); | |
576 | return status; | |
577 | } | |
578 | ||
579 | insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n); | |
580 | } | |
581 | ||
582 | return riscv_disassemble_insn (memaddr, insn, info); | |
583 | } | |
584 | ||
884b49e3 AB |
585 | /* Prevent use of the fake labels that are generated as part of the DWARF |
586 | and for relaxable relocations in the assembler. */ | |
587 | ||
588 | bfd_boolean | |
589 | riscv_symbol_is_valid (asymbol * sym, | |
590 | struct disassemble_info * info ATTRIBUTE_UNUSED) | |
591 | { | |
592 | const char * name; | |
593 | ||
594 | if (sym == NULL) | |
595 | return FALSE; | |
596 | ||
597 | name = bfd_asymbol_name (sym); | |
598 | ||
599 | return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0); | |
600 | } | |
601 | ||
e23eba97 NC |
602 | void |
603 | print_riscv_disassembler_options (FILE *stream) | |
604 | { | |
605 | fprintf (stream, _("\n\ | |
606 | The following RISC-V-specific disassembler options are supported for use\n\ | |
607 | with the -M switch (multiple options should be separated by commas):\n")); | |
608 | ||
609 | fprintf (stream, _("\n\ | |
8f595e9b NC |
610 | numeric Print numeric register names, rather than ABI names.\n")); |
611 | ||
612 | fprintf (stream, _("\n\ | |
613 | no-aliases Disassemble only into canonical instructions, rather\n\ | |
614 | than into pseudoinstructions.\n")); | |
e23eba97 NC |
615 | |
616 | fprintf (stream, _("\n\ | |
8f595e9b NC |
617 | priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\ |
618 | (1.9, 1.9.1, 1.10, 1.11).\n")); | |
e23eba97 NC |
619 | |
620 | fprintf (stream, _("\n")); | |
621 | } |