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e23eba97 | 1 | /* RISC-V opcode list |
219d1afa | 2 | Copyright (C) 2011-2018 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of the GNU opcodes library. | |
8 | ||
9 | This library is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | It is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "sysdep.h" | |
24 | #include "opcode/riscv.h" | |
25 | #include <stdio.h> | |
26 | ||
27 | /* Register names used by gas and objdump. */ | |
28 | ||
29 | const char * const riscv_gpr_names_numeric[NGPR] = | |
30 | { | |
31 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
32 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
33 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
34 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31" | |
35 | }; | |
36 | ||
1d65abb5 | 37 | const char * const riscv_gpr_names_abi[NGPR] = { |
e23eba97 NC |
38 | "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", |
39 | "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", | |
40 | "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", | |
41 | "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" | |
42 | }; | |
43 | ||
44 | const char * const riscv_fpr_names_numeric[NFPR] = | |
45 | { | |
46 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
47 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
48 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
49 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
50 | }; | |
51 | ||
1d65abb5 | 52 | const char * const riscv_fpr_names_abi[NFPR] = { |
e23eba97 NC |
53 | "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", |
54 | "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", | |
55 | "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", | |
56 | "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" | |
57 | }; | |
58 | ||
59 | /* The order of overloaded instructions matters. Label arguments and | |
60 | register arguments look the same. Instructions that can have either | |
61 | for arguments must apear in the correct order in this table for the | |
62 | assembler to pick the right one. In other words, entries with | |
63 | immediate operands must apear after the same instruction with | |
64 | registers. | |
65 | ||
66 | Because of the lookup algorithm used, entries with the same opcode | |
67 | name must be contiguous. */ | |
68 | ||
69 | #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) | |
70 | #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) | |
71 | #define MASK_RD (OP_MASK_RD << OP_SH_RD) | |
72 | #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) | |
1d65abb5 AW |
73 | #define MASK_IMM ENCODE_ITYPE_IMM (-1U) |
74 | #define MASK_RVC_IMM ENCODE_RVC_IMM (-1U) | |
75 | #define MASK_UIMM ENCODE_UTYPE_IMM (-1U) | |
e23eba97 NC |
76 | #define MASK_RM (OP_MASK_RM << OP_SH_RM) |
77 | #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED) | |
78 | #define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC) | |
79 | #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ) | |
80 | #define MASK_RL (OP_MASK_RL << OP_SH_RL) | |
81 | #define MASK_AQRL (MASK_AQ | MASK_RL) | |
82 | ||
83 | static int | |
84 | match_opcode (const struct riscv_opcode *op, insn_t insn) | |
85 | { | |
86 | return ((insn ^ op->match) & op->mask) == 0; | |
87 | } | |
88 | ||
89 | static int | |
90 | match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED, | |
91 | insn_t insn ATTRIBUTE_UNUSED) | |
92 | { | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int | |
97 | match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn) | |
98 | { | |
99 | int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; | |
100 | int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; | |
101 | return match_opcode (op, insn) && rs1 == rs2; | |
102 | } | |
103 | ||
104 | static int | |
105 | match_rd_nonzero (const struct riscv_opcode *op, insn_t insn) | |
106 | { | |
107 | return match_opcode (op, insn) && ((insn & MASK_RD) != 0); | |
108 | } | |
109 | ||
110 | static int | |
111 | match_c_add (const struct riscv_opcode *op, insn_t insn) | |
112 | { | |
113 | return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0); | |
114 | } | |
115 | ||
21a186f2 JW |
116 | /* We don't allow mv zero,X to become a c.mv hint, so we need a separate |
117 | matching function for this. */ | |
118 | ||
119 | static int | |
120 | match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn) | |
121 | { | |
122 | return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0); | |
123 | } | |
124 | ||
2721d702 JW |
125 | static int |
126 | match_c_nop (const struct riscv_opcode *op, insn_t insn) | |
127 | { | |
128 | return (match_opcode (op, insn) | |
129 | && (((insn & MASK_RD) >> OP_SH_RD) == 0)); | |
130 | } | |
131 | ||
63a25ea0 AW |
132 | static int |
133 | match_c_addi16sp (const struct riscv_opcode *op, insn_t insn) | |
134 | { | |
135 | return (match_opcode (op, insn) | |
136 | && (((insn & MASK_RD) >> OP_SH_RD) == 2) | |
137 | && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0); | |
138 | } | |
139 | ||
e23eba97 NC |
140 | static int |
141 | match_c_lui (const struct riscv_opcode *op, insn_t insn) | |
142 | { | |
63a25ea0 AW |
143 | return (match_rd_nonzero (op, insn) |
144 | && (((insn & MASK_RD) >> OP_SH_RD) != 2) | |
145 | && EXTRACT_RVC_LUI_IMM (insn) != 0); | |
146 | } | |
147 | ||
21a186f2 JW |
148 | /* We don't allow lui zero,X to become a c.lui hint, so we need a separate |
149 | matching function for this. */ | |
150 | ||
151 | static int | |
152 | match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn) | |
153 | { | |
154 | return (match_opcode (op, insn) | |
155 | && (((insn & MASK_RD) >> OP_SH_RD) != 2) | |
156 | && EXTRACT_RVC_LUI_IMM (insn) != 0); | |
157 | } | |
158 | ||
63a25ea0 AW |
159 | static int |
160 | match_c_addi4spn (const struct riscv_opcode *op, insn_t insn) | |
161 | { | |
162 | return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0; | |
e23eba97 NC |
163 | } |
164 | ||
e6f372ba JW |
165 | /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */ |
166 | ||
167 | static int | |
168 | match_c_slli (const struct riscv_opcode *op, insn_t insn) | |
169 | { | |
170 | return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0; | |
171 | } | |
172 | ||
173 | /* This requires a non-zero rd, and a non-zero shift. */ | |
174 | ||
175 | static int | |
176 | match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn) | |
177 | { | |
178 | return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0; | |
179 | } | |
180 | ||
181 | /* This requires a zero shift. A zero rd is a hint, so is allowed. */ | |
182 | ||
183 | static int | |
184 | match_c_slli64 (const struct riscv_opcode *op, insn_t insn) | |
185 | { | |
186 | return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0; | |
187 | } | |
188 | ||
189 | /* This is used for both srli and srai. This requires a non-zero shift. | |
190 | A zero rd is not possible. */ | |
191 | ||
192 | static int | |
193 | match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn) | |
194 | { | |
195 | return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0; | |
196 | } | |
197 | ||
e23eba97 NC |
198 | const struct riscv_opcode riscv_opcodes[] = |
199 | { | |
200 | /* name, isa, operands, match, mask, match_func, pinfo. */ | |
201 | {"unimp", "C", "", 0, 0xffffU, match_opcode, 0 }, | |
202 | {"unimp", "I", "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ | |
203 | {"ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, | |
204 | {"ebreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, | |
205 | {"sbreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, | |
206 | {"sbreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS }, | |
207 | {"ret", "C", "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS }, | |
208 | {"ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, | |
209 | {"jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS }, | |
210 | {"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, | |
755c5297 | 211 | {"jr", "I", "o(s)", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, |
e23eba97 NC |
212 | {"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, |
213 | {"jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS }, | |
214 | {"jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, | |
755c5297 | 215 | {"jalr", "I", "o(s)", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, |
e23eba97 NC |
216 | {"jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, |
217 | {"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS }, | |
755c5297 | 218 | {"jalr", "I", "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, 0 }, |
e23eba97 NC |
219 | {"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, 0 }, |
220 | {"j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS }, | |
221 | {"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, | |
58a6d3c9 | 222 | {"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, 0 }, |
e23eba97 NC |
223 | {"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS }, |
224 | {"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, | |
e23eba97 | 225 | {"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, |
43e379d7 | 226 | {"call", "I", "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, |
e23eba97 NC |
227 | {"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, |
228 | {"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, | |
229 | {"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, | |
230 | {"nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, | |
231 | {"lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, | |
232 | {"lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, | |
233 | {"li", "C", "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, | |
21a186f2 | 234 | {"li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, |
e23eba97 NC |
235 | {"li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ |
236 | {"li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, | |
237 | {"mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, | |
238 | {"mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, | |
239 | {"move", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, | |
240 | {"move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, | |
21a186f2 | 241 | {"andi", "C", "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, |
e23eba97 NC |
242 | {"andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, |
243 | {"and", "C", "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, | |
244 | {"and", "C", "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, | |
21a186f2 | 245 | {"and", "C", "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, |
e23eba97 NC |
246 | {"and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, |
247 | {"and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, | |
248 | {"beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS }, | |
249 | {"beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS }, | |
250 | {"beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, 0 }, | |
251 | {"blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS }, | |
252 | {"bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS }, | |
253 | {"ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS }, | |
254 | {"bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS }, | |
255 | {"bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, 0 }, | |
256 | {"bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, 0 }, | |
257 | {"bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS }, | |
258 | {"bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS }, | |
259 | {"blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, 0 }, | |
260 | {"bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, 0 }, | |
261 | {"bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS }, | |
262 | {"bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS }, | |
263 | {"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS }, | |
264 | {"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS }, | |
265 | {"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, | |
63a25ea0 | 266 | {"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, |
e23eba97 | 267 | {"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, |
e925c834 | 268 | {"addi", "C", "d,CU,z", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, |
63a25ea0 | 269 | {"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, |
e23eba97 NC |
270 | {"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, |
271 | {"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, | |
272 | {"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, | |
21a186f2 | 273 | {"add", "C", "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, |
63a25ea0 AW |
274 | {"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, |
275 | {"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, | |
e23eba97 | 276 | {"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, |
21a186f2 JW |
277 | /* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc |
278 | applied to an add instruction, for relaxation to use. */ | |
e23eba97 NC |
279 | {"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 }, |
280 | {"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, | |
281 | {"la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO }, | |
282 | {"lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO }, | |
283 | {"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, | |
284 | {"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, | |
285 | {"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ | |
e6f372ba | 286 | {"slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, |
e23eba97 | 287 | {"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, |
e6f372ba | 288 | {"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, |
e23eba97 NC |
289 | {"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, |
290 | {"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, | |
e6f372ba | 291 | {"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, |
e23eba97 | 292 | {"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, |
e6f372ba | 293 | {"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, |
e23eba97 NC |
294 | {"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, |
295 | {"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, | |
e6f372ba | 296 | {"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, |
e23eba97 | 297 | {"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, |
e6f372ba | 298 | {"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, |
e23eba97 NC |
299 | {"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, |
300 | {"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, | |
301 | {"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, | |
302 | {"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, | |
303 | {"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, 0 }, | |
304 | {"lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, | |
305 | {"lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, 0 }, | |
306 | {"lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, | |
307 | {"lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, 0 }, | |
308 | {"lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, | |
309 | {"lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, 0 }, | |
310 | {"lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, | |
311 | {"lw", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS }, | |
312 | {"lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS }, | |
313 | {"lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, 0 }, | |
314 | {"lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, | |
315 | {"not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS }, | |
316 | {"ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, | |
317 | {"or", "C", "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, | |
318 | {"or", "C", "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, | |
319 | {"or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, | |
320 | {"or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, | |
321 | {"auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, | |
1d65abb5 | 322 | {"seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS }, |
e23eba97 NC |
323 | {"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS }, |
324 | {"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS }, | |
325 | {"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS }, | |
9bdfdbf9 | 326 | {"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, |
e23eba97 | 327 | {"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, |
9bdfdbf9 | 328 | {"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, |
e23eba97 NC |
329 | {"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, |
330 | {"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, | |
331 | {"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, | |
332 | {"sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS }, | |
333 | {"sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS }, | |
334 | {"sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, 0 }, | |
335 | {"sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, | |
336 | {"sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, 0 }, | |
337 | {"sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, | |
338 | {"sw", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS }, | |
339 | {"sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS }, | |
340 | {"sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, 0 }, | |
341 | {"sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, | |
342 | {"fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, | |
343 | {"fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, | |
344 | {"fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, | |
04386d9e AW |
345 | {"rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, |
346 | {"rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, | |
347 | {"rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS }, | |
348 | {"rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS }, | |
349 | {"rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, | |
350 | {"rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, | |
e23eba97 NC |
351 | {"ecall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, |
352 | {"scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, | |
353 | {"xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, | |
354 | {"xor", "C", "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, | |
355 | {"xor", "C", "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, | |
356 | {"xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 }, | |
357 | {"xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, | |
358 | {"lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, 0 }, | |
359 | {"lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO }, | |
360 | {"ld", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS }, | |
361 | {"ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS }, | |
362 | {"ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, 0 }, | |
363 | {"ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO }, | |
364 | {"sd", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS }, | |
365 | {"sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS }, | |
366 | {"sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, 0 }, | |
367 | {"sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO }, | |
368 | {"sext.w", "64C", "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, | |
369 | {"sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS }, | |
21a186f2 | 370 | {"addiw", "64C", "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, |
e23eba97 NC |
371 | {"addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 }, |
372 | {"addw", "64C", "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, | |
373 | {"addw", "64C", "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, | |
21a186f2 | 374 | {"addw", "64C", "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, |
e23eba97 NC |
375 | {"addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, |
376 | {"addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, | |
377 | {"negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ | |
378 | {"slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 }, | |
379 | {"sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 }, | |
380 | {"sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS }, | |
381 | {"srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 }, | |
382 | {"srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 }, | |
383 | {"srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS }, | |
384 | {"sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 }, | |
385 | {"sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 }, | |
386 | {"sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS }, | |
387 | {"subw", "64C", "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, | |
388 | {"subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, | |
389 | ||
390 | /* Atomic memory operation instruction subset */ | |
391 | {"lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, | |
392 | {"sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, | |
393 | {"amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, | |
394 | {"amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, | |
395 | {"amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, | |
396 | {"amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, | |
397 | {"amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, | |
398 | {"amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, | |
399 | {"amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, | |
400 | {"amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, | |
401 | {"amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, | |
402 | {"lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, | |
403 | {"sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, | |
404 | {"amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, | |
405 | {"amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, | |
406 | {"amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, | |
407 | {"amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, | |
408 | {"amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, | |
409 | {"amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, | |
410 | {"amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, | |
411 | {"amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, | |
412 | {"amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, | |
413 | {"lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, | |
414 | {"sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, | |
415 | {"amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, | |
416 | {"amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, | |
417 | {"amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, | |
418 | {"amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, | |
419 | {"amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, | |
420 | {"amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, | |
421 | {"amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, | |
422 | {"amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, | |
423 | {"amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, | |
3e67a378 AW |
424 | {"lr.w.aqrl", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, |
425 | {"sc.w.aqrl", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, | |
426 | {"amoadd.w.aqrl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, | |
427 | {"amoswap.w.aqrl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, | |
428 | {"amoand.w.aqrl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, | |
429 | {"amoor.w.aqrl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, | |
430 | {"amoxor.w.aqrl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, | |
431 | {"amomax.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, | |
432 | {"amomaxu.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, | |
433 | {"amomin.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, | |
434 | {"amominu.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, | |
e23eba97 NC |
435 | {"lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, |
436 | {"sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, | |
437 | {"amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, | |
438 | {"amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, | |
439 | {"amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, | |
440 | {"amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, | |
441 | {"amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, | |
442 | {"amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, | |
443 | {"amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, | |
444 | {"amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, | |
445 | {"amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, | |
446 | {"lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, | |
447 | {"sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, | |
448 | {"amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, | |
449 | {"amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, | |
450 | {"amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, | |
451 | {"amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, | |
452 | {"amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, | |
453 | {"amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, | |
454 | {"amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, | |
455 | {"amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, | |
456 | {"amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, | |
457 | {"lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, | |
458 | {"sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, | |
459 | {"amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, | |
460 | {"amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, | |
461 | {"amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, | |
462 | {"amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, | |
463 | {"amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, | |
464 | {"amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, | |
465 | {"amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, | |
466 | {"amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, | |
467 | {"amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, | |
3e67a378 AW |
468 | {"lr.d.aqrl", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, |
469 | {"sc.d.aqrl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, | |
470 | {"amoadd.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, | |
471 | {"amoswap.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, | |
472 | {"amoand.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, | |
473 | {"amoor.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, | |
474 | {"amoxor.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, | |
475 | {"amomax.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, | |
476 | {"amomaxu.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, | |
477 | {"amomin.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, | |
478 | {"amominu.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, | |
e23eba97 NC |
479 | |
480 | /* Multiply/Divide instruction subset */ | |
481 | {"mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, | |
482 | {"mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, | |
483 | {"mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, | |
484 | {"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, | |
485 | {"div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, | |
486 | {"divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, | |
487 | {"rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, | |
488 | {"remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, | |
489 | {"mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, | |
490 | {"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, | |
491 | {"divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, | |
492 | {"remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, | |
493 | {"remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, | |
494 | ||
495 | /* Single-precision floating-point instruction subset */ | |
496 | {"frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, | |
497 | {"fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, | |
498 | {"fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, | |
499 | {"frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, | |
500 | {"fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, | |
501 | {"fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, | |
502 | {"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 }, | |
503 | {"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 }, | |
504 | {"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 }, | |
25982ee0 JW |
505 | {"fsrmi", "F", "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 }, |
506 | {"fsrmi", "F", "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 }, | |
e23eba97 NC |
507 | {"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 }, |
508 | {"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 }, | |
509 | {"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, | |
25982ee0 JW |
510 | {"fsflagsi", "F", "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 }, |
511 | {"fsflagsi", "F", "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 }, | |
e23eba97 NC |
512 | {"flw", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS }, |
513 | {"flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS }, | |
514 | {"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, 0 }, | |
515 | {"flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, | |
516 | {"fsw", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS }, | |
517 | {"fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS }, | |
518 | {"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 }, | |
519 | {"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, | |
8e43602e NC |
520 | |
521 | {"fmv.x.w", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, | |
522 | {"fmv.w.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, | |
523 | ||
e23eba97 NC |
524 | {"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, |
525 | {"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, | |
8e43602e | 526 | |
e23eba97 NC |
527 | {"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, |
528 | {"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, | |
529 | {"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, | |
530 | {"fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, | |
531 | {"fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, | |
532 | {"fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, | |
533 | {"fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 }, | |
534 | {"fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, | |
535 | {"fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 }, | |
536 | {"fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, | |
537 | {"fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 }, | |
538 | {"fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, | |
539 | {"fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 }, | |
540 | {"fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, | |
541 | {"fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 }, | |
542 | {"fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, | |
543 | {"fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, | |
544 | {"fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, | |
545 | {"fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 }, | |
546 | {"fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, | |
547 | {"fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 }, | |
548 | {"fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, | |
549 | {"fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 }, | |
550 | {"fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, | |
551 | {"fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 }, | |
552 | {"fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, | |
553 | {"fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 }, | |
554 | {"fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, | |
555 | {"fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 }, | |
556 | {"fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, | |
557 | {"fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, | |
558 | {"fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, | |
559 | {"fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, | |
560 | {"fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, | |
561 | {"fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, | |
562 | {"feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, | |
563 | {"flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, | |
564 | {"fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, | |
565 | {"fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, | |
566 | {"fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, | |
567 | {"fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 }, | |
568 | {"fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, | |
569 | {"fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 }, | |
570 | {"fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, | |
571 | {"fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, | |
572 | {"fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, | |
573 | {"fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, | |
574 | {"fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, | |
575 | ||
576 | /* Double-precision floating-point instruction subset */ | |
577 | {"fld", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS }, | |
578 | {"fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS }, | |
579 | {"fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, 0 }, | |
580 | {"fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, | |
581 | {"fsd", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS }, | |
582 | {"fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS }, | |
583 | {"fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, 0 }, | |
584 | {"fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, | |
585 | {"fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, | |
586 | {"fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, | |
587 | {"fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, | |
588 | {"fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, | |
589 | {"fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, | |
590 | {"fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, | |
591 | {"fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 }, | |
592 | {"fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, | |
593 | {"fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 }, | |
594 | {"fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, | |
595 | {"fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 }, | |
596 | {"fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, | |
597 | {"fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 }, | |
598 | {"fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, | |
599 | {"fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 }, | |
600 | {"fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, | |
601 | {"fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, | |
602 | {"fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, | |
603 | {"fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 }, | |
604 | {"fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, | |
605 | {"fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 }, | |
606 | {"fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, | |
607 | {"fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 }, | |
608 | {"fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, | |
609 | {"fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 }, | |
610 | {"fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, | |
611 | {"fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 }, | |
612 | {"fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, | |
613 | {"fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 }, | |
614 | {"fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, | |
615 | {"fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 }, | |
616 | {"fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 }, | |
617 | {"fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 }, | |
618 | {"fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 }, | |
619 | {"fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, | |
620 | {"fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, | |
621 | {"feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, | |
622 | {"flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, | |
623 | {"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, | |
624 | {"fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, | |
625 | {"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, | |
626 | {"fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, | |
627 | {"fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, | |
628 | {"fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 }, | |
629 | {"fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, | |
630 | {"fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 }, | |
631 | {"fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, | |
632 | {"fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, | |
633 | {"fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, | |
634 | {"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, | |
635 | {"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, | |
636 | ||
cc917fd9 KC |
637 | /* Quad-precision floating-point instruction subset */ |
638 | {"flq", "Q", "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, 0 }, | |
639 | {"flq", "Q", "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, | |
640 | {"fsq", "Q", "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, 0 }, | |
641 | {"fsq", "Q", "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, | |
642 | {"fmv.q", "Q", "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, | |
643 | {"fneg.q", "Q", "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, | |
644 | {"fabs.q", "Q", "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, | |
645 | {"fsgnj.q", "Q", "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, | |
646 | {"fsgnjn.q", "Q", "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, | |
647 | {"fsgnjx.q", "Q", "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, | |
648 | {"fadd.q", "Q", "D,S,T", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 }, | |
649 | {"fadd.q", "Q", "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, | |
650 | {"fsub.q", "Q", "D,S,T", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 }, | |
651 | {"fsub.q", "Q", "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, | |
652 | {"fmul.q", "Q", "D,S,T", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 }, | |
653 | {"fmul.q", "Q", "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, | |
654 | {"fdiv.q", "Q", "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 }, | |
655 | {"fdiv.q", "Q", "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, | |
656 | {"fsqrt.q", "Q", "D,S", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 }, | |
657 | {"fsqrt.q", "Q", "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, | |
658 | {"fmin.q", "Q", "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, | |
659 | {"fmax.q", "Q", "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, | |
660 | {"fmadd.q", "Q", "D,S,T,R", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 }, | |
661 | {"fmadd.q", "Q", "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, | |
662 | {"fnmadd.q", "Q", "D,S,T,R", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 }, | |
663 | {"fnmadd.q", "Q", "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, | |
664 | {"fmsub.q", "Q", "D,S,T,R", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 }, | |
665 | {"fmsub.q", "Q", "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, | |
666 | {"fnmsub.q", "Q", "D,S,T,R", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 }, | |
667 | {"fnmsub.q", "Q", "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, | |
668 | {"fcvt.w.q", "Q", "d,S", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 }, | |
669 | {"fcvt.w.q", "Q", "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, | |
670 | {"fcvt.wu.q", "Q", "d,S", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 }, | |
671 | {"fcvt.wu.q", "Q", "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, | |
672 | {"fcvt.q.w", "Q", "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 }, | |
673 | {"fcvt.q.wu", "Q", "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 }, | |
674 | {"fcvt.q.s", "Q", "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 }, | |
675 | {"fcvt.q.d", "Q", "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 }, | |
676 | {"fcvt.s.q", "Q", "D,S", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 }, | |
677 | {"fcvt.s.q", "Q", "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, | |
678 | {"fcvt.d.q", "Q", "D,S", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 }, | |
679 | {"fcvt.d.q", "Q", "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, | |
680 | {"fclass.q", "Q", "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, | |
681 | {"feq.q", "Q", "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, | |
682 | {"flt.q", "Q", "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, | |
683 | {"fle.q", "Q", "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, | |
684 | {"fgt.q", "Q", "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, | |
685 | {"fge.q", "Q", "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, | |
686 | {"fmv.x.q", "64Q", "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 }, | |
687 | {"fmv.q.x", "64Q", "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 }, | |
688 | {"fcvt.l.q", "64Q", "d,S", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 }, | |
689 | {"fcvt.l.q", "64Q", "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, | |
690 | {"fcvt.lu.q", "64Q", "d,S", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 }, | |
691 | {"fcvt.lu.q", "64Q", "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, | |
692 | {"fcvt.q.l", "64Q", "D,s", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 }, | |
693 | {"fcvt.q.l", "64Q", "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, | |
694 | {"fcvt.q.lu", "64Q", "D,s", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 }, | |
695 | {"fcvt.q.lu", "64Q", "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, | |
696 | ||
e23eba97 NC |
697 | /* Compressed instructions. */ |
698 | {"c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, | |
699 | {"c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 }, | |
700 | {"c.jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 }, | |
701 | {"c.j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, 0 }, | |
702 | {"c.jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 }, | |
703 | {"c.beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 }, | |
704 | {"c.bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 }, | |
705 | {"c.lwsp", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, | |
706 | {"c.lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, 0 }, | |
707 | {"c.swsp", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 }, | |
708 | {"c.sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, 0 }, | |
67d888f5 | 709 | {"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, |
21a186f2 JW |
710 | {"c.nop", "C", "Cj", MATCH_C_ADDI, MASK_C_ADDI | MASK_RD, match_opcode, INSN_ALIAS }, |
711 | {"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 }, | |
712 | {"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 }, | |
713 | {"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_opcode, 0 }, | |
63a25ea0 AW |
714 | {"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 }, |
715 | {"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 }, | |
21a186f2 JW |
716 | {"c.addi", "C", "d,Co", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, |
717 | {"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 }, | |
e23eba97 NC |
718 | {"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, |
719 | {"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, | |
720 | {"c.or", "C", "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, | |
721 | {"c.xor", "C", "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, | |
e6f372ba JW |
722 | {"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 }, |
723 | {"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 }, | |
724 | {"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 }, | |
725 | {"c.slli64", "C", "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 }, | |
726 | {"c.srli64", "C", "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 }, | |
727 | {"c.srai64", "C", "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 }, | |
b416fe87 KC |
728 | {"c.andi", "C", "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, |
729 | {"c.addiw", "64C", "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, | |
e23eba97 NC |
730 | {"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, |
731 | {"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, | |
732 | {"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, | |
733 | {"c.ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, 0 }, | |
734 | {"c.sdsp", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 }, | |
735 | {"c.sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, 0 }, | |
736 | {"c.fldsp", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, 0 }, | |
737 | {"c.fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, 0 }, | |
738 | {"c.fsdsp", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, 0 }, | |
739 | {"c.fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, 0 }, | |
740 | {"c.flwsp", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, 0 }, | |
741 | {"c.flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, 0 }, | |
742 | {"c.fswsp", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, 0 }, | |
743 | {"c.fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, 0 }, | |
744 | ||
745 | /* Supervisor instructions */ | |
04386d9e AW |
746 | {"csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS }, |
747 | {"csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS }, | |
748 | {"csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS }, | |
749 | {"csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS }, | |
750 | {"csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS }, | |
751 | {"csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS }, | |
752 | {"csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS }, | |
753 | {"csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS }, | |
754 | {"csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS }, | |
755 | {"csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS }, | |
e23eba97 NC |
756 | {"csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, |
757 | {"csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, | |
758 | {"csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, | |
04386d9e AW |
759 | {"csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, |
760 | {"csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS }, | |
761 | {"csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, | |
762 | {"csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS }, | |
763 | {"csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, | |
764 | {"csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS }, | |
e23eba97 NC |
765 | {"uret", "I", "", MATCH_URET, MASK_URET, match_opcode, 0 }, |
766 | {"sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, | |
767 | {"hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, | |
768 | {"mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, | |
769 | {"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, | |
770 | {"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, | |
771 | {"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, | |
f98d33be AW |
772 | {"sfence.vma","I", "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS }, |
773 | {"sfence.vma","I", "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS }, | |
774 | {"sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, | |
e23eba97 NC |
775 | {"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, |
776 | ||
777 | /* Terminate the list. */ | |
778 | {0, 0, 0, 0, 0, 0, 0} | |
779 | }; | |
0e35537d JW |
780 | |
781 | /* Instruction format for .insn directive. */ | |
782 | const struct riscv_opcode riscv_insn_types[] = | |
783 | { | |
784 | /* name, isa, operands, match, mask, match_func, pinfo. */ | |
785 | {"r", "I", "O4,F3,F7,d,s,t", 0, 0, match_opcode, 0 }, | |
786 | {"r", "I", "O4,F3,F7,D,s,t", 0, 0, match_opcode, 0 }, | |
787 | {"r", "I", "O4,F3,F7,d,S,t", 0, 0, match_opcode, 0 }, | |
788 | {"r", "I", "O4,F3,F7,D,S,t", 0, 0, match_opcode, 0 }, | |
789 | {"r", "I", "O4,F3,F7,d,s,T", 0, 0, match_opcode, 0 }, | |
790 | {"r", "I", "O4,F3,F7,D,s,T", 0, 0, match_opcode, 0 }, | |
791 | {"r", "I", "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 }, | |
792 | {"r", "I", "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 }, | |
793 | ||
794 | {"r", "I", "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 }, | |
795 | {"r", "I", "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 }, | |
796 | {"r", "I", "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 }, | |
797 | {"r", "I", "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 }, | |
798 | {"r", "I", "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 }, | |
799 | {"r", "I", "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 }, | |
800 | {"r", "I", "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 }, | |
801 | {"r", "I", "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 }, | |
802 | {"r", "I", "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 }, | |
803 | {"r", "I", "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 }, | |
804 | {"r", "I", "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 }, | |
805 | {"r", "I", "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 }, | |
806 | {"r", "I", "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 }, | |
807 | {"r", "I", "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 }, | |
808 | {"r", "I", "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 }, | |
809 | {"r", "I", "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 }, | |
810 | ||
811 | {"i", "I", "O4,F3,d,s,j", 0, 0, match_opcode, 0 }, | |
812 | {"i", "I", "O4,F3,D,s,j", 0, 0, match_opcode, 0 }, | |
813 | {"i", "I", "O4,F3,d,S,j", 0, 0, match_opcode, 0 }, | |
814 | {"i", "I", "O4,F3,D,S,j", 0, 0, match_opcode, 0 }, | |
815 | ||
816 | {"i", "I", "O4,F3,d,o(s)", 0, 0, match_opcode, 0 }, | |
817 | {"i", "I", "O4,F3,D,o(s)", 0, 0, match_opcode, 0 }, | |
818 | ||
819 | {"s", "I", "O4,F3,d,o(s)", 0, 0, match_opcode, 0 }, | |
820 | {"s", "I", "O4,F3,D,o(s)", 0, 0, match_opcode, 0 }, | |
821 | ||
822 | {"sb", "I", "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, | |
823 | {"sb", "I", "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, | |
824 | {"sb", "I", "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, | |
825 | {"sb", "I", "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, | |
826 | ||
827 | {"sb", "I", "O4,F3,t,q(s)", 0, 0, match_opcode, 0 }, | |
828 | {"sb", "I", "O4,F3,T,q(s)", 0, 0, match_opcode, 0 }, | |
829 | ||
830 | {"u", "I", "O4,d,u", 0, 0, match_opcode, 0 }, | |
831 | {"u", "I", "O4,D,u", 0, 0, match_opcode, 0 }, | |
832 | ||
833 | {"uj", "I", "O4,d,a", 0, 0, match_opcode, 0 }, | |
834 | {"uj", "I", "O4,D,a", 0, 0, match_opcode, 0 }, | |
835 | ||
836 | {"cr", "C", "O2,CF4,d,CV", 0, 0, match_opcode, 0 }, | |
837 | {"cr", "C", "O2,CF4,D,CV", 0, 0, match_opcode, 0 }, | |
838 | {"cr", "C", "O2,CF4,d,CT", 0, 0, match_opcode, 0 }, | |
839 | {"cr", "C", "O2,CF4,D,CT", 0, 0, match_opcode, 0 }, | |
840 | ||
841 | {"ci", "C", "O2,CF3,d,Co", 0, 0, match_opcode, 0 }, | |
842 | {"ci", "C", "O2,CF3,D,Co", 0, 0, match_opcode, 0 }, | |
843 | ||
844 | {"ciw", "C", "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 }, | |
845 | {"ciw", "C", "O2,CF3,CD,C8", 0, 0, match_opcode, 0 }, | |
846 | ||
847 | {"cb", "C", "O2,CF3,Cs,Cp", 0, 0, match_opcode, 0 }, | |
848 | {"cb", "C", "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 }, | |
849 | ||
850 | {"cj", "C", "O2,CF3,Ca", 0, 0, match_opcode, 0 }, | |
851 | /* Terminate the list. */ | |
852 | {0, 0, 0, 0, 0, 0, 0} | |
853 | }; |