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ubsan: iq2000: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / s12z-opc.c
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ef1ad42b
JD		 1/* s12z-decode.c -- Freescale S12Z disassembly
2 Copyright (C) 2018 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21#include "sysdep.h"
22#include <stdio.h>
23#include <stdint.h>
24#include <stdbool.h>
25#include <assert.h>
26
27#include "opcode/s12z.h"
28
29#include "bfd.h"
30
31#include "s12z-opc.h"
32
33
34typedef int (* insn_bytes_f) (struct mem_read_abstraction_base *);
35
36typedef void (*operands_f) (struct mem_read_abstraction_base *,
37 int *n_operands, struct operand **operand);
38
e5a557ac
JD		 39typedef enum optr (*discriminator_f) (struct mem_read_abstraction_base *,
40 enum optr hint);
ef1ad42b
JD		 41
42enum OPR_MODE
43 {
44 OPR_IMMe4,
45 OPR_REG,
46 OPR_OFXYS,
47 OPR_XY_PRE_INC,
48 OPR_XY_POST_INC,
49 OPR_XY_PRE_DEC,
50 OPR_XY_POST_DEC,
51 OPR_S_PRE_DEC,
52 OPR_S_POST_INC,
53 OPR_REG_DIRECT,
54 OPR_REG_INDIRECT,
55 OPR_IDX_DIRECT,
56 OPR_IDX_INDIRECT,
57 OPR_EXT1,
58 OPR_IDX2_REG,
59 OPR_IDX3_DIRECT,
60 OPR_IDX3_INDIRECT,
61
62 OPR_EXT18,
63 OPR_IDX3_DIRECT_REG,
64 OPR_EXT3_DIRECT,
65 OPR_EXT3_INDIRECT
66 };
67
68struct opr_pb
69{
70 uint8_t mask;
71 uint8_t value;
72 int n_operands;
73 enum OPR_MODE mode;
74};
75
76static const struct opr_pb opr_pb[] = {
77 {0xF0, 0x70, 1, OPR_IMMe4},
78 {0xF8, 0xB8, 1, OPR_REG},
79 {0xC0, 0x40, 1, OPR_OFXYS},
80 {0xEF, 0xE3, 1, OPR_XY_PRE_INC},
81 {0xEF, 0xE7, 1, OPR_XY_POST_INC},
82 {0xEF, 0xC3, 1, OPR_XY_PRE_DEC},
83 {0xEF, 0xC7, 1, OPR_XY_POST_DEC},
84 {0xFF, 0xFB, 1, OPR_S_PRE_DEC},
85 {0xFF, 0xFF, 1, OPR_S_POST_INC},
86 {0xC8, 0x88, 1, OPR_REG_DIRECT},
87 {0xE8, 0xC8, 1, OPR_REG_INDIRECT},
88
89 {0xCE, 0xC0, 2, OPR_IDX_DIRECT},
90 {0xCE, 0xC4, 2, OPR_IDX_INDIRECT},
91 {0xC0, 0x00, 2, OPR_EXT1},
92
93 {0xC8, 0x80, 3, OPR_IDX2_REG},
94 {0xFA, 0xF8, 3, OPR_EXT18},
95
96 {0xCF, 0xC2, 4, OPR_IDX3_DIRECT},
97 {0xCF, 0xC6, 4, OPR_IDX3_INDIRECT},
98
99 {0xF8, 0xE8, 4, OPR_IDX3_DIRECT_REG},
100 {0xFF, 0xFA, 4, OPR_EXT3_DIRECT},
101 {0xFF, 0xFE, 4, OPR_EXT3_INDIRECT},
102};
103
104/* Return the number of bytes in a OPR operand, including the XB postbyte.
105 It does not include any preceeding opcodes. */
106static int
107x_opr_n_bytes (struct mem_read_abstraction_base *mra, int offset)
108{
109 bfd_byte xb;
110 int status = mra->read (mra, offset, 1, &xb);
111 if (status < 0)
112 return status;
113
114 size_t i;
115 for (i = 0; i < sizeof (opr_pb) / sizeof (opr_pb[0]); ++i)
116 {
117 const struct opr_pb *pb = opr_pb + i;
118 if ((xb & pb->mask) == pb->value)
119 {
120 return pb->n_operands;
121 }
122 }
123
124 return 1;
125}
126
127static int
128opr_n_bytes_p1 (struct mem_read_abstraction_base *mra)
129{
130 return 1 + x_opr_n_bytes (mra, 0);
131}
132
133static int
134opr_n_bytes2 (struct mem_read_abstraction_base *mra)
135{
136 int s = x_opr_n_bytes (mra, 0);
137 s += x_opr_n_bytes (mra, s);
138 return s + 1;
139}
140
141enum BB_MODE
142 {
143 BB_REG_REG_REG,
144 BB_REG_REG_IMM,
145 BB_REG_OPR_REG,
146 BB_OPR_REG_REG,
147 BB_REG_OPR_IMM,
148 BB_OPR_REG_IMM
149 };
150
151struct opr_bb
152{
153 uint8_t mask;
154 uint8_t value;
155 int n_operands;
156 bool opr;
157 enum BB_MODE mode;
158};
159
160static const struct opr_bb bb_modes[] =
161 {
162 {0x60, 0x00, 2, false, BB_REG_REG_REG},
163 {0x60, 0x20, 3, false, BB_REG_REG_IMM},
164 {0x70, 0x40, 2, true, BB_REG_OPR_REG},
165 {0x70, 0x50, 2, true, BB_OPR_REG_REG},
166 {0x70, 0x60, 3, true, BB_REG_OPR_IMM},
167 {0x70, 0x70, 3, true, BB_OPR_REG_IMM}
168 };
169
170static int
171bfextins_n_bytes (struct mem_read_abstraction_base *mra)
172{
173 bfd_byte bb;
174 int status = mra->read (mra, 0, 1, &bb);
175 if (status < 0)
176 return status;
177
178 size_t i;
179 const struct opr_bb *bbs = 0;
180 for (i = 0; i < sizeof (bb_modes) / sizeof (bb_modes[0]); ++i)
181 {
182 bbs = bb_modes + i;
183 if ((bb & bbs->mask) == bbs->value)
184 {
185 break;
186 }
187 }
188
189 int n = bbs->n_operands;
190 if (bbs->opr)
191 n += x_opr_n_bytes (mra, n - 1);
192
193 return n;
194}
195
196static int
197single (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED)
198{
199 return 1;
200}
201
202static int
203two (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED)
204{
205 return 2;
206}
207
208static int
209three (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED)
210{
211 return 3;
212}
213
214static int
215four (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED)
216{
217 return 4;
218}
219
220static int
221five (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED)
222{
223 return 5;
224}
225
226static int
227pcrel_15bit (struct mem_read_abstraction_base *mra)
228{
229 bfd_byte byte;
230 int status = mra->read (mra, 0, 1, &byte);
231 if (status < 0)
232 return status;
233 return (byte & 0x80) ? 3 : 2;
234}
235
236
237\f
238static int
239xysp_reg_from_postbyte (uint8_t postbyte)
240{
241 int reg = -1;
242 switch ((postbyte & 0x30) >> 4)
243 {
244 case 0:
245 reg = REG_X;
246 break;
247 case 1:
248 reg = REG_Y;
249 break;
250 case 2:
251 reg = REG_S;
252 break;
253 default:
254 reg = REG_P;
255 }
256 return reg;
257}
258
e7c22a69
AM		 259static struct operand *
260create_immediate_operand (int value)
ef1ad42b
JD		 261{
262 struct immediate_operand *op = malloc (sizeof (*op));
263
264 ((struct operand *)op)->cl = OPND_CL_IMMEDIATE;
265 op->value = value;
266 ((struct operand *)op)->osize = -1;
267
268 return (struct operand *) op;
269}
270
e7c22a69
AM		 271static struct operand *
272create_bitfield_operand (int width, int offset)
ef1ad42b
JD		 273{
274 struct bitfield_operand *op = malloc (sizeof (*op));
275
276 ((struct operand *)op)->cl = OPND_CL_BIT_FIELD;
277 op->width = width;
278 op->offset = offset;
279 ((struct operand *)op)->osize = -1;
280
281 return (struct operand *) op;
282}
283
284static struct operand *
285create_register_operand_with_size (int reg, short osize)
286{
287 struct register_operand *op = malloc (sizeof (*op));
288
289 ((struct operand *)op)->cl = OPND_CL_REGISTER;
290 op->reg = reg;
291 ((struct operand *)op)->osize = osize;
292
293 return (struct operand *) op;
294}
295
296static struct operand *
297create_register_operand (int reg)
298{
299 return create_register_operand_with_size (reg, -1);
300}
301
e7c22a69
AM		 302static struct operand *
303create_register_all_operand (void)
ef1ad42b
JD		 304{
305 struct register_operand *op = malloc (sizeof (*op));
306
307 ((struct operand *)op)->cl = OPND_CL_REGISTER_ALL;
308 ((struct operand *)op)->osize = -1;
309
310 return (struct operand *) op;
311}
312
e7c22a69
AM		 313static struct operand *
314create_register_all16_operand (void)
ef1ad42b
JD		 315{
316 struct register_operand *op = malloc (sizeof (*op));
317
318 ((struct operand *)op)->cl = OPND_CL_REGISTER_ALL16;
319 ((struct operand *)op)->osize = -1;
320
321 return (struct operand *) op;
322}
323
324
325static struct operand *
326create_simple_memory_operand (bfd_vma addr, bfd_vma base, bool relative)
327{
328 struct simple_memory_operand *op = malloc (sizeof (*op));
329
330 ((struct operand *)op)->cl = OPND_CL_SIMPLE_MEMORY;
331 op->addr = addr;
332 op->base = base;
333 op->relative = relative;
334 ((struct operand *)op)->osize = -1;
335
336 assert (relative || base == 0);
337
338 return (struct operand *) op;
339}
340
341static struct operand *
342create_memory_operand (bool indirect, int base, int n_regs, int reg0, int reg1)
343{
344 struct memory_operand *op = malloc (sizeof (*op));
345
346 ((struct operand *)op)->cl = OPND_CL_MEMORY;
347 op->indirect = indirect;
348 op->base_offset = base;
349 op->mutation = OPND_RM_NONE;
350 op->n_regs = n_regs;
351 op->regs[0] = reg0;
352 op->regs[1] = reg1;
353 ((struct operand *)op)->osize = -1;
354
355 return (struct operand *) op;
356}
357
358static struct operand *
359create_memory_auto_operand (enum op_reg_mutation mutation, int reg)
360{
361 struct memory_operand *op = malloc (sizeof (*op));
362
363 ((struct operand *)op)->cl = OPND_CL_MEMORY;
364 op->indirect = false;
365 op->base_offset = 0;
366 op->mutation = mutation;
367 op->n_regs = 1;
368 op->regs[0] = reg;
369 op->regs[1] = -1;
370 ((struct operand *)op)->osize = -1;
371
372 return (struct operand *) op;
373}
374
375\f
376
377static void
e7c22a69
AM		 378z_ext24_decode (struct mem_read_abstraction_base *mra, int *n_operands,
379 struct operand **operand)
ef1ad42b
JD		 380{
381 uint8_t buffer[3];
382 int status = mra->read (mra, 0, 3, buffer);
383 if (status < 0)
384 return;
385
386 int i;
387 uint32_t addr = 0;
388 for (i = 0; i < 3; ++i)
389 {
390 addr <<= 8;
391 addr |= buffer[i];
392 }
393
394 operand[(*n_operands)++] = create_simple_memory_operand (addr, 0, false);
395}
396
397
398static uint32_t
e7c22a69
AM		 399z_decode_signed_value (struct mem_read_abstraction_base *mra, int offset,
400 short size)
ef1ad42b
JD		 401{
402 assert (size >0);
403 assert (size <= 4);
404 bfd_byte buffer[4];
405 if (0 > mra->read (mra, offset, size, buffer))
406 {
407 return 0;
408 }
409
410 int i;
411 uint32_t value = 0;
412 for (i = 0; i < size; ++i)
205c426a 413 value = (value << 8) | buffer[i];
ef1ad42b
JD		 414
415 if (buffer[0] & 0x80)
416 {
417 /* Deal with negative values */
418 value -= 0x1UL << (size * 8);
419 }
420 return value;
421}
422
423static uint32_t
424decode_signed_value (struct mem_read_abstraction_base *mra, short size)
425{
426 return z_decode_signed_value (mra, 0, size);
427}
428
429static void
430x_imm1 (struct mem_read_abstraction_base *mra,
431 int offset,
432 int *n_operands, struct operand **operand)
433{
434 bfd_byte byte;
435 int status = mra->read (mra, offset, 1, &byte);
436 if (status < 0)
437 return;
438
439 operand[(*n_operands)++] = create_immediate_operand (byte);
440}
441
442/* An eight bit immediate operand. */
443static void
444imm1_decode (struct mem_read_abstraction_base *mra,
e7c22a69 445 int *n_operands, struct operand **operand)
ef1ad42b
JD		 446{
447 x_imm1 (mra, 0, n_operands, operand);
448}
449
450static void
451trap_decode (struct mem_read_abstraction_base *mra,
452 int *n_operands, struct operand **operand)
453{
454 x_imm1 (mra, -1, n_operands, operand);
455}
456
457
458static struct operand *
459x_opr_decode_with_size (struct mem_read_abstraction_base *mra, int offset,
460 short osize)
461{
462 bfd_byte postbyte;
463 int status = mra->read (mra, offset, 1, &postbyte);
464 if (status < 0)
465 return NULL;
466 offset++;
467
468 enum OPR_MODE mode = -1;
469 size_t i;
470 for (i = 0; i < sizeof (opr_pb) / sizeof (opr_pb[0]); ++i)
471 {
472 const struct opr_pb *pb = opr_pb + i;
473 if ((postbyte & pb->mask) == pb->value)
474 {
475 mode = pb->mode;
476 break;
477 }
478 }
479
480 struct operand *operand = NULL;
481 switch (mode)
482 {
483 case OPR_IMMe4:
484 {
485 int n;
486 uint8_t x = (postbyte & 0x0F);
487 if (x == 0)
488 n = -1;
489 else
490 n = x;
491
e7c22a69 492 operand = create_immediate_operand (n);
ef1ad42b
JD		 493 break;
494 }
495 case OPR_REG:
496 {
497 uint8_t x = (postbyte & 0x07);
e7c22a69 498 operand = create_register_operand (x);
ef1ad42b
JD		 499 break;
500 }
501 case OPR_OFXYS:
502 {
e7c22a69 503 operand = create_memory_operand (false, postbyte & 0x0F, 1,
ef1ad42b
JD		 504 xysp_reg_from_postbyte (postbyte), -1);
505 break;
506 }
507 case OPR_REG_DIRECT:
508 {
e7c22a69 509 operand = create_memory_operand (false, 0, 2, postbyte & 0x07,
ef1ad42b
JD		 510 xysp_reg_from_postbyte (postbyte));
511 break;
512 }
513 case OPR_REG_INDIRECT:
514 {
e7c22a69 515 operand = create_memory_operand (true, 0, 2, postbyte & 0x07,
ef1ad42b
JD		 516 (postbyte & 0x10) ? REG_Y : REG_X);
517 break;
518 }
519
520 case OPR_IDX_INDIRECT:
521 {
522 uint8_t x1;
523 mra->read (mra, offset, 1, &x1);
524 int idx = x1;
525
526 if (postbyte & 0x01)
527 {
528 /* Deal with negative values */
529 idx -= 0x1UL << 8;
530 }
531
e7c22a69 532 operand = create_memory_operand (true, idx, 1,
ef1ad42b
JD		 533 xysp_reg_from_postbyte (postbyte), -1);
534 break;
535 }
536
537 case OPR_IDX3_DIRECT:
538 {
539 uint8_t x[3];
540 mra->read (mra, offset, 3, x);
541 int idx = x[0] << 16 | x[1] << 8 | x[2];
542
543 if (x[0] & 0x80)
544 {
545 /* Deal with negative values */
546 idx -= 0x1UL << 24;
547 }
548
e7c22a69 549 operand = create_memory_operand (false, idx, 1,
ef1ad42b
JD		 550 xysp_reg_from_postbyte (postbyte), -1);
551 break;
552 }
553
554 case OPR_IDX3_DIRECT_REG:
555 {
556 uint8_t x[3];
557 mra->read (mra, offset, 3, x);
558 int idx = x[0] << 16 | x[1] << 8 | x[2];
559
560 if (x[0] & 0x80)
561 {
562 /* Deal with negative values */
563 idx -= 0x1UL << 24;
564 }
565
e7c22a69 566 operand = create_memory_operand (false, idx, 1, postbyte & 0x07, -1);
ef1ad42b
JD		 567 break;
568 }
569
570 case OPR_IDX3_INDIRECT:
571 {
572 uint8_t x[3];
573 mra->read (mra, offset, 3, x);
574 int idx = x[0] << 16 | x[1] << 8 | x[2];
575
576 if (x[0] & 0x80)
577 {
578 /* Deal with negative values */
579 idx -= 0x1UL << 24;
580 }
581
582 operand = create_memory_operand (true, idx, 1,
583 xysp_reg_from_postbyte (postbyte), -1);
584 break;
585 }
586
587 case OPR_IDX_DIRECT:
588 {
589 uint8_t x1;
590 mra->read (mra, offset, 1, &x1);
591 int idx = x1;
592
593 if (postbyte & 0x01)
594 {
595 /* Deal with negative values */
596 idx -= 0x1UL << 8;
597 }
598
e7c22a69 599 operand = create_memory_operand (false, idx, 1,
ef1ad42b
JD		 600 xysp_reg_from_postbyte (postbyte), -1);
601 break;
602 }
603
604 case OPR_IDX2_REG:
605 {
606 uint8_t x[2];
607 mra->read (mra, offset, 2, x);
608 uint32_t idx = x[1] | x[0] << 8 ;
609 idx |= (postbyte & 0x30) << 12;
610
e7c22a69 611 operand = create_memory_operand (false, idx, 1, postbyte & 0x07, -1);
ef1ad42b
JD		 612 break;
613 }
614
615 case OPR_XY_PRE_INC:
616 {
617 operand = create_memory_auto_operand (OPND_RM_PRE_INC,
618 (postbyte & 0x10) ? REG_Y: REG_X);
619 break;
620 }
621 case OPR_XY_POST_INC:
622 {
623 operand = create_memory_auto_operand (OPND_RM_POST_INC,
624 (postbyte & 0x10) ? REG_Y: REG_X);
625 break;
626 }
627 case OPR_XY_PRE_DEC:
628 {
629 operand = create_memory_auto_operand (OPND_RM_PRE_DEC,
630 (postbyte & 0x10) ? REG_Y: REG_X);
631 break;
632 }
633 case OPR_XY_POST_DEC:
634 {
635 operand = create_memory_auto_operand (OPND_RM_POST_DEC,
636 (postbyte & 0x10) ? REG_Y: REG_X);
637 break;
638 }
639 case OPR_S_PRE_DEC:
640 {
641 operand = create_memory_auto_operand (OPND_RM_PRE_DEC, REG_S);
642 break;
643 }
644 case OPR_S_POST_INC:
645 {
646 operand = create_memory_auto_operand (OPND_RM_POST_INC, REG_S);
647 break;
648 }
649
650 case OPR_EXT18:
651 {
652 const size_t size = 2;
653 bfd_byte buffer[4];
654 status = mra->read (mra, offset, size, buffer);
655 if (status < 0)
656 operand = NULL;
657
658 uint32_t ext18 = 0;
659 for (i = 0; i < size; ++i)
660 {
661 ext18 <<= 8;
662 ext18 |= buffer[i];
663 }
664
665 ext18 |= (postbyte & 0x01) << 16;
666 ext18 |= (postbyte & 0x04) << 15;
667
668 operand = create_simple_memory_operand (ext18, 0, false);
669 break;
670 }
671
672 case OPR_EXT1:
673 {
674 uint8_t x1 = 0;
675 mra->read (mra, offset, 1, &x1);
676 int16_t addr;
677 addr = x1;
678 addr |= (postbyte & 0x3f) << 8;
679
680 operand = create_simple_memory_operand (addr, 0, false);
681 break;
682 }
683
684 case OPR_EXT3_DIRECT:
685 {
686 const size_t size = 3;
687 bfd_byte buffer[4];
688 status = mra->read (mra, offset, size, buffer);
689 if (status < 0)
690 operand = NULL;
691
692 uint32_t ext24 = 0;
693 for (i = 0; i < size; ++i)
694 {
695 ext24 |= buffer[i] << (8 * (size - i - 1));
696 }
697
698 operand = create_simple_memory_operand (ext24, 0, false);
699 break;
700 }
701
702 case OPR_EXT3_INDIRECT:
703 {
704 const size_t size = 3;
705 bfd_byte buffer[4];
706 status = mra->read (mra, offset, size, buffer);
707 if (status < 0)
708 operand = NULL;
709
710 uint32_t ext24 = 0;
711 for (i = 0; i < size; ++i)
712 {
713 ext24 |= buffer[i] << (8 * (size - i - 1));
714 }
715
e7c22a69 716 operand = create_memory_operand (true, ext24, 0, -1, -1);
ef1ad42b
JD		 717 break;
718 }
719
720 default:
721 printf ("Unknown OPR mode #0x%x (%d)", postbyte, mode);
722 abort ();
723 }
724
725 operand->osize = osize;
726
727 return operand;
728}
729
730static struct operand *
731x_opr_decode (struct mem_read_abstraction_base *mra, int offset)
732{
733 return x_opr_decode_with_size (mra, offset, -1);
734}
735
736static void
737z_opr_decode (struct mem_read_abstraction_base *mra,
738 int *n_operands, struct operand **operand)
739{
740 operand[(*n_operands)++] = x_opr_decode (mra, 0);
741}
742
743static void
744z_opr_decode2 (struct mem_read_abstraction_base *mra,
745 int *n_operands, struct operand **operand)
746{
747 int n = x_opr_n_bytes (mra, 0);
748
749 operand[(*n_operands)++] = x_opr_decode (mra, 0);
750 operand[(*n_operands)++] = x_opr_decode (mra, n);
751}
752
753static void
754imm1234 (struct mem_read_abstraction_base *mra, int base,
755 int *n_operands, struct operand **operand)
756{
757 bfd_byte opcode;
758 int status = mra->read (mra, -1, 1, &opcode);
759 if (status < 0)
760 return;
761
762 opcode -= base;
763
764 int size = registers[opcode & 0xF].bytes;
765
766 uint32_t imm = decode_signed_value (mra, size);
767
768 operand[(*n_operands)++] = create_immediate_operand (imm);
769}
770
771
772/* Special case of LD and CMP with register S and IMM operand */
773static void
774reg_s_imm (struct mem_read_abstraction_base *mra, int *n_operands,
775 struct operand **operand)
776{
777 operand[(*n_operands)++] = create_register_operand (REG_S);
778
779 uint32_t imm = decode_signed_value (mra, 3);
780 operand[(*n_operands)++] = create_immediate_operand (imm);
781}
782
783/* Special case of LD, CMP and ST with register S and OPR operand */
784static void
785reg_s_opr (struct mem_read_abstraction_base *mra, int *n_operands,
786 struct operand **operand)
787{
788 operand[(*n_operands)++] = create_register_operand (REG_S);
789 operand[(*n_operands)++] = x_opr_decode (mra, 0);
790}
791
792static void
793z_imm1234_8base (struct mem_read_abstraction_base *mra, int *n_operands,
794 struct operand **operand)
795{
796 imm1234 (mra, 8, n_operands, operand);
797}
798
799static void
800z_imm1234_0base (struct mem_read_abstraction_base *mra, int *n_operands,
801 struct operand **operand)
802{
803 imm1234 (mra, 0, n_operands, operand);
804}
805
806
807static void
808z_tfr (struct mem_read_abstraction_base *mra, int *n_operands,
809 struct operand **operand)
810{
811 bfd_byte byte;
812 int status = mra->read (mra, 0, 1, &byte);
813 if (status < 0)
814 return;
815
816 operand[(*n_operands)++] = create_register_operand (byte >> 4);
817 operand[(*n_operands)++] = create_register_operand (byte & 0x0F);
818}
819
820static void
821z_reg (struct mem_read_abstraction_base *mra, int *n_operands,
822 struct operand **operand)
823{
824 bfd_byte byte;
825 int status = mra->read (mra, -1, 1, &byte);
826 if (status < 0)
827 return;
828
829 operand[(*n_operands)++] = create_register_operand (byte & 0x07);
830}
831
832
833static void
834reg_xy (struct mem_read_abstraction_base *mra,
835 int *n_operands, struct operand **operand)
836{
837 bfd_byte byte;
838 int status = mra->read (mra, -1, 1, &byte);
839 if (status < 0)
840 return;
841
842 operand[(*n_operands)++] =
843 create_register_operand ((byte & 0x01) ? REG_Y : REG_X);
844}
845
846static void
847lea_reg_xys_opr (struct mem_read_abstraction_base *mra,
848 int *n_operands, struct operand **operand)
849{
850 bfd_byte byte;
851 int status = mra->read (mra, -1, 1, &byte);
852 if (status < 0)
853 return;
854
855 int reg_xys = -1;
856 switch (byte & 0x03)
857 {
858 case 0x00:
859 reg_xys = REG_X;
860 break;
861 case 0x01:
862 reg_xys = REG_Y;
863 break;
864 case 0x02:
865 reg_xys = REG_S;
866 break;
867 }
868
869 operand[(*n_operands)++] = create_register_operand (reg_xys);
870 operand[(*n_operands)++] = x_opr_decode (mra, 0);
871}
872
873static void
874lea_reg_xys (struct mem_read_abstraction_base *mra,
875 int *n_operands, struct operand **operand)
876{
877 bfd_byte byte;
878 int status = mra->read (mra, -1, 1, &byte);
879 if (status < 0)
880 return;
881
882 int reg_n = -1;
883 switch (byte & 0x03)
884 {
885 case 0x00:
886 reg_n = REG_X;
887 break;
888 case 0x01:
889 reg_n = REG_Y;
890 break;
891 case 0x02:
892 reg_n = REG_S;
893 break;
894 }
895
896 status = mra->read (mra, 0, 1, &byte);
897 if (status < 0)
898 return;
899
900 operand[(*n_operands)++] = create_register_operand (reg_n);
901 operand[(*n_operands)++] = create_memory_operand (false, (int8_t) byte,
902 1, reg_n, -1);
903}
904
905
906/* PC Relative offsets of size 15 or 7 bits */
907static void
908rel_15_7 (struct mem_read_abstraction_base *mra, int offset,
909 int *n_operands, struct operand **operands)
910{
911 bfd_byte upper;
912 int status = mra->read (mra, offset - 1, 1, &upper);
913 if (status < 0)
914 return;
915
916 bool rel_size = (upper & 0x80);
917
918 int16_t addr = upper;
919 if (rel_size)
920 {
921 /* 15 bits. Get the next byte */
922 bfd_byte lower;
923 status = mra->read (mra, offset, 1, &lower);
924 if (status < 0)
925 return;
926
927 addr <<= 8;
928 addr |= lower;
929 addr &= 0x7FFF;
930
931 bool negative = (addr & 0x4000);
932 addr &= 0x3FFF;
933 if (negative)
934 addr = addr - 0x4000;
935 }
936 else
937 {
938 /* 7 bits. */
939 bool negative = (addr & 0x40);
940 addr &= 0x3F;
941 if (negative)
942 addr = addr - 0x40;
943 }
944
945 operands[(*n_operands)++] =
946 create_simple_memory_operand (addr, mra->posn (mra) - 1, true);
947}
948
949
950/* PC Relative offsets of size 15 or 7 bits */
951static void
952decode_rel_15_7 (struct mem_read_abstraction_base *mra,
953 int *n_operands, struct operand **operand)
954{
955 rel_15_7 (mra, 1, n_operands, operand);
956}
957
958static int shift_n_bytes (struct mem_read_abstraction_base *);
959static int mov_imm_opr_n_bytes (struct mem_read_abstraction_base *);
960static int loop_prim_n_bytes (struct mem_read_abstraction_base *);
961static int bm_rel_n_bytes (struct mem_read_abstraction_base *);
962static int mul_n_bytes (struct mem_read_abstraction_base *);
963static int bm_n_bytes (struct mem_read_abstraction_base *);
964
965static void psh_pul_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand);
966static void shift_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand);
967static void mul_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand);
968static void bm_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand);
969static void bm_rel_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand);
970static void mov_imm_opr (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand);
971static void loop_primitive_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operands);
972static void bit_field_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operands);
973static void exg_sex_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operands);
974
975
e5a557ac
JD		 976static enum optr shift_discrim (struct mem_read_abstraction_base *mra, enum optr hint);
977static enum optr psh_pul_discrim (struct mem_read_abstraction_base *mra, enum optr hint);
978static enum optr mul_discrim (struct mem_read_abstraction_base *mra, enum optr hint);
979static enum optr loop_primitive_discrim (struct mem_read_abstraction_base *mra, enum optr hint);
980static enum optr bit_field_discrim (struct mem_read_abstraction_base *mra, enum optr hint);
981static enum optr exg_sex_discrim (struct mem_read_abstraction_base *mra, enum optr hint);
ef1ad42b
JD		 982
983
984static void
985cmp_xy (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED,
986 int *n_operands, struct operand **operand)
987{
988 operand[(*n_operands)++] = create_register_operand (REG_X);
989 operand[(*n_operands)++] = create_register_operand (REG_Y);
990}
991
992static void
993sub_d6_x_y (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED,
994 int *n_operands, struct operand **operand)
995{
996 operand[(*n_operands)++] = create_register_operand (REG_D6);
997 operand[(*n_operands)++] = create_register_operand (REG_X);
998 operand[(*n_operands)++] = create_register_operand (REG_Y);
999}
1000
1001static void
1002sub_d6_y_x (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED,
1003 int *n_operands, struct operand **operand)
1004{
1005 operand[(*n_operands)++] = create_register_operand (REG_D6);
1006 operand[(*n_operands)++] = create_register_operand (REG_Y);
1007 operand[(*n_operands)++] = create_register_operand (REG_X);
1008}
1009
e7c22a69
AM		 1010static void
1011ld_18bit_decode (struct mem_read_abstraction_base *mra, int *n_operands,
1012 struct operand **operand);
ef1ad42b 1013
e5a557ac
JD		 1014static enum optr
1015mul_discrim (struct mem_read_abstraction_base *mra, enum optr hint)
ef1ad42b
JD		 1016{
1017 uint8_t mb;
1018 int status = mra->read (mra, 0, 1, &mb);
1019 if (status < 0)
1020 return OP_INVALID;
1021
1022 bool signed_op = (mb & 0x80);
1023
1024 switch (hint)
1025 {
1026 case OPBASE_mul:
1027 return signed_op ? OP_muls : OP_mulu;
1028 break;
1029 case OPBASE_div:
1030 return signed_op ? OP_divs : OP_divu;
1031 break;
1032 case OPBASE_mod:
1033 return signed_op ? OP_mods : OP_modu;
1034 break;
1035 case OPBASE_mac:
1036 return signed_op ? OP_macs : OP_macu;
1037 break;
1038 case OPBASE_qmul:
1039 return signed_op ? OP_qmuls : OP_qmulu;
1040 break;
1041 default:
1042 abort ();
1043 }
1044
1045 return OP_INVALID;
1046}
1047
1048struct opcode
1049{
1050 /* The operation that this opcode performs. */
e5a557ac 1051 enum optr operator;
ef1ad42b
JD		 1052
1053 /* The size of this operation. May be -1 if it is implied
1054 in the operands or if size is not applicable. */
1055 short osize;
1056
1057 /* Some operations need this function to work out which operation
1058 is intended. */
1059 discriminator_f discriminator;
1060
1061 /* A function returning the number of bytes in this instruction. */
1062 insn_bytes_f insn_bytes;
1063
1064 operands_f operands;
1065 operands_f operands2;
1066};
1067
1068static const struct opcode page2[] =
1069 {
1070 [0x00] = {OP_ld, -1, 0, opr_n_bytes_p1, reg_s_opr, 0},
1071 [0x01] = {OP_st, -1, 0, opr_n_bytes_p1, reg_s_opr, 0},
1072 [0x02] = {OP_cmp, -1, 0, opr_n_bytes_p1, reg_s_opr, 0},
1073 [0x03] = {OP_ld, -1, 0, four, reg_s_imm, 0},
1074 [0x04] = {OP_cmp, -1, 0, four, reg_s_imm, 0},
1075 [0x05] = {OP_stop, -1, 0, single, 0, 0},
1076 [0x06] = {OP_wai, -1, 0, single, 0, 0},
1077 [0x07] = {OP_sys, -1, 0, single, 0, 0},
1078 [0x08] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, /* BFEXT / BFINS */
1079 [0x09] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0},
1080 [0x0a] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0},
1081 [0x0b] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0},
1082 [0x0c] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0},
1083 [0x0d] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0},
1084 [0x0e] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0},
1085 [0x0f] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0},
1086 [0x10] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1087 [0x11] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1088 [0x12] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1089 [0x13] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1090 [0x14] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1091 [0x15] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1092 [0x16] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1093 [0x17] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1094 [0x18] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1095 [0x19] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1096 [0x1a] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1097 [0x1b] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1098 [0x1c] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1099 [0x1d] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1100 [0x1e] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1101 [0x1f] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1102 [0x20] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1103 [0x21] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1104 [0x22] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1105 [0x23] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1106 [0x24] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1107 [0x25] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1108 [0x26] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1109 [0x27] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1110 [0x28] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1111 [0x29] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1112 [0x2a] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1113 [0x2b] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1114 [0x2c] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1115 [0x2d] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1116 [0x2e] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1117 [0x2f] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1118 [0x30] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1119 [0x31] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1120 [0x32] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1121 [0x33] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1122 [0x34] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1123 [0x35] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1124 [0x36] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1125 [0x37] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1126 [0x38] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1127 [0x39] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1128 [0x3a] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1129 [0x3b] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1130 [0x3c] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1131 [0x3d] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1132 [0x3e] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1133 [0x3f] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1134 [0x40] = {OP_abs, -1, 0, single, z_reg, 0},
1135 [0x41] = {OP_abs, -1, 0, single, z_reg, 0},
1136 [0x42] = {OP_abs, -1, 0, single, z_reg, 0},
1137 [0x43] = {OP_abs, -1, 0, single, z_reg, 0},
1138 [0x44] = {OP_abs, -1, 0, single, z_reg, 0},
1139 [0x45] = {OP_abs, -1, 0, single, z_reg, 0},
1140 [0x46] = {OP_abs, -1, 0, single, z_reg, 0},
1141 [0x47] = {OP_abs, -1, 0, single, z_reg, 0},
1142 [0x48] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1143 [0x49] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1144 [0x4a] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1145 [0x4b] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1146 [0x4c] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1147 [0x4d] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1148 [0x4e] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1149 [0x4f] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1150 [0x50] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base},
1151 [0x51] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base},
1152 [0x52] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base},
1153 [0x53] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base},
1154 [0x54] = {OP_adc, -1, 0, two, z_reg, z_imm1234_0base},
1155 [0x55] = {OP_adc, -1, 0, two, z_reg, z_imm1234_0base},
1156 [0x56] = {OP_adc, -1, 0, five, z_reg, z_imm1234_0base},
1157 [0x57] = {OP_adc, -1, 0, five, z_reg, z_imm1234_0base},
1158 [0x58] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base},
1159 [0x59] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base},
1160 [0x5a] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base},
1161 [0x5b] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base},
1162 [0x5c] = {OP_bit, -1, 0, two, z_reg, z_imm1234_8base},
1163 [0x5d] = {OP_bit, -1, 0, two, z_reg, z_imm1234_8base},
1164 [0x5e] = {OP_bit, -1, 0, five, z_reg, z_imm1234_8base},
1165 [0x5f] = {OP_bit, -1, 0, five, z_reg, z_imm1234_8base},
1166 [0x60] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1167 [0x61] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1168 [0x62] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1169 [0x63] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1170 [0x64] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1171 [0x65] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1172 [0x66] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1173 [0x67] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1174 [0x68] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1175 [0x69] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1176 [0x6a] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1177 [0x6b] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1178 [0x6c] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1179 [0x6d] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1180 [0x6e] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1181 [0x6f] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1182 [0x70] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base},
1183 [0x71] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base},
1184 [0x72] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base},
1185 [0x73] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base},
1186 [0x74] = {OP_sbc, -1, 0, two, z_reg, z_imm1234_0base},
1187 [0x75] = {OP_sbc, -1, 0, two, z_reg, z_imm1234_0base},
1188 [0x76] = {OP_sbc, -1, 0, five, z_reg, z_imm1234_0base},
1189 [0x77] = {OP_sbc, -1, 0, five, z_reg, z_imm1234_0base},
1190 [0x78] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base},
1191 [0x79] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base},
1192 [0x7a] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base},
1193 [0x7b] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base},
1194 [0x7c] = {OP_eor, -1, 0, two, z_reg, z_imm1234_8base},
1195 [0x7d] = {OP_eor, -1, 0, two, z_reg, z_imm1234_8base},
1196 [0x7e] = {OP_eor, -1, 0, five, z_reg, z_imm1234_8base},
1197 [0x7f] = {OP_eor, -1, 0, five, z_reg, z_imm1234_8base},
1198 [0x80] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1199 [0x81] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1200 [0x82] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1201 [0x83] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1202 [0x84] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1203 [0x85] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1204 [0x86] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1205 [0x87] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1206 [0x88] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1207 [0x89] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1208 [0x8a] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1209 [0x8b] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1210 [0x8c] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1211 [0x8d] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1212 [0x8e] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1213 [0x8f] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1214 [0x90] = {OP_rti, -1, 0, single, 0, 0},
1215 [0x91] = {OP_clb, -1, 0, two, z_tfr, 0},
1216 [0x92] = {OP_trap, -1, 0, single, trap_decode, 0},
1217 [0x93] = {OP_trap, -1, 0, single, trap_decode, 0},
1218 [0x94] = {OP_trap, -1, 0, single, trap_decode, 0},
1219 [0x95] = {OP_trap, -1, 0, single, trap_decode, 0},
1220 [0x96] = {OP_trap, -1, 0, single, trap_decode, 0},
1221 [0x97] = {OP_trap, -1, 0, single, trap_decode, 0},
1222 [0x98] = {OP_trap, -1, 0, single, trap_decode, 0},
1223 [0x99] = {OP_trap, -1, 0, single, trap_decode, 0},
1224 [0x9a] = {OP_trap, -1, 0, single, trap_decode, 0},
1225 [0x9b] = {OP_trap, -1, 0, single, trap_decode, 0},
1226 [0x9c] = {OP_trap, -1, 0, single, trap_decode, 0},
1227 [0x9d] = {OP_trap, -1, 0, single, trap_decode, 0},
1228 [0x9e] = {OP_trap, -1, 0, single, trap_decode, 0},
1229 [0x9f] = {OP_trap, -1, 0, single, trap_decode, 0},
1230 [0xa0] = {OP_sat, -1, 0, single, z_reg, 0},
1231 [0xa1] = {OP_sat, -1, 0, single, z_reg, 0},
1232 [0xa2] = {OP_sat, -1, 0, single, z_reg, 0},
1233 [0xa3] = {OP_sat, -1, 0, single, z_reg, 0},
1234 [0xa4] = {OP_sat, -1, 0, single, z_reg, 0},
1235 [0xa5] = {OP_sat, -1, 0, single, z_reg, 0},
1236 [0xa6] = {OP_sat, -1, 0, single, z_reg, 0},
1237 [0xa7] = {OP_sat, -1, 0, single, z_reg, 0},
1238 [0xa8] = {OP_trap, -1, 0, single, trap_decode, 0},
1239 [0xa9] = {OP_trap, -1, 0, single, trap_decode, 0},
1240 [0xaa] = {OP_trap, -1, 0, single, trap_decode, 0},
1241 [0xab] = {OP_trap, -1, 0, single, trap_decode, 0},
1242 [0xac] = {OP_trap, -1, 0, single, trap_decode, 0},
1243 [0xad] = {OP_trap, -1, 0, single, trap_decode, 0},
1244 [0xae] = {OP_trap, -1, 0, single, trap_decode, 0},
1245 [0xaf] = {OP_trap, -1, 0, single, trap_decode, 0},
1246 [0xb0] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1247 [0xb1] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1248 [0xb2] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1249 [0xb3] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1250 [0xb4] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1251 [0xb5] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1252 [0xb6] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1253 [0xb7] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1254 [0xb8] = {OP_trap, -1, 0, single, trap_decode, 0},
1255 [0xb9] = {OP_trap, -1, 0, single, trap_decode, 0},
1256 [0xba] = {OP_trap, -1, 0, single, trap_decode, 0},
1257 [0xbb] = {OP_trap, -1, 0, single, trap_decode, 0},
1258 [0xbc] = {OP_trap, -1, 0, single, trap_decode, 0},
1259 [0xbd] = {OP_trap, -1, 0, single, trap_decode, 0},
1260 [0xbe] = {OP_trap, -1, 0, single, trap_decode, 0},
1261 [0xbf] = {OP_trap, -1, 0, single, trap_decode, 0},
1262 [0xc0] = {OP_trap, -1, 0, single, trap_decode, 0},
1263 [0xc1] = {OP_trap, -1, 0, single, trap_decode, 0},
1264 [0xc2] = {OP_trap, -1, 0, single, trap_decode, 0},
1265 [0xc3] = {OP_trap, -1, 0, single, trap_decode, 0},
1266 [0xc4] = {OP_trap, -1, 0, single, trap_decode, 0},
1267 [0xc5] = {OP_trap, -1, 0, single, trap_decode, 0},
1268 [0xc6] = {OP_trap, -1, 0, single, trap_decode, 0},
1269 [0xc7] = {OP_trap, -1, 0, single, trap_decode, 0},
1270 [0xc8] = {OP_trap, -1, 0, single, trap_decode, 0},
1271 [0xc9] = {OP_trap, -1, 0, single, trap_decode, 0},
1272 [0xca] = {OP_trap, -1, 0, single, trap_decode, 0},
1273 [0xcb] = {OP_trap, -1, 0, single, trap_decode, 0},
1274 [0xcc] = {OP_trap, -1, 0, single, trap_decode, 0},
1275 [0xcd] = {OP_trap, -1, 0, single, trap_decode, 0},
1276 [0xce] = {OP_trap, -1, 0, single, trap_decode, 0},
1277 [0xcf] = {OP_trap, -1, 0, single, trap_decode, 0},
1278 [0xd0] = {OP_trap, -1, 0, single, trap_decode, 0},
1279 [0xd1] = {OP_trap, -1, 0, single, trap_decode, 0},
1280 [0xd2] = {OP_trap, -1, 0, single, trap_decode, 0},
1281 [0xd3] = {OP_trap, -1, 0, single, trap_decode, 0},
1282 [0xd4] = {OP_trap, -1, 0, single, trap_decode, 0},
1283 [0xd5] = {OP_trap, -1, 0, single, trap_decode, 0},
1284 [0xd6] = {OP_trap, -1, 0, single, trap_decode, 0},
1285 [0xd7] = {OP_trap, -1, 0, single, trap_decode, 0},
1286 [0xd8] = {OP_trap, -1, 0, single, trap_decode, 0},
1287 [0xd9] = {OP_trap, -1, 0, single, trap_decode, 0},
1288 [0xda] = {OP_trap, -1, 0, single, trap_decode, 0},
1289 [0xdb] = {OP_trap, -1, 0, single, trap_decode, 0},
1290 [0xdc] = {OP_trap, -1, 0, single, trap_decode, 0},
1291 [0xdd] = {OP_trap, -1, 0, single, trap_decode, 0},
1292 [0xde] = {OP_trap, -1, 0, single, trap_decode, 0},
1293 [0xdf] = {OP_trap, -1, 0, single, trap_decode, 0},
1294 [0xe0] = {OP_trap, -1, 0, single, trap_decode, 0},
1295 [0xe1] = {OP_trap, -1, 0, single, trap_decode, 0},
1296 [0xe2] = {OP_trap, -1, 0, single, trap_decode, 0},
1297 [0xe3] = {OP_trap, -1, 0, single, trap_decode, 0},
1298 [0xe4] = {OP_trap, -1, 0, single, trap_decode, 0},
1299 [0xe5] = {OP_trap, -1, 0, single, trap_decode, 0},
1300 [0xe6] = {OP_trap, -1, 0, single, trap_decode, 0},
1301 [0xe7] = {OP_trap, -1, 0, single, trap_decode, 0},
1302 [0xe8] = {OP_trap, -1, 0, single, trap_decode, 0},
1303 [0xe9] = {OP_trap, -1, 0, single, trap_decode, 0},
1304 [0xea] = {OP_trap, -1, 0, single, trap_decode, 0},
1305 [0xeb] = {OP_trap, -1, 0, single, trap_decode, 0},
1306 [0xec] = {OP_trap, -1, 0, single, trap_decode, 0},
1307 [0xed] = {OP_trap, -1, 0, single, trap_decode, 0},
1308 [0xee] = {OP_trap, -1, 0, single, trap_decode, 0},
1309 [0xef] = {OP_trap, -1, 0, single, trap_decode, 0},
1310 [0xf0] = {OP_trap, -1, 0, single, trap_decode, 0},
1311 [0xf1] = {OP_trap, -1, 0, single, trap_decode, 0},
1312 [0xf2] = {OP_trap, -1, 0, single, trap_decode, 0},
1313 [0xf3] = {OP_trap, -1, 0, single, trap_decode, 0},
1314 [0xf4] = {OP_trap, -1, 0, single, trap_decode, 0},
1315 [0xf5] = {OP_trap, -1, 0, single, trap_decode, 0},
1316 [0xf6] = {OP_trap, -1, 0, single, trap_decode, 0},
1317 [0xf7] = {OP_trap, -1, 0, single, trap_decode, 0},
1318 [0xf8] = {OP_trap, -1, 0, single, trap_decode, 0},
1319 [0xf9] = {OP_trap, -1, 0, single, trap_decode, 0},
1320 [0xfa] = {OP_trap, -1, 0, single, trap_decode, 0},
1321 [0xfb] = {OP_trap, -1, 0, single, trap_decode, 0},
1322 [0xfc] = {OP_trap, -1, 0, single, trap_decode, 0},
1323 [0xfd] = {OP_trap, -1, 0, single, trap_decode, 0},
1324 [0xfe] = {OP_trap, -1, 0, single, trap_decode, 0},
1325 [0xff] = {OP_trap, -1, 0, single, trap_decode, 0},
1326 };
1327
1328static const struct opcode page1[] =
1329 {
1330 [0x00] = {OP_bgnd, -1, 0, single, 0, 0},
1331 [0x01] = {OP_nop, -1, 0, single, 0, 0},
1332 [0x02] = {OP_brclr, -1, 0, bm_rel_n_bytes, bm_rel_decode, 0},
1333 [0x03] = {OP_brset, -1, 0, bm_rel_n_bytes, bm_rel_decode, 0},
1334 [0x04] = {0xFFFF, -1, psh_pul_discrim, two, psh_pul_decode, 0}, /* psh/pul */
1335 [0x05] = {OP_rts, -1, 0, single, 0, 0},
1336 [0x06] = {OP_lea, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1337 [0x07] = {OP_lea, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1338 [0x08] = {OP_lea, -1, 0, opr_n_bytes_p1, lea_reg_xys_opr, 0},
1339 [0x09] = {OP_lea, -1, 0, opr_n_bytes_p1, lea_reg_xys_opr, 0},
1340 [0x0a] = {OP_lea, -1, 0, opr_n_bytes_p1, lea_reg_xys_opr, 0},
1341 [0x0b] = {0xFFFF, -1, loop_primitive_discrim, loop_prim_n_bytes, loop_primitive_decode, 0}, /* Loop primitives TBcc / DBcc */
1342 [0x0c] = {OP_mov, 0, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0},
1343 [0x0d] = {OP_mov, 1, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0},
1344 [0x0e] = {OP_mov, 2, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0},
1345 [0x0f] = {OP_mov, 3, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0},
1346 [0x10] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, /* lsr/lsl/asl/asr/rol/ror */
1347 [0x11] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0},
1348 [0x12] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0},
1349 [0x13] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0},
1350 [0x14] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0},
1351 [0x15] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0},
1352 [0x16] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0},
1353 [0x17] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0},
1354 [0x18] = {OP_lea, -1, 0, two, lea_reg_xys, NULL},
1355 [0x19] = {OP_lea, -1, 0, two, lea_reg_xys, NULL},
1356 [0x1a] = {OP_lea, -1, 0, two, lea_reg_xys, NULL},
1357 /* 0x1b PG2 */
1358 [0x1c] = {OP_mov, 0, 0, opr_n_bytes2, z_opr_decode2, 0},
1359 [0x1d] = {OP_mov, 1, 0, opr_n_bytes2, z_opr_decode2, 0},
1360 [0x1e] = {OP_mov, 2, 0, opr_n_bytes2, z_opr_decode2, 0},
1361 [0x1f] = {OP_mov, 3, 0, opr_n_bytes2, z_opr_decode2, 0},
1362 [0x20] = {OP_bra, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1363 [0x21] = {OP_bsr, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1364 [0x22] = {OP_bhi, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1365 [0x23] = {OP_bls, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1366 [0x24] = {OP_bcc, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1367 [0x25] = {OP_bcs, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1368 [0x26] = {OP_bne, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1369 [0x27] = {OP_beq, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1370 [0x28] = {OP_bvc, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1371 [0x29] = {OP_bvs, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1372 [0x2a] = {OP_bpl, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1373 [0x2b] = {OP_bmi, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1374 [0x2c] = {OP_bge, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1375 [0x2d] = {OP_blt, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1376 [0x2e] = {OP_bgt, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1377 [0x2f] = {OP_ble, -1, 0, pcrel_15bit, decode_rel_15_7, 0},
1378 [0x30] = {OP_inc, -1, 0, single, z_reg, 0},
1379 [0x31] = {OP_inc, -1, 0, single, z_reg, 0},
1380 [0x32] = {OP_inc, -1, 0, single, z_reg, 0},
1381 [0x33] = {OP_inc, -1, 0, single, z_reg, 0},
1382 [0x34] = {OP_inc, -1, 0, single, z_reg, 0},
1383 [0x35] = {OP_inc, -1, 0, single, z_reg, 0},
1384 [0x36] = {OP_inc, -1, 0, single, z_reg, 0},
1385 [0x37] = {OP_inc, -1, 0, single, z_reg, 0},
1386 [0x38] = {OP_clr, -1, 0, single, z_reg, 0},
1387 [0x39] = {OP_clr, -1, 0, single, z_reg, 0},
1388 [0x3a] = {OP_clr, -1, 0, single, z_reg, 0},
1389 [0x3b] = {OP_clr, -1, 0, single, z_reg, 0},
1390 [0x3c] = {OP_clr, -1, 0, single, z_reg, 0},
1391 [0x3d] = {OP_clr, -1, 0, single, z_reg, 0},
1392 [0x3e] = {OP_clr, -1, 0, single, z_reg, 0},
1393 [0x3f] = {OP_clr, -1, 0, single, z_reg, 0},
1394 [0x40] = {OP_dec, -1, 0, single, z_reg, 0},
1395 [0x41] = {OP_dec, -1, 0, single, z_reg, 0},
1396 [0x42] = {OP_dec, -1, 0, single, z_reg, 0},
1397 [0x43] = {OP_dec, -1, 0, single, z_reg, 0},
1398 [0x44] = {OP_dec, -1, 0, single, z_reg, 0},
1399 [0x45] = {OP_dec, -1, 0, single, z_reg, 0},
1400 [0x46] = {OP_dec, -1, 0, single, z_reg, 0},
1401 [0x47] = {OP_dec, -1, 0, single, z_reg, 0},
1402 [0x48] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1403 [0x49] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1404 [0x4a] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1405 [0x4b] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1406 [0x4c] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1407 [0x4d] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1408 [0x4e] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1409 [0x4f] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0},
1410 [0x50] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base},
1411 [0x51] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base},
1412 [0x52] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base},
1413 [0x53] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base},
1414 [0x54] = {OP_add, -1, 0, two, z_reg, z_imm1234_0base},
1415 [0x55] = {OP_add, -1, 0, two, z_reg, z_imm1234_0base},
1416 [0x56] = {OP_add, -1, 0, five, z_reg, z_imm1234_0base},
1417 [0x57] = {OP_add, -1, 0, five, z_reg, z_imm1234_0base},
1418 [0x58] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base},
1419 [0x59] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base},
1420 [0x5a] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base},
1421 [0x5b] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base},
1422 [0x5c] = {OP_and, -1, 0, two, z_reg, z_imm1234_8base},
1423 [0x5d] = {OP_and, -1, 0, two, z_reg, z_imm1234_8base},
1424 [0x5e] = {OP_and, -1, 0, five, z_reg, z_imm1234_8base},
1425 [0x5f] = {OP_and, -1, 0, five, z_reg, z_imm1234_8base},
1426 [0x60] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1427 [0x61] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1428 [0x62] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1429 [0x63] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1430 [0x64] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1431 [0x65] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1432 [0x66] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1433 [0x67] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1434 [0x68] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1435 [0x69] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1436 [0x6a] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1437 [0x6b] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1438 [0x6c] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1439 [0x6d] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1440 [0x6e] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1441 [0x6f] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1442 [0x70] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base},
1443 [0x71] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base},
1444 [0x72] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base},
1445 [0x73] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base},
1446 [0x74] = {OP_sub, -1, 0, two, z_reg, z_imm1234_0base},
1447 [0x75] = {OP_sub, -1, 0, two, z_reg, z_imm1234_0base},
1448 [0x76] = {OP_sub, -1, 0, five, z_reg, z_imm1234_0base},
1449 [0x77] = {OP_sub, -1, 0, five, z_reg, z_imm1234_0base},
1450 [0x78] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base},
1451 [0x79] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base},
1452 [0x7a] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base},
1453 [0x7b] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base},
1454 [0x7c] = {OP_or, -1, 0, two, z_reg, z_imm1234_8base},
1455 [0x7d] = {OP_or, -1, 0, two, z_reg, z_imm1234_8base},
1456 [0x7e] = {OP_or, -1, 0, five, z_reg, z_imm1234_8base},
1457 [0x7f] = {OP_or, -1, 0, five, z_reg, z_imm1234_8base},
1458 [0x80] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1459 [0x81] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1460 [0x82] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1461 [0x83] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1462 [0x84] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1463 [0x85] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1464 [0x86] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1465 [0x87] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1466 [0x88] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1467 [0x89] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1468 [0x8a] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1469 [0x8b] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1470 [0x8c] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1471 [0x8d] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1472 [0x8e] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1473 [0x8f] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1474 [0x90] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base},
1475 [0x91] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base},
1476 [0x92] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base},
1477 [0x93] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base},
1478 [0x94] = {OP_ld, -1, 0, two, z_reg, z_imm1234_0base},
1479 [0x95] = {OP_ld, -1, 0, two, z_reg, z_imm1234_0base},
1480 [0x96] = {OP_ld, -1, 0, five, z_reg, z_imm1234_0base},
1481 [0x97] = {OP_ld, -1, 0, five, z_reg, z_imm1234_0base},
1482 [0x98] = {OP_ld, -1, 0, four, reg_xy, z_imm1234_0base},
1483 [0x99] = {OP_ld, -1, 0, four, reg_xy, z_imm1234_0base},
1484 [0x9a] = {OP_clr, -1, 0, single, reg_xy, 0},
1485 [0x9b] = {OP_clr, -1, 0, single, reg_xy, 0},
1486 [0x9c] = {OP_inc, 0, 0, opr_n_bytes_p1, z_opr_decode, 0},
1487 [0x9d] = {OP_inc, 1, 0, opr_n_bytes_p1, z_opr_decode, 0},
1488 [0x9e] = {OP_tfr, -1, 0, two, z_tfr, NULL},
1489 [0x9f] = {OP_inc, 3, 0, opr_n_bytes_p1, z_opr_decode, 0},
1490 [0xa0] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1491 [0xa1] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1492 [0xa2] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1493 [0xa3] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1494 [0xa4] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1495 [0xa5] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1496 [0xa6] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1497 [0xa7] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1498 [0xa8] = {OP_ld, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode},
1499 [0xa9] = {OP_ld, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode},
1500 [0xaa] = {OP_jmp, -1, 0, opr_n_bytes_p1, z_opr_decode, 0},
1501 [0xab] = {OP_jsr, -1, 0, opr_n_bytes_p1, z_opr_decode, 0},
1502 [0xac] = {OP_dec, 0, 0, opr_n_bytes_p1, z_opr_decode, 0},
1503 [0xad] = {OP_dec, 1, 0, opr_n_bytes_p1, z_opr_decode, 0},
1504 [0xae] = {0xFFFF, -1, exg_sex_discrim, two, exg_sex_decode, 0}, /* EXG / SEX */
1505 [0xaf] = {OP_dec, 3, 0, opr_n_bytes_p1, 0, z_opr_decode},
1506 [0xb0] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1507 [0xb1] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1508 [0xb2] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1509 [0xb3] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1510 [0xb4] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1511 [0xb5] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1512 [0xb6] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1513 [0xb7] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode},
1514 [0xb8] = {OP_ld, -1, 0, four, reg_xy, z_ext24_decode},
1515 [0xb9] = {OP_ld, -1, 0, four, reg_xy, z_ext24_decode},
1516 [0xba] = {OP_jmp, -1, 0, four, z_ext24_decode, 0},
1517 [0xbb] = {OP_jsr, -1, 0, four, z_ext24_decode, 0},
1518 [0xbc] = {OP_clr, 0, 0, opr_n_bytes_p1, z_opr_decode, 0},
1519 [0xbd] = {OP_clr, 1, 0, opr_n_bytes_p1, z_opr_decode, 0},
1520 [0xbe] = {OP_clr, 2, 0, opr_n_bytes_p1, z_opr_decode, 0},
1521 [0xbf] = {OP_clr, 3, 0, opr_n_bytes_p1, z_opr_decode, 0},
1522 [0xc0] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1523 [0xc1] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1524 [0xc2] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1525 [0xc3] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1526 [0xc4] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1527 [0xc5] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1528 [0xc6] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1529 [0xc7] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1530 [0xc8] = {OP_st, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode},
1531 [0xc9] = {OP_st, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode},
1532 [0xca] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1533 [0xcb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1534 [0xcc] = {OP_com, 0, 0, opr_n_bytes_p1, NULL, z_opr_decode},
1535 [0xcd] = {OP_com, 1, 0, opr_n_bytes_p1, NULL, z_opr_decode},
1536 [0xce] = {OP_andcc, -1, 0, two, imm1_decode, 0},
1537 [0xcf] = {OP_com, 3, 0, opr_n_bytes_p1, NULL, z_opr_decode},
1538 [0xd0] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1539 [0xd1] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1540 [0xd2] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1541 [0xd3] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1542 [0xd4] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1543 [0xd5] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1544 [0xd6] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1545 [0xd7] = {OP_st, -1, 0, four, z_reg, z_ext24_decode},
1546 [0xd8] = {OP_st, -1, 0, four, reg_xy, z_ext24_decode},
1547 [0xd9] = {OP_st, -1, 0, four, reg_xy, z_ext24_decode},
1548 [0xda] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1549 [0xdb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1550 [0xdc] = {OP_neg, 0, 0, opr_n_bytes_p1, NULL, z_opr_decode},
1551 [0xdd] = {OP_neg, 1, 0, opr_n_bytes_p1, NULL, z_opr_decode},
1552 [0xde] = {OP_orcc, -1, 0, two, imm1_decode, 0},
1553 [0xdf] = {OP_neg, 3, 0, opr_n_bytes_p1, NULL, z_opr_decode},
1554 [0xe0] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base},
1555 [0xe1] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base},
1556 [0xe2] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base},
1557 [0xe3] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base},
1558 [0xe4] = {OP_cmp, -1, 0, two, z_reg, z_imm1234_0base},
1559 [0xe5] = {OP_cmp, -1, 0, two, z_reg, z_imm1234_0base},
1560 [0xe6] = {OP_cmp, -1, 0, five, z_reg, z_imm1234_0base},
1561 [0xe7] = {OP_cmp, -1, 0, five, z_reg, z_imm1234_0base},
1562 [0xe8] = {OP_cmp, -1, 0, four, reg_xy, z_imm1234_0base},
1563 [0xe9] = {OP_cmp, -1, 0, four, reg_xy, z_imm1234_0base},
1564 [0xea] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1565 [0xeb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1566 [0xec] = {OP_bclr, -1, 0, bm_n_bytes, bm_decode, 0},
1567 [0xed] = {OP_bset, -1, 0, bm_n_bytes, bm_decode, 0},
1568 [0xee] = {OP_btgl, -1, 0, bm_n_bytes, bm_decode, 0},
1569 [0xef] = {OP_INVALID, -1, 0, NULL, NULL, NULL}, /* SPARE */
1570 [0xf0] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1571 [0xf1] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1572 [0xf2] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1573 [0xf3] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1574 [0xf4] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1575 [0xf5] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1576 [0xf6] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1577 [0xf7] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode},
1578 [0xf8] = {OP_cmp, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode},
1579 [0xf9] = {OP_cmp, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode},
1580 [0xfa] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1581 [0xfb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode},
1582 [0xfc] = {OP_cmp, -1, 0, single, cmp_xy, 0},
1583 [0xfd] = {OP_sub, -1, 0, single, sub_d6_x_y, 0},
1584 [0xfe] = {OP_sub, -1, 0, single, sub_d6_y_x, 0},
1585 [0xff] = {OP_swi, -1, 0, single, 0, 0}
1586 };
1587
1588static const int oprregs1[] =
1589 {
1590 REG_D3, REG_D2, REG_D1, REG_D0, REG_CCL, REG_CCH
1591 };
1592
1593static const int oprregs2[] =
1594 {
1595 REG_Y, REG_X, REG_D7, REG_D6, REG_D5, REG_D4
1596 };
1597
1598
1599\f
1600
1601enum MUL_MODE
1602 {
1603 MUL_REG_REG,
1604 MUL_REG_OPR,
1605 MUL_REG_IMM,
1606 MUL_OPR_OPR
1607 };
1608
1609struct mb
1610{
1611 uint8_t mask;
1612 uint8_t value;
1613 enum MUL_MODE mode;
1614};
1615
1616static const struct mb mul_table[] = {
1617 {0x40, 0x00, MUL_REG_REG},
1618
1619 {0x47, 0x40, MUL_REG_OPR},
1620 {0x47, 0x41, MUL_REG_OPR},
1621 {0x47, 0x43, MUL_REG_OPR},
1622
1623 {0x47, 0x44, MUL_REG_IMM},
1624 {0x47, 0x45, MUL_REG_IMM},
1625 {0x47, 0x47, MUL_REG_IMM},
1626
1627 {0x43, 0x42, MUL_OPR_OPR},
1628};
1629
1630
1631static void
1632mul_decode (struct mem_read_abstraction_base *mra,
1633 int *n_operands, struct operand **operand)
1634{
1635 uint8_t mb;
1636 int status = mra->read (mra, 0, 1, &mb);
1637 if (status < 0)
1638 return;
1639
1640 uint8_t byte;
1641 status = mra->read (mra, -1, 1, &byte);
1642 if (status < 0)
1643 return;
1644
1645 enum MUL_MODE mode = -1;
1646 size_t i;
1647 for (i = 0; i < sizeof (mul_table) / sizeof (mul_table[0]); ++i)
1648 {
1649 const struct mb *mm = mul_table + i;
1650 if ((mb & mm->mask) == mm->value)
1651 {
1652 mode = mm->mode;
1653 break;
1654 }
1655 }
1656 operand[(*n_operands)++] = create_register_operand (byte & 0x07);
1657
1658 switch (mode)
1659 {
1660 case MUL_REG_IMM:
1661 {
1662 int size = (mb & 0x3);
1663 operand[(*n_operands)++] =
1664 create_register_operand_with_size ((mb & 0x38) >> 3, size);
1665 uint32_t imm = z_decode_signed_value (mra, 1, size + 1);
1666 operand[(*n_operands)++] = create_immediate_operand (imm);
1667 }
1668 break;
1669 case MUL_REG_REG:
1670 operand[(*n_operands)++] = create_register_operand ((mb & 0x38) >> 3);
1671 operand[(*n_operands)++] = create_register_operand (mb & 0x07);
1672 break;
1673 case MUL_REG_OPR:
1674 operand[(*n_operands)++] = create_register_operand ((mb & 0x38) >> 3);
1675 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, mb & 0x3);
1676 break;
1677 case MUL_OPR_OPR:
1678 {
1679 int first = x_opr_n_bytes (mra, 1);
1680 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1,
1681 (mb & 0x30) >> 4);
1682 operand[(*n_operands)++] = x_opr_decode_with_size (mra, first + 1,
1683 (mb & 0x0c) >> 2);
1684 break;
1685 }
1686 }
1687}
1688
1689
1690static int
1691mul_n_bytes (struct mem_read_abstraction_base *mra)
1692{
1693 int nx = 2;
1694 uint8_t mb;
1695 int status = mra->read (mra, 0, 1, &mb);
1696 if (status < 0)
1697 return 0;
1698
1699 enum MUL_MODE mode = -1;
1700 size_t i;
1701 for (i = 0; i < sizeof (mul_table) / sizeof (mul_table[0]); ++i)
1702 {
1703 const struct mb *mm = mul_table + i;
1704 if ((mb & mm->mask) == mm->value)
1705 {
1706 mode = mm->mode;
1707 break;
1708 }
1709 }
1710
1711 int size = (mb & 0x3) + 1;
1712
1713 switch (mode)
1714 {
1715 case MUL_REG_IMM:
1716 nx += size;
1717 break;
1718 case MUL_REG_REG:
1719 break;
1720 case MUL_REG_OPR:
1721 nx += x_opr_n_bytes (mra, 1);
1722 break;
1723 case MUL_OPR_OPR:
1724 {
1725 int first = x_opr_n_bytes (mra, nx - 1);
1726 nx += first;
1727 int second = x_opr_n_bytes (mra, nx - 1);
1728 nx += second;
1729 }
1730 break;
1731 }
1732
1733 return nx;
1734}
1735
1736\f
1737/* The NXP documentation is vague about BM_RESERVED0 and BM_RESERVED1,
1738 and contains obvious typos.
1739 However the Freescale tools and experiments with the chip itself
1740 seem to indicate that they behave like BM_REG_IMM and BM_OPR_REG
1741 respectively. */
1742
1743enum BM_MODE
1744{
1745 BM_REG_IMM,
1746 BM_RESERVED0,
1747 BM_OPR_B,
1748 BM_OPR_W,
1749 BM_OPR_L,
1750 BM_OPR_REG,
1751 BM_RESERVED1
1752};
1753
1754struct bm
1755{
1756 uint8_t mask;
1757 uint8_t value;
1758 enum BM_MODE mode;
1759};
1760
1761static const struct bm bm_table[] = {
1762 { 0xC6, 0x04, BM_REG_IMM},
1763 { 0x84, 0x00, BM_REG_IMM},
1764 { 0x06, 0x06, BM_REG_IMM},
1765 { 0xC6, 0x44, BM_RESERVED0},
1766 // 00
1767 { 0x8F, 0x80, BM_OPR_B},
1768 { 0x8E, 0x82, BM_OPR_W},
1769 { 0x8C, 0x88, BM_OPR_L},
1770
1771 { 0x83, 0x81, BM_OPR_REG},
1772 { 0x87, 0x84, BM_RESERVED1},
1773};
1774
1775static void
1776bm_decode (struct mem_read_abstraction_base *mra,
1777 int *n_operands, struct operand **operand)
1778{
1779 uint8_t bm;
1780 int status = mra->read (mra, 0, 1, &bm);
1781 if (status < 0)
1782 return;
1783
1784 size_t i;
1785 enum BM_MODE mode = -1;
1786 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i)
1787 {
1788 const struct bm *bme = bm_table + i;
1789 if ((bm & bme->mask) == bme->value)
1790 {
1791 mode = bme->mode;
1792 break;
1793 }
1794 }
1795
1796 switch (mode)
1797 {
1798 case BM_REG_IMM:
1799 case BM_RESERVED0:
1800 operand[(*n_operands)++] = create_register_operand (bm & 0x07);
1801 break;
1802 case BM_OPR_B:
1803 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, 0);
1804 break;
1805 case BM_OPR_W:
1806 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, 1);
1807 break;
1808 case BM_OPR_L:
1809 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, 3);
1810 break;
1811 case BM_OPR_REG:
1812 case BM_RESERVED1:
1813 {
1814 uint8_t xb;
1815 mra->read (mra, 1, 1, &xb);
1816 /* Don't emit a size suffix for register operands */
1817 if ((xb & 0xF8) != 0xB8)
1818 operand[(*n_operands)++] =
1819 x_opr_decode_with_size (mra, 1, (bm & 0x0c) >> 2);
1820 else
1821 operand[(*n_operands)++] = x_opr_decode (mra, 1);
1822 }
1823 break;
1824 }
1825
1826 uint8_t imm = 0;
1827 switch (mode)
1828 {
1829 case BM_REG_IMM:
a679f24e 1830 case BM_RESERVED0:
ef1ad42b
JD		 1831 imm = (bm & 0x38) >> 3;
1832 operand[(*n_operands)++] = create_immediate_operand (imm);
1833 break;
1834 case BM_OPR_L:
1835 imm |= (bm & 0x03) << 3;
1836 /* fallthrough */
1837 case BM_OPR_W:
1838 imm |= (bm & 0x01) << 3;
1839 /* fallthrough */
1840 case BM_OPR_B:
1841 imm |= (bm & 0x70) >> 4;
1842 operand[(*n_operands)++] = create_immediate_operand (imm);
1843 break;
1844 case BM_OPR_REG:
1845 case BM_RESERVED1:
1846 operand[(*n_operands)++] = create_register_operand ((bm & 0x70) >> 4);
1847 break;
ef1ad42b
JD		 1848 }
1849}
1850
1851
1852static void
1853bm_rel_decode (struct mem_read_abstraction_base *mra,
1854 int *n_operands, struct operand **operand)
1855{
1856 uint8_t bm;
1857 int status = mra->read (mra, 0, 1, &bm);
1858 if (status < 0)
1859 return;
1860
1861 size_t i;
1862 enum BM_MODE mode = -1;
1863 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i)
1864 {
1865 const struct bm *bme = bm_table + i;
1866 if ((bm & bme->mask) == bme->value)
1867 {
1868 mode = bme->mode;
1869 break;
1870 }
1871 }
1872
1873 int n = 1;
1874 switch (mode)
1875 {
1876 case BM_REG_IMM:
1877 case BM_RESERVED0:
1878 operand[(*n_operands)++] = create_register_operand (bm & 0x07);
1879 break;
1880 case BM_OPR_B:
1881 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, 0);
1882 n = 1 + x_opr_n_bytes (mra, 1);
1883 break;
1884 case BM_OPR_W:
1885 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, 1);
1886 n = 1 + x_opr_n_bytes (mra, 1);
1887 break;
1888 case BM_OPR_L:
1889 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, 3);
1890 n = 1 + x_opr_n_bytes (mra, 1);
1891 break;
1892 case BM_OPR_REG:
1893 case BM_RESERVED1:
1894 {
1895 uint8_t xb;
1896 mra->read (mra, +1, 1, &xb);
1897 /* Don't emit a size suffix for register operands */
1898 if ((xb & 0xF8) != 0xB8)
1899 {
1900 short os = (bm & 0x0c) >> 2;
1901 operand[(*n_operands)++] = x_opr_decode_with_size (mra, 1, os);
1902 }
1903 else
1904 operand[(*n_operands)++] = x_opr_decode (mra, 1);
1905
1906 }
1907 break;
1908 }
1909
1910 int imm = 0;
1911 switch (mode)
1912 {
1913 case BM_OPR_L:
1914 imm |= (bm & 0x02) << 3;
1915 /* fall through */
1916 case BM_OPR_W:
1917 imm |= (bm & 0x01) << 3;
1918 /* fall through */
1919 case BM_OPR_B:
1920 imm |= (bm & 0x70) >> 4;
1921 operand[(*n_operands)++] = create_immediate_operand (imm);
1922 break;
1923 case BM_RESERVED0:
1924 imm = (bm & 0x38) >> 3;
1925 operand[(*n_operands)++] = create_immediate_operand (imm);
1926 break;
1927 case BM_REG_IMM:
1928 imm = (bm & 0xF8) >> 3;
1929 operand[(*n_operands)++] = create_immediate_operand (imm);
1930 break;
1931 case BM_OPR_REG:
1932 case BM_RESERVED1:
1933 operand[(*n_operands)++] = create_register_operand ((bm & 0x70) >> 4);
1934 n += x_opr_n_bytes (mra, 1);
1935 break;
1936 }
1937
1938 rel_15_7 (mra, n + 1, n_operands, operand);
1939}
1940
1941static int
1942bm_n_bytes (struct mem_read_abstraction_base *mra)
1943{
1944 uint8_t bm;
1945 int status = mra->read (mra, 0, 1, &bm);
1946 if (status < 0)
1947 return status;
1948
1949 size_t i;
1950 enum BM_MODE mode = -1;
1951 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i)
1952 {
1953 const struct bm *bme = bm_table + i;
1954 if ((bm & bme->mask) == bme->value)
1955 {
1956 mode = bme->mode;
1957 break;
1958 }
1959 }
1960
1961 int n = 2;
1962 switch (mode)
1963 {
1964 case BM_REG_IMM:
1965 case BM_RESERVED0:
1966 break;
1967
1968 case BM_OPR_B:
1969 case BM_OPR_W:
1970 case BM_OPR_L:
1971 n += x_opr_n_bytes (mra, 1);
1972 break;
1973 case BM_OPR_REG:
1974 case BM_RESERVED1:
1975 n += x_opr_n_bytes (mra, 1);
1976 break;
1977 }
1978
1979 return n;
1980}
1981
1982static int
1983bm_rel_n_bytes (struct mem_read_abstraction_base *mra)
1984{
1985 int n = 1 + bm_n_bytes (mra);
1986
1987 bfd_byte rb;
1988 int status = mra->read (mra, n - 2, 1, &rb);
1989 if (status != 0)
1990 return status;
1991
1992 if (rb & 0x80)
1993 n++;
1994
1995 return n;
1996}
1997
1998
1999\f
2000
2001
2002/* shift direction */
2003enum SB_DIR
2004 {
2005 SB_LEFT,
2006 SB_RIGHT
2007 };
2008
2009enum SB_TYPE
2010 {
2011 SB_ARITHMETIC,
2012 SB_LOGICAL
2013 };
2014
2015
2016enum SB_MODE
2017 {
2018 SB_REG_REG_N_EFF,
2019 SB_REG_REG_N,
2020 SB_REG_OPR_EFF,
2021 SB_ROT,
2022 SB_REG_OPR_OPR,
2023 SB_OPR_N
2024 };
2025
2026struct sb
2027{
2028 uint8_t mask;
2029 uint8_t value;
2030 enum SB_MODE mode;
2031};
2032
2033static const struct sb sb_table[] = {
2034 {0x30, 0x00, SB_REG_REG_N_EFF},
2035 {0x30, 0x10, SB_REG_REG_N},
2036 {0x34, 0x20, SB_REG_OPR_EFF},
2037 {0x34, 0x24, SB_ROT},
2038 {0x34, 0x30, SB_REG_OPR_OPR},
2039 {0x34, 0x34, SB_OPR_N},
2040};
2041
2042static int
2043shift_n_bytes (struct mem_read_abstraction_base *mra)
2044{
2045 bfd_byte sb;
2046 int status = mra->read (mra, 0, 1, &sb);
2047 if (status != 0)
2048 return status;
2049
2050 size_t i;
2051 enum SB_MODE mode = -1;
2052 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i)
2053 {
2054 const struct sb *sbe = sb_table + i;
2055 if ((sb & sbe->mask) == sbe->value)
2056 mode = sbe->mode;
2057 }
2058
2059 switch (mode)
2060 {
2061 case SB_REG_REG_N_EFF:
2062 return 2;
2063 break;
2064 case SB_REG_OPR_EFF:
2065 case SB_ROT:
2066 return 2 + x_opr_n_bytes (mra, 1);
2067 break;
2068 case SB_REG_OPR_OPR:
2069 {
2070 int opr1 = x_opr_n_bytes (mra, 1);
2071 int opr2 = 0;
2072 if ((sb & 0x30) != 0x20)
2073 opr2 = x_opr_n_bytes (mra, opr1 + 1);
2074 return 2 + opr1 + opr2;
2075 }
2076 break;
2077 default:
2078 return 3;
2079 }
2080
2081 /* not reached */
2082 return -1;
2083}
2084\f
2085
2086static int
2087
2088mov_imm_opr_n_bytes (struct mem_read_abstraction_base *mra)
2089{
2090 bfd_byte byte;
2091 int status = mra->read (mra, -1, 1, &byte);
2092 if (status < 0)
2093 return status;
2094
2095 int size = byte - 0x0c + 1;
2096
2097 return size + x_opr_n_bytes (mra, size) + 1;
2098}
2099
2100static void
2101mov_imm_opr (struct mem_read_abstraction_base *mra,
2102 int *n_operands, struct operand **operand)
2103{
2104 bfd_byte byte;
2105 int status = mra->read (mra, -1, 1, &byte);
2106 if (status < 0)
2107 return ;
2108
2109 int size = byte - 0x0c + 1;
2110 uint32_t imm = decode_signed_value (mra, size);
2111
2112 operand[(*n_operands)++] = create_immediate_operand (imm);
2113 operand[(*n_operands)++] = x_opr_decode (mra, size);
2114}
2115
2116\f
2117
2118static void
2119ld_18bit_decode (struct mem_read_abstraction_base *mra,
2120 int *n_operands, struct operand **operand)
2121{
2122 size_t size = 3;
2123 bfd_byte buffer[3];
2124 int status = mra->read (mra, 0, 2, buffer + 1);
2125 if (status < 0)
2126 return ;
2127
2128 status = mra->read (mra, -1, 1, buffer);
2129 if (status < 0)
2130 return ;
2131
2132 buffer[0] = (buffer[0] & 0x30) >> 4;
2133
2134 size_t i;
2135 uint32_t imm = 0;
2136 for (i = 0; i < size; ++i)
2137 {
2138 imm |= buffer[i] << (8 * (size - i - 1));
2139 }
2140
2141 operand[(*n_operands)++] = create_immediate_operand (imm);
2142}
2143
2144\f
2145
2146/* Loop Primitives */
2147
2148enum LP_MODE {
2149 LP_REG,
2150 LP_XY,
2151 LP_OPR
2152};
2153
2154struct lp
2155{
2156 uint8_t mask;
2157 uint8_t value;
2158 enum LP_MODE mode;
2159};
2160
2161static const struct lp lp_mode[] = {
2162 {0x08, 0x00, LP_REG},
2163 {0x0C, 0x08, LP_XY},
2164 {0x0C, 0x0C, LP_OPR},
2165};
2166
2167
2168static int
2169loop_prim_n_bytes (struct mem_read_abstraction_base *mra)
2170{
2171 int mx = 0;
2172 uint8_t lb;
2173 mra->read (mra, mx++, 1, &lb);
2174
2175 enum LP_MODE mode = -1;
2176 size_t i;
2177 for (i = 0; i < sizeof (lp_mode) / sizeof (lp_mode[0]); ++i)
2178 {
2179 const struct lp *pb = lp_mode + i;
2180 if ((lb & pb->mask) == pb->value)
2181 {
2182 mode = pb->mode;
2183 break;
2184 }
2185 }
2186
2187 if (mode == LP_OPR)
2188 {
2189 mx += x_opr_n_bytes (mra, mx) ;
2190 }
2191
2192 uint8_t rb;
2193 mra->read (mra, mx++, 1, &rb);
2194 if (rb & 0x80)
2195 mx++;
2196
2197 return mx + 1;
2198}
2199
2200
2201\f
2202
e5a557ac 2203static enum optr
0a6aef6b
AM		 2204exg_sex_discrim (struct mem_read_abstraction_base *mra,
2205 enum optr hint ATTRIBUTE_UNUSED)
ef1ad42b
JD		 2206{
2207 uint8_t eb;
2208 int status = mra->read (mra, 0, 1, &eb);
0a6aef6b 2209 enum optr operator = OP_INVALID;
ef1ad42b 2210 if (status < 0)
0a6aef6b 2211 return operator;
ef1ad42b
JD		 2212
2213 struct operand *op0 = create_register_operand ((eb & 0xf0) >> 4);
2214 struct operand *op1 = create_register_operand (eb & 0xf);
2215
66a66a17 2216 int reg0 = ((struct register_operand *) op0)->reg;
66a66a17 2217 int reg1 = ((struct register_operand *) op1)->reg;
0a6aef6b
AM		 2218 if (reg0 >= 0 && reg0 < S12Z_N_REGISTERS
2219 && reg1 >= 0 && reg1 < S12Z_N_REGISTERS)
2220 {
2221 const struct reg *r0 = registers + reg0;
2222 const struct reg *r1 = registers + reg1;
ef1ad42b 2223
0a6aef6b
AM		 2224 operator = r0->bytes < r1->bytes ? OP_sex : OP_exg;
2225 }
ef1ad42b
JD		 2226
2227 free (op0);
2228 free (op1);
0a6aef6b 2229
ef1ad42b
JD		 2230 return operator;
2231}
2232
2233
2234static void
2235exg_sex_decode (struct mem_read_abstraction_base *mra,
2236 int *n_operands, struct operand **operands)
2237{
2238 uint8_t eb;
2239 int status = mra->read (mra, 0, 1, &eb);
2240 if (status < 0)
2241 return;
2242
2243 /* Ship out the operands. */
2244 operands[(*n_operands)++] = create_register_operand ((eb & 0xf0) >> 4);
2245 operands[(*n_operands)++] = create_register_operand (eb & 0xf);
2246}
2247
e5a557ac 2248static enum optr
ef1ad42b 2249loop_primitive_discrim (struct mem_read_abstraction_base *mra,
e5a557ac 2250 enum optr hint ATTRIBUTE_UNUSED)
ef1ad42b
JD		 2251{
2252 uint8_t lb;
2253 int status = mra->read (mra, 0, 1, &lb);
2254 if (status < 0)
2255 return OP_INVALID;
2256
e5a557ac 2257 enum optr opbase = (lb & 0x80) ? OP_dbNE : OP_tbNE;
ef1ad42b
JD		 2258 return opbase + ((lb & 0x70) >> 4);
2259}
2260
2261static void
2262loop_primitive_decode (struct mem_read_abstraction_base *mra,
e7c22a69 2263 int *n_operands, struct operand **operands)
ef1ad42b
JD		 2264{
2265 int offs = 1;
2266 uint8_t lb;
2267 int status = mra->read (mra, 0, 1, &lb);
2268 if (status < 0)
2269 return ;
2270
2271 enum LP_MODE mode = -1;
2272 size_t i;
2273 for (i = 0; i < sizeof (lp_mode) / sizeof (lp_mode[0]); ++i)
2274 {
2275 const struct lp *pb = lp_mode + i;
2276 if ((lb & pb->mask) == pb->value)
2277 {
2278 mode = pb->mode;
2279 break;
2280 }
2281 }
2282
2283 switch (mode)
2284 {
2285 case LP_REG:
2286 operands[(*n_operands)++] = create_register_operand (lb & 0x07);
2287 break;
2288 case LP_XY:
2289 operands[(*n_operands)++] =
2290 create_register_operand ((lb & 0x01) + REG_X);
2291 break;
2292 case LP_OPR:
2293 offs += x_opr_n_bytes (mra, 1);
2294 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 1, lb & 0x03);
2295 break;
2296 }
2297
2298 rel_15_7 (mra, offs + 1, n_operands, operands);
2299}
2300
2301
e5a557ac 2302static enum optr
e7c22a69
AM		 2303shift_discrim (struct mem_read_abstraction_base *mra,
2304 enum optr hint ATTRIBUTE_UNUSED)
ef1ad42b
JD		 2305{
2306 size_t i;
2307 uint8_t sb;
2308 int status = mra->read (mra, 0, 1, &sb);
2309 if (status < 0)
4a90ce95 2310 return OP_INVALID;
ef1ad42b
JD		 2311
2312 enum SB_DIR dir = (sb & 0x40) ? SB_LEFT : SB_RIGHT;
2313 enum SB_TYPE type = (sb & 0x80) ? SB_ARITHMETIC : SB_LOGICAL;
2314 enum SB_MODE mode = -1;
2315 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i)
2316 {
2317 const struct sb *sbe = sb_table + i;
2318 if ((sb & sbe->mask) == sbe->value)
2319 mode = sbe->mode;
2320 }
2321
2322 if (mode == SB_ROT)
2323 return (dir == SB_LEFT) ? OP_rol : OP_ror;
2324
2325 if (type == SB_LOGICAL)
2326 return (dir == SB_LEFT) ? OP_lsl : OP_lsr;
2327
2328 return (dir == SB_LEFT) ? OP_asl : OP_asr;
2329}
2330
2331
2332static void
e7c22a69
AM		 2333shift_decode (struct mem_read_abstraction_base *mra, int *n_operands,
2334 struct operand **operands)
ef1ad42b
JD		 2335{
2336 size_t i;
2337
2338 uint8_t byte;
2339 int status = mra->read (mra, -1, 1, &byte);
2340 if (status < 0)
2341 return ;
2342
2343 uint8_t sb;
2344 status = mra->read (mra, 0, 1, &sb);
2345 if (status < 0)
2346 return ;
2347
2348 enum SB_MODE mode = -1;
2349 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i)
2350 {
2351 const struct sb *sbe = sb_table + i;
2352 if ((sb & sbe->mask) == sbe->value)
2353 mode = sbe->mode;
2354 }
2355
2356 short osize = -1;
2357 switch (mode)
2358 {
2359 case SB_REG_OPR_EFF:
2360 case SB_ROT:
2361 case SB_REG_OPR_OPR:
2362 osize = sb & 0x03;
2363 break;
2364 case SB_OPR_N:
2365 {
2366 uint8_t xb;
2367 mra->read (mra, 1, 1, &xb);
2368 /* The size suffix is not printed if the OPR operand refers
2369 directly to a register, because the size is implied by the
2370 size of that register. */
2371 if ((xb & 0xF8) != 0xB8)
2372 osize = sb & 0x03;
2373 }
2374 break;
2375 default:
2376 break;
2377 };
2378
2379 /* Destination register */
2380 switch (mode)
2381 {
2382 case SB_REG_REG_N_EFF:
2383 case SB_REG_REG_N:
2384 operands[(*n_operands)++] = create_register_operand (byte & 0x07);
2385 break;
2386 case SB_REG_OPR_EFF:
2387 case SB_REG_OPR_OPR:
2388 operands[(*n_operands)++] = create_register_operand (byte & 0x07);
2389 break;
2390
2391 case SB_ROT:
2392 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 1, osize);
2393 break;
2394
2395 default:
2396 break;
2397 }
2398
2399 /* Source register */
2400 switch (mode)
2401 {
2402 case SB_REG_REG_N_EFF:
2403 case SB_REG_REG_N:
2404 operands[(*n_operands)++] =
2405 create_register_operand_with_size (sb & 0x07, osize);
2406 break;
2407
2408 case SB_REG_OPR_OPR:
2409 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 1, osize);
2410 break;
2411
2412 default:
2413 break;
2414 }
2415
2416 /* 3rd arg */
2417 switch (mode)
2418 {
2419 case SB_REG_OPR_EFF:
2420 case SB_OPR_N:
2421 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 1, osize);
2422 break;
2423
2424 case SB_REG_REG_N:
2425 {
e7c22a69
AM		 2426 uint8_t xb;
2427 mra->read (mra, 1, 1, &xb);
2428
2429 /* This case is slightly unusual.
2430 If XB matches the binary pattern 0111XXXX, then instead of
2431 interpreting this as a general OPR postbyte in the IMMe4 mode,
2432 the XB byte is interpreted in s special way. */
2433 if ((xb & 0xF0) == 0x70)
2434 {
2435 if (byte & 0x10)
2436 {
2437 int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
2438 operands[(*n_operands)++] = create_immediate_operand (shift);
2439 }
2440 else
2441 {
2442 /* This should not happen. */
2443 abort ();
2444 }
2445 }
2446 else
2447 {
2448 operands[(*n_operands)++] = x_opr_decode (mra, 1);
2449 }
ef1ad42b
JD		 2450 }
2451 break;
2452 case SB_REG_OPR_OPR:
2453 {
2454 uint8_t xb;
2455 int n = x_opr_n_bytes (mra, 1);
2456 mra->read (mra, 1 + n, 1, &xb);
2457
2458 if ((xb & 0xF0) == 0x70)
2459 {
2460 int imm = xb & 0x0F;
2461 imm <<= 1;
2462 imm |= (sb & 0x08) >> 3;
2463 operands[(*n_operands)++] = create_immediate_operand (imm);
2464 }
2465 else
2466 {
2467 operands[(*n_operands)++] = x_opr_decode (mra, 1 + n);
2468 }
2469 }
2470 break;
2471 default:
2472 break;
2473 }
2474
2475 switch (mode)
2476 {
2477 case SB_REG_REG_N_EFF:
2478 case SB_REG_OPR_EFF:
2479 case SB_OPR_N:
2480 {
e7c22a69
AM		 2481 int imm = (sb & 0x08) ? 2 : 1;
2482 operands[(*n_operands)++] = create_immediate_operand (imm);
ef1ad42b
JD		 2483 }
2484 break;
2485
2486 default:
2487 break;
2488 }
2489}
2490
e5a557ac 2491static enum optr
ef1ad42b 2492psh_pul_discrim (struct mem_read_abstraction_base *mra,
e5a557ac 2493 enum optr hint ATTRIBUTE_UNUSED)
ef1ad42b
JD		 2494{
2495 uint8_t byte;
2496 int status = mra->read (mra, 0, 1, &byte);
2497 if (status != 0)
2498 return OP_INVALID;
2499
2500 return (byte & 0x80) ? OP_pull: OP_push;
2501}
2502
2503
2504static void
2505psh_pul_decode (struct mem_read_abstraction_base *mra,
2506 int *n_operands, struct operand **operand)
2507{
2508 uint8_t byte;
2509 int status = mra->read (mra, 0, 1, &byte);
2510 if (status != 0)
2511 return;
2512 int bit;
2513 if (byte & 0x40)
2514 {
2515 if ((byte & 0x3F) == 0)
e7c22a69 2516 operand[(*n_operands)++] = create_register_all16_operand ();
ef1ad42b
JD		 2517 else
2518 for (bit = 5; bit >= 0; --bit)
2519 {
2520 if (byte & (0x1 << bit))
2521 {
2522 operand[(*n_operands)++] = create_register_operand (oprregs2[bit]);
2523 }
2524 }
2525 }
2526 else
2527 {
2528 if ((byte & 0x3F) == 0)
e7c22a69 2529 operand[(*n_operands)++] = create_register_all_operand ();
ef1ad42b
JD		 2530 else
2531 for (bit = 5; bit >= 0; --bit)
2532 {
2533 if (byte & (0x1 << bit))
2534 {
2535 operand[(*n_operands)++] = create_register_operand (oprregs1[bit]);
2536 }
2537 }
2538 }
2539}
2540
e5a557ac 2541static enum optr
e7c22a69
AM		 2542bit_field_discrim (struct mem_read_abstraction_base *mra,
2543 enum optr hint ATTRIBUTE_UNUSED)
ef1ad42b
JD		 2544{
2545 int status;
2546 bfd_byte bb;
2547 status = mra->read (mra, 0, 1, &bb);
2548 if (status != 0)
2549 return OP_INVALID;
2550
2551 return (bb & 0x80) ? OP_bfins : OP_bfext;
2552}
2553
2554static void
2555bit_field_decode (struct mem_read_abstraction_base *mra,
2556 int *n_operands, struct operand **operands)
2557{
2558 int status;
2559
2560 bfd_byte byte2;
2561 status = mra->read (mra, -1, 1, &byte2);
2562 if (status != 0)
2563 return;
2564
2565 bfd_byte bb;
2566 status = mra->read (mra, 0, 1, &bb);
2567 if (status != 0)
2568 return;
2569
2570 enum BB_MODE mode = -1;
2571 size_t i;
2572 const struct opr_bb *bbs = 0;
2573 for (i = 0; i < sizeof (bb_modes) / sizeof (bb_modes[0]); ++i)
2574 {
2575 bbs = bb_modes + i;
2576 if ((bb & bbs->mask) == bbs->value)
e7c22a69
AM		 2577 {
2578 mode = bbs->mode;
2579 break;
2580 }
ef1ad42b
JD		 2581 }
2582 int reg1 = byte2 & 0x07;
2583 /* First operand */
2584 switch (mode)
2585 {
2586 case BB_REG_REG_REG:
2587 case BB_REG_REG_IMM:
2588 case BB_REG_OPR_REG:
2589 case BB_REG_OPR_IMM:
2590 operands[(*n_operands)++] = create_register_operand (reg1);
2591 break;
2592 case BB_OPR_REG_REG:
2593 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 1,
2594 (bb >> 2) & 0x03);
2595 break;
2596 case BB_OPR_REG_IMM:
2597 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 2,
2598 (bb >> 2) & 0x03);
2599 break;
2600 }
2601
2602 /* Second operand */
2603 switch (mode)
2604 {
2605 case BB_REG_REG_REG:
2606 case BB_REG_REG_IMM:
2607 {
e7c22a69
AM		 2608 int reg_src = (bb >> 2) & 0x07;
2609 operands[(*n_operands)++] = create_register_operand (reg_src);
ef1ad42b
JD		 2610 }
2611 break;
2612 case BB_OPR_REG_REG:
2613 case BB_OPR_REG_IMM:
2614 {
e7c22a69
AM		 2615 int reg_src = (byte2 & 0x07);
2616 operands[(*n_operands)++] = create_register_operand (reg_src);
ef1ad42b
JD		 2617 }
2618 break;
2619 case BB_REG_OPR_REG:
2620 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 1,
2621 (bb >> 2) & 0x03);
2622 break;
2623 case BB_REG_OPR_IMM:
2624 operands[(*n_operands)++] = x_opr_decode_with_size (mra, 2,
2625 (bb >> 2) & 0x03);
2626 break;
2627 }
2628
2629 /* Third operand */
2630 switch (mode)
2631 {
2632 case BB_REG_REG_REG:
2633 case BB_OPR_REG_REG:
2634 case BB_REG_OPR_REG:
2635 {
e7c22a69 2636 int reg_parm = bb & 0x03;
ef1ad42b
JD		 2637 operands[(*n_operands)++] = create_register_operand (reg_parm);
2638 }
2639 break;
2640 case BB_REG_REG_IMM:
2641 case BB_OPR_REG_IMM:
2642 case BB_REG_OPR_IMM:
2643 {
e7c22a69
AM		 2644 bfd_byte i1;
2645 mra->read (mra, 1, 1, &i1);
2646 int offset = i1 & 0x1f;
2647 int width = bb & 0x03;
2648 width <<= 3;
2649 width |= i1 >> 5;
2650 operands[(*n_operands)++] = create_bitfield_operand (width, offset);
ef1ad42b
JD		 2651 }
2652 break;
2653 }
2654}
2655
2656
2657/* Decode the next instruction at MRA, according to OPC.
2658 The operation to be performed is returned.
2659 The number of operands, will be placed in N_OPERANDS.
2660 The operands themselved into OPERANDS. */
e5a557ac 2661static enum optr
ef1ad42b
JD		 2662decode_operation (const struct opcode *opc,
2663 struct mem_read_abstraction_base *mra,
2664 int *n_operands, struct operand **operands)
2665{
e5a557ac 2666 enum optr op = opc->operator;
ef1ad42b
JD		 2667 if (opc->discriminator)
2668 op = opc->discriminator (mra, opc->operator);
2669
2670 if (opc->operands)
2671 opc->operands (mra, n_operands, operands);
2672
2673 if (opc->operands2)
2674 opc->operands2 (mra, n_operands, operands);
2675
2676 return op;
2677}
2678
2679int
e5a557ac 2680decode_s12z (enum optr *myoperator, short *osize,
ef1ad42b
JD		 2681 int *n_operands, struct operand **operands,
2682 struct mem_read_abstraction_base *mra)
2683{
2684 int n_bytes = 0;
2685 bfd_byte byte;
2686
2687 int status = mra->read (mra, 0, 1, &byte);
2688 if (status != 0)
2689 return status;
2690
2691 mra->advance (mra);
2692
2693 const struct opcode *opc = page1 + byte;
2694 if (byte == PAGE2_PREBYTE)
2695 {
2696 /* Opcodes in page2 have an additional byte */
2697 n_bytes++;
2698
2699 bfd_byte byte2;
2700 mra->read (mra, 0, 1, &byte2);
2701 mra->advance (mra);
2702 opc = page2 + byte2;
2703 }
2704 *myoperator = decode_operation (opc, mra, n_operands, operands);
2705 *osize = opc->osize;
2706
2707 /* Return the number of bytes in the instruction. */
2708 n_bytes += (opc && opc->insn_bytes) ? opc->insn_bytes (mra) : 0;
2709
2710 return n_bytes;
2711}
2712
GDB Binutils - Deliverables
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