projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a85d7ed0 | 1 | /* s390-opc.c -- S390 opcode list |
| 9b201bb5 | 2 | Copyright 2000, 2001, 2003, 2007 Free Software Foundation, Inc. |
| a85d7ed0 NC |
3 | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
| 4 | ||
| 9b201bb5 | 5 | This file is part of the GNU opcodes library. |
| a85d7ed0 | 6 | |
| 9b201bb5 | 7 | This library is free software; you can redistribute it and/or modify |
| a85d7ed0 | 8 | it under the terms of the GNU General Public License as published by |
| 9b201bb5 NC |
9 | the Free Software Foundation; either version 3, or (at your option) |
| 10 | any later version. | |
| a85d7ed0 | 11 | |
| 9b201bb5 NC |
12 | It is distributed in the hope that it will be useful, but WITHOUT |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 | License for more details. | |
| a85d7ed0 NC |
16 | |
| 17 | You should have received a copy of the GNU General Public License | |
| 9b201bb5 NC |
18 | along with this file; see the file COPYING. If not, write to the |
| 19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 20 | MA 02110-1301, USA. */ | |
| a85d7ed0 NC |
21 | |
| 22 | #include <stdio.h> | |
| 23 | #include "ansidecl.h" | |
| 24 | #include "opcode/s390.h" | |
| 25 | ||
| 26 | /* This file holds the S390 opcode table. The opcode table | |
| 27 | includes almost all of the extended instruction mnemonics. This | |
| 28 | permits the disassembler to use them, and simplifies the assembler | |
| 29 | logic, at the cost of increasing the table size. The table is | |
| 30 | strictly constant data, so the compiler should be able to put it in | |
| 31 | the .text section. | |
| 32 | ||
| 33 | This file also holds the operand table. All knowledge about | |
| 34 | inserting operands into instructions and vice-versa is kept in this | |
| 35 | file. */ | |
| 36 | ||
| 37 | /* The operands table. | |
| 38 | The fields are bits, shift, insert, extract, flags. */ | |
| 39 | ||
| 40 | const struct s390_operand s390_operands[] = | |
| 41 | { | |
| 42 | #define UNUSED 0 | |
| 43 | { 0, 0, 0 }, /* Indicates the end of the operand list */ | |
| 44 | ||
| 5746fb46 AK |
45 | /* General purpose register operands. */ |
| 46 | ||
| a85d7ed0 NC |
47 | #define R_8 1 /* GPR starting at position 8 */ |
| 48 | { 4, 8, S390_OPERAND_GPR }, | |
| 49 | #define R_12 2 /* GPR starting at position 12 */ | |
| 355d475e | 50 | { 4, 12, S390_OPERAND_GPR }, |
| ce21feb4 MS |
51 | #define RO_12 3 /* optional GPR starting at position 12 */ |
| 52 | { 4, 12, S390_OPERAND_GPR|S390_OPERAND_OPTIONAL }, | |
| 53 | #define R_16 4 /* GPR starting at position 16 */ | |
| 355d475e | 54 | { 4, 16, S390_OPERAND_GPR }, |
| ce21feb4 | 55 | #define R_20 5 /* GPR starting at position 20 */ |
| 355d475e | 56 | { 4, 20, S390_OPERAND_GPR }, |
| ce21feb4 | 57 | #define R_24 6 /* GPR starting at position 24 */ |
| 355d475e | 58 | { 4, 24, S390_OPERAND_GPR }, |
| ce21feb4 | 59 | #define R_28 7 /* GPR starting at position 28 */ |
| 355d475e | 60 | { 4, 28, S390_OPERAND_GPR }, |
| ce21feb4 | 61 | #define RO_28 8 /* optional GPR starting at position 28 */ |
| 5746fb46 | 62 | { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }, |
| ce21feb4 | 63 | #define R_32 9 /* GPR starting at position 32 */ |
| a85d7ed0 NC |
64 | { 4, 32, S390_OPERAND_GPR }, |
| 65 | ||
| 5746fb46 AK |
66 | /* Floating point register operands. */ |
| 67 | ||
| ce21feb4 | 68 | #define F_8 10 /* FPR starting at position 8 */ |
| a85d7ed0 | 69 | { 4, 8, S390_OPERAND_FPR }, |
| ce21feb4 | 70 | #define F_12 11 /* FPR starting at position 12 */ |
| a85d7ed0 | 71 | { 4, 12, S390_OPERAND_FPR }, |
| ce21feb4 | 72 | #define F_16 12 /* FPR starting at position 16 */ |
| a85d7ed0 | 73 | { 4, 16, S390_OPERAND_FPR }, |
| ce21feb4 | 74 | #define F_20 13 /* FPR starting at position 16 */ |
| a85d7ed0 | 75 | { 4, 16, S390_OPERAND_FPR }, |
| ce21feb4 | 76 | #define F_24 14 /* FPR starting at position 24 */ |
| a85d7ed0 | 77 | { 4, 24, S390_OPERAND_FPR }, |
| ce21feb4 | 78 | #define F_28 15 /* FPR starting at position 28 */ |
| a85d7ed0 | 79 | { 4, 28, S390_OPERAND_FPR }, |
| ce21feb4 | 80 | #define F_32 16 /* FPR starting at position 32 */ |
| a85d7ed0 NC |
81 | { 4, 32, S390_OPERAND_FPR }, |
| 82 | ||
| 5746fb46 AK |
83 | /* Access register operands. */ |
| 84 | ||
| ce21feb4 | 85 | #define A_8 17 /* Access reg. starting at position 8 */ |
| a85d7ed0 | 86 | { 4, 8, S390_OPERAND_AR }, |
| ce21feb4 | 87 | #define A_12 18 /* Access reg. starting at position 12 */ |
| a85d7ed0 | 88 | { 4, 12, S390_OPERAND_AR }, |
| ce21feb4 | 89 | #define A_24 19 /* Access reg. starting at position 24 */ |
| a85d7ed0 | 90 | { 4, 24, S390_OPERAND_AR }, |
| ce21feb4 | 91 | #define A_28 20 /* Access reg. starting at position 28 */ |
| a85d7ed0 NC |
92 | { 4, 28, S390_OPERAND_AR }, |
| 93 | ||
| 5746fb46 AK |
94 | /* Control register operands. */ |
| 95 | ||
| ce21feb4 | 96 | #define C_8 21 /* Control reg. starting at position 8 */ |
| a85d7ed0 | 97 | { 4, 8, S390_OPERAND_CR }, |
| ce21feb4 | 98 | #define C_12 22 /* Control reg. starting at position 12 */ |
| a85d7ed0 NC |
99 | { 4, 12, S390_OPERAND_CR }, |
| 100 | ||
| 5746fb46 AK |
101 | /* Base register operands. */ |
| 102 | ||
| ce21feb4 | 103 | #define B_16 23 /* Base register starting at position 16 */ |
| 355d475e | 104 | { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
| ce21feb4 | 105 | #define B_32 24 /* Base register starting at position 32 */ |
| 355d475e | 106 | { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
| a85d7ed0 | 107 | |
| ce21feb4 | 108 | #define X_12 25 /* Index register starting at position 12 */ |
| 355d475e | 109 | { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, |
| a85d7ed0 | 110 | |
| 5746fb46 AK |
111 | /* Address displacement operands. */ |
| 112 | ||
| ce21feb4 | 113 | #define D_20 26 /* Displacement starting at position 20 */ |
| 355d475e | 114 | { 12, 20, S390_OPERAND_DISP }, |
| ce21feb4 MS |
115 | #define DO_20 27 /* optional Displ. starting at position 20 */ |
| 116 | { 12, 20, S390_OPERAND_DISP|S390_OPERAND_OPTIONAL }, | |
| 117 | #define D_36 28 /* Displacement starting at position 36 */ | |
| 355d475e | 118 | { 12, 36, S390_OPERAND_DISP }, |
| ce21feb4 | 119 | #define D20_20 29 /* 20 bit displacement starting at 20 */ |
| bac02689 | 120 | { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, |
| a85d7ed0 | 121 | |
| 5746fb46 AK |
122 | /* Length operands. */ |
| 123 | ||
| ce21feb4 | 124 | #define L4_8 30 /* 4 bit length starting at position 8 */ |
| 355d475e | 125 | { 4, 8, S390_OPERAND_LENGTH }, |
| ce21feb4 | 126 | #define L4_12 31 /* 4 bit length starting at position 12 */ |
| a85d7ed0 | 127 | { 4, 12, S390_OPERAND_LENGTH }, |
| ce21feb4 | 128 | #define L8_8 32 /* 8 bit length starting at position 8 */ |
| 355d475e | 129 | { 8, 8, S390_OPERAND_LENGTH }, |
| a85d7ed0 | 130 | |
| 5746fb46 AK |
131 | /* Signed immediate operands. */ |
| 132 | ||
| ce21feb4 | 133 | #define I8_8 33 /* 8 bit signed value starting at 8 */ |
| 5746fb46 | 134 | { 8, 8, S390_OPERAND_SIGNED }, |
| ce21feb4 | 135 | #define I8_32 34 /* 8 bit signed value starting at 32 */ |
| 5746fb46 | 136 | { 8, 32, S390_OPERAND_SIGNED }, |
| ce21feb4 | 137 | #define I16_16 35 /* 16 bit signed value starting at 16 */ |
| 5746fb46 | 138 | { 16, 16, S390_OPERAND_SIGNED }, |
| ce21feb4 | 139 | #define I16_32 36 /* 16 bit signed value starting at 32 */ |
| 5746fb46 | 140 | { 16, 32, S390_OPERAND_SIGNED }, |
| ce21feb4 | 141 | #define I32_16 37 /* 32 bit signed value starting at 16 */ |
| 5746fb46 AK |
142 | { 32, 16, S390_OPERAND_SIGNED }, |
| 143 | ||
| 144 | /* Unsigned immediate operands. */ | |
| 145 | ||
| ce21feb4 | 146 | #define U4_8 38 /* 4 bit unsigned value starting at 8 */ |
| a85d7ed0 | 147 | { 4, 8, 0 }, |
| ce21feb4 | 148 | #define U4_12 39 /* 4 bit unsigned value starting at 12 */ |
| a85d7ed0 | 149 | { 4, 12, 0 }, |
| ce21feb4 | 150 | #define U4_16 40 /* 4 bit unsigned value starting at 16 */ |
| a85d7ed0 | 151 | { 4, 16, 0 }, |
| ce21feb4 | 152 | #define U4_20 41 /* 4 bit unsigned value starting at 20 */ |
| a85d7ed0 | 153 | { 4, 20, 0 }, |
| ce21feb4 | 154 | #define U4_32 42 /* 4 bit unsigned value starting at 32 */ |
| 5746fb46 | 155 | { 4, 32, 0 }, |
| ce21feb4 | 156 | #define U8_8 43 /* 8 bit unsigned value starting at 8 */ |
| 355d475e | 157 | { 8, 8, 0 }, |
| ce21feb4 | 158 | #define U8_16 44 /* 8 bit unsigned value starting at 16 */ |
| a85d7ed0 | 159 | { 8, 16, 0 }, |
| ce21feb4 | 160 | #define U8_24 45 /* 8 bit unsigned value starting at 24 */ |
| 5746fb46 | 161 | { 8, 24, 0 }, |
| ce21feb4 | 162 | #define U8_32 46 /* 8 bit unsigned value starting at 32 */ |
| 5746fb46 | 163 | { 8, 32, 0 }, |
| ce21feb4 | 164 | #define U16_16 47 /* 16 bit unsigned value starting at 16 */ |
| 355d475e | 165 | { 16, 16, 0 }, |
| ce21feb4 | 166 | #define U16_32 48 /* 16 bit unsigned value starting at 32 */ |
| 5746fb46 | 167 | { 16, 32, 0 }, |
| ce21feb4 | 168 | #define U32_16 49 /* 32 bit unsigned value starting at 16 */ |
| 5746fb46 AK |
169 | { 32, 16, 0 }, |
| 170 | ||
| 171 | /* PC-relative address operands. */ | |
| 172 | ||
| ce21feb4 | 173 | #define J16_16 50 /* PC relative jump offset at 16 */ |
| 355d475e | 174 | { 16, 16, S390_OPERAND_PCREL }, |
| ce21feb4 | 175 | #define J32_16 51 /* PC relative long offset at 16 */ |
| ad101263 | 176 | { 32, 16, S390_OPERAND_PCREL }, |
| 5746fb46 AK |
177 | |
| 178 | /* Conditional mask operands. */ | |
| 179 | ||
| ce21feb4 | 180 | #define M_16 52 /* 4 bit optional mask starting at 16 */ |
| b8e55848 | 181 | { 4, 16, S390_OPERAND_OPTIONAL }, |
| b8e55848 | 182 | |
| a85d7ed0 NC |
183 | }; |
| 184 | ||
| 185 | ||
| 186 | /* Macros used to form opcodes. */ | |
| 187 | ||
| b6849f55 | 188 | /* 8/16/48 bit opcodes. */ |
| a85d7ed0 | 189 | #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 82b66b23 NC |
190 | #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
| 191 | #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ | |
| 192 | (x >> 16) & 255, (x >> 8) & 255, x & 255} | |
| a85d7ed0 | 193 | |
| b6849f55 NC |
194 | /* The new format of the INSTR_x_y and MASK_x_y defines is based |
| 195 | on the following rules: | |
| 196 | 1) the middle part of the definition (x in INSTR_x_y) is the official | |
| 197 | names of the instruction format that you can find in the principals | |
| 198 | of operation. | |
| 199 | 2) the last part of the definition (y in INSTR_x_y) gives you an idea | |
| 200 | which operands the binary represenation of the instruction has. | |
| 201 | The meanings of the letters in y are: | |
| 202 | a - access register | |
| 203 | c - control register | |
| 204 | d - displacement, 12 bit | |
| 205 | f - floating pointer register | |
| ad101263 | 206 | i - signed integer, 4, 8, 16 or 32 bit |
| b6849f55 NC |
207 | l - length, 4 or 8 bit |
| 208 | p - pc relative | |
| 209 | r - general purpose register | |
| ad101263 MS |
210 | u - unsigned integer, 4, 8, 16 or 32 bit |
| 211 | m - mode field, 4 bit | |
| b6849f55 NC |
212 | 0 - operand skipped. |
| 213 | The order of the letters reflects the layout of the format in | |
| 214 | storage and not the order of the paramaters of the instructions. | |
| 215 | The use of the letters is not a 100% match with the PoP but it is | |
| 216 | quite close. | |
| 217 | ||
| 218 | For example the instruction "mvo" is defined in the PoP as follows: | |
| 219 | ||
| 220 | MVO D1(L1,B1),D2(L2,B2) [SS] | |
| 221 | ||
| 222 | -------------------------------------- | |
| 223 | | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | | |
| 224 | -------------------------------------- | |
| 225 | 0 8 12 16 20 32 36 | |
| 226 | ||
| 227 | The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ | |
| 228 | ||
| 229 | #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ | |
| 230 | #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ | |
| 5746fb46 AK |
231 | #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ |
| 232 | #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ | |
| 233 | #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ | |
| 234 | #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ | |
| 235 | #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ | |
| 236 | #define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ | |
| 237 | #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ | |
| 238 | #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ | |
| 239 | #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ | |
| 240 | #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ | |
| 241 | #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ | |
| b6849f55 NC |
242 | #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ |
| 243 | #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ | |
| 244 | #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ | |
| ad101263 MS |
245 | #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
| 246 | #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ | |
| b6849f55 NC |
247 | #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
| 248 | #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ | |
| 249 | #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ | |
| 250 | #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ | |
| 251 | #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ | |
| 5746fb46 AK |
252 | #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ |
| 253 | #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ | |
| 254 | #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ | |
| 255 | #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ | |
| b6849f55 NC |
256 | #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ |
| 257 | #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ | |
| 258 | #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ | |
| 259 | #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ | |
| 260 | #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ | |
| 261 | #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ | |
| 262 | #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ | |
| 263 | #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ | |
| 264 | #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ | |
| 265 | #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ | |
| b5639b37 | 266 | #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
| b8e55848 MS |
267 | /* Actually efpc and sfpc do not take an optional operand. |
| 268 | This is just a workaround for existing code e.g. glibc. */ | |
| 269 | #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ | |
| b6849f55 | 270 | #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
| b5639b37 MS |
271 | #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
| 272 | #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ | |
| b6849f55 NC |
273 | #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
| 274 | #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ | |
| 725a9891 | 275 | #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ |
| 929e4d1a MS |
276 | #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ |
| 277 | #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ | |
| b5639b37 MS |
278 | #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
| 279 | #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ | |
| 7dc6076f | 280 | #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ |
| ad101263 | 281 | #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ |
| 5746fb46 AK |
282 | #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ |
| 283 | #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ | |
| b6849f55 | 284 | #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
| ce21feb4 | 285 | #define INSTR_RR_0R_OPT 2, { RO_12, 0,0,0,0,0 } /* e.g. nopr */ |
| b6849f55 NC |
286 | #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ |
| 287 | #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ | |
| 288 | #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ | |
| 289 | #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ | |
| 290 | #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ | |
| b5639b37 | 291 | #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
| 5746fb46 AK |
292 | #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ |
| 293 | #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ | |
| b6849f55 | 294 | #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| ad101263 | 295 | #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| b6849f55 | 296 | #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
| 98c3d905 | 297 | #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ |
| b6849f55 | 298 | #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
| bac02689 MS |
299 | #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
| 300 | #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ | |
| 301 | #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ | |
| ad101263 | 302 | #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
| b6849f55 NC |
303 | #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
| 304 | #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ | |
| 305 | #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ | |
| 306 | #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ | |
| 307 | #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ | |
| 308 | #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ | |
| 309 | #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ | |
| 310 | #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ | |
| 311 | #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ | |
| bac02689 MS |
312 | #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
| 313 | #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ | |
| 5746fb46 | 314 | #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ |
| b6849f55 | 315 | #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
| ce21feb4 | 316 | #define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 } /* e.g. nop */ |
| b6849f55 NC |
317 | #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ |
| 318 | #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ | |
| 319 | #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ | |
| 320 | #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ | |
| bac02689 | 321 | #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
| 5746fb46 AK |
322 | #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ |
| 323 | #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ | |
| 324 | #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ | |
| b6849f55 NC |
325 | #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ |
| 326 | #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ | |
| b2e818b7 | 327 | #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
| b6849f55 NC |
328 | #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
| 329 | #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ | |
| 330 | #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ | |
| 331 | #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ | |
| 332 | #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ | |
| 5746fb46 | 333 | #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
| b6849f55 NC |
334 | #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ |
| 335 | #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ | |
| 336 | ||
| 337 | #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 338 | #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 5746fb46 AK |
339 | #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 340 | #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| 341 | #define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 342 | #define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| 343 | #define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 344 | #define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| 345 | #define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } | |
| 346 | #define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| 347 | #define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } | |
| 348 | #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| 349 | #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
350 | #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 351 | #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 352 | #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| ad101263 MS |
353 | #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 354 | #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
355 | #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 356 | #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 357 | #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 358 | #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 359 | #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 AK |
360 | #define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 361 | #define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } | |
| 362 | #define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 363 | #define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
364 | #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 365 | #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } | |
| 366 | #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 367 | #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 368 | #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } | |
| 369 | #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 370 | #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } | |
| 371 | #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 372 | #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 373 | #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| b5639b37 | 374 | #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b8e55848 | 375 | #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b6849f55 | 376 | #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 MS |
377 | #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 378 | #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
379 | #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 380 | #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 | 381 | #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 382 | #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 929e4d1a | 383 | #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 MS |
384 | #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 385 | #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } | |
| 7dc6076f | 386 | #define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| ad101263 | 387 | #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5746fb46 AK |
388 | #define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 389 | #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| b6849f55 | 390 | #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| ce21feb4 | 391 | #define MASK_RR_0R_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
392 | #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 393 | #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 394 | #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 395 | #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 396 | #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b5639b37 | 397 | #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5746fb46 AK |
398 | #define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
| 399 | #define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } | |
| b6849f55 | 400 | #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| ad101263 | 401 | #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 | 402 | #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| bac02689 | 403 | #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 NC |
404 | #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 405 | #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 406 | #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 407 | #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 408 | #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 409 | #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 MS |
410 | #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 411 | #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 412 | #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| ad101263 | 413 | #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 NC |
414 | #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 415 | #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 416 | #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 417 | #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| bac02689 MS |
418 | #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 419 | #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 5746fb46 | 420 | #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 | 421 | #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| ce21feb4 | 422 | #define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
423 | #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 424 | #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 425 | #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 426 | #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 | 427 | #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 5746fb46 AK |
428 | #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 429 | #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 430 | #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
431 | #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 432 | #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b2e818b7 | 433 | #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
434 | #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 435 | #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 436 | #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 437 | #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 438 | #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 | 439 | #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
440 | #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 441 | #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 | 442 | |
| b6849f55 NC |
443 | |
| 444 | /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ | |
| a85d7ed0 | 445 | |
| 82b66b23 NC |
446 | const struct s390_opcode s390_opformats[] = |
| 447 | { | |
| af169f23 MS |
448 | { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, |
| 449 | { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, | |
| 450 | { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, | |
| 451 | { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, | |
| ad101263 | 452 | { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, |
| 5746fb46 | 453 | { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 }, |
| af169f23 MS |
454 | { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, |
| 455 | { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, | |
| 456 | { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, | |
| 5746fb46 | 457 | { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 }, |
| af169f23 MS |
458 | { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, |
| 459 | { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, | |
| 460 | { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, | |
| bac02689 | 461 | { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, |
| af169f23 MS |
462 | { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, |
| 463 | { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, | |
| 464 | { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, | |
| bac02689 | 465 | { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, |
| af169f23 MS |
466 | { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, |
| 467 | { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, | |
| bac02689 | 468 | { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, |
| 5746fb46 | 469 | { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 }, |
| af169f23 MS |
470 | { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, |
| 471 | { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, | |
| ad101263 | 472 | { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, |
| a85d7ed0 NC |
473 | }; |
| 474 | ||
| 475 | const int s390_num_opformats = | |
| 476 | sizeof (s390_opformats) / sizeof (s390_opformats[0]); | |
| 477 | ||
| b6849f55 | 478 | #include "s390-opc.tab" |