[deliverable/binutils-gdb.git] / opcodes / sh-dis.c

/* Disassemble SH instructions.
   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001
   Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <stdio.h>
#include "sysdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE

#include "sh-opc.h"
#include "dis-asm.h"

static void print_movxy
  PARAMS ((sh_opcode_info *, int, int, fprintf_ftype, void *));
static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
static void print_insn_ppi PARAMS ((int, struct disassemble_info *));

static void
print_movxy (op, rn, rm, fprintf_fn, stream)
     sh_opcode_info *op;
     int rn, rm;
     fprintf_ftype fprintf_fn;
     void *stream;
{
  int n;

  fprintf_fn (stream, "%s\t", op->name);
  for (n = 0; n < 2; n++)
    {
      switch (op->arg[n])
	{
	case A_IND_N:
	  fprintf_fn (stream, "@r%d", rn);
	  break;
	case A_INC_N:
	  fprintf_fn (stream, "@r%d+", rn);
	  break;
	case A_PMOD_N:
	  fprintf_fn (stream, "@r%d+r8", rn);
	  break;
	case A_PMODY_N:
	  fprintf_fn (stream, "@r%d+r9", rn);
	  break;
	case DSP_REG_M:
	  fprintf_fn (stream, "a%c", '0' + rm);
	  break;
	case DSP_REG_X:
	  fprintf_fn (stream, "x%c", '0' + rm);
	  break;
	case DSP_REG_Y:
	  fprintf_fn (stream, "y%c", '0' + rm);
	  break;
	default:
	  abort ();
	}
      if (n == 0)
	fprintf_fn (stream, ",");
    }
}

/* Print a double data transfer insn.  INSN is just the lower three
   nibbles of the insn, i.e. field a and the bit that indicates if
   a parallel processing insn follows.
   Return nonzero if a field b of a parallel processing insns follows.  */

static void
print_insn_ddt (insn, info)
     int insn;
     struct disassemble_info *info;
{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;

  /* If this is just a nop, make sure to emit something.  */
  if (insn == 0x000)
    fprintf_fn (stream, "nopx\tnopy");

  /* If a parallel processing insn was printed before,
     and we got a non-nop, emit a tab.  */
  if ((insn & 0x800) && (insn & 0x3ff))
    fprintf_fn (stream, "\t");

  /* Check if either the x or y part is invalid.  */
  if (((insn & 0xc) == 0 && (insn & 0x2a0))
      || ((insn & 3) == 0 && (insn & 0x150)))
    fprintf_fn (stream, ".word 0x%x", insn);
  else
    {
      static sh_opcode_info *first_movx, *first_movy;
      sh_opcode_info *opx, *opy;
      unsigned int insn_x, insn_y;

      if (! first_movx)
	{
	  for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
	    first_movx++;
	  for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
	    first_movy++;
	}
      insn_x = (insn >> 2) & 0xb;
      if (insn_x)
	{
	  for (opx = first_movx; opx->nibbles[2] != insn_x;)
	    opx++;
	  print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
		       fprintf_fn, stream);
	}
      insn_y = (insn & 3) | ((insn >> 1) & 8);
      if (insn_y)
	{
	  if (insn_x)
	    fprintf_fn (stream, "\t");
	  for (opy = first_movy; opy->nibbles[2] != insn_y;)
	    opy++;
	  print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
		       fprintf_fn, stream);
	}
    }
}

static void
print_dsp_reg (rm, fprintf_fn, stream)
     int rm;
     fprintf_ftype fprintf_fn;
     void *stream;
{
  switch (rm)
    {
    case A_A1_NUM:
      fprintf_fn (stream, "a1");
      break;
    case A_A0_NUM:
      fprintf_fn (stream, "a0");
      break;
    case A_X0_NUM:
      fprintf_fn (stream, "x0");
      break;
    case A_X1_NUM:
      fprintf_fn (stream, "x1");
      break;
    case A_Y0_NUM:
      fprintf_fn (stream, "y0");
      break;
    case A_Y1_NUM:
      fprintf_fn (stream, "y1");
      break;
    case A_M0_NUM:
      fprintf_fn (stream, "m0");
      break;
    case A_A1G_NUM:
      fprintf_fn (stream, "a1g");
      break;
    case A_M1_NUM:
      fprintf_fn (stream, "m1");
      break;
    case A_A0G_NUM:
      fprintf_fn (stream, "a0g");
      break;
    default:
      fprintf_fn (stream, "0x%x", rm);
      break;
    }
}

static void
print_insn_ppi (field_b, info)
     int field_b;
     struct disassemble_info *info;
{
  static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
  static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  unsigned int nib1, nib2, nib3;
  char *dc = NULL;
  sh_opcode_info *op;

  if ((field_b & 0xe800) == 0)
    {
      fprintf_fn (stream, "psh%c\t#%d,",
		  field_b & 0x1000 ? 'a' : 'l',
		  (field_b >> 4) & 127);
      print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
      return;
    }
  if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
    {
      static char *du_tab[] = { "x0", "y0", "a0", "a1" };
      static char *se_tab[] = { "x0", "x1", "y0", "a1" };
      static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
      static char *sg_tab[] = { "m0", "m1", "a0", "a1" };

      if (field_b & 0x2000)
	{
	  fprintf_fn (stream, "p%s %s,%s,%s\t",
		      (field_b & 0x1000) ? "add" : "sub",
		      sx_tab[(field_b >> 6) & 3],
		      sy_tab[(field_b >> 4) & 3],
		      du_tab[(field_b >> 0) & 3]);
	}
      fprintf_fn (stream, "pmuls%c%s,%s,%s",
		  field_b & 0x2000 ? ' ' : '\t',
		  se_tab[(field_b >> 10) & 3],
		  sf_tab[(field_b >>  8) & 3],
		  sg_tab[(field_b >>  2) & 3]);
      return;
    }

  nib1 = PPIC;
  nib2 = field_b >> 12 & 0xf;
  nib3 = field_b >> 8 & 0xf;
  switch (nib3 & 0x3)
    {
    case 0:
      dc = "";
      nib1 = PPI3;
      break;
    case 1:
      dc = "";
      break;
    case 2:
      dc = "dct ";
      nib3 -= 1;
      break;
    case 3:
      dc = "dcf ";
      nib3 -= 2;
      break;
    }
  for (op = sh_table; op->name; op++)
    {
      if (op->nibbles[1] == nib1
	  && op->nibbles[2] == nib2
	  && op->nibbles[3] == nib3)
	{
	  int n;

	  fprintf_fn (stream, "%s%s\t", dc, op->name);
	  for (n = 0; n < 3 && op->arg[n] != A_END; n++)
	    {
	      if (n && op->arg[1] != A_END)
		fprintf_fn (stream, ",");
	      switch (op->arg[n])
		{
		case DSP_REG_N:
		  print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
		  break;
		case DSP_REG_X:
		  fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
		  break;
		case DSP_REG_Y:
		  fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
		  break;
		case A_MACH:
		  fprintf_fn (stream, "mach");
		  break;
		case A_MACL:
		  fprintf_fn (stream, "macl");
		  break;
		default:
		  abort ();
		}
	    }
	  return;
	}
    }
  /* Not found.  */
  fprintf_fn (stream, ".word 0x%x", field_b);
}

int
print_insn_sh (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  unsigned char insn[2];
  unsigned char nibs[4];
  int status;
  bfd_vma relmask = ~(bfd_vma) 0;
  sh_opcode_info *op;
  int target_arch;

  switch (info->mach)
    {
    case bfd_mach_sh:
      target_arch = arch_sh1;
      /* SH coff object files lack information about the machine type, so
         we end up with bfd_mach_sh unless it was set explicitly (which
	 could have happended if this is a call from gdb or the simulator.)  */
      if (bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour)
	target_arch = arch_sh4;
      break;
    case bfd_mach_sh2:
      target_arch = arch_sh2;
      break;
    case bfd_mach_sh_dsp:
      target_arch = arch_sh_dsp;
      break;
    case bfd_mach_sh3:
      target_arch = arch_sh3;
      break;
    case bfd_mach_sh3_dsp:
      target_arch = arch_sh3_dsp;
      break;
    case bfd_mach_sh3e:
      target_arch = arch_sh3e;
      break;
    case bfd_mach_sh4:
      target_arch = arch_sh4;
      break;
    case bfd_mach_sh5:
#ifdef INCLUDE_SHMEDIA
      status = print_insn_sh64 (memaddr, info);
      if (status != -2)
	return status;
#endif
      /* When we get here for sh64, it's because we want to disassemble
	 SHcompact, i.e. arch_sh4.  */
      target_arch = arch_sh4;
      break;
    default:
      abort ();
    }

  status = info->read_memory_func (memaddr, insn, 2, info);

  if (status != 0)
    {
      info->memory_error_func (status, memaddr, info);
      return -1;
    }

  if (info->endian == BFD_ENDIAN_LITTLE)
    {
      nibs[0] = (insn[1] >> 4) & 0xf;
      nibs[1] = insn[1] & 0xf;

      nibs[2] = (insn[0] >> 4) & 0xf;
      nibs[3] = insn[0] & 0xf;
    }
  else
    {
      nibs[0] = (insn[0] >> 4) & 0xf;
      nibs[1] = insn[0] & 0xf;

      nibs[2] = (insn[1] >> 4) & 0xf;
      nibs[3] = insn[1] & 0xf;
    }

  if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up)
    {
      if (nibs[1] & 8)
	{
	  int field_b;

	  status = info->read_memory_func (memaddr + 2, insn, 2, info);

	  if (status != 0)
	    {
	      info->memory_error_func (status, memaddr + 2, info);
	      return -1;
	    }

	  if (info->endian == BFD_ENDIAN_LITTLE)
	    field_b = insn[1] << 8 | insn[0];
	  else
	    field_b = insn[0] << 8 | insn[1];

	  print_insn_ppi (field_b, info);
	  print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
	  return 4;
	}
      print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
      return 2;
    }
  for (op = sh_table; op->name; op++)
    {
      int n;
      int imm = 0;
      int rn = 0;
      int rm = 0;
      int rb = 0;
      int disp_pc;
      bfd_vma disp_pc_addr = 0;

      if ((op->arch & target_arch) == 0)
	goto fail;
      for (n = 0; n < 4; n++)
	{
	  int i = op->nibbles[n];

	  if (i < 16)
	    {
	      if (nibs[n] == i)
		continue;
	      goto fail;
	    }
	  switch (i)
	    {
	    case BRANCH_8:
	      imm = (nibs[2] << 4) | (nibs[3]);
	      if (imm & 0x80)
		imm |= ~0xff;
	      imm = ((char) imm) * 2 + 4;
	      goto ok;
	    case BRANCH_12:
	      imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
	      if (imm & 0x800)
		imm |= ~0xfff;
	      imm = imm * 2 + 4;
	      goto ok;
	    case IMM0_4:
	    case IMM1_4:
	      imm = nibs[3];
	      goto ok;
	    case IMM0_4BY2:
	    case IMM1_4BY2:
	      imm = nibs[3] << 1;
	      goto ok;
	    case IMM0_4BY4:
	    case IMM1_4BY4:
	      imm = nibs[3] << 2;
	      goto ok;
	    case IMM0_8:
	    case IMM1_8:
	      imm = (nibs[2] << 4) | nibs[3];
	      goto ok;
	    case PCRELIMM_8BY2:
	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
	      relmask = ~(bfd_vma) 1;
	      goto ok;
	    case PCRELIMM_8BY4:
	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
	      relmask = ~(bfd_vma) 3;
	      goto ok;
	    case IMM0_8BY2:
	    case IMM1_8BY2:
	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
	      goto ok;
	    case IMM0_8BY4:
	    case IMM1_8BY4:
	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
	      goto ok;
	    case REG_N:
	      rn = nibs[n];
	      break;
	    case REG_M:
	      rm = nibs[n];
	      break;
	    case REG_NM:
	      rn = (nibs[n] & 0xc) >> 2;
	      rm = (nibs[n] & 0x3);
	      break;
	    case REG_B:
	      rb = nibs[n] & 0x07;
	      break;
	    case SDT_REG_N:
	      /* sh-dsp: single data transfer.  */
	      rn = nibs[n];
	      if ((rn & 0xc) != 4)
		goto fail;
	      rn = rn & 0x3;
	      rn |= (!(rn & 2)) << 2;
	      break;
	    case PPI:
	    case REPEAT:
	      goto fail;
	    default:
	      abort ();
	    }
	}

    ok:
      fprintf_fn (stream, "%s\t", op->name);
      disp_pc = 0;
      for (n = 0; n < 3 && op->arg[n] != A_END; n++)
	{
	  if (n && op->arg[1] != A_END)
	    fprintf_fn (stream, ",");
	  switch (op->arg[n])
	    {
	    case A_IMM:
	      fprintf_fn (stream, "#%d", (char) (imm));
	      break;
	    case A_R0:
	      fprintf_fn (stream, "r0");
	      break;
	    case A_REG_N:
	      fprintf_fn (stream, "r%d", rn);
	      break;
	    case A_INC_N:
	      fprintf_fn (stream, "@r%d+", rn);
	      break;
	    case A_DEC_N:
	      fprintf_fn (stream, "@-r%d", rn);
	      break;
	    case A_IND_N:
	      fprintf_fn (stream, "@r%d", rn);
	      break;
	    case A_DISP_REG_N:
	      fprintf_fn (stream, "@(%d,r%d)", imm, rn);
	      break;
	    case A_PMOD_N:
	      fprintf_fn (stream, "@r%d+r8", rn);
	      break;
	    case A_REG_M:
	      fprintf_fn (stream, "r%d", rm);
	      break;
	    case A_INC_M:
	      fprintf_fn (stream, "@r%d+", rm);
	      break;
	    case A_DEC_M:
	      fprintf_fn (stream, "@-r%d", rm);
	      break;
	    case A_IND_M:
	      fprintf_fn (stream, "@r%d", rm);
	      break;
	    case A_DISP_REG_M:
	      fprintf_fn (stream, "@(%d,r%d)", imm, rm);
	      break;
	    case A_REG_B:
	      fprintf_fn (stream, "r%d_bank", rb);
	      break;
	    case A_DISP_PC:
	      disp_pc = 1;
	      disp_pc_addr = imm + 4 + (memaddr & relmask);
	      (*info->print_address_func) (disp_pc_addr, info);
	      break;
	    case A_IND_R0_REG_N:
	      fprintf_fn (stream, "@(r0,r%d)", rn);
	      break;
	    case A_IND_R0_REG_M:
	      fprintf_fn (stream, "@(r0,r%d)", rm);
	      break;
	    case A_DISP_GBR:
	      fprintf_fn (stream, "@(%d,gbr)", imm);
	      break;
	    case A_R0_GBR:
	      fprintf_fn (stream, "@(r0,gbr)");
	      break;
	    case A_BDISP12:
	    case A_BDISP8:
	      (*info->print_address_func) (imm + memaddr, info);
	      break;
	    case A_SR:
	      fprintf_fn (stream, "sr");
	      break;
	    case A_GBR:
	      fprintf_fn (stream, "gbr");
	      break;
	    case A_VBR:
	      fprintf_fn (stream, "vbr");
	      break;
	    case A_DSR:
	      fprintf_fn (stream, "dsr");
	      break;
	    case A_MOD:
	      fprintf_fn (stream, "mod");
	      break;
	    case A_RE:
	      fprintf_fn (stream, "re");
	      break;
	    case A_RS:
	      fprintf_fn (stream, "rs");
	      break;
	    case A_A0:
	      fprintf_fn (stream, "a0");
	      break;
	    case A_X0:
	      fprintf_fn (stream, "x0");
	      break;
	    case A_X1:
	      fprintf_fn (stream, "x1");
	      break;
	    case A_Y0:
	      fprintf_fn (stream, "y0");
	      break;
	    case A_Y1:
	      fprintf_fn (stream, "y1");
	      break;
	    case DSP_REG_M:
	      print_dsp_reg (rm, fprintf_fn, stream);
	      break;
	    case A_SSR:
	      fprintf_fn (stream, "ssr");
	      break;
	    case A_SPC:
	      fprintf_fn (stream, "spc");
	      break;
	    case A_MACH:
	      fprintf_fn (stream, "mach");
	      break;
	    case A_MACL:
	      fprintf_fn (stream, "macl");
	      break;
	    case A_PR:
	      fprintf_fn (stream, "pr");
	      break;
	    case A_SGR:
	      fprintf_fn (stream, "sgr");
	      break;
	    case A_DBR:
	      fprintf_fn (stream, "dbr");
	      break;
	    case F_REG_N:
	      fprintf_fn (stream, "fr%d", rn);
	      break;
	    case F_REG_M:
	      fprintf_fn (stream, "fr%d", rm);
	      break;
	    case DX_REG_N:
	      if (rn & 1)
		{
		  fprintf_fn (stream, "xd%d", rn & ~1);
		  break;
		}
	    case D_REG_N:
	      fprintf_fn (stream, "dr%d", rn);
	      break;
	    case DX_REG_M:
	      if (rm & 1)
		{
		  fprintf_fn (stream, "xd%d", rm & ~1);
		  break;
		}
	    case D_REG_M:
	      fprintf_fn (stream, "dr%d", rm);
	      break;
	    case FPSCR_M:
	    case FPSCR_N:
	      fprintf_fn (stream, "fpscr");
	      break;
	    case FPUL_M:
	    case FPUL_N:
	      fprintf_fn (stream, "fpul");
	      break;
	    case F_FR0:
	      fprintf_fn (stream, "fr0");
	      break;
	    case V_REG_N:
	      fprintf_fn (stream, "fv%d", rn * 4);
	      break;
	    case V_REG_M:
	      fprintf_fn (stream, "fv%d", rm * 4);
	      break;
	    case XMTRX_M4:
	      fprintf_fn (stream, "xmtrx");
	      break;
	    default:
	      abort ();
	    }
	}

#if 0
      /* This code prints instructions in delay slots on the same line
         as the instruction which needs the delay slots.  This can be
         confusing, since other disassembler don't work this way, and
         it means that the instructions are not all in a line.  So I
         disabled it.  Ian.  */
      if (!(info->flags & 1)
	  && (op->name[0] == 'j'
	      || (op->name[0] == 'b'
		  && (op->name[1] == 'r'
		      || op->name[1] == 's'))
	      || (op->name[0] == 'r' && op->name[1] == 't')
	      || (op->name[0] == 'b' && op->name[2] == '.')))
	{
	  info->flags |= 1;
	  fprintf_fn (stream, "\t(slot ");
	  print_insn_sh (memaddr + 2, info);
	  info->flags &= ~1;
	  fprintf_fn (stream, ")");
	  return 4;
	}
#endif

      if (disp_pc && strcmp (op->name, "mova") != 0)
	{
	  int size;
	  bfd_byte bytes[4];

	  if (relmask == ~(bfd_vma) 1)
	    size = 2;
	  else
	    size = 4;
	  status = info->read_memory_func (disp_pc_addr, bytes, size, info);
	  if (status == 0)
	    {
	      unsigned int val;

	      if (size == 2)
		{
		  if (info->endian == BFD_ENDIAN_LITTLE)
		    val = bfd_getl16 (bytes);
		  else
		    val = bfd_getb16 (bytes);
		}
	      else
		{
		  if (info->endian == BFD_ENDIAN_LITTLE)
		    val = bfd_getl32 (bytes);
		  else
		    val = bfd_getb32 (bytes);
		}
	      fprintf_fn (stream, "\t! 0x%x", val);
	    }
	}

      return 2;
    fail:
      ;

    }
  fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
  return 2;
}
Commit	Line	Data
252b5132	1	/* Disassemble SH instructions.
d83c6548	2	Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001
69eb4bbf	3	Free Software Foundation, Inc.
252b5132 RH	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	18
	19	#include <stdio.h>
0d8dfecf	20	#include "sysdep.h"
252b5132 RH	21	#define STATIC_TABLE
	22	#define DEFINE_TABLE
	23
	24	#include "sh-opc.h"
	25	#include "dis-asm.h"
	26
d83c6548 AJ	27	static void print_movxy
	28	PARAMS ((sh_opcode_info , int, int, fprintf_ftype, void ));
	29	static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
	30	static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
	31	static void print_insn_ppi PARAMS ((int, struct disassemble_info *));
d83c6548	32
d4845d57 JR	33	static void
	34	print_movxy (op, rn, rm, fprintf_fn, stream)
	35	sh_opcode_info *op;
	36	int rn, rm;
	37	fprintf_ftype fprintf_fn;
	38	void *stream;
	39	{
	40	int n;
	41
69eb4bbf	42	fprintf_fn (stream, "%s\t", op->name);
d4845d57 JR	43	for (n = 0; n < 2; n++)
	44	{
	45	switch (op->arg[n])
	46	{
	47	case A_IND_N:
69eb4bbf	48	fprintf_fn (stream, "@r%d", rn);
d4845d57 JR	49	break;
d4845d57 JR	50	case A_INC_N:
69eb4bbf	51	fprintf_fn (stream, "@r%d+", rn);
d4845d57 JR	52	break;
d4845d57 JR	53	case A_PMOD_N:
69eb4bbf	54	fprintf_fn (stream, "@r%d+r8", rn);
d4845d57 JR	55	break;
d4845d57 JR	56	case A_PMODY_N:
69eb4bbf	57	fprintf_fn (stream, "@r%d+r9", rn);
d4845d57 JR	58	break;
	59	case DSP_REG_M:
	60	fprintf_fn (stream, "a%c", '0' + rm);
	61	break;
	62	case DSP_REG_X:
	63	fprintf_fn (stream, "x%c", '0' + rm);
	64	break;
	65	case DSP_REG_Y:
	66	fprintf_fn (stream, "y%c", '0' + rm);
	67	break;
	68	default:
	69	abort ();
	70	}
	71	if (n == 0)
69eb4bbf	72	fprintf_fn (stream, ",");
d4845d57 JR	73	}
	74	}
	75
	76	/* Print a double data transfer insn. INSN is just the lower three
	77	nibbles of the insn, i.e. field a and the bit that indicates if
	78	a parallel processing insn follows.
	79	Return nonzero if a field b of a parallel processing insns follows. */
69eb4bbf	80
d4845d57 JR	81	static void
	82	print_insn_ddt (insn, info)
	83	int insn;
	84	struct disassemble_info *info;
	85	{
	86	fprintf_ftype fprintf_fn = info->fprintf_func;
	87	void *stream = info->stream;
	88
	89	/* If this is just a nop, make sure to emit something. */
	90	if (insn == 0x000)
	91	fprintf_fn (stream, "nopx\tnopy");
	92
	93	/* If a parallel processing insn was printed before,
	94	and we got a non-nop, emit a tab. */
	95	if ((insn & 0x800) && (insn & 0x3ff))
	96	fprintf_fn (stream, "\t");
	97
	98	/* Check if either the x or y part is invalid. */
	99	if (((insn & 0xc) == 0 && (insn & 0x2a0))
	100	\|\| ((insn & 3) == 0 && (insn & 0x150)))
	101	fprintf_fn (stream, ".word 0x%x", insn);
	102	else
	103	{
	104	static sh_opcode_info first_movx, first_movy;
	105	sh_opcode_info opx, opy;
caaaf822	106	unsigned int insn_x, insn_y;
d4845d57 JR	107
	108	if (! first_movx)
	109	{
69eb4bbf	110	for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
d4845d57	111	first_movx++;
69eb4bbf	112	for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
d4845d57 JR	113	first_movy++;
	114	}
	115	insn_x = (insn >> 2) & 0xb;
	116	if (insn_x)
	117	{
69eb4bbf KH	118	for (opx = first_movx; opx->nibbles[2] != insn_x;)
69eb4bbf KH	119	opx++;
d4845d57 JR	120	print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
	121	fprintf_fn, stream);
	122	}
	123	insn_y = (insn & 3) \| ((insn >> 1) & 8);
	124	if (insn_y)
	125	{
	126	if (insn_x)
	127	fprintf_fn (stream, "\t");
69eb4bbf KH	128	for (opy = first_movy; opy->nibbles[2] != insn_y;)
69eb4bbf KH	129	opy++;
d4845d57 JR	130	print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
	131	fprintf_fn, stream);
	132	}
	133	}
	134	}
	135
	136	static void
	137	print_dsp_reg (rm, fprintf_fn, stream)
	138	int rm;
	139	fprintf_ftype fprintf_fn;
	140	void *stream;
	141	{
	142	switch (rm)
	143	{
	144	case A_A1_NUM:
	145	fprintf_fn (stream, "a1");
	146	break;
	147	case A_A0_NUM:
	148	fprintf_fn (stream, "a0");
	149	break;
	150	case A_X0_NUM:
	151	fprintf_fn (stream, "x0");
	152	break;
	153	case A_X1_NUM:
	154	fprintf_fn (stream, "x1");
	155	break;
	156	case A_Y0_NUM:
	157	fprintf_fn (stream, "y0");
	158	break;
	159	case A_Y1_NUM:
	160	fprintf_fn (stream, "y1");
	161	break;
	162	case A_M0_NUM:
	163	fprintf_fn (stream, "m0");
	164	break;
	165	case A_A1G_NUM:
	166	fprintf_fn (stream, "a1g");
	167	break;
	168	case A_M1_NUM:
	169	fprintf_fn (stream, "m1");
	170	break;
	171	case A_A0G_NUM:
	172	fprintf_fn (stream, "a0g");
	173	break;
	174	default:
	175	fprintf_fn (stream, "0x%x", rm);
	176	break;
	177	}
	178	}
	179
	180	static void
	181	print_insn_ppi (field_b, info)
	182	int field_b;
	183	struct disassemble_info *info;
	184	{
69eb4bbf KH	185	static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
69eb4bbf KH	186	static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
d4845d57 JR	187	fprintf_ftype fprintf_fn = info->fprintf_func;
d4845d57 JR	188	void *stream = info->stream;
caaaf822 HPN	189	unsigned int nib1, nib2, nib3;
caaaf822 HPN	190	char *dc = NULL;
d4845d57 JR	191	sh_opcode_info *op;
	192
	193	if ((field_b & 0xe800) == 0)
	194	{
	195	fprintf_fn (stream, "psh%c\t#%d,",
	196	field_b & 0x1000 ? 'a' : 'l',
	197	(field_b >> 4) & 127);
	198	print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
	199	return;
	200	}
	201	if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
	202	{
69eb4bbf KH	203	static char *du_tab[] = { "x0", "y0", "a0", "a1" };
	204	static char *se_tab[] = { "x0", "x1", "y0", "a1" };
	205	static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
	206	static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
d4845d57 JR	207
	208	if (field_b & 0x2000)
	209	{
	210	fprintf_fn (stream, "p%s %s,%s,%s\t",
	211	(field_b & 0x1000) ? "add" : "sub",
	212	sx_tab[(field_b >> 6) & 3],
	213	sy_tab[(field_b >> 4) & 3],
	214	du_tab[(field_b >> 0) & 3]);
	215	}
	216	fprintf_fn (stream, "pmuls%c%s,%s,%s",
	217	field_b & 0x2000 ? ' ' : '\t',
	218	se_tab[(field_b >> 10) & 3],
	219	sf_tab[(field_b >> 8) & 3],
	220	sg_tab[(field_b >> 2) & 3]);
	221	return;
	222	}
	223
	224	nib1 = PPIC;
	225	nib2 = field_b >> 12 & 0xf;
	226	nib3 = field_b >> 8 & 0xf;
	227	switch (nib3 & 0x3)
	228	{
	229	case 0:
	230	dc = "";
	231	nib1 = PPI3;
	232	break;
	233	case 1:
	234	dc = "";
	235	break;
	236	case 2:
	237	dc = "dct ";
	238	nib3 -= 1;
	239	break;
	240	case 3:
	241	dc = "dcf ";
	242	nib3 -= 2;
	243	break;
	244	}
	245	for (op = sh_table; op->name; op++)
	246	{
	247	if (op->nibbles[1] == nib1
	248	&& op->nibbles[2] == nib2
	249	&& op->nibbles[3] == nib3)
	250	{
	251	int n;
	252
	253	fprintf_fn (stream, "%s%s\t", dc, op->name);
69eb4bbf	254	for (n = 0; n < 3 && op->arg[n] != A_END; n++)
d4845d57 JR	255	{
	256	if (n && op->arg[1] != A_END)
	257	fprintf_fn (stream, ",");
69eb4bbf	258	switch (op->arg[n])
d4845d57 JR	259	{
	260	case DSP_REG_N:
	261	print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
	262	break;
	263	case DSP_REG_X:
	264	fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
	265	break;
	266	case DSP_REG_Y:
	267	fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
	268	break;
	269	case A_MACH:
	270	fprintf_fn (stream, "mach");
	271	break;
	272	case A_MACL:
69eb4bbf	273	fprintf_fn (stream, "macl");
d4845d57 JR	274	break;
	275	default:
	276	abort ();
	277	}
	278	}
	279	return;
	280	}
	281	}
	282	/* Not found. */
	283	fprintf_fn (stream, ".word 0x%x", field_b);
	284	}
	285
1c509ca8 JR	286	int
1c509ca8 JR	287	print_insn_sh (memaddr, info)
252b5132 RH	288	bfd_vma memaddr;
	289	struct disassemble_info *info;
	290	{
	291	fprintf_ftype fprintf_fn = info->fprintf_func;
	292	void *stream = info->stream;
	293	unsigned char insn[2];
	294	unsigned char nibs[4];
	295	int status;
69eb4bbf	296	bfd_vma relmask = ~(bfd_vma) 0;
252b5132	297	sh_opcode_info *op;
d4845d57 JR	298	int target_arch;
	299
	300	switch (info->mach)
	301	{
	302	case bfd_mach_sh:
	303	target_arch = arch_sh1;
426e6456 JR	304	/* SH coff object files lack information about the machine type, so
	305	we end up with bfd_mach_sh unless it was set explicitly (which
	306	could have happended if this is a call from gdb or the simulator.) */
	307	if (bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour)
	308	target_arch = arch_sh4;
d4845d57 JR	309	break;
	310	case bfd_mach_sh2:
	311	target_arch = arch_sh2;
	312	break;
	313	case bfd_mach_sh_dsp:
	314	target_arch = arch_sh_dsp;
	315	break;
	316	case bfd_mach_sh3:
	317	target_arch = arch_sh3;
	318	break;
	319	case bfd_mach_sh3_dsp:
	320	target_arch = arch_sh3_dsp;
	321	break;
	322	case bfd_mach_sh3e:
	323	target_arch = arch_sh3e;
	324	break;
	325	case bfd_mach_sh4:
	326	target_arch = arch_sh4;
	327	break;
d28847ce	328	case bfd_mach_sh5:
1c509ca8 JR	329	#ifdef INCLUDE_SHMEDIA
	330	status = print_insn_sh64 (memaddr, info);
	331	if (status != -2)
	332	return status;
	333	#endif
d28847ce AO	334	/* When we get here for sh64, it's because we want to disassemble
	335	SHcompact, i.e. arch_sh4. */
	336	target_arch = arch_sh4;
	337	break;
d4845d57 JR	338	default:
	339	abort ();
	340	}
252b5132 RH	341
	342	status = info->read_memory_func (memaddr, insn, 2, info);
	343
69eb4bbf	344	if (status != 0)
252b5132 RH	345	{
	346	info->memory_error_func (status, memaddr, info);
	347	return -1;
	348	}
	349
1c509ca8	350	if (info->endian == BFD_ENDIAN_LITTLE)
252b5132 RH	351	{
	352	nibs[0] = (insn[1] >> 4) & 0xf;
	353	nibs[1] = insn[1] & 0xf;
	354
	355	nibs[2] = (insn[0] >> 4) & 0xf;
	356	nibs[3] = insn[0] & 0xf;
	357	}
69eb4bbf	358	else
252b5132 RH	359	{
	360	nibs[0] = (insn[0] >> 4) & 0xf;
	361	nibs[1] = insn[0] & 0xf;
	362
	363	nibs[2] = (insn[1] >> 4) & 0xf;
	364	nibs[3] = insn[1] & 0xf;
	365	}
	366
d4845d57 JR	367	if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up)
	368	{
	369	if (nibs[1] & 8)
	370	{
	371	int field_b;
	372
	373	status = info->read_memory_func (memaddr + 2, insn, 2, info);
	374
69eb4bbf	375	if (status != 0)
d4845d57 JR	376	{
	377	info->memory_error_func (status, memaddr + 2, info);
	378	return -1;
	379	}
	380
1c509ca8	381	if (info->endian == BFD_ENDIAN_LITTLE)
d4845d57 JR	382	field_b = insn[1] << 8 \| insn[0];
	383	else
	384	field_b = insn[0] << 8 \| insn[1];
	385
	386	print_insn_ppi (field_b, info);
	387	print_insn_ddt ((nibs[1] << 8) \| (nibs[2] << 4) \| nibs[3], info);
	388	return 4;
	389	}
	390	print_insn_ddt ((nibs[1] << 8) \| (nibs[2] << 4) \| nibs[3], info);
	391	return 2;
	392	}
69eb4bbf	393	for (op = sh_table; op->name; op++)
252b5132 RH	394	{
	395	int n;
	396	int imm = 0;
	397	int rn = 0;
	398	int rm = 0;
	399	int rb = 0;
	400	int disp_pc;
	401	bfd_vma disp_pc_addr = 0;
	402
d4845d57 JR	403	if ((op->arch & target_arch) == 0)
d4845d57 JR	404	goto fail;
252b5132 RH	405	for (n = 0; n < 4; n++)
	406	{
	407	int i = op->nibbles[n];
	408
69eb4bbf	409	if (i < 16)
252b5132 RH	410	{
	411	if (nibs[n] == i)
	412	continue;
	413	goto fail;
	414	}
	415	switch (i)
	416	{
	417	case BRANCH_8:
69eb4bbf	418	imm = (nibs[2] << 4) \| (nibs[3]);
252b5132 RH	419	if (imm & 0x80)
252b5132 RH	420	imm \|= ~0xff;
69eb4bbf	421	imm = ((char) imm) * 2 + 4;
252b5132 RH	422	goto ok;
	423	case BRANCH_12:
	424	imm = ((nibs[1]) << 8) \| (nibs[2] << 4) \| (nibs[3]);
	425	if (imm & 0x800)
	426	imm \|= ~0xfff;
	427	imm = imm * 2 + 4;
	428	goto ok;
015551fc JR	429	case IMM0_4:
015551fc JR	430	case IMM1_4:
252b5132 RH	431	imm = nibs[3];
252b5132 RH	432	goto ok;
015551fc JR	433	case IMM0_4BY2:
015551fc JR	434	case IMM1_4BY2:
69eb4bbf	435	imm = nibs[3] << 1;
252b5132	436	goto ok;
015551fc JR	437	case IMM0_4BY4:
015551fc JR	438	case IMM1_4BY4:
69eb4bbf	439	imm = nibs[3] << 2;
252b5132	440	goto ok;
015551fc JR	441	case IMM0_8:
015551fc JR	442	case IMM1_8:
252b5132 RH	443	imm = (nibs[2] << 4) \| nibs[3];
	444	goto ok;
	445	case PCRELIMM_8BY2:
69eb4bbf KH	446	imm = ((nibs[2] << 4) \| nibs[3]) << 1;
69eb4bbf KH	447	relmask = ~(bfd_vma) 1;
252b5132 RH	448	goto ok;
252b5132 RH	449	case PCRELIMM_8BY4:
69eb4bbf KH	450	imm = ((nibs[2] << 4) \| nibs[3]) << 2;
69eb4bbf KH	451	relmask = ~(bfd_vma) 3;
252b5132	452	goto ok;
015551fc JR	453	case IMM0_8BY2:
015551fc JR	454	case IMM1_8BY2:
69eb4bbf	455	imm = ((nibs[2] << 4) \| nibs[3]) << 1;
252b5132	456	goto ok;
015551fc JR	457	case IMM0_8BY4:
015551fc JR	458	case IMM1_8BY4:
69eb4bbf	459	imm = ((nibs[2] << 4) \| nibs[3]) << 2;
252b5132	460	goto ok;
252b5132 RH	461	case REG_N:
	462	rn = nibs[n];
	463	break;
	464	case REG_M:
	465	rm = nibs[n];
	466	break;
	467	case REG_NM:
	468	rn = (nibs[n] & 0xc) >> 2;
	469	rm = (nibs[n] & 0x3);
	470	break;
	471	case REG_B:
	472	rb = nibs[n] & 0x07;
69eb4bbf	473	break;
d4845d57 JR	474	case SDT_REG_N:
	475	/* sh-dsp: single data transfer. */
	476	rn = nibs[n];
	477	if ((rn & 0xc) != 4)
	478	goto fail;
	479	rn = rn & 0x3;
ddb68265	480	rn \|= (!(rn & 2)) << 2;
d4845d57 JR	481	break;
d4845d57 JR	482	case PPI:
015551fc	483	case REPEAT:
d4845d57	484	goto fail;
252b5132	485	default:
69eb4bbf	486	abort ();
252b5132 RH	487	}
	488	}
	489
	490	ok:
69eb4bbf	491	fprintf_fn (stream, "%s\t", op->name);
252b5132	492	disp_pc = 0;
69eb4bbf	493	for (n = 0; n < 3 && op->arg[n] != A_END; n++)
252b5132 RH	494	{
	495	if (n && op->arg[1] != A_END)
	496	fprintf_fn (stream, ",");
69eb4bbf	497	switch (op->arg[n])
252b5132 RH	498	{
252b5132 RH	499	case A_IMM:
69eb4bbf	500	fprintf_fn (stream, "#%d", (char) (imm));
252b5132 RH	501	break;
	502	case A_R0:
	503	fprintf_fn (stream, "r0");
	504	break;
	505	case A_REG_N:
	506	fprintf_fn (stream, "r%d", rn);
	507	break;
	508	case A_INC_N:
69eb4bbf	509	fprintf_fn (stream, "@r%d+", rn);
252b5132 RH	510	break;
252b5132 RH	511	case A_DEC_N:
69eb4bbf	512	fprintf_fn (stream, "@-r%d", rn);
252b5132 RH	513	break;
252b5132 RH	514	case A_IND_N:
69eb4bbf	515	fprintf_fn (stream, "@r%d", rn);
252b5132 RH	516	break;
252b5132 RH	517	case A_DISP_REG_N:
69eb4bbf	518	fprintf_fn (stream, "@(%d,r%d)", imm, rn);
252b5132	519	break;
d4845d57	520	case A_PMOD_N:
69eb4bbf	521	fprintf_fn (stream, "@r%d+r8", rn);
d4845d57	522	break;
252b5132 RH	523	case A_REG_M:
	524	fprintf_fn (stream, "r%d", rm);
	525	break;
	526	case A_INC_M:
69eb4bbf	527	fprintf_fn (stream, "@r%d+", rm);
252b5132 RH	528	break;
252b5132 RH	529	case A_DEC_M:
69eb4bbf	530	fprintf_fn (stream, "@-r%d", rm);
252b5132 RH	531	break;
252b5132 RH	532	case A_IND_M:
69eb4bbf	533	fprintf_fn (stream, "@r%d", rm);
252b5132 RH	534	break;
252b5132 RH	535	case A_DISP_REG_M:
69eb4bbf	536	fprintf_fn (stream, "@(%d,r%d)", imm, rm);
252b5132 RH	537	break;
	538	case A_REG_B:
	539	fprintf_fn (stream, "r%d_bank", rb);
	540	break;
	541	case A_DISP_PC:
	542	disp_pc = 1;
	543	disp_pc_addr = imm + 4 + (memaddr & relmask);
	544	(*info->print_address_func) (disp_pc_addr, info);
	545	break;
	546	case A_IND_R0_REG_N:
	547	fprintf_fn (stream, "@(r0,r%d)", rn);
69eb4bbf	548	break;
252b5132 RH	549	case A_IND_R0_REG_M:
252b5132 RH	550	fprintf_fn (stream, "@(r0,r%d)", rm);
69eb4bbf	551	break;
252b5132	552	case A_DISP_GBR:
69eb4bbf	553	fprintf_fn (stream, "@(%d,gbr)", imm);
252b5132 RH	554	break;
	555	case A_R0_GBR:
	556	fprintf_fn (stream, "@(r0,gbr)");
	557	break;
	558	case A_BDISP12:
	559	case A_BDISP8:
	560	(*info->print_address_func) (imm + memaddr, info);
	561	break;
	562	case A_SR:
	563	fprintf_fn (stream, "sr");
	564	break;
	565	case A_GBR:
	566	fprintf_fn (stream, "gbr");
	567	break;
	568	case A_VBR:
	569	fprintf_fn (stream, "vbr");
	570	break;
d4845d57 JR	571	case A_DSR:
	572	fprintf_fn (stream, "dsr");
	573	break;
	574	case A_MOD:
	575	fprintf_fn (stream, "mod");
	576	break;
	577	case A_RE:
	578	fprintf_fn (stream, "re");
	579	break;
	580	case A_RS:
	581	fprintf_fn (stream, "rs");
	582	break;
	583	case A_A0:
	584	fprintf_fn (stream, "a0");
	585	break;
	586	case A_X0:
	587	fprintf_fn (stream, "x0");
	588	break;
	589	case A_X1:
	590	fprintf_fn (stream, "x1");
	591	break;
	592	case A_Y0:
	593	fprintf_fn (stream, "y0");
	594	break;
	595	case A_Y1:
	596	fprintf_fn (stream, "y1");
	597	break;
	598	case DSP_REG_M:
	599	print_dsp_reg (rm, fprintf_fn, stream);
	600	break;
252b5132 RH	601	case A_SSR:
	602	fprintf_fn (stream, "ssr");
	603	break;
	604	case A_SPC:
	605	fprintf_fn (stream, "spc");
	606	break;
	607	case A_MACH:
	608	fprintf_fn (stream, "mach");
	609	break;
	610	case A_MACL:
69eb4bbf	611	fprintf_fn (stream, "macl");
252b5132 RH	612	break;
	613	case A_PR:
	614	fprintf_fn (stream, "pr");
	615	break;
	616	case A_SGR:
	617	fprintf_fn (stream, "sgr");
	618	break;
	619	case A_DBR:
	620	fprintf_fn (stream, "dbr");
	621	break;
252b5132 RH	622	case F_REG_N:
	623	fprintf_fn (stream, "fr%d", rn);
	624	break;
	625	case F_REG_M:
	626	fprintf_fn (stream, "fr%d", rm);
	627	break;
	628	case DX_REG_N:
	629	if (rn & 1)
	630	{
	631	fprintf_fn (stream, "xd%d", rn & ~1);
	632	break;
	633	}
252b5132 RH	634	case D_REG_N:
	635	fprintf_fn (stream, "dr%d", rn);
	636	break;
	637	case DX_REG_M:
	638	if (rm & 1)
	639	{
	640	fprintf_fn (stream, "xd%d", rm & ~1);
	641	break;
	642	}
	643	case D_REG_M:
	644	fprintf_fn (stream, "dr%d", rm);
	645	break;
	646	case FPSCR_M:
	647	case FPSCR_N:
	648	fprintf_fn (stream, "fpscr");
	649	break;
	650	case FPUL_M:
	651	case FPUL_N:
	652	fprintf_fn (stream, "fpul");
	653	break;
	654	case F_FR0:
	655	fprintf_fn (stream, "fr0");
	656	break;
	657	case V_REG_N:
69eb4bbf	658	fprintf_fn (stream, "fv%d", rn * 4);
252b5132 RH	659	break;
252b5132 RH	660	case V_REG_M:
69eb4bbf	661	fprintf_fn (stream, "fv%d", rm * 4);
252b5132 RH	662	break;
	663	case XMTRX_M4:
	664	fprintf_fn (stream, "xmtrx");
	665	break;
	666	default:
69eb4bbf	667	abort ();
252b5132 RH	668	}
	669	}
	670
	671	#if 0
	672	/* This code prints instructions in delay slots on the same line
	673	as the instruction which needs the delay slots. This can be
	674	confusing, since other disassembler don't work this way, and
	675	it means that the instructions are not all in a line. So I
	676	disabled it. Ian. */
	677	if (!(info->flags & 1)
	678	&& (op->name[0] == 'j'
	679	\|\| (op->name[0] == 'b'
69eb4bbf	680	&& (op->name[1] == 'r'
252b5132 RH	681	\|\| op->name[1] == 's'))
	682	\|\| (op->name[0] == 'r' && op->name[1] == 't')
	683	\|\| (op->name[0] == 'b' && op->name[2] == '.')))
	684	{
	685	info->flags \|= 1;
	686	fprintf_fn (stream, "\t(slot ");
1c509ca8	687	print_insn_sh (memaddr + 2, info);
252b5132 RH	688	info->flags &= ~1;
	689	fprintf_fn (stream, ")");
	690	return 4;
	691	}
	692	#endif
	693
	694	if (disp_pc && strcmp (op->name, "mova") != 0)
	695	{
	696	int size;
	697	bfd_byte bytes[4];
	698
69eb4bbf	699	if (relmask == ~(bfd_vma) 1)
252b5132 RH	700	size = 2;
	701	else
	702	size = 4;
	703	status = info->read_memory_func (disp_pc_addr, bytes, size, info);
	704	if (status == 0)
	705	{
	706	unsigned int val;
	707
	708	if (size == 2)
	709	{
1c509ca8	710	if (info->endian == BFD_ENDIAN_LITTLE)
252b5132 RH	711	val = bfd_getl16 (bytes);
	712	else
	713	val = bfd_getb16 (bytes);
	714	}
	715	else
	716	{
1c509ca8	717	if (info->endian == BFD_ENDIAN_LITTLE)
252b5132 RH	718	val = bfd_getl32 (bytes);
	719	else
	720	val = bfd_getb32 (bytes);
	721	}
	722	fprintf_fn (stream, "\t! 0x%x", val);
	723	}
	724	}
	725
	726	return 2;
	727	fail:
	728	;
	729
	730	}
	731	fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
	732	return 2;
	733	}