[deliverable/binutils-gdb.git] / opcodes / sh-dis.c

/* Disassemble SH instructions.
   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002
   Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <stdio.h>
#include "sysdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE

#include "sh-opc.h"
#include "dis-asm.h"

#ifdef ARCH_all
#define INCLUDE_SHMEDIA
#endif

static void print_movxy
  PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *));
static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
static void print_insn_ppi PARAMS ((int, struct disassemble_info *));

static void
print_movxy (op, rn, rm, fprintf_fn, stream)
     const sh_opcode_info *op;
     int rn, rm;
     fprintf_ftype fprintf_fn;
     void *stream;
{
  int n;

  fprintf_fn (stream, "%s\t", op->name);
  for (n = 0; n < 2; n++)
    {
      switch (op->arg[n])
	{
	case A_IND_N:
	  fprintf_fn (stream, "@r%d", rn);
	  break;
	case A_INC_N:
	  fprintf_fn (stream, "@r%d+", rn);
	  break;
	case A_PMOD_N:
	  fprintf_fn (stream, "@r%d+r8", rn);
	  break;
	case A_PMODY_N:
	  fprintf_fn (stream, "@r%d+r9", rn);
	  break;
	case DSP_REG_M:
	  fprintf_fn (stream, "a%c", '0' + rm);
	  break;
	case DSP_REG_X:
	  fprintf_fn (stream, "x%c", '0' + rm);
	  break;
	case DSP_REG_Y:
	  fprintf_fn (stream, "y%c", '0' + rm);
	  break;
	default:
	  abort ();
	}
      if (n == 0)
	fprintf_fn (stream, ",");
    }
}

/* Print a double data transfer insn.  INSN is just the lower three
   nibbles of the insn, i.e. field a and the bit that indicates if
   a parallel processing insn follows.
   Return nonzero if a field b of a parallel processing insns follows.  */

static void
print_insn_ddt (insn, info)
     int insn;
     struct disassemble_info *info;
{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;

  /* If this is just a nop, make sure to emit something.  */
  if (insn == 0x000)
    fprintf_fn (stream, "nopx\tnopy");

  /* If a parallel processing insn was printed before,
     and we got a non-nop, emit a tab.  */
  if ((insn & 0x800) && (insn & 0x3ff))
    fprintf_fn (stream, "\t");

  /* Check if either the x or y part is invalid.  */
  if (((insn & 0xc) == 0 && (insn & 0x2a0))
      || ((insn & 3) == 0 && (insn & 0x150)))
    fprintf_fn (stream, ".word 0x%x", insn);
  else
    {
      static const sh_opcode_info *first_movx, *first_movy;
      const sh_opcode_info *opx, *opy;
      unsigned int insn_x, insn_y;

      if (! first_movx)
	{
	  for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
	    first_movx++;
	  for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
	    first_movy++;
	}
      insn_x = (insn >> 2) & 0xb;
      if (insn_x)
	{
	  for (opx = first_movx; opx->nibbles[2] != insn_x;)
	    opx++;
	  print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
		       fprintf_fn, stream);
	}
      insn_y = (insn & 3) | ((insn >> 1) & 8);
      if (insn_y)
	{
	  if (insn_x)
	    fprintf_fn (stream, "\t");
	  for (opy = first_movy; opy->nibbles[2] != insn_y;)
	    opy++;
	  print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
		       fprintf_fn, stream);
	}
    }
}

static void
print_dsp_reg (rm, fprintf_fn, stream)
     int rm;
     fprintf_ftype fprintf_fn;
     void *stream;
{
  switch (rm)
    {
    case A_A1_NUM:
      fprintf_fn (stream, "a1");
      break;
    case A_A0_NUM:
      fprintf_fn (stream, "a0");
      break;
    case A_X0_NUM:
      fprintf_fn (stream, "x0");
      break;
    case A_X1_NUM:
      fprintf_fn (stream, "x1");
      break;
    case A_Y0_NUM:
      fprintf_fn (stream, "y0");
      break;
    case A_Y1_NUM:
      fprintf_fn (stream, "y1");
      break;
    case A_M0_NUM:
      fprintf_fn (stream, "m0");
      break;
    case A_A1G_NUM:
      fprintf_fn (stream, "a1g");
      break;
    case A_M1_NUM:
      fprintf_fn (stream, "m1");
      break;
    case A_A0G_NUM:
      fprintf_fn (stream, "a0g");
      break;
    default:
      fprintf_fn (stream, "0x%x", rm);
      break;
    }
}

static void
print_insn_ppi (field_b, info)
     int field_b;
     struct disassemble_info *info;
{
  static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
  static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  unsigned int nib1, nib2, nib3;
  char *dc = NULL;
  const sh_opcode_info *op;

  if ((field_b & 0xe800) == 0)
    {
      fprintf_fn (stream, "psh%c\t#%d,",
		  field_b & 0x1000 ? 'a' : 'l',
		  (field_b >> 4) & 127);
      print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
      return;
    }
  if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
    {
      static char *du_tab[] = { "x0", "y0", "a0", "a1" };
      static char *se_tab[] = { "x0", "x1", "y0", "a1" };
      static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
      static char *sg_tab[] = { "m0", "m1", "a0", "a1" };

      if (field_b & 0x2000)
	{
	  fprintf_fn (stream, "p%s %s,%s,%s\t",
		      (field_b & 0x1000) ? "add" : "sub",
		      sx_tab[(field_b >> 6) & 3],
		      sy_tab[(field_b >> 4) & 3],
		      du_tab[(field_b >> 0) & 3]);
	}
      fprintf_fn (stream, "pmuls%c%s,%s,%s",
		  field_b & 0x2000 ? ' ' : '\t',
		  se_tab[(field_b >> 10) & 3],
		  sf_tab[(field_b >>  8) & 3],
		  sg_tab[(field_b >>  2) & 3]);
      return;
    }

  nib1 = PPIC;
  nib2 = field_b >> 12 & 0xf;
  nib3 = field_b >> 8 & 0xf;
  switch (nib3 & 0x3)
    {
    case 0:
      dc = "";
      nib1 = PPI3;
      break;
    case 1:
      dc = "";
      break;
    case 2:
      dc = "dct ";
      nib3 -= 1;
      break;
    case 3:
      dc = "dcf ";
      nib3 -= 2;
      break;
    }
  for (op = sh_table; op->name; op++)
    {
      if (op->nibbles[1] == nib1
	  && op->nibbles[2] == nib2
	  && op->nibbles[3] == nib3)
	{
	  int n;

	  fprintf_fn (stream, "%s%s\t", dc, op->name);
	  for (n = 0; n < 3 && op->arg[n] != A_END; n++)
	    {
	      if (n && op->arg[1] != A_END)
		fprintf_fn (stream, ",");
	      switch (op->arg[n])
		{
		case DSP_REG_N:
		  print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
		  break;
		case DSP_REG_X:
		  fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
		  break;
		case DSP_REG_Y:
		  fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
		  break;
		case A_MACH:
		  fprintf_fn (stream, "mach");
		  break;
		case A_MACL:
		  fprintf_fn (stream, "macl");
		  break;
		default:
		  abort ();
		}
	    }
	  return;
	}
    }
  /* Not found.  */
  fprintf_fn (stream, ".word 0x%x", field_b);
}

int
print_insn_sh (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  unsigned char insn[2];
  unsigned char nibs[4];
  int status;
  bfd_vma relmask = ~(bfd_vma) 0;
  const sh_opcode_info *op;
  int target_arch;

  switch (info->mach)
    {
    case bfd_mach_sh:
      target_arch = arch_sh1;
      /* SH coff object files lack information about the machine type, so
         we end up with bfd_mach_sh unless it was set explicitly (which
	 could have happended if this is a call from gdb or the simulator.)  */
      if (info->symbols
	  && bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour)
	target_arch = arch_sh4;
      break;
    case bfd_mach_sh2:
      target_arch = arch_sh2;
      break;
    case bfd_mach_sh_dsp:
      target_arch = arch_sh_dsp;
      break;
    case bfd_mach_sh3:
      target_arch = arch_sh3;
      break;
    case bfd_mach_sh3_dsp:
      target_arch = arch_sh3_dsp;
      break;
    case bfd_mach_sh3e:
      target_arch = arch_sh3e;
      break;
    case bfd_mach_sh4:
      target_arch = arch_sh4;
      break;
    case bfd_mach_sh5:
#ifdef INCLUDE_SHMEDIA
      status = print_insn_sh64 (memaddr, info);
      if (status != -2)
	return status;
#endif
      /* When we get here for sh64, it's because we want to disassemble
	 SHcompact, i.e. arch_sh4.  */
      target_arch = arch_sh4;
      break;
    default:
      abort ();
    }

  status = info->read_memory_func (memaddr, insn, 2, info);

  if (status != 0)
    {
      info->memory_error_func (status, memaddr, info);
      return -1;
    }

  if (info->endian == BFD_ENDIAN_LITTLE)
    {
      nibs[0] = (insn[1] >> 4) & 0xf;
      nibs[1] = insn[1] & 0xf;

      nibs[2] = (insn[0] >> 4) & 0xf;
      nibs[3] = insn[0] & 0xf;
    }
  else
    {
      nibs[0] = (insn[0] >> 4) & 0xf;
      nibs[1] = insn[0] & 0xf;

      nibs[2] = (insn[1] >> 4) & 0xf;
      nibs[3] = insn[1] & 0xf;
    }

  if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up)
    {
      if (nibs[1] & 8)
	{
	  int field_b;

	  status = info->read_memory_func (memaddr + 2, insn, 2, info);

	  if (status != 0)
	    {
	      info->memory_error_func (status, memaddr + 2, info);
	      return -1;
	    }

	  if (info->endian == BFD_ENDIAN_LITTLE)
	    field_b = insn[1] << 8 | insn[0];
	  else
	    field_b = insn[0] << 8 | insn[1];

	  print_insn_ppi (field_b, info);
	  print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
	  return 4;
	}
      print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
      return 2;
    }
  for (op = sh_table; op->name; op++)
    {
      int n;
      int imm = 0;
      int rn = 0;
      int rm = 0;
      int rb = 0;
      int disp_pc;
      bfd_vma disp_pc_addr = 0;

      if ((op->arch & target_arch) == 0)
	goto fail;
      for (n = 0; n < 4; n++)
	{
	  int i = op->nibbles[n];

	  if (i < 16)
	    {
	      if (nibs[n] == i)
		continue;
	      goto fail;
	    }
	  switch (i)
	    {
	    case BRANCH_8:
	      imm = (nibs[2] << 4) | (nibs[3]);
	      if (imm & 0x80)
		imm |= ~0xff;
	      imm = ((char) imm) * 2 + 4;
	      goto ok;
	    case BRANCH_12:
	      imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
	      if (imm & 0x800)
		imm |= ~0xfff;
	      imm = imm * 2 + 4;
	      goto ok;
	    case IMM0_4:
	    case IMM1_4:
	      imm = nibs[3];
	      goto ok;
	    case IMM0_4BY2:
	    case IMM1_4BY2:
	      imm = nibs[3] << 1;
	      goto ok;
	    case IMM0_4BY4:
	    case IMM1_4BY4:
	      imm = nibs[3] << 2;
	      goto ok;
	    case IMM0_8:
	    case IMM1_8:
	      imm = (nibs[2] << 4) | nibs[3];
	      goto ok;
	    case PCRELIMM_8BY2:
	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
	      relmask = ~(bfd_vma) 1;
	      goto ok;
	    case PCRELIMM_8BY4:
	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
	      relmask = ~(bfd_vma) 3;
	      goto ok;
	    case IMM0_8BY2:
	    case IMM1_8BY2:
	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
	      goto ok;
	    case IMM0_8BY4:
	    case IMM1_8BY4:
	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
	      goto ok;
	    case REG_N:
	      rn = nibs[n];
	      break;
	    case REG_M:
	      rm = nibs[n];
	      break;
	    case REG_NM:
	      rn = (nibs[n] & 0xc) >> 2;
	      rm = (nibs[n] & 0x3);
	      break;
	    case REG_B:
	      rb = nibs[n] & 0x07;
	      break;
	    case SDT_REG_N:
	      /* sh-dsp: single data transfer.  */
	      rn = nibs[n];
	      if ((rn & 0xc) != 4)
		goto fail;
	      rn = rn & 0x3;
	      rn |= (!(rn & 2)) << 2;
	      break;
	    case PPI:
	    case REPEAT:
	      goto fail;
	    default:
	      abort ();
	    }
	}

    ok:
      fprintf_fn (stream, "%s\t", op->name);
      disp_pc = 0;
      for (n = 0; n < 3 && op->arg[n] != A_END; n++)
	{
	  if (n && op->arg[1] != A_END)
	    fprintf_fn (stream, ",");
	  switch (op->arg[n])
	    {
	    case A_IMM:
	      fprintf_fn (stream, "#%d", (char) (imm));
	      break;
	    case A_R0:
	      fprintf_fn (stream, "r0");
	      break;
	    case A_REG_N:
	      fprintf_fn (stream, "r%d", rn);
	      break;
	    case A_INC_N:
	      fprintf_fn (stream, "@r%d+", rn);
	      break;
	    case A_DEC_N:
	      fprintf_fn (stream, "@-r%d", rn);
	      break;
	    case A_IND_N:
	      fprintf_fn (stream, "@r%d", rn);
	      break;
	    case A_DISP_REG_N:
	      fprintf_fn (stream, "@(%d,r%d)", imm, rn);
	      break;
	    case A_PMOD_N:
	      fprintf_fn (stream, "@r%d+r8", rn);
	      break;
	    case A_REG_M:
	      fprintf_fn (stream, "r%d", rm);
	      break;
	    case A_INC_M:
	      fprintf_fn (stream, "@r%d+", rm);
	      break;
	    case A_DEC_M:
	      fprintf_fn (stream, "@-r%d", rm);
	      break;
	    case A_IND_M:
	      fprintf_fn (stream, "@r%d", rm);
	      break;
	    case A_DISP_REG_M:
	      fprintf_fn (stream, "@(%d,r%d)", imm, rm);
	      break;
	    case A_REG_B:
	      fprintf_fn (stream, "r%d_bank", rb);
	      break;
	    case A_DISP_PC:
	      disp_pc = 1;
	      disp_pc_addr = imm + 4 + (memaddr & relmask);
	      (*info->print_address_func) (disp_pc_addr, info);
	      break;
	    case A_IND_R0_REG_N:
	      fprintf_fn (stream, "@(r0,r%d)", rn);
	      break;
	    case A_IND_R0_REG_M:
	      fprintf_fn (stream, "@(r0,r%d)", rm);
	      break;
	    case A_DISP_GBR:
	      fprintf_fn (stream, "@(%d,gbr)", imm);
	      break;
	    case A_R0_GBR:
	      fprintf_fn (stream, "@(r0,gbr)");
	      break;
	    case A_BDISP12:
	    case A_BDISP8:
	      (*info->print_address_func) (imm + memaddr, info);
	      break;
	    case A_SR:
	      fprintf_fn (stream, "sr");
	      break;
	    case A_GBR:
	      fprintf_fn (stream, "gbr");
	      break;
	    case A_VBR:
	      fprintf_fn (stream, "vbr");
	      break;
	    case A_DSR:
	      fprintf_fn (stream, "dsr");
	      break;
	    case A_MOD:
	      fprintf_fn (stream, "mod");
	      break;
	    case A_RE:
	      fprintf_fn (stream, "re");
	      break;
	    case A_RS:
	      fprintf_fn (stream, "rs");
	      break;
	    case A_A0:
	      fprintf_fn (stream, "a0");
	      break;
	    case A_X0:
	      fprintf_fn (stream, "x0");
	      break;
	    case A_X1:
	      fprintf_fn (stream, "x1");
	      break;
	    case A_Y0:
	      fprintf_fn (stream, "y0");
	      break;
	    case A_Y1:
	      fprintf_fn (stream, "y1");
	      break;
	    case DSP_REG_M:
	      print_dsp_reg (rm, fprintf_fn, stream);
	      break;
	    case A_SSR:
	      fprintf_fn (stream, "ssr");
	      break;
	    case A_SPC:
	      fprintf_fn (stream, "spc");
	      break;
	    case A_MACH:
	      fprintf_fn (stream, "mach");
	      break;
	    case A_MACL:
	      fprintf_fn (stream, "macl");
	      break;
	    case A_PR:
	      fprintf_fn (stream, "pr");
	      break;
	    case A_SGR:
	      fprintf_fn (stream, "sgr");
	      break;
	    case A_DBR:
	      fprintf_fn (stream, "dbr");
	      break;
	    case F_REG_N:
	      fprintf_fn (stream, "fr%d", rn);
	      break;
	    case F_REG_M:
	      fprintf_fn (stream, "fr%d", rm);
	      break;
	    case DX_REG_N:
	      if (rn & 1)
		{
		  fprintf_fn (stream, "xd%d", rn & ~1);
		  break;
		}
	    case D_REG_N:
	      fprintf_fn (stream, "dr%d", rn);
	      break;
	    case DX_REG_M:
	      if (rm & 1)
		{
		  fprintf_fn (stream, "xd%d", rm & ~1);
		  break;
		}
	    case D_REG_M:
	      fprintf_fn (stream, "dr%d", rm);
	      break;
	    case FPSCR_M:
	    case FPSCR_N:
	      fprintf_fn (stream, "fpscr");
	      break;
	    case FPUL_M:
	    case FPUL_N:
	      fprintf_fn (stream, "fpul");
	      break;
	    case F_FR0:
	      fprintf_fn (stream, "fr0");
	      break;
	    case V_REG_N:
	      fprintf_fn (stream, "fv%d", rn * 4);
	      break;
	    case V_REG_M:
	      fprintf_fn (stream, "fv%d", rm * 4);
	      break;
	    case XMTRX_M4:
	      fprintf_fn (stream, "xmtrx");
	      break;
	    default:
	      abort ();
	    }
	}

#if 0
      /* This code prints instructions in delay slots on the same line
         as the instruction which needs the delay slots.  This can be
         confusing, since other disassembler don't work this way, and
         it means that the instructions are not all in a line.  So I
         disabled it.  Ian.  */
      if (!(info->flags & 1)
	  && (op->name[0] == 'j'
	      || (op->name[0] == 'b'
		  && (op->name[1] == 'r'
		      || op->name[1] == 's'))
	      || (op->name[0] == 'r' && op->name[1] == 't')
	      || (op->name[0] == 'b' && op->name[2] == '.')))
	{
	  info->flags |= 1;
	  fprintf_fn (stream, "\t(slot ");
	  print_insn_sh (memaddr + 2, info);
	  info->flags &= ~1;
	  fprintf_fn (stream, ")");
	  return 4;
	}
#endif

      if (disp_pc && strcmp (op->name, "mova") != 0)
	{
	  int size;
	  bfd_byte bytes[4];

	  if (relmask == ~(bfd_vma) 1)
	    size = 2;
	  else
	    size = 4;
	  status = info->read_memory_func (disp_pc_addr, bytes, size, info);
	  if (status == 0)
	    {
	      unsigned int val;

	      if (size == 2)
		{
		  if (info->endian == BFD_ENDIAN_LITTLE)
		    val = bfd_getl16 (bytes);
		  else
		    val = bfd_getb16 (bytes);
		}
	      else
		{
		  if (info->endian == BFD_ENDIAN_LITTLE)
		    val = bfd_getl32 (bytes);
		  else
		    val = bfd_getb32 (bytes);
		}
	      fprintf_fn (stream, "\t! 0x%x", val);
	    }
	}

      return 2;
    fail:
      ;

    }
  fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
  return 2;
}
Commit	Line	Data
252b5132	1	/* Disassemble SH instructions.
b34976b6	2	Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002
69eb4bbf	3	Free Software Foundation, Inc.
252b5132 RH	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	18
	19	#include <stdio.h>
0d8dfecf	20	#include "sysdep.h"
252b5132 RH	21	#define STATIC_TABLE
	22	#define DEFINE_TABLE
	23
	24	#include "sh-opc.h"
	25	#include "dis-asm.h"
	26
b34976b6 AM	27	#ifdef ARCH_all
	28	#define INCLUDE_SHMEDIA
	29	#endif
	30
d83c6548	31	static void print_movxy
6a51a8a8	32	PARAMS ((const sh_opcode_info , int, int, fprintf_ftype, void ));
d83c6548 AJ	33	static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
	34	static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
	35	static void print_insn_ppi PARAMS ((int, struct disassemble_info *));
d83c6548	36
d4845d57 JR	37	static void
d4845d57 JR	38	print_movxy (op, rn, rm, fprintf_fn, stream)
6a51a8a8	39	const sh_opcode_info *op;
d4845d57 JR	40	int rn, rm;
	41	fprintf_ftype fprintf_fn;
	42	void *stream;
	43	{
	44	int n;
	45
69eb4bbf	46	fprintf_fn (stream, "%s\t", op->name);
d4845d57 JR	47	for (n = 0; n < 2; n++)
	48	{
	49	switch (op->arg[n])
	50	{
	51	case A_IND_N:
69eb4bbf	52	fprintf_fn (stream, "@r%d", rn);
d4845d57 JR	53	break;
d4845d57 JR	54	case A_INC_N:
69eb4bbf	55	fprintf_fn (stream, "@r%d+", rn);
d4845d57 JR	56	break;
d4845d57 JR	57	case A_PMOD_N:
69eb4bbf	58	fprintf_fn (stream, "@r%d+r8", rn);
d4845d57 JR	59	break;
d4845d57 JR	60	case A_PMODY_N:
69eb4bbf	61	fprintf_fn (stream, "@r%d+r9", rn);
d4845d57 JR	62	break;
	63	case DSP_REG_M:
	64	fprintf_fn (stream, "a%c", '0' + rm);
	65	break;
	66	case DSP_REG_X:
	67	fprintf_fn (stream, "x%c", '0' + rm);
	68	break;
	69	case DSP_REG_Y:
	70	fprintf_fn (stream, "y%c", '0' + rm);
	71	break;
	72	default:
	73	abort ();
	74	}
	75	if (n == 0)
69eb4bbf	76	fprintf_fn (stream, ",");
d4845d57 JR	77	}
	78	}
	79
	80	/* Print a double data transfer insn. INSN is just the lower three
	81	nibbles of the insn, i.e. field a and the bit that indicates if
	82	a parallel processing insn follows.
	83	Return nonzero if a field b of a parallel processing insns follows. */
69eb4bbf	84
d4845d57 JR	85	static void
	86	print_insn_ddt (insn, info)
	87	int insn;
	88	struct disassemble_info *info;
	89	{
	90	fprintf_ftype fprintf_fn = info->fprintf_func;
	91	void *stream = info->stream;
	92
	93	/* If this is just a nop, make sure to emit something. */
	94	if (insn == 0x000)
	95	fprintf_fn (stream, "nopx\tnopy");
	96
	97	/* If a parallel processing insn was printed before,
	98	and we got a non-nop, emit a tab. */
	99	if ((insn & 0x800) && (insn & 0x3ff))
	100	fprintf_fn (stream, "\t");
	101
	102	/* Check if either the x or y part is invalid. */
	103	if (((insn & 0xc) == 0 && (insn & 0x2a0))
	104	\|\| ((insn & 3) == 0 && (insn & 0x150)))
	105	fprintf_fn (stream, ".word 0x%x", insn);
	106	else
	107	{
6a51a8a8 AM	108	static const sh_opcode_info first_movx, first_movy;
6a51a8a8 AM	109	const sh_opcode_info opx, opy;
caaaf822	110	unsigned int insn_x, insn_y;
d4845d57 JR	111
	112	if (! first_movx)
	113	{
69eb4bbf	114	for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
d4845d57	115	first_movx++;
69eb4bbf	116	for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
d4845d57 JR	117	first_movy++;
	118	}
	119	insn_x = (insn >> 2) & 0xb;
	120	if (insn_x)
	121	{
69eb4bbf KH	122	for (opx = first_movx; opx->nibbles[2] != insn_x;)
69eb4bbf KH	123	opx++;
d4845d57 JR	124	print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
	125	fprintf_fn, stream);
	126	}
	127	insn_y = (insn & 3) \| ((insn >> 1) & 8);
	128	if (insn_y)
	129	{
	130	if (insn_x)
	131	fprintf_fn (stream, "\t");
69eb4bbf KH	132	for (opy = first_movy; opy->nibbles[2] != insn_y;)
69eb4bbf KH	133	opy++;
d4845d57 JR	134	print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
	135	fprintf_fn, stream);
	136	}
	137	}
	138	}
	139
	140	static void
	141	print_dsp_reg (rm, fprintf_fn, stream)
	142	int rm;
	143	fprintf_ftype fprintf_fn;
	144	void *stream;
	145	{
	146	switch (rm)
	147	{
	148	case A_A1_NUM:
	149	fprintf_fn (stream, "a1");
	150	break;
	151	case A_A0_NUM:
	152	fprintf_fn (stream, "a0");
	153	break;
	154	case A_X0_NUM:
	155	fprintf_fn (stream, "x0");
	156	break;
	157	case A_X1_NUM:
	158	fprintf_fn (stream, "x1");
	159	break;
	160	case A_Y0_NUM:
	161	fprintf_fn (stream, "y0");
	162	break;
	163	case A_Y1_NUM:
	164	fprintf_fn (stream, "y1");
	165	break;
	166	case A_M0_NUM:
	167	fprintf_fn (stream, "m0");
	168	break;
	169	case A_A1G_NUM:
	170	fprintf_fn (stream, "a1g");
	171	break;
	172	case A_M1_NUM:
	173	fprintf_fn (stream, "m1");
	174	break;
	175	case A_A0G_NUM:
	176	fprintf_fn (stream, "a0g");
	177	break;
	178	default:
	179	fprintf_fn (stream, "0x%x", rm);
	180	break;
	181	}
	182	}
	183
	184	static void
	185	print_insn_ppi (field_b, info)
	186	int field_b;
	187	struct disassemble_info *info;
	188	{
69eb4bbf KH	189	static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
69eb4bbf KH	190	static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
d4845d57 JR	191	fprintf_ftype fprintf_fn = info->fprintf_func;
d4845d57 JR	192	void *stream = info->stream;
caaaf822 HPN	193	unsigned int nib1, nib2, nib3;
caaaf822 HPN	194	char *dc = NULL;
6a51a8a8	195	const sh_opcode_info *op;
d4845d57 JR	196
	197	if ((field_b & 0xe800) == 0)
	198	{
	199	fprintf_fn (stream, "psh%c\t#%d,",
	200	field_b & 0x1000 ? 'a' : 'l',
	201	(field_b >> 4) & 127);
	202	print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
	203	return;
	204	}
	205	if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
	206	{
69eb4bbf KH	207	static char *du_tab[] = { "x0", "y0", "a0", "a1" };
	208	static char *se_tab[] = { "x0", "x1", "y0", "a1" };
	209	static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
	210	static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
d4845d57 JR	211
	212	if (field_b & 0x2000)
	213	{
	214	fprintf_fn (stream, "p%s %s,%s,%s\t",
	215	(field_b & 0x1000) ? "add" : "sub",
	216	sx_tab[(field_b >> 6) & 3],
	217	sy_tab[(field_b >> 4) & 3],
	218	du_tab[(field_b >> 0) & 3]);
	219	}
	220	fprintf_fn (stream, "pmuls%c%s,%s,%s",
	221	field_b & 0x2000 ? ' ' : '\t',
	222	se_tab[(field_b >> 10) & 3],
	223	sf_tab[(field_b >> 8) & 3],
	224	sg_tab[(field_b >> 2) & 3]);
	225	return;
	226	}
	227
	228	nib1 = PPIC;
	229	nib2 = field_b >> 12 & 0xf;
	230	nib3 = field_b >> 8 & 0xf;
	231	switch (nib3 & 0x3)
	232	{
	233	case 0:
	234	dc = "";
	235	nib1 = PPI3;
	236	break;
	237	case 1:
	238	dc = "";
	239	break;
	240	case 2:
	241	dc = "dct ";
	242	nib3 -= 1;
	243	break;
	244	case 3:
	245	dc = "dcf ";
	246	nib3 -= 2;
	247	break;
	248	}
	249	for (op = sh_table; op->name; op++)
	250	{
	251	if (op->nibbles[1] == nib1
	252	&& op->nibbles[2] == nib2
	253	&& op->nibbles[3] == nib3)
	254	{
	255	int n;
	256
	257	fprintf_fn (stream, "%s%s\t", dc, op->name);
69eb4bbf	258	for (n = 0; n < 3 && op->arg[n] != A_END; n++)
d4845d57 JR	259	{
	260	if (n && op->arg[1] != A_END)
	261	fprintf_fn (stream, ",");
69eb4bbf	262	switch (op->arg[n])
d4845d57 JR	263	{
	264	case DSP_REG_N:
	265	print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
	266	break;
	267	case DSP_REG_X:
	268	fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
	269	break;
	270	case DSP_REG_Y:
	271	fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
	272	break;
	273	case A_MACH:
	274	fprintf_fn (stream, "mach");
	275	break;
	276	case A_MACL:
69eb4bbf	277	fprintf_fn (stream, "macl");
d4845d57 JR	278	break;
	279	default:
	280	abort ();
	281	}
	282	}
	283	return;
	284	}
	285	}
	286	/* Not found. */
	287	fprintf_fn (stream, ".word 0x%x", field_b);
	288	}
	289
1c509ca8 JR	290	int
1c509ca8 JR	291	print_insn_sh (memaddr, info)
252b5132 RH	292	bfd_vma memaddr;
	293	struct disassemble_info *info;
	294	{
	295	fprintf_ftype fprintf_fn = info->fprintf_func;
	296	void *stream = info->stream;
	297	unsigned char insn[2];
	298	unsigned char nibs[4];
	299	int status;
69eb4bbf	300	bfd_vma relmask = ~(bfd_vma) 0;
6a51a8a8	301	const sh_opcode_info *op;
d4845d57 JR	302	int target_arch;
	303
	304	switch (info->mach)
	305	{
	306	case bfd_mach_sh:
	307	target_arch = arch_sh1;
426e6456 JR	308	/* SH coff object files lack information about the machine type, so
	309	we end up with bfd_mach_sh unless it was set explicitly (which
	310	could have happended if this is a call from gdb or the simulator.) */
4ee33023 JR	311	if (info->symbols
4ee33023 JR	312	&& bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour)
426e6456	313	target_arch = arch_sh4;
d4845d57 JR	314	break;
	315	case bfd_mach_sh2:
	316	target_arch = arch_sh2;
	317	break;
	318	case bfd_mach_sh_dsp:
	319	target_arch = arch_sh_dsp;
	320	break;
	321	case bfd_mach_sh3:
	322	target_arch = arch_sh3;
	323	break;
	324	case bfd_mach_sh3_dsp:
	325	target_arch = arch_sh3_dsp;
	326	break;
	327	case bfd_mach_sh3e:
	328	target_arch = arch_sh3e;
	329	break;
	330	case bfd_mach_sh4:
	331	target_arch = arch_sh4;
	332	break;
d28847ce	333	case bfd_mach_sh5:
1c509ca8 JR	334	#ifdef INCLUDE_SHMEDIA
	335	status = print_insn_sh64 (memaddr, info);
	336	if (status != -2)
	337	return status;
	338	#endif
d28847ce AO	339	/* When we get here for sh64, it's because we want to disassemble
	340	SHcompact, i.e. arch_sh4. */
	341	target_arch = arch_sh4;
	342	break;
d4845d57 JR	343	default:
	344	abort ();
	345	}
252b5132 RH	346
	347	status = info->read_memory_func (memaddr, insn, 2, info);
	348
69eb4bbf	349	if (status != 0)
252b5132 RH	350	{
	351	info->memory_error_func (status, memaddr, info);
	352	return -1;
	353	}
	354
1c509ca8	355	if (info->endian == BFD_ENDIAN_LITTLE)
252b5132 RH	356	{
	357	nibs[0] = (insn[1] >> 4) & 0xf;
	358	nibs[1] = insn[1] & 0xf;
	359
	360	nibs[2] = (insn[0] >> 4) & 0xf;
	361	nibs[3] = insn[0] & 0xf;
	362	}
69eb4bbf	363	else
252b5132 RH	364	{
	365	nibs[0] = (insn[0] >> 4) & 0xf;
	366	nibs[1] = insn[0] & 0xf;
	367
	368	nibs[2] = (insn[1] >> 4) & 0xf;
	369	nibs[3] = insn[1] & 0xf;
	370	}
	371
d4845d57 JR	372	if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up)
	373	{
	374	if (nibs[1] & 8)
	375	{
	376	int field_b;
	377
	378	status = info->read_memory_func (memaddr + 2, insn, 2, info);
	379
69eb4bbf	380	if (status != 0)
d4845d57 JR	381	{
	382	info->memory_error_func (status, memaddr + 2, info);
	383	return -1;
	384	}
	385
1c509ca8	386	if (info->endian == BFD_ENDIAN_LITTLE)
d4845d57 JR	387	field_b = insn[1] << 8 \| insn[0];
	388	else
	389	field_b = insn[0] << 8 \| insn[1];
	390
	391	print_insn_ppi (field_b, info);
	392	print_insn_ddt ((nibs[1] << 8) \| (nibs[2] << 4) \| nibs[3], info);
	393	return 4;
	394	}
	395	print_insn_ddt ((nibs[1] << 8) \| (nibs[2] << 4) \| nibs[3], info);
	396	return 2;
	397	}
69eb4bbf	398	for (op = sh_table; op->name; op++)
252b5132 RH	399	{
	400	int n;
	401	int imm = 0;
	402	int rn = 0;
	403	int rm = 0;
	404	int rb = 0;
	405	int disp_pc;
	406	bfd_vma disp_pc_addr = 0;
	407
d4845d57 JR	408	if ((op->arch & target_arch) == 0)
d4845d57 JR	409	goto fail;
252b5132 RH	410	for (n = 0; n < 4; n++)
	411	{
	412	int i = op->nibbles[n];
	413
69eb4bbf	414	if (i < 16)
252b5132 RH	415	{
	416	if (nibs[n] == i)
	417	continue;
	418	goto fail;
	419	}
	420	switch (i)
	421	{
	422	case BRANCH_8:
69eb4bbf	423	imm = (nibs[2] << 4) \| (nibs[3]);
252b5132 RH	424	if (imm & 0x80)
252b5132 RH	425	imm \|= ~0xff;
69eb4bbf	426	imm = ((char) imm) * 2 + 4;
252b5132 RH	427	goto ok;
	428	case BRANCH_12:
	429	imm = ((nibs[1]) << 8) \| (nibs[2] << 4) \| (nibs[3]);
	430	if (imm & 0x800)
	431	imm \|= ~0xfff;
	432	imm = imm * 2 + 4;
	433	goto ok;
015551fc JR	434	case IMM0_4:
015551fc JR	435	case IMM1_4:
252b5132 RH	436	imm = nibs[3];
252b5132 RH	437	goto ok;
015551fc JR	438	case IMM0_4BY2:
015551fc JR	439	case IMM1_4BY2:
69eb4bbf	440	imm = nibs[3] << 1;
252b5132	441	goto ok;
015551fc JR	442	case IMM0_4BY4:
015551fc JR	443	case IMM1_4BY4:
69eb4bbf	444	imm = nibs[3] << 2;
252b5132	445	goto ok;
015551fc JR	446	case IMM0_8:
015551fc JR	447	case IMM1_8:
252b5132 RH	448	imm = (nibs[2] << 4) \| nibs[3];
	449	goto ok;
	450	case PCRELIMM_8BY2:
69eb4bbf KH	451	imm = ((nibs[2] << 4) \| nibs[3]) << 1;
69eb4bbf KH	452	relmask = ~(bfd_vma) 1;
252b5132 RH	453	goto ok;
252b5132 RH	454	case PCRELIMM_8BY4:
69eb4bbf KH	455	imm = ((nibs[2] << 4) \| nibs[3]) << 2;
69eb4bbf KH	456	relmask = ~(bfd_vma) 3;
252b5132	457	goto ok;
015551fc JR	458	case IMM0_8BY2:
015551fc JR	459	case IMM1_8BY2:
69eb4bbf	460	imm = ((nibs[2] << 4) \| nibs[3]) << 1;
252b5132	461	goto ok;
015551fc JR	462	case IMM0_8BY4:
015551fc JR	463	case IMM1_8BY4:
69eb4bbf	464	imm = ((nibs[2] << 4) \| nibs[3]) << 2;
252b5132	465	goto ok;
252b5132 RH	466	case REG_N:
	467	rn = nibs[n];
	468	break;
	469	case REG_M:
	470	rm = nibs[n];
	471	break;
	472	case REG_NM:
	473	rn = (nibs[n] & 0xc) >> 2;
	474	rm = (nibs[n] & 0x3);
	475	break;
	476	case REG_B:
	477	rb = nibs[n] & 0x07;
69eb4bbf	478	break;
d4845d57 JR	479	case SDT_REG_N:
	480	/* sh-dsp: single data transfer. */
	481	rn = nibs[n];
	482	if ((rn & 0xc) != 4)
	483	goto fail;
	484	rn = rn & 0x3;
ddb68265	485	rn \|= (!(rn & 2)) << 2;
d4845d57 JR	486	break;
d4845d57 JR	487	case PPI:
015551fc	488	case REPEAT:
d4845d57	489	goto fail;
252b5132	490	default:
69eb4bbf	491	abort ();
252b5132 RH	492	}
	493	}
	494
	495	ok:
69eb4bbf	496	fprintf_fn (stream, "%s\t", op->name);
252b5132	497	disp_pc = 0;
69eb4bbf	498	for (n = 0; n < 3 && op->arg[n] != A_END; n++)
252b5132 RH	499	{
	500	if (n && op->arg[1] != A_END)
	501	fprintf_fn (stream, ",");
69eb4bbf	502	switch (op->arg[n])
252b5132 RH	503	{
252b5132 RH	504	case A_IMM:
69eb4bbf	505	fprintf_fn (stream, "#%d", (char) (imm));
252b5132 RH	506	break;
	507	case A_R0:
	508	fprintf_fn (stream, "r0");
	509	break;
	510	case A_REG_N:
	511	fprintf_fn (stream, "r%d", rn);
	512	break;
	513	case A_INC_N:
69eb4bbf	514	fprintf_fn (stream, "@r%d+", rn);
252b5132 RH	515	break;
252b5132 RH	516	case A_DEC_N:
69eb4bbf	517	fprintf_fn (stream, "@-r%d", rn);
252b5132 RH	518	break;
252b5132 RH	519	case A_IND_N:
69eb4bbf	520	fprintf_fn (stream, "@r%d", rn);
252b5132 RH	521	break;
252b5132 RH	522	case A_DISP_REG_N:
69eb4bbf	523	fprintf_fn (stream, "@(%d,r%d)", imm, rn);
252b5132	524	break;
d4845d57	525	case A_PMOD_N:
69eb4bbf	526	fprintf_fn (stream, "@r%d+r8", rn);
d4845d57	527	break;
252b5132 RH	528	case A_REG_M:
	529	fprintf_fn (stream, "r%d", rm);
	530	break;
	531	case A_INC_M:
69eb4bbf	532	fprintf_fn (stream, "@r%d+", rm);
252b5132 RH	533	break;
252b5132 RH	534	case A_DEC_M:
69eb4bbf	535	fprintf_fn (stream, "@-r%d", rm);
252b5132 RH	536	break;
252b5132 RH	537	case A_IND_M:
69eb4bbf	538	fprintf_fn (stream, "@r%d", rm);
252b5132 RH	539	break;
252b5132 RH	540	case A_DISP_REG_M:
69eb4bbf	541	fprintf_fn (stream, "@(%d,r%d)", imm, rm);
252b5132 RH	542	break;
	543	case A_REG_B:
	544	fprintf_fn (stream, "r%d_bank", rb);
	545	break;
	546	case A_DISP_PC:
	547	disp_pc = 1;
	548	disp_pc_addr = imm + 4 + (memaddr & relmask);
	549	(*info->print_address_func) (disp_pc_addr, info);
	550	break;
	551	case A_IND_R0_REG_N:
	552	fprintf_fn (stream, "@(r0,r%d)", rn);
69eb4bbf	553	break;
252b5132 RH	554	case A_IND_R0_REG_M:
252b5132 RH	555	fprintf_fn (stream, "@(r0,r%d)", rm);
69eb4bbf	556	break;
252b5132	557	case A_DISP_GBR:
69eb4bbf	558	fprintf_fn (stream, "@(%d,gbr)", imm);
252b5132 RH	559	break;
	560	case A_R0_GBR:
	561	fprintf_fn (stream, "@(r0,gbr)");
	562	break;
	563	case A_BDISP12:
	564	case A_BDISP8:
	565	(*info->print_address_func) (imm + memaddr, info);
	566	break;
	567	case A_SR:
	568	fprintf_fn (stream, "sr");
	569	break;
	570	case A_GBR:
	571	fprintf_fn (stream, "gbr");
	572	break;
	573	case A_VBR:
	574	fprintf_fn (stream, "vbr");
	575	break;
d4845d57 JR	576	case A_DSR:
	577	fprintf_fn (stream, "dsr");
	578	break;
	579	case A_MOD:
	580	fprintf_fn (stream, "mod");
	581	break;
	582	case A_RE:
	583	fprintf_fn (stream, "re");
	584	break;
	585	case A_RS:
	586	fprintf_fn (stream, "rs");
	587	break;
	588	case A_A0:
	589	fprintf_fn (stream, "a0");
	590	break;
	591	case A_X0:
	592	fprintf_fn (stream, "x0");
	593	break;
	594	case A_X1:
	595	fprintf_fn (stream, "x1");
	596	break;
	597	case A_Y0:
	598	fprintf_fn (stream, "y0");
	599	break;
	600	case A_Y1:
	601	fprintf_fn (stream, "y1");
	602	break;
	603	case DSP_REG_M:
	604	print_dsp_reg (rm, fprintf_fn, stream);
	605	break;
252b5132 RH	606	case A_SSR:
	607	fprintf_fn (stream, "ssr");
	608	break;
	609	case A_SPC:
	610	fprintf_fn (stream, "spc");
	611	break;
	612	case A_MACH:
	613	fprintf_fn (stream, "mach");
	614	break;
	615	case A_MACL:
69eb4bbf	616	fprintf_fn (stream, "macl");
252b5132 RH	617	break;
	618	case A_PR:
	619	fprintf_fn (stream, "pr");
	620	break;
	621	case A_SGR:
	622	fprintf_fn (stream, "sgr");
	623	break;
	624	case A_DBR:
	625	fprintf_fn (stream, "dbr");
	626	break;
252b5132 RH	627	case F_REG_N:
	628	fprintf_fn (stream, "fr%d", rn);
	629	break;
	630	case F_REG_M:
	631	fprintf_fn (stream, "fr%d", rm);
	632	break;
	633	case DX_REG_N:
	634	if (rn & 1)
	635	{
	636	fprintf_fn (stream, "xd%d", rn & ~1);
	637	break;
	638	}
252b5132 RH	639	case D_REG_N:
	640	fprintf_fn (stream, "dr%d", rn);
	641	break;
	642	case DX_REG_M:
	643	if (rm & 1)
	644	{
	645	fprintf_fn (stream, "xd%d", rm & ~1);
	646	break;
	647	}
	648	case D_REG_M:
	649	fprintf_fn (stream, "dr%d", rm);
	650	break;
	651	case FPSCR_M:
	652	case FPSCR_N:
	653	fprintf_fn (stream, "fpscr");
	654	break;
	655	case FPUL_M:
	656	case FPUL_N:
	657	fprintf_fn (stream, "fpul");
	658	break;
	659	case F_FR0:
	660	fprintf_fn (stream, "fr0");
	661	break;
	662	case V_REG_N:
69eb4bbf	663	fprintf_fn (stream, "fv%d", rn * 4);
252b5132 RH	664	break;
252b5132 RH	665	case V_REG_M:
69eb4bbf	666	fprintf_fn (stream, "fv%d", rm * 4);
252b5132 RH	667	break;
	668	case XMTRX_M4:
	669	fprintf_fn (stream, "xmtrx");
	670	break;
	671	default:
69eb4bbf	672	abort ();
252b5132 RH	673	}
	674	}
	675
	676	#if 0
	677	/* This code prints instructions in delay slots on the same line
	678	as the instruction which needs the delay slots. This can be
	679	confusing, since other disassembler don't work this way, and
	680	it means that the instructions are not all in a line. So I
	681	disabled it. Ian. */
	682	if (!(info->flags & 1)
	683	&& (op->name[0] == 'j'
	684	\|\| (op->name[0] == 'b'
69eb4bbf	685	&& (op->name[1] == 'r'
252b5132 RH	686	\|\| op->name[1] == 's'))
	687	\|\| (op->name[0] == 'r' && op->name[1] == 't')
	688	\|\| (op->name[0] == 'b' && op->name[2] == '.')))
	689	{
	690	info->flags \|= 1;
	691	fprintf_fn (stream, "\t(slot ");
1c509ca8	692	print_insn_sh (memaddr + 2, info);
252b5132 RH	693	info->flags &= ~1;
	694	fprintf_fn (stream, ")");
	695	return 4;
	696	}
	697	#endif
	698
	699	if (disp_pc && strcmp (op->name, "mova") != 0)
	700	{
	701	int size;
	702	bfd_byte bytes[4];
	703
69eb4bbf	704	if (relmask == ~(bfd_vma) 1)
252b5132 RH	705	size = 2;
	706	else
	707	size = 4;
	708	status = info->read_memory_func (disp_pc_addr, bytes, size, info);
	709	if (status == 0)
	710	{
	711	unsigned int val;
	712
	713	if (size == 2)
	714	{
1c509ca8	715	if (info->endian == BFD_ENDIAN_LITTLE)
252b5132 RH	716	val = bfd_getl16 (bytes);
	717	else
	718	val = bfd_getb16 (bytes);
	719	}
	720	else
	721	{
1c509ca8	722	if (info->endian == BFD_ENDIAN_LITTLE)
252b5132 RH	723	val = bfd_getl32 (bytes);
	724	else
	725	val = bfd_getb32 (bytes);
	726	}
	727	fprintf_fn (stream, "\t! 0x%x", val);
	728	}
	729	}
	730
	731	return 2;
	732	fail:
	733	;
	734
	735	}
	736	fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
	737	return 2;
	738	}