Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print SPARC instructions. |
060d22b0 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
df7b86aa | 3 | 2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2012 |
aa820537 | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
9b201bb5 NC |
6 | This file is part of the GNU opcodes library. |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
0f6ab988 | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. | |
252b5132 | 12 | |
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
252b5132 | 17 | |
0f6ab988 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
47b0e7ad NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "sysdep.h" |
df7b86aa | 24 | #include <stdio.h> |
252b5132 RH |
25 | #include "opcode/sparc.h" |
26 | #include "dis-asm.h" | |
27 | #include "libiberty.h" | |
28 | #include "opintl.h" | |
29 | ||
30 | /* Bitmask of v9 architectures. */ | |
31 | #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ | |
19f7b010 JJ |
32 | | (1 << SPARC_OPCODE_ARCH_V9A) \ |
33 | | (1 << SPARC_OPCODE_ARCH_V9B)) | |
252b5132 RH |
34 | /* 1 if INSN is for v9 only. */ |
35 | #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) | |
36 | /* 1 if INSN is for v9. */ | |
37 | #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) | |
38 | ||
39 | /* The sorted opcode table. */ | |
47b0e7ad | 40 | static const sparc_opcode **sorted_opcodes; |
252b5132 RH |
41 | |
42 | /* For faster lookup, after insns are sorted they are hashed. */ | |
43 | /* ??? I think there is room for even more improvement. */ | |
44 | ||
45 | #define HASH_SIZE 256 | |
46 | /* It is important that we only look at insn code bits as that is how the | |
47 | opcode table is hashed. OPCODE_BITS is a table of valid bits for each | |
48 | of the main types (0,1,2,3). */ | |
49 | static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; | |
50 | #define HASH_INSN(INSN) \ | |
51 | ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) | |
47b0e7ad | 52 | typedef struct sparc_opcode_hash |
0f6ab988 | 53 | { |
47b0e7ad NC |
54 | struct sparc_opcode_hash *next; |
55 | const sparc_opcode *opcode; | |
56 | } sparc_opcode_hash; | |
252b5132 | 57 | |
47b0e7ad | 58 | static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; |
252b5132 RH |
59 | |
60 | /* Sign-extend a value which is N bits long. */ | |
61 | #define SEX(value, bits) \ | |
62 | ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ | |
63 | >> ((8 * sizeof (int)) - bits) ) | |
64 | ||
65 | static char *reg_names[] = | |
47b0e7ad NC |
66 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
67 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
68 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
69 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
70 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
71 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
252b5132 RH |
72 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
73 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
47b0e7ad NC |
74 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
75 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", | |
252b5132 RH |
76 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
77 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", | |
78 | /* psr, wim, tbr, fpsr, cpsr are v8 only. */ | |
79 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" | |
80 | }; | |
81 | ||
82 | #define freg_names (®_names[4 * 8]) | |
83 | ||
84 | /* These are ordered according to there register number in | |
85 | rdpr and wrpr insns. */ | |
86 | static char *v9_priv_reg_names[] = | |
87 | { | |
88 | "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", | |
89 | "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", | |
ff3f9d5b | 90 | "wstate", "fq", "gl" |
252b5132 RH |
91 | /* "ver" - special cased */ |
92 | }; | |
93 | ||
ff3f9d5b DM |
94 | /* These are ordered according to there register number in |
95 | rdhpr and wrhpr insns. */ | |
96 | static char *v9_hpriv_reg_names[] = | |
97 | { | |
98 | "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver", | |
99 | "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", | |
100 | "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20", | |
101 | "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27", | |
102 | "resv28", "resv29", "resv30", "hstick_cmpr" | |
103 | }; | |
104 | ||
252b5132 RH |
105 | /* These are ordered according to there register number in |
106 | rd and wr insns (-16). */ | |
107 | static char *v9a_asr_reg_names[] = | |
108 | { | |
109 | "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", | |
2e52845b | 110 | "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr", |
58004e23 | 111 | "pause", "cps" |
252b5132 RH |
112 | }; |
113 | ||
114 | /* Macros used to extract instruction fields. Not all fields have | |
115 | macros defined here, only those which are actually used. */ | |
116 | ||
47b0e7ad NC |
117 | #define X_RD(i) (((i) >> 25) & 0x1f) |
118 | #define X_RS1(i) (((i) >> 14) & 0x1f) | |
119 | #define X_LDST_I(i) (((i) >> 13) & 1) | |
120 | #define X_ASI(i) (((i) >> 5) & 0xff) | |
121 | #define X_RS2(i) (((i) >> 0) & 0x1f) | |
ea783ef3 | 122 | #define X_RS3(i) (((i) >> 9) & 0x1f) |
47b0e7ad NC |
123 | #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) |
124 | #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) | |
125 | #define X_DISP22(i) (((i) >> 0) & 0x3fffff) | |
126 | #define X_IMM22(i) X_DISP22 (i) | |
127 | #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) | |
252b5132 RH |
128 | |
129 | /* These are for v9. */ | |
47b0e7ad | 130 | #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) |
2615994e | 131 | #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff)) |
47b0e7ad NC |
132 | #define X_DISP19(i) (((i) >> 0) & 0x7ffff) |
133 | #define X_MEMBAR(i) ((i) & 0x7f) | |
252b5132 RH |
134 | |
135 | /* Here is the union which was used to extract instruction fields | |
136 | before the shift and mask macros were written. | |
137 | ||
138 | union sparc_insn | |
139 | { | |
140 | unsigned long int code; | |
141 | struct | |
142 | { | |
143 | unsigned int anop:2; | |
144 | #define op ldst.anop | |
145 | unsigned int anrd:5; | |
146 | #define rd ldst.anrd | |
147 | unsigned int op3:6; | |
148 | unsigned int anrs1:5; | |
149 | #define rs1 ldst.anrs1 | |
150 | unsigned int i:1; | |
151 | unsigned int anasi:8; | |
152 | #define asi ldst.anasi | |
153 | unsigned int anrs2:5; | |
154 | #define rs2 ldst.anrs2 | |
155 | #define shcnt rs2 | |
156 | } ldst; | |
157 | struct | |
158 | { | |
159 | unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; | |
160 | unsigned int IMM13:13; | |
161 | #define imm13 IMM13.IMM13 | |
162 | } IMM13; | |
163 | struct | |
164 | { | |
165 | unsigned int anop:2; | |
166 | unsigned int a:1; | |
167 | unsigned int cond:4; | |
168 | unsigned int op2:3; | |
169 | unsigned int DISP22:22; | |
170 | #define disp22 branch.DISP22 | |
171 | #define imm22 disp22 | |
172 | } branch; | |
173 | struct | |
174 | { | |
175 | unsigned int anop:2; | |
176 | unsigned int a:1; | |
177 | unsigned int z:1; | |
178 | unsigned int rcond:3; | |
179 | unsigned int op2:3; | |
180 | unsigned int DISP16HI:2; | |
181 | unsigned int p:1; | |
182 | unsigned int _rs1:5; | |
183 | unsigned int DISP16LO:14; | |
184 | } branch16; | |
185 | struct | |
186 | { | |
187 | unsigned int anop:2; | |
188 | unsigned int adisp30:30; | |
189 | #define disp30 call.adisp30 | |
190 | } call; | |
47b0e7ad | 191 | }; */ |
252b5132 RH |
192 | |
193 | /* Nonzero if INSN is the opcode for a delayed branch. */ | |
47b0e7ad | 194 | |
252b5132 | 195 | static int |
47b0e7ad | 196 | is_delayed_branch (unsigned long insn) |
252b5132 | 197 | { |
47b0e7ad | 198 | sparc_opcode_hash *op; |
252b5132 RH |
199 | |
200 | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) | |
201 | { | |
47b0e7ad NC |
202 | const sparc_opcode *opcode = op->opcode; |
203 | ||
252b5132 RH |
204 | if ((opcode->match & insn) == opcode->match |
205 | && (opcode->lose & insn) == 0) | |
47b0e7ad | 206 | return opcode->flags & F_DELAYED; |
252b5132 RH |
207 | } |
208 | return 0; | |
209 | } | |
210 | ||
211 | /* extern void qsort (); */ | |
212 | ||
213 | /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value | |
214 | to compare_opcodes. */ | |
215 | static unsigned int current_arch_mask; | |
216 | ||
47b0e7ad NC |
217 | /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ |
218 | ||
219 | static int | |
220 | compute_arch_mask (unsigned long mach) | |
221 | { | |
222 | switch (mach) | |
223 | { | |
224 | case 0 : | |
225 | case bfd_mach_sparc : | |
d6787ef9 EB |
226 | return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) |
227 | | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)); | |
47b0e7ad NC |
228 | case bfd_mach_sparc_sparclet : |
229 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); | |
230 | case bfd_mach_sparc_sparclite : | |
231 | case bfd_mach_sparc_sparclite_le : | |
232 | /* sparclites insns are recognized by default (because that's how | |
233 | they've always been treated, for better or worse). Kludge this by | |
234 | indicating generic v8 is also selected. */ | |
235 | return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) | |
236 | | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); | |
237 | case bfd_mach_sparc_v8plus : | |
238 | case bfd_mach_sparc_v9 : | |
239 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
240 | case bfd_mach_sparc_v8plusa : | |
241 | case bfd_mach_sparc_v9a : | |
242 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); | |
243 | case bfd_mach_sparc_v8plusb : | |
244 | case bfd_mach_sparc_v9b : | |
245 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); | |
246 | } | |
247 | abort (); | |
248 | } | |
249 | ||
250 | /* Compare opcodes A and B. */ | |
251 | ||
252 | static int | |
253 | compare_opcodes (const void * a, const void * b) | |
254 | { | |
255 | sparc_opcode *op0 = * (sparc_opcode **) a; | |
256 | sparc_opcode *op1 = * (sparc_opcode **) b; | |
257 | unsigned long int match0 = op0->match, match1 = op1->match; | |
258 | unsigned long int lose0 = op0->lose, lose1 = op1->lose; | |
259 | register unsigned int i; | |
260 | ||
261 | /* If one (and only one) insn isn't supported by the current architecture, | |
262 | prefer the one that is. If neither are supported, but they're both for | |
263 | the same architecture, continue processing. Otherwise (both unsupported | |
264 | and for different architectures), prefer lower numbered arch's (fudged | |
265 | by comparing the bitmasks). */ | |
266 | if (op0->architecture & current_arch_mask) | |
267 | { | |
268 | if (! (op1->architecture & current_arch_mask)) | |
269 | return -1; | |
270 | } | |
271 | else | |
272 | { | |
273 | if (op1->architecture & current_arch_mask) | |
274 | return 1; | |
275 | else if (op0->architecture != op1->architecture) | |
276 | return op0->architecture - op1->architecture; | |
277 | } | |
278 | ||
279 | /* If a bit is set in both match and lose, there is something | |
280 | wrong with the opcode table. */ | |
281 | if (match0 & lose0) | |
282 | { | |
283 | fprintf | |
284 | (stderr, | |
285 | /* xgettext:c-format */ | |
286 | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), | |
287 | op0->name, match0, lose0); | |
288 | op0->lose &= ~op0->match; | |
289 | lose0 = op0->lose; | |
290 | } | |
291 | ||
292 | if (match1 & lose1) | |
293 | { | |
294 | fprintf | |
295 | (stderr, | |
296 | /* xgettext:c-format */ | |
297 | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), | |
298 | op1->name, match1, lose1); | |
299 | op1->lose &= ~op1->match; | |
300 | lose1 = op1->lose; | |
301 | } | |
302 | ||
303 | /* Because the bits that are variable in one opcode are constant in | |
304 | another, it is important to order the opcodes in the right order. */ | |
305 | for (i = 0; i < 32; ++i) | |
306 | { | |
307 | unsigned long int x = 1 << i; | |
308 | int x0 = (match0 & x) != 0; | |
309 | int x1 = (match1 & x) != 0; | |
310 | ||
311 | if (x0 != x1) | |
312 | return x1 - x0; | |
313 | } | |
314 | ||
315 | for (i = 0; i < 32; ++i) | |
316 | { | |
317 | unsigned long int x = 1 << i; | |
318 | int x0 = (lose0 & x) != 0; | |
319 | int x1 = (lose1 & x) != 0; | |
320 | ||
321 | if (x0 != x1) | |
322 | return x1 - x0; | |
323 | } | |
324 | ||
325 | /* They are functionally equal. So as long as the opcode table is | |
326 | valid, we can put whichever one first we want, on aesthetic grounds. */ | |
327 | ||
328 | /* Our first aesthetic ground is that aliases defer to real insns. */ | |
329 | { | |
330 | int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); | |
331 | ||
332 | if (alias_diff != 0) | |
333 | /* Put the one that isn't an alias first. */ | |
334 | return alias_diff; | |
335 | } | |
336 | ||
337 | /* Except for aliases, two "identical" instructions had | |
338 | better have the same opcode. This is a sanity check on the table. */ | |
339 | i = strcmp (op0->name, op1->name); | |
340 | if (i) | |
341 | { | |
0afd1215 DM |
342 | if (op0->flags & F_ALIAS) |
343 | { | |
344 | if (op0->flags & F_PREFERRED) | |
345 | return -1; | |
346 | if (op1->flags & F_PREFERRED) | |
347 | return 1; | |
348 | ||
349 | /* If they're both aliases, and neither is marked as preferred, | |
350 | be arbitrary. */ | |
351 | return i; | |
352 | } | |
47b0e7ad NC |
353 | else |
354 | fprintf (stderr, | |
355 | /* xgettext:c-format */ | |
356 | _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), | |
357 | op0->name, op1->name); | |
358 | } | |
359 | ||
360 | /* Fewer arguments are preferred. */ | |
361 | { | |
362 | int length_diff = strlen (op0->args) - strlen (op1->args); | |
363 | ||
364 | if (length_diff != 0) | |
365 | /* Put the one with fewer arguments first. */ | |
366 | return length_diff; | |
367 | } | |
368 | ||
369 | /* Put 1+i before i+1. */ | |
370 | { | |
371 | char *p0 = (char *) strchr (op0->args, '+'); | |
372 | char *p1 = (char *) strchr (op1->args, '+'); | |
373 | ||
374 | if (p0 && p1) | |
375 | { | |
376 | /* There is a plus in both operands. Note that a plus | |
377 | sign cannot be the first character in args, | |
378 | so the following [-1]'s are valid. */ | |
379 | if (p0[-1] == 'i' && p1[1] == 'i') | |
380 | /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ | |
381 | return 1; | |
382 | if (p0[1] == 'i' && p1[-1] == 'i') | |
383 | /* op0 is 1+i and op1 is i+1, so op0 goes first. */ | |
384 | return -1; | |
385 | } | |
386 | } | |
387 | ||
388 | /* Put 1,i before i,1. */ | |
389 | { | |
390 | int i0 = strncmp (op0->args, "i,1", 3) == 0; | |
391 | int i1 = strncmp (op1->args, "i,1", 3) == 0; | |
392 | ||
393 | if (i0 ^ i1) | |
394 | return i0 - i1; | |
395 | } | |
396 | ||
397 | /* They are, as far as we can tell, identical. | |
398 | Since qsort may have rearranged the table partially, there is | |
399 | no way to tell which one was first in the opcode table as | |
400 | written, so just say there are equal. */ | |
401 | /* ??? This is no longer true now that we sort a vector of pointers, | |
402 | not the table itself. */ | |
403 | return 0; | |
404 | } | |
405 | ||
406 | /* Build a hash table from the opcode table. | |
407 | OPCODE_TABLE is a sorted list of pointers into the opcode table. */ | |
408 | ||
409 | static void | |
410 | build_hash_table (const sparc_opcode **opcode_table, | |
411 | sparc_opcode_hash **hash_table, | |
412 | int num_opcodes) | |
413 | { | |
414 | int i; | |
415 | int hash_count[HASH_SIZE]; | |
416 | static sparc_opcode_hash *hash_buf = NULL; | |
417 | ||
418 | /* Start at the end of the table and work backwards so that each | |
419 | chain is sorted. */ | |
420 | ||
421 | memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); | |
422 | memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); | |
423 | if (hash_buf != NULL) | |
424 | free (hash_buf); | |
425 | hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes); | |
426 | for (i = num_opcodes - 1; i >= 0; --i) | |
427 | { | |
428 | int hash = HASH_INSN (opcode_table[i]->match); | |
429 | sparc_opcode_hash *h = &hash_buf[i]; | |
430 | ||
431 | h->next = hash_table[hash]; | |
432 | h->opcode = opcode_table[i]; | |
433 | hash_table[hash] = h; | |
434 | ++hash_count[hash]; | |
435 | } | |
436 | ||
437 | #if 0 /* for debugging */ | |
438 | { | |
439 | int min_count = num_opcodes, max_count = 0; | |
440 | int total; | |
441 | ||
442 | for (i = 0; i < HASH_SIZE; ++i) | |
443 | { | |
444 | if (hash_count[i] < min_count) | |
445 | min_count = hash_count[i]; | |
446 | if (hash_count[i] > max_count) | |
447 | max_count = hash_count[i]; | |
448 | total += hash_count[i]; | |
449 | } | |
450 | ||
451 | printf ("Opcode hash table stats: min %d, max %d, ave %f\n", | |
452 | min_count, max_count, (double) total / HASH_SIZE); | |
453 | } | |
454 | #endif | |
455 | } | |
456 | ||
252b5132 RH |
457 | /* Print one instruction from MEMADDR on INFO->STREAM. |
458 | ||
459 | We suffix the instruction with a comment that gives the absolute | |
460 | address involved, as well as its symbolic form, if the instruction | |
461 | is preceded by a findable `sethi' and it either adds an immediate | |
462 | displacement to that register, or it is an `add' or `or' instruction | |
463 | on that register. */ | |
464 | ||
465 | int | |
47b0e7ad | 466 | print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
252b5132 RH |
467 | { |
468 | FILE *stream = info->stream; | |
469 | bfd_byte buffer[4]; | |
470 | unsigned long insn; | |
47b0e7ad | 471 | sparc_opcode_hash *op; |
252b5132 RH |
472 | /* Nonzero of opcode table has been initialized. */ |
473 | static int opcodes_initialized = 0; | |
474 | /* bfd mach number of last call. */ | |
475 | static unsigned long current_mach = 0; | |
7bfeee7b | 476 | bfd_vma (*getword) (const void *); |
252b5132 RH |
477 | |
478 | if (!opcodes_initialized | |
479 | || info->mach != current_mach) | |
480 | { | |
481 | int i; | |
482 | ||
483 | current_arch_mask = compute_arch_mask (info->mach); | |
484 | ||
485 | if (!opcodes_initialized) | |
47b0e7ad NC |
486 | sorted_opcodes = |
487 | xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *)); | |
252b5132 RH |
488 | /* Reset the sorted table so we can resort it. */ |
489 | for (i = 0; i < sparc_num_opcodes; ++i) | |
490 | sorted_opcodes[i] = &sparc_opcodes[i]; | |
491 | qsort ((char *) sorted_opcodes, sparc_num_opcodes, | |
492 | sizeof (sorted_opcodes[0]), compare_opcodes); | |
493 | ||
494 | build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); | |
495 | current_mach = info->mach; | |
496 | opcodes_initialized = 1; | |
497 | } | |
498 | ||
499 | { | |
500 | int status = | |
501 | (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); | |
47b0e7ad | 502 | |
252b5132 RH |
503 | if (status != 0) |
504 | { | |
505 | (*info->memory_error_func) (status, memaddr, info); | |
506 | return -1; | |
507 | } | |
508 | } | |
509 | ||
510 | /* On SPARClite variants such as DANlite (sparc86x), instructions | |
0f6ab988 | 511 | are always big-endian even when the machine is in little-endian mode. */ |
252b5132 RH |
512 | if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) |
513 | getword = bfd_getb32; | |
514 | else | |
515 | getword = bfd_getl32; | |
516 | ||
517 | insn = getword (buffer); | |
518 | ||
0f6ab988 NC |
519 | info->insn_info_valid = 1; /* We do return this info. */ |
520 | info->insn_type = dis_nonbranch; /* Assume non branch insn. */ | |
521 | info->branch_delay_insns = 0; /* Assume no delay. */ | |
522 | info->target = 0; /* Assume no target known. */ | |
252b5132 RH |
523 | |
524 | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) | |
525 | { | |
47b0e7ad | 526 | const sparc_opcode *opcode = op->opcode; |
252b5132 RH |
527 | |
528 | /* If the insn isn't supported by the current architecture, skip it. */ | |
529 | if (! (opcode->architecture & current_arch_mask)) | |
530 | continue; | |
531 | ||
532 | if ((opcode->match & insn) == opcode->match | |
533 | && (opcode->lose & insn) == 0) | |
534 | { | |
535 | /* Nonzero means that we have found an instruction which has | |
536 | the effect of adding or or'ing the imm13 field to rs1. */ | |
537 | int imm_added_to_rs1 = 0; | |
9df31319 | 538 | int imm_ored_to_rs1 = 0; |
252b5132 RH |
539 | |
540 | /* Nonzero means that we have found a plus sign in the args | |
541 | field of the opcode table. */ | |
542 | int found_plus = 0; | |
47b0e7ad | 543 | |
252b5132 RH |
544 | /* Nonzero means we have an annulled branch. */ |
545 | int is_annulled = 0; | |
546 | ||
547 | /* Do we have an `add' or `or' instruction combining an | |
548 | immediate with rs1? */ | |
9df31319 RH |
549 | if (opcode->match == 0x80102000) /* or */ |
550 | imm_ored_to_rs1 = 1; | |
551 | if (opcode->match == 0x80002000) /* add */ | |
252b5132 RH |
552 | imm_added_to_rs1 = 1; |
553 | ||
554 | if (X_RS1 (insn) != X_RD (insn) | |
555 | && strchr (opcode->args, 'r') != 0) | |
556 | /* Can't do simple format if source and dest are different. */ | |
557 | continue; | |
558 | if (X_RS2 (insn) != X_RD (insn) | |
559 | && strchr (opcode->args, 'O') != 0) | |
560 | /* Can't do simple format if source and dest are different. */ | |
561 | continue; | |
562 | ||
d908c8af | 563 | (*info->fprintf_func) (stream, "%s", opcode->name); |
252b5132 RH |
564 | |
565 | { | |
47b0e7ad | 566 | const char *s; |
252b5132 RH |
567 | |
568 | if (opcode->args[0] != ',') | |
569 | (*info->fprintf_func) (stream, " "); | |
0f6ab988 | 570 | |
252b5132 RH |
571 | for (s = opcode->args; *s != '\0'; ++s) |
572 | { | |
573 | while (*s == ',') | |
574 | { | |
575 | (*info->fprintf_func) (stream, ","); | |
576 | ++s; | |
0f6ab988 NC |
577 | switch (*s) |
578 | { | |
579 | case 'a': | |
580 | (*info->fprintf_func) (stream, "a"); | |
581 | is_annulled = 1; | |
582 | ++s; | |
583 | continue; | |
584 | case 'N': | |
585 | (*info->fprintf_func) (stream, "pn"); | |
586 | ++s; | |
587 | continue; | |
588 | ||
589 | case 'T': | |
590 | (*info->fprintf_func) (stream, "pt"); | |
591 | ++s; | |
592 | continue; | |
593 | ||
594 | default: | |
595 | break; | |
596 | } | |
597 | } | |
252b5132 RH |
598 | |
599 | (*info->fprintf_func) (stream, " "); | |
47b0e7ad | 600 | |
252b5132 RH |
601 | switch (*s) |
602 | { | |
603 | case '+': | |
604 | found_plus = 1; | |
47b0e7ad | 605 | /* Fall through. */ |
252b5132 | 606 | |
252b5132 RH |
607 | default: |
608 | (*info->fprintf_func) (stream, "%c", *s); | |
609 | break; | |
610 | ||
611 | case '#': | |
612 | (*info->fprintf_func) (stream, "0"); | |
613 | break; | |
614 | ||
615 | #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) | |
616 | case '1': | |
617 | case 'r': | |
618 | reg (X_RS1 (insn)); | |
619 | break; | |
620 | ||
621 | case '2': | |
622 | case 'O': | |
623 | reg (X_RS2 (insn)); | |
624 | break; | |
625 | ||
626 | case 'd': | |
627 | reg (X_RD (insn)); | |
628 | break; | |
629 | #undef reg | |
630 | ||
631 | #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) | |
632 | #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) | |
633 | case 'e': | |
634 | freg (X_RS1 (insn)); | |
635 | break; | |
47b0e7ad NC |
636 | case 'v': /* Double/even. */ |
637 | case 'V': /* Quad/multiple of 4. */ | |
252b5132 RH |
638 | fregx (X_RS1 (insn)); |
639 | break; | |
640 | ||
641 | case 'f': | |
642 | freg (X_RS2 (insn)); | |
643 | break; | |
47b0e7ad NC |
644 | case 'B': /* Double/even. */ |
645 | case 'R': /* Quad/multiple of 4. */ | |
252b5132 RH |
646 | fregx (X_RS2 (insn)); |
647 | break; | |
648 | ||
ea783ef3 DM |
649 | case '4': |
650 | freg (X_RS3 (insn)); | |
651 | break; | |
652 | case '5': /* Double/even. */ | |
653 | fregx (X_RS3 (insn)); | |
654 | break; | |
655 | ||
252b5132 RH |
656 | case 'g': |
657 | freg (X_RD (insn)); | |
658 | break; | |
47b0e7ad NC |
659 | case 'H': /* Double/even. */ |
660 | case 'J': /* Quad/multiple of 4. */ | |
252b5132 RH |
661 | fregx (X_RD (insn)); |
662 | break; | |
663 | #undef freg | |
664 | #undef fregx | |
665 | ||
666 | #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) | |
667 | case 'b': | |
668 | creg (X_RS1 (insn)); | |
669 | break; | |
670 | ||
671 | case 'c': | |
672 | creg (X_RS2 (insn)); | |
673 | break; | |
674 | ||
675 | case 'D': | |
676 | creg (X_RD (insn)); | |
677 | break; | |
678 | #undef creg | |
679 | ||
680 | case 'h': | |
681 | (*info->fprintf_func) (stream, "%%hi(%#x)", | |
56930d37 | 682 | ((unsigned) 0xFFFFFFFF |
252b5132 RH |
683 | & ((int) X_IMM22 (insn) << 10))); |
684 | break; | |
685 | ||
47b0e7ad NC |
686 | case 'i': /* 13 bit immediate. */ |
687 | case 'I': /* 11 bit immediate. */ | |
688 | case 'j': /* 10 bit immediate. */ | |
252b5132 RH |
689 | { |
690 | int imm; | |
691 | ||
692 | if (*s == 'i') | |
693 | imm = X_SIMM (insn, 13); | |
694 | else if (*s == 'I') | |
695 | imm = X_SIMM (insn, 11); | |
696 | else | |
697 | imm = X_SIMM (insn, 10); | |
698 | ||
699 | /* Check to see whether we have a 1+i, and take | |
700 | note of that fact. | |
701 | ||
702 | Note: because of the way we sort the table, | |
703 | we will be matching 1+i rather than i+1, | |
704 | so it is OK to assume that i is after +, | |
705 | not before it. */ | |
706 | if (found_plus) | |
707 | imm_added_to_rs1 = 1; | |
47b0e7ad | 708 | |
252b5132 RH |
709 | if (imm <= 9) |
710 | (*info->fprintf_func) (stream, "%d", imm); | |
711 | else | |
712 | (*info->fprintf_func) (stream, "%#x", imm); | |
713 | } | |
714 | break; | |
715 | ||
6cda1326 | 716 | case ')': /* 5 bit unsigned immediate from RS3. */ |
d908c8af | 717 | (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn)); |
6cda1326 DM |
718 | break; |
719 | ||
47b0e7ad NC |
720 | case 'X': /* 5 bit unsigned immediate. */ |
721 | case 'Y': /* 6 bit unsigned immediate. */ | |
252b5132 RH |
722 | { |
723 | int imm = X_IMM (insn, *s == 'X' ? 5 : 6); | |
724 | ||
725 | if (imm <= 9) | |
726 | (info->fprintf_func) (stream, "%d", imm); | |
727 | else | |
728 | (info->fprintf_func) (stream, "%#x", (unsigned) imm); | |
729 | } | |
730 | break; | |
731 | ||
19f7b010 | 732 | case '3': |
0fd3a477 | 733 | (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); |
19f7b010 JJ |
734 | break; |
735 | ||
252b5132 RH |
736 | case 'K': |
737 | { | |
738 | int mask = X_MEMBAR (insn); | |
739 | int bit = 0x40, printed_one = 0; | |
740 | const char *name; | |
741 | ||
742 | if (mask == 0) | |
743 | (info->fprintf_func) (stream, "0"); | |
744 | else | |
745 | while (bit) | |
746 | { | |
747 | if (mask & bit) | |
748 | { | |
749 | if (printed_one) | |
750 | (info->fprintf_func) (stream, "|"); | |
751 | name = sparc_decode_membar (bit); | |
752 | (info->fprintf_func) (stream, "%s", name); | |
753 | printed_one = 1; | |
754 | } | |
755 | bit >>= 1; | |
756 | } | |
757 | break; | |
758 | } | |
759 | ||
2615994e DM |
760 | case '=': |
761 | info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4; | |
762 | (*info->print_address_func) (info->target, info); | |
763 | break; | |
764 | ||
252b5132 RH |
765 | case 'k': |
766 | info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; | |
767 | (*info->print_address_func) (info->target, info); | |
768 | break; | |
769 | ||
770 | case 'G': | |
771 | info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; | |
772 | (*info->print_address_func) (info->target, info); | |
773 | break; | |
774 | ||
775 | case '6': | |
776 | case '7': | |
777 | case '8': | |
778 | case '9': | |
779 | (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); | |
780 | break; | |
781 | ||
782 | case 'z': | |
783 | (*info->fprintf_func) (stream, "%%icc"); | |
784 | break; | |
785 | ||
786 | case 'Z': | |
787 | (*info->fprintf_func) (stream, "%%xcc"); | |
788 | break; | |
789 | ||
790 | case 'E': | |
791 | (*info->fprintf_func) (stream, "%%ccr"); | |
792 | break; | |
793 | ||
794 | case 's': | |
795 | (*info->fprintf_func) (stream, "%%fprs"); | |
796 | break; | |
797 | ||
798 | case 'o': | |
799 | (*info->fprintf_func) (stream, "%%asi"); | |
800 | break; | |
47b0e7ad | 801 | |
252b5132 RH |
802 | case 'W': |
803 | (*info->fprintf_func) (stream, "%%tick"); | |
804 | break; | |
805 | ||
806 | case 'P': | |
807 | (*info->fprintf_func) (stream, "%%pc"); | |
808 | break; | |
809 | ||
810 | case '?': | |
811 | if (X_RS1 (insn) == 31) | |
812 | (*info->fprintf_func) (stream, "%%ver"); | |
ff3f9d5b | 813 | else if ((unsigned) X_RS1 (insn) < 17) |
252b5132 RH |
814 | (*info->fprintf_func) (stream, "%%%s", |
815 | v9_priv_reg_names[X_RS1 (insn)]); | |
816 | else | |
817 | (*info->fprintf_func) (stream, "%%reserved"); | |
818 | break; | |
819 | ||
820 | case '!': | |
ff3f9d5b | 821 | if ((unsigned) X_RD (insn) < 17) |
252b5132 RH |
822 | (*info->fprintf_func) (stream, "%%%s", |
823 | v9_priv_reg_names[X_RD (insn)]); | |
824 | else | |
825 | (*info->fprintf_func) (stream, "%%reserved"); | |
826 | break; | |
827 | ||
ff3f9d5b DM |
828 | case '$': |
829 | if ((unsigned) X_RS1 (insn) < 32) | |
830 | (*info->fprintf_func) (stream, "%%%s", | |
831 | v9_hpriv_reg_names[X_RS1 (insn)]); | |
832 | else | |
833 | (*info->fprintf_func) (stream, "%%reserved"); | |
834 | break; | |
835 | ||
836 | case '%': | |
837 | if ((unsigned) X_RD (insn) < 32) | |
838 | (*info->fprintf_func) (stream, "%%%s", | |
839 | v9_hpriv_reg_names[X_RD (insn)]); | |
840 | else | |
841 | (*info->fprintf_func) (stream, "%%reserved"); | |
842 | break; | |
843 | ||
252b5132 | 844 | case '/': |
ea783ef3 | 845 | if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28) |
252b5132 RH |
846 | (*info->fprintf_func) (stream, "%%reserved"); |
847 | else | |
848 | (*info->fprintf_func) (stream, "%%%s", | |
849 | v9a_asr_reg_names[X_RS1 (insn)-16]); | |
850 | break; | |
851 | ||
852 | case '_': | |
ea783ef3 | 853 | if (X_RD (insn) < 16 || X_RD (insn) > 28) |
252b5132 RH |
854 | (*info->fprintf_func) (stream, "%%reserved"); |
855 | else | |
856 | (*info->fprintf_func) (stream, "%%%s", | |
857 | v9a_asr_reg_names[X_RD (insn)-16]); | |
858 | break; | |
859 | ||
860 | case '*': | |
861 | { | |
862 | const char *name = sparc_decode_prefetch (X_RD (insn)); | |
863 | ||
864 | if (name) | |
865 | (*info->fprintf_func) (stream, "%s", name); | |
866 | else | |
0fd3a477 | 867 | (*info->fprintf_func) (stream, "%ld", X_RD (insn)); |
252b5132 RH |
868 | break; |
869 | } | |
47b0e7ad | 870 | |
252b5132 | 871 | case 'M': |
0fd3a477 | 872 | (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); |
252b5132 | 873 | break; |
47b0e7ad | 874 | |
252b5132 | 875 | case 'm': |
0fd3a477 | 876 | (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); |
252b5132 | 877 | break; |
47b0e7ad | 878 | |
252b5132 RH |
879 | case 'L': |
880 | info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; | |
881 | (*info->print_address_func) (info->target, info); | |
882 | break; | |
883 | ||
884 | case 'n': | |
885 | (*info->fprintf_func) | |
886 | (stream, "%#x", SEX (X_DISP22 (insn), 22)); | |
887 | break; | |
888 | ||
889 | case 'l': | |
890 | info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; | |
891 | (*info->print_address_func) (info->target, info); | |
892 | break; | |
893 | ||
894 | case 'A': | |
895 | { | |
896 | const char *name = sparc_decode_asi (X_ASI (insn)); | |
897 | ||
898 | if (name) | |
899 | (*info->fprintf_func) (stream, "%s", name); | |
900 | else | |
0fd3a477 | 901 | (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); |
252b5132 RH |
902 | break; |
903 | } | |
904 | ||
905 | case 'C': | |
906 | (*info->fprintf_func) (stream, "%%csr"); | |
907 | break; | |
908 | ||
909 | case 'F': | |
910 | (*info->fprintf_func) (stream, "%%fsr"); | |
911 | break; | |
912 | ||
ea783ef3 DM |
913 | case '(': |
914 | (*info->fprintf_func) (stream, "%%efsr"); | |
915 | break; | |
916 | ||
252b5132 RH |
917 | case 'p': |
918 | (*info->fprintf_func) (stream, "%%psr"); | |
919 | break; | |
920 | ||
921 | case 'q': | |
922 | (*info->fprintf_func) (stream, "%%fq"); | |
923 | break; | |
924 | ||
925 | case 'Q': | |
926 | (*info->fprintf_func) (stream, "%%cq"); | |
927 | break; | |
928 | ||
929 | case 't': | |
930 | (*info->fprintf_func) (stream, "%%tbr"); | |
931 | break; | |
932 | ||
933 | case 'w': | |
934 | (*info->fprintf_func) (stream, "%%wim"); | |
935 | break; | |
936 | ||
937 | case 'x': | |
0fd3a477 | 938 | (*info->fprintf_func) (stream, "%ld", |
252b5132 RH |
939 | ((X_LDST_I (insn) << 8) |
940 | + X_ASI (insn))); | |
941 | break; | |
942 | ||
943 | case 'y': | |
944 | (*info->fprintf_func) (stream, "%%y"); | |
945 | break; | |
946 | ||
947 | case 'u': | |
948 | case 'U': | |
949 | { | |
950 | int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); | |
951 | const char *name = sparc_decode_sparclet_cpreg (val); | |
952 | ||
953 | if (name) | |
954 | (*info->fprintf_func) (stream, "%s", name); | |
955 | else | |
956 | (*info->fprintf_func) (stream, "%%cpreg(%d)", val); | |
957 | break; | |
958 | } | |
959 | } | |
960 | } | |
961 | } | |
962 | ||
963 | /* If we are adding or or'ing something to rs1, then | |
964 | check to see whether the previous instruction was | |
965 | a sethi to the same register as in the sethi. | |
966 | If so, attempt to print the result of the add or | |
967 | or (in this context add and or do the same thing) | |
968 | and its symbolic value. */ | |
9df31319 | 969 | if (imm_ored_to_rs1 || imm_added_to_rs1) |
252b5132 RH |
970 | { |
971 | unsigned long prev_insn; | |
972 | int errcode; | |
973 | ||
0f6ab988 NC |
974 | if (memaddr >= 4) |
975 | errcode = | |
976 | (*info->read_memory_func) | |
252b5132 | 977 | (memaddr - 4, buffer, sizeof (buffer), info); |
0f6ab988 NC |
978 | else |
979 | errcode = 1; | |
980 | ||
252b5132 RH |
981 | prev_insn = getword (buffer); |
982 | ||
983 | if (errcode == 0) | |
984 | { | |
985 | /* If it is a delayed branch, we need to look at the | |
986 | instruction before the delayed branch. This handles | |
0f6ab988 | 987 | sequences such as: |
252b5132 RH |
988 | |
989 | sethi %o1, %hi(_foo), %o1 | |
990 | call _printf | |
0f6ab988 | 991 | or %o1, %lo(_foo), %o1 */ |
252b5132 RH |
992 | |
993 | if (is_delayed_branch (prev_insn)) | |
994 | { | |
0f6ab988 NC |
995 | if (memaddr >= 8) |
996 | errcode = (*info->read_memory_func) | |
997 | (memaddr - 8, buffer, sizeof (buffer), info); | |
998 | else | |
999 | errcode = 1; | |
1000 | ||
252b5132 RH |
1001 | prev_insn = getword (buffer); |
1002 | } | |
1003 | } | |
1004 | ||
1005 | /* If there was a problem reading memory, then assume | |
1006 | the previous instruction was not sethi. */ | |
1007 | if (errcode == 0) | |
1008 | { | |
1009 | /* Is it sethi to the same register? */ | |
1010 | if ((prev_insn & 0xc1c00000) == 0x01000000 | |
1011 | && X_RD (prev_insn) == X_RS1 (insn)) | |
1012 | { | |
1013 | (*info->fprintf_func) (stream, "\t! "); | |
47b0e7ad | 1014 | info->target = |
56930d37 AO |
1015 | ((unsigned) 0xFFFFFFFF |
1016 | & ((int) X_IMM22 (prev_insn) << 10)); | |
9df31319 RH |
1017 | if (imm_added_to_rs1) |
1018 | info->target += X_SIMM (insn, 13); | |
1019 | else | |
1020 | info->target |= X_SIMM (insn, 13); | |
252b5132 RH |
1021 | (*info->print_address_func) (info->target, info); |
1022 | info->insn_type = dis_dref; | |
1023 | info->data_size = 4; /* FIXME!!! */ | |
1024 | } | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) | |
1029 | { | |
c7e2358a AM |
1030 | /* FIXME -- check is_annulled flag. */ |
1031 | (void) is_annulled; | |
252b5132 RH |
1032 | if (opcode->flags & F_UNBR) |
1033 | info->insn_type = dis_branch; | |
1034 | if (opcode->flags & F_CONDBR) | |
1035 | info->insn_type = dis_condbranch; | |
1036 | if (opcode->flags & F_JSR) | |
1037 | info->insn_type = dis_jsr; | |
1038 | if (opcode->flags & F_DELAYED) | |
1039 | info->branch_delay_insns = 1; | |
1040 | } | |
1041 | ||
1042 | return sizeof (buffer); | |
1043 | } | |
1044 | } | |
1045 | ||
0f6ab988 | 1046 | info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ |
252b5132 RH |
1047 | (*info->fprintf_func) (stream, _("unknown")); |
1048 | return sizeof (buffer); | |
1049 | } |