Commit | Line | Data |
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026df7c5 NC |
1 | /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils. |
2 | ||
3 | Copyright 2002 Free Software Foundation, Inc. | |
4 | ||
5 | Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <math.h> | |
22 | #include "libiberty.h" | |
23 | #include "dis-asm.h" | |
24 | #include "opcode/tic4x.h" | |
25 | ||
26 | #define C4X_DEBUG 0 | |
27 | ||
9c87d6c7 SS |
28 | #define C4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */ |
29 | #define C4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */ | |
026df7c5 NC |
30 | |
31 | typedef enum | |
32 | { | |
33 | IMMED_SINT, | |
34 | IMMED_SUINT, | |
35 | IMMED_SFLOAT, | |
36 | IMMED_INT, | |
37 | IMMED_UINT, | |
38 | IMMED_FLOAT | |
39 | } | |
40 | immed_t; | |
41 | ||
42 | typedef enum | |
43 | { | |
44 | INDIRECT_SHORT, | |
45 | INDIRECT_LONG, | |
46 | INDIRECT_C4X | |
47 | } | |
48 | indirect_t; | |
49 | ||
50 | static int c4x_version = 0; | |
51 | static int c4x_dp = 0; | |
52 | ||
4415b5c2 | 53 | static int c4x_pc_offset |
9c87d6c7 | 54 | PARAMS ((unsigned int)); |
4415b5c2 | 55 | static int c4x_print_char |
9c87d6c7 | 56 | PARAMS ((struct disassemble_info *, char)); |
4415b5c2 | 57 | static int c4x_print_str |
9c87d6c7 | 58 | PARAMS ((struct disassemble_info *, char *)); |
4415b5c2 | 59 | static int c4x_print_register |
9c87d6c7 | 60 | PARAMS ((struct disassemble_info *, unsigned long)); |
4415b5c2 | 61 | static int c4x_print_addr |
9c87d6c7 | 62 | PARAMS ((struct disassemble_info *, unsigned long)); |
4415b5c2 | 63 | static int c4x_print_relative |
9c87d6c7 | 64 | PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long)); |
4415b5c2 | 65 | void c4x_print_ftoa |
9c87d6c7 | 66 | PARAMS ((unsigned int, FILE *, fprintf_ftype)); |
4415b5c2 | 67 | static int c4x_print_direct |
9c87d6c7 | 68 | PARAMS ((struct disassemble_info *, unsigned long)); |
4415b5c2 | 69 | static int c4x_print_immed |
9c87d6c7 | 70 | PARAMS ((struct disassemble_info *, immed_t, unsigned long)); |
4415b5c2 | 71 | static int c4x_print_cond |
9c87d6c7 | 72 | PARAMS ((struct disassemble_info *, unsigned int)); |
4415b5c2 | 73 | static int c4x_print_indirect |
9c87d6c7 | 74 | PARAMS ((struct disassemble_info *, indirect_t, unsigned long)); |
4415b5c2 | 75 | static int c4x_print_op |
9c87d6c7 SS |
76 | PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long)); |
77 | static void c4x_hash_opcode_special | |
78 | PARAMS ((c4x_inst_t **, const c4x_inst_t *)); | |
4415b5c2 | 79 | static void c4x_hash_opcode |
9c87d6c7 | 80 | PARAMS ((c4x_inst_t **, c4x_inst_t **, const c4x_inst_t *, unsigned long)); |
4415b5c2 | 81 | static int c4x_disassemble |
9c87d6c7 | 82 | PARAMS ((unsigned long, unsigned long, struct disassemble_info *)); |
4415b5c2 | 83 | int print_insn_tic4x |
9c87d6c7 | 84 | PARAMS ((bfd_vma, struct disassemble_info *)); |
4415b5c2 AM |
85 | |
86 | ||
026df7c5 | 87 | static int |
4415b5c2 AM |
88 | c4x_pc_offset (op) |
89 | unsigned int op; | |
026df7c5 NC |
90 | { |
91 | /* Determine the PC offset for a C[34]x instruction. | |
92 | This could be simplified using some boolean algebra | |
93 | but at the expense of readability. */ | |
94 | switch (op >> 24) | |
95 | { | |
96 | case 0x60: /* br */ | |
97 | case 0x62: /* call (C4x) */ | |
98 | case 0x64: /* rptb (C4x) */ | |
99 | return 1; | |
100 | case 0x61: /* brd */ | |
101 | case 0x63: /* laj */ | |
102 | case 0x65: /* rptbd (C4x) */ | |
103 | return 3; | |
104 | case 0x66: /* swi */ | |
105 | case 0x67: | |
106 | return 0; | |
107 | default: | |
108 | break; | |
109 | } | |
110 | ||
111 | switch ((op & 0xffe00000) >> 20) | |
112 | { | |
113 | case 0x6a0: /* bB */ | |
114 | case 0x720: /* callB */ | |
115 | case 0x740: /* trapB */ | |
116 | return 1; | |
117 | ||
118 | case 0x6a2: /* bBd */ | |
119 | case 0x6a6: /* bBat */ | |
120 | case 0x6aa: /* bBaf */ | |
121 | case 0x722: /* lajB */ | |
122 | case 0x748: /* latB */ | |
123 | case 0x798: /* rptbd */ | |
124 | return 3; | |
125 | ||
126 | default: | |
127 | break; | |
128 | } | |
129 | ||
130 | switch ((op & 0xfe200000) >> 20) | |
131 | { | |
132 | case 0x6e0: /* dbB */ | |
133 | return 1; | |
134 | ||
135 | case 0x6e2: /* dbBd */ | |
136 | return 3; | |
137 | ||
138 | default: | |
139 | break; | |
140 | } | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
145 | static int | |
4415b5c2 AM |
146 | c4x_print_char (info, ch) |
147 | struct disassemble_info * info; | |
148 | char ch; | |
026df7c5 NC |
149 | { |
150 | if (info != NULL) | |
151 | (*info->fprintf_func) (info->stream, "%c", ch); | |
152 | return 1; | |
153 | } | |
154 | ||
155 | static int | |
4415b5c2 AM |
156 | c4x_print_str (info, str) |
157 | struct disassemble_info *info; | |
158 | char *str; | |
026df7c5 NC |
159 | { |
160 | if (info != NULL) | |
161 | (*info->fprintf_func) (info->stream, "%s", str); | |
162 | return 1; | |
163 | } | |
164 | ||
165 | static int | |
4415b5c2 AM |
166 | c4x_print_register (info, regno) |
167 | struct disassemble_info *info; | |
168 | unsigned long regno; | |
026df7c5 NC |
169 | { |
170 | static c4x_register_t **registertable = NULL; | |
171 | unsigned int i; | |
172 | ||
173 | if (registertable == NULL) | |
174 | { | |
175 | registertable = (c4x_register_t **) | |
176 | xmalloc (sizeof (c4x_register_t *) * REG_TABLE_SIZE); | |
177 | for (i = 0; i < c3x_num_registers; i++) | |
178 | registertable[c3x_registers[i].regno] = (void *)&c3x_registers[i]; | |
179 | if (IS_CPU_C4X (c4x_version)) | |
180 | { | |
181 | /* Add C4x additional registers, overwriting | |
182 | any C3x registers if necessary. */ | |
183 | for (i = 0; i < c4x_num_registers; i++) | |
184 | registertable[c4x_registers[i].regno] = (void *)&c4x_registers[i]; | |
185 | } | |
186 | } | |
187 | if ((int) regno > (IS_CPU_C4X (c4x_version) ? C4X_REG_MAX : C3X_REG_MAX)) | |
188 | return 0; | |
189 | if (info != NULL) | |
190 | (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name); | |
191 | return 1; | |
192 | } | |
193 | ||
194 | static int | |
4415b5c2 AM |
195 | c4x_print_addr (info, addr) |
196 | struct disassemble_info *info; | |
197 | unsigned long addr; | |
026df7c5 NC |
198 | { |
199 | if (info != NULL) | |
200 | (*info->print_address_func)(addr, info); | |
201 | return 1; | |
202 | } | |
203 | ||
204 | static int | |
4415b5c2 AM |
205 | c4x_print_relative (info, pc, offset, opcode) |
206 | struct disassemble_info *info; | |
207 | unsigned long pc; | |
208 | long offset; | |
209 | unsigned long opcode; | |
026df7c5 NC |
210 | { |
211 | return c4x_print_addr (info, pc + offset + c4x_pc_offset (opcode)); | |
212 | } | |
213 | ||
214 | static int | |
4415b5c2 AM |
215 | c4x_print_direct (info, arg) |
216 | struct disassemble_info *info; | |
217 | unsigned long arg; | |
026df7c5 NC |
218 | { |
219 | if (info != NULL) | |
220 | { | |
221 | (*info->fprintf_func) (info->stream, "@"); | |
222 | c4x_print_addr (info, arg + (c4x_dp << 16)); | |
223 | } | |
224 | return 1; | |
225 | } | |
226 | ||
227 | /* FIXME: make the floating point stuff not rely on host | |
228 | floating point arithmetic. */ | |
229 | void | |
4415b5c2 AM |
230 | c4x_print_ftoa (val, stream, pfunc) |
231 | unsigned int val; | |
232 | FILE *stream; | |
233 | fprintf_ftype pfunc; | |
026df7c5 NC |
234 | { |
235 | int e; | |
236 | int s; | |
237 | int f; | |
238 | double num = 0.0; | |
239 | ||
240 | e = EXTRS (val, 31, 24); /* exponent */ | |
241 | if (e != -128) | |
242 | { | |
243 | s = EXTRU (val, 23, 23); /* sign bit */ | |
244 | f = EXTRU (val, 22, 0); /* mantissa */ | |
245 | if (s) | |
246 | f += -2 * (1 << 23); | |
247 | else | |
248 | f += (1 << 23); | |
249 | num = f / (double)(1 << 23); | |
250 | num = ldexp (num, e); | |
251 | } | |
252 | (*pfunc)(stream, "%.9g", num); | |
253 | } | |
254 | ||
255 | static int | |
4415b5c2 AM |
256 | c4x_print_immed (info, type, arg) |
257 | struct disassemble_info *info; | |
258 | immed_t type; | |
259 | unsigned long arg; | |
026df7c5 NC |
260 | { |
261 | int s; | |
262 | int f; | |
263 | int e; | |
264 | double num = 0.0; | |
265 | ||
266 | if (info == NULL) | |
267 | return 1; | |
268 | switch (type) | |
269 | { | |
270 | case IMMED_SINT: | |
271 | case IMMED_INT: | |
272 | (*info->fprintf_func) (info->stream, "%d", (long)arg); | |
273 | break; | |
274 | ||
275 | case IMMED_SUINT: | |
276 | case IMMED_UINT: | |
277 | (*info->fprintf_func) (info->stream, "%u", arg); | |
278 | break; | |
279 | ||
280 | case IMMED_SFLOAT: | |
281 | e = EXTRS (arg, 15, 12); | |
282 | if (e != -8) | |
283 | { | |
284 | s = EXTRU (arg, 11, 11); | |
285 | f = EXTRU (arg, 10, 0); | |
286 | if (s) | |
287 | f += -2 * (1 << 11); | |
288 | else | |
289 | f += (1 << 11); | |
290 | num = f / (double)(1 << 11); | |
291 | num = ldexp (num, e); | |
292 | } | |
293 | (*info->fprintf_func) (info->stream, "%f", num); | |
294 | break; | |
295 | case IMMED_FLOAT: | |
296 | e = EXTRS (arg, 31, 24); | |
297 | if (e != -128) | |
298 | { | |
299 | s = EXTRU (arg, 23, 23); | |
300 | f = EXTRU (arg, 22, 0); | |
301 | if (s) | |
302 | f += -2 * (1 << 23); | |
303 | else | |
304 | f += (1 << 23); | |
305 | num = f / (double)(1 << 23); | |
306 | num = ldexp (num, e); | |
307 | } | |
308 | (*info->fprintf_func) (info->stream, "%f", num); | |
309 | break; | |
310 | } | |
311 | return 1; | |
312 | } | |
313 | ||
314 | static int | |
4415b5c2 AM |
315 | c4x_print_cond (info, cond) |
316 | struct disassemble_info *info; | |
317 | unsigned int cond; | |
026df7c5 NC |
318 | { |
319 | static c4x_cond_t **condtable = NULL; | |
320 | unsigned int i; | |
321 | ||
322 | if (condtable == NULL) | |
323 | { | |
324 | condtable = (c4x_cond_t **)xmalloc (sizeof (c4x_cond_t *) * 32); | |
325 | for (i = 0; i < num_conds; i++) | |
326 | condtable[c4x_conds[i].cond] = (void *)&c4x_conds[i]; | |
327 | } | |
328 | if (cond > 31 || condtable[cond] == NULL) | |
329 | return 0; | |
330 | if (info != NULL) | |
331 | (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name); | |
332 | return 1; | |
333 | } | |
334 | ||
335 | static int | |
4415b5c2 AM |
336 | c4x_print_indirect (info, type, arg) |
337 | struct disassemble_info *info; | |
338 | indirect_t type; | |
339 | unsigned long arg; | |
026df7c5 NC |
340 | { |
341 | unsigned int aregno; | |
342 | unsigned int modn; | |
343 | unsigned int disp; | |
344 | char *a; | |
345 | ||
346 | aregno = 0; | |
347 | modn = 0; | |
348 | disp = 1; | |
349 | switch(type) | |
350 | { | |
351 | case INDIRECT_C4X: /* *+ARn(disp) */ | |
352 | disp = EXTRU (arg, 7, 3); | |
353 | aregno = EXTRU (arg, 2, 0) + REG_AR0; | |
354 | modn = 0; | |
355 | break; | |
356 | case INDIRECT_SHORT: | |
357 | disp = 1; | |
358 | aregno = EXTRU (arg, 2, 0) + REG_AR0; | |
359 | modn = EXTRU (arg, 7, 3); | |
360 | break; | |
361 | case INDIRECT_LONG: | |
362 | disp = EXTRU (arg, 7, 0); | |
363 | aregno = EXTRU (arg, 10, 8) + REG_AR0; | |
364 | modn = EXTRU (arg, 15, 11); | |
365 | if (modn > 7 && disp != 0) | |
366 | return 0; | |
367 | break; | |
368 | default: | |
369 | abort (); | |
370 | } | |
371 | if (modn > C3X_MODN_MAX) | |
372 | return 0; | |
373 | a = c4x_indirects[modn].name; | |
374 | while (*a) | |
375 | { | |
376 | switch (*a) | |
377 | { | |
378 | case 'a': | |
379 | c4x_print_register (info, aregno); | |
380 | break; | |
381 | case 'd': | |
382 | c4x_print_immed (info, IMMED_UINT, disp); | |
383 | break; | |
384 | case 'y': | |
385 | c4x_print_str (info, "ir0"); | |
386 | break; | |
387 | case 'z': | |
388 | c4x_print_str (info, "ir1"); | |
389 | break; | |
390 | default: | |
391 | c4x_print_char (info, *a); | |
392 | break; | |
393 | } | |
394 | a++; | |
395 | } | |
396 | return 1; | |
397 | } | |
398 | ||
399 | static int | |
4415b5c2 AM |
400 | c4x_print_op (info, instruction, p, pc) |
401 | struct disassemble_info *info; | |
402 | unsigned long instruction; | |
403 | c4x_inst_t *p; | |
404 | unsigned long pc; | |
026df7c5 NC |
405 | { |
406 | int val; | |
407 | char *s; | |
408 | char *parallel = NULL; | |
409 | ||
410 | /* Print instruction name. */ | |
411 | s = p->name; | |
412 | while (*s && parallel == NULL) | |
413 | { | |
414 | switch (*s) | |
415 | { | |
416 | case 'B': | |
417 | if (! c4x_print_cond (info, EXTRU (instruction, 20, 16))) | |
418 | return 0; | |
419 | break; | |
420 | case 'C': | |
421 | if (! c4x_print_cond (info, EXTRU (instruction, 27, 23))) | |
422 | return 0; | |
423 | break; | |
424 | case '_': | |
425 | parallel = s + 1; /* Skip past `_' in name */ | |
426 | break; | |
427 | default: | |
428 | c4x_print_char (info, *s); | |
429 | break; | |
430 | } | |
431 | s++; | |
432 | } | |
433 | ||
434 | /* Print arguments. */ | |
435 | s = p->args; | |
436 | if (*s) | |
437 | c4x_print_char (info, ' '); | |
438 | ||
439 | while (*s) | |
440 | { | |
441 | switch (*s) | |
442 | { | |
443 | case '*': /* indirect 0--15 */ | |
444 | if (! c4x_print_indirect (info, INDIRECT_LONG, | |
445 | EXTRU (instruction, 15, 0))) | |
446 | return 0; | |
447 | break; | |
448 | ||
449 | case '#': /* only used for ldp, ldpk */ | |
450 | c4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); | |
451 | break; | |
452 | ||
453 | case '@': /* direct 0--15 */ | |
454 | c4x_print_direct (info, EXTRU (instruction, 15, 0)); | |
455 | break; | |
456 | ||
457 | case 'A': /* address register 24--22 */ | |
458 | if (! c4x_print_register (info, EXTRU (instruction, 24, 22) + | |
459 | REG_AR0)) | |
460 | return 0; | |
461 | break; | |
462 | ||
463 | case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb | |
464 | address 0--23. */ | |
465 | if (IS_CPU_C4X (c4x_version)) | |
466 | c4x_print_relative (info, pc, EXTRS (instruction, 23, 0), | |
467 | p->opcode); | |
468 | else | |
469 | c4x_print_addr (info, EXTRU (instruction, 23, 0)); | |
470 | break; | |
471 | ||
472 | case 'C': /* indirect (short C4x) 0--7 */ | |
473 | if (! IS_CPU_C4X (c4x_version)) | |
474 | return 0; | |
475 | if (! c4x_print_indirect (info, INDIRECT_C4X, | |
476 | EXTRU (instruction, 7, 0))) | |
477 | return 0; | |
478 | break; | |
479 | ||
480 | case 'D': | |
481 | /* Cockup if get here... */ | |
482 | break; | |
483 | ||
484 | case 'E': /* register 0--7 */ | |
44287f60 | 485 | case 'e': |
026df7c5 NC |
486 | if (! c4x_print_register (info, EXTRU (instruction, 7, 0))) |
487 | return 0; | |
488 | break; | |
489 | ||
490 | case 'F': /* 16-bit float immediate 0--15 */ | |
491 | c4x_print_immed (info, IMMED_SFLOAT, | |
492 | EXTRU (instruction, 15, 0)); | |
493 | break; | |
494 | ||
9c87d6c7 SS |
495 | case 'i': /* Extended indirect 0--7 */ |
496 | if ( EXTRU (instruction, 7, 5) == 7 ) | |
497 | { | |
498 | if( !c4x_print_register (info, EXTRU (instruction, 4, 0)) ) | |
499 | return 0; | |
500 | break; | |
501 | } | |
502 | /* Fallthrough */ | |
503 | ||
026df7c5 NC |
504 | case 'I': /* indirect (short) 0--7 */ |
505 | if (! c4x_print_indirect (info, INDIRECT_SHORT, | |
506 | EXTRU (instruction, 7, 0))) | |
507 | return 0; | |
508 | break; | |
509 | ||
9c87d6c7 SS |
510 | case 'j': /* Extended indirect 8--15 */ |
511 | if ( EXTRU (instruction, 15, 13) == 7 ) | |
512 | { | |
513 | if( !c4x_print_register (info, EXTRU (instruction, 12, 8)) ) | |
514 | return 0; | |
515 | break; | |
516 | } | |
517 | ||
026df7c5 NC |
518 | case 'J': /* indirect (short) 8--15 */ |
519 | if (! c4x_print_indirect (info, INDIRECT_SHORT, | |
520 | EXTRU (instruction, 15, 8))) | |
521 | return 0; | |
522 | break; | |
523 | ||
524 | case 'G': /* register 8--15 */ | |
44287f60 | 525 | case 'g': |
026df7c5 NC |
526 | if (! c4x_print_register (info, EXTRU (instruction, 15, 8))) |
527 | return 0; | |
528 | break; | |
529 | ||
530 | case 'H': /* register 16--18 */ | |
531 | if (! c4x_print_register (info, EXTRU (instruction, 18, 16))) | |
532 | return 0; | |
533 | break; | |
534 | ||
535 | case 'K': /* register 19--21 */ | |
536 | if (! c4x_print_register (info, EXTRU (instruction, 21, 19))) | |
537 | return 0; | |
538 | break; | |
539 | ||
540 | case 'L': /* register 22--24 */ | |
541 | if (! c4x_print_register (info, EXTRU (instruction, 24, 22))) | |
542 | return 0; | |
543 | break; | |
544 | ||
545 | case 'M': /* register 22--22 */ | |
546 | c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2); | |
547 | break; | |
548 | ||
549 | case 'N': /* register 23--23 */ | |
44287f60 | 550 | c4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0); |
026df7c5 NC |
551 | break; |
552 | ||
553 | case 'O': /* indirect (short C4x) 8--15 */ | |
554 | if (! IS_CPU_C4X (c4x_version)) | |
555 | return 0; | |
556 | if (! c4x_print_indirect (info, INDIRECT_C4X, | |
557 | EXTRU (instruction, 15, 8))) | |
558 | return 0; | |
559 | break; | |
560 | ||
561 | case 'P': /* displacement 0--15 (used by Bcond and BcondD) */ | |
562 | c4x_print_relative (info, pc, EXTRS (instruction, 15, 0), | |
563 | p->opcode); | |
564 | break; | |
565 | ||
566 | case 'Q': /* register 0--15 */ | |
44287f60 | 567 | case 'q': |
026df7c5 NC |
568 | if (! c4x_print_register (info, EXTRU (instruction, 15, 0))) |
569 | return 0; | |
570 | break; | |
571 | ||
572 | case 'R': /* register 16--20 */ | |
44287f60 | 573 | case 'r': |
026df7c5 NC |
574 | if (! c4x_print_register (info, EXTRU (instruction, 20, 16))) |
575 | return 0; | |
576 | break; | |
577 | ||
578 | case 'S': /* 16-bit signed immediate 0--15 */ | |
579 | c4x_print_immed (info, IMMED_SINT, | |
580 | EXTRS (instruction, 15, 0)); | |
581 | break; | |
582 | ||
583 | case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */ | |
584 | if (! IS_CPU_C4X (c4x_version)) | |
585 | return 0; | |
586 | if (! c4x_print_immed (info, IMMED_SUINT, | |
587 | EXTRU (instruction, 20, 16))) | |
588 | return 0; | |
589 | break; | |
590 | ||
591 | case 'U': /* 16-bit unsigned int immediate 0--15 */ | |
592 | c4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0)); | |
593 | break; | |
594 | ||
595 | case 'V': /* 5/9-bit unsigned vector 0--4/8 */ | |
596 | c4x_print_immed (info, IMMED_SUINT, | |
597 | IS_CPU_C4X (c4x_version) ? | |
598 | EXTRU (instruction, 8, 0) : | |
599 | EXTRU (instruction, 4, 0) & ~0x20); | |
600 | break; | |
601 | ||
602 | case 'W': /* 8-bit signed immediate 0--7 */ | |
603 | if (! IS_CPU_C4X (c4x_version)) | |
604 | return 0; | |
605 | c4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0)); | |
606 | break; | |
607 | ||
608 | case 'X': /* expansion register 4--0 */ | |
609 | val = EXTRU (instruction, 4, 0) + REG_IVTP; | |
610 | if (val < REG_IVTP || val > REG_TVTP) | |
611 | return 0; | |
612 | if (! c4x_print_register (info, val)) | |
613 | return 0; | |
614 | break; | |
615 | ||
616 | case 'Y': /* address register 16--20 */ | |
617 | val = EXTRU (instruction, 20, 16); | |
618 | if (val < REG_AR0 || val > REG_SP) | |
619 | return 0; | |
620 | if (! c4x_print_register (info, val)) | |
621 | return 0; | |
622 | break; | |
623 | ||
624 | case 'Z': /* expansion register 16--20 */ | |
625 | val = EXTRU (instruction, 20, 16) + REG_IVTP; | |
626 | if (val < REG_IVTP || val > REG_TVTP) | |
627 | return 0; | |
628 | if (! c4x_print_register (info, val)) | |
629 | return 0; | |
630 | break; | |
631 | ||
632 | case '|': /* Parallel instruction */ | |
633 | c4x_print_str (info, " || "); | |
634 | c4x_print_str (info, parallel); | |
635 | c4x_print_char (info, ' '); | |
636 | break; | |
637 | ||
638 | case ';': | |
639 | c4x_print_char (info, ','); | |
640 | break; | |
641 | ||
642 | default: | |
643 | c4x_print_char (info, *s); | |
644 | break; | |
645 | } | |
646 | s++; | |
647 | } | |
648 | return 1; | |
649 | } | |
650 | ||
651 | static void | |
9c87d6c7 SS |
652 | c4x_hash_opcode_special (optable_special, inst) |
653 | c4x_inst_t **optable_special; | |
654 | const c4x_inst_t *inst; | |
655 | { | |
656 | int i; | |
657 | ||
658 | for( i=0; i<C4X_SPESOP_SIZE; i++ ) | |
659 | if( optable_special[i] != NULL | |
660 | && optable_special[i]->opcode == inst->opcode ) | |
661 | { | |
662 | /* Collision (we have it already) - overwrite */ | |
663 | optable_special[i] = (void *)inst; | |
664 | return; | |
665 | } | |
666 | ||
667 | for( i=0; i<C4X_SPESOP_SIZE; i++ ) | |
668 | if( optable_special[i] == NULL ) | |
669 | { | |
670 | /* Add the new opcode */ | |
671 | optable_special[i] = (void *)inst; | |
672 | return; | |
673 | } | |
674 | ||
675 | /* This should never occur. This happens if the number of special | |
676 | instructions exceeds C4X_SPESOP_SIZE. Please increase the variable | |
677 | of this variable */ | |
678 | #if C4X_DEBUG | |
679 | printf("optable_special[] is full, please increase C4X_SPESOP_SIZE!\n"); | |
680 | #endif | |
681 | } | |
682 | ||
683 | static void | |
684 | c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel) | |
4415b5c2 | 685 | c4x_inst_t **optable; |
9c87d6c7 | 686 | c4x_inst_t **optable_special; |
4415b5c2 | 687 | const c4x_inst_t *inst; |
9c87d6c7 | 688 | const unsigned long c4x_oplevel; |
026df7c5 NC |
689 | { |
690 | int j; | |
691 | int opcode = inst->opcode >> (32 - C4X_HASH_SIZE); | |
692 | int opmask = inst->opmask >> (32 - C4X_HASH_SIZE); | |
693 | ||
694 | /* Use a C4X_HASH_SIZE bit index as a hash index. We should | |
695 | have unique entries so there's no point having a linked list | |
696 | for each entry? */ | |
697 | for (j = opcode; j < opmask; j++) | |
9c87d6c7 SS |
698 | if ( (j & opmask) == opcode |
699 | && inst->oplevel & c4x_oplevel ) | |
026df7c5 NC |
700 | { |
701 | #if C4X_DEBUG | |
702 | /* We should only have collisions for synonyms like | |
703 | ldp for ldi. */ | |
704 | if (optable[j] != NULL) | |
705 | printf("Collision at index %d, %s and %s\n", | |
706 | j, optable[j]->name, inst->name); | |
707 | #endif | |
9c87d6c7 SS |
708 | /* Catch those ops that collide with others already inside the |
709 | hash, and have a opmask greater than the one we use in the | |
710 | hash. Store them in a special-list, that will handle full | |
711 | 32-bit INSN, not only the first 11-bit (or so). */ | |
712 | if ( optable[j] != NULL | |
713 | && inst->opmask & ~(opmask << (32 - C4X_HASH_SIZE)) ) | |
714 | { | |
715 | /* Add the instruction already on the list */ | |
716 | c4x_hash_opcode_special(optable_special, optable[j]); | |
717 | ||
718 | /* Add the new instruction */ | |
719 | c4x_hash_opcode_special(optable_special, inst); | |
720 | } | |
721 | ||
722 | optable[j] = (void *)inst; | |
026df7c5 NC |
723 | } |
724 | } | |
725 | ||
726 | /* Disassemble the instruction in 'instruction'. | |
727 | 'pc' should be the address of this instruction, it will | |
728 | be used to print the target address if this is a relative jump or call | |
729 | the disassembled instruction is written to 'info'. | |
730 | The function returns the length of this instruction in words. */ | |
731 | ||
732 | static int | |
4415b5c2 AM |
733 | c4x_disassemble (pc, instruction, info) |
734 | unsigned long pc; | |
735 | unsigned long instruction; | |
736 | struct disassemble_info *info; | |
026df7c5 NC |
737 | { |
738 | static c4x_inst_t **optable = NULL; | |
9c87d6c7 | 739 | static c4x_inst_t **optable_special = NULL; |
026df7c5 NC |
740 | c4x_inst_t *p; |
741 | int i; | |
9c87d6c7 | 742 | unsigned long c4x_oplevel; |
026df7c5 NC |
743 | |
744 | c4x_version = info->mach; | |
9c87d6c7 SS |
745 | |
746 | c4x_oplevel = (IS_CPU_C4X (c4x_version)) ? OP_C4X : 0; | |
747 | c4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH; | |
026df7c5 NC |
748 | |
749 | if (optable == NULL) | |
750 | { | |
751 | optable = (c4x_inst_t **) | |
752 | xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE)); | |
9c87d6c7 SS |
753 | |
754 | optable_special = (c4x_inst_t **) | |
755 | xcalloc (sizeof (c4x_inst_t *), C4X_SPESOP_SIZE ); | |
756 | ||
026df7c5 NC |
757 | /* Install opcodes in reverse order so that preferred |
758 | forms overwrite synonyms. */ | |
9c87d6c7 SS |
759 | for (i = c4x_num_insts - 1; i >= 0; i--) |
760 | c4x_hash_opcode (optable, optable_special, &c4x_insts[i], c4x_oplevel); | |
761 | ||
762 | /* We now need to remove the insn that are special from the | |
763 | "normal" optable, to make the disasm search this extra list | |
764 | for them. | |
765 | */ | |
766 | for (i=0; i<C4X_SPESOP_SIZE; i++) | |
767 | if ( optable_special[i] != NULL ) | |
768 | optable[optable_special[i]->opcode >> (32 - C4X_HASH_SIZE)] = NULL; | |
026df7c5 NC |
769 | } |
770 | ||
771 | /* See if we can pick up any loading of the DP register... */ | |
772 | if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70) | |
773 | c4x_dp = EXTRU (instruction, 15, 0); | |
9c87d6c7 | 774 | |
026df7c5 | 775 | p = optable[instruction >> (32 - C4X_HASH_SIZE)]; |
9c87d6c7 SS |
776 | if ( p != NULL ) |
777 | { | |
778 | if ( ((instruction & p->opmask) == p->opcode) | |
779 | && c4x_print_op (NULL, instruction, p, pc) ) | |
780 | c4x_print_op (info, instruction, p, pc); | |
781 | else | |
782 | (*info->fprintf_func) (info->stream, "%08x", instruction); | |
783 | } | |
026df7c5 | 784 | else |
9c87d6c7 SS |
785 | { |
786 | for (i = 0; i<C4X_SPESOP_SIZE; i++) | |
787 | if (optable_special[i] != NULL | |
788 | && optable_special[i]->opcode == instruction ) | |
789 | { | |
790 | (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name); | |
791 | break; | |
792 | } | |
793 | if (i==C4X_SPESOP_SIZE) | |
794 | (*info->fprintf_func) (info->stream, "%08x", instruction); | |
795 | } | |
026df7c5 NC |
796 | |
797 | /* Return size of insn in words. */ | |
798 | return 1; | |
799 | } | |
800 | ||
801 | /* The entry point from objdump and gdb. */ | |
802 | int | |
803 | print_insn_tic4x (memaddr, info) | |
804 | bfd_vma memaddr; | |
805 | struct disassemble_info *info; | |
806 | { | |
807 | int status; | |
808 | unsigned long pc; | |
809 | unsigned long op; | |
810 | bfd_byte buffer[4]; | |
811 | ||
812 | status = (*info->read_memory_func) (memaddr, buffer, 4, info); | |
813 | if (status != 0) | |
814 | { | |
815 | (*info->memory_error_func) (status, memaddr, info); | |
816 | return -1; | |
817 | } | |
818 | ||
819 | pc = memaddr; | |
820 | op = bfd_getl32 (buffer); | |
821 | info->bytes_per_line = 4; | |
822 | info->bytes_per_chunk = 4; | |
823 | info->octets_per_byte = 4; | |
824 | info->display_endian = BFD_ENDIAN_LITTLE; | |
825 | return c4x_disassemble (pc, op, info) * 4; | |
826 | } |